mirror of https://github.com/OpenIPC/firmware.git
923 lines
23 KiB
Diff
923 lines
23 KiB
Diff
diff -drupN a/sound/soc/sunxi/sun50iw9-codec.h b/sound/soc/sunxi/sun50iw9-codec.h
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--- a/sound/soc/sunxi/sun50iw9-codec.h 1970-01-01 03:00:00.000000000 +0300
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+++ b/sound/soc/sunxi/sun50iw9-codec.h 2022-06-12 05:28:14.000000000 +0300
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@@ -0,0 +1,918 @@
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+/*
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+ * sound\soc\sunxi\sun50iw9-codec.h
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+ * (C) Copyright 2014-2018
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+ * allwinner Technology Co., Ltd. <www.allwinnertech.com>
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+ *
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+ * yumingfeng <yumingfeng@allwinnertech.com>
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+ *
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+ * some simple description for this code
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of
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+ * the License, or (at your option) any later version.
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+ *
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+ */
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+#ifndef _SUN50IW9_CODEC_H
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+#define _SUN50IW9_CODEC_H
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+
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+#define SUNXI_CODEC_CPUDAI_RX_CHANNELS_MAX 4
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+#define SUNXI_CODEC_CPUDAI_TX_CHANNELS_MAX 2
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+
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+#define SUNXI_DAC_DPC 0x00
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+#define SUNXI_DAC_FIFO_CTL 0x10
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+#define SUNXI_DAC_FIFO_STA 0x14
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+
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+/* left blank */
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+#define SUNXI_DAC_TXDATA 0X20
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+#define SUNXI_DAC_CNT 0x24
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+#define SUNXI_DAC_DG_REG 0x28
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+
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+#define SUNXI_ADC_FIFO_CTL 0x30
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+#define SUNXI_ADC_FIFO_STA 0x34
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+#define SUNXI_ADC_RXDATA 0x40
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+#define SUNXI_ADC_CNT 0x44
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+#define SUNXI_ADC_DG_REG 0x4C
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+
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+/*left blank */
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+#define SUNXI_DAC_DAP_CTL 0xf0
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+#define SUNXI_ADC_DAP_CTL 0xf8
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+
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+/* DAC */
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+#define AC_DAC_REG 0x310
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+#define AC_MIXER_REG 0x314
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+#define AC_RAMP_REG 0x31c
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+
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+/* SUNXI_DAC_DPC:0x00 */
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+#define EN_DA 31
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+#define MODQU 25
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+#define DWA_EN 24
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+#define HPF_EN 18
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+#define DVOL 12
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+#define DAC_HUB_EN 0
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+
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+/* SUNXI_DAC_FIFO_CTL:0x10 */
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+#define DAC_FS 29
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+#define FIR_VER 28
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+#define SEND_LASAT 26
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+#define DAC_FIFO_MODE 24
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+#define DAC_DRQ_CLR_CNT 21
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+#define TX_TRIG_LEVEL 8
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+#define DAC_MONO_EN 6
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+#define TX_SAMPLE_BITS 5
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+#define DAC_DRQ_EN 4
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+#define DAC_IRQ_EN 3
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+#define DAC_FIFO_UNDERRUN_IRQ_EN 2
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+#define DAC_FIFO_OVERRUN_IRQ_EN 1
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+#define DAC_FIFO_FLUSH 0
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+
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+/* SUNXI_DAC_FIFO_STA:0x14 */
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+#define DAC_TX_EMPTY 23
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+#define DAC_TXE_CNT 8
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+#define DAC_TXE_INT 3
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+#define DAC_TXU_INT 2
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+#define DAC_TXO_INT 1
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+
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+/* SUNXI_DAC_DG_REG:0x28 */
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+#define DAC_MODU_SELECT 11
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+#define DAC_PATTERN_SEL 9
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+#define CODEC_CLK_SEL 8
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+#define DA_SWP 6
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+#define ADDA_LOOP_MODE 0
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+
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+/* SUNXI_ADC_FIFO_CTL:0x30 */
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+#define ADC_FS 29
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+#define EN_AD 28
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+#define ADCFDT 26
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+#define ADCDFEN 25
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+#define RX_FIFO_MODE 24
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+#define RX_SAMPLE_BITS 16
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+#define ADCY_EN 15
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+#define ADCX_EN 14
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+#define ADCR_EN 13
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+#define ADCL_EN 12
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+#define ADC_CHAN_SEL 12
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+#define RX_FIFO_TRG_LEVEL 4
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+#define ADC_DRQ_EN 3
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+#define ADC_IRQ_EN 2
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+#define ADC_OVERRUN_IRQ_EN 1
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+#define ADC_FIFO_FLUSH 0
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+
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+/* SUNXI_ADC_FIFO_STA:0x38 */
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+#define ADC_RXA 23
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+#define ADC_RXA_CNT 8
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+#define ADC_RXA_INT 3
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+#define ADC_RXO_INT 1
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+
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+/* SUNXI_ADC_DG_REG:0x4c */
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+#define ADXY_SWP 25
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+#define ADLR_SWP 24
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+
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+/* SUNXI_DAC_DAP_CTL:0xf0 */
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+#define DDAP_EN 31
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+#define DDAP_DRC_EN 29
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+#define DDAP_HPF_EN 28
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+
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+/* SUNXI_ADC_DAP_CTR:0xf8 */
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+#define ADC_DAP0_EN 31
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+#define ADC_DRC0_EN 29
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+#define ADC_HPF0_EN 28
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+#define ADC_DAP1_EN 27
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+#define ADC_DRC1_EN 25
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+#define ADC_HPF1_EN 24
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+
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+#define AC_DAC_DRC_HHPFC (0x100)
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+#define AC_DAC_DRC_LHPFC (0x104)
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+#define AC_DAC_DRC_CTL (0x108)
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+#define AC_DAC_DRC_LPFHAT (0x10c)
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+#define AC_DAC_DRC_LPFLAT (0x110)
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+#define AC_DAC_DRC_RPFHAT (0x114)
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+#define AC_DAC_DRC_RPFLAT (0x118)
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+#define AC_DAC_DRC_LPFHRT (0x11c)
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+#define AC_DAC_DRC_LPFLRT (0x120)
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+#define AC_DAC_DRC_RPFHRT (0x124)
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+#define AC_DAC_DRC_RPFLRT (0x128)
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+#define AC_DAC_DRC_LRMSHAT (0x12c)
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+#define AC_DAC_DRC_LRMSLAT (0x130)
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+#define AC_DAC_DRC_RRMSHAT (0x134)
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+#define AC_DAC_DRC_RRMSLAT (0x138)
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+#define AC_DAC_DRC_HCT (0x13c)
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+#define AC_DAC_DRC_LCT (0x140)
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+#define AC_DAC_DRC_HKC (0x144)
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+#define AC_DAC_DRC_LKC (0x148)
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+#define AC_DAC_DRC_HOPC (0x14c)
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+#define AC_DAC_DRC_LOPC (0x150)
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+#define AC_DAC_DRC_HLT (0x154)
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+#define AC_DAC_DRC_LLT (0x158)
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+#define AC_DAC_DRC_HKI (0x15c)
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+#define AC_DAC_DRC_LKI (0x160)
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+#define AC_DAC_DRC_HOPL (0x164)
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+#define AC_DAC_DRC_LOPL (0x168)
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+#define AC_DAC_DRC_HET (0x16c)
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+#define AC_DAC_DRC_LET (0x170)
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+#define AC_DAC_DRC_HKE (0x174)
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+#define AC_DAC_DRC_LKE (0x178)
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+#define AC_DAC_DRC_HOPE (0x17c)
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+#define AC_DAC_DRC_LOPE (0x180)
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+#define AC_DAC_DRC_HKN (0x184)
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+#define AC_DAC_DRC_LKN (0x188)
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+#define AC_DAC_DRC_SFHAT (0x18c)
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+#define AC_DAC_DRC_SFLAT (0x190)
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+#define AC_DAC_DRC_SFHRT (0x194)
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+#define AC_DAC_DRC_SFLRT (0x198)
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+#define AC_DAC_DRC_MXGHS (0x19c)
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+#define AC_DAC_DRC_MXGLS (0x1a0)
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+#define AC_DAC_DRC_MNGHS (0x1a4)
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+#define AC_DAC_DRC_MNGLS (0x1a8)
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+#define AC_DAC_DRC_EPSHC (0x1ac)
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+#define AC_DAC_DRC_EPSLC (0x1b0)
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+#define AC_DAC_DRC_OPT (0x1b4)
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+#define AC_DAC_DRC_HPFHGAIN (0x1b8)
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+#define AC_DAC_DRC_HPFLGAIN (0x1bc)
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+
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+/*
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+ * DAC_DRC Control Register
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+ * AC_DAC_DRC_CTL:codecbase+0x108
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+ */
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+#define DAC_DRC_CTL_COMPLETE (15)
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+#define DAC_DRC_CTL_SIGNAL_DEL_TIMESET (8)
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+#define DAC_DRC_CTL_DELAY_USE_BUF (7)
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+#define DAC_DRC_CTL_GAIN_MAXLIM_EN (6)
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+#define DAC_DRC_CTL_GAIN_MINLIM_EN (5)
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+#define DAC_DRC_CTL_CONTROL_DRC_EN (4)
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+#define DAC_DRC_CTL_SIGNAL_FUN_SEL (3)
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+#define DAC_DRC_CTL_DEL_FUN_EN (2)
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+#define DAC_DRC_CTL_DRC_LT_EN (1)
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+#define DAC_DRC_CTL_DRC_ET_EN (0)
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+
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+/*
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+ * DAC_DRC Left Peak Filter High Attack Time Coef Register
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+ * AC_DAC_DRC_LPFHAT:codecbase+0x10c
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+ */
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+#define DAC_DRC_LPFHAT_ATT_TIME_PARA_SET (0)
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+
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+/*
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+ * DAC_DRC Left Peak Filter Low Attack Time Coef Register
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+ * AC_DAC_DRC_LPFLAT:codecbase+0x110
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+ */
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+#define DAC_DRC_LPFLAT_ATT_TIME_PARA_SET (0)
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+
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+/*
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+ * DAC_DRC Right Peak Filter High Attack Time Coef Register
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+ * AC_DAC_DRC_RPFHAT:codecbase+0x114
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+ */
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+#define DAC_DRC_RPFHAT_ATT_TIME_PARA_SET (0)
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+
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+/*
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+ * DAC_DRC Right Peak Filter Low Attack Time Coef Register
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+ * AC_DAC_DRC_RPFLAT:codecbase+0x118
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+ */
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+#define DAC_DRC_RPFLAT_ATT_TIME_PARA_SET (0)
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+
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+/*
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+ * DAC_DRC Left Peak Filter High Release Time Coef Register
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+ * AC_DAC_DRC_LPFHRT:codecbase+0x11c
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+ */
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+#define DAC_DRC_LPFHRT_REL_TIME_PARA_SET (0)
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+
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+/*
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+ * DAC_DRC Left Peak Filter Low Release Time Coef Register
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+ * AC_DAC_DRC_LPFLRT:codecbase+0x120
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+ */
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+#define DAC_DRC_LPFLRT_REL_TIME_PARA_SET (0)
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+
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+/*
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+ * DAC_DRC Right Peak Filter High Release Time Coef Register
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+ * AC_DAC_DRC_RPFHRT:codecbase+0x124
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+ */
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+#define DAC_DRC_RPFHRT_REL_TIME_PARA_SET (0)
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+
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+/*
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+ * DAC_DRC Left Peak Filter Low Release Time Coef Register
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+ * AC_DAC_DRC_RPFLRT:codecbase+0x128
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+ */
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+#define DAC_DRC_RPFLRT_REL_TIME_PARA_SET (0)
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+
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+/*
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+ * DAC_DRC Left RMS Filter High Coef Register
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+ * AC_DAC_DRC_LRMSHAT:codecbase+0x12c
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+ */
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+#define DAC_DRC_LRMSHAT_AVE_TIME_PARA_SET (0)
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+
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+/*
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+ * DAC_DRC Left RMS Filter Low Coef Register
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+ * AC_DAC_DRC_LRMSLAT:codecbase+0x130
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+ */
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+#define DAC_DRC_LRMSHAT_AVE_TIME_PARA_SET (0)
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+
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+/*
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+ * DAC_DRC Right RMS Filter High Coef Register
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+ * AC_DAC_DRC_RRMSHAT:codecbase+0x134
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+ */
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+#define DAC_DRC_RRMSHAT_AVE_TIME_PARA_SET (0)
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+
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+/*
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+ * DAC_DRC Right RMS Filter Low Coef Register
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+ * AC_DAC_DRC_RRMSLAT:codecbase+0x138
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+ */
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+#define DAC_DRC_RRMSLAT_AVE_TIME_PARA_SET (0)
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+
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+/*
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+ * DAC_DRC Compressor Theshold High Setting Register
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+ * AC_DAC_DRC_HCT:codecbase+0x13c
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+ */
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+#define DAC_DRC_HCT_COMP_THRES_SET (0)
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+
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+/*
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+ * DAC_DRC Compressor Theshold Low Setting Register
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+ * AC_DAC_DRC_LCT:codecbase+0x140
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+ */
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+#define DAC_DRC_LCT_COMP_THRES_SET (0)
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+
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+/*
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+ * DAC_DRC Compressor Slope High Setting Register
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+ * AC_DAC_DRC_HKC:codecbase+0x144
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+ */
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+#define DAC_DRC_HKC_SLOPE_SET (0)
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+
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+/*
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+ * DAC_DRC Compressor Slope Low Setting Register
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+ * AC_DAC_DRC_LKC:codecbase+0x148
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+ */
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+#define DAC_DRC_LKC_SLOPE_SET (0)
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+
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+/*
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+ * DAC_DRC Compressor High Output at Compressor Threshold Register
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+ * AC_DAC_DRC_HOPC:codecbase+0x14c
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+ */
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+#define DAC_DRC_HOPC_COMP_OUT (0)
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+
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+/*
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+ * DAC_DRC Compressor Low Output at Compressor Threshold Register
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+ * AC_DAC_DRC_LOPC:codecbase+0x150
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+ */
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+#define DAC_DRC_LOPC_COMP_OUT (0)
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+
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+/*
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+ * DAC_DRC Limiter Threshold High Setting Register
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+ * AC_DAC_DRC_HLT:codecbase+0x154
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+ */
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+#define DAC_DRC_HLT_LIM_THRES_SET (0)
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+
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+/*
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+ * DAC_DRC Limiter Threshold Low Setting Register
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+ * AC_DAC_DRC_LLT:codecbase+0x158
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+ */
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+#define DAC_DRC_LLT_LIM_THRES_SET (0)
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+
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+/*
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+ * DAC_DRC Limiter Slope High Setting Register
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+ * AC_DAC_DRC_HKI:codecbase+0x15c
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+ */
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+#define DAC_DRC_HKI_LIM_SLOPE_SET (0)
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+
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+/*
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+ * DAC_DRC Limiter Slope Low Setting Register
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+ * AC_DAC_DRC_LKI:codecbase+0x160
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+ */
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+#define DAC_DRC_LKI_LIM_SLOPE_SET (0)
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+
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+/*
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+ * DAC_DRC Limiter High Output at Limiter Threshold
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+ * AC_DAC_DRC_HOPL:codecbase+0x164
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+ */
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+#define DAC_DRC_HOPL_LIM_THRES_OUT (0)
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+
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+/*
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+ * DAC_DRC Limiter Low Output at Limiter Threshold
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+ * AC_DAC_DRC_LOPL:codecbase+0x168
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+ */
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+#define DAC_DRC_LOPL_LIM_THRES_OUT (0)
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+
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+/*
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+ * DAC_DRC Expander Theshold High Setting Register
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+ * AC_DAC_DRC_HET:codecbase+0x16c
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+ */
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+#define DAC_DRC_HET_EXPAN_THRES_SET (0)
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+
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+/*
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+ * DAC_DRC Expander Theshold Low Setting Register
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+ * AC_DAC_DRC_LET:codecbase+0x170
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+ */
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+#define DAC_DRC_LET_EXPAN_THRES_SET (0)
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+
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+/*
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+ * DAC_DRC Expander Slope High Setting Register
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+ * AC_DAC_DRC_HKE:codecbase+0x174
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+ */
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+#define DAC_DRC_HKE_EXPAN_SLOPE_SET (0)
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+
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+/*
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+ * DAC_DRC Expander Slope Low Setting Register
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+ * AC_DAC_DRC_LKE:codecbase+0x178
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+ */
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+#define DAC_DRC_LKE_EXPAN_SLOPE_SET (0)
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+
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+/*
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+ * DAC_DRC Expander High Output at Expander Threshold
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+ * AC_DAC_DRC_HOPE:codecbase+0x17c
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+ */
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+#define DAC_DRC_HOPE_EXPAN_DET_EQU (0)
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+
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+/*
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+ * DAC_DRC Expander Low Output at Expander Threshold
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+ * AC_DAC_DRC_LOPE:codecbase+0x180
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+ */
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+#define DAC_DRC_LOPE_EXPAN_DET_EQU (0)
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+
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+/*
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+ * DAC_DRC Linear Slope High Setting Register
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+ * AC_DAC_DRC_HKN:codecbase+0x184
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+ */
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+#define DAC_DRC_HKN_SLOPE_LIN_DET_EQU (0)
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+
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+/*
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+ * DAC_DRC Linear Slope Low Setting Register
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+ * AC_DAC_DRC_LKN:codecbase+0x188
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+ */
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+#define DAC_DRC_LKN_SLOPE_LIN_DET_EQU (0)
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+
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+/*
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+ * DAC_DRC Smooth filter Gain High Attack Time Coef Register
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+ * AC_DAC_DRC_SFHAT:codecbase+0x18c
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+ */
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+#define DAC_DRC_SFHAT_ATT_TIME_PARAM_SET (0)
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+
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+/*
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+ * DAC_DRC Smooth filter Gain Low Attack Time Coef Register
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+ * AC_DAC_DRC_SFLAT:codecbase+0x190
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+ */
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+#define DAC_DRC_SFLAT_ATT_TIME_PARAM_SET (0)
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+
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+/*
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+ * DAC_DRC Smooth filter Gain High Release Time Coef Register
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+ * AC_DAC_DRC_SFHRT:codecbase+0x194
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+ */
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+#define DAC_DRC_SFHRT_REL_TIME_PARAM_SET (0)
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+
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+/*
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+ * DAC_DRC Smooth filter Gain Low Release Time Coef Register
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+ * AC_DAC_DRC_SFLRT:codecbase+0x198
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+ */
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+#define DAC_DRC_SFLRT_REL_TIME_PARAM_SET (0)
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+
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+/*
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+ * DAC_DRC MAX Gain High Setting Register
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+ * AC_DAC_DRC_MXGHS:codecbase+0x19c
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+ */
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+#define DAC_DRC_MXGHS_GAIN_SET_DET_EUQ (0)
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+
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+/*
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+ * DAC_DRC MAX Gain Low Setting Register
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+ * AC_DAC_DRC_MXGLS:codecbase+0x1A0
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+ */
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+#define DAC_DRC_MXGLS_GAIN_SET_DET_EUQ (0)
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+
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+/*
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+ * DAC_DRC Min Gain High Setting Register
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+ * AC_DAC_DRC_MNGHS:codecbase+0x1A4
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+ */
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+#define DAC_DRC_MNGHS_GAIN_SET_DET_EUQ (0)
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+
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|
+/*
|
|
+ * DAC_DRC Min Gain Low Setting Register
|
|
+ * AC_DAC_DRC_MNGHS:codecbase+0x1A8
|
|
+ */
|
|
+#define DAC_DRC_MNGLS_GAIN_SET_DET_EUQ (0)
|
|
+
|
|
+/*
|
|
+ * DAC_DRC Expander Smooth Time High Coef Register
|
|
+ * AC_DAC_DRC_EPSHC:codecbase+0x1AC
|
|
+ */
|
|
+#define DAC_DRC_EPSHC_GAIN_FILT_REL_ATT_PARA (0)
|
|
+
|
|
+/*
|
|
+ * DAC_DRC Expander Smooth Time Low Coef Register
|
|
+ * AC_DAC_DRC_EPSLC:codecbase+0x1B0
|
|
+ */
|
|
+#define DAC_DRC_EPSLC_GAIN_FILT_REL_ATT_PARA (0)
|
|
+
|
|
+/*
|
|
+ * DAC_DRC Optimum Register
|
|
+ * AC_DAC_DRC_OPT:codecbase+0x1B4
|
|
+ */
|
|
+#define DAC_DRC_OPT_GS_EXP_COEFF_USE_SEL (10)
|
|
+#define DAC_DRC_OPT_GS_COEFF_MOD_SEL (9)
|
|
+#define DAC_DRC_OPT_MIN_ENERGY (8)
|
|
+#define DAC_DRC_OPT_RMS_DET_MOD (7)
|
|
+#define DAC_DRC_OPT_DATA_OUTPUT (6)
|
|
+#define DAC_DRC_OPT_GAIN_DEFAULT_VAL (5)
|
|
+#define DAC_DRC_OPT_HYS_GAIN_SMOOTH_DEL_TIME (0)
|
|
+
|
|
+/*
|
|
+ * DAC_DRC HPF Gain High Coef Register
|
|
+ * AC_DAC_DRC_HPFHGAIN:codecbase+0x1B8
|
|
+ */
|
|
+#define DAC_DRC_HPFHGAIN_GAIN_HPF_COEFF_SET (0)
|
|
+
|
|
+/*
|
|
+ * DAC_DRC HPF Gain Low Coef Register
|
|
+ * AC_DAC_DRC_HPFLGAIN:codecbase+0x1Bc
|
|
+ */
|
|
+#define DAC_DRC_HPFLGAIN_GAIN_HPF_COEFF_SET (0)
|
|
+
|
|
+
|
|
+/*
|
|
+ * ADC DRC
|
|
+ */
|
|
+#define AC_ADC_DRC_HHPFC (0x200)
|
|
+#define AC_ADC_DRC_LHPFC (0x204)
|
|
+#define AC_ADC_DRC_CTRL (0x208)
|
|
+#define AC_ADC_DRC_LPFHAT (0x20c)
|
|
+#define AC_ADC_DRC_LPFLAT (0x210)
|
|
+#define AC_ADC_DRC_RPFHAT (0x214)
|
|
+#define AC_ADC_DRC_RPFLAT (0x218)
|
|
+#define AC_ADC_DRC_LPFHRT (0x21c)
|
|
+#define AC_ADC_DRC_LPFLRT (0x220)
|
|
+#define AC_ADC_DRC_RPFHRT (0x224)
|
|
+#define AC_ADC_DRC_RPFLRT (0x228)
|
|
+#define AC_ADC_DRC_LRMSHAT (0x22c)
|
|
+#define AC_ADC_DRC_LRMSLAT (0x230)
|
|
+#define AC_ADC_DRC_RRMSHAT (0x234)
|
|
+#define AC_ADC_DRC_RRMSLAT (0x238)
|
|
+#define AC_ADC_DRC_HCT (0x23c)
|
|
+#define AC_ADC_DRC_LCT (0x240)
|
|
+#define AC_ADC_DRC_HKC (0x244)
|
|
+#define AC_ADC_DRC_LKC (0x248)
|
|
+#define AC_ADC_DRC_HOPC (0x24c)
|
|
+#define AC_ADC_DRC_LOPC (0x250)
|
|
+#define AC_ADC_DRC_HLT (0x254)
|
|
+#define AC_ADC_DRC_LLT (0x258)
|
|
+#define AC_ADC_DRC_HKI (0x25c)
|
|
+#define AC_ADC_DRC_LKI (0x260)
|
|
+#define AC_ADC_DRC_HOPL (0x264)
|
|
+#define AC_ADC_DRC_LOPL (0x268)
|
|
+#define AC_ADC_DRC_HET (0x26c)
|
|
+#define AC_ADC_DRC_LET (0x270)
|
|
+#define AC_ADC_DRC_HKE (0x274)
|
|
+#define AC_ADC_DRC_LKE (0x278)
|
|
+#define AC_ADC_DRC_HOPE (0x27c)
|
|
+#define AC_ADC_DRC_LOPE (0x280)
|
|
+#define AC_ADC_DRC_HKN (0x284)
|
|
+#define AC_ADC_DRC_LKN (0x288)
|
|
+#define AC_ADC_DRC_SFHAT (0x28c)
|
|
+#define AC_ADC_DRC_SFLAT (0x290)
|
|
+#define AC_ADC_DRC_SFHRT (0x294)
|
|
+#define AC_ADC_DRC_SFLRT (0x298)
|
|
+#define AC_ADC_DRC_MXGHS (0x29c)
|
|
+#define AC_ADC_DRC_MXGLS (0x2a0)
|
|
+#define AC_ADC_DRC_MNGHS (0x2a4)
|
|
+#define AC_ADC_DRC_MNGLS (0x2a8)
|
|
+#define AC_ADC_DRC_EPSHC (0x2ac)
|
|
+#define AC_ADC_DRC_EPSLC (0x2b0)
|
|
+#define AC_ADC_DRC_OPT (0x2b4)
|
|
+#define AC_ADC_DRC_HPFHGAIN (0x2b8)
|
|
+#define AC_ADC_DRC_HPFLGAIN (0x2bc)
|
|
+
|
|
+#define AC_VERSION (0x2c0)
|
|
+
|
|
+
|
|
+/*
|
|
+ * ADC_DRC High HPF Coef Register
|
|
+ * AC_ADC_DRC_HHPFC:codecbase+0x200
|
|
+ */
|
|
+#define ADC_DRC_HHPFC_COEF_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Low HPF Coef Register
|
|
+ * AC_ADC_DRC_LHPFC:codecbase+0x204
|
|
+ */
|
|
+#define ADC_DRC_LHPFC_COEF_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Control Register
|
|
+ * AC_ADC_DRC_CTRL:codecbase+0x208
|
|
+ */
|
|
+#define ADC_DRC_CTL_COMPLETE (15)
|
|
+#define ADC_DRC_CTL_SIGNAL_DEL_TIMESET (8)
|
|
+#define ADC_DRC_CTL_DELAY_USE_BUF (7)
|
|
+#define ADC_DRC_CTL_GAIN_MAXLIM_EN (6)
|
|
+#define ADC_DRC_CTL_GAIN_MINLIM_EN (5)
|
|
+#define ADC_DRC_CTL_CONTROL_DRC_EN (4)
|
|
+#define ADC_DRC_CTL_SIGNAL_FUN_SEL (3)
|
|
+#define ADC_DRC_CTL_DEL_FUN_EN (2)
|
|
+#define ADC_DRC_CTL_DRC_LT_EN (1)
|
|
+#define ADC_DRC_CTL_DRC_ET_EN (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Left Peak Filter High Attack Time Coef Register
|
|
+ * AC_ADC_DRC_LPFHAT:codecbase+0x20c
|
|
+ */
|
|
+#define ADC_DRC_LPFHAT_ATT_TIME_PARA_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Left Peak Filter Low Attack Time Coef Register
|
|
+ * AC_ADC_DRC_LPFLAT:codecbase+0x210
|
|
+ */
|
|
+#define ADC_DRC_LPFLAT_ATT_TIME_PARA_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Right Peak Filter High Attack Time Coef Register
|
|
+ * AC_ADC_DRC_RPFHAT:codecbase+0x214
|
|
+ */
|
|
+#define ADC_DRC_RPFHAT_ATT_TIME_PARA_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Right Peak Filter Low Attack Time Coef Register
|
|
+ * AC_ADC_DRC_RPFLAT:codecbase+0x218
|
|
+ */
|
|
+#define ADC_DRC_RPFLAT_ATT_TIME_PARA_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Left Peak Filter High Release Time Coef Register
|
|
+ * AC_ADC_DRC_LPFHRT:codecbase+0x21c
|
|
+ */
|
|
+#define DRC7_LPFHRT_REL_TIME_PARA_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Left Peak Filter Low Release Time Coef Register
|
|
+ * AC_ADC_DRC_LPFLRT:codecbase+0x220
|
|
+ */
|
|
+#define ADC_DRC_LPFLRT_REL_TIME_PARA_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Right Peak Filter High Release Time Coef Register
|
|
+ * AC_ADC_DRC_RPFHRT:codecbase+0x224
|
|
+ */
|
|
+#define ADC_DRC_RPFHRT_REL_TIME_PARA_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Left Peak Filter Low Release Time Coef Register
|
|
+ * AC_ADC_DRC_RPFLRT:codecbase+0x228
|
|
+ */
|
|
+#define ADC_DRC_RPFLRT_REL_TIME_PARA_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Left RMS Filter High Coef Register
|
|
+ * AC_ADC_DRC_LRMSHAT:codecbase+0x22c
|
|
+ */
|
|
+#define ADC_DRC_LRMSHAT_AVE_TIME_PARA_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Left RMS Filter Low Coef Register
|
|
+ * AC_ADC_DRC_LRMSLAT:codecbase+0x230
|
|
+ */
|
|
+#define ADC_DRC_LRMSHAT_AVE_TIME_PARA_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Right RMS Filter High Coef Register
|
|
+ * AC_ADC_DRC_RRMSHAT:codecbase+0x234
|
|
+ */
|
|
+#define ADC_DRC_RRMSHAT_AVE_TIME_PARA_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Right RMS Filter Low Coef Register
|
|
+ * AC_ADC_DRC_RRMSLAT:codecbase+0x238
|
|
+ */
|
|
+#define ADC_DRC_RRMSLAT_AVE_TIME_PARA_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Compressor Theshold High Setting Register
|
|
+ * AC_ADC_DRC_HCT:codecbase+0x23c
|
|
+ */
|
|
+#define ADC_DRC_HCT_COMP_THRES_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Compressor Theshold Low Setting Register
|
|
+ * AC_ADC_DRC_LCT:codecbase+0x240
|
|
+ */
|
|
+#define ADC_DRC_LCT_COMP_THRES_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Compressor Slope High Setting Register
|
|
+ * AC_ADC_DRC_HKC:codecbase+0x244
|
|
+ */
|
|
+#define ADC_DRC_HKC_SLOPE_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Compressor Slope Low Setting Register
|
|
+ * AC_ADC_DRC_LKC:codecbase+0x248
|
|
+ */
|
|
+#define ADC_DRC_LKC_SLOPE_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Compressor High Output at Compressor Threshold Register
|
|
+ * AC_ADC_DRC_HOPC:codecbase+0x24c
|
|
+ */
|
|
+#define ADC_DRC_HOPC_COMP_OUT (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Compressor Low Output at Compressor Threshold Register
|
|
+ * AC_ADC_DRC_LOPC:codecbase+0x250
|
|
+ */
|
|
+#define ADC_DRC_LOPC_COMP_OUT (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Limiter Threshold High Setting Register
|
|
+ * AC_ADC_DRC_HLT:codecbase+0x254
|
|
+ */
|
|
+#define ADC_DRC_HLT_LIM_THRES_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Limiter Threshold Low Setting Register
|
|
+ * AC_ADC_DRC_LLT:codecbase+0x258
|
|
+ */
|
|
+#define ADC_DRC_LLT_LIM_THRES_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Limiter Slope High Setting Register
|
|
+ * AC_ADC_DRC_HKI:codecbase+0x25c
|
|
+ */
|
|
+#define ADC_DRC_HKI_LIM_SLOPE_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Limiter Slope Low Setting Register
|
|
+ * AC_ADC_DRC_LKI:codecbase+0x260
|
|
+ */
|
|
+#define ADC_DRC_LKI_LIM_SLOPE_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Limiter High Output at Limiter Threshold
|
|
+ * AC_ADC_DRC_HOPL:codecbase+0x264
|
|
+ */
|
|
+#define ADC_DRC_HOPL_LIM_THRES_OUT (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Limiter Low Output at Limiter Threshold
|
|
+ * AC_ADC_DRC_LOPL:codecbase+0x268
|
|
+ */
|
|
+#define ADC_DRC_LOPL_LIM_THRES_OUT (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Expander Theshold High Setting Register
|
|
+ * AC_ADC_DRC_HET:codecbase+0x26c
|
|
+ */
|
|
+#define ADC_DRC_HET_EXPAN_THRES_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Expander Theshold Low Setting Register
|
|
+ * AC_ADC_DRC_LET:codecbase+0x270
|
|
+ */
|
|
+#define ADC_DRC_LET_EXPAN_THRES_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Expander Slope High Setting Register
|
|
+ * AC_ADC_DRC_HKE:codecbase+0x274
|
|
+ */
|
|
+#define ADC_DRC_HKE_EXPAN_SLOPE_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Expander Slope Low Setting Register
|
|
+ * AC_ADC_DRC_LKE:codecbase+0x278
|
|
+ */
|
|
+#define ADC_DRC_LKE_EXPAN_SLOPE_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Expander High Output at Expander Threshold
|
|
+ * AC_ADC_DRC_HOPE:codecbase+0x27c
|
|
+ */
|
|
+#define ADC_DRC_HOPE_EXPAN_DET_EQU (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Expander Low Output at Expander Threshold
|
|
+ * AC_ADC_DRC_LOPE:codecbase+0x280
|
|
+ */
|
|
+#define ADC_DRC_LOPE_EXPAN_DET_EQU (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Linear Slope High Setting Register
|
|
+ * AC_ADC_DRC_HKN:codecbase+0x284
|
|
+ */
|
|
+#define ADC_DRC_HKN_SLOPE_LIN_DET_EQU (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Linear Slope Low Setting Register
|
|
+ * AC_ADC_DRC_LKN:codecbase+0x288
|
|
+ */
|
|
+#define ADC_DRC_LKN_SLOPE_LIN_DET_EQU (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Smooth filter Gain High Attack Time Coef Register
|
|
+ * AC_ADC_DRC_SFHAT:codecbase+0x28c
|
|
+ */
|
|
+#define ADC_DRC_SFHAT_ATT_TIME_PARAM_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Smooth filter Gain Low Attack Time Coef Register
|
|
+ * AC_ADC_DRC_SFLAT:codecbase+0x290
|
|
+ */
|
|
+#define ADC_DRC_SFLAT_ATT_TIME_PARAM_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Smooth filter Gain High Release Time Coef Register
|
|
+ * AC_ADC_DRC_SFHRT:codecbase+0x294
|
|
+ */
|
|
+#define ADC_DRC_SFHRT_REL_TIME_PARAM_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Smooth filter Gain Low Release Time Coef Register
|
|
+ * AC_ADC_DRC_SFLRT:codecbase+0x298
|
|
+ */
|
|
+#define ADC_DRC_SFLRT_REL_TIME_PARAM_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC MAX Gain High Setting Register
|
|
+ * AC_ADC_DRC_MXGHS:codecbase+0x29c
|
|
+ */
|
|
+#define ADC_DRC_MXGHS_GAIN_SET_DET_EUQ (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC MAX Gain Low Setting Register
|
|
+ * AC_ADC_DRC_MXGLS:codecbase+0x2A0
|
|
+ */
|
|
+#define ADC_DRC_MXGLS_GAIN_SET_DET_EUQ (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Min Gain High Setting Register
|
|
+ * AC_ADC_DRC_MNGHS:codecbase+0x2A4
|
|
+ */
|
|
+#define ADC_DRC_MNGHS_GAIN_SET_DET_EUQ (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Min Gain Low Setting Register
|
|
+ * AC_ADC_DRC_MNGHS:codecbase+0x2A8
|
|
+ */
|
|
+#define ADC_DRC_MNGLS_GAIN_SET_DET_EUQ (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Expander Smooth Time High Coef Register
|
|
+ * AC_ADC_DRC_EPSHC:codecbase+0x2AC
|
|
+ */
|
|
+#define ADC_DRC_EPSHC_GAIN_FILT_REL_ATT_PARA (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Expander Smooth Time Low Coef Register
|
|
+ * AC_ADC_DRC_EPSLC:codecbase+0x2B0
|
|
+ */
|
|
+#define ADC_DRC_EPSLC_GAIN_FILT_REL_ATT_PARA (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC Optimum Register
|
|
+ * AC_ADC_DRC_OPT:codecbase+0x2B4
|
|
+ */
|
|
+#define ADC_DRC_OPT_GS_EXP_COEFF_USE_SEL (10)
|
|
+#define ADC_DRC_OPT_GS_COEFF_MOD_SEL (9)
|
|
+#define ADC_DRC_OPT_MIN_ENERGY (8)
|
|
+#define ADC_DRC_OPT_RMS_DET_MOD (7)
|
|
+#define ADC_DRC_OPT_DATA_OUTPUT (6)
|
|
+#define ADC_DRC_OPT_GAIN_DEFAULT_VAL (5)
|
|
+#define ADC_DRC_OPT_HYS_GAIN_SMOOTH_DEL_TIME (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC HPF Gain High Coef Register
|
|
+ * AC_ADC_DRC_HPFHGAIN:codecbase+0x2B8
|
|
+ */
|
|
+#define ADC_DRC_HPFHGAIN_GAIN_HPF_COEFF_SET (0)
|
|
+
|
|
+/*
|
|
+ * ADC_DRC HPF Gain Low Coef Register
|
|
+ * AC_ADC_DRC_HPFLGAIN:codecbase+0x2Bc
|
|
+ */
|
|
+#define ADC_DRC_HPFLGAIN_GAIN_HPF_COEFF_SET (0)
|
|
+
|
|
+
|
|
+/* DAC */
|
|
+/* AC_DAC_REG */
|
|
+#define CURRENT_TEST_SEL 23
|
|
+#define IOPVRS 20
|
|
+#define ILINEOUTAMPS 18
|
|
+#define IOPDACS 16
|
|
+#define DACLEN 15
|
|
+#define DACREN 14
|
|
+#define LINEOUTL_EN 13
|
|
+#define LINEOUTR_EN 11
|
|
+#define RSWITCH 9
|
|
+#define RAMPEN 8
|
|
+#define LINEOUTL_SEL 6
|
|
+#define LINEOUTR_SEL 5
|
|
+#define LINEOUT_VOL 0
|
|
+
|
|
+/* AC_MIXER_REG */
|
|
+#define LMIX_LINEINL 23
|
|
+#define LMIX_FMINL 22
|
|
+#define LMIX_LDAC 21
|
|
+#define LMIX_RDAC 20
|
|
+#define LMIXMUTE 20
|
|
+#define RMIX_LINEINR 19
|
|
+#define RMIX_FMINR 18
|
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+#define RMIX_RDAC 17
|
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+#define RMIX_LDAC 16
|
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+#define RMIXMUTE 16
|
|
+#define LMIXEN 11
|
|
+#define RMIXEN 10
|
|
+#define IOPMIXS 8
|
|
+#define LINEING 4
|
|
+#define FMING 0
|
|
+
|
|
+/* AC_RAMP_REG */
|
|
+#define RAMP_STEP 4
|
|
+#define RMDEN 3
|
|
+#define RMUEN 2
|
|
+#define RMCEN 1
|
|
+#define RDEN 0
|
|
+
|
|
+#define LABEL(constant) {#constant, constant, 0}
|
|
+#define LABEL_END {NULL, 0, -1}
|
|
+
|
|
+struct audiocodec_reg_label {
|
|
+ const char *name;
|
|
+ const unsigned int address;
|
|
+ int value;
|
|
+};
|
|
+
|
|
+struct spk_config {
|
|
+ bool used;
|
|
+ bool pa_ctl_level;
|
|
+ u32 gpio;
|
|
+ u32 pa_msleep_time;
|
|
+};
|
|
+
|
|
+struct gain_config {
|
|
+ u32 lineout_vol;
|
|
+ u32 linein_gain;
|
|
+ u32 fmin_gain;
|
|
+ u32 digital_vol;
|
|
+};
|
|
+
|
|
+struct codec_hw_config {
|
|
+ u8 adcdrc_cfg;
|
|
+ u8 dacdrc_cfg;
|
|
+ u8 adchpf_cfg;
|
|
+ u8 dachpf_cfg;
|
|
+};
|
|
+
|
|
+struct voltage_supply {
|
|
+ struct regulator *cpvdd;
|
|
+ struct regulator *avcc;
|
|
+};
|
|
+
|
|
+struct sunxi_codec_info {
|
|
+ struct device *dev;
|
|
+ struct regmap *regmap;
|
|
+ void __iomem *digitbase;
|
|
+ struct clk *pllclk;
|
|
+ struct clk *moduleclk;
|
|
+ /* self user config params */
|
|
+ struct spk_config spk_cfg;
|
|
+ struct gain_config gain_cfg;
|
|
+ struct voltage_supply vol_supply;
|
|
+ struct codec_hw_config hw_cfg;
|
|
+
|
|
+ u32 dac_en;
|
|
+ u32 adc_en;
|
|
+ u32 dacdap_en;
|
|
+ u32 adcdap_en;
|
|
+};
|
|
+
|
|
+
|
|
+#endif /* __SUN50IW9_CODEC_H */
|