mirror of https://github.com/OpenIPC/firmware.git
138 lines
3.4 KiB
Diff
138 lines
3.4 KiB
Diff
diff -drupN a/include/linux/mfd/acx00-mfd.h b/include/linux/mfd/acx00-mfd.h
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--- a/include/linux/mfd/acx00-mfd.h 1970-01-01 03:00:00.000000000 +0300
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+++ b/include/linux/mfd/acx00-mfd.h 2022-06-12 05:28:14.000000000 +0300
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@@ -0,0 +1,133 @@
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+/*
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+ * include/linux/mfd/acx00/core.h -- Core interface for ACX00
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+ *
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+ * Copyright 2009 Wolfson Microelectronics PLC.
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+ *
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+ * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ *
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+ */
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+
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+#ifndef __MFD_ACX00_CORE_H__
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+#define __MFD_ACX00_CORE_H__
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+
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+#include <linux/mutex.h>
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+#include <linux/interrupt.h>
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+
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+/* GPIOs in the chip are numbered from 1-11 */
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+#define ACX00_IRQ_GPIO(x) (x + ACX00_IRQ_TEMP_WARN)
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+
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+#define SYS_VERSION 0x0000
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+#define SYS_CONTROL 0x0002
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+#define SYS_IRQ_ENABLE 0x0004
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+#define SYS_IRQ_STATUS 0x0006
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+/*#define SYS_CLK_CTL 0x0008*/
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+#define SYS_DLDO_OSC_CTL 0x000a
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+#define SYS_PLL_CTL0 0x000c
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+#define SYS_PLL_CTL1 0x000e
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+#define SYS_AUDIO_CTL0 0x0010
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+#define SYS_AUDIO_CTL1 0x0012
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+#define SYS_EPHY_CTL0 0x0014
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+#define SYS_EPHY_CTL1 0x0016
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+#define SYS_TVE_CTL0 0x0018
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+#define SYS_TVE_CTL1 0x001a
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+
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+/*SYS_VERSION:0x0000*/
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+#define CHIP_PACKAGE 14
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+#define CHIP_VERSION 0
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+
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+/*SYS_CONTROL:0x0002*/
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+#define CIHP_RESET 0
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+
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+/*SYS_IRQ_ENABLE:0x0004*/
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+#define INTB_OUTPUT_ENABLE 15
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+#define INTB_OUTPUT_CFG 14
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+#define RTC_IRQ_ENABLE 12
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+#define EPHY_IRQ_ENABLE 8
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+#define TVE_IRQ_ENABLE 4
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+
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+/*SYS_IRQ_STATUS:0x0006*/
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+#define RTC_IRQ_STATUS 12
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+#define EPHY_IRQ_STATUS 8
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+#define TVE_IRQ_STATUS 4
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+
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+/*SYS_CLK_CTL:0x0008*/
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+#define EFUSE_CLK_SEL 5
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+#define SYS_CLK_SEL 4
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+#define CKI_24M_ENABLE 2
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+#define CKO_RTC_ENABLE 1
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+#define CKO_32K_ENABLE 0
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+
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+/*SYS_DLDO_OSC_CTL:0x000a*/
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+#define DLDOEN 15
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+#define DLDOVOL 12
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+#define ENBG 11
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+#define RESBYPS 10
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+#define OSCEN 3
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+#define OSCSEL 0
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+
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+/*SYS_PLL_CTL0:0x000c*/
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+#define PLL_ENABLE 15
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+#define PLL_BIAS_EN 14
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+#define PLL_LDO1_EN 11
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+#define PLL_LDO_EN 10
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+#define PLL_POST_DIV 9
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+#define PLL_PRE_DIV_M 0
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+
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+/*SYS_PLL_CTL1:0x000e*/
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+#define PLL_CS 10
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+#define PLL_VCO_S 5
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+#define PLL_CP_S 0
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+
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+/*SYS_AUDIO_CTL0:0x0010*/
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+#define AC_MCLK_GATING 1
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+#define AC_RESET_INVALID 0
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+
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+/*SYS_AUDIO_CTL1:0x0012*/
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+#define AC_I2S_IO_EN 0
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+
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+/*SYS_EPHY_CTL0:0x0014*/
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+#define EPHY_SYSCLK_GATING 1
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+#define EPHY_RESET_INVALID 0
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+
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+/*SYS_EPHY_CTL1:0x0016*/
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+#define EPHY_MII_IO_FOR_I2S 15
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+#define EPHY_MII_IO_FOR_PLL 14
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+#define E_DPX_LED_IO_EN 3
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+#define E_SPD_LED_IO_EN 2
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+#define E_LNK_LED_IO_EN 1
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+#define EPHY_MII_IO_EN 0
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+
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+/*SYS_TVE_CTL0:0x0018*/
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+#define TVE_SYSCLK_GATING 3
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+#define TVE_SCLK_GATING 2
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+#define TVE_DCLK_GATING 1
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+#define TVE_RESET_INVALID 0
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+
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+/*SYS_TVE_CTL1:0x001a*/
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+#define TVE_CCIR_CLK_IO_EN 1
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+#define TVE_CCIR_SYNC_DATA_IO_EN 0
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+
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+struct acx00 {
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+ struct mutex lock;
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+
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+ struct device *dev;
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+ struct regmap *regmap;
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+ struct pwm_device *pwm_ac200;
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+ struct work_struct init_work;
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+ int irq;
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+};
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+
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+/* Device I/O API */
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+int acx00_reg_read(struct acx00 *acx00, unsigned short reg);
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+int acx00_reg_write(struct acx00 *acx00, unsigned short reg,
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+ unsigned short val);
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+int acx00_enable(void);
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+int acx00_set_bits(struct acx00 *acx00, unsigned short reg,
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+ unsigned short mask, unsigned short val);
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+
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+#endif
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