mirror of https://github.com/OpenIPC/firmware.git
285 lines
9.4 KiB
Diff
285 lines
9.4 KiB
Diff
diff -drupN a/drivers/tty/serial/sunxi-uart.h b/drivers/tty/serial/sunxi-uart.h
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--- a/drivers/tty/serial/sunxi-uart.h 1970-01-01 03:00:00.000000000 +0300
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+++ b/drivers/tty/serial/sunxi-uart.h 2022-06-12 05:28:14.000000000 +0300
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@@ -0,0 +1,280 @@
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+/*
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+ * drivers/tty/serial/sunxi-uart.h
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+ * (C) Copyright 2007-2013
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+ * Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com>
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+ * Aaron.Maoye <leafy.myeh@reuuimllatech.com>
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+ *
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+ * Some macro and struct of Allwinner UART controller.
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of
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+ * the License, or (at your option) any later version.
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+ *
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+ * 2013.6.6 Mintow <duanmintao@allwinnertech.com>
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+ * Adapt to support sun8i/sun9i of Allwinner.
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+ */
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+
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+#ifndef _SUNXI_UART_H_
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+#define _SUNXI_UART_H_
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+
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+#include <linux/regulator/consumer.h>
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+#include <linux/dmaengine.h>
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+
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+struct sw_uart_pdata {
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+ unsigned int used;
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+ unsigned int io_num;
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+ unsigned int port_no;
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+ char regulator_id[16];
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+ struct regulator *regulator;
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+};
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+
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+#ifdef CONFIG_SERIAL_SUNXI_DMA
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+struct sw_uart_dma {
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+ u32 use_dma; /* 1:used */
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+
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+ /* receive and transfer buffer */
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+ char *rx_buffer; /* visual memory */
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+ char *tx_buffer;
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+ dma_addr_t rx_phy_addr; /* physical memory */
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+ dma_addr_t tx_phy_addr;
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+ u32 rb_size; /* buffer size */
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+ u32 tb_size;
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+
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+ /* regard the rx buffer as a circular buffer */
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+ u32 rb_head;
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+ u32 rb_tail;
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+ u32 rx_size;
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+
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+ dma_cookie_t rx_cookie;
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+
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+ char tx_dma_inited; /* 1:dma tx channel has been init */
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+ char rx_dma_inited; /* 1:dma rx channel has been init */
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+ char tx_dma_used; /* 1:dma tx is working */
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+ char rx_dma_used; /* 1:dma rx is working */
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+
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+ /* timer to poll activity on rx dma */
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+ char use_timer;
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+ int rx_timeout;
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+
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+ struct dma_chan *dma_chan_rx, *dma_chan_tx;
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+ struct scatterlist rx_sgl, tx_sgl;
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+ unsigned int rx_bytes, tx_bytes;
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+};
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+#endif
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+
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+struct sw_uart_port {
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+ struct uart_port port;
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+ char name[16];
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+ struct clk *mclk;
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+ struct clk *sclk;
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+ struct clk *pclk;
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+ unsigned char id;
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+ unsigned char ier;
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+ unsigned char lcr;
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+ unsigned char mcr;
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+ unsigned char fcr;
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+ unsigned char dll;
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+ unsigned char dlh;
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+ unsigned char rs485;
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+ unsigned char msr_saved_flags;
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+ unsigned int lsr_break_flag;
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+ struct sw_uart_pdata *pdata;
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+#ifdef CONFIG_SERIAL_SUNXI_DMA
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+ struct sw_uart_dma *dma;
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+ struct hrtimer rx_hrtimer;
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+ u32 rx_last_pos;
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+#define SUNXI_UART_DRQ_RX(ch) (DRQSRC_UART0_RX + ch)
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+#define SUNXI_UART_DRQ_TX(ch) (DRQDST_UART0_TX + ch)
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+#endif
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+
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+ /* for debug */
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+#define MAX_DUMP_SIZE 1024
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+ unsigned int dump_len;
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+ char *dump_buff;
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+ struct proc_dir_entry *proc_root;
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+ struct proc_dir_entry *proc_info;
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+
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+ struct pinctrl *pctrl;
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+ struct serial_rs485 rs485conf;
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+ bool card_print;
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+ bool throttled;
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+};
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+
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+/* register offset define */
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+#define SUNXI_UART_RBR (0x00) /* receive buffer register */
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+#define SUNXI_UART_THR (0x00) /* transmit holding register */
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+#define SUNXI_UART_DLL (0x00) /* divisor latch low register */
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+#define SUNXI_UART_DLH (0x04) /* diviso latch high register */
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+#define SUNXI_UART_IER (0x04) /* interrupt enable register */
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+#define SUNXI_UART_IIR (0x08) /* interrupt identity register */
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+#define SUNXI_UART_FCR (0x08) /* FIFO control register */
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+#define SUNXI_UART_LCR (0x0c) /* line control register */
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+#define SUNXI_UART_MCR (0x10) /* modem control register */
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+#define SUNXI_UART_LSR (0x14) /* line status register */
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+#define SUNXI_UART_MSR (0x18) /* modem status register */
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+#define SUNXI_UART_SCH (0x1c) /* scratch register */
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+#define SUNXI_UART_USR (0x7c) /* status register */
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+#define SUNXI_UART_TFL (0x80) /* transmit FIFO level */
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+#define SUNXI_UART_RFL (0x84) /* RFL */
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+#define SUNXI_UART_HALT (0xa4) /* halt tx register */
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+#define SUNXI_UART_RS485 (0xc0) /* RS485 control and status register */
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+
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+/* register bit field define */
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+/* Interrupt Enable Register */
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+#define SUNXI_UART_IER_PTIME (BIT(7))
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+#define SUNXI_UART_IER_RS485 (BIT(4))
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+#define SUNXI_UART_IER_MSI (BIT(3))
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+#define SUNXI_UART_IER_RLSI (BIT(2))
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+#define SUNXI_UART_IER_THRI (BIT(1))
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+#define SUNXI_UART_IER_RDI (BIT(0))
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+/* Interrupt ID Register */
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+#define SUNXI_UART_IIR_FEFLAG_MASK (BIT(6)|BIT(7))
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+#define SUNXI_UART_IIR_IID_MASK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
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+ #define SUNXI_UART_IIR_IID_MSTA (0)
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+ #define SUNXI_UART_IIR_IID_NOIRQ (1)
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+ #define SUNXI_UART_IIR_IID_THREMP (2)
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+ #define SUNXI_UART_IIR_IID_RXDVAL (4)
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+ #define SUNXI_UART_IIR_IID_LINESTA (6)
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+ #define SUNXI_UART_IIR_IID_BUSBSY (7)
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+ #define SUNXI_UART_IIR_IID_CHARTO (12)
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+/* FIFO Control Register */
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+#define SUNXI_UART_FCR_RXTRG_MASK (BIT(6)|BIT(7))
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+ #define SUNXI_UART_FCR_RXTRG_1CH (0 << 6)
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+ #define SUNXI_UART_FCR_RXTRG_1_4 (1 << 6)
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+ #define SUNXI_UART_FCR_RXTRG_1_2 (2 << 6)
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+ #define SUNXI_UART_FCR_RXTRG_FULL (3 << 6)
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+#define SUNXI_UART_FCR_TXTRG_MASK (BIT(4)|BIT(5))
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+ #define SUNXI_UART_FCR_TXTRG_EMP (0 << 4)
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+ #define SUNXI_UART_FCR_TXTRG_2CH (1 << 4)
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+ #define SUNXI_UART_FCR_TXTRG_1_4 (2 << 4)
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+ #define SUNXI_UART_FCR_TXTRG_1_2 (3 << 4)
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+#define SUNXI_UART_FCR_TXFIFO_RST (BIT(2))
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+#define SUNXI_UART_FCR_RXFIFO_RST (BIT(1))
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+#define SUNXI_UART_FCR_FIFO_EN (BIT(0))
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+/* Line Control Register */
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+#define SUNXI_UART_LCR_DLAB (BIT(7))
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+#define SUNXI_UART_LCR_SBC (BIT(6))
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+#define SUNXI_UART_LCR_PARITY_MASK (BIT(5)|BIT(4))
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+ #define SUNXI_UART_LCR_EPAR (1 << 4)
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+ #define SUNXI_UART_LCR_OPAR (0 << 4)
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+#define SUNXI_UART_LCR_PARITY (BIT(3))
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+#define SUNXI_UART_LCR_STOP (BIT(2))
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+#define SUNXI_UART_LCR_DLEN_MASK (BIT(1)|BIT(0))
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+ #define SUNXI_UART_LCR_WLEN5 (0)
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+ #define SUNXI_UART_LCR_WLEN6 (1)
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+ #define SUNXI_UART_LCR_WLEN7 (2)
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+ #define SUNXI_UART_LCR_WLEN8 (3)
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+/* Modem Control Register */
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+#define SUNXI_UART_MCR_MODE_MASK (BIT(7)|BIT(6))
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+ #define SUNXI_UART_MCR_MODE_RS485 (2 << 6)
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+ #define SUNXI_UART_MCR_MODE_SIRE (1 << 6)
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+ #define SUNXI_UART_MCR_MODE_UART (0 << 6)
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+#define SUNXI_UART_MCR_AFE (BIT(5))
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+#define SUNXI_UART_MCR_LOOP (BIT(4))
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+#define SUNXI_UART_MCR_RTS (BIT(1))
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+#define SUNXI_UART_MCR_DTR (BIT(0))
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+/* Line Status Rigster */
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+#define SUNXI_UART_LSR_RXFIFOE (BIT(7))
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+#define SUNXI_UART_LSR_TEMT (BIT(6))
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+#define SUNXI_UART_LSR_THRE (BIT(5))
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+#define SUNXI_UART_LSR_BI (BIT(4))
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+#define SUNXI_UART_LSR_FE (BIT(3))
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+#define SUNXI_UART_LSR_PE (BIT(2))
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+#define SUNXI_UART_LSR_OE (BIT(1))
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+#define SUNXI_UART_LSR_DR (BIT(0))
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+#define SUNXI_UART_LSR_BRK_ERROR_BITS 0x1E /* BI, FE, PE, OE bits */
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+/* Modem Status Register */
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+#define SUNXI_UART_MSR_DCD (BIT(7))
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+#define SUNXI_UART_MSR_RI (BIT(6))
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+#define SUNXI_UART_MSR_DSR (BIT(5))
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+#define SUNXI_UART_MSR_CTS (BIT(4))
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+#define SUNXI_UART_MSR_DDCD (BIT(3))
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+#define SUNXI_UART_MSR_TERI (BIT(2))
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+#define SUNXI_UART_MSR_DDSR (BIT(1))
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+#define SUNXI_UART_MSR_DCTS (BIT(0))
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+#define SUNXI_UART_MSR_ANY_DELTA 0x0F
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+#define MSR_SAVE_FLAGS SUNXI_UART_MSR_ANY_DELTA
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+/* Status Register */
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+#define SUNXI_UART_USR_RFF (BIT(4))
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+#define SUNXI_UART_USR_RFNE (BIT(3))
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+#define SUNXI_UART_USR_TFE (BIT(2))
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+#define SUNXI_UART_USR_TFNF (BIT(1))
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+#define SUNXI_UART_USR_BUSY (BIT(0))
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+/* Halt Register */
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+#define SUNXI_UART_HALT_LCRUP (BIT(2))
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+#define SUNXI_UART_HALT_FORCECFG (BIT(1))
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+#define SUNXI_UART_HALT_HTX (BIT(0))
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+/* RS485 Control and Status Register */
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+#define SUNXI_UART_RS485_RXBFA (BIT(3))
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+#define SUNXI_UART_RS485_RXAFA (BIT(2))
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+
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+/* The global infor of UART channel. */
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+
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+#if defined(CONFIG_ARCH_SUN8IW5) || defined(CONFIG_ARCH_SUN8IW17)
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+#define SUNXI_UART_NUM 5
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+#endif
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+
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+#if defined(CONFIG_ARCH_SUN8IW8)
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+#define SUNXI_UART_NUM 3
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+#endif
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+
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+#if defined(CONFIG_ARCH_SUN8IW11) || defined(CONFIG_ARCH_SUN50IW10)
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+#define SUNXI_UART_NUM 8
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+#endif
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+#if defined(CONFIG_ARCH_SUN8IW10) || defined(CONFIG_ARCH_SUN50IW1)
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+#define SUNXI_UART_NUM 6
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+#endif
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+#if defined(CONFIG_ARCH_SUN8IW12) \
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+ || defined(CONFIG_ARCH_SUN8IW15) \
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+ || defined(CONFIG_ARCH_SUN8IW16) \
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+ || defined(CONFIG_ARCH_SUN8IW6) \
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+ || defined(CONFIG_ARCH_SUN50IW8) \
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+ || defined(CONFIG_ARCH_SUN50IW11) \
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+ || defined(CONFIG_ARCH_SUN50IW3)
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+#define SUNXI_UART_NUM 5
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+#endif
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+#if defined(CONFIG_ARCH_SUN50IW2) \
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+ || defined(CONFIG_ARCH_SUN50IW6) \
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+ || defined(CONFIG_ARCH_SUN8IW7) \
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+ || defined(CONFIG_ARCH_SUN8IW18) \
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+ || defined(CONFIG_ARCH_SUN8IW19)
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+#define SUNXI_UART_NUM 4
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+#endif
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+#if defined(CONFIG_ARCH_SUN3IW1)
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+#define SUNXI_UART_NUM 3
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+#endif
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+
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+#ifndef SUNXI_UART_NUM
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+#define SUNXI_UART_NUM 1
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+#endif
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+
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+/* In 50/39 FPGA, two UART is available, but they share one IRQ.
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+ So we define the number of UART port as 1. */
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+#ifndef CONFIG_EVB_PLATFORM
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+#undef SUNXI_UART_NUM
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+#define SUNXI_UART_NUM 1
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+#endif
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+
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+#if defined(CONFIG_ARCH_SUN8IW12) \
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+ || defined(CONFIG_ARCH_SUN8IW15) \
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+ || defined(CONFIG_ARCH_SUN8IW16) \
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+ || defined(CONFIG_ARCH_SUN8IW18) \
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+ || defined(CONFIG_ARCH_SUN8IW19) \
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+ || defined(CONFIG_ARCH_SUN50IW3) \
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+ || defined(CONFIG_ARCH_SUN50IW6) \
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+ || defined(CONFIG_ARCH_SUN50IW8) \
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+ || defined(CONFIG_ARCH_SUN50IW11) \
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+ || defined(CONFIG_ARCH_SUN8IW17)
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+#define SUNXI_UART_FIFO_SIZE 256
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+#elif defined(CONFIG_ARCH_SUN3IW1)
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+#define SUNXI_UART_FIFO_SIZE 32
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+#else
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+#define SUNXI_UART_FIFO_SIZE 64
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+#endif
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+
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+#define SUNXI_UART_DEV_NAME "uart"
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+
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+struct platform_device *sw_uart_get_pdev(int uart_id);
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+
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+#endif /* end of _SUNXI_UART_H_ */
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