mirror of https://github.com/OpenIPC/firmware.git
243 lines
8.3 KiB
Diff
243 lines
8.3 KiB
Diff
diff -drupN a/drivers/pinctrl/sunxi/pinctrl-sun50iw3p1-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50iw3p1-r.c
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--- a/drivers/pinctrl/sunxi/pinctrl-sun50iw3p1-r.c 1970-01-01 03:00:00.000000000 +0300
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+++ b/drivers/pinctrl/sunxi/pinctrl-sun50iw3p1-r.c 2022-06-12 05:28:14.000000000 +0300
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@@ -0,0 +1,238 @@
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+/*
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+ * Allwinner sun50iw3p1 SoCs R_PIO pinctrl driver.
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+ *
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+ * Copyright(c) 2016-2020 Allwinnertech Co., Ltd.
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+ * Author: WimHuang <huangwei@allwinnertech.com>
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+ *
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+ * This file is licensed under the terms of the GNU General Public
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+ * License version 2. This program is licensed "as is" without any
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+ * warranty of any kind, whether express or implied.
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+ */
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+
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+#include <linux/module.h>
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+#include <linux/platform_device.h>
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+#include <linux/of.h>
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+#include <linux/of_device.h>
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+#include <linux/pinctrl/pinctrl.h>
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+
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+#include "pinctrl-sunxi.h"
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+
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+#ifdef CONFIG_SUNXI_CPUX_NOT_USE_PL_IRQ
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+ #undef SUNXI_FUNCTION_IRQ_BANK
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+ #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) {}
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+ #define PIN_PM_BANK 0
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+#else
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+ #define PIN_PM_BANK 1
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+#endif
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+
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+#define PIN_PL_BANK 0
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+#define IRQ_BANKS (PIN_PM_BANK + 1)
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+
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+static const struct sunxi_desc_pin sun50iw3p1_r_pins[] = {
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x2, "s_rsb0"), /* SCK */
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+ SUNXI_FUNCTION(0x3, "s_twi0"), /* SCK */
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+ SUNXI_FUNCTION(0x7, "io_disabled"),
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+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x2, "s_rsb0"), /* SDA */
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+ SUNXI_FUNCTION(0x3, "s_twi0"), /* SDA */
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+ SUNXI_FUNCTION(0x7, "io_disabled"),
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+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x2, "s_uart0"), /* TX */
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+ SUNXI_FUNCTION(0x7, "io_disabled"),
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+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x2, "s_uart0"), /* RX */
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+ SUNXI_FUNCTION(0x7, "io_disabled"),
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+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x2, "s_jtag0"), /* MS */
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+ SUNXI_FUNCTION(0x7, "io_disabled"),
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+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x2, "s_jtag0"), /* CK */
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+ SUNXI_FUNCTION(0x7, "io_disabled"),
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+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x2, "s_jtag0"), /* DO */
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+ SUNXI_FUNCTION(0x7, "io_disabled"),
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+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x2, "s_jtag0"), /* DI */
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+ SUNXI_FUNCTION(0x7, "io_disabled"),
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+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x2, "s_twi1"), /* SCK */
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+ SUNXI_FUNCTION(0x7, "io_disabled"),
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+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x2, "s_twi1"), /* SDA */
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+ SUNXI_FUNCTION(0x7, "io_disabled"),
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+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x2, "s_twi2"), /* SCK */
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+ SUNXI_FUNCTION(0x7, "io_disabled"),
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+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x2, "s_twi2"), /* SDA */
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+ SUNXI_FUNCTION(0x7, "io_disabled"),
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+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 12),
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x2, "s_spi1"), /* CS */
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+ SUNXI_FUNCTION(0x7, "io_disabled"),
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+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 13),
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x2, "s_spi1"), /* CLK */
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+ SUNXI_FUNCTION(0x7, "io_disabled"),
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+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 14),
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x2, "s_spi1"), /* MOSO */
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+ SUNXI_FUNCTION(0x7, "io_disabled"),
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+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 15),
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x2, "s_spi1"), /* MISO */
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+ SUNXI_FUNCTION(0x7, "io_disabled"),
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+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 16),
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x2, "s_pwm0"), /* PWM */
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+ SUNXI_FUNCTION(0x7, "io_disabled"),
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+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 17),
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x2, "s_cpu"), /* CUR_W */
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+ SUNXI_FUNCTION(0x7, "io_disabled"),
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+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 18),
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x7, "io_disabled"),
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+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 19),
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x7, "io_disabled"),
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+ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)),
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+
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+ /* Hole */
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x7, "io_disabled"),
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+ SUNXI_FUNCTION_IRQ_BANK(0x6, PIN_PM_BANK, 0)),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x7, "io_disabled"),
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+ SUNXI_FUNCTION_IRQ_BANK(0x6, PIN_PM_BANK, 1)),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x7, "io_disabled"),
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+ SUNXI_FUNCTION_IRQ_BANK(0x6, PIN_PM_BANK, 2)),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x7, "io_disabled"),
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+ SUNXI_FUNCTION_IRQ_BANK(0x6, PIN_PM_BANK, 3)),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x7, "io_disabled"),
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+ SUNXI_FUNCTION_IRQ_BANK(0x6, PIN_PM_BANK, 4)),
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+ SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 5),
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+ SUNXI_FUNCTION(0x0, "gpio_in"),
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+ SUNXI_FUNCTION(0x1, "gpio_out"),
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+ SUNXI_FUNCTION(0x7, "io_disabled"),
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+ SUNXI_FUNCTION_IRQ_BANK(0x6, PIN_PM_BANK, 5)),
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+};
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+
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+static const unsigned sun50iw3p1_r_irq_bank_base[] = {
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+#ifndef CONFIG_SUNXI_CPUX_NOT_USE_PL_IRQ
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+ SUNXI_R_PIO_BANK_BASE(PL_BASE, PIN_PL_BANK),
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+#endif
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+ SUNXI_R_PIO_BANK_BASE(PM_BASE, PIN_PM_BANK),
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+};
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+
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+static const struct sunxi_pinctrl_desc sun50iw3p1_r_pinctrl_data = {
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+ .pins = sun50iw3p1_r_pins,
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+ .npins = ARRAY_SIZE(sun50iw3p1_r_pins),
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+ .pin_base = PL_BASE,
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+ .irq_banks = IRQ_BANKS,
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+ .irq_bank_base = sun50iw3p1_r_irq_bank_base,
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+};
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+
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+static int sun50iw3p1_r_pinctrl_probe(struct platform_device *pdev)
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+{
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+ return sunxi_pinctrl_init(pdev, &sun50iw3p1_r_pinctrl_data);
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+}
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+
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+static struct of_device_id sun50iw3p1_r_pinctrl_match[] = {
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+ { .compatible = "allwinner,sun50iw3p1-r-pinctrl", },
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+ {}
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+};
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+MODULE_DEVICE_TABLE(of, sun50iw3p1_r_pinctrl_match);
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+
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+static struct platform_driver sun50iw3p1_r_pinctrl_driver = {
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+ .probe = sun50iw3p1_r_pinctrl_probe,
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+ .driver = {
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+ .name = "sun50iw3p1-r-pinctrl",
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+ .owner = THIS_MODULE,
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+ .of_match_table = sun50iw3p1_r_pinctrl_match,
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+ },
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+};
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+
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+static int __init sun50iw3p1_r_pio_init(void)
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+{
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+ int ret;
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+ ret = platform_driver_register(&sun50iw3p1_r_pinctrl_driver);
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+ if (ret) {
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+ pr_debug("register sun50i r-pio controller failed\n");
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+ return -EINVAL;
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+ }
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+ return 0;
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+}
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+postcore_initcall(sun50iw3p1_r_pio_init);
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+
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+
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+
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+
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+MODULE_AUTHOR("WimHuang<huangwei@allwinnertech.com>");
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+MODULE_DESCRIPTION("Allwinner sun50iw3p1 R_PIO pinctrl driver");
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+MODULE_LICENSE("GPL");
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