mirror of https://github.com/OpenIPC/firmware.git
126 lines
4.6 KiB
Diff
126 lines
4.6 KiB
Diff
diff -drupN a/drivers/clk/sunxi/clk-sun8iw18.h b/drivers/clk/sunxi/clk-sun8iw18.h
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--- a/drivers/clk/sunxi/clk-sun8iw18.h 1970-01-01 03:00:00.000000000 +0300
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+++ b/drivers/clk/sunxi/clk-sun8iw18.h 2022-06-12 05:28:14.000000000 +0300
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@@ -0,0 +1,121 @@
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+/*
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+ * Copyright (C) 2016 Allwinnertech
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * Adjustable factor-based clock implementation
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+ */
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+#ifndef __MACH_SUNXI_CLK_sun8iw18_H
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+#define __MACH_SUNXI_CLK_sun8iw18_H
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+
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+#include <linux/clk-provider.h>
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+#include <linux/clkdev.h>
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+#include <linux/io.h>
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+#include "clk-factors.h"
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+
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+/* CCMU Register List */
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+#define PLL_CPU 0x0000
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+#define PLL_DDR 0x0010
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+#define PLL_PERIPH0 0x0020
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+#define PLL_PERIPH1 0x0028
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+#define PLL_AUDIO 0x0078
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+#define PLL_32K 0x00d8
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+#define PLL_DDRPAT 0x0110
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+#define PLL_PERI0PAT0 0x0120
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+#define PLL_PERI0PAT1 0x0124
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+#define PLL_PERI1PAT0 0x0128
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+#define PLL_PERI1PAT1 0x012C
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+#define PLL_AUDIOPAT0 0x0178
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+#define PLL_AUDIOPAT1 0x017C
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+#define PLL_32kPAT0 0x01D8
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+#define PLL_32kPAT1 0x01DC
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+#define PLL_CPUX_BIAS 0X0300
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+#define PLL_DDR_BIAS 0X0310
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+#define PLL_PERI0_BIAS 0X0320
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+#define PLL_PERI1_BIAS 0X0328
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+#define PLL_AUDIO_BIAS 0X0378
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+#define PLL_32K_BIAS 0X03D8
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+#define PLL_CPUX_TUN 0X0400
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+#define CPU_CFG 0x0500
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+#define PSI_CFG 0x0510
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+#define AHB3_CFG 0x051C
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+#define APB1_CFG 0x0520
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+#define APB2_CFG 0x0524
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+#define MBUS_CFG 0x0540
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+
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+/* Accelerator */
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+#define CE_CFG 0x0680
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+#define CE_GATE 0x068C
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+
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+/* SYS Resource */
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+#define DMA_GATE 0x070C
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+#define HSTIMER_GATE 0x073C
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+#define AVS_CFG 0x0740
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+#define DBGSYS_GATE 0x078C
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+#define PSI_GATE 0x079C
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+#define PWM_GATE 0x07AC
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+
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+/* Storage Medium */
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+#define DRAM_CFG 0x0800
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+#define MBUS_GATE 0x0804
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+#define DRAM_GATE 0x080C
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+#define NAND0_CFG 0x0810
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+#define NAND1_CFG 0x0814
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+#define NAND_GATE 0x082C
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+#define SMHC1_CFG 0x0834
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+#define SMHC_GATE 0x084C
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+
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+/* Common Interface */
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+#define UART_GATE 0x090C
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+#define TWI_GATE 0x091C
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+#define SPI0_CFG 0x0940
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+#define SPI1_CFG 0x0944
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+#define SPI_GATE 0x096C
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+#define GPADC_GATE 0x09EC
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+#define THS_GATE 0x09FC
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+#define I2S0_CFG 0x0A10
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+#define I2S1_CFG 0x0A14
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+#define I2S2_CFG 0x0A18
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+#define I2S_GATE 0x0A1C
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+#define SPDIF_CFG 0x0A20
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+#define SPDIF_GATE 0x0A2C
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+#define DMIC_CFG 0x0A40
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+#define DMIC_GATE 0x0A4C
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+#define CODEC_1X_CFG 0x0A50
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+#define CODEC_4X_CFG 0x0A54
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+#define CODEC_GATE 0x0A5C
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+#define USB0_CFG 0x0A70
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+#define USB_GATE 0x0A8C
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+#define MAD_GATE 0x0ACC
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+#define LPSD_CFG 0x0AD0
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+#define LPSD_GATE 0x0ADC
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+#define LEDC_CFG 0x0BF0
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+#define LEDC_GATE 0x0BFC
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+#define CCMU_SEC_SWITCH 0x0F00
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+#define PLL_LOCK_DBG_CTRL 0x0F04
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+#define PLL_CPUX_HW_FM 0x0F20
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+#define MOD_SPE_CLK 0x0F30
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+#define HOSC_CFG 0x0F40
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+#define CCMU_VERSION 0x0FF0
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+
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+/* range of the registers we want to dump via debugfs/ccudbg/command "dumpreg" */
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+#define SUNXI_CLK_MAX_REG LEDC_GATE
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+
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+/* RTC Register List */
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+#define LOSC_OUT_GATE 0x0060
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+
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+#define F_N8X8_P16x2(nv, pv) (FACTOR_ALL(nv, 8, 8, 0, 0, 0, 0, 0, 0, pv, 16, 2, 0, 0, 0, 0, 0, 0))
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+#define F_N8X8_D1V1X1_D2V0X1(nv, d1v, d2v) (FACTOR_ALL(nv, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, d1v, 1, 1, d2v, 0, 1))
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+#define F_N8X8_D1V1X1(nv, d1v) (FACTOR_ALL(nv, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, d1v, 1, 1, 0, 0, 0))
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+#define F_N8X8_D1V4X2_D2V0X2(nv, d1v, d2v) (FACTOR_ALL(nv, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, d1v, 4, 2, d2v, 0, 2))
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+#define F_N8X8_P16X6_D1V1X1_D2V0X1(nv, pv, d1v, d2v) (FACTOR_ALL(nv, 8, 8, 0, 0, 0, 0, 0, 0, pv, 16, 6, d1v, 1, 1, d2v, 0, 1))
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+
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+#define PLLCPU(n, p, freq) {F_N8X8_P16x2(n, p), freq}
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+#define PLLDDR(n, d1, d2, freq) {F_N8X8_D1V1X1_D2V0X1(n, d1, d2), freq}
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+#define PLLPERIPH0(n, d1, d2, freq) {F_N8X8_D1V1X1_D2V0X1(n, d1, d2), freq}
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+#define PLLPERIPH1(n, d1, d2, freq) {F_N8X8_D1V1X1_D2V0X1(n, d1, d2), freq}
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+#define PLLAUDIO(n, p, d1, d2, freq) {F_N8X8_P16X6_D1V1X1_D2V0X1(n, p, d1, d2), freq}
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+
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+#endif
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