mirror of https://github.com/OpenIPC/firmware.git
301 lines
7.2 KiB
Diff
301 lines
7.2 KiB
Diff
diff -drupN a/drivers/clk/sunxi/clk-sun4i-tcon-ch1.c b/drivers/clk/sunxi/clk-sun4i-tcon-ch1.c
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--- a/drivers/clk/sunxi/clk-sun4i-tcon-ch1.c 2018-08-06 17:23:04.000000000 +0300
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+++ b/drivers/clk/sunxi/clk-sun4i-tcon-ch1.c 1970-01-01 03:00:00.000000000 +0300
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@@ -1,296 +0,0 @@
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-/*
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- * Copyright 2015 Maxime Ripard
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- *
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- * Maxime Ripard <maxime.ripard@free-electrons.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; either version 2 of the License, or
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- * (at your option) any later version.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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- * GNU General Public License for more details.
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- */
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-
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-#include <linux/clk-provider.h>
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-#include <linux/of.h>
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-#include <linux/of_address.h>
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-#include <linux/slab.h>
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-#include <linux/spinlock.h>
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-
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-#define TCON_CH1_SCLK2_PARENTS 4
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-
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-#define TCON_CH1_SCLK2_GATE_BIT BIT(31)
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-#define TCON_CH1_SCLK2_MUX_MASK 3
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-#define TCON_CH1_SCLK2_MUX_SHIFT 24
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-#define TCON_CH1_SCLK2_DIV_MASK 0xf
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-#define TCON_CH1_SCLK2_DIV_SHIFT 0
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-
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-#define TCON_CH1_SCLK1_GATE_BIT BIT(15)
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-#define TCON_CH1_SCLK1_HALF_BIT BIT(11)
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-
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-struct tcon_ch1_clk {
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- struct clk_hw hw;
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- spinlock_t lock;
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- void __iomem *reg;
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-};
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-
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-#define hw_to_tclk(hw) container_of(hw, struct tcon_ch1_clk, hw)
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-
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-static void tcon_ch1_disable(struct clk_hw *hw)
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-{
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- struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
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- unsigned long flags;
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- u32 reg;
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-
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- spin_lock_irqsave(&tclk->lock, flags);
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- reg = readl(tclk->reg);
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- reg &= ~(TCON_CH1_SCLK2_GATE_BIT | TCON_CH1_SCLK1_GATE_BIT);
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- writel(reg, tclk->reg);
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- spin_unlock_irqrestore(&tclk->lock, flags);
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-}
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-
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-static int tcon_ch1_enable(struct clk_hw *hw)
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-{
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- struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
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- unsigned long flags;
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- u32 reg;
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-
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- spin_lock_irqsave(&tclk->lock, flags);
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- reg = readl(tclk->reg);
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- reg |= TCON_CH1_SCLK2_GATE_BIT | TCON_CH1_SCLK1_GATE_BIT;
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- writel(reg, tclk->reg);
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- spin_unlock_irqrestore(&tclk->lock, flags);
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-
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- return 0;
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-}
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-
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-static int tcon_ch1_is_enabled(struct clk_hw *hw)
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-{
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- struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
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- u32 reg;
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-
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- reg = readl(tclk->reg);
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- return reg & (TCON_CH1_SCLK2_GATE_BIT | TCON_CH1_SCLK1_GATE_BIT);
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-}
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-
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-static u8 tcon_ch1_get_parent(struct clk_hw *hw)
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-{
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- struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
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- u32 reg;
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-
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- reg = readl(tclk->reg) >> TCON_CH1_SCLK2_MUX_SHIFT;
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- reg &= reg >> TCON_CH1_SCLK2_MUX_MASK;
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-
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- return reg;
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-}
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-
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-static int tcon_ch1_set_parent(struct clk_hw *hw, u8 index)
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-{
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- struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
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- unsigned long flags;
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- u32 reg;
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-
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- spin_lock_irqsave(&tclk->lock, flags);
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- reg = readl(tclk->reg);
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- reg &= ~(TCON_CH1_SCLK2_MUX_MASK << TCON_CH1_SCLK2_MUX_SHIFT);
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- reg |= index << TCON_CH1_SCLK2_MUX_SHIFT;
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- writel(reg, tclk->reg);
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- spin_unlock_irqrestore(&tclk->lock, flags);
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-
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- return 0;
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-};
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-
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-static unsigned long tcon_ch1_calc_divider(unsigned long rate,
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- unsigned long parent_rate,
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- u8 *div,
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- bool *half)
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-{
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- unsigned long best_rate = 0;
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- u8 best_m = 0, m;
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- bool is_double;
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-
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- for (m = 1; m < 16; m++) {
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- u8 d;
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-
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- for (d = 1; d < 3; d++) {
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- unsigned long tmp_rate;
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-
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- tmp_rate = parent_rate / m / d;
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-
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- if (tmp_rate > rate)
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- continue;
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-
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- if (!best_rate ||
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- (rate - tmp_rate) < (rate - best_rate)) {
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- best_rate = tmp_rate;
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- best_m = m;
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- is_double = d;
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- }
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- }
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- }
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-
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- if (div && half) {
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- *div = best_m;
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- *half = is_double;
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- }
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-
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- return best_rate;
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-}
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-
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-static int tcon_ch1_determine_rate(struct clk_hw *hw,
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- struct clk_rate_request *req)
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-{
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- long best_rate = -EINVAL;
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- int i;
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-
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- for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
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- unsigned long parent_rate;
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- unsigned long tmp_rate;
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- struct clk_hw *parent;
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-
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- parent = clk_hw_get_parent_by_index(hw, i);
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- if (!parent)
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- continue;
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-
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- parent_rate = clk_hw_get_rate(parent);
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-
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- tmp_rate = tcon_ch1_calc_divider(req->rate, parent_rate,
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- NULL, NULL);
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-
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- if (best_rate < 0 ||
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- (req->rate - tmp_rate) < (req->rate - best_rate)) {
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- best_rate = tmp_rate;
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- req->best_parent_rate = parent_rate;
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- req->best_parent_hw = parent;
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- }
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- }
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-
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- if (best_rate < 0)
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- return best_rate;
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-
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- req->rate = best_rate;
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- return 0;
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-}
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-
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-static unsigned long tcon_ch1_recalc_rate(struct clk_hw *hw,
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- unsigned long parent_rate)
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-{
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- struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
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- u32 reg;
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-
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- reg = readl(tclk->reg);
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-
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- parent_rate /= (reg & TCON_CH1_SCLK2_DIV_MASK) + 1;
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-
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- if (reg & TCON_CH1_SCLK1_HALF_BIT)
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- parent_rate /= 2;
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-
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- return parent_rate;
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-}
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-
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-static int tcon_ch1_set_rate(struct clk_hw *hw, unsigned long rate,
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- unsigned long parent_rate)
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-{
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- struct tcon_ch1_clk *tclk = hw_to_tclk(hw);
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- unsigned long flags;
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- bool half;
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- u8 div_m;
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- u32 reg;
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-
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- tcon_ch1_calc_divider(rate, parent_rate, &div_m, &half);
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-
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- spin_lock_irqsave(&tclk->lock, flags);
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- reg = readl(tclk->reg);
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- reg &= ~(TCON_CH1_SCLK2_DIV_MASK | TCON_CH1_SCLK1_HALF_BIT);
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- reg |= (div_m - 1) & TCON_CH1_SCLK2_DIV_MASK;
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-
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- if (half)
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- reg |= TCON_CH1_SCLK1_HALF_BIT;
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-
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- writel(reg, tclk->reg);
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- spin_unlock_irqrestore(&tclk->lock, flags);
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-
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- return 0;
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-}
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-
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-static const struct clk_ops tcon_ch1_ops = {
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- .disable = tcon_ch1_disable,
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- .enable = tcon_ch1_enable,
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- .is_enabled = tcon_ch1_is_enabled,
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-
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- .get_parent = tcon_ch1_get_parent,
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- .set_parent = tcon_ch1_set_parent,
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-
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- .determine_rate = tcon_ch1_determine_rate,
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- .recalc_rate = tcon_ch1_recalc_rate,
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- .set_rate = tcon_ch1_set_rate,
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-};
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-
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-static void __init tcon_ch1_setup(struct device_node *node)
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-{
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- const char *parents[TCON_CH1_SCLK2_PARENTS];
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- const char *clk_name = node->name;
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- struct clk_init_data init;
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- struct tcon_ch1_clk *tclk;
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- struct resource res;
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- struct clk *clk;
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- void __iomem *reg;
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- int ret;
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-
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- of_property_read_string(node, "clock-output-names", &clk_name);
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-
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- reg = of_io_request_and_map(node, 0, of_node_full_name(node));
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- if (IS_ERR(reg)) {
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- pr_err("%s: Could not map the clock registers\n", clk_name);
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- return;
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- }
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-
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- ret = of_clk_parent_fill(node, parents, TCON_CH1_SCLK2_PARENTS);
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- if (ret != TCON_CH1_SCLK2_PARENTS) {
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- pr_err("%s Could not retrieve the parents\n", clk_name);
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- goto err_unmap;
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- }
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-
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- tclk = kzalloc(sizeof(*tclk), GFP_KERNEL);
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- if (!tclk)
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- goto err_unmap;
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-
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- init.name = clk_name;
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- init.ops = &tcon_ch1_ops;
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- init.parent_names = parents;
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- init.num_parents = TCON_CH1_SCLK2_PARENTS;
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- init.flags = CLK_SET_RATE_PARENT;
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-
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- tclk->reg = reg;
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- tclk->hw.init = &init;
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- spin_lock_init(&tclk->lock);
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-
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- clk = clk_register(NULL, &tclk->hw);
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- if (IS_ERR(clk)) {
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- pr_err("%s: Couldn't register the clock\n", clk_name);
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- goto err_free_data;
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- }
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-
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- ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
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- if (ret) {
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- pr_err("%s: Couldn't register our clock provider\n", clk_name);
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- goto err_unregister_clk;
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- }
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-
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- return;
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-
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-err_unregister_clk:
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- clk_unregister(clk);
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-err_free_data:
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- kfree(tclk);
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-err_unmap:
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- iounmap(reg);
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- of_address_to_resource(node, 0, &res);
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- release_mem_region(res.start, resource_size(&res));
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-}
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-
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-CLK_OF_DECLARE(tcon_ch1, "allwinner,sun4i-a10-tcon-ch1-clk",
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- tcon_ch1_setup);
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