mirror of https://github.com/OpenIPC/firmware.git
131 lines
3.9 KiB
Diff
131 lines
3.9 KiB
Diff
diff -drupN a/arch/arm/mach-sunxi/irq-gic-common-sun8iw6.c b/arch/arm/mach-sunxi/irq-gic-common-sun8iw6.c
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--- a/arch/arm/mach-sunxi/irq-gic-common-sun8iw6.c 1970-01-01 03:00:00.000000000 +0300
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+++ b/arch/arm/mach-sunxi/irq-gic-common-sun8iw6.c 2022-06-12 05:28:14.000000000 +0300
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@@ -0,0 +1,126 @@
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+/*
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+ * Copyright (C) 2002 ARM Limited, All Rights Reserved.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
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+ */
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+
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+#include <linux/interrupt.h>
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+#include <linux/io.h>
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+#include <linux/irq.h>
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+#include <linux/irqchip/arm-gic.h>
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+
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+#include "irq-gic-common.h"
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+
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+extern u32 cpu_gic_readl(void __iomem *reg);
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+extern void cpu_gic_writel(u32 val, void __iomem *reg);
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+
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+void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks,
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+ void *data)
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+{
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+ for (; quirks->desc; quirks++) {
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+ if (quirks->iidr != (quirks->mask & iidr))
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+ continue;
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+ quirks->init(data);
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+ pr_info("GIC: enabling workaround for %s\n", quirks->desc);
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+ }
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+}
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+
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+int gic_configure_irq(unsigned int irq, unsigned int type,
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+ void __iomem *base, void (*sync_access)(void))
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+{
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+ u32 confmask = 0x2 << ((irq % 16) * 2);
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+ u32 confoff = (irq / 16) * 4;
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+ u32 val, oldval;
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+ int ret = 0;
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+
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+ /*
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+ * Read current configuration register, and insert the config
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+ * for "irq", depending on "type".
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+ */
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+ val = oldval = cpu_gic_readl(base + GIC_DIST_CONFIG + confoff);
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+ if (type & IRQ_TYPE_LEVEL_MASK)
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+ val &= ~confmask;
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+ else if (type & IRQ_TYPE_EDGE_BOTH)
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+ val |= confmask;
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+
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+ /*
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+ * Write back the new configuration, and possibly re-enable
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+ * the interrupt. If we tried to write a new configuration and failed,
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+ * return an error.
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+ */
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+ cpu_gic_writel(val, base + GIC_DIST_CONFIG + confoff);
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+ if (cpu_gic_readl(base + GIC_DIST_CONFIG + confoff) != val && val != oldval)
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+ ret = -EINVAL;
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+
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+ if (sync_access)
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+ sync_access();
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+
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+ return ret;
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+}
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+
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+void __init gic_dist_config(void __iomem *base, int gic_irqs,
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+ void (*sync_access)(void))
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+{
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+ unsigned int i;
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+
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+ /*
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+ * Set all global interrupts to be level triggered, active low.
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+ */
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+ for (i = 32; i < gic_irqs; i += 16)
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+ cpu_gic_writel(GICD_INT_ACTLOW_LVLTRIG,
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+ base + GIC_DIST_CONFIG + i / 4);
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+
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+ /*
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+ * Set priority on all global interrupts.
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+ */
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+ for (i = 32; i < gic_irqs; i += 4)
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+ cpu_gic_writel(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i);
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+
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+ /*
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+ * Deactivate and disable all SPIs. Leave the PPI and SGIs
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+ * alone as they are in the redistributor registers on GICv3.
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+ */
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+ for (i = 32; i < gic_irqs; i += 32) {
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+ cpu_gic_writel(GICD_INT_EN_CLR_X32,
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+ base + GIC_DIST_ACTIVE_CLEAR + i / 8);
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+ cpu_gic_writel(GICD_INT_EN_CLR_X32,
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+ base + GIC_DIST_ENABLE_CLEAR + i / 8);
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+ }
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+
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+ if (sync_access)
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+ sync_access();
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+}
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+
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+void gic_cpu_config(void __iomem *base, void (*sync_access)(void))
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+{
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+ int i;
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+
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+ /*
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+ * Deal with the banked PPI and SGI interrupts - disable all
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+ * PPI interrupts, ensure all SGI interrupts are enabled.
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+ * Make sure everything is deactivated.
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+ */
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+ cpu_gic_writel(GICD_INT_EN_CLR_X32, base + GIC_DIST_ACTIVE_CLEAR);
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+ cpu_gic_writel(GICD_INT_EN_CLR_PPI, base + GIC_DIST_ENABLE_CLEAR);
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+ cpu_gic_writel(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET);
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+
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+ /*
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+ * Set priority on PPI and SGI interrupts
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+ */
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+ for (i = 0; i < 32; i += 4)
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+ cpu_gic_writel(GICD_INT_DEF_PRI_X4,
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+ base + GIC_DIST_PRI + i * 4 / 4);
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+
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+ if (sync_access)
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+ sync_access();
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+}
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