mirror of https://github.com/OpenIPC/firmware.git
126 lines
5.1 KiB
INI
126 lines
5.1 KiB
INI
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# Untested sensor 2021.01.25
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[sensor]
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Sensor_type =sc1035 ;sensor name
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Mode =0 ;WDR_MODE_NONE = 0
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;WDR_MODE_BUILT_IN = 1
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;WDR_MODE_2To1_LINE = 2
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;WDR_MODE_2To1_FRAME = 3
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;WDR_MODE_2To1_FRAME_FULL_RATE =4 ...etc
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DllFile =/usr/lib/sensors/libsns_sc1035_960p.so ;sensor lib path
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[mode]
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input_mode =4 ;INPUT_MODE_MIPI = 0
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;INPUT_MODE_SUBLVDS = 1
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;INPUT_MODE_LVDS = 2 ...etc
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dev_attr = 2 ;mipi_dev_attr_t = 0
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;lvds_dev_attr_t = 1
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;NULL =2
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[isp_image]
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Isp_x =0
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Isp_y =0
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Isp_W =1280
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Isp_H =720
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Isp_FrameRate=30
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Isp_Bayer =3 ;BAYER_RGGB=0, BAYER_GRBG=1, BAYER_GBRG=2, BAYER_BGGR=3
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[vi_dev]
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Input_mod =2 ;VI_INPUT_MODE_BT656 = 0
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;VI_INPUT_MODE_BT601,
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;VI_INPUT_MODE_DIGITAL_CAMERA
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Work_mod =0 ;VI_WORK_MODE_1Multiplex = 0
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;VI_WORK_MODE_2Multiplex,
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;VI_WORK_MODE_4Multiplex
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Combine_mode =0 ;Y/C composite or separation mode
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;VI_COMBINE_COMPOSITE = 0 /*Composite mode */
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;VI_COMBINE_SEPARATE, /*Separate mode */
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Comp_mode =0 ;Component mode (single-component or dual-component)
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;VI_COMP_MODE_SINGLE = 0, /*single component mode */
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;VI_COMP_MODE_DOUBLE = 1, /*double component mode */
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Clock_edge =1 ;Clock edge mode (sampling on the rising or falling edge)
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;VI_CLK_EDGE_SINGLE_UP=0, /*rising edge */
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;VI_CLK_EDGE_SINGLE_DOWN, /*falling edge */
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Mask_num =2 ;Component mask
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Mask_0 =0xFFF0000
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Mask_1 =0x0
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Scan_mode =1 ;VI_SCAN_INTERLACED = 0
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;VI_SCAN_PROGRESSIVE,
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Data_seq =2 ;data sequence (ONLY for YUV format)
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;----2th component U/V sequence in bt1120
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; VI_INPUT_DATA_VUVU = 0,
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; VI_INPUT_DATA_UVUV,
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;----input sequence for yuv
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; VI_INPUT_DATA_UYVY = 0,
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; VI_INPUT_DATA_VYUY,
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; VI_INPUT_DATA_YUYV,
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; VI_INPUT_DATA_YVYU
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Vsync =1 ; vertical synchronization signal
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;VI_VSYNC_FIELD = 0,
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;VI_VSYNC_PULSE,
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VsyncNeg=0 ;Polarity of the vertical synchronization signal
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;VI_VSYNC_NEG_HIGH = 0,
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;VI_VSYNC_NEG_LOW /*if VIU_VSYNC_E
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Hsync =0 ;Attribute of the horizontal synchronization signal
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;VI_HSYNC_VALID_SINGNAL = 0,
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;VI_HSYNC_PULSE,
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HsyncNeg =0 ;Polarity of the horizontal synchronization signal
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;VI_HSYNC_NEG_HIGH = 0,
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;VI_HSYNC_NEG_LOW
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VsyncValid =0 ;Attribute of the valid vertical synchronization signal
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;VI_VSYNC_NORM_PULSE = 0,
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;VI_VSYNC_VALID_SINGAL,
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VsyncValidNeg =0;Polarity of the valid vertical synchronization signal
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;VI_VSYNC_VALID_NEG_HIGH = 0,
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;VI_VSYNC_VALID_NEG_LOW
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Timingblank_HsyncHfb =0 ;Horizontal front blanking width
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Timingblank_HsyncAct =1280 ;Horizontal effetive width
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Timingblank_HsyncHbb =0 ;Horizontal back blanking width
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Timingblank_VsyncVfb =0 ;Vertical front blanking height
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Timingblank_VsyncVact =960 ;Vertical effetive width
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Timingblank_VsyncVbb=0 ;Vertical back blanking height
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Timingblank_VsyncVbfb =0 ;Even-field vertical front blanking height(interlace, invalid progressive)
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Timingblank_VsyncVbact=0 ;Even-field vertical effetive width(interlace, invalid progressive)
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Timingblank_VsyncVbbb =0 ;Even-field vertical back blanking height(interlace, invalid progressive)
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;----- only for bt656 ----------
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FixCode =0 ;BT656_FIXCODE_1 = 0,
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;BT656_FIXCODE_0
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FieldPolar=0 ;BT656_FIELD_POLAR_STD = 0
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;BT656_FIELD_POLAR_NSTD
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DataPath =1 ;ISP enable or bypass
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;VI_PATH_BYPASS = 0,/* ISP bypass */
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;VI_PATH_ISP = 1,/* ISP enable */
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;VI_PATH_RAW = 2,/* Capture raw data, for debug */
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InputDataType=1 ;VI_DATA_TYPE_YUV = 0,VI_DATA_TYPE_RGB = 1,
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DataRev =FALSE ;Data reverse. FALSE = 0; TRUE = 1
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DevRect_x=0 ;
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DevRect_y=0 ;
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DevRect_w=1280 ;
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DevRect_h=960 ;
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[vi_chn]
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CapRect_X =0
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CapRect_Y =0
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CapRect_Width=1280
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CapRect_Height=960
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DestSize_Width=1280
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DestSize_Height=960
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CapSel =2 ;Frame/field select. ONLY used in interlaced mode
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;VI_CAPSEL_TOP = 0, /* top field */
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;VI_CAPSEL_BOTTOM, /* bottom field */
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;VI_CAPSEL_BOTH, /* top and bottom field */
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PixFormat =19;PIXEL_FORMAT_YUV_SEMIPLANAR_422 = 22
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;PIXEL_FORMAT_YUV_SEMIPLANAR_420 = 23 ...etc
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CompressMode =0 ;COMPRESS_MODE_NONE = 0
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;COMPRESS_MODE_SEG =1 ...etc
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SrcFrameRate=-1 ;Source frame rate. -1: not controll
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FrameRate =-1 ;Target frame rate. -1: not controll
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