mirror of https://github.com/OpenIPC/firmware.git
98 lines
2.5 KiB
Diff
98 lines
2.5 KiB
Diff
diff -drupN a/tools/pm-sleep/include/cpm.h b/tools/pm-sleep/include/cpm.h
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--- a/tools/pm-sleep/include/cpm.h 1970-01-01 03:00:00.000000000 +0300
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+++ b/tools/pm-sleep/include/cpm.h 2022-06-09 05:02:37.000000000 +0300
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@@ -0,0 +1,93 @@
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+/*
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+ * JZSOC CPM register definition.
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+ *
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+ * CPM (Clock reset and Power control Management)
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+ *
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+ * Copyright (C) 2010 Ingenic Semiconductor Co., Ltd.
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+ */
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+
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+#ifndef __CPM_H__
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+#define __CPM_H__
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+#define CPM_IOBASE 0xb0000000
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+
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+
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+#define CPM_CPCCR (0x00)
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+#define CPM_CPCSR (0xd4)
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+
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+#define CPM_DDRCDR (0x2c)
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+#define CPM_VPUCDR (0x30)
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+#define CPM_I2SCDR (0x60)
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+#define CPM_LPCDR (0x64)
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+#define CPM_MSC0CDR (0x68)
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+#define CPM_MSC1CDR (0xa4)
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+#define CPM_MSC2CDR (0xa8)
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+#define CPM_USBCDR (0x50)
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+#define CPM_UHCCDR (0x6c)
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+#define CPM_SSICDR (0x74)
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+#define CPM_CIMCDR (0x7c)
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+#define CPM_PCMCDR (0x84)
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+#define CPM_GPUCDR (0x88)
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+#define CPM_ISPCDR (0x80)
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+#define CPM_BCHCDR (0xac)
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+
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+#define CPM_MPHYC (0xe0)
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+
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+#define CPM_INTR (0xb0)
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+#define CPM_INTRE (0xb4)
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+#define CPM_CPSPPR (0x38)
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+#define CPM_CPPSR (0x34)
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+
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+#define CPM_USBPCR (0x3c)
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+#define CPM_USBRDT (0x40)
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+#define CPM_USBVBFIL (0x44)
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+#define CPM_USBPCR1 (0x48)
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+
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+#define CPM_CPAPCR (0x10)
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+#define CPM_CPMPCR (0x14)
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+#define CPM_CPPCR (0x0c)
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+
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+#define CPM_LCR (0x04)
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+#define CPM_SPCR0 (0xb8)
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+//#define CPM_SPCR1 (0xbc)
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+//#define CPM_SPPC (0xc0)
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+#define CPM_PSWC0ST (0x90)
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+#define CPM_PSWC1ST (0x94)
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+#define CPM_PSWC2ST (0x98)
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+#define CPM_PSWC3ST (0x9c)
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+#define CPM_CLKGR (0x20)
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+#define CPM_CLKGR1 (0x28)
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+#define CPM_SRBC (0xc4)
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+#define CPM_SLBC (0xc8)
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+#define CPM_SLPC (0xcc)
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+#define CPM_OPCR (0x24)
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+#define CPM_RSR (0x08)
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+#define CPM_PGR (0xe4)
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+
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+#define LCR_LPM_MASK (0x3)
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+#define LCR_LPM_SLEEP (0x1)
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+
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+#define CPM_LCR_PD_X2D (0x1<<31)
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+#define CPM_LCR_PD_VPU (0x1<<30)
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+#define CPM_LCR_PD_MASK (0x3<<30)
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+#define CPM_LCR_X2DS (0x1<<27)
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+#define CPM_LCR_VPUS (0x1<<26)
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+#define CPM_LCR_STATUS_MASK (0x3<<26)
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+
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+#define OPCR_ERCS (0x1<<2)
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+#define OPCR_PD (0x1<<3)
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+#define OPCR_IDLE (0x1<<31)
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+
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+//#define CLKGR1_VPU (0x1<<2)
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+#define CLKGR_VPU (0x1<<19)
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+
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+#define cpm_inl(off) REG32(CPM_IOBASE + (off))
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+#define cpm_outl(val,off) REG32(CPM_IOBASE + (off)) = val;
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+#define cpm_clear_bit(val,off) do{cpm_outl((cpm_inl(off) & ~(1 << (val))),off);}while(0)
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+#define cpm_set_bit(val,off) do{cpm_outl((cpm_inl(off) | (1 << (val))),off);}while(0)
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+#define cpm_test_bit(val,off) (cpm_inl(off) & (0x1 << (val)))
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+enum {
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+ SCALE = 0,
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+ RESTORE,
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+};
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+#endif
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+/* __CPM_H__ */
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