mirror of https://github.com/OpenIPC/firmware.git
135 lines
5.3 KiB
Diff
135 lines
5.3 KiB
Diff
diff -drupN a/include/dt-bindings/clock/ingenic-x2000-v12-fpga.h b/include/dt-bindings/clock/ingenic-x2000-v12-fpga.h
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--- a/include/dt-bindings/clock/ingenic-x2000-v12-fpga.h 1970-01-01 03:00:00.000000000 +0300
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+++ b/include/dt-bindings/clock/ingenic-x2000-v12-fpga.h 2022-06-09 05:02:35.000000000 +0300
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@@ -0,0 +1,130 @@
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+#ifndef _DT_BINDINGS_CLOCK_M200_H
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+#define _DT_BINDINGS_CLOCK_M200_H
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+
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+/* Fixed Clk */
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+#define CLK_ID_FIEXED 0
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+#define CLK_EXT (CLK_ID_FIEXED + 0)
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+#define CLK_RTC_EXT (CLK_ID_FIEXED + 1)
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+#define CLK_NR_FIXED (2)
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+
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+/* PLL clk */
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+#define CLK_ID_PLL (CLK_ID_FIEXED + CLK_NR_FIXED)
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+#define CLK_PLL_APLL (CLK_ID_PLL + 0)
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+#define CLK_PLL_MPLL (CLK_ID_PLL + 1)
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+#define CLK_PLL_EPLL (CLK_ID_PLL + 2)
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+#define CLK_NR_PLL (3)
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+
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+/* CPU Clocks */
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+#define CLK_ID_CPCCR (CLK_ID_PLL + CLK_NR_PLL)
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+#define CLK_MUX_SCLKA (CLK_ID_CPCCR + 0)
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+#define CLK_MUX_CPLL (CLK_ID_CPCCR + 1)
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+#define CLK_MUX_H0PLL (CLK_ID_CPCCR + 2)
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+#define CLK_MUX_H2PLL (CLK_ID_CPCCR + 3)
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+#define CLK_RATE_CPUCLK (CLK_ID_CPCCR + 4)
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+#define CLK_RATE_L2CCLK (CLK_ID_CPCCR + 5)
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+#define CLK_RATE_H0CLK (CLK_ID_CPCCR + 6)
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+#define CLK_RATE_H2CLK (CLK_ID_CPCCR + 7)
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+#define CLK_RATE_PCLK (CLK_ID_CPCCR + 8)
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+#define CLK_NR_CPCCR (9)
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+
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+/* CGU clocks */
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+#define CLK_ID_CGU (CLK_ID_CPCCR + CLK_NR_CPCCR)
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+#define CLK_CGU_DDR (CLK_ID_CGU + 0)
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+#define CLK_CGU_MAC0 (CLK_ID_CGU + 1)
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+#define CLK_CGU_LCD (CLK_ID_CGU + 2)
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+#define CLK_CGU_MSC0 (CLK_ID_CGU + 3)
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+#define CLK_CGU_MSC1 (CLK_ID_CGU + 4)
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+#define CLK_CGU_SFC (CLK_ID_CGU + 5)
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+#define CLK_CGU_CIM (CLK_ID_CGU + 6)
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+#define CLK_CGU_PWM (CLK_ID_CGU + 7)
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+#define CLK_CGU_OST (CLK_ID_CGU + 8)
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+#define CLK_CGU_UART4 (CLK_ID_CGU + 9)
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+#define CLK_CGU_UART3 (CLK_ID_CGU + 10)
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+#define CLK_CGU_UART2 (CLK_ID_CGU + 11)
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+#define CLK_CGU_UART1 (CLK_ID_CGU + 12)
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+#define CLK_CGU_UART0 (CLK_ID_CGU + 13)
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+#define CLK_CGU_SMB3 (CLK_ID_CGU + 14)
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+#define CLK_CGU_SMB2 (CLK_ID_CGU + 15)
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+#define CLK_CGU_SMB1 (CLK_ID_CGU + 16)
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+#define CLK_CGU_SMB0 (CLK_ID_CGU + 17)
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+#define CLK_CGU_SSI1 (CLK_ID_CGU + 18)
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+#define CLK_CGU_SSI0 (CLK_ID_CGU + 19)
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+#define CLK_CGU_PDMA (CLK_ID_CGU + 20)
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+#define CLK_CGU_MAC1 (CLK_ID_CGU + 21)
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+#define CLK_CGU_MSC2 (CLK_ID_CGU + 22)
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+#define CLK_CGU_SMB4 (CLK_ID_CGU + 23)
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+#define CLK_NR_CGU (24)
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+
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+#define CLK_ID_CGU_AUDIO (CLK_ID_CGU + CLK_NR_CGU)
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+#define CLK_CGU_I2S0 (CLK_ID_CGU_AUDIO + 0)
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+#define CLK_CGU_I2S1 (CLK_ID_CGU_AUDIO + 1)
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+#define CLK_CGU_I2S2 (CLK_ID_CGU_AUDIO + 2)
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+#define CLK_CGU_I2S3 (CLK_ID_CGU_AUDIO + 3)
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+#define CLK_CGU_SPDIF (CLK_ID_CGU_AUDIO + 4)
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+#define CLK_CGU_PCM (CLK_ID_CGU_AUDIO + 5)
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+#define CLK_CGU_DMIC (CLK_ID_CGU_AUDIO + 6)
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+#define CLK_NR_CGU_AUDIO (7)
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+
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+/* Gate Clocks */
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+#define CLK_ID_GATE (CLK_ID_CGU_AUDIO + CLK_NR_CGU_AUDIO)
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+#define CLK_GATE_DDR (CLK_ID_GATE + 0)
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+#define CLK_GATE_CPU1 (CLK_ID_GATE + 1)
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+#define CLK_GATE_AHB0 (CLK_ID_GATE + 2)
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+#define CLK_GATE_APB0 (CLK_ID_GATE + 3)
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+#define CLK_GATE_RTC (CLK_ID_GATE + 4)
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+#define CLK_GATE_SSI1 (CLK_ID_GATE + 5)
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+#define CLK_GATE_MAC0 (CLK_ID_GATE + 6)
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+#define CLK_GATE_AES (CLK_ID_GATE + 7)
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+#define CLK_GATE_LCD (CLK_ID_GATE + 8)
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+#define CLK_GATE_CIM (CLK_ID_GATE + 9)
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+#define CLK_GATE_PDMA (CLK_ID_GATE + 10)
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+#define CLK_GATE_OST (CLK_ID_GATE + 11)
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+#define CLK_GATE_SSI0 (CLK_ID_GATE + 12)
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+#define CLK_GATE_TCU (CLK_ID_GATE + 13)
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+#define CLK_GATE_DTRNG (CLK_ID_GATE + 14)
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+#define CLK_GATE_UART2 (CLK_ID_GATE + 15)
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+#define CLK_GATE_UART1 (CLK_ID_GATE + 16)
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+#define CLK_GATE_UART0 (CLK_ID_GATE + 17)
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+#define CLK_GATE_SADC (CLK_ID_GATE + 18)
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+#define CLK_GATE_JPEG (CLK_ID_GATE + 19)
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+#define CLK_GATE_AUDIO (CLK_ID_GATE + 20)
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+#define CLK_GATE_SMB3 (CLK_ID_GATE + 21)
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+#define CLK_GATE_SMB2 (CLK_ID_GATE + 22)
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+#define CLK_GATE_SMB1 (CLK_ID_GATE + 23)
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+#define CLK_GATE_SMB0 (CLK_ID_GATE + 24)
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+#define CLK_GATE_SCC (CLK_ID_GATE + 25)
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+#define CLK_GATE_MSC1 (CLK_ID_GATE + 26)
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+#define CLK_GATE_MSC0 (CLK_ID_GATE + 27)
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+#define CLK_GATE_OTG (CLK_ID_GATE + 28)
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+#define CLK_GATE_SFC (CLK_ID_GATE + 29)
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+#define CLK_GATE_EFUSE (CLK_ID_GATE + 30)
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+#define CLK_GATE_NEMC (CLK_ID_GATE + 31)
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+#define CLK_GATE_ARB (CLK_ID_GATE + 32)
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+#define CLK_GATE_MIPI (CLK_ID_GATE + 33)
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+#define CLK_GATE_CPU (CLK_ID_GATE + 34)
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+#define CLK_GATE_INTC (CLK_ID_GATE + 35)
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+#define CLK_GATE_GPIO (CLK_ID_GATE + 36)
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+#define CLK_GATE_SPDIF (CLK_ID_GATE + 37)
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+#define CLK_GATE_DMIC (CLK_ID_GATE + 38)
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+#define CLK_GATE_PCM (CLK_ID_GATE + 39)
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+#define CLK_GATE_I2S3 (CLK_ID_GATE + 40)
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+#define CLK_GATE_I2S2 (CLK_ID_GATE + 41)
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+#define CLK_GATE_I2S1 (CLK_ID_GATE + 42)
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+#define CLK_GATE_I2S0 (CLK_ID_GATE + 43)
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+#define CLK_GATE_ROT (CLK_ID_GATE + 44)
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+#define CLK_GATE_HASH (CLK_ID_GATE + 45)
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+#define CLK_GATE_PWM (CLK_ID_GATE + 46)
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+#define CLK_GATE_UART5 (CLK_ID_GATE + 47)
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+#define CLK_GATE_UART4 (CLK_ID_GATE + 48)
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+#define CLK_GATE_UART3 (CLK_ID_GATE + 49)
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+#define CLK_GATE_SMB5 (CLK_ID_GATE + 50)
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+#define CLK_GATE_SMB4 (CLK_ID_GATE + 51)
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+#define CLK_GATE_USBPHY (CLK_ID_GATE + 52)
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+#define CLK_GATE_MAC1 (CLK_ID_GATE + 53)
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+#define CLK_GATE_MSC2 (CLK_ID_GATE + 54)
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+#define CLK_GATE_VPU (CLK_ID_GATE + 55)
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+#define CLK_NR_GATE (56)
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+#define CLK_ID_OTHER (CLK_ID_GATE + CLK_NR_GATE)
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+
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+#define NR_CLKS (CLK_NR_FIXED + CLK_NR_PLL + CLK_NR_CPCCR + CLK_NR_CGU + CLK_NR_CGU_AUDIO + CLK_NR_GATE)
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+#endif
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