mirror of https://github.com/OpenIPC/firmware.git
97 lines
3.5 KiB
Diff
97 lines
3.5 KiB
Diff
diff -drupN a/include/dt-bindings/clock/ingenic-x1000.h b/include/dt-bindings/clock/ingenic-x1000.h
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--- a/include/dt-bindings/clock/ingenic-x1000.h 1970-01-01 03:00:00.000000000 +0300
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+++ b/include/dt-bindings/clock/ingenic-x1000.h 2022-06-09 05:02:35.000000000 +0300
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@@ -0,0 +1,92 @@
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+#ifndef _DT_BINDINGS_CLOCK_X1000_H
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+#define _DT_BINDINGS_CLOCK_X1000_H
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+
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+
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+/* Fixed Clk */
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+#define CLK_ID_FIEXED 0
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+#define CLK_EXT (CLK_ID_FIEXED + 0)
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+#define CLK_RTC_EXT (CLK_ID_FIEXED + 1)
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+#define CLK_NR_FIXED 2
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+
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+
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+/* PLL clk */
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+#define CLK_ID_PLL (CLK_ID_FIEXED + CLK_NR_FIXED)
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+#define CLK_PLL_APLL (CLK_ID_PLL + 0)
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+#define CLK_PLL_MPLL (CLK_ID_PLL + 1)
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+#define CLK_NR_PLL (2)
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+
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+
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+/* cpccr clocks */
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+#define CLK_ID_CPCCR (CLK_ID_PLL + CLK_NR_PLL)
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+#define CLK_MUX_SCLKA (CLK_ID_CPCCR + 0)
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+#define CLK_MUX_CPLL (CLK_ID_CPCCR + 1)
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+#define CLK_MUX_H0PLL (CLK_ID_CPCCR + 2)
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+#define CLK_MUX_H2PLL (CLK_ID_CPCCR + 3)
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+#define CLK_RATE_CPUCLK (CLK_ID_CPCCR + 4)
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+#define CLK_RATE_L2CCLK (CLK_ID_CPCCR + 5)
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+#define CLK_RATE_H0CLK (CLK_ID_CPCCR + 6)
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+#define CLK_RATE_H2CLK (CLK_ID_CPCCR + 7)
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+#define CLK_RATE_PCLK (CLK_ID_CPCCR + 8)
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+#define CLK_NR_CPCCR (9)
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+
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+/* cgu clocks */
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+#define CLK_ID_DIV (CLK_ID_CPCCR + CLK_NR_CPCCR)
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+#define CLK_CGU_PCM (CLK_ID_DIV + 0)
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+#define CLK_CGU_DDR (CLK_ID_DIV + 1)
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+#define CLK_CGU_MAC (CLK_ID_DIV + 2)
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+#define CLK_CGU_LCD (CLK_ID_DIV + 3)
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+#define CLK_CGU_MSCMUX (CLK_ID_DIV + 4)
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+#define CLK_CGU_MSC0 (CLK_ID_DIV + 5)
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+#define CLK_CGU_MSC1 (CLK_ID_DIV + 6)
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+#define CLK_CGU_USB (CLK_ID_DIV + 7)
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+#define CLK_CGU_SFC (CLK_ID_DIV + 8)
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+#define CLK_CGU_SSI (CLK_ID_DIV + 9)
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+#define CLK_CGU_CIM (CLK_ID_DIV + 10)
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+#define CLK_CGU_I2S (CLK_ID_DIV + 11)
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+#define CLK_NR_CGU (12)
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+
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+/* Gate Clocks */
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+#define CLK_ID_GATE (CLK_ID_DIV + CLK_NR_CGU)
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+#define CLK_GATE_NEMC (CLK_ID_GATE + 0)
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+#define CLK_GATE_EFUSE (CLK_ID_GATE + 1)
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+#define CLK_GATE_SFC (CLK_ID_GATE + 2)
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+#define CLK_GATE_OTG (CLK_ID_GATE + 3)
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+#define CLK_GATE_MSC0 (CLK_ID_GATE + 4)
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+#define CLK_GATE_MSC1 (CLK_ID_GATE + 5)
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+#define CLK_GATE_SCC (CLK_ID_GATE + 6)
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+#define CLK_GATE_I2C0 (CLK_ID_GATE + 7)
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+#define CLK_GATE_I2C1 (CLK_ID_GATE + 8)
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+#define CLK_GATE_I2C2 (CLK_ID_GATE + 9)
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+#define CLK_GATE_I2C3 (CLK_ID_GATE + 10)
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+#define CLK_GATE_AIC (CLK_ID_GATE + 11)
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+#define CLK_GATE_JPEG (CLK_ID_GATE + 12)
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+#define CLK_GATE_SADC (CLK_ID_GATE + 13)
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+#define CLK_GATE_UART0 (CLK_ID_GATE + 14)
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+#define CLK_GATE_UART1 (CLK_ID_GATE + 15)
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+#define CLK_GATE_UART2 (CLK_ID_GATE + 16)
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+#define CLK_GATE_DMIC (CLK_ID_GATE + 17)
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+#define CLK_GATE_TCU (CLK_ID_GATE + 18)
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+#define CLK_GATE_SSI (CLK_ID_GATE + 19)
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+#define CLK_GATE_OST (CLK_ID_GATE + 20)
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+#define CLK_GATE_PDMA (CLK_ID_GATE + 21)
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+#define CLK_GATE_CIM (CLK_ID_GATE + 22)
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+#define CLK_GATE_LCD (CLK_ID_GATE + 23)
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+#define CLK_GATE_AES (CLK_ID_GATE + 24)
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+#define CLK_GATE_MAC (CLK_ID_GATE + 25)
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+#define CLK_GATE_PCM (CLK_ID_GATE + 26)
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+#define CLK_GATE_RTC (CLK_ID_GATE + 27)
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+#define CLK_GATE_APB0 (CLK_ID_GATE + 28)
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+#define CLK_GATE_AHB0 (CLK_ID_GATE + 29)
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+#define CLK_GATE_CPU (CLK_ID_GATE + 30)
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+#define CLK_GATE_DDR (CLK_ID_GATE + 31)
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+#define CLK_GATE_SCLKA (CLK_ID_GATE + 32)
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+#define CLK_GATE_USBPHY (CLK_ID_GATE + 33)
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+#define CLK_GATE_SCLKABUS (CLK_ID_GATE + 34)
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+#define CLK_NR_GATE (35)
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+
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+#define CLK_ID_OTHER (CLK_ID_GATE + CLK_NR_GATE)
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+#define CLK_RTC (CLK_ID_OTHER + 0)
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+#define CLK_NR_OTHER (1)
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+
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+#define NR_CLKS (CLK_NR_FIXED + CLK_NR_PLL + CLK_NR_CPCCR + CLK_NR_CGU + CLK_NR_GATE + CLK_NR_OTHER)
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+#endif
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