mirror of https://github.com/OpenIPC/firmware.git
136 lines
4.5 KiB
Diff
136 lines
4.5 KiB
Diff
diff -drupN a/drivers/rtc/rtc-ingenic.h b/drivers/rtc/rtc-ingenic.h
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--- a/drivers/rtc/rtc-ingenic.h 1970-01-01 03:00:00.000000000 +0300
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+++ b/drivers/rtc/rtc-ingenic.h 2022-06-09 05:02:33.000000000 +0300
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@@ -0,0 +1,131 @@
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+/*
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+ * Copyright (C) 2015 Ingenic Semiconductor Co., Ltd.
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+ * Author: cli <chen.li@ingenic.com>
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+ *
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+ * Real Time Clock register definition for Ingenic's SOC, such as X1000,
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+ * and so on. (kernel.4.4)
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ */
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+
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+#ifndef __RTC_INGENIC_H__
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+#define __RTC_INGENIC_H__
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+
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+/*
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+ * RTC registers offset address definition
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+ */
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+#define RTC_RTCCR (0x00) /* rw, 32, 0x00000081 */
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+#define RTC_RTCSR (0x04) /* rw, 32, 0x???????? */
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+#define RTC_RTCSAR (0x08) /* rw, 32, 0x???????? */
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+#define RTC_RTCGR (0x0c) /* rw, 32, 0x0??????? */
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+
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+#define RTC_HCR (0x20) /* rw, 32, 0x00000000 */
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+#define RTC_HWFCR (0x24) /* rw, 32, 0x0000???0 */
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+#define RTC_HRCR (0x28) /* rw, 32, 0x00000??0 */
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+#define RTC_HWCR (0x2c) /* rw, 32, 0x00000008 */
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+#define RTC_HWRSR (0x30) /* rw, 32, 0x00000000 */
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+#define RTC_HSPR (0x34) /* rw, 32, 0x???????? */
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+#define RTC_WENR (0x3c) /* rw, 32, 0x00000000 */
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+#define RTC_WKUPPINCR (0x48) /* rw, 32, 0x00050064*/
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+
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+/*
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+ * RTC registers common define
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+ */
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+
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+/* RTC control register(RTCCR) */
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+#define RTCCR_WRDY BIT(7)
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+#define RTCCR_1HZ BIT(6)
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+#define RTCCR_1HZIE BIT(5)
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+#define RTCCR_AF BIT(4)
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+#define RTCCR_AIE BIT(3)
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+#define RTCCR_AE BIT(2)
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+#define RTCCR_SELEXC BIT(1)
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+#define RTCCR_RTCE BIT(0)
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+
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+
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+/* Generate the bit field mask from msb to lsb */
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+#define BITS_H2L(msb, lsb) ((0xFFFFFFFF >> (32-((msb)-(lsb)+1))) << (lsb))
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+
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+/* RTC regulator register(RTCGR) */
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+#define RTCGR_LOCK BIT(31)
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+#define RTCGR_ADJC_LSB 16
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+#define RTCGR_ADJC_MASK BITS_H2L(25, RTCGR_ADJC_LSB)
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+#define RTCGR_NC1HZ_LSB 0
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+#define RTCGR_NC1HZ_MASK BITS_H2L(15, RTCGR_NC1HZ_LSB)
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+
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+/* Hibernate control register(HCR) */
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+#define HCR_PD BIT(0)
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+
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+/* Hibernate wakeup filter counter register(HWFCR) */
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+#define HWFCR_LSB 5
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+#define HWFCR_MASK BITS_H2L(15, HWFCR_LSB)
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+#define HWFCR_WAIT_TIME(ms, clk) (((ms)*(clk)/1000+0xf) > HWFCR_MASK ? HWFCR_MASK : ((ms)*(clk)/1000+0xf) & HWFCR_MASK)
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+
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+/* Hibernate reset counter register(HRCR) */
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+#define HRCR_LSB 11
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+#define HRCR_MASK BITS_H2L(14, HRCR_LSB)
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+#define HRCR_WAIT_TIME(ms, clk) (((ms)*(clk)/1000 + 0x3ff - 0x800) > HRCR_MASK ? HRCR_MASK : \
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+ ((ms)*(clk)/1000 + 0x3ff - 0x800) & HRCR_MASK)
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+
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+
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+/* Hibernate wakeup control register(HWCR) */
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+/* Power detect default value; this value means enable */
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+#define EPDET_LSB 3
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+#define EPDET_DEFAULT (0x5aa5a5a << EPDET_LSB)
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+#define EPDET_ENABLE (0x5aa5a5a << EPDET_LSB)
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+#define EPDET_DISABLE (0x1a55a5a5 << EPDET_LSB)
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+#define HWCR_EALM BIT(0)
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+
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+
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+/* Hibernate wakeup status register(HWRSR) */
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+#define HWRSR_APD BIT(8)
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+#define HWRSR_HR BIT(5)
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+#define HWRSR_PPR BIT(4)
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+#define HWRSR_PIN BIT(1)
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+#define HWRSR_ALM BIT(0)
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+
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+/* write enable pattern register(WENR) */
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+#define WENR_WEN BIT(31)
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+#define WENR_WENPAT_LSB 0
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+#define WENR_WENPAT_MASK BITS_H2L(15, WENR_WENPAT_LSB)
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+#define WENR_WENPAT_WRITABLE (0xa55a)
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+
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+/* Hibernate scratch pattern register(HSPR) */
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+#define HSPR_RTCV 0x52544356 /* The value is 'RTCV', means rtc is valid */
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+
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+/*WKUP_PIN_RST control register (WKUPPINCR)*/
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+#define WKUPPINCR_BIAS_CTRL (0x1 << 16) /* fix value*/
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+#define WKUPPINCR_OSC_EN BIT(18)
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+#define WKUPPINCR_P_JUD_LEN_LSB 4
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+#define WKUPPINCR_P_JUD_LEN_MASK BITS_H2L(7, WKUPPINCR_P_JUD_LEN_LSB)
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+#define WKUPPINCR_P_JUD_LEN(s) ((s) << WKUPPINCR_P_JUD_LEN_LSB) > WKUPPINCR_P_JUD_LEN_MASK ? \
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+ WKUPPINCR_P_JUD_LEN_MASK : (s) << WKUPPINCR_P_JUD_LEN_LSB
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+#define WKUPPINCR_P_JUD_EN (0x4)
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+/* The divider is decided by the RTC clock frequency. */
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+#define RTC_FREQ_DIVIDER (32768 - 1)
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+
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+/*ingenic rtc device struct*/
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+struct ingenic_rtc {
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+ int irq;
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+ struct clk *clk;
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+ spinlock_t lock;
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+ spinlock_t rd_lock;
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+ spinlock_t wr_lock;
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+ void __iomem *iomem;
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+ struct mutex mutexlock;
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+ struct mutex mutex_wr_lock;
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+ struct resource *res;
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+ struct work_struct work;
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+ struct rtc_device *rtc;
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+ struct rtc_time rtc_alarm;
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+#ifdef CONFIG_SUSPEND_TEST
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+ unsigned int sleep_count;
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+ unsigned int os_alarm_time;
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+ unsigned int save_rtccr;
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+#endif
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+ struct dentry *debugfs;
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+};
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+#endif /* __RTC_INGENIC_H__ */
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