mirror of https://github.com/OpenIPC/firmware.git
133 lines
3.5 KiB
Diff
133 lines
3.5 KiB
Diff
diff -drupN a/drivers/irqchip/irq-ingenic-cpu.c b/drivers/irqchip/irq-ingenic-cpu.c
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--- a/drivers/irqchip/irq-ingenic-cpu.c 1970-01-01 03:00:00.000000000 +0300
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+++ b/drivers/irqchip/irq-ingenic-cpu.c 2022-06-09 05:02:29.000000000 +0300
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@@ -0,0 +1,128 @@
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+/*
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+ * Copyright (C) 2014 Ingenic Semiconductor Co., Ltd.
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+ *
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+ * Author: dongsheng.qiu, dongsheng.qiu@ingenic.com bo.liu@ingenic.com
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ */
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+
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+#include <linux/init.h>
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+#include <linux/interrupt.h>
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+#include <linux/kernel.h>
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+#include <linux/irq.h>
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+#include <linux/irqchip.h>
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+#include <linux/irqdomain.h>
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+
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+#include <dt-bindings/interrupt-controller/mips-irq.h>
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+
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+#include <asm/irq_cpu.h>
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+#include <asm/mipsregs.h>
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+#include <asm/mipsmtregs.h>
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+#include <asm/setup.h>
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+
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+static inline void unmask_ingenic_irq(struct irq_data *d)
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+{
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+ set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
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+#ifdef CONFIG_SMP
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+ ingenic_irq_cpumask_idle(1);
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+#endif
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+}
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+
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+static inline void mask_ingenic_irq(struct irq_data *d)
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+{
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+ clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
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+#ifdef CONFIG_SMP
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+ ingenic_irq_cpumask_idle(0);
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+ if(d->irq != CORE_INTC_IRQ){
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+ ingenic_irq_migration(1);
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+ }
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+#endif
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+}
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+
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+static struct irq_chip ingenic_cpu_irq_controller = {
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+ .name = "XBurst2",
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+ .irq_ack = mask_ingenic_irq,
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+ .irq_mask = mask_ingenic_irq,
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+ .irq_mask_ack = mask_ingenic_irq,
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+ .irq_unmask = unmask_ingenic_irq,
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+ .irq_eoi = unmask_ingenic_irq,
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+ .irq_disable = mask_ingenic_irq,
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+ .irq_enable = unmask_ingenic_irq,
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+};
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+
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+asmlinkage void __weak plat_irq_dispatch(void)
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+{
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+ unsigned int status = read_c0_status();
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+ unsigned int cause = read_c0_cause();
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+
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+ unsigned long pending = ((status & cause) >> 8) & 0xff;
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+ int irq;
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+
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+ if (!pending) {
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+ spurious_interrupt();
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+ return;
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+ }
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+
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+ if(pending) {
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+ if (pending & 8) { /* IPI */
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+ do_IRQ(MIPS_CPU_IRQ_BASE + 3);
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+ } else if(pending & 16) { /* OST */
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+ do_IRQ(MIPS_CPU_IRQ_BASE + 4);
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+ } else if (pending & 4) { /* INTC */
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+ do_IRQ(MIPS_CPU_IRQ_BASE + 2);
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+ } else { /* Others */
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+ do_IRQ(MIPS_CPU_IRQ_BASE + __ffs(pending));
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+ }
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+
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+ } else {
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+ //printk("IRQ Error, cpu: %d Cause:0x%08lx, Status:0x%08lx\n", smp_processor_id(), cause, status);
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+ }
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+}
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+
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+static int ingenic_cpu_intc_map(struct irq_domain *d, unsigned int irq,
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+ irq_hw_number_t hw)
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+{
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+ static struct irq_chip *chip;
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+
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+ chip = &ingenic_cpu_irq_controller;
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+
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+ irq_set_percpu_devid(irq);
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+ irq_set_chip_and_handler(irq, chip, handle_percpu_devid_irq);
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+
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+ return 0;
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+}
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+
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+static const struct irq_domain_ops ingenic_cpu_intc_irq_domain_ops = {
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+ .map = ingenic_cpu_intc_map,
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+ .xlate = irq_domain_xlate_onecell,
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+};
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+
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+static void __init __ingenic_cpu_irq_init(struct device_node *of_node)
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+{
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+ struct irq_domain *domain;
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+
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+ /* Mask interrupts. */
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+ clear_c0_status(ST0_IM);
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+ clear_c0_cause(CAUSEF_IP);
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+
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+ domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
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+ &ingenic_cpu_intc_irq_domain_ops, NULL);
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+ if (!domain)
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+ panic("Failed to add irqdomain for MIPS CPU");
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+}
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+
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+void __init ingenic_cpu_irq_init(void)
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+{
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+ __ingenic_cpu_irq_init(NULL);
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+}
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+
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+int __init ingenic_cpu_irq_of_init(struct device_node *of_node,
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+ struct device_node *parent)
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+{
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+ __ingenic_cpu_irq_init(of_node);
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+ return 0;
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+}
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+IRQCHIP_DECLARE(cpu_intc, "ingenic,cpu-interrupt-controller", ingenic_cpu_irq_of_init);
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