mirror of https://github.com/OpenIPC/firmware.git
266 lines
7.1 KiB
Diff
266 lines
7.1 KiB
Diff
diff -drupN a/drivers/clk/ingenic/clk-div.c b/drivers/clk/ingenic/clk-div.c
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--- a/drivers/clk/ingenic/clk-div.c 1970-01-01 03:00:00.000000000 +0300
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+++ b/drivers/clk/ingenic/clk-div.c 2022-06-09 05:02:28.000000000 +0300
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@@ -0,0 +1,261 @@
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+#include <linux/clk.h>
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+#include <linux/clk-provider.h>
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+#include <linux/io.h>
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+#include <linux/slab.h>
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+#include <linux/jiffies.h>
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+#include <linux/err.h>
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+#include "clk.h"
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+
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+
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+struct clk_cgu_divider {
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+ struct clk_divider div;
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+ const struct clk_ops *div_ops;
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+ int busy_shift;
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+ int en_shift;
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+ int stop_shift;
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+ spinlock_t *lock;
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+};
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+
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+
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+static int clk_cgu_wait(void __iomem *reg, u8 shift)
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+{
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+ unsigned int timeout = 0xfffff;
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+
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+ while (((readl(reg) >> shift) & 1) && timeout--);
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+ if (!timeout) {
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+ printk("WARNING : why cannot wait cgu stable ???\n");
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+ return -EIO;
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+ } else {
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+ return 0;
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+ }
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+
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+}
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+
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+static int cgu_divider_enable(struct clk_cgu_divider *cgu_div)
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+{
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+ int ret;
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+ unsigned int val;
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+ int ce, stop;
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+
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+ val = readl(cgu_div->div.reg);
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+
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+ ce = cgu_div->en_shift;
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+ stop = cgu_div->stop_shift;
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+
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+ val |= (1 << ce);
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+ val &= ~(1 << stop);
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+ writel(val, cgu_div->div.reg);
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+
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+ ret = clk_cgu_wait(cgu_div->div.reg, cgu_div->busy_shift);
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+ if(ret < 0) {
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+ printk("wait cgu stable timeout!\n");
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+ }
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+
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+ val &= ~(1 << ce);
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+ writel(val, cgu_div->div.reg);
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+
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+ return ret;
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+}
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+
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+static void cgu_divider_disable(struct clk_cgu_divider *cgu_div)
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+{
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+ unsigned int val;
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+ int ce, stop;
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+
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+ val = readl(cgu_div->div.reg);
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+
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+ ce = cgu_div->en_shift;
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+ stop = cgu_div->stop_shift;
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+
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+ val |= (1 << ce);
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+ val |= (1 << stop);
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+ writel(val, cgu_div->div.reg);
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+
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+ val &= ~(1 << ce);
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+ writel(val, cgu_div->div.reg);
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+
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+}
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+
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+static inline struct clk_cgu_divider *to_clk_cgu_divider(struct clk_hw *hw)
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+{
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+ struct clk_divider *div = container_of(hw, struct clk_divider, hw);
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+
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+ return container_of(div, struct clk_cgu_divider, div);
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+}
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+
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+static unsigned long clk_cgu_divider_recalc_rate(struct clk_hw *hw,
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+ unsigned long parent_rate)
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+{
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+ struct clk_cgu_divider *cgu_div = to_clk_cgu_divider(hw);
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+ struct clk_divider *divider = &cgu_div->div;
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+
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+ return cgu_div->div_ops->recalc_rate(&cgu_div->div.hw, parent_rate);
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+}
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+
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+static long clk_cgu_divider_round_rate(struct clk_hw *hw, unsigned long rate,
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+ unsigned long *prate)
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+{
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+ struct clk_cgu_divider *cgu_div = to_clk_cgu_divider(hw);
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+ unsigned long bestrate;
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+
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+ return cgu_div->div_ops->round_rate(&cgu_div->div.hw, rate, prate);
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+}
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+
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+static int clk_cgu_divider_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate)
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+{
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+ struct clk_cgu_divider *cgu_div = to_clk_cgu_divider(hw);
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+ struct clk_divider *divider = &cgu_div->div;
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+ int ret;
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+ unsigned long flags = 0;
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+
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+ if(cgu_div->lock)
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+ spin_lock_irqsave(cgu_div->lock, flags);
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+
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+ ret = cgu_div->div_ops->set_rate(&cgu_div->div.hw, rate, parent_rate);
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+
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+ cgu_divider_enable(cgu_div);
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+
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+
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+ if(cgu_div->lock)
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+ spin_unlock_irqrestore(cgu_div->lock, flags);
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+
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+ return ret;
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+}
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+
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+static void clk_cgu_divider_disable(struct clk_hw *hw)
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+{
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+ struct clk_cgu_divider *cgu_div = to_clk_cgu_divider(hw);
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+ unsigned long flags = 0;
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+
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+ if(cgu_div->lock)
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+ spin_lock_irqsave(cgu_div->lock, flags);
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+
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+ cgu_divider_disable(cgu_div);
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+
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+ if(cgu_div->lock)
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+ spin_unlock_irqrestore(cgu_div->lock, flags);
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+
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+}
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+
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+
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+static int clk_cgu_divider_enable(struct clk_hw *hw)
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+{
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+ struct clk_cgu_divider *cgu_div = to_clk_cgu_divider(hw);
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+ unsigned long flags = 0;
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+
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+ if(cgu_div->lock)
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+ spin_lock_irqsave(cgu_div->lock, flags);
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+
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+ cgu_divider_enable(cgu_div);
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+
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+ if(cgu_div->lock)
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+ spin_unlock_irqrestore(cgu_div->lock, flags);
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+
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+ return 0;
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+}
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+
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+static struct clk_ops clk_cgu_divider_ops = {
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+ .recalc_rate = clk_cgu_divider_recalc_rate,
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+ .round_rate = clk_cgu_divider_round_rate,
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+ .set_rate = clk_cgu_divider_set_rate,
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+ .enable = clk_cgu_divider_enable,
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+ .disable = clk_cgu_divider_disable,
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+};
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+
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+struct clk *_register_cgu_divider(struct device *dev, const char *name,
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+ const char *parent_name, unsigned long flags,
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+ void __iomem *reg, u8 shift, u8 width, u8 busy_shift,
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+ int en_shift, u8 stop_shift, u8 clk_divider_flags,
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+ const struct clk_div_table *table,
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+ spinlock_t *lock)
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+{
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+ struct clk_cgu_divider *cgu_div;
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+ struct clk *clk;
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+ struct clk_init_data init;
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+
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+ cgu_div = kzalloc(sizeof(*cgu_div), GFP_KERNEL);
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+ if (!cgu_div)
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+ return ERR_PTR(-ENOMEM);
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+
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+ init.name = name;
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+ init.ops = &clk_cgu_divider_ops;
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+ init.flags = flags | CLK_IS_BASIC;
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+ init.parent_names = (parent_name ? &parent_name: NULL);
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+ init.num_parents = (parent_name ? 1 : 0);
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+
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+ cgu_div->busy_shift = busy_shift;
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+ cgu_div->en_shift = en_shift;
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+ cgu_div->stop_shift = stop_shift;
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+ cgu_div->lock = lock;
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+
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+ cgu_div->div.reg = reg;
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+ cgu_div->div.shift = shift;
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+ cgu_div->div.width = width;
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+ //cgu_div->div.lock = lock;
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+ cgu_div->div.lock = NULL; /* keep common block unlocked. add lock in this file */
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+ cgu_div->div.table = table;
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+ cgu_div->div.flags = clk_divider_flags;
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+ cgu_div->div_ops = &clk_divider_ops;
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+
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+
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+ cgu_div->div.hw.init = &init;
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+
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+ clk = clk_register(dev, &cgu_div->div.hw);
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+ if (IS_ERR(clk)) {
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+ kfree(cgu_div);
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+ } else {
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+ __clk_set_flags(clk, 1);
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+ }
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+
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+ return clk;
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+}
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+
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+/**
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+ * clk_register_divider_table - register a table based divider clock with
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+ * the clock framework
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+ * @dev: device registering this clock
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+ * @name: name of this clock
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+ * @parent_name: name of clock's parent
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+ * @flags: framework-specific flags
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+ * @reg: register address to adjust divider
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+ * @shift: number of bits to shift the bitfield
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+ * @busy_shift: bit index of busy in busy register.
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+ * @width: width of the bitfield
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+ * @clk_divider_flags: divider-specific flags for this clock
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+ * @table: array of divider/value pairs ending with a div set to 0
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+ * @lock: shared register lock for this clock
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+ */
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+struct clk *clk_register_cgu_divider_table(struct device *dev, const char *name,
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+ const char *parent_name, unsigned long flags,
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+ void __iomem *reg, u8 shift, u8 width, u8 busy_shift,
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+ int en_shift, u8 stop_shift, u8 clk_divider_flags,
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+ const struct clk_div_table *table,
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+ spinlock_t *lock)
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+{
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+ return _register_cgu_divider(dev, name, parent_name, flags, reg, shift,
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+ width, busy_shift, en_shift, stop_shift, clk_divider_flags, table, lock);
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+}
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+
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+
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+/**
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+ * clk_register_divider - register a divider clock with the clock framework
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+ * @dev: device registering this clock
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+ * @name: name of this clock
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+ * @parent_name: name of clock's parent
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+ * @flags: framework-specific flags
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+ * @reg: register address to adjust divider
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+ * @shift: number of bits to shift the bitfield
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+ * @width: width of the bitfield
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+ * @busy_shift: bit index of busy in busy register.
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+ * @clk_divider_flags: divider-specific flags for this clock
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+ * @lock: shared register lock for this clock
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+ */
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+struct clk *clk_register_cgu_divider(struct device *dev, const char *name,
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+ const char *parent_name, unsigned long flags,
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+ void __iomem *reg, u8 shift, u8 width, u8 busy_shift,
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+ int en_shift, u8 stop_shift,
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+ u8 clk_divider_flags, spinlock_t *lock)
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+{
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+ return _register_cgu_divider(dev, name, parent_name, flags, reg, shift, width, busy_shift, en_shift, stop_shift, clk_divider_flags, NULL, lock);
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+}
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+
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