firmware/br-ext-chip-hisilicon/board/hi3536cv100/kernel/patches/0013-add-xm25qh128-spi-nor....

49 lines
1.7 KiB
Diff

--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1024,6 +1024,23 @@
.erase_types[1] = SNOR_OP_ERASE_4K(SPINOR_OP_BE_4K),
};
+
+static const struct spi_nor_basic_flash_parameter xmc_params = {
+ .rd_modes = SNOR_RD_MODES,
+ .reads[SNOR_MIDX_SLOW] = SNOR_OP_READ(0, 0, SPINOR_OP_READ),
+ .reads[SNOR_MIDX_1_1_1] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_FAST),
+ .reads[SNOR_MIDX_1_1_2] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_2),
+ .reads[SNOR_MIDX_1_2_2] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_2_2),
+ .reads[SNOR_MIDX_1_1_4] = SNOR_OP_READ(0, 8, SPINOR_OP_READ_1_1_4),
+ .reads[SNOR_MIDX_1_4_4] = SNOR_OP_READ(0, 24, SPINOR_OP_READ_1_4_4),
+
+ .wr_modes = SNOR_WR_MODES,
+ .page_programs[SNOR_MIDX_1_1_1] = SPINOR_OP_PP,
+ .page_programs[SNOR_MIDX_1_1_4] = SPINOR_OP_PP_1_1_4,
+
+ .erase_types[0] = SNOR_OP_ERASE_64K(SPINOR_OP_SE),
+};
+
#define PARAMS(_name) .params = &_name##_params
/* Used when the "_ext_id" is two bytes at most */
@@ -1063,7 +1080,7 @@
.addr_width = (_addr_width), \
.flags = (_flags),
-/* Different from spi-max-frequency in DTS, the clk here stands for the clock
+/* Different from spi-max-frequency in DTS, the clk here stands for the clock
* rate on SPI interface, it is half of the FMC CRG configuration */
#define CLK_MHZ_2X(clk) .clkrate = (clk * 2000000),
@@ -1387,6 +1404,12 @@
{ "pn25f32s", INFO(0xe04016, 0, 64 * 1024, 64,
SPI_NOR_QUAD_READ), PARAMS(paragon), CLK_MHZ_2X(80) },
+ /* XMC 3.3V */
+ { "xm25qh128a", INFO(0x207018, 0, 64 * 1024, 256, SPI_NOR_DUAL_READ),
+ PARAMS(xmc) },
+ { "xm25qh128b", INFO(0x206018, 0, 64 * 1024, 256, SPI_NOR_DUAL_READ),
+ PARAMS(xmc) },
+
{ },
};