diff -drupN a/include/linux/sunxi_dramfreq.h b/include/linux/sunxi_dramfreq.h --- a/include/linux/sunxi_dramfreq.h 1970-01-01 03:00:00.000000000 +0300 +++ b/include/linux/sunxi_dramfreq.h 2022-06-12 05:28:14.000000000 +0300 @@ -0,0 +1,280 @@ +/* + * drivers/devfreq/dramfreq/sunxi_dramfreq.h + * + * Copyright(c) 2013-2015 Allwinnertech Co., Ltd. + * + * Author: Pan Nan + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __SUNXI_DRAMFREQ_H__ +#define __SUNXI_DRAMFREQ_H__ + +#if defined(CONFIG_ARCH_SUN50IW3) +#define SUNXI_DRAMFREQ_NORMAL (552000) +#else +#define SUNXI_DRAMFREQ_NORMAL (300000) +#endif +#define SUNXI_DRAMFREQ_IDLE (168000) + +#if defined(CONFIG_ARCH_SUN50IW3) || defined(CONFIG_ARCH_SUN50IW6) +#if defined(CONFIG_ARCH_SUN50IW6) +#define SUNXI_DRAM_FREQ_GOVERNOR "performance" +#else +#define SUNXI_DRAM_FREQ_GOVERNOR "adaptive" +#endif +/* Master reg number depend on platform */ +#define MASTER_REG_NUM 2 +/* Dramc Common register define */ +#define MC_WORK_MODE (0x000) +#define MC_TIME_MEASUREMENT (0x00c) +#define MC_MDFSCR (0x100) +#define MC_MDFSMRMR (0x108) +#define MDFS_BWC_PRD (0x114) + +#define MDFS_MASTER_ENABLE(x) (0x130 + 0x4 * (x)) +#define MDFS_MASTER_ENABLE0 (0x130) +#define MDFS_MASTER_ENABLE1 (0x134) + +#define MDFS_IRQ_ACCESS_STATUS(x) (0x140 + 0x4 * (x)) +#define MDFS_IRQ_ACCESS_STATUS0 (0x140) +#define MDFS_IRQ_ACCESS_STATUS1 (0x144) + +#define MDFS_IRQ_IDLE_STATUS(x) (0x148 + 0x4 * (x)) +#define MDFS_IRQ_IDLE_STATUS0 (0x148) +#define MDFS_IRQ_IDLE_STATUS1 (0x14C) + +#define MDFS_IRQ_ACCESS_MASK_STA(x) (0x150 + 0x4 * (x)) +#define MDFS_IRQ_ACCESS_MASK_STA0 (0x150) +#define MDFS_IRQ_ACCESS_MASK_STA1 (0x154) + +#define MDFS_IRQ_IDLE_MASK_STA(x) (0x158 + 0x4 * (x)) +#define MDFS_IRQ_IDLE_MASK_STA0 (0x158) +#define MDFS_IRQ_IDLE_MASK_STA1 (0x15C) +/* Dram Controller register define */ +#define PTR2 (0x04c) +#define RFSHTMG (0x090) +#define RFSHCTL1 (0x094) +#define VTFCR (0x0b8) +#define PGCR0 (0x100) +#define ODTMAP (0x120) +#define DXnGCR0(x) (0x344 + 0x80 * (x)) +/* CCMU register define */ +#define CCM_PLL_DDR1_REG (0x18) +#define CCM_DRAM_CFG_REG (0x800) +/* CCMU register define */ +#define CCM_DRAM_CFG_REG_PLL0_1_BIT (24) + +#elif defined(CONFIG_ARCH_SUN8IW16) + +/* avoid compiler error */ +#define MASTER_MAX (0) +#define MASTER_REG_NUM (0) +#define PTR2 (0) +#define MC_MDFSMRMR (0) + +#define _DRAM_CLK_REG (0x800) + +#elif defined(CONFIG_ARCH_SUN8IW18) + +/* avoid compiler error */ +#define MASTER_MAX (0) +#define MASTER_REG_NUM (0) + +#define _DRAM_CLK_REG (0x800) +#define MC_WORK_MODE (0x00) +#define MC_MDFSCR (0x100) +#define MC_MDFSMRMR (0x108) +#define PTR2 (0x0000004c) +#define PGCR0 (0x00000100) +#define VTFCR (0x000000b8) +#define RFSHTMG (0x00000090) +#define DXnGCR0(x) (0x00000344 + 0x80 * x) +#define ODTMAP (0x00000120) + +#else +#define SUNXI_DRAM_FREQ_GOVERNOR "adaptive" + +/* Master reg number depend on platform */ +#define MASTER_REG_NUM 1 +/* Dramc Common register define */ +#define MC_WORK_MODE (0x000) +#define MC_TIME_MEASUREMENT (0x00c) +#define MC_MDFSCR (0x100) +#define MC_MDFSMRMR (0x108) +#define MDFS_IRQ_ACCESS_STATUS(x) (0x114 + 0x4 * (x)) +#define MDFS_IRQ_ACCESS_STATUS0 (0x114) +#define MDFS_IRQ_IDLE_STATUS(x) (0x118 + 0x4 * (x)) +#define MDFS_IRQ_IDLE_STATUS0 (0x118) +#define MDFS_IRQ_ACCESS_MASK_STA(x) (0x11C + 0x4 * (x)) +#define MDFS_IRQ_ACCESS_MASK_STA0 (0x11C) +#define MDFS_IRQ_IDLE_MASK_STA(x) (0x120 + 0x4 * (x)) +#define MDFS_IRQ_IDLE_MASK_STA0 (0x120) +#define MDFS_BWC_PRD (0x124) +#define MDFS_MASTER_ENABLE(x) (0x134 + 0x4 * (x)) +#define MDFS_MASTER_ENABLE0 (0x134) +#define MDFS_MASTER_STATUS (0x138) +/* Dram Controller register define */ +#define PTR2 (0x04c) +#define RFSHTMG (0x090) +#define VTFCR (0x0b8) +#define PGCR0 (0x100) +#define ODTMAP (0x120) +#define DXnGCR0(x) (0x344 + 0x80 * (x)) +/* CCMU register define */ +#define CCM_PLL_DDR1_REG (0x4C) +#define CCM_DRAM_CFG_REG (0xF4) +/* CCMU register define */ +#define CCM_DRAM_CFG_REG_PLL0_1_BIT (20) + +#endif + +#if defined(CONFIG_ARCH_SUN50I) +#if defined(CONFIG_ARCH_SUN50IW6) +enum DRAM_KEY_MASTER { + MASTER_NULL, + MASTER_GPU, + MASTER_CSI, + MASTER_DE, + MASTER_MAX, +}; +#elif defined(CONFIG_ARCH_SUN50IW3) +enum DRAM_KEY_MASTER { + MASTER_GPU, + MASTER_VE, + MASTER_DE, + MASTER_MAX, +}; +#else +enum DRAM_KEY_MASTER { + MASTER_GPU, + MASTER_CSI, + MASTER_DE, + MASTER_MAX, +}; +#endif +#elif defined(CONFIG_ARCH_SUN8IW10) +enum DRAM_KEY_MASTER { +#ifdef CONFIG_EINK_PANEL_USED + MASTER_EINK0, + MASTER_EDMA, + MASTER_EINK1, +#else + MASTER_DE, +#endif + MASTER_CSI, + MASTER_MAX, +}; + +#elif defined(CONFIG_ARCH_SUN8IW11) +enum DRAM_KEY_MASTER { + MASTER_GPU, + MASTER_CSI, + MASTER_DE, + MASTER_MAX, +}; +#endif + +enum DRAM_FREQ_LEVEL { + LV_0, + LV_1, + LV_2, + LV_3, + LV_4, + LV_END, +}; + +enum DRAM_FREQ_TREND { + FREQ_DOWN, + FREQ_UP, +}; + +enum DRAM_MDFS_MODE { + DFS_MODE, + CFS_MODE, +}; + +enum GOVERNOR_STATE { + STATE_INIT, + STATE_EXIT, + STATE_RUNNING, + STATE_PAUSE, +}; + +struct dram_para_t { + unsigned int dram_clk; + unsigned int dram_type; + unsigned int dram_zq; + unsigned int dram_odt_en; + unsigned int dram_para1; + unsigned int dram_para2; + unsigned int dram_mr0; + unsigned int dram_mr1; + unsigned int dram_mr2; + unsigned int dram_mr3; + unsigned int dram_tpr0; + unsigned int dram_tpr1; + unsigned int dram_tpr2; + unsigned int dram_tpr3; + unsigned int dram_tpr4; + unsigned int dram_tpr5; + unsigned int dram_tpr6; + unsigned int dram_tpr7; + unsigned int dram_tpr8; + unsigned int dram_tpr9; + unsigned int dram_tpr10; + unsigned int dram_tpr11; + unsigned int dram_tpr12; + unsigned int dram_tpr13; +}; + +struct sunxi_dramfreq { + struct devfreq_soc_data const *soc_data; + struct dev_pm_opp *curr_opp; + unsigned int max; + unsigned int min; +#ifndef CONFIG_DEVFREQ_DRAM_FREQ_WITH_SOFT_NOTIFY + unsigned int irq; + unsigned int irq_access_status[MASTER_REG_NUM]; + unsigned int irq_idle_status[MASTER_REG_NUM]; + unsigned int irq_access_mask_sta[MASTER_REG_NUM]; + unsigned int irq_idle_mask_sta[MASTER_REG_NUM]; +#endif + unsigned int pause; + unsigned int key_masters[MASTER_MAX]; + enum DRAM_MDFS_MODE mode; + +#ifdef CONFIG_DEBUG_FS + s64 dramfreq_set_us; + s64 dramfreq_get_us; +#endif + + struct mutex lock; + spinlock_t master_lock; + struct dram_para_t dram_para; + unsigned int master_reg_num; + + struct devfreq *devfreq; + + void __iomem *dramcom_base; + void __iomem *dramctl_base; + void __iomem *ccu_base; + + struct clk *clk_pll_ddr0; + struct clk *clk_pll_ddr1; + + int (*governor_state_update)(char *name, enum GOVERNOR_STATE); +}; + +extern struct sunxi_dramfreq *dramfreq; +extern unsigned long dramfreq_get(void); + +#ifdef CONFIG_DEVFREQ_DRAM_FREQ_WITH_SOFT_NOTIFY +extern int dramfreq_master_access(enum DRAM_KEY_MASTER master, bool access); +#endif + +#endif /* __SUNXI_DRAMFREQ_H__ */