diff -drupN a/arch/arm/mach-sunxi/irq-gic-sun8iw6.c b/arch/arm/mach-sunxi/irq-gic-sun8iw6.c --- a/arch/arm/mach-sunxi/irq-gic-sun8iw6.c 1970-01-01 03:00:00.000000000 +0300 +++ b/arch/arm/mach-sunxi/irq-gic-sun8iw6.c 2022-06-12 05:28:14.000000000 +0300 @@ -0,0 +1,1542 @@ +/* + * Copyright (C) 2002 ARM Limited, All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Interrupt architecture for the GIC: + * + * o There is one Interrupt Distributor, which receives interrupts + * from system devices and sends them to the Interrupt Controllers. + * + * o There is one CPU Interface per CPU, which sends interrupts sent + * by the Distributor, and interrupts generated locally, to the + * associated CPU. The base address of the CPU interface is usually + * aliased so that the same address points to different chips depending + * on the CPU it is accessed from. + * + * Note that IRQs 0-31 are special - they are local to each CPU. + * As such, the enable set/clear, pending set/clear and active bit + * registers are banked per-cpu for these sources. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "irq-gic-common.h" +#include + +#ifdef CONFIG_ARM64 +#include + +static void gic_check_cpu_features(void) +{ + WARN_TAINT_ONCE(cpus_have_cap(ARM64_HAS_SYSREG_GIC_CPUIF), + TAINT_CPU_OUT_OF_SPEC, + "GICv3 system registers enabled, broken firmware!\n"); +} +#else +#define gic_check_cpu_features() do { } while (0) +#endif + +union gic_base { + void __iomem *common_base; + void __percpu * __iomem *percpu_base; +}; + +struct gic_chip_data { + union gic_base dist_base; + union gic_base cpu_base; +#ifdef CONFIG_CPU_PM + u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; + u32 saved_spi_active[DIV_ROUND_UP(1020, 32)]; + u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; + u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; + u32 __percpu *saved_ppi_enable; + u32 __percpu *saved_ppi_active; + u32 __percpu *saved_ppi_conf; +#endif + struct irq_domain *domain; + unsigned int gic_irqs; +#ifdef CONFIG_GIC_NON_BANKED + void __iomem *(*get_base)(union gic_base *); +#endif +}; + +static DEFINE_RAW_SPINLOCK(irq_controller_lock); + +/* + * The GIC mapping of CPU interfaces does not necessarily match + * the logical CPU numbering. Let's use a mapping as returned + * by the GIC itself. + */ +#define NR_GIC_CPU_IF 8 +static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; + +static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; + +#ifndef MAX_GIC_NR +#define MAX_GIC_NR 1 +#endif + +static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly; +static DEFINE_RWLOCK(cpu_ahb_lock); + +#if (defined CONFIG_ARM_SUN8IW6_CPUIDLE) +static DEFINE_SPINLOCK(gic_cpucfg_lock); +static volatile unsigned int hwlock_initd_flg; + +void hwspinlock_ready_init(void) +{ + hwlock_initd_flg = 1; +} + +EXPORT_SYMBOL(hwspinlock_ready_init); +#endif + +u32 cpu_cfg_readl(void __iomem *reg) +{ + u32 ret; + unsigned long flags; + +#if (defined CONFIG_ARM_SUN8IW6_CPUIDLE) + if (hwlock_initd_flg) { + if (arisc_hwspin_lock_timeout(SUNXI_HWSPINLOCKID_CPUIDLE, + ARISC_SPINLOCK_TIMEOUT, &gic_cpucfg_lock, &flags)) + printk(KERN_WARNING "%s,%d timeout\n", __func__, __LINE__); + } else +#endif + write_lock_irqsave(&cpu_ahb_lock, flags); + + ret = sunxi_smc_readl(reg); + +#if (defined CONFIG_ARM_SUN8IW6_CPUIDLE) + if (hwlock_initd_flg) + arisc_hwspin_unlock(SUNXI_HWSPINLOCKID_CPUIDLE, + &gic_cpucfg_lock, &flags); + else +#endif + write_unlock_irqrestore(&cpu_ahb_lock, flags); + + return ret; +} +EXPORT_SYMBOL(cpu_cfg_readl); + +void cpu_cfg_writel(u32 val, void __iomem *reg) +{ + unsigned long flags; + +#if (defined CONFIG_ARM_SUN8IW6_CPUIDLE) + if (hwlock_initd_flg) { + if (arisc_hwspin_lock_timeout(SUNXI_HWSPINLOCKID_CPUIDLE, + ARISC_SPINLOCK_TIMEOUT, &gic_cpucfg_lock, &flags)) + printk(KERN_WARNING "%s,%d timeout\n", __func__, __LINE__); + } else +#endif + write_lock_irqsave(&cpu_ahb_lock, flags); + + sunxi_smc_writel(val, reg); + +#if (defined CONFIG_ARM_SUN8IW6_CPUIDLE) + if (hwlock_initd_flg) + arisc_hwspin_unlock(SUNXI_HWSPINLOCKID_CPUIDLE, + &gic_cpucfg_lock, &flags); + else +#endif + write_unlock_irqrestore(&cpu_ahb_lock, flags); +} +EXPORT_SYMBOL(cpu_cfg_writel); + +u32 cpu_gic_readl(void __iomem *reg) +{ + u32 ret; + unsigned long flags; + +#if (defined CONFIG_ARM_SUN8IW6_CPUIDLE) + if (hwlock_initd_flg) { + if (arisc_hwspin_lock_timeout(SUNXI_HWSPINLOCKID_CPUIDLE, + ARISC_SPINLOCK_TIMEOUT, &gic_cpucfg_lock, &flags)) + printk(KERN_WARNING "%s,%d timeout\n", __func__, __LINE__); + } else +#endif + read_lock_irqsave(&cpu_ahb_lock, flags); + + ret = readl(reg); + +#if (defined CONFIG_ARM_SUN8IW6_CPUIDLE) + if (hwlock_initd_flg) + arisc_hwspin_unlock(SUNXI_HWSPINLOCKID_CPUIDLE, + &gic_cpucfg_lock, &flags); + else +#endif + read_unlock_irqrestore(&cpu_ahb_lock, flags); + + return ret; +} +EXPORT_SYMBOL(cpu_gic_readl); + +void cpu_gic_writel(u32 val, void __iomem *reg) +{ + unsigned long flags; + +#if (defined CONFIG_ARM_SUN8IW6_CPUIDLE) + if (hwlock_initd_flg) { + if (arisc_hwspin_lock_timeout(SUNXI_HWSPINLOCKID_CPUIDLE, + ARISC_SPINLOCK_TIMEOUT, &gic_cpucfg_lock, &flags)) + printk(KERN_WARNING "%s,%d timeout\n", __func__, __LINE__); + } else +#endif + read_lock_irqsave(&cpu_ahb_lock, flags); + + writel(val, reg); + +#if (defined CONFIG_ARM_SUN8IW6_CPUIDLE) + if (hwlock_initd_flg) + arisc_hwspin_unlock(SUNXI_HWSPINLOCKID_CPUIDLE, + &gic_cpucfg_lock, &flags); + else +#endif + read_unlock_irqrestore(&cpu_ahb_lock, flags); +} +EXPORT_SYMBOL(cpu_gic_writel); + +#ifdef CONFIG_GIC_NON_BANKED +static void __iomem *gic_get_percpu_base(union gic_base *base) +{ + return raw_cpu_read(*base->percpu_base); +} + +static void __iomem *gic_get_common_base(union gic_base *base) +{ + return base->common_base; +} + +static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) +{ + return data->get_base(&data->dist_base); +} + +static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) +{ + return data->get_base(&data->cpu_base); +} + +static inline void gic_set_base_accessor(struct gic_chip_data *data, + void __iomem *(*f)(union gic_base *)) +{ + data->get_base = f; +} +#else +#define gic_data_dist_base(d) ((d)->dist_base.common_base) +#define gic_data_cpu_base(d) ((d)->cpu_base.common_base) +#define gic_set_base_accessor(d, f) +#endif + +static inline void __iomem *gic_dist_base(struct irq_data *d) +{ + struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); + return gic_data_dist_base(gic_data); +} + +static inline void __iomem *gic_cpu_base(struct irq_data *d) +{ + struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); + return gic_data_cpu_base(gic_data); +} + +static inline unsigned int gic_irq(struct irq_data *d) +{ + return d->hwirq; +} + +static inline bool cascading_gic_irq(struct irq_data *d) +{ + void *data = irq_data_get_irq_handler_data(d); + + /* + * If handler_data is set, this is a cascading interrupt, and + * it cannot possibly be forwarded. + */ + return data != NULL; +} + +/* + * Routines to acknowledge, disable and enable interrupts + */ +static void gic_poke_irq(struct irq_data *d, u32 offset) +{ + u32 mask = 1 << (gic_irq(d) % 32); + cpu_gic_writel(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); +} + +static int gic_peek_irq(struct irq_data *d, u32 offset) +{ + u32 mask = 1 << (gic_irq(d) % 32); + return !!(cpu_gic_readl(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask); +} + +static void gic_mask_irq(struct irq_data *d) +{ + gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); +} + +static void gic_eoimode1_mask_irq(struct irq_data *d) +{ + gic_mask_irq(d); + /* + * When masking a forwarded interrupt, make sure it is + * deactivated as well. + * + * This ensures that an interrupt that is getting + * disabled/masked will not get "stuck", because there is + * noone to deactivate it (guest is being terminated). + */ + if (irqd_is_forwarded_to_vcpu(d)) + gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR); +} + +static void gic_unmask_irq(struct irq_data *d) +{ + gic_poke_irq(d, GIC_DIST_ENABLE_SET); +} + +#ifdef CONFIG_SUNXI_GIC_ACCESS_SS +static unsigned int get_irqnr_from_active(unsigned int cpu) +{ + int i = 0, found = 0; + unsigned int state, irq_active; + unsigned int check_reg_num; + if (cpu) + check_reg_num = 1; + else + check_reg_num = 5; + + for (i = 0; i < check_reg_num; i++) { + state = readl_relaxed(gic_data_dist_base(&gic_data[0]) + GIC_DIST_ACTIVE_SET + i*4); + + if (state) { + irq_active = ffs(state); + irq_active = irq_active - 1 + i*32; + found = 1; + break; + } + } + if (found) + return irq_active; + else + return 0x3ff; +} + +static void check_irq_active_after_eoi(unsigned int cpu, unsigned int irqnr) +{ + unsigned int irqactive; + + while (1) { + irqactive = get_irqnr_from_active(cpu); + if (irqnr == irqactive) { + writel_relaxed(irqnr, gic_data_cpu_base(&gic_data[0]) + GIC_CPU_EOI); + } else + break; + } +} +extern void sun8i_write_dword(unsigned int val1, + unsigned int val2, unsigned int reg); +#endif + +static void gic_eoi_irq(struct irq_data *d) +{ + cpu_gic_writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); + +#ifdef CONFIG_SUNXI_GIC_ACCESS_SS + check_irq_active_after_eoi(raw_smp_processor_id(), gic_irq(d)); +#endif +} + +static void gic_eoimode1_eoi_irq(struct irq_data *d) +{ + /* Do not deactivate an IRQ forwarded to a vcpu. */ + if (irqd_is_forwarded_to_vcpu(d)) + return; + + cpu_gic_writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE); +} + +static int gic_irq_set_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, bool val) +{ + u32 reg; + + switch (which) { + case IRQCHIP_STATE_PENDING: + reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR; + break; + + case IRQCHIP_STATE_ACTIVE: + reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR; + break; + + case IRQCHIP_STATE_MASKED: + reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; + break; + + default: + return -EINVAL; + } + + gic_poke_irq(d, reg); + return 0; +} + +static int gic_irq_get_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, bool *val) +{ + switch (which) { + case IRQCHIP_STATE_PENDING: + *val = gic_peek_irq(d, GIC_DIST_PENDING_SET); + break; + + case IRQCHIP_STATE_ACTIVE: + *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET); + break; + + case IRQCHIP_STATE_MASKED: + *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); + break; + + default: + return -EINVAL; + } + + return 0; +} + +static int gic_set_type(struct irq_data *d, unsigned int type) +{ + void __iomem *base = gic_dist_base(d); + unsigned int gicirq = gic_irq(d); + + /* Interrupt configuration for SGIs can't be changed */ + if (gicirq < 16) + return -EINVAL; + + /* SPIs have restrictions on the supported types */ + if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && + type != IRQ_TYPE_EDGE_RISING) + return -EINVAL; + + return gic_configure_irq(gicirq, type, base, NULL); +} + +static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) +{ + /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ + if (cascading_gic_irq(d)) + return -EINVAL; + + if (vcpu) + irqd_set_forwarded_to_vcpu(d); + else + irqd_clr_forwarded_to_vcpu(d); + return 0; +} + +#ifdef CONFIG_SMP +static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, + bool force) +{ + void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); + unsigned int cpu, shift = (gic_irq(d) % 4) * 8; + u32 val, mask, bit; + unsigned long flags; + + if (!force) + cpu = cpumask_any_and(mask_val, cpu_online_mask); + else + cpu = cpumask_first(mask_val); + + if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) + return -EINVAL; + + raw_spin_lock_irqsave(&irq_controller_lock, flags); + mask = 0xff << shift; + bit = gic_cpu_map[cpu] << shift; + val = cpu_gic_readl(reg) & ~mask; + cpu_gic_writel(val | bit, reg); + raw_spin_unlock_irqrestore(&irq_controller_lock, flags); + + return IRQ_SET_MASK_OK; +} +#endif + +#ifdef CONFIG_SUNXI_GIC_ACCESS_SS +static DEFINE_RAW_SPINLOCK(irq_ipi_lock); + +unsigned int last_ipi_cache[CONFIG_NR_CPUS][CONFIG_NR_CPUS]; +u64 last_timer_stamp[CONFIG_NR_CPUS]; + +static void save_last_ipi(unsigned int src_cpu, + unsigned int dst_cpu, unsigned int ipi) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&irq_ipi_lock, flags); + last_ipi_cache[src_cpu][dst_cpu] = 0x55aa0000 | (ipi & 0x0000ffff); + dsb(); + raw_spin_unlock_irqrestore(&irq_ipi_lock, flags); +} + +static int match_ack_last_ipi(unsigned int dst_cpu, unsigned int ipi) +{ + int i, found = 0; + unsigned long flags = 0; + + raw_spin_lock_irqsave(&irq_ipi_lock, flags); + for (i = 0; i < CONFIG_NR_CPUS; i++) { + if ((last_ipi_cache[i][dst_cpu] & 0xffff0000) == 0x55aa0000 + && (last_ipi_cache[i][dst_cpu] & 0x0000ffff) + == (ipi & 0x0000ffff)) { + last_ipi_cache[i][dst_cpu] = 0; + found = 1; + break; + } + } + + dsb(); + + raw_spin_unlock_irqrestore(&irq_ipi_lock, flags); + return found; +} + +static void save_last_timer_stamp(unsigned int cpu) +{ + last_timer_stamp[cpu] = cpu_clock(cpu); +} + +void dump_gic_stats(void) +{ + int i, j; + + for (i = 0; i < CONFIG_NR_CPUS; i++) { + pr_debug("CPU%d last_IPI:", i); + for (j = 0; j < CONFIG_NR_CPUS; j++) + pr_debug(" 0x%x", last_ipi_cache[i][j]); + pr_debug("\n"); + } + + for (i = 0; i < CONFIG_NR_CPUS; i++) + pr_debug("CPU%d last_time_stamp:%llu\n", i, + last_timer_stamp[i]); +} +#endif + +static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) +{ + u32 irqstat, irqnr; +#ifdef CONFIG_SUNXI_GIC_ACCESS_SS + u32 irqactive, cpu; +#endif + struct gic_chip_data *gic = &gic_data[0]; + void __iomem *cpu_base = gic_data_cpu_base(gic); + + do { + irqstat = cpu_gic_readl(cpu_base + GIC_CPU_INTACK); + irqnr = irqstat & GICC_IAR_INT_ID_MASK; +#ifdef CONFIG_SUNXI_GIC_ACCESS_SS + cpu = raw_smp_processor_id(); + irqactive = get_irqnr_from_active(cpu); + if (irqnr != irqactive) { + if (irqnr >= 1021) + irqnr = irqactive; + } +#endif + + if (likely(irqnr > 15 && irqnr < 1021)) { + if (static_key_true(&supports_deactivate)) + cpu_gic_writel(irqstat, cpu_base + GIC_CPU_EOI); +#ifdef CONFIG_SUNXI_GIC_ACCESS_SS + if (irqnr == 29) + save_last_timer_stamp(cpu); +#endif + handle_domain_irq(gic->domain, irqnr, regs); + continue; + } + if (irqnr < 16) { + cpu_gic_writel(irqstat, cpu_base + GIC_CPU_EOI); +#ifdef CONFIG_SUNXI_GIC_ACCESS_SS + check_irq_active_after_eoi(raw_smp_processor_id(), irqnr); +#endif + if (static_key_true(&supports_deactivate)) + cpu_gic_writel(irqstat, cpu_base + GIC_CPU_DEACTIVATE); +#ifdef CONFIG_SMP + /* + * Ensure any shared data written by the CPU sending + * the IPI is read after we've read the ACK register + * on the GIC. + * + * Pairs with the write barrier in gic_raise_softirq + */ +#ifdef CONFIG_SUNXI_GIC_ACCESS_SS + if (match_ack_last_ipi(raw_smp_processor_id(), irqnr)) { + smp_rmb(); + handle_IPI(irqnr, regs); + } else { +#define LOCAL_IPI_RESCHEDULE 2 +#define LOCAL_IPI_CALL_FUNC_SINGLE 4 +#define LOCAL_IPI_CALL_FUNC 3 + if ((irqnr == LOCAL_IPI_RESCHEDULE) + || (irqnr == LOCAL_IPI_CALL_FUNC_SINGLE) + || (irqnr == LOCAL_IPI_CALL_FUNC)) { + smp_rmb(); + handle_IPI(irqnr, regs); + } + } +#else + smp_rmb(); + handle_IPI(irqnr, regs); +#endif +#endif + continue; + } + break; + } while (1); +} + +static void gic_handle_cascade_irq(struct irq_desc *desc) +{ + struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned int cascade_irq, gic_irq; + unsigned long status; + + chained_irq_enter(chip, desc); + + raw_spin_lock(&irq_controller_lock); + status = cpu_gic_readl(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); + raw_spin_unlock(&irq_controller_lock); + + gic_irq = (status & GICC_IAR_INT_ID_MASK); + if (gic_irq == GICC_INT_SPURIOUS) + goto out; + + cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); + if (unlikely(gic_irq < 32 || gic_irq > 1020)) + handle_bad_irq(desc); + else + generic_handle_irq(cascade_irq); + + out: + chained_irq_exit(chip, desc); +} + +static struct irq_chip gic_chip = { + .name = "GIC", + .irq_mask = gic_mask_irq, + .irq_unmask = gic_unmask_irq, + .irq_eoi = gic_eoi_irq, + .irq_set_type = gic_set_type, +#ifdef CONFIG_SMP + .irq_set_affinity = gic_set_affinity, +#endif + .irq_get_irqchip_state = gic_irq_get_irqchip_state, + .irq_set_irqchip_state = gic_irq_set_irqchip_state, + .flags = IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_MASK_ON_SUSPEND, +}; + +static struct irq_chip gic_eoimode1_chip = { + .name = "GICv2", + .irq_mask = gic_eoimode1_mask_irq, + .irq_unmask = gic_unmask_irq, + .irq_eoi = gic_eoimode1_eoi_irq, + .irq_set_type = gic_set_type, +#ifdef CONFIG_SMP + .irq_set_affinity = gic_set_affinity, +#endif + .irq_get_irqchip_state = gic_irq_get_irqchip_state, + .irq_set_irqchip_state = gic_irq_set_irqchip_state, + .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, + .flags = IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_MASK_ON_SUSPEND, +}; + +void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) +{ + if (gic_nr >= MAX_GIC_NR) + BUG(); + irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, + &gic_data[gic_nr]); +} + +static u8 gic_get_cpumask(struct gic_chip_data *gic) +{ + void __iomem *base = gic_data_dist_base(gic); + u32 mask, i; + + for (i = mask = 0; i < 32; i += 4) { + mask = cpu_gic_readl(base + GIC_DIST_TARGET + i); + mask |= mask >> 16; + mask |= mask >> 8; + if (mask) + break; + } + + if (!mask && num_possible_cpus() > 1) + pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); + + return mask; +} + +static void gic_cpu_if_up(struct gic_chip_data *gic) +{ + void __iomem *cpu_base = gic_data_cpu_base(gic); + u32 bypass = 0; + u32 mode = 0; + + if (static_key_true(&supports_deactivate)) + mode = GIC_CPU_CTRL_EOImodeNS; + + /* + * Preserve bypass disable bits to be written back later + */ + bypass = readl(cpu_base + GIC_CPU_CTRL); + bypass &= GICC_DIS_BYPASS_MASK; + + cpu_gic_writel(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); +} + + +static void __init gic_dist_init(struct gic_chip_data *gic) +{ + unsigned int i; + u32 cpumask; + unsigned int gic_irqs = gic->gic_irqs; + void __iomem *base = gic_data_dist_base(gic); + + cpu_gic_writel(GICD_DISABLE, base + GIC_DIST_CTRL); + + /* + * Set all global interrupts to this CPU only. + */ + cpumask = gic_get_cpumask(gic); + cpumask |= cpumask << 8; + cpumask |= cpumask << 16; + for (i = 32; i < gic_irqs; i += 4) + cpu_gic_writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); + + gic_dist_config(base, gic_irqs, NULL); + + cpu_gic_writel(GICD_ENABLE, base + GIC_DIST_CTRL); +} + +static void gic_cpu_init(struct gic_chip_data *gic) +{ + void __iomem *dist_base = gic_data_dist_base(gic); + void __iomem *base = gic_data_cpu_base(gic); + unsigned int cpu_mask, cpu = smp_processor_id(); + int i; + + /* + * Setting up the CPU map is only relevant for the primary GIC + * because any nested/secondary GICs do not directly interface + * with the CPU(s). + */ + if (gic == &gic_data[0]) { + /* + * Get what the GIC says our CPU mask is. + */ + BUG_ON(cpu >= NR_GIC_CPU_IF); + cpu_mask = gic_get_cpumask(gic); + gic_cpu_map[cpu] = cpu_mask; + + /* + * Clear our mask from the other map entries in case they're + * still undefined. + */ + for (i = 0; i < NR_GIC_CPU_IF; i++) + if (i != cpu) + gic_cpu_map[i] &= ~cpu_mask; + } + + gic_cpu_config(dist_base, NULL); + + cpu_gic_writel(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); + gic_cpu_if_up(gic); +} + +int gic_cpu_if_down(unsigned int gic_nr) +{ + void __iomem *cpu_base; + u32 val = 0; + + if (gic_nr >= MAX_GIC_NR) + return -EINVAL; + + cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); + val = readl(cpu_base + GIC_CPU_CTRL); + val &= ~GICC_ENABLE; + cpu_gic_writel(val, cpu_base + GIC_CPU_CTRL); + + return 0; +} + +#ifdef CONFIG_CPU_PM +/* + * Saves the GIC distributor registers during suspend or idle. Must be called + * with interrupts disabled but before powering down the GIC. After calling + * this function, no interrupts will be delivered by the GIC, and another + * platform-specific wakeup source must be enabled. + */ +static void gic_dist_save(unsigned int gic_nr) +{ + unsigned int gic_irqs; + void __iomem *dist_base; + int i; + + if (gic_nr >= MAX_GIC_NR) + BUG(); + + gic_irqs = gic_data[gic_nr].gic_irqs; + dist_base = gic_data_dist_base(&gic_data[gic_nr]); + + if (!dist_base) + return; + + for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) + gic_data[gic_nr].saved_spi_conf[i] = + cpu_gic_readl(dist_base + GIC_DIST_CONFIG + i * 4); + + for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) + gic_data[gic_nr].saved_spi_target[i] = + cpu_gic_readl(dist_base + GIC_DIST_TARGET + i * 4); + + for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) + gic_data[gic_nr].saved_spi_enable[i] = + cpu_gic_readl(dist_base + GIC_DIST_ENABLE_SET + i * 4); + + for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) + gic_data[gic_nr].saved_spi_active[i] = + cpu_gic_readl(dist_base + GIC_DIST_ACTIVE_SET + i * 4); +} + +/* + * Restores the GIC distributor registers during resume or when coming out of + * idle. Must be called before enabling interrupts. If a level interrupt + * that occured while the GIC was suspended is still present, it will be + * handled normally, but any edge interrupts that occured will not be seen by + * the GIC and need to be handled by the platform-specific wakeup source. + */ +static void gic_dist_restore(unsigned int gic_nr) +{ + unsigned int gic_irqs; + unsigned int i; + void __iomem *dist_base; + + if (gic_nr >= MAX_GIC_NR) + BUG(); + + gic_irqs = gic_data[gic_nr].gic_irqs; + dist_base = gic_data_dist_base(&gic_data[gic_nr]); + + if (!dist_base) + return; + + cpu_gic_writel(GICD_DISABLE, dist_base + GIC_DIST_CTRL); + + for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) + cpu_gic_writel(gic_data[gic_nr].saved_spi_conf[i], + dist_base + GIC_DIST_CONFIG + i * 4); + + for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) + cpu_gic_writel(GICD_INT_DEF_PRI_X4, + dist_base + GIC_DIST_PRI + i * 4); + + for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) + cpu_gic_writel(gic_data[gic_nr].saved_spi_target[i], + dist_base + GIC_DIST_TARGET + i * 4); + + for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { + cpu_gic_writel(GICD_INT_EN_CLR_X32, + dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); + cpu_gic_writel(gic_data[gic_nr].saved_spi_enable[i], + dist_base + GIC_DIST_ENABLE_SET + i * 4); + } + + for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { + cpu_gic_writel(GICD_INT_EN_CLR_X32, + dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); + cpu_gic_writel(gic_data[gic_nr].saved_spi_active[i], + dist_base + GIC_DIST_ACTIVE_SET + i * 4); + } + + cpu_gic_writel(GICD_ENABLE, dist_base + GIC_DIST_CTRL); +} + +static void gic_cpu_save(unsigned int gic_nr) +{ + int i; + u32 *ptr; + void __iomem *dist_base; + void __iomem *cpu_base; + + if (gic_nr >= MAX_GIC_NR) + BUG(); + + dist_base = gic_data_dist_base(&gic_data[gic_nr]); + cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); + + if (!dist_base || !cpu_base) + return; + + ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); + for (i = 0; i < DIV_ROUND_UP(32, 32); i++) + ptr[i] = cpu_gic_readl(dist_base + GIC_DIST_ENABLE_SET + i * 4); + + ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_active); + for (i = 0; i < DIV_ROUND_UP(32, 32); i++) + ptr[i] = cpu_gic_readl(dist_base + GIC_DIST_ACTIVE_SET + i * 4); + + ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); + for (i = 0; i < DIV_ROUND_UP(32, 16); i++) + ptr[i] = cpu_gic_readl(dist_base + GIC_DIST_CONFIG + i * 4); + +} + +static void gic_cpu_restore(unsigned int gic_nr) +{ +#ifndef CONFIG_SUNXI_GIC_ACCESS_SS + int i; + u32 *ptr; +#endif + void __iomem *dist_base; + void __iomem *cpu_base; + + if (gic_nr >= MAX_GIC_NR) + BUG(); + + dist_base = gic_data_dist_base(&gic_data[gic_nr]); + cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); + + if (!dist_base || !cpu_base) + return; + +#ifndef CONFIG_SUNXI_GIC_ACCESS_SS + ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); + for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { + cpu_gic_writel(GICD_INT_EN_CLR_X32, + dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); + cpu_gic_writel(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); + } + + ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_active); + for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { + cpu_gic_writel(GICD_INT_EN_CLR_X32, + dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); + cpu_gic_writel(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4); + } + + ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); + for (i = 0; i < DIV_ROUND_UP(32, 16); i++) + cpu_gic_writel(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); + + for (i = 0; i < DIV_ROUND_UP(32, 4); i++) + cpu_gic_writel(GICD_INT_DEF_PRI_X4, + dist_base + GIC_DIST_PRI + i * 4); +#endif + cpu_gic_writel(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK); + gic_cpu_if_up(&gic_data[gic_nr]); +} + +static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) +{ + int i; + + for (i = 0; i < MAX_GIC_NR; i++) { +#ifdef CONFIG_GIC_NON_BANKED + /* Skip over unused GICs */ + if (!gic_data[i].get_base) + continue; +#endif + switch (cmd) { + case CPU_PM_ENTER: + gic_cpu_save(i); + break; + case CPU_PM_ENTER_FAILED: + case CPU_PM_EXIT: + gic_cpu_restore(i); + break; + case CPU_CLUSTER_PM_ENTER: + gic_dist_save(i); + break; + case CPU_CLUSTER_PM_ENTER_FAILED: + case CPU_CLUSTER_PM_EXIT: + gic_dist_restore(i); + break; + } + } + + return NOTIFY_OK; +} + +static struct notifier_block gic_notifier_block = { + .notifier_call = gic_notifier, +}; + +static void __init gic_pm_init(struct gic_chip_data *gic) +{ + gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, + sizeof(u32)); + BUG_ON(!gic->saved_ppi_enable); + + gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, + sizeof(u32)); + BUG_ON(!gic->saved_ppi_active); + + gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, + sizeof(u32)); + BUG_ON(!gic->saved_ppi_conf); + + if (gic == &gic_data[0]) + cpu_pm_register_notifier(&gic_notifier_block); +} +#else +static void __init gic_pm_init(struct gic_chip_data *gic) +{ +} +#endif + +#ifdef CONFIG_SMP +void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) +{ + int cpu; + unsigned long flags, map = 0; + + raw_spin_lock_irqsave(&irq_controller_lock, flags); + + /* Convert our logical CPU mask into a physical one. */ + for_each_cpu(cpu, mask) + map |= gic_cpu_map[cpu]; + +#ifdef CONFIG_SUNXI_GIC_ACCESS_SS + save_last_ipi(raw_smp_processor_id(), cpu, irq); +#endif + /* + * Ensure that stores to Normal memory are visible to the + * other CPUs before they observe us issuing the IPI. + */ + dmb(ishst); + + /* this always happens on GIC0 */ +#ifdef CONFIG_SUNXI_GIC_ACCESS_SS + sun8i_write_dword(0, map << 16 | irq, + (unsigned int)(gic_data_dist_base(&gic_data[0]) + + GIC_DIST_SOFTINT - 4)); + sun8i_write_dword(0, map << 16 | irq, + (unsigned int)(gic_data_dist_base(&gic_data[0]) + + GIC_DIST_SOFTINT - 4)); +#else + cpu_gic_writel(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); +#endif + + raw_spin_unlock_irqrestore(&irq_controller_lock, flags); +} +#endif + +#ifdef CONFIG_BL_SWITCHER +/* + * gic_send_sgi - send a SGI directly to given CPU interface number + * + * cpu_id: the ID for the destination CPU interface + * irq: the IPI number to send a SGI for + */ +void gic_send_sgi(unsigned int cpu_id, unsigned int irq) +{ + BUG_ON(cpu_id >= NR_GIC_CPU_IF); + cpu_id = 1 << cpu_id; + /* this always happens on GIC0 */ + cpu_gic_writel((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); +} + +/* + * gic_get_cpu_id - get the CPU interface ID for the specified CPU + * + * @cpu: the logical CPU number to get the GIC ID for. + * + * Return the CPU interface ID for the given logical CPU number, + * or -1 if the CPU number is too large or the interface ID is + * unknown (more than one bit set). + */ +int gic_get_cpu_id(unsigned int cpu) +{ + unsigned int cpu_bit; + + if (cpu >= NR_GIC_CPU_IF) + return -1; + cpu_bit = gic_cpu_map[cpu]; + if (cpu_bit & (cpu_bit - 1)) + return -1; + return __ffs(cpu_bit); +} + +/* + * gic_migrate_target - migrate IRQs to another CPU interface + * + * @new_cpu_id: the CPU target ID to migrate IRQs to + * + * Migrate all peripheral interrupts with a target matching the current CPU + * to the interface corresponding to @new_cpu_id. The CPU interface mapping + * is also updated. Targets to other CPU interfaces are unchanged. + * This must be called with IRQs locally disabled. + */ +void gic_migrate_target(unsigned int new_cpu_id) +{ + unsigned int cur_cpu_id, gic_irqs, gic_nr = 0; + void __iomem *dist_base; + int i, ror_val, cpu = smp_processor_id(); + u32 val, cur_target_mask, active_mask; + + if (gic_nr >= MAX_GIC_NR) + BUG(); + + dist_base = gic_data_dist_base(&gic_data[gic_nr]); + if (!dist_base) + return; + gic_irqs = gic_data[gic_nr].gic_irqs; + + cur_cpu_id = __ffs(gic_cpu_map[cpu]); + cur_target_mask = 0x01010101 << cur_cpu_id; + ror_val = (cur_cpu_id - new_cpu_id) & 31; + + raw_spin_lock(&irq_controller_lock); + + /* Update the target interface for this logical CPU */ + gic_cpu_map[cpu] = 1 << new_cpu_id; + + /* + * Find all the peripheral interrupts targetting the current + * CPU interface and migrate them to the new CPU interface. + * We skip DIST_TARGET 0 to 7 as they are read-only. + */ + for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) { + val = cpu_gic_readl(dist_base + GIC_DIST_TARGET + i * 4); + active_mask = val & cur_target_mask; + if (active_mask) { + val &= ~active_mask; + val |= ror32(active_mask, ror_val); + cpu_gic_writel(val, dist_base + GIC_DIST_TARGET + i*4); + } + } + + raw_spin_unlock(&irq_controller_lock); + + /* + * Now let's migrate and clear any potential SGIs that might be + * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET + * is a banked register, we can only forward the SGI using + * GIC_DIST_SOFTINT. The original SGI source is lost but Linux + * doesn't use that information anyway. + * + * For the same reason we do not adjust SGI source information + * for previously sent SGIs by us to other CPUs either. + */ + for (i = 0; i < 16; i += 4) { + int j; + val = cpu_gic_readl(dist_base + GIC_DIST_SGI_PENDING_SET + i); + if (!val) + continue; + cpu_gic_writel(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); + for (j = i; j < i + 4; j++) { + if (val & 0xff) + cpu_gic_writel((1 << (new_cpu_id + 16)) | j, + dist_base + GIC_DIST_SOFTINT); + val >>= 8; + } + } +} + +/* + * gic_get_sgir_physaddr - get the physical address for the SGI register + * + * REturn the physical address of the SGI register to be used + * by some early assembly code when the kernel is not yet available. + */ +static unsigned long gic_dist_physaddr; + +unsigned long gic_get_sgir_physaddr(void) +{ + if (!gic_dist_physaddr) + return 0; + return gic_dist_physaddr + GIC_DIST_SOFTINT; +} + +void __init gic_init_physaddr(struct device_node *node) +{ + struct resource res; + if (of_address_to_resource(node, 0, &res) == 0) { + gic_dist_physaddr = res.start; + pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); + } +} + +#else +#define gic_init_physaddr(node) do { } while (0) +#endif + +static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, + irq_hw_number_t hw) +{ + struct irq_chip *chip = &gic_chip; + + if (static_key_true(&supports_deactivate)) { + if (d->host_data == (void *)&gic_data[0]) + chip = &gic_eoimode1_chip; + } + + if (hw < 32) { + irq_set_percpu_devid(irq); + irq_domain_set_info(d, irq, hw, chip, d->host_data, + handle_percpu_devid_irq, NULL, NULL); + irq_set_status_flags(irq, IRQ_NOAUTOEN); + } else { + irq_domain_set_info(d, irq, hw, chip, d->host_data, + handle_fasteoi_irq, NULL, NULL); + irq_set_probe(irq); + } + return 0; +} + +static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq) +{ +} + +static int gic_irq_domain_translate(struct irq_domain *d, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + if (is_of_node(fwspec->fwnode)) { + if (fwspec->param_count < 3) + return -EINVAL; + + /* Get the interrupt number and add 16 to skip over SGIs */ + *hwirq = fwspec->param[1] + 16; + + /* + * For SPIs, we need to add 16 more to get the GIC irq + * ID number + */ + if (!fwspec->param[0]) + *hwirq += 16; + + *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; + return 0; + } + + if (fwspec->fwnode->type == FWNODE_IRQCHIP) { + if (fwspec->param_count != 2) + return -EINVAL; + + *hwirq = fwspec->param[0]; + *type = fwspec->param[1]; + return 0; + } + + return -EINVAL; +} + +#ifdef CONFIG_SMP +int gic_secondary_init(struct notifier_block *nfb, unsigned long action, + void *hcpu) +{ + if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) + gic_cpu_init(&gic_data[0]); + return NOTIFY_OK; +} + +/* + * Notifier for enabling the GIC CPU interface. Set an arbitrarily high + * priority because the GIC needs to be up before the ARM generic timers. + */ +static struct notifier_block gic_cpu_notifier = { + .notifier_call = gic_secondary_init, + .priority = 100, +}; +#endif + +static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *arg) +{ + int i, ret; + irq_hw_number_t hwirq; + unsigned int type = IRQ_TYPE_NONE; + struct irq_fwspec *fwspec = arg; + + ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); + if (ret) + return ret; + + for (i = 0; i < nr_irqs; i++) + gic_irq_domain_map(domain, virq + i, hwirq + i); + + return 0; +} + +static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = { + .translate = gic_irq_domain_translate, + .alloc = gic_irq_domain_alloc, + .free = irq_domain_free_irqs_top, +}; + +static const struct irq_domain_ops gic_irq_domain_ops = { + .map = gic_irq_domain_map, + .unmap = gic_irq_domain_unmap, +}; + +static void __init __gic_init_bases(unsigned int gic_nr, int irq_start, + void __iomem *dist_base, void __iomem *cpu_base, + u32 percpu_offset, struct fwnode_handle *handle) +{ + irq_hw_number_t hwirq_base; + struct gic_chip_data *gic; + int gic_irqs, irq_base, i; + + BUG_ON(gic_nr >= MAX_GIC_NR); +#ifdef CONFIG_SUNXI_GIC_ACCESS_SS + memset(last_ipi_cache, 0x0, sizeof(last_ipi_cache)); +#endif + gic_check_cpu_features(); + + gic = &gic_data[gic_nr]; +#ifdef CONFIG_GIC_NON_BANKED + if (percpu_offset) { /* Frankein-GIC without banked registers... */ + unsigned int cpu; + + gic->dist_base.percpu_base = alloc_percpu(void __iomem *); + gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); + if (WARN_ON(!gic->dist_base.percpu_base || + !gic->cpu_base.percpu_base)) { + free_percpu(gic->dist_base.percpu_base); + free_percpu(gic->cpu_base.percpu_base); + return; + } + + for_each_possible_cpu(cpu) { + u32 mpidr = cpu_logical_map(cpu); + u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); + unsigned long offset = percpu_offset * core_id; + *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset; + *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset; + } + + gic_set_base_accessor(gic, gic_get_percpu_base); + } else +#endif + { /* Normal, sane GIC... */ + WARN(percpu_offset, + "GIC_NON_BANKED not enabled, ignoring %08x offset!", + percpu_offset); + gic->dist_base.common_base = dist_base; + gic->cpu_base.common_base = cpu_base; + gic_set_base_accessor(gic, gic_get_common_base); + } + + /* + * Find out how many interrupts are supported. + * The GIC only supports up to 1020 interrupt sources. + */ + gic_irqs = cpu_gic_readl(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; + gic_irqs = (gic_irqs + 1) * 32; + if (gic_irqs > 1020) + gic_irqs = 1020; + gic->gic_irqs = gic_irqs; + + if (handle) { /* DT/ACPI */ + gic->domain = irq_domain_create_linear(handle, gic_irqs, + &gic_irq_domain_hierarchy_ops, + gic); + } else { /* Legacy support */ + /* + * For primary GICs, skip over SGIs. + * For secondary GICs, skip over PPIs, too. + */ + if (gic_nr == 0 && (irq_start & 31) > 0) { + hwirq_base = 16; + if (irq_start != -1) + irq_start = (irq_start & ~31) + 16; + } else { + hwirq_base = 32; + } + + gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */ + + irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, + numa_node_id()); + if (IS_ERR_VALUE(irq_base)) { + WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", + irq_start); + irq_base = irq_start; + } + + gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base, + hwirq_base, &gic_irq_domain_ops, gic); + } + + if (WARN_ON(!gic->domain)) + return; + + if (gic_nr == 0) { + /* + * Initialize the CPU interface map to all CPUs. + * It will be refined as each CPU probes its ID. + * This is only necessary for the primary GIC. + */ + for (i = 0; i < NR_GIC_CPU_IF; i++) + gic_cpu_map[i] = 0xff; +#ifdef CONFIG_SMP + set_smp_cross_call(gic_raise_softirq); + register_cpu_notifier(&gic_cpu_notifier); +#endif + set_handle_irq(gic_handle_irq); + if (static_key_true(&supports_deactivate)) + pr_info("GIC: Using split EOI/Deactivate mode\n"); + } + + gic_dist_init(gic); + gic_cpu_init(gic); + gic_pm_init(gic); +} + +void __init gic_init(unsigned int gic_nr, int irq_start, + void __iomem *dist_base, void __iomem *cpu_base) +{ + /* + * Non-DT/ACPI systems won't run a hypervisor, so let's not + * bother with these... + */ + static_key_slow_dec(&supports_deactivate); + __gic_init_bases(gic_nr, irq_start, dist_base, cpu_base, 0, NULL); +} + +#ifdef CONFIG_OF +static int gic_cnt __initdata; + +static bool gic_check_eoimode(struct device_node *node, void __iomem **base) +{ + struct resource cpuif_res; + + of_address_to_resource(node, 1, &cpuif_res); + + if (!is_hyp_mode_available()) + return false; + if (resource_size(&cpuif_res) < SZ_8K) + return false; + if (resource_size(&cpuif_res) == SZ_128K) { + u32 val_low, val_high; + + /* + * Verify that we have the first 4kB of a GIC400 + * aliased over the first 64kB by checking the + * GICC_IIDR register on both ends. + */ + val_low = cpu_gic_readl(*base + GIC_CPU_IDENT); + val_high = cpu_gic_readl(*base + GIC_CPU_IDENT + 0xf000); + if ((val_low & 0xffff0fff) != 0x0202043B || + val_low != val_high) + return false; + + /* + * Move the base up by 60kB, so that we have a 8kB + * contiguous region, which allows us to use GICC_DIR + * at its normal offset. Please pass me that bucket. + */ + *base += 0xf000; + cpuif_res.start += 0xf000; + pr_warn("GIC: Adjusting CPU interface base to %pa", + &cpuif_res.start); + } + + return true; +} + +int __init gic_of_init(struct device_node *node, struct device_node *parent) +{ + void __iomem *cpu_base; + void __iomem *dist_base; + u32 percpu_offset; + int irq; + + if (WARN_ON(!node)) + return -ENODEV; + + dist_base = of_iomap(node, 0); + WARN(!dist_base, "unable to map gic dist registers\n"); + + cpu_base = of_iomap(node, 1); + WARN(!cpu_base, "unable to map gic cpu registers\n"); + + /* + * Disable split EOI/Deactivate if either HYP is not available + * or the CPU interface is too small. + */ + if (gic_cnt == 0 && !gic_check_eoimode(node, &cpu_base)) + static_key_slow_dec(&supports_deactivate); + + if (of_property_read_u32(node, "cpu-offset", &percpu_offset)) + percpu_offset = 0; + + __gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, + &node->fwnode); + if (!gic_cnt) + gic_init_physaddr(node); + + if (parent) { + irq = irq_of_parse_and_map(node, 0); + gic_cascade_irq(gic_cnt, irq); + } + + /* + if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) + gicv2m_of_init(node, gic_data[gic_cnt].domain); + */ + + gic_cnt++; + return 0; +} +IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init); +IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init); +IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init); +IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); +IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); +IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); +IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); +IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); +IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init); + +#endif +