diff -drupN a/sound/soc/sunxi/sun8iw19-codec.h b/sound/soc/sunxi/sun8iw19-codec.h --- a/sound/soc/sunxi/sun8iw19-codec.h 1970-01-01 03:00:00.000000000 +0300 +++ b/sound/soc/sunxi/sun8iw19-codec.h 2022-06-12 05:28:14.000000000 +0300 @@ -0,0 +1,343 @@ +/* + * sound\soc\sunxi\sun8iw19-codec.h + * (C) Copyright 2014-2019 + * allwinner Technology Co., Ltd. + * yumingfeng + * + * some simple description for this code + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + */ +#ifndef _SUN8IW19_CODEC_H +#define _SUN8IW19_CODEC_H + +#include "sun8iw19-pcm.h" +#include "sun8iw19-daudio.h" + +#define SUNXI_DAC_DPC 0x00 +#define SUNXI_DAC_FIFOC 0x10 +#define SUNXI_DAC_FIFOS 0x14 +#define SUNXI_DAC_TXDATA 0X20 +#define SUNXI_DAC_CNT 0x24 +#define SUNXI_DAC_DG 0x28 + +#define SUNXI_ADC_FIFOC 0x30 +#define SUNXI_ADC_FIFOS 0x38 +#define SUNXI_ADC_RXDATA 0x40 +#define SUNXI_ADC_CNT 0x44 +#define SUNXI_ADC_DG 0x4C + +#define SUNXI_DAC_DAP_CTL 0xF0 +#define SUNXI_ADC_DAP_CTL 0xF8 + +#define SUNXI_DAC_DRC_HHPFC 0x100 +#define SUNXI_DAC_DRC_LHPFC 0x104 +#define SUNXI_DAC_DRC_CTRL 0x108 +#define SUNXI_DAC_DRC_LPFHAT 0x10C +#define SUNXI_DAC_DRC_LPFLAT 0x110 +#define SUNXI_DAC_DRC_RPFHAT 0x114 +#define SUNXI_DAC_DRC_RPFLAT 0x118 +#define SUNXI_DAC_DRC_LPFHRT 0x11C +#define SUNXI_DAC_DRC_LPFLRT 0x120 +#define SUNXI_DAC_DRC_RPFHRT 0x124 +#define SUNXI_DAC_DRC_RPFLRT 0x128 +#define SUNXI_DAC_DRC_LRMSHAT 0x12C +#define SUNXI_DAC_DRC_LRMSLAT 0x130 +#define SUNXI_DAC_DRC_RRMSHAT 0x134 +#define SUNXI_DAC_DRC_RRMSLAT 0x138 +#define SUNXI_DAC_DRC_HCT 0x13C +#define SUNXI_DAC_DRC_LCT 0x140 +#define SUNXI_DAC_DRC_HKC 0x144 +#define SUNXI_DAC_DRC_LKC 0x148 +#define SUNXI_DAC_DRC_HOPC 0x14C +#define SUNXI_DAC_DRC_LOPC 0x150 +#define SUNXI_DAC_DRC_HLT 0x154 +#define SUNXI_DAC_DRC_LLT 0x158 +#define SUNXI_DAC_DRC_HKI 0x15C +#define SUNXI_DAC_DRC_LKI 0x160 +#define SUNXI_DAC_DRC_HOPL 0x164 +#define SUNXI_DAC_DRC_LOPL 0x168 +#define SUNXI_DAC_DRC_HET 0x16C +#define SUNXI_DAC_DRC_LET 0x170 +#define SUNXI_DAC_DRC_HKE 0x174 +#define SUNXI_DAC_DRC_LKE 0x178 +#define SUNXI_DAC_DRC_HOPE 0x17C +#define SUNXI_DAC_DRC_LOPE 0x180 +#define SUNXI_DAC_DRC_HKN 0x184 +#define SUNXI_DAC_DRC_LKN 0x188 +#define SUNXI_DAC_DRC_SFHAT 0x18C +#define SUNXI_DAC_DRC_SFLAT 0x190 +#define SUNXI_DAC_DRC_SFHRT 0x194 +#define SUNXI_DAC_DRC_SFLRT 0x198 +#define SUNXI_DAC_DRC_MXGHS 0x19C +#define SUNXI_DAC_DRC_MXGLS 0x1A0 +#define SUNXI_DAC_DRC_MNGHS 0x1A4 +#define SUNXI_DAC_DRC_MNGLS 0x1A8 +#define SUNXI_DAC_DRC_EPSHC 0x1AC +#define SUNXI_DAC_DRC_EPSLC 0x1B0 +#define SUNXI_DAC_DRC_OPT 0x1B4 +#define SUNXI_DAC_DRC_HPFHGAIN 0x1B8 +#define SUNXI_DAC_DRC_HPFLGAIN 0x1BC + +#define SUNXI_ADC_DRC_HHPFC 0x200 +#define SUNXI_ADC_DRC_LHPFC 0x204 +#define SUNXI_ADC_DRC_CTRL 0x208 +#define SUNXI_ADC_DRC_LPFHAT 0x20C +#define SUNXI_ADC_DRC_LPFLAT 0x210 +#define SUNXI_ADC_DRC_RPFHAT 0x214 +#define SUNXI_ADC_DRC_RPFLAT 0x218 +#define SUNXI_ADC_DRC_LPFHRT 0x21C +#define SUNXI_ADC_DRC_LPFLRT 0x220 +#define SUNXI_ADC_DRC_RPFHRT 0x224 +#define SUNXI_ADC_DRC_RPFLRT 0x228 +#define SUNXI_ADC_DRC_LRMSHAT 0x22C +#define SUNXI_ADC_DRC_LRMSLAT 0x230 +#define SUNXI_ADC_DRC_HCT 0x23C +#define SUNXI_ADC_DRC_LCT 0x240 +#define SUNXI_ADC_DRC_HKC 0x244 +#define SUNXI_ADC_DRC_LKC 0x248 +#define SUNXI_ADC_DRC_HOPC 0x24C +#define SUNXI_ADC_DRC_LOPC 0x250 +#define SUNXI_ADC_DRC_HLT 0x254 +#define SUNXI_ADC_DRC_LLT 0x258 +#define SUNXI_ADC_DRC_HKI 0x25C +#define SUNXI_ADC_DRC_LKI 0x260 +#define SUNXI_ADC_DRC_HOPL 0x264 +#define SUNXI_ADC_DRC_LOPL 0x268 +#define SUNXI_ADC_DRC_HET 0x26C +#define SUNXI_ADC_DRC_LET 0x270 +#define SUNXI_ADC_DRC_HKE 0x274 +#define SUNXI_ADC_DRC_LKE 0x278 +#define SUNXI_ADC_DRC_HOPE 0x27C +#define SUNXI_ADC_DRC_LOPE 0x280 +#define SUNXI_ADC_DRC_HKN 0x284 +#define SUNXI_ADC_DRC_LKN 0x288 +#define SUNXI_ADC_DRC_SFHAT 0x28C +#define SUNXI_ADC_DRC_SFLAT 0x290 +#define SUNXI_ADC_DRC_SFHRT 0x294 +#define SUNXI_ADC_DRC_SFLRT 0x298 +#define SUNXI_ADC_DRC_MXGHS 0x29C +#define SUNXI_ADC_DRC_MXGLS 0x2A0 +#define SUNXI_ADC_DRC_MNGHS 0x2A4 +#define SUNXI_ADC_DRC_MNGLS 0x2A8 +#define SUNXI_ADC_DRC_EPSHC 0x2AC +#define SUNXI_ADC_DRC_EPSLC 0x2B0 +#define SUNXI_ADC_DRC_OPT 0x2B4 +#define SUNXI_ADC_DRC_HPFHGAIN 0x2B8 +#define SUNXI_ADC_DRC_HPFLGAIN 0x2BC + +#define SUNXI_AC_VERSION 0x2C0 + +/* Analog register base - Digital register base */ +/*SUNXI_PR_CFG is to tear the acreg and dcreg, it is of no real meaning*/ +#define SUNXI_PR_CFG (0x300) +#define SUNXI_ADCL_ANA_CTL (SUNXI_PR_CFG + 0x00) +#define SUNXI_DAC_ANA_CTL (SUNXI_PR_CFG + 0x10) +#define SUNXI_MICBIAS_ANA_CTL (SUNXI_PR_CFG + 0x18) +#define SUNXI_BIAS_ANA_CTL (SUNXI_PR_CFG + 0x20) + +/* SUNXI_DAC_DPC:0x00 */ +#define EN_DAC 31 +#define MODQU 25 +#define DWA_EN 24 +#define HPF_EN 18 +#define DVOL 12 +#define DAC_HUB_EN 0 + +/* SUNXI_DAC_FIFOC:0x10 */ +#define DAC_FS 29 +#define FIR_VER 28 +#define SEND_LASAT 26 +#define FIFO_MODE 24 +#define DAC_DRQ_CLR_CNT 21 +#define TX_TRIG_LEVEL 8 +#define DAC_MONO_EN 6 +#define TX_SAMPLE_BITS 5 +#define DAC_DRQ_EN 4 +#define DAC_IRQ_EN 3 +#define FIFO_UNDERRUN_IRQ_EN 2 +#define FIFO_OVERRUN_IRQ_EN 1 +#define FIFO_FLUSH 0 + +/* SUNXI_DAC_FIFOS:0x14 */ +#define TX_EMPTY 23 +#define DAC_TXE_CNT 8 +#define DAC_TXE_INT 3 +#define DAC_TXU_INT 2 +#define DAC_TXO_INT 1 + +/* SUNXI_DAC_DG:0x28 */ +#define DAC_MODU_SEL 11 +#define DAC_PATTERN_SEL 9 +#define DAC_CODEC_CLK_SEL 8 +#define DAC_SWP 6 +#define ADDA_LOOP_MODE 0 + +/* SUNXI_ADC_FIFOC:0x30 */ +#define ADC_FS 29 +#define EN_AD 28 +#define ADCFDT 26 +#define ADCDFEN 25 +#define RX_FIFO_MODE 24 +#define RX_SAMPLE_BITS 16 +#define ADC_CHAN_SEL 12 +#define RX_FIFO_TRG_LEVEL 4 +#define ADC_DRQ_EN 3 +#define ADC_IRQ_EN 2 +#define ADC_OVERRUN_IRQ_EN 1 +#define ADC_FIFO_FLUSH 0 + +/* SUNXI_ADC_FIFOS:0x38 */ +#define RXA 23 +#define ADC_RXA_CNT 8 +#define ADC_RXA_INT 3 +#define ADC_RXO_INT 1 + +/* SUNXI_ADC_DG:0x4C */ +#define AD_SWP 24 + +/* SUNXI_DAC_DAP_CTL:0xf0 */ +#define DDAP_EN 31 +#define DDAP_DRC_EN 29 +#define DDAP_HPF_EN 28 + +/* SUNXI_ADC_DAP_CTL:0xf8 */ +#define ADC_DAP0_EN 31 +#define ADC_DRC0_EN 29 +#define ADC_HPF0_EN 28 + +/* SUNXI_DAC_DRC_HHPFC : 0x100*/ +#define DAC_HHPF_CONF 0 + +/* SUNXI_DAC_DRC_LHPFC : 0x104*/ +#define DAC_LHPF_CONF 0 + +/* SUNXI_DAC_DRC_CTRL : 0x108*/ +#define DAC_DRC_DELAY_OUT_STATE 15 +#define DAC_DRC_SIGNAL_DELAY 8 +#define DAC_DRC_DELAY_BUF_EN 7 +#define DAC_DRC_GAIN_MAX_EN 6 +#define DAC_DRC_GAIN_MIN_EN 5 +#define DAC_DRC_NOISE_DET_EN 4 +#define DAC_DRC_SIGNAL_SEL 3 +#define DAC_DRC_DELAY_EN 2 +#define DAC_DRC_LT_EN 1 +#define DAC_DRC_ET_EN 0 + +/* SUNXI_ADC_DRC_HHPFC : 0x200*/ +#define ADC_HHPF_CONF 0 + +/* SUNXI_ADC_DRC_LHPFC : 0x204*/ +#define ADC_LHPF_CONF 0 + +/* SUNXI_ADC_DRC_CTRL : 0x208*/ +#define ADC_DRC_DELAY_OUT_STATE 15 +#define ADC_DRC_SIGNAL_DELAY 8 +#define ADC_DRC_DELAY_BUF_EN 7 +#define ADC_DRC_GAIN_MAX_EN 6 +#define ADC_DRC_GAIN_MIN_EN 5 +#define ADC_DRC_NOISE_DET_EN 4 +#define ADC_DRC_SIGNAL_SEL 3 +#define ADC_DRC_DELAY_EN 2 +#define ADC_DRC_LT_EN 1 +#define ADC_DRC_ER_EN 0 + +/* SUNXI_ADCL_ANA_CTL: SUNXI_PR_CFG + 0x00 */ +#define ADCLEN 31 +#define MIC1AMPEN 30 +#define ADC_DITHER_RESET 29 +#define LINEINLEN 23 +#define LINEINLG 22 +#define IOPLINE 20 +#define PGA_CTRL_RCM 18 +#define PGA_IN_VCM_CTRL 16 +#define PGA_GAIN_CTRL 8 +#define ADCL_IOPAAFL 6 +#define ADCLIOPSDML1 4 +#define ADCLIOPSDML2 2 +#define PGA_IOPMICL 0 + +/* SUNXI_DAC_ANA_CTL: SUNXI_PR_CFG + 0x10 */ +#define CURRENT_TEST_SELECT 23 +#define VRA2_IOPVRS 20 +#define ILINEOUTAMPS 18 +#define IOPDACS 16 +#define DACLEN 15 +#define LINEOUTL_EN 13 +#define DACLMUTE 12 +#define LINEOUTLDIFFEN 6 +#define LINEOUT_VOL 0 + +/* SUNXI_MICBIAS_ANA_CTL: SUNXI_PR_CFG + 0x18 */ +#define MMICBIASEN 7 +#define MBIASSEL 5 +#define MMICBIAS_CHOP_EN 4 +#define MMICBIAS_CHOP_CLK_SEL 2 + +/* SUNXI_BIAS_ANA_CTL: SUNXI_PR_CFG + 0x20 */ +#define AC_BIASDATA 0 + +#define CODEC_REG_LABEL(constant) {#constant, constant, 0} +#define CODEC_REG_LABEL_END {NULL, 0, 0} + +/* SUNXI_CODEC_DAP_ENABLE: Whether to use the adc/dac drc/hpf function */ +#define SUNXI_CODEC_DAP_ENABLE + +/* SUNXI_CODEC_HUB_ENABLE: Whether to use the hub mode */ +#define SUNXI_CODEC_HUB_ENABLE + +struct codec_reg_label { + const char *name; + const unsigned int address; + unsigned int value; +}; + +struct codec_hw_config { + u32 adcdrc_cfg:1; + u32 dacdrc_cfg:1; + u32 adchpf_cfg:1; + u32 dachpf_cfg:1; +}; + +struct codec_spk_config { + u32 spk_gpio; + u32 pa_msleep; + bool used; + bool pa_level; +}; + +struct sample_rate { + unsigned int samplerate; + unsigned int rate_bit; +}; + +struct sunxi_codec_info { + int codec_word_size; + struct device *dev; + struct regmap *regmap; + void __iomem *digital_base; + struct clk *pll_clk; + struct clk *module_clk; + + /* for dap function */ + u32 dac_dap_enable; + u32 adc_dap_enable; + + /* self user config params */ + u32 lineout_vol; + u32 digital_vol; + u32 main_gain; + u32 linein_gain; + + struct sunxi_dma_params playback_dma_param; + struct sunxi_dma_params capture_dma_param; + + struct codec_spk_config spk_config; + struct codec_hw_config hw_config; +}; + +#endif /* __SUN8IW19_CODEC_H */