--- linux-4.9.37/drivers/mmc/host/sdhci.h 2017-07-12 16:42:41.000000000 +0300 +++ linux-4.9.y/drivers/mmc/host/sdhci.h 2021-06-07 13:01:33.000000000 +0300 @@ -20,6 +20,8 @@ #include +#define SDHCI_GOKE_EDGE_TUNING /* enable edge tuning */ + /* * Controller registers */ @@ -84,6 +86,7 @@ #define SDHCI_CTRL_ADMA1 0x08 #define SDHCI_CTRL_ADMA32 0x10 #define SDHCI_CTRL_ADMA64 0x18 +#define SDHCI_CTRL_ADMA3 0x18 #define SDHCI_CTRL_8BITBUS 0x20 #define SDHCI_CTRL_CDTEST_INS 0x40 #define SDHCI_CTRL_CDTEST_EN 0x80 @@ -108,6 +111,7 @@ #define SDHCI_DIV_MASK_LEN 8 #define SDHCI_DIV_HI_MASK 0x300 #define SDHCI_PROG_CLOCK_MODE 0x0020 +#define SDHCI_CLOCK_PLL_EN 0x0008 #define SDHCI_CLOCK_CARD_EN 0x0004 #define SDHCI_CLOCK_INT_STABLE 0x0002 #define SDHCI_CLOCK_INT_EN 0x0001 @@ -132,6 +136,7 @@ #define SDHCI_INT_CARD_REMOVE 0x00000080 #define SDHCI_INT_CARD_INT 0x00000100 #define SDHCI_INT_RETUNE 0x00001000 +#define SDHCI_INT_CQE 0x00004000 #define SDHCI_INT_ERROR 0x00008000 #define SDHCI_INT_TIMEOUT 0x00010000 #define SDHCI_INT_CRC 0x00020000 @@ -141,14 +146,16 @@ #define SDHCI_INT_DATA_CRC 0x00200000 #define SDHCI_INT_DATA_END_BIT 0x00400000 #define SDHCI_INT_BUS_POWER 0x00800000 -#define SDHCI_INT_ACMD12ERR 0x01000000 +#define SDHCI_INT_ACMD_ERR 0x01000000 #define SDHCI_INT_ADMA_ERROR 0x02000000 #define SDHCI_INT_NORMAL_MASK 0x00007FFF #define SDHCI_INT_ERROR_MASK 0xFFFF8000 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \ - SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) + SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX | \ + SDHCI_INT_ACMD_ERR) + #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ @@ -156,7 +163,13 @@ SDHCI_INT_BLK_GAP) #define SDHCI_INT_ALL_MASK ((unsigned int)-1) -#define SDHCI_ACMD12_ERR 0x3C +#define SDHCI_AUTO_CMD_ERR 0x3C +#define SDHCI_AUTO_CMD12_NOT_EXEC 0x0001 +#define SDHCI_AUTO_CMD_TIMEOUT_ERR 0x0002 +#define SDHCI_AUTO_CMD_CRC_ERR 0x0004 +#define SDHCI_AUTO_CMD_ENDBIT_ERR 0x0008 +#define SDHCI_AUTO_CMD_INDEX_ERR 0x0010 +#define SDHCI_AUTO_CMD12_NOT_ISSUED 0x0080 #define SDHCI_HOST_CONTROL2 0x3E #define SDHCI_CTRL_UHS_MASK 0x0007 @@ -165,7 +178,7 @@ #define SDHCI_CTRL_UHS_SDR50 0x0002 #define SDHCI_CTRL_UHS_SDR104 0x0003 #define SDHCI_CTRL_UHS_DDR50 0x0004 -#define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ +#define SDHCI_CTRL_HS400 0x0007 /* Non-standard */ #define SDHCI_CTRL_VDD_180 0x0008 #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 #define SDHCI_CTRL_DRV_TYPE_B 0x0000 @@ -174,6 +187,9 @@ #define SDHCI_CTRL_DRV_TYPE_D 0x0030 #define SDHCI_CTRL_EXEC_TUNING 0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 +#define SDHCI_CTRL_HOST_VER4_ENABLE 0x1000 +#define SDHCI_CTRL_ADDRESSING_64BIT 0x2000 +#define SDHCI_CTRL_ASYNC_INT_ENABLE 0x4000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 #define SDHCI_CAPABILITIES 0x40 @@ -195,6 +211,7 @@ #define SDHCI_CAN_VDD_300 0x02000000 #define SDHCI_CAN_VDD_180 0x04000000 #define SDHCI_CAN_64BIT 0x10000000 +#define SDHCI_CAN_ASYNC_INT 0x20000000 #define SDHCI_SUPPORT_SDR50 0x00000001 #define SDHCI_SUPPORT_SDR104 0x00000002 @@ -209,6 +226,7 @@ #define SDHCI_RETUNING_MODE_SHIFT 14 #define SDHCI_CLOCK_MUL_MASK 0x00FF0000 #define SDHCI_CLOCK_MUL_SHIFT 16 +#define SDHCI_CAN_DO_ADMA3 0x08000000 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */ #define SDHCI_CAPABILITIES_1 0x44 @@ -250,6 +268,9 @@ #define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF #define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0 +#define SDHCI_ADMA3_ID_ADDR_LOW 0x78 +#define SDHCI_ADMA3_ID_ADDR_HI 0x7C + #define SDHCI_SLOT_INT_STATUS 0xFC #define SDHCI_HOST_VERSION 0xFE @@ -260,7 +281,38 @@ #define SDHCI_SPEC_100 0 #define SDHCI_SPEC_200 1 #define SDHCI_SPEC_300 2 - +#define SDHCI_SPEC_400 3 +#define SDHCI_SPEC_410 4 +#define SDHCI_SPEC_420 5 + +#define SDHCI_MSHC_CTRL 0x508 +#define SDHCI_CMD_CONFLIT_CHECK 0x01 + +#define SDHCI_AXI_MBIIU_CTRL 0x510 +#define SDHCI_GM_WR_OSRC_LMT_MASK (0x7 << 24) +#define SDHCI_GM_WR_OSRC_LMT_SEL(x) ((x) << 24) +#define SDHCI_GM_RD_OSRC_LMT_MASK (0x7 << 16) +#define SDHCI_GM_RD_OSRC_LMT_SEL(x) ((x) << 16) +#define SDHCI_UNDEFL_INCR_EN 0x1 + +#define SDHCI_EMMC_CTRL 0x52c +#define SDHCI_CARD_IS_EMMC 0x00000001 +#define SDHCI_ENH_STROBE_EN 0x00000100 + +#define SDHCI_EMMC_HW_RESET 0x534 + +#define SDHCI_AT_CTRL 0x540 +#define SDHCI_SAMPLE_EN 0x00000010 + +#define SDHCI_AT_STAT 0x544 +#define SDHCI_PHASE_SEL_MASK 0x000000ff + +#define SDHCI_MULTI_CYCLE 0x54c +#define SDHCI_FOUND_EDGE (0x1 << 11) +#define SDHCI_EDGE_DETECT_EN (0x1 << 8) +#define SDHCI_DOUT_EN_F_EDGE (0x1 << 6) +#define SDHCI_DATA_DLY_EN (0x1 << 3) +#define SDHCI_CMD_DLY_EN (0x1 << 2) /* * End of controller registers. */ @@ -273,6 +325,7 @@ */ #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024) #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12) +#define SDHCI_DMA_BOUNDARY_SIZE (0x1 << 27) /* ADMA2 32-bit DMA descriptor size */ #define SDHCI_ADMA2_32_DESC_SZ 8 @@ -298,6 +351,12 @@ /* ADMA2 64-bit DMA descriptor size */ #define SDHCI_ADMA2_64_DESC_SZ 12 +/* ADMA3 32-bit DMA descriptor size */ +#define SDHCI_ADMA3_32_DESC_SZ 8 + +/* ADMA3 64-bit DMA descriptor size */ +#define SDHCI_ADMA3_64_DESC_SZ 16 + /* * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte * aligned. @@ -312,6 +371,9 @@ #define ADMA2_TRAN_VALID 0x21 #define ADMA2_NOP_END_VALID 0x3 #define ADMA2_END 0x2 +#define ADMA2_LINK_VALID 0x31 +#define ADMA3_CMD_VALID 0x9 +#define ADMA3_END 0x3b /* * Maximum segments assuming a 512KiB maximum requisition size and a minimum @@ -328,6 +390,18 @@ COOKIE_MAPPED, /* mapped by sdhci_prepare_data() */ }; +struct card_info { + unsigned int card_type; + unsigned char timing; + unsigned char card_connect; +#define CARD_CONNECT 1 +#define CARD_DISCONNECT 0 + unsigned int card_support_clock; /* clock rate */ + unsigned int card_state; /* (our) card state */ + unsigned int sd_bus_speed; + unsigned int ssr[16]; +}; + struct sdhci_host { /* Data set by hardware interface driver */ const char *hw_name; /* Hardware bus name */ @@ -425,6 +499,7 @@ #define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14) /* Broken Clock divider zero in controller */ #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN (1<<15) +#define SDHCI_QUIRK2_BROKEN_ADMA3 (1<<16) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */ @@ -458,6 +533,8 @@ #define SDHCI_SIGNALING_330 (1<<14) /* Host is capable of 3.3V signaling */ #define SDHCI_SIGNALING_180 (1<<15) /* Host is capable of 1.8V signaling */ #define SDHCI_SIGNALING_120 (1<<16) /* Host is capable of 1.2V signaling */ +#define SDHCI_USE_ADMA3 (1<<17) /* Host is ADMA3 capable */ +#define SDHCI_HOST_VER4_ENABLE (1<<18) /* Host version 4 enable */ unsigned int version; /* SDHCI spec. version */ @@ -486,14 +563,21 @@ void *adma_table; /* ADMA descriptor table */ void *align_buffer; /* Bounce buffer */ + void *adma3_table; /* ADMA3 integrated descriptor table */ + void *cmd_table; /* ADMA3 command descriptor table */ size_t adma_table_sz; /* ADMA descriptor table size */ size_t align_buffer_sz; /* Bounce buffer size */ + size_t adma3_table_sz; /* ADMA3 integrated descriptor table size */ + size_t cmd_table_sz; /* ADMA3 command descriptor table size */ dma_addr_t adma_addr; /* Mapped ADMA descr. table */ dma_addr_t align_addr; /* Mapped bounce buffer */ + dma_addr_t adma3_addr; /* Mapped ADMA3 integrated descr. table */ + dma_addr_t cmd_addr; /* Mapped ADMA3 command descr. table */ unsigned int desc_sz; /* ADMA descriptor size */ + unsigned int adma3_desc_sz; /* ADMA3 integrated descriptor size */ struct tasklet_struct finish_tasklet; /* Tasklet structures */ @@ -525,6 +609,10 @@ #define SDHCI_TUNING_MODE_2 1 #define SDHCI_TUNING_MODE_3 2 + struct cmdq_host *cq_host; + unsigned int is_tuning; + unsigned int error_count; + struct card_info c_info; unsigned long private[0] ____cacheline_aligned; }; @@ -564,6 +652,10 @@ struct mmc_card *card, unsigned int max_dtr, int host_drv, int card_drv, int *drv_type); + int (*start_signal_voltage_switch)(struct sdhci_host *host, + struct mmc_ios *ios); + void (*pre_init)(struct sdhci_host *host); + void (*extra_init)(struct sdhci_host *host); }; #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS @@ -698,4 +790,18 @@ extern int sdhci_runtime_resume_host(struct sdhci_host *host); #endif +#define UNSTUFF_BITS(resp,start,size) \ + ({ \ + const int __size = size; \ + const u32 __mask = (__size < 32 ? 1 << __size : 0) - 1; \ + const int __off = 3 - ((start) / 32); \ + const int __shft = (start) & 31; \ + u32 __res; \ + \ + __res = resp[__off] >> __shft; \ + if (__size + __shft > 32) \ + __res |= resp[__off-1] << ((32 - __shft) % 32); \ + __res & __mask; \ + }) + #endif /* __SDHCI_HW_H */