--- linux-4.9.37/arch/arm/boot/compressed/head.S	2017-07-12 16:42:41.000000000 +0300
+++ linux-4.9.y/arch/arm/boot/compressed/head.S	2021-06-07 13:01:32.000000000 +0300
@@ -218,6 +218,21 @@
 		addcc	r0, r0, pc
 		cmpcc	r4, r0
 		orrcc	r4, r4, #1		@ remember we skipped cache_on
+
+/*TODO all the Cortex-A7 Single Core must fix this bug */
+#if defined(CONFIG_ARCH_GK7205V200) || defined(CONFIG_ARCH_GK7205V300) \
+  || defined(CONFIG_ARCH_GK7202V300) || defined(CONFIG_ARCH_GK7605V100) 
+/*
+ * This is a bug on Cortex-A7 MPCORE. see buglist of Cortex-A7
+ * The D-caches are disabled when ACTLR.SMP is set to 0 regardless of the
+ * value of the cache enable bit. so we must set SMP bit of ACTLR register
+ * before enable D cache
+ */
+		mrc     p15, 0, r0, c1, c0, 1
+		orr     r0, #(1 << 6)
+		mcr     p15, 0, r0, c1, c0, 1
+#endif
+
 		blcs	cache_on
 
 restart:	adr	r0, LC0