diff -drupN a/drivers/pinctrl/sunxi/pinctrl-sun50iw3p1-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50iw3p1-r.c
--- a/drivers/pinctrl/sunxi/pinctrl-sun50iw3p1-r.c	1970-01-01 03:00:00.000000000 +0300
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50iw3p1-r.c	2022-06-12 05:28:14.000000000 +0300
@@ -0,0 +1,238 @@
+/*
+ * Allwinner sun50iw3p1 SoCs R_PIO pinctrl driver.
+ *
+ * Copyright(c) 2016-2020 Allwinnertech Co., Ltd.
+ * Author: WimHuang <huangwei@allwinnertech.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-sunxi.h"
+
+#ifdef CONFIG_SUNXI_CPUX_NOT_USE_PL_IRQ
+	#undef SUNXI_FUNCTION_IRQ_BANK
+	#define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) {}
+	#define PIN_PM_BANK	0
+#else
+	#define PIN_PM_BANK	1
+#endif
+
+#define PIN_PL_BANK	0
+#define IRQ_BANKS (PIN_PM_BANK + 1)
+
+static const struct sunxi_desc_pin sun50iw3p1_r_pins[] = {
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
+		SUNXI_FUNCTION(0x0, "gpio_in"),
+		SUNXI_FUNCTION(0x1, "gpio_out"),
+		SUNXI_FUNCTION(0x2, "s_rsb0"),		/* SCK */
+		SUNXI_FUNCTION(0x3, "s_twi0"),		/* SCK */
+		SUNXI_FUNCTION(0x7, "io_disabled"),
+		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
+		SUNXI_FUNCTION(0x0, "gpio_in"),
+		SUNXI_FUNCTION(0x1, "gpio_out"),
+		SUNXI_FUNCTION(0x2, "s_rsb0"),		/* SDA */
+		SUNXI_FUNCTION(0x3, "s_twi0"),		/* SDA */
+		SUNXI_FUNCTION(0x7, "io_disabled"),
+		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
+		SUNXI_FUNCTION(0x0, "gpio_in"),
+		SUNXI_FUNCTION(0x1, "gpio_out"),
+		SUNXI_FUNCTION(0x2, "s_uart0"),		/* TX */
+		SUNXI_FUNCTION(0x7, "io_disabled"),
+		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
+		SUNXI_FUNCTION(0x0, "gpio_in"),
+		SUNXI_FUNCTION(0x1, "gpio_out"),
+		SUNXI_FUNCTION(0x2, "s_uart0"),		/* RX */
+		SUNXI_FUNCTION(0x7, "io_disabled"),
+		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
+		SUNXI_FUNCTION(0x0, "gpio_in"),
+		SUNXI_FUNCTION(0x1, "gpio_out"),
+		SUNXI_FUNCTION(0x2, "s_jtag0"),		/* MS */
+		SUNXI_FUNCTION(0x7, "io_disabled"),
+		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
+		SUNXI_FUNCTION(0x0, "gpio_in"),
+		SUNXI_FUNCTION(0x1, "gpio_out"),
+		SUNXI_FUNCTION(0x2, "s_jtag0"),		/* CK */
+		SUNXI_FUNCTION(0x7, "io_disabled"),
+		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
+		SUNXI_FUNCTION(0x0, "gpio_in"),
+		SUNXI_FUNCTION(0x1, "gpio_out"),
+		SUNXI_FUNCTION(0x2, "s_jtag0"),		/* DO */
+		SUNXI_FUNCTION(0x7, "io_disabled"),
+		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
+		SUNXI_FUNCTION(0x0, "gpio_in"),
+		SUNXI_FUNCTION(0x1, "gpio_out"),
+		SUNXI_FUNCTION(0x2, "s_jtag0"),		/* DI */
+		SUNXI_FUNCTION(0x7, "io_disabled"),
+		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
+		SUNXI_FUNCTION(0x0, "gpio_in"),
+		SUNXI_FUNCTION(0x1, "gpio_out"),
+		SUNXI_FUNCTION(0x2, "s_twi1"),		/* SCK */
+		SUNXI_FUNCTION(0x7, "io_disabled"),
+		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
+		SUNXI_FUNCTION(0x0, "gpio_in"),
+		SUNXI_FUNCTION(0x1, "gpio_out"),
+		SUNXI_FUNCTION(0x2, "s_twi1"),		/* SDA */
+		SUNXI_FUNCTION(0x7, "io_disabled"),
+		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
+		SUNXI_FUNCTION(0x0, "gpio_in"),
+		SUNXI_FUNCTION(0x1, "gpio_out"),
+		SUNXI_FUNCTION(0x2, "s_twi2"),		/* SCK */
+		SUNXI_FUNCTION(0x7, "io_disabled"),
+		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
+		SUNXI_FUNCTION(0x0, "gpio_in"),
+		SUNXI_FUNCTION(0x1, "gpio_out"),
+		SUNXI_FUNCTION(0x2, "s_twi2"),		/* SDA */
+		SUNXI_FUNCTION(0x7, "io_disabled"),
+		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 12),
+		SUNXI_FUNCTION(0x0, "gpio_in"),
+		SUNXI_FUNCTION(0x1, "gpio_out"),
+		SUNXI_FUNCTION(0x2, "s_spi1"),		/* CS */
+		SUNXI_FUNCTION(0x7, "io_disabled"),
+		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 13),
+		SUNXI_FUNCTION(0x0, "gpio_in"),
+		SUNXI_FUNCTION(0x1, "gpio_out"),
+		SUNXI_FUNCTION(0x2, "s_spi1"),		/* CLK */
+		SUNXI_FUNCTION(0x7, "io_disabled"),
+		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 14),
+		SUNXI_FUNCTION(0x0, "gpio_in"),
+		SUNXI_FUNCTION(0x1, "gpio_out"),
+		SUNXI_FUNCTION(0x2, "s_spi1"),		/* MOSO */
+		SUNXI_FUNCTION(0x7, "io_disabled"),
+		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 15),
+		SUNXI_FUNCTION(0x0, "gpio_in"),
+		SUNXI_FUNCTION(0x1, "gpio_out"),
+		SUNXI_FUNCTION(0x2, "s_spi1"),		/* MISO */
+		SUNXI_FUNCTION(0x7, "io_disabled"),
+		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 16),
+		SUNXI_FUNCTION(0x0, "gpio_in"),
+		SUNXI_FUNCTION(0x1, "gpio_out"),
+		SUNXI_FUNCTION(0x2, "s_pwm0"),		/* PWM */
+		SUNXI_FUNCTION(0x7, "io_disabled"),
+		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 17),
+		SUNXI_FUNCTION(0x0, "gpio_in"),
+		SUNXI_FUNCTION(0x1, "gpio_out"),
+		SUNXI_FUNCTION(0x2, "s_cpu"),		/* CUR_W */
+		SUNXI_FUNCTION(0x7, "io_disabled"),
+		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 18),
+		SUNXI_FUNCTION(0x0, "gpio_in"),
+		SUNXI_FUNCTION(0x1, "gpio_out"),
+		SUNXI_FUNCTION(0x7, "io_disabled"),
+		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 19),
+		SUNXI_FUNCTION(0x0, "gpio_in"),
+		SUNXI_FUNCTION(0x1, "gpio_out"),
+		SUNXI_FUNCTION(0x7, "io_disabled"),
+		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)),
+
+	/* Hole */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
+		SUNXI_FUNCTION(0x0, "gpio_in"),
+		SUNXI_FUNCTION(0x1, "gpio_out"),
+		SUNXI_FUNCTION(0x7, "io_disabled"),
+		SUNXI_FUNCTION_IRQ_BANK(0x6, PIN_PM_BANK, 0)),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
+		SUNXI_FUNCTION(0x0, "gpio_in"),
+		SUNXI_FUNCTION(0x1, "gpio_out"),
+		SUNXI_FUNCTION(0x7, "io_disabled"),
+		SUNXI_FUNCTION_IRQ_BANK(0x6, PIN_PM_BANK, 1)),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
+		SUNXI_FUNCTION(0x0, "gpio_in"),
+		SUNXI_FUNCTION(0x1, "gpio_out"),
+		SUNXI_FUNCTION(0x7, "io_disabled"),
+		SUNXI_FUNCTION_IRQ_BANK(0x6, PIN_PM_BANK, 2)),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
+		SUNXI_FUNCTION(0x0, "gpio_in"),
+		SUNXI_FUNCTION(0x1, "gpio_out"),
+		SUNXI_FUNCTION(0x7, "io_disabled"),
+		SUNXI_FUNCTION_IRQ_BANK(0x6, PIN_PM_BANK, 3)),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
+		SUNXI_FUNCTION(0x0, "gpio_in"),
+		SUNXI_FUNCTION(0x1, "gpio_out"),
+		SUNXI_FUNCTION(0x7, "io_disabled"),
+		SUNXI_FUNCTION_IRQ_BANK(0x6, PIN_PM_BANK, 4)),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 5),
+		SUNXI_FUNCTION(0x0, "gpio_in"),
+		SUNXI_FUNCTION(0x1, "gpio_out"),
+		SUNXI_FUNCTION(0x7, "io_disabled"),
+		SUNXI_FUNCTION_IRQ_BANK(0x6, PIN_PM_BANK, 5)),
+};
+
+static const unsigned sun50iw3p1_r_irq_bank_base[] = {
+#ifndef CONFIG_SUNXI_CPUX_NOT_USE_PL_IRQ
+	SUNXI_R_PIO_BANK_BASE(PL_BASE, PIN_PL_BANK),
+#endif
+	SUNXI_R_PIO_BANK_BASE(PM_BASE, PIN_PM_BANK),
+};
+
+static const struct sunxi_pinctrl_desc sun50iw3p1_r_pinctrl_data = {
+	.pins = sun50iw3p1_r_pins,
+	.npins = ARRAY_SIZE(sun50iw3p1_r_pins),
+	.pin_base = PL_BASE,
+	.irq_banks = IRQ_BANKS,
+	.irq_bank_base = sun50iw3p1_r_irq_bank_base,
+};
+
+static int sun50iw3p1_r_pinctrl_probe(struct platform_device *pdev)
+{
+	return sunxi_pinctrl_init(pdev, &sun50iw3p1_r_pinctrl_data);
+}
+
+static struct of_device_id sun50iw3p1_r_pinctrl_match[] = {
+	{ .compatible = "allwinner,sun50iw3p1-r-pinctrl", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, sun50iw3p1_r_pinctrl_match);
+
+static struct platform_driver sun50iw3p1_r_pinctrl_driver = {
+	.probe	= sun50iw3p1_r_pinctrl_probe,
+	.driver	= {
+		.name		= "sun50iw3p1-r-pinctrl",
+		.owner		= THIS_MODULE,
+		.of_match_table	= sun50iw3p1_r_pinctrl_match,
+	},
+};
+
+static int __init sun50iw3p1_r_pio_init(void)
+{
+	int ret;
+	ret = platform_driver_register(&sun50iw3p1_r_pinctrl_driver);
+	if (ret) {
+		pr_debug("register sun50i r-pio controller failed\n");
+		return -EINVAL;
+	}
+	return 0;
+}
+postcore_initcall(sun50iw3p1_r_pio_init);
+
+
+
+
+MODULE_AUTHOR("WimHuang<huangwei@allwinnertech.com>");
+MODULE_DESCRIPTION("Allwinner sun50iw3p1 R_PIO pinctrl driver");
+MODULE_LICENSE("GPL");