diff -drupN a/drivers/clk/sunxi/clk-sun50iw8.c b/drivers/clk/sunxi/clk-sun50iw8.c --- a/drivers/clk/sunxi/clk-sun50iw8.c 1970-01-01 03:00:00.000000000 +0300 +++ b/drivers/clk/sunxi/clk-sun50iw8.c 2022-06-12 05:28:14.000000000 +0300 @@ -0,0 +1,562 @@ +/* + * Copyright (C) 2016 Allwinnertech + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include +#include +#include "clk-sunxi.h" +#include "clk-factors.h" +#include "clk-periph.h" +#include "clk-sun50iw8.h" +#include "clk-sun50iw8_tbl.c" + +#define FACTOR_SIZEOF(name) (sizeof(factor_pll##name##_tbl)/ \ + sizeof(struct sunxi_clk_factor_freq)) + +#define FACTOR_SEARCH(name) (sunxi_clk_com_ftr_sr( \ + &sunxi_clk_factor_pll_##name, factor, \ + factor_pll##name##_tbl, index, \ + FACTOR_SIZEOF(name))) + +#ifndef CONFIG_EVB_PLATFORM + #define LOCKBIT(x) 31 +#else + #define LOCKBIT(x) x +#endif + +/** pll input select ** + * SUNXI_PLL_24M_INPUT --pll_24m input + * SUNXI_PLL_HOSC_INPUT --hosc input + */ +#define SUNXI_PLL_HOSC_INPUT + +DEFINE_SPINLOCK(clk_lock); +void __iomem *sunxi_clk_base; +void __iomem *sunxi_clk_cpus_base; +void __iomem *sunxi_clk_rtc_base; +int sunxi_clk_maxreg = SUNXI_CLK_MAX_REG; +int cpus_clk_maxreg = CPUS_CLK_MAX_REG; + +#if defined SUNXI_PLL_HOSC_INPUT +/* ns nw ks kw ms mw ps pw d1s d1w d2s d2w {frac out mode} en-s sdmss sdmsw sdmpat sdmval*/ +SUNXI_CLK_FACTORS1(pll_cpu, 8, 8, 0, 0, 0, 0, 16, 2, 0, 0, 0, 0, 0, 0, 0, 31, 0, 0, 0, 0, 23, 27); +SUNXI_CLK_FACTORS1(pll_ddr, 8, 8, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 31, 24, 0, PLL_DDRPAT, 0xd1303333, 23, 27); +SUNXI_CLK_FACTORS1(pll_periph0, 8, 8, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 31, 0, 0, 0, 0, 23, 27); +SUNXI_CLK_FACTORS1(pll_periph1, 8, 8, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 31, 24, 0, PLL_PERI1PAT0, 0xd1303333, 23, 27); +SUNXI_CLK_FACTORS1(pll_video0, 8, 8, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 31, 24, 0, PLL_VIDEO0PAT0, 0xd1303333, 23, 27); +SUNXI_CLK_FACTORS1(pll_audio, 8, 8, 0, 0, 0, 0, 16, 6, 1, 1, 0, 1, 0, 0, 0, 31, 24, 1, PLL_AUDIOPAT0, 0xc00121ff, 23, 27); +SUNXI_CLK_FACTORS1(pll_24m, 8, 8, 0, 0, 0, 0, 16, 6, 1, 1, 0, 1, 0, 0, 0, 31, 24, 0, 0, 0xc00121ff, 23, 27); +#elif defined SUNXI_PLL_24M_INPUT +/* ns nw ks kw ms mw ps pw d1s d1w d2s d2w {frac out mode} en-s sdmss sdmsw sdmpat sdmval*/ +SUNXI_CLK_FACTORS1(pll_cpu, 8, 8, 0, 0, 0, 0, 16, 2, 0, 0, 0, 0, 0, 0, 0, 31, 0, 0, 0, 0, 0, 27); +SUNXI_CLK_FACTORS1(pll_ddr, 8, 8, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 31, 24, 0, PLL_DDRPAT, 0xd1303333, 0, 27); +SUNXI_CLK_FACTORS1(pll_periph0, 8, 8, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 31, 0, 0, 0, 0, 0, 27); +SUNXI_CLK_FACTORS1(pll_periph1, 8, 8, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 31, 24, 0, PLL_PERI1PAT0, 0xd1303333, 0, 27); +SUNXI_CLK_FACTORS1(pll_video0, 8, 8, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 31, 24, 0, PLL_VIDEO0PAT0, 0xd1303333, 0, 27); +SUNXI_CLK_FACTORS1(pll_audio, 8, 8, 0, 0, 0, 0, 16, 6, 1, 1, 0, 1, 0, 0, 0, 31, 24, 1, PLL_AUDIOPAT0, 0xc00121ff, 0, 27); +SUNXI_CLK_FACTORS1(pll_24m, 8, 8, 0, 0, 0, 0, 16, 6, 1, 1, 0, 1, 0, 0, 0, 31, 24, 0, 0, 0xc00121ff, 0, 27); +#endif + +static int get_factors_pll_cpu(u32 rate, u32 parent_rate, + struct clk_factors_value *factor) +{ + + int index; + u64 tmp_rate; + + if (!factor) + return -1; + tmp_rate = rate > pllcpu_max ? pllcpu_max : rate; + do_div(tmp_rate, 1000000); + index = tmp_rate; + + if (FACTOR_SEARCH(cpu)) + return -1; + + return 0; +} + +static int get_factors_pll_ddr(u32 rate, u32 parent_rate, + struct clk_factors_value *factor) +{ + int index; + u64 tmp_rate; + + if (!factor) + return -1; + + tmp_rate = rate > pllddr_max ? pllddr_max : rate; + do_div(tmp_rate, 1000000); + index = tmp_rate; + + if (FACTOR_SEARCH(ddr)) + return -1; + + return 0; +} + +static int get_factors_pll_periph0(u32 rate, u32 parent_rate, + struct clk_factors_value *factor) +{ + int index; + u64 tmp_rate; + + if (!factor) + return -1; + + tmp_rate = rate > pllperiph0_max ? pllperiph0_max : rate; + do_div(tmp_rate, 1000000); + index = tmp_rate; + + if (FACTOR_SEARCH(periph0)) + return -1; + + return 0; +} + +static int get_factors_pll_periph1(u32 rate, u32 parent_rate, + struct clk_factors_value *factor) +{ + int index; + u64 tmp_rate; + + if (!factor) + return -1; + + tmp_rate = rate > pllperiph1_max ? pllperiph1_max : rate; + do_div(tmp_rate, 1000000); + index = tmp_rate; + + if (FACTOR_SEARCH(periph1)) + return -1; + + return 0; +} + +static int get_factors_pll_video0(u32 rate, u32 parent_rate, + struct clk_factors_value *factor) +{ + u64 tmp_rate; + int index; + + if (!factor) + return -1; + + tmp_rate = rate > pllvideo0_max ? pllvideo0_max : rate; + do_div(tmp_rate, 1000000); + index = tmp_rate; + + if (FACTOR_SEARCH(video0)) + return -1; + + return 0; +} + +/* pll_cpux: 24*N/P (P=2^factorp) */ +static unsigned long calc_rate_pll_cpu(u32 parent_rate, + struct clk_factors_value *factor) +{ + u64 tmp_rate = (parent_rate ? parent_rate : 24000000); + tmp_rate = tmp_rate * (factor->factorn + 1); + do_div(tmp_rate, (1 << factor->factorp)); + return (unsigned long)tmp_rate; +} + +/* pll_ddr: 24*N/D1/D2 */ +static unsigned long calc_rate_pll_ddr(u32 parent_rate, + struct clk_factors_value *factor) +{ + u64 tmp_rate = (parent_rate ? parent_rate : 24000000); + tmp_rate = tmp_rate * (factor->factorn + 1); + do_div(tmp_rate, (factor->factord1 + 1) * (factor->factord2 + 1)); + return (unsigned long)tmp_rate; +} + +/* pll_periph0/pll_periph1: 24*N/D1/D2/2 */ +static unsigned long calc_rate_pll_periph(u32 parent_rate, + struct clk_factors_value *factor) +{ + u64 tmp_rate = (parent_rate ? parent_rate : 24000000); + tmp_rate = tmp_rate * (factor->factorn + 1); + do_div(tmp_rate, 2 * (factor->factord1 + 1) * (factor->factord2 + 1)); + return (unsigned long)tmp_rate; +} + +/* pll_video0/pll_video1: 24*N/D1/4 */ +static unsigned long calc_rate_video(u32 parent_rate, + struct clk_factors_value *factor) +{ + u64 tmp_rate = (parent_rate ? parent_rate : 24000000); + tmp_rate = tmp_rate * (factor->factorn + 1); + do_div(tmp_rate, 4 * (factor->factord1 + 1)); + return (unsigned long)tmp_rate; +} + +/* + * pll_audio: 24*N/D1/D2/P + * + * NOTE: pll_audiox4 = 24*N/D1/2 + * pll_audiox2 = 24*N/D1/4 + * + * pll_audiox4=2*pll_audiox2=4*pll_audio only when D2*P=8 + */ +static unsigned long calc_rate_audio(u32 parent_rate, + struct clk_factors_value *factor) +{ + u64 tmp_rate = (parent_rate ? parent_rate : 24000000); + if ((factor->factorn == 21) && + (factor->factorp == 11) && + (factor->factord1 == 0) && + (factor->factord2 == 1)) + return 22579200; + else if ((factor->factorn == 23) && + (factor->factorp == 11) && + (factor->factord1 == 0) && + (factor->factord2 == 1)) + return 24576000; + else { + tmp_rate = tmp_rate * (factor->factorn + 1); + do_div(tmp_rate, ((factor->factorp + 1) * + (factor->factord1 + 1) * + (factor->factord2 + 1))); + return (unsigned long)tmp_rate; + } +} + +static int get_factors_pll_audio(u32 rate, u32 parent_rate, + struct clk_factors_value *factor) +{ + if (rate == 22579200) { + factor->factorn = 21; + factor->factorp = 11; + factor->factord1 = 0; + factor->factord2 = 1; + sunxi_clk_factor_pll_audio.sdmval = 0xC001288D; + } else if (rate == 24576000) { + factor->factorn = 23; + factor->factorp = 11; + factor->factord1 = 0; + factor->factord2 = 1; + sunxi_clk_factor_pll_audio.sdmval = 0xC00126E9; + } else + return -1; + + return 0; +} + +static const char *hosc_parents[] = {"hosc"}; +struct factor_init_data sunxi_factos[] = { + /* name parent parent_num, flags reg lock_reg lock_bit pll_lock_ctrl_reg lock_en_bit lock_mode config get_factors calc_rate priv_ops*/ + {"pll_cpu", hosc_parents, 1, CLK_GET_RATE_NOCACHE, PLL_CPU, PLL_CPU, LOCKBIT(28), PLL_CPU, 29, PLL_LOCK_NEW_MODE, &sunxi_clk_factor_pll_cpu, &get_factors_pll_cpu, &calc_rate_pll_cpu, (struct clk_ops *)NULL}, + {"pll_ddr", hosc_parents, 1, CLK_GET_RATE_NOCACHE, PLL_DDR, PLL_DDR, LOCKBIT(28), PLL_DDR, 29, PLL_LOCK_NEW_MODE, &sunxi_clk_factor_pll_ddr, &get_factors_pll_ddr, &calc_rate_pll_ddr, (struct clk_ops *)NULL}, + {"pll_periph0", hosc_parents, 1, 0, PLL_PERIPH0, PLL_PERIPH0, LOCKBIT(28), PLL_PERIPH0, 29, PLL_LOCK_NEW_MODE, &sunxi_clk_factor_pll_periph0, &get_factors_pll_periph0, &calc_rate_pll_periph, (struct clk_ops *)NULL}, + {"pll_periph1", hosc_parents, 1, 0, PLL_PERIPH1, PLL_PERIPH1, LOCKBIT(28), PLL_PERIPH1, 29, PLL_LOCK_NEW_MODE, &sunxi_clk_factor_pll_periph1, &get_factors_pll_periph1, &calc_rate_pll_periph, (struct clk_ops *)NULL}, + {"pll_video0", hosc_parents, 1, 0, PLL_VIDEO0, PLL_VIDEO0, LOCKBIT(28), PLL_VIDEO0, 29, PLL_LOCK_NEW_MODE, &sunxi_clk_factor_pll_video0, &get_factors_pll_video0, &calc_rate_video, (struct clk_ops *)NULL}, + {"pll_audio", hosc_parents, 1, 0, PLL_AUDIO, PLL_AUDIO, LOCKBIT(28), PLL_AUDIO, 29, PLL_LOCK_NEW_MODE, &sunxi_clk_factor_pll_audio, &get_factors_pll_audio, &calc_rate_audio, (struct clk_ops *)NULL}, + {"pll_24m", hosc_parents, 1, 0, PLL_24M, PLL_24M, LOCKBIT(28), PLL_24M, 29, PLL_LOCK_NEW_MODE, &sunxi_clk_factor_pll_24m, NULL, NULL, (struct clk_ops *)NULL}, +}; + +static const char *cpu_parents[] = {"hosc", "losc", "iosc", "pll_cpu", "pll_24m", "", "", ""}; +static const char *axi_parents[] = {"cpu"}; +static const char *cpuapb_parents[] = {"cpu"}; +static const char *psi_parents[] = {"hosc", "losc", "iosc", "pll_periph0", "pll_24m", "", "", ""}; +static const char *ahb1_parents[] = {"psi"}; +static const char *ahb2_parents[] = {"psi"}; +static const char *ahb3_parents[] = {"hosc", "losc", "psi", "pll_periph0", "pll_24m", "", "", ""}; +static const char *apb1_parents[] = {"hosc", "losc", "psi", "pll_periph0", "pll_24m", "", "", ""}; +static const char *apb2_parents[] = {"hosc", "losc", "psi", "pll_periph0", "pll_24m", "", "", ""}; +static const char *mbus_parents[] = {"hosc", "pll_periph0x2", "pll_ddr", "pll_periph0x4"}; +static const char *de_parents[] = {"pll_periph0x2"}; +static const char *ce_parents[] = {"hosc", "pll_periph0x2"}; +static const char *emce_parents[] = {"hosc", "pll_periph0x2"}; +static const char *ahb1mod_parents[] = {"ahb1"}; +static const char *ahb3mod_parents[] = {"ahb3"}; +static const char *apb1mod_parents[] = {"apb1"}; +static const char *apb2mod_parents[] = {"apb2"}; +static const char *sdram_parents[] = {"pll_ddr", "", "", ""}; +static const char *nand_parents[] = {"hosc", "pll_periph0", "pll_periph1", "pll_periph0x2", "pll_periph1x2", "", "", ""}; +static const char *smhc_parents[] = {"hosc", "pll_periph0x2", "pll_periph1x2", "", "", "", "", ""}; +static const char *spi_parents[] = {"hosc", "pll_periph0", "pll_periph1", "pll_periph0x2", "pll_periph1x2", "", "", ""}; +static const char *audio_parents[] = {"pll_audio", "pll_audiox2", "pll_audiox4", ""}; +static const char *usbohci_12m_parents[] = {"osc48md4", "hoscd2", "losc", "iosc"}; +static const char *tcon_lcd_parents[] = {"pll_video0", "pll_video0x4", "pll_video1", "", "", "", "", ""}; +static const char *cpurcpus_pll_parents[] = {"pll_periph0"}; +static const char *cpurcpus_parents[] = {"hosc", "losc", "iosc", "cpurcpus_pll"}; +static const char *cpurahbs_parents[] = {"cpurcpus"}; +static const char *cpurapbs1_parents[] = {"cpurahbs"}; +static const char *cpurapbs2_pll_parents[] = {"pll_periph0"}; +static const char *cpurapbs2_parents[] = {"hosc", "losc", "iosc", "cpurapbs2_pll"}; +static const char *cpurpio_parents[] = {"cpurapbs1"}; +static const char *losc_parents[] = {"losc"}; +static const char *spwm_parents[] = {"hosc", "losc", "iosc", ""}; +static const char *ledc_parents[] = {"hosc", "pll_periph0"}; +static const char *lpsd_parents[] = {"hosc", "pll_audio"}; +static const char *ir_parents[] = {"losc", "hosc"}; + +struct sunxi_clk_comgate com_gates[] = { +{"nand", 0, 0x3, BUS_GATE_SHARE|RST_GATE_SHARE|MBUS_GATE_SHARE, 0}, +{"codec", 0, 0x3, BUS_GATE_SHARE|RST_GATE_SHARE, 0}, +{"csi", 0, 0x7, BUS_GATE_SHARE|RST_GATE_SHARE|MBUS_GATE_SHARE, 0}, +}; + +/* +SUNXI_CLK_PERIPH(name, mux_reg, mux_sft, mux_wid, div_reg, div_msft, div_mwid, div_nsft, div_nwid, gate_flag, en_reg, rst_reg, bus_gate_reg, drm_gate_reg, en_sft, rst_sft, bus_gate_sft, dram_gate_sft, lock, com_gate, com_gate_off) +*/ +SUNXI_CLK_PERIPH(cpu, CPU_CFG, 24, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(axi, 0, 0, 0, CPU_CFG, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(cpuapb, 0, 0, 0, CPU_CFG, 8, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(psi, PSI_CFG, 24, 2, PSI_CFG, 0, 2, 8, 2, 0, 0, PSI_GATE, PSI_GATE, 0, 0, 16, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(ahb1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(ahb2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(ahb3, AHB3_CFG, 24, 3, AHB3_CFG, 0, 2, 8, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(apb1, APB1_CFG, 24, 3, APB1_CFG, 0, 2, 8, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(apb2, APB2_CFG, 24, 3, APB2_CFG, 0, 2, 8, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(mbus, MBUS_CFG, 24, 2, MBUS_CFG, 0, 3, 0, 0, 0, MBUS_CFG, MBUS_CFG, 0, 0, 31, 30, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(de, DE_CFG, 24, 1, DE_CFG, 0, 4, 0, 0, 0, DE_CFG, DE_GATE, DE_GATE, 0, 31, 16, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(ce, CE_CFG, 24, 1, CE_CFG, 0, 4, 8, 2, 0, CE_CFG, CE_GATE, CE_GATE, MBUS_GATE, 31, 16, 0, 2, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(emce, EMCE_CFG, 24, 1, EMCE_CFG, 0, 4, 8, 2, 0, EMCE_CFG, EMCE_GATE, EMCE_GATE, MBUS_GATE, 31, 16, 0, 24, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(dma, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, DMA_GATE, DMA_GATE, MBUS_GATE, 0, 16, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(msgbox, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, MSGBOX_GATE, MSGBOX_GATE, 0, 0, 16, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(hwspinlock_rst, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, SPINLOCK_GATE, 0, 0, 0, 16, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(hwspinlock_bus, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, SPINLOCK_GATE, 0, 0, 0, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(hstimer, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, HSTIMER_GATE, HSTIMER_GATE, 0, 0, 16, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(avs, 0, 0, 0, 0, 0, 0, 0, 0, 0, AVS_CFG, 0, 0, 0, 31, 0, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(dbgsys, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, DBGSYS_GATE, DBGSYS_GATE, 0, 0, 16, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(pwm, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PWM_GATE, PWM_GATE, 0, 0, 16, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(sdram, DRAM_CFG, 24, 2, DRAM_CFG, 0, 2, 0, 0, 0, 0, DRAM_GATE, DRAM_GATE, 0, 0, 16, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(nand0, NAND0_CFG, 24, 3, NAND0_CFG, 0, 4, 8, 2, 0, NAND0_CFG, NAND_GATE, NAND_GATE, MBUS_GATE, 31, 16, 0, 5, &clk_lock, &com_gates[0], 0); +SUNXI_CLK_PERIPH(nand1, NAND1_CFG, 24, 3, NAND1_CFG, 0, 4, 8, 2, 0, NAND1_CFG, NAND_GATE, NAND_GATE, MBUS_GATE, 31, 16, 0, 5, &clk_lock, &com_gates[0], 1); +SUNXI_CLK_PERIPH(sdmmc0_mod, SMHC0_CFG, 24, 2, SMHC0_CFG, 0, 4, 8, 2, 0, SMHC0_CFG, 0, 0, 0, 31, 0, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(sdmmc0_rst, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, SMHC_GATE, 0, 0, 0, 16, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(sdmmc0_bus, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, SMHC_GATE, 0, 0, 0, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(sdmmc1_mod, SMHC1_CFG, 24, 2, SMHC1_CFG, 0, 4, 8, 2, 0, SMHC1_CFG, 0, 0, 0, 31, 0, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(sdmmc1_rst, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, SMHC_GATE, 0, 0, 0, 17, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(sdmmc1_bus, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, SMHC_GATE, 0, 0, 0, 1, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(sdmmc2_mod, SMHC2_CFG, 24, 2, SMHC2_CFG, 0, 4, 8, 2, 0, SMHC2_CFG, 0, 0, 0, 31, 0, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(sdmmc2_rst, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, SMHC_GATE, 0, 0, 0, 18, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(sdmmc2_bus, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, SMHC_GATE, 0, 0, 0, 2, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(uart0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, UART_GATE, UART_GATE, 0, 0, 16, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(uart1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, UART_GATE, UART_GATE, 0, 0, 17, 1, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(uart2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, UART_GATE, UART_GATE, 0, 0, 18, 2, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(uart3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, UART_GATE, UART_GATE, 0, 0, 19, 3, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(uart4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, UART_GATE, UART_GATE, 0, 0, 20, 4, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(twi0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, TWI_GATE, TWI_GATE, 0, 0, 16, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(twi1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, TWI_GATE, TWI_GATE, 0, 0, 17, 1, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(twi2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, TWI_GATE, TWI_GATE, 0, 0, 18, 2, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(spi0, SPI0_CFG, 24, 3, SPI0_CFG, 0, 4, 8, 2, 0, SPI0_CFG, SPI_GATE, SPI_GATE, 0, 31, 16, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(spi1, SPI1_CFG, 24, 3, SPI1_CFG, 0, 4, 8, 2, 0, SPI1_CFG, SPI_GATE, SPI_GATE, 0, 31, 17, 1, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(gmac, 0, 0, 0, 0, 0, 4, 8, 2, 0, GMAC_CFG, GMAC_GATE, GMAC_GATE, 0, 31, 16, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(irtx, IRTX_CFG, 24, 1, IRTX_CFG, 0, 4, 8, 2, 0, IRTX_CFG, IRTX_GATE, IRTX_GATE, 0, 31, 16, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(gpadc, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, GPADC_GATE, GPADC_GATE, 0, 0, 16, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(ths, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, THS_GATE, THS_GATE, 0, 0, 16, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(i2s0, I2S0_CFG, 24, 2, I2S0_CFG, 0, 0, 8, 2, 0, I2S0_CFG, I2S_GATE, I2S_GATE, 0, 31, 16, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(i2s1, I2S1_CFG, 24, 2, I2S1_CFG, 0, 0, 8, 2, 0, I2S1_CFG, I2S_GATE, I2S_GATE, 0, 31, 17, 1, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(i2s2, I2S2_CFG, 24, 2, I2S2_CFG, 0, 0, 8, 2, 0, I2S2_CFG, I2S_GATE, I2S_GATE, 0, 31, 18, 2, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(spdif, SPDIF_CFG, 24, 2, SPDIF_CFG, 0, 0, 8, 2, 0, SPDIF_CFG, SPDIF_GATE, SPDIF_GATE, 0, 31, 16, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(dmic, DMIC_CFG, 24, 2, DMIC_CFG, 0, 0, 8, 2, 0, DMIC_CFG, DMIC_GATE, DMIC_GATE, 0, 31, 16, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(codec_1x, CODEC_1X_CFG, 24, 2, CODEC_1X_CFG, 0, 4, 0, 0, 0, CODEC_1X_CFG, CODEC_GATE, CODEC_GATE, 0, 31, 16, 0, 0, &clk_lock, &com_gates[1], 0); +SUNXI_CLK_PERIPH(codec_4x, CODEC_4X_CFG, 24, 2, CODEC_4X_CFG, 0, 4, 0, 0, 0, CODEC_4X_CFG, CODEC_GATE, CODEC_GATE, 0, 31, 16, 0, 0, &clk_lock, &com_gates[1], 1); +SUNXI_CLK_PERIPH(usbphy0, 0, 0, 0, 0, 0, 0, 0, 0, 0, USB0_CFG, USB0_CFG, 0, 0, 29, 30, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(usbphy1, 0, 0, 0, 0, 0, 0, 0, 0, 0, USB1_CFG, USB1_CFG, 0, 0, 29, 30, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(usbohci0, 0, 0, 0, 0, 0, 0, 0, 0, 0, USB0_CFG, USB_GATE, USB_GATE, 0, 31, 16, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(usbohci0_12m, USB0_CFG, 24, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(usbohci1, 0, 0, 0, 0, 0, 0, 0, 0, 0, USB1_CFG, USB_GATE, USB_GATE, 0, 31, 17, 1, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(usbohci1_12m, USB1_CFG, 24, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(usbehci0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, USB_GATE, USB_GATE, 0, 0, 20, 4, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(usbehci1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, USB_GATE, USB_GATE, 0, 0, 21, 5, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(usbotg, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, USB_GATE, USB_GATE, 0, 0, 24, 8, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(display_top, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, DISPLAY_TOP_GATE, DISPLAY_TOP_GATE, 0, 0, 16, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(tcon_lcd0, TCON_LCD0_CFG, 24, 3, 0, 0, 0, 0, 0, 0, TCON_LCD0_CFG, TCON_LCD_GATE, TCON_LCD_GATE, 0, 31, 16, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(ledc, LEDC_CFG, 24, 1, LEDC_CFG, 0, 4, 8, 2, 0, LEDC_CFG, LEDC_GATE, LEDC_GATE, 0, 31, 16, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(pio, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(mad, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, MAD_GATE, MAD_GATE, 0, 0, 16, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(lpsd, LPSD_CFG, 24, 1, LPSD_CFG, 0, 4, 8, 2, 0, LPSD_CFG, 0, 0, 0, 31, 0, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(cpurcpus_pll, 0, 0, 0, CPUS_CFG, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(cpurcpus, CPUS_CFG, 24, 2, CPUS_CFG, 0, 0, 8, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(cpurahbs, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(cpurapbs1, 0, 0, 0, CPUS_APBS1_CFG, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(cpurapbs2_pll, 0, 0, 0, CPUS_APBS2_CFG, 0, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(cpurapbs2, CPUS_APBS2_CFG, 24, 2, CPUS_APBS2_CFG, 0, 0, 8, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(losc_out, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, LOSC_OUT_GATE, 0, 0, 0, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(cpurpio, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(cpurcir, CPUS_CIR_CFG, 24, 1, CPUS_CIR_CFG, 0, 5, 8, 2, 0, CPUS_CIR_CFG, CPUS_CIR_GATE, CPUS_CIR_GATE, 0, 31, 16, 0, 0, &clk_lock, NULL, 0); +SUNXI_CLK_PERIPH(spwm, CPUS_PWM_CFG, 24, 2, 0, 0, 0, 0, 0, 0, CPUS_PWM_GATE, CPUS_PWM_GATE, CPUS_PWM_GATE, 0, 31, 16, 0, 0, &clk_lock, NULL, 0); +struct periph_init_data sunxi_periphs_init[] = { + {"cpu", CLK_GET_RATE_NOCACHE, cpu_parents, ARRAY_SIZE(cpu_parents), &sunxi_clk_periph_cpu }, + {"axi", 0, axi_parents, ARRAY_SIZE(axi_parents), &sunxi_clk_periph_axi }, + {"cpuapb", 0, cpuapb_parents, ARRAY_SIZE(cpuapb_parents), &sunxi_clk_periph_cpuapb }, + {"psi", 0, psi_parents, ARRAY_SIZE(psi_parents), &sunxi_clk_periph_psi }, + {"ahb1", 0, ahb1_parents, ARRAY_SIZE(ahb1_parents), &sunxi_clk_periph_ahb1 }, + {"ahb2", 0, ahb2_parents, ARRAY_SIZE(ahb2_parents), &sunxi_clk_periph_ahb2 }, + {"ahb3", 0, ahb3_parents, ARRAY_SIZE(ahb3_parents), &sunxi_clk_periph_ahb3 }, + {"apb1", 0, apb1_parents, ARRAY_SIZE(apb1_parents), &sunxi_clk_periph_apb1 }, + {"apb2", 0, apb2_parents, ARRAY_SIZE(apb2_parents), &sunxi_clk_periph_apb2 }, + {"mbus", 0, mbus_parents, ARRAY_SIZE(mbus_parents), &sunxi_clk_periph_mbus }, + {"de", 0, de_parents, ARRAY_SIZE(de_parents), &sunxi_clk_periph_de }, + {"ce", 0, ce_parents, ARRAY_SIZE(ce_parents), &sunxi_clk_periph_ce }, + {"emce", 0, emce_parents, ARRAY_SIZE(emce_parents), &sunxi_clk_periph_emce }, + {"dma", 0, ahb1mod_parents, ARRAY_SIZE(ahb1mod_parents), &sunxi_clk_periph_dma }, + {"msgbox", 0, ahb1mod_parents, ARRAY_SIZE(ahb1mod_parents), &sunxi_clk_periph_msgbox }, + {"hwspinlock_rst", 0, ahb1mod_parents, ARRAY_SIZE(ahb1mod_parents), &sunxi_clk_periph_hwspinlock_rst }, + {"hwspinlock_bus", 0, ahb1mod_parents, ARRAY_SIZE(ahb1mod_parents), &sunxi_clk_periph_hwspinlock_bus }, + {"hstimer", 0, ahb1mod_parents, ARRAY_SIZE(ahb1mod_parents), &sunxi_clk_periph_hstimer }, + {"avs", 0, hosc_parents, ARRAY_SIZE(hosc_parents), &sunxi_clk_periph_avs }, + {"dbgsys", 0, ahb1mod_parents, ARRAY_SIZE(ahb1mod_parents), &sunxi_clk_periph_dbgsys }, + {"pwm", 0, apb1mod_parents, ARRAY_SIZE(apb1mod_parents), &sunxi_clk_periph_pwm }, + {"sdram", 0, sdram_parents, ARRAY_SIZE(sdram_parents), &sunxi_clk_periph_sdram }, + {"nand0", 0, nand_parents, ARRAY_SIZE(nand_parents), &sunxi_clk_periph_nand0 }, + {"nand1", 0, nand_parents, ARRAY_SIZE(nand_parents), &sunxi_clk_periph_nand1 }, + {"sdmmc0_mod", 0, smhc_parents, ARRAY_SIZE(smhc_parents), &sunxi_clk_periph_sdmmc0_mod }, + {"sdmmc0_rst", 0, smhc_parents, ARRAY_SIZE(smhc_parents), &sunxi_clk_periph_sdmmc0_rst }, + {"sdmmc0_bus", 0, smhc_parents, ARRAY_SIZE(smhc_parents), &sunxi_clk_periph_sdmmc0_bus }, + {"sdmmc1_mod", 0, smhc_parents, ARRAY_SIZE(smhc_parents), &sunxi_clk_periph_sdmmc1_mod }, + {"sdmmc1_rst", 0, smhc_parents, ARRAY_SIZE(smhc_parents), &sunxi_clk_periph_sdmmc1_rst }, + {"sdmmc1_bus", 0, smhc_parents, ARRAY_SIZE(smhc_parents), &sunxi_clk_periph_sdmmc1_bus }, + {"sdmmc2_mod", 0, smhc_parents, ARRAY_SIZE(smhc_parents), &sunxi_clk_periph_sdmmc2_mod }, + {"sdmmc2_rst", 0, smhc_parents, ARRAY_SIZE(smhc_parents), &sunxi_clk_periph_sdmmc2_rst }, + {"sdmmc2_bus", 0, smhc_parents, ARRAY_SIZE(smhc_parents), &sunxi_clk_periph_sdmmc2_bus }, + {"uart0", 0, apb2mod_parents, ARRAY_SIZE(apb2mod_parents), &sunxi_clk_periph_uart0 }, + {"uart1", 0, apb2mod_parents, ARRAY_SIZE(apb2mod_parents), &sunxi_clk_periph_uart1 }, + {"uart2", 0, apb2mod_parents, ARRAY_SIZE(apb2mod_parents), &sunxi_clk_periph_uart2 }, + {"uart3", 0, apb2mod_parents, ARRAY_SIZE(apb2mod_parents), &sunxi_clk_periph_uart3 }, + {"uart4", 0, apb2mod_parents, ARRAY_SIZE(apb2mod_parents), &sunxi_clk_periph_uart4 }, + {"twi0", 0, apb2mod_parents, ARRAY_SIZE(apb2mod_parents), &sunxi_clk_periph_twi0 }, + {"twi1", 0, apb2mod_parents, ARRAY_SIZE(apb2mod_parents), &sunxi_clk_periph_twi1 }, + {"twi2", 0, apb2mod_parents, ARRAY_SIZE(apb2mod_parents), &sunxi_clk_periph_twi2 }, + {"spi0", 0, spi_parents, ARRAY_SIZE(spi_parents), &sunxi_clk_periph_spi0 }, + {"spi1", 0, spi_parents, ARRAY_SIZE(spi_parents), &sunxi_clk_periph_spi1 }, + {"ths", 0, apb1mod_parents, ARRAY_SIZE(apb1mod_parents), &sunxi_clk_periph_ths }, + {"gmac", 0, cpurapbs2_pll_parents, ARRAY_SIZE(cpurapbs2_pll_parents), &sunxi_clk_periph_gmac }, + {"irtx", 0, ir_parents, ARRAY_SIZE(ir_parents), &sunxi_clk_periph_irtx }, + {"gpadc", 0, apb1mod_parents, ARRAY_SIZE(apb1mod_parents), &sunxi_clk_periph_gpadc }, + {"i2s0", 0, audio_parents, ARRAY_SIZE(audio_parents), &sunxi_clk_periph_i2s0 }, + {"i2s1", 0, audio_parents, ARRAY_SIZE(audio_parents), &sunxi_clk_periph_i2s1 }, + {"i2s2", 0, audio_parents, ARRAY_SIZE(audio_parents), &sunxi_clk_periph_i2s2 }, + {"spdif", 0, audio_parents, ARRAY_SIZE(audio_parents), &sunxi_clk_periph_spdif }, + {"dmic", 0, audio_parents, ARRAY_SIZE(audio_parents), &sunxi_clk_periph_dmic }, + {"codec_1x", 0, audio_parents, ARRAY_SIZE(audio_parents), &sunxi_clk_periph_codec_1x }, + {"codec_4x", 0, audio_parents, ARRAY_SIZE(audio_parents), &sunxi_clk_periph_codec_4x }, + {"usbphy0", 0, hosc_parents, ARRAY_SIZE(hosc_parents), &sunxi_clk_periph_usbphy0 }, + {"usbphy1", 0, hosc_parents, ARRAY_SIZE(hosc_parents), &sunxi_clk_periph_usbphy1 }, + {"usbohci0", 0, ahb3mod_parents, ARRAY_SIZE(ahb3mod_parents), &sunxi_clk_periph_usbohci0 }, + {"usbohci0_12m", 0, usbohci_12m_parents, ARRAY_SIZE(usbohci_12m_parents), &sunxi_clk_periph_usbohci0_12m }, + {"usbohci1", 0, ahb3mod_parents, ARRAY_SIZE(ahb3mod_parents), &sunxi_clk_periph_usbohci1 }, + {"usbohci1_12m", 0, usbohci_12m_parents, ARRAY_SIZE(usbohci_12m_parents), &sunxi_clk_periph_usbohci1_12m }, + {"usbehci0", 0, ahb3mod_parents, ARRAY_SIZE(ahb3mod_parents), &sunxi_clk_periph_usbehci0 }, + {"usbehci1", 0, ahb3mod_parents, ARRAY_SIZE(ahb3mod_parents), &sunxi_clk_periph_usbehci1 }, + {"usbotg", 0, ahb3mod_parents, ARRAY_SIZE(ahb3mod_parents), &sunxi_clk_periph_usbotg }, + {"display_top", 0, ahb3mod_parents, ARRAY_SIZE(ahb3mod_parents), &sunxi_clk_periph_display_top }, + {"tcon_lcd0", 0, tcon_lcd_parents, ARRAY_SIZE(tcon_lcd_parents), &sunxi_clk_periph_tcon_lcd0 }, + {"ledc", 0, ledc_parents, ARRAY_SIZE(ledc_parents), &sunxi_clk_periph_ledc }, + {"pio", 0, apb1mod_parents, ARRAY_SIZE(apb1mod_parents), &sunxi_clk_periph_pio }, + {"mad", 0, apb1mod_parents, ARRAY_SIZE(apb1mod_parents), &sunxi_clk_periph_mad }, + {"lpsd", 0, lpsd_parents, ARRAY_SIZE(lpsd_parents), &sunxi_clk_periph_lpsd }, +}; + +struct periph_init_data sunxi_periphs_cpus_init[] = { + {"cpurcpus_pll", CLK_GET_RATE_NOCACHE|CLK_READONLY, cpurcpus_pll_parents, ARRAY_SIZE(cpurcpus_pll_parents), &sunxi_clk_periph_cpurcpus_pll }, + {"cpurcpus", CLK_GET_RATE_NOCACHE|CLK_READONLY, cpurcpus_parents, ARRAY_SIZE(cpurcpus_parents), &sunxi_clk_periph_cpurcpus }, + {"cpurahbs", CLK_GET_RATE_NOCACHE|CLK_READONLY, cpurahbs_parents, ARRAY_SIZE(cpurahbs_parents), &sunxi_clk_periph_cpurahbs }, + {"cpurapbs1", CLK_GET_RATE_NOCACHE|CLK_READONLY, cpurapbs1_parents, ARRAY_SIZE(cpurapbs1_parents), &sunxi_clk_periph_cpurapbs1 }, + {"cpurapbs2_pll", CLK_GET_RATE_NOCACHE|CLK_READONLY, cpurapbs2_pll_parents, ARRAY_SIZE(cpurapbs2_pll_parents), &sunxi_clk_periph_cpurapbs2_pll }, + {"cpurapbs2", CLK_GET_RATE_NOCACHE|CLK_READONLY, cpurapbs2_parents, ARRAY_SIZE(cpurapbs2_parents), &sunxi_clk_periph_cpurapbs2 }, + {"losc_out", 0, losc_parents, ARRAY_SIZE(losc_parents), &sunxi_clk_periph_losc_out }, + {"cpurpio", CLK_GET_RATE_NOCACHE|CLK_READONLY, cpurpio_parents, ARRAY_SIZE(cpurpio_parents), &sunxi_clk_periph_cpurpio }, + {"cpurcir", CLK_GET_RATE_NOCACHE, ir_parents, ARRAY_SIZE(ir_parents), &sunxi_clk_periph_cpurcir }, + {"spwm", 0, spwm_parents, ARRAY_SIZE(spwm_parents), &sunxi_clk_periph_spwm }, +}; + + +/* + * sunxi_clk_get_factor_by_name() - Get factor clk init config + */ +struct factor_init_data *sunxi_clk_get_factor_by_name(const char *name) +{ + struct factor_init_data *factor; + int i; + + /* get pll clk init config */ + for (i = 0; i < ARRAY_SIZE(sunxi_factos); i++) { + factor = &sunxi_factos[i]; + if (strcmp(name, factor->name)) + continue; + return factor; + } + + return NULL; +} +struct periph_init_data *sunxi_clk_get_periph_rtc_by_name(const char *name) +{ + return NULL; +}; +/* + * sunxi_clk_get_periph_by_name() - Get periph clk init config + */ +struct periph_init_data *sunxi_clk_get_periph_by_name(const char *name) +{ + struct periph_init_data *perpih; + int i; + + for (i = 0; i < ARRAY_SIZE(sunxi_periphs_init); i++) { + perpih = &sunxi_periphs_init[i]; + if (strcmp(name, perpih->name)) + continue; + return perpih; + } + + return NULL; +} + +/* + * sunxi_clk_get_periph_cpus_by_name() - Get periph clk init config + */ +struct periph_init_data *sunxi_clk_get_periph_cpus_by_name(const char *name) +{ + struct periph_init_data *perpih; + int i; + + for (i = 0; i < ARRAY_SIZE(sunxi_periphs_cpus_init); i++) { + perpih = &sunxi_periphs_cpus_init[i]; + if (strcmp(name, perpih->name)) + continue; + return perpih; + } + + return NULL; +} +struct periph_init_data *sunxi_cpus_clk_get_periph_by_name(const char *name) +{ + struct periph_init_data *perpih; + int i; + + for (i = 0; i < ARRAY_SIZE(sunxi_periphs_cpus_init); i++) { + perpih = &sunxi_periphs_cpus_init[i]; + if (strcmp(name, perpih->name)) + continue; + return perpih; + } + + return NULL; +} + +void __init sunxi_clocks_init(struct device_node *node) +{ + sunxi_clk_base = of_iomap(node, 0); + sunxi_clk_cpus_base = of_iomap(node, 1); + sunxi_clk_periph_losc_out.gate.bus = of_iomap(node, 2); + /*do some initialize arguments here*/ + sunxi_clk_factor_initlimits(); +} +void __init sunxi_cpu_clocks_init(struct device_node *node) {}