diff -drupN a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
--- a/arch/arm/mm/proc-v7.S	2018-08-06 17:23:04.000000000 +0300
+++ b/arch/arm/mm/proc-v7.S	2022-06-12 05:28:14.000000000 +0300
@@ -93,7 +93,7 @@ ENDPROC(cpu_v7_dcache_clean_area)
 
 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
 .globl	cpu_v7_suspend_size
-.equ	cpu_v7_suspend_size, 4 * 9
+.equ	cpu_v7_suspend_size, 4 * 11
 #ifdef CONFIG_ARM_CPU_SUSPEND
 ENTRY(cpu_v7_do_suspend)
 	stmfd	sp!, {r4 - r11, lr}
@@ -112,7 +112,13 @@ ENTRY(cpu_v7_do_suspend)
 	mrc	p15, 0, r8, c1, c0, 0	@ Control register
 	mrc	p15, 0, r9, c1, c0, 1	@ Auxiliary control register
 	mrc	p15, 0, r10, c1, c0, 2	@ Co-processor access control
-	stmia	r0, {r5 - r11}
+	stmia	r0!, {r5 - r11}
+#ifdef CONFIG_ARM_LPAE
+	mrrc	p15, 1, r4, r5, c2	@ TTB 0
+#else
+	mrc	p15, 0, r4, c2, c0, 0	@ TTB 0
+#endif
+	stmia	r0, {r4 - r5}
 	ldmfd	sp!, {r4 - r11, pc}
 ENDPROC(cpu_v7_do_suspend)
 
@@ -123,7 +129,7 @@ ENTRY(cpu_v7_do_resume)
 	ldmia	r0!, {r4 - r5}
 	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
 	mcr	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
-	ldmia	r0, {r5 - r11}
+	ldmia	r0!, {r5 - r11}
 #ifdef CONFIG_MMU
 	mcr	p15, 0, ip, c8, c7, 0	@ invalidate TLBs
 	mcr	p15, 0, r6, c3, c0, 0	@ Domain ID
@@ -133,14 +139,14 @@ ENTRY(cpu_v7_do_resume)
 #else
 	ALT_SMP(orr	r1, r1, #TTB_FLAGS_SMP)
 	ALT_UP(orr	r1, r1, #TTB_FLAGS_UP)
-	mcr	p15, 0, r1, c2, c0, 0	@ TTB 0
+	mcr	p15, 0, r1, c2, c0, 0	@ TTB 0, it is idmap_pgd to prepare enable mmu
 	mcr	p15, 0, r7, c2, c0, 1	@ TTB 1
 #endif
 	mcr	p15, 0, r11, c2, c0, 2	@ TTB control register
 	ldr	r4, =PRRR		@ PRRR
-	ldr	r5, =NMRR		@ NMRR
 	mcr	p15, 0, r4, c10, c2, 0	@ write PRRR
-	mcr	p15, 0, r5, c10, c2, 1	@ write NMRR
+	ldr	r4, =NMRR		@ NMRR
+	mcr	p15, 0, r4, c10, c2, 1	@ write NMRR
 #endif	/* CONFIG_MMU */
 	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary control register
 	teq	r4, r9			@ Is it already set?
@@ -148,6 +154,7 @@ ENTRY(cpu_v7_do_resume)
 	mcr	p15, 0, r10, c1, c0, 2	@ Co-processor access control
 	isb
 	dsb
+	ldmia	r0, {r1 - r2}		@ TTBR0 for current
 	mov	r0, r8			@ control register
 	b	cpu_resume_mmu
 ENDPROC(cpu_v7_do_resume)