diff --git a/Makefile b/Makefile
index cdc9cf7c..f38bdbae 100644
--- a/Makefile
+++ b/Makefile
@@ -398,7 +398,7 @@ LINUXINCLUDE := \
KBUILD_CPPFLAGS := -D__KERNEL__
-KBUILD_CFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \
+KBUILD_CFLAGS := -Wno-error -Wundef -Wstrict-prototypes -Wno-trigraphs \
-fno-strict-aliasing -fno-common \
-Werror-implicit-function-declaration \
-Wno-format-security \
@@ -940,9 +940,51 @@ define filechk_kernel.release
echo "$(KERNELVERSION)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))"
endef
+MS_KERNEL_TYPE :=
+ifneq ($(CONFIG_MS_KERNEL_TYPE),"")
+ MS_KERNEL_TYPE=--lib_type $(CONFIG_MS_KERNEL_TYPE)
+endif
+MS_PLATFORM_ID :=
+ifneq ($(CONFIG_ARCH_CEDRIC),)
+MS_PLATFORM_ID := C3
+endif
+ifneq ($(CONFIG_ARCH_INFINITY),)
+MS_PLATFORM_ID := I1
+endif
+ifneq ($(CONFIG_ARCH_INFINITY3),)
+MS_PLATFORM_ID := I3
+endif
+ifneq ($(CONFIG_ARCH_CHICAGO),)
+MS_PLATFORM_ID := C4
+endif
+
+
+COMMITNUMBER := g$(shell git log --format=%h -n 1 2> /dev/null)
+BRANCH_ID := $(shell git rev-parse --abbrev-ref HEAD 2> /dev/null | sed -e 's/\//_/g')
+
+ifeq ($(COMMITNUMBER),g)
+file := gitInformation.txt
+gitLog := $(shell strings ${file})
+gitTemp := $(subst \#, ,$(gitLog))
+COMMITNUMBER := g$(word 1, $(gitTemp))
+BRANCH_ID := g$(word 2, $(gitTemp))
+endif
+
# Store (new) KERNELRELEASE string in include/config/kernel.release
include/config/kernel.release: include/config/auto.conf FORCE
$(call filechk,kernel.release)
+# @python scripts/ms_gen_mvxv_h.py drivers/mstar/include/ms_version.h --comp_id KL_LX318 \
+# --changelist G$$(git describe --match CL* --tags --long | cut -b 12-18 | awk '{print toupper($$0)}')
+ifeq ($(MS_PLATFORM_ID),)
+ @echo "ERROR!! MS_PLATOFRM_ID is empty!!"; /bin/false
+else
+ @echo ' MVXV'
+ @echo ' changelist ${COMMITNUMBER}'
+ @echo ' BRANCHID ${BRANCH_ID} '
+ @python scripts/ms_gen_mvxv_h.py drivers/mstar/include/ms_version.h --comp_id KL_LX318 \
+ --changelist $(COMMITNUMBER) --chip_id $(MS_PLATFORM_ID) --branch $(BRANCH_ID) $(MS_KERNEL_TYPE)
+endif
+
# Things we need to do before we recursively start building the kernel
@@ -1092,6 +1134,9 @@ all: modules
# A module can be listed more than once in obj-m resulting in
# duplicate lines in modules.order files. Those are removed
# using awk while concatenating to the final file.
+ifdef CONFIG_XIP_KERNEL
+ MODULE_PACK_OPTIONS += "-x"
+endif
PHONY += modules
modules: $(vmlinux-dirs) $(if $(KBUILD_BUILTIN),vmlinux) modules.builtin
diff --git a/README b/README
index a24ec89b..a2930faf 100644
--- a/README
+++ b/README
@@ -1,5 +1,6 @@
Linux kernel release 3.x
+
These are the release notes for Linux version 3. Read them carefully,
as they tell you what this is all about, explain how to install the
kernel, and what to do if something goes wrong.
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 89c4b5cc..75fe0358 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -214,6 +214,9 @@ config FIQ
config NEED_RET_TO_USER
bool
+config MULTIPLATFORM_XIP_CAPABLE
+ bool
+
config ARCH_MTD_XIP
bool
@@ -310,7 +313,7 @@ config ARCH_MULTIPLATFORM
depends on MMU
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARM_HAS_SG_CHAIN
- select ARM_PATCH_PHYS_VIRT
+ select ARM_PATCH_PHYS_VIRT if !XIP_KERNEL
select AUTO_ZRELADDR
select CLKSRC_OF
select COMMON_CLK
@@ -898,6 +901,8 @@ source "arch/arm/mach-meson/Kconfig"
source "arch/arm/mach-msm/Kconfig"
+source "arch/arm/mach-mstar/Kconfig"
+
source "arch/arm/mach-moxart/Kconfig"
source "arch/arm/mach-mv78xx0/Kconfig"
@@ -1712,6 +1717,7 @@ config FORCE_MAX_ZONEORDER
range 11 64 if ARCH_SHMOBILE_LEGACY
default "12" if SOC_AM33XX
default "9" if SA1111 || ARCH_EFM32
+ default "10" if ARCH_MSTAR
default "11"
help
The kernel memory allocator divides physically contiguous memory
@@ -1973,7 +1979,7 @@ endchoice
config XIP_KERNEL
bool "Kernel Execute-In-Place from ROM"
- depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
+ depends on (!ARM_LPAE && !ARCH_MULTIPLATFORM) || (!ARM_LPAE && MULTIPLATFORM_XIP_CAPABLE)
help
Execute-In-Place allows the kernel to run from non-volatile storage
directly addressable by the CPU, such as NOR flash. This saves RAM
@@ -2159,7 +2165,7 @@ config ARCH_HIBERNATION_POSSIBLE
bool
depends on MMU
default y if ARCH_SUSPEND_POSSIBLE
-
+
endmenu
source "net/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index b5d79884..cc30c609 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -179,6 +179,7 @@ machine-$(CONFIG_ARCH_MESON) += meson
machine-$(CONFIG_ARCH_MMP) += mmp
machine-$(CONFIG_ARCH_MOXART) += moxart
machine-$(CONFIG_ARCH_MSM) += msm
+machine-$(CONFIG_ARCH_MSTAR) += mstar
machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0
machine-$(CONFIG_ARCH_MVEBU) += mvebu
machine-$(CONFIG_ARCH_MXC) += imx
@@ -215,6 +216,7 @@ machine-$(CONFIG_ARCH_W90X900) += w90x900
machine-$(CONFIG_ARCH_ZYNQ) += zynq
machine-$(CONFIG_PLAT_SPEAR) += spear
+
# Platform directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
plat-$(CONFIG_ARCH_EXYNOS) += samsung
@@ -318,6 +320,12 @@ $(INSTALL_TARGETS):
%.dtb: | scripts
$(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $(boot)/dts/$@
+ @if [ -e arch/arm/boot/Image ]; then \
+ echo " BNDTB $@"; \
+ python scripts/ms_builtin_dtb_update.py arch/arm/boot/Image arch/arm/boot/dts/$@; \
+ echo; \
+ fi;
+
PHONY += dtbs dtbs_install
dtbs dtbs_install: prepare scripts
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index ec2f8065..c9806770 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -11,6 +11,29 @@
# Copyright (C) 1995-2002 Russell King
#
+
+MKIMAGE_BIN = scripts/mkimage
+MZ_BIN = scripts/mz
+KERNEL_RELEASE_FILE = include/config/kernel.release
+ROOTFS = $(obj)/ramdisk_linaro4.8_minit.img.xz
+
+MS_BUILTIN_DTB=arch/arm/boot/dts/infinity3-BGA128M.dtb
+_BUILTIN_DTB_NAME=$(strip $(shell echo ${CONFIG_MS_BUILTIN_DTB}))
+ifneq ($(_BUILTIN_DTB_NAME),)
+ifneq ($(wildcard arch/arm/boot/dts/$(_BUILTIN_DTB_NAME).dts),)
+MS_BUILTIN_DTB=arch/arm/boot/dts/$(_BUILTIN_DTB_NAME).dtb
+endif
+endif
+
+MS_EXTRA_DTBS=
+ifneq ($(CONFIG_ARCH_INFINITY),)
+MS_EXTRA_DTBS=arch/arm/boot/dts/infinity-fpga.dtb arch/arm/boot/dts/infinity-zebu.dtb
+endif
+
+#ifneq ($(CONFIG_ARCH_INFINITY3),)
+#MS_EXTRA_DTBS=arch/arm/boot/dts/infinity3-fpga.dtb arch/arm/boot/dts/infinity3-fpgaxl.dtb
+#endif
+
ifneq ($(MACHINE),)
include $(srctree)/$(MACHINE)/Makefile.boot
endif
@@ -19,6 +42,7 @@ endif
# ZRELADDR == virt_to_phys(PAGE_OFFSET + TEXT_OFFSET)
# PARAMS_PHYS must be within 4MB of ZRELADDR
# INITRD_PHYS must be in RAM
+LOADADDR := 0x40008000
ZRELADDR := $(zreladdr-y)
PARAMS_PHYS := $(params_phys-y)
INITRD_PHYS := $(initrd_phys-y)
@@ -29,9 +53,19 @@ targets := Image zImage xipImage bootpImage uImage
ifeq ($(CONFIG_XIP_KERNEL),y)
-$(obj)/xipImage: vmlinux FORCE
+$(obj)/xipImage: vmlinux FORCE $(MS_BUILTIN_DTB) $(MS_EXTRA_DTBS)
$(call if_changed,objcopy)
@$(kecho) ' Kernel: $@ is ready (physical address: $(CONFIG_XIP_PHYS_ADDR))'
+ @test "${MS_BUILTIN_DTB}" = "" || \
+ if [ -e ${MS_BUILTIN_DTB} ]; then \
+ echo " BNDTB ${MS_BUILTIN_DTB}"; \
+ python scripts/ms_builtin_dtb_update.py $@ ${MS_BUILTIN_DTB}; \
+ echo; \
+ fi;
+ @python scripts/ms_bin_option_update_int.py $@ '#IMG_SZ#' $$(stat -c %s $@)
+ @python scripts/ms_bin_option_update_int.py $@ '#XIP_PA#' $(CONFIG_XIP_PHYS_ADDR)
+ @echo " xipImage size: $(shell stat -c %s $@) bytes"
+
$(obj)/Image $(obj)/zImage: FORCE
@echo 'Kernel configured for XIP (CONFIG_XIP_KERNEL=y)'
@@ -44,9 +78,87 @@ $(obj)/xipImage: FORCE
@echo 'Kernel not configured for XIP (CONFIG_XIP_KERNEL!=y)'
@false
-$(obj)/Image: vmlinux FORCE
+$(obj)/Image: vmlinux FORCE $(MS_BUILTIN_DTB) $(MS_EXTRA_DTBS)
$(call if_changed,objcopy)
- @$(kecho) ' Kernel: $@ is ready'
+
+ #update builtin DTB
+ @test "${MS_BUILTIN_DTB}" = "" || \
+ if [ -e ${MS_BUILTIN_DTB} ]; then \
+ echo " BNDTB ${MS_BUILTIN_DTB}"; \
+ python scripts/ms_builtin_dtb_update.py $@ ${MS_BUILTIN_DTB}; \
+ echo; \
+ fi;
+
+ #update the image size into Image
+ @python scripts/ms_bin_option_update_int.py $@ '#IMG_SZ#' $$(stat -c %s $@)
+
+ #build Image
+ @LD_ADDR=40008000; \
+ IMGNAME=Linux-`cat $(KERNEL_RELEASE_FILE)`; \
+# if [ -e ${MKIMAGE_BIN} ]; then \
+# ${MKIMAGE_BIN} -A arm -O linux -T kernel -C none -a $${LD_ADDR} -e $${LD_ADDR} -n $${IMGNAME} -d $@ $(obj)/uImage; \
+# echo; \
+# else \
+# echo ">> Can't find $${MKIMAGE}. Please check the u-boot path or build u-boot <<"; \
+# fi; \
+# if [ -e $(ROOTFS) ]; then \
+# ${MKIMAGE_BIN} -A arm -O linux -T multi -C none -a $${LD_ADDR} -e $${LD_ADDR} -n $${IMGNAME} -d $@:$(ROOTFS) $(obj)/kernel.img; \
+# echo; \
+# if [ -e ${MZ_BIN} ]; then \
+# ${MZ_BIN} c $@ $@.mz ; \
+# echo; \
+# ${MKIMAGE_BIN} -A arm -O linux -T multi -C mz -a $${LD_ADDR} -e $${LD_ADDR} -n $${IMGNAME} -d $@.mz:$(ROOTFS) $(obj)/kernel.mz.img; \
+# echo; \
+# fi; \
+# fi;
+ @$(kecho) ' Kernel: $@ is ready'
+ @echo
+ifneq ($(CONFIG_ARCH_INFINITY),)
+ @echo 'Building extra images wifh different DTB for iNfinity:'
+ @echo
+# @if [ -e "arch/arm/boot/dts/infinity-zebu.dtb" ]; then \
+# echo " IMAGE $(obj)/Image-zebu"; \
+# cp -f $(obj)/Image $(obj)/Image-zebu; \
+# echo " BNDTB infinity-zebu.dtb"; \
+# python scripts/ms_builtin_dtb_update.py $(obj)/Image-zebu "arch/arm/boot/dts/infinity-zebu.dtb"; \
+# echo; \
+# fi;
+
+ @if [ -e "arch/arm/boot/dts/infinity-fpga.dtb" ]; then \
+ echo " IMAGE $(obj)/Image-fpga"; \
+ cp -f $(obj)/Image $(obj)/Image-fpga; \
+ echo " BNDTB infinity-fpga.dtb"; \
+ python scripts/ms_builtin_dtb_update.py $(obj)/Image-fpga "arch/arm/boot/dts/infinity-fpga.dtb"; \
+ echo; \
+ fi;
+endif
+ifneq ($(CONFIG_ARCH_INFINITY3),)
+# @echo 'Building extra images wifh different DTB for iNfinity3:'
+# @echo
+# @if [ -e "arch/arm/boot/dts/inf3-zebu.dtb" ]; then \
+# echo " IMAGE $(obj)/Image-zebu"; \
+# cp -f $(obj)/Image $(obj)/Image-zebu; \
+# echo " BNDTB inf3-zebu.dtb"; \
+# python scripts/ms_builtin_dtb_update.py $(obj)/Image-zebu "arch/arm/boot/dts/inf3-zebu.dtb"; \
+# echo; \
+# fi;
+
+# @if [ -e "arch/arm/boot/dts/infinity3-fpga.dtb" ]; then \
+# echo " IMAGE $(obj)/Image-fpga"; \
+# cp -f $(obj)/Image $(obj)/Image-fpga; \
+# echo " BNDTB infinity3-fpga.dtb"; \
+# python scripts/ms_builtin_dtb_update.py $(obj)/Image-fpga "arch/arm/boot/dts/infinity3-fpga.dtb"; \
+# echo; \
+# fi;
+## Run Kernel file system on norflash with infinity3-fpgaxl.dts
+# @if [ -e "arch/arm/boot/dts/infinity3-fpgaxl.dtb" ]; then \
+# echo " IMAGE $(obj)/Image-fpgaxl"; \
+# cp -f $(obj)/Image $(obj)/Image-fpgaxl; \
+# echo " BNDTB infinity3-fpgaxl.dtb"; \
+# python scripts/ms_builtin_dtb_update.py $(obj)/Image-fpgaxl "arch/arm/boot/dts/infinity3-fpgaxl.dtb"; \
+# echo; \
+# fi;
+endif
$(obj)/compressed/vmlinux: $(obj)/Image FORCE
$(Q)$(MAKE) $(build)=$(obj)/compressed $@
diff --git a/arch/arm/boot/dts/cedric-154a.dts b/arch/arm/boot/dts/cedric-154a.dts
new file mode 100644
index 00000000..d4e5e6ce
--- /dev/null
+++ b/arch/arm/boot/dts/cedric-154a.dts
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "cedric.dtsi"
+
+/ {
+ model = "Cedric MST154A Board";
+ compatible = "mstar,cedric";
+
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/ram rootwait";
+ /*bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/ram rootwait sysp=squashfs:/dev/block/mtdblock0 datap=jffs2:/dev/block/mtdblock1";*/
+
+ linux,initrd-start = <0x45000000>;
+ linux,initrd-end = <0x45020000>;
+ };
+
+
+
+ memory {
+ reg = <0x40000000 0x10000000>;
+ };
+
+ sysp:rammtd@0 {
+ compatible = "mtd-ram";
+ reg= <0x50000000 0x02000000>;
+ bank-width = <1>;
+ };
+
+ datap:rammtd@1 {
+ compatible = "mtd-ram";
+ reg= <0x52000000 0x00020000>;
+ bank-width = <1>;
+ };
+
+};
diff --git a/arch/arm/boot/dts/cedric-clks.dtsi b/arch/arm/boot/dts/cedric-clks.dtsi
new file mode 100644
index 00000000..6ca5c23f
--- /dev/null
+++ b/arch/arm/boot/dts/cedric-clks.dtsi
@@ -0,0 +1,1153 @@
+&clks {
+
+ clk_mpll_432M: clk_mpll_432M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <432000000>;
+ };
+
+ clk_mpll_288M: clk_mpll_288M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <288000000>;
+ };
+
+ clk_utmi_240M: clk_utmi_240M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <240000000>;
+ };
+
+ clk_mpll_216M: clk_mpll_216M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <216000000>;
+ };
+
+ clk_utmi_192M: clk_utmi_192M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <192000000>;
+ };
+
+ clk_mpll_172M: clk_mpll_172M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <172000000>;
+ };
+
+ clk_utmi_160M: clk_utmi_160M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <160000000>;
+ };
+
+ clk_mpll_123M: clk_mpll_123M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <123000000>;
+ };
+
+ clk_mpll_86M: clk_mpll_86M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <86000000>;
+ };
+
+ clk_mpll_144M: clk_mpll_144M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_mpll_288M>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ clk_mpll_72M: clk_mpll_72M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_mpll_288M>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ clk_mpll_36M: clk_mpll_36M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_mpll_288M>;
+ clock-mult = <1>;
+ clock-div = <8>;
+ };
+
+ clk_mpll_108M: clk_mpll_108M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_mpll_216M>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ clk_mpll_54M: clk_mpll_54M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_mpll_216M>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ clk_mpll_27M: clk_mpll_27M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_mpll_216M>;
+ clock-mult = <1>;
+ clock-div = <8>;
+ };
+
+ clk_mpll_61M: clk_mpll_61M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_mpll_123M>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ clk_mpll_43M: clk_mpll_43M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_mpll_86M>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
+
+ clk_mpll_21M: clk_mpll_21M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_mpll_86M>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ clk_mpll_5M: clk_mpll_5M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_mpll_86M>;
+ clock-mult = <1>;
+ clock-div = <16>;
+ };
+
+ clk_utmi_48M: clk_utmi_48M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_utmi_192M>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ clk_utmi_40M: clk_utmi_40M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_utmi_160M>;
+ clock-mult = <1>;
+ clock-div = <4>;
+ };
+
+ clk_utmi_32M: clk_utmi_32M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_utmi_160M>;
+ clock-mult = <1>;
+ clock-div = <5>;
+ };
+
+ clk_utmi_20M: clk_utmi_20M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_utmi_160M>;
+ clock-mult = <1>;
+ clock-div = <8>;
+ };
+
+ clk_xtali_12M: clk_xtali_12M {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+ };
+
+ clk_xtali_1M: clk_xtali_1M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_xtali_12M>;
+ clock-mult = <1>;
+ clock-div = <8>;
+ };
+
+ clk_xtali_750K: clk_xtali_750K {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_xtali_12M>;
+ clock-mult = <1>;
+ clock-div = <16>;
+ };
+
+ clk_xtali_300K: clk_xtali_300K {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_xtali_12M>;
+ clock-mult = <1>;
+ clock-div = <40>;
+ };
+
+ clk_xtali_187K: clk_xtali_187K {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_xtali_12M>;
+ clock-mult = <1>;
+ clock-div = <64>;
+ };
+
+ clk_xtali_93K: clk_xtali_93K {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_xtali_12M>;
+ clock-mult = <1>;
+ clock-div = <128>;
+ };
+
+ clk_RTC_CLK_32K: clk_RTC_CLK_32K {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ };
+
+ clk_miupll_clk: clk_miupll_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_ddrpll_clk: clk_ddrpll_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_lpll_clk: clk_lpll_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_cpupll_clk: clk_cpupll_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_riu_w_clk_in: clk_riu_w_clk_in {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_riu_w_clk_top: clk_riu_w_clk_top {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_riu_w_clk_sc_gp: clk_riu_w_clk_sc_gp {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_riu_w_clk_vhe_gp: clk_riu_w_clk_vhe_gp {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_riu_w_clk_hemcu_gp: clk_riu_w_clk_hemcu_gp {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_riu_w_clk_mipi_if_gp: clk_riu_w_clk_mipi_if_gp {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_riu_w_clk_mcu_if_gp: clk_riu_w_clk_mcu_if_gp {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_clk_fuart0_synth_out: clk_clk_fuart0_synth_out {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_clk_miu: clk_clk_miu {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_clk_miu_p: clk_clk_miu_p {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_clk_miu_vhe_gp_p: clk_clk_miu_vhe_gp_p {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_clk_miu_sc_gp_p: clk_clk_miu_sc_gp_p {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_clk_miu2x_p: clk_clk_miu2x_p {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_clk_mcu_p: clk_clk_mcu_p {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_clk_mcu_pm_p: clk_clk_mcu_pm_p {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_clk_isp_p: clk_clk_isp_p {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_clk_fclk1_p: clk_clk_fclk1_p {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_clk_sdio_p: clk_clk_sdio_p {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_clk_fcie_p: clk_clk_fcie_p {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_clk_tck_buf: clk_clk_tck_buf {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_pad2isp_sr_pclk: clk_pad2isp_sr_pclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_clk_csi2_mac_p: clk_clk_csi2_mac_p {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_ccir_in_clk: clk_ccir_in_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_clk_eth_buf: clk_clk_eth_buf {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_clk_rmii_buf: clk_clk_rmii_buf {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_clk_emac_testrx125_in_lan: clk_clk_emac_testrx125_in_lan {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clk_miu: clk_miu {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_mpll_216M>, <&clk_miupll_clk>;
+ bist = <0>;
+ glitch = <1>;
+ };
+
+ clk_miu_ff: clk_miu_ff {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_sc_gp: clk_miu_sc_gp {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_vhe_gp: clk_miu_vhe_gp {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_dig: clk_miu_dig {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_xd2miu: clk_miu_xd2miu {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_urdma: clk_miu_urdma {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_bdma: clk_miu_bdma {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_vhe: clk_miu_vhe {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_vhe_gp_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_mfeh: clk_miu_mfeh {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_sc_gp_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_mfe: clk_miu_mfe {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_sc_gp_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_jpe1: clk_miu_jpe1 {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_sc_gp_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_jpe0: clk_miu_jpe0 {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_sc_gp_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_bach: clk_miu_bach {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_sc_gp_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_file: clk_miu_file {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_sc_gp_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_uhc0: clk_miu_uhc0 {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_sc_gp_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_emac: clk_miu_emac {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_sc_gp_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_cmdq: clk_miu_cmdq {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_sc_gp_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_isp_dnr: clk_miu_isp_dnr {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_sc_gp_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_isp_rot: clk_miu_isp_rot {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_sc_gp_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_isp_dma: clk_miu_isp_dma {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_sc_gp_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_isp_sta: clk_miu_isp_sta {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_sc_gp_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_gop: clk_miu_gop {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_sc_gp_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_sc_dnr: clk_miu_sc_dnr {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_sc_gp_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_sc_dnr_sad: clk_miu_sc_dnr_sad {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_sc_gp_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_sc_crop: clk_miu_sc_crop {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_sc_gp_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_sc1_frm: clk_miu_sc1_frm {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_sc_gp_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_sc1_snp: clk_miu_sc1_snp {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_sc_gp_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_sc1_snpi: clk_miu_sc1_snpi {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_sc_gp_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_sc1_dbg: clk_miu_sc1_dbg {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_sc_gp_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_sc2_frm: clk_miu_sc2_frm {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_sc_gp_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_sc2_snpi: clk_miu_sc2_snpi {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_sc_gp_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_sc3_frm: clk_miu_sc3_frm {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_sc_gp_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_fcie: clk_miu_fcie {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_sc_gp_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_sdio: clk_miu_sdio {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_sc_gp_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_riu: clk_riu {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_riu_w_clk_top>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_riu_nogating: clk_riu_nogating {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_riu_w_clk_in>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_riu_sc_gp: clk_riu_sc_gp {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_riu_w_clk_sc_gp>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_riu_vhe_gp: clk_riu_vhe_gp {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_riu_w_clk_vhe_gp>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_riu_hemcu_gp: clk_riu_hemcu_gp {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_riu_w_clk_hemcu_gp>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_riu_mipi_gp: clk_riu_mipi_gp {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_riu_w_clk_mipi_if_gp>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_riu_mcu_if: clk_riu_mcu_if {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_riu_w_clk_mcu_if_gp>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu2x: clk_miu2x {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_ddrpll_clk>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_axi2x: clk_axi2x {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu2x_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_ddr_syn: clk_ddr_syn {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_mpll_432M>, <&clk_mpll_216M>, <&clk_xtali_12M>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miu_rec: clk_miu_rec {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_xtali_1M>, <&clk_xtali_750K>, <&clk_xtali_187K>, <&clk_xtali_93K>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_tck: clk_tck {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_tck_buf>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_mcu: clk_mcu {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_mpll_216M>, <&clk_mpll_172M>, <&clk_mpll_144M>, <&clk_mpll_108M>;
+ bist = <0>;
+ glitch = <1>;
+ };
+
+ clk_riubrdg: clk_riubrdg {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_mcu_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_bdma: clk_bdma {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_spi: clk_spi {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_mpll_216M>, <&clk_mpll_108M>, <&clk_mpll_86M>, <&clk_mpll_72M>;
+ bist = <0>;
+ glitch = <1>;
+ };
+
+ clk_uart0: clk_uart0 {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_mpll_172M>, <&clk_mpll_144M>, <&clk_xtali_12M>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_uart1: clk_uart1 {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_mpll_172M>, <&clk_mpll_144M>, <&clk_xtali_12M>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_fuart0_synth_in: clk_fuart0_synth_in {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_mpll_432M>, <&clk_mpll_216M>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_fuart: clk_fuart {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_mpll_172M>, <&clk_mpll_144M>, <&clk_xtali_12M>, <&clk_clk_fuart0_synth_out>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_mspi0: clk_mspi0 {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_mpll_108M>, <&clk_mpll_54M>, <&clk_xtali_12M>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_mspi1: clk_mspi1 {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_mpll_108M>, <&clk_mpll_54M>, <&clk_xtali_12M>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miic0: clk_miic0 {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_mpll_72M>, <&clk_mpll_54M>, <&clk_xtali_12M>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_miic1: clk_miic1 {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_mpll_72M>, <&clk_mpll_54M>, <&clk_xtali_12M>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_bist: clk_bist {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_mpll_172M>, <&clk_mpll_108M>, <&clk_mpll_54M>, <&clk_xtali_12M>;
+ bist = <1>;
+ glitch = <0>;
+ };
+
+ clk_xtali: clk_xtali {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_xtali_12M>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_live: clk_live {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_xtali_12M>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_sr_mclk: clk_sr_mclk {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_mpll_27M>, <&clk_mpll_21M>, <&clk_xtali_12M>, <&clk_mpll_5M>, <&clk_mpll_36M>, <&clk_mpll_54M>, <&clk_mpll_43M>, <&clk_mpll_61M>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_bist_pm: clk_bist_pm {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_mpll_172M>, <&clk_mpll_108M>, <&clk_mpll_54M>, <&clk_xtali_12M>;
+ bist = <1>;
+ glitch = <0>;
+ };
+
+ clk_bist_vhe_gp: clk_bist_vhe_gp {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_mpll_172M>, <&clk_mpll_108M>, <&clk_mpll_54M>, <&clk_xtali_12M>;
+ bist = <1>;
+ glitch = <0>;
+ };
+
+ clk_vhe: clk_vhe {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_utmi_240M>, <&clk_mpll_216M>, <&clk_utmi_192M>, <&clk_utmi_160M>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_xtali_sc_gp: clk_xtali_sc_gp {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_xtali_12M>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_bist_sc_gp: clk_bist_sc_gp {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_mpll_172M>, <&clk_mpll_108M>, <&clk_mpll_54M>, <&clk_xtali_12M>;
+ bist = <1>;
+ glitch = <0>;
+ };
+
+ clk_imi: clk_imi {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_emac_ahb: clk_emac_ahb {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_mpll_144M>, <&clk_mpll_123M>, <&clk_mpll_86M>, <&clk_clk_emac_testrx125_in_lan>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_mfe: clk_mfe {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_mpll_288M>, <&clk_utmi_240M>, <&clk_utmi_192M>, <&clk_mpll_123M>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_jpe: clk_jpe {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_mpll_288M>, <&clk_mpll_216M>, <&clk_mpll_54M>, <&clk_mpll_27M>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_aesdma: clk_aesdma {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_mpll_86M>, <&clk_mpll_172M>;
+ bist = <0>;
+ glitch = <1>;
+ };
+
+ clk_sdio: clk_sdio {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_utmi_48M>, <&clk_mpll_43M>, <&clk_utmi_40M>, <&clk_mpll_36M>, <&clk_utmi_32M>, <&clk_utmi_20M>, <&clk_xtali_12M>, <&clk_xtali_300K>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_fcie: clk_fcie {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_mpll_72M>, <&clk_mpll_61M>, <&clk_mpll_54M>, <&clk_xtali_12M>, <&clk_mpll_86M>, <&clk_utmi_48M>, <&clk_mpll_43M>, <&clk_utmi_40M>, <&clk_mpll_36M>, <&clk_utmi_32M>, <&clk_utmi_20M>, <&clk_mpll_5M>, <&clk_xtali_300K>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_sdio: clk_sdio {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_sdio_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_fcie: clk_fcie {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_fcie_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_ecc: clk_ecc {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_utmi_160M>, <&clk_mpll_108M>, <&clk_mpll_54M>, <&clk_xtali_12M>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_sr: clk_sr {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_pad2isp_sr_pclk>, <&clk_clk_csi2_mac_p>, <&clk_utmi_40M>, <&clk_mpll_86M>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_isp: clk_isp {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_mpll_123M>, <&clk_mpll_86M>, <&clk_mpll_72M>, <&clk_mpll_54M>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_idclk: clk_idclk {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_isp_p>, <&clk_ccir_in_clk>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_fclk1: clk_fclk1 {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_mpll_172M>, <&clk_mpll_86M>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_fclk2: clk_fclk2 {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_mpll_172M>, <&clk_mpll_86M>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_odclk: clk_odclk {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_mpll_86M>, <&clk_mpll_43M>, <&clk_mpll_21M>, <&clk_lpll_clk>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_gop: clk_gop {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_fclk1_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_nlm: clk_nlm {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_miu_p>, <&clk_clk_fclk1_p>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_emac_tx: clk_emac_tx {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_eth_buf>, <&clk_clk_rmii_buf>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_emac_rx: clk_emac_rx {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_eth_buf>, <&clk_clk_rmii_buf>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_emac_tx_ref: clk_emac_tx_ref {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_rmii_buf>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_emac_rx_ref: clk_emac_rx_ref {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_clk_rmii_buf>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_hemcu_216m: clk_hemcu_216m {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_mpll_216M>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_csi_mac: clk_csi_mac {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_xtali_12M>, <&clk_mpll_216M>, <&clk_mpll_288M>, <&clk_mpll_172M>, <&clk_mpll_123M>, <&clk_mpll_86M>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_mac_lptx: clk_mac_lptx {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_xtali_12M>, <&clk_mpll_216M>, <&clk_mpll_288M>, <&clk_mpll_172M>, <&clk_mpll_123M>, <&clk_mpll_86M>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+ clk_ns: clk_ns {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&clk_xtali_12M>, <&clk_mpll_216M>;
+ bist = <0>;
+ glitch = <0>;
+ };
+
+};
\ No newline at end of file
diff --git a/arch/arm/boot/dts/cedric.dtsi b/arch/arm/boot/dts/cedric.dtsi
new file mode 100644
index 00000000..9b14175c
--- /dev/null
+++ b/arch/arm/boot/dts/cedric.dtsi
@@ -0,0 +1,260 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <../../../drivers/mstar/include/cedric/irqs.h>
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "mstar,cedric";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0x0>;
+ };
+
+ };
+
+ xtal: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ aliases {
+ console = &uart0;
+ serial0 = &uart0;
+ sdmmc0 = &sd0;
+ sdmmc1 = &sd1;
+ sdmmc2 = &sd2;
+ iic0 = &i2c0;
+ iic1 = &i2c1;
+ };
+
+
+
+ soc {
+
+ compatible = "simple-bus";
+ interrupt-parent = <&intrctl>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xFFFFFFFF>;
+
+ intrctl: interrupt-controller@0 {
+ compatible = "mstar,intrctl-cedric";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
+ cpuclk: clk@1F221800 {
+ compatible = "mstar,cedric-cpuclk";
+ #clock-cells = <1>;
+ reg = <0x1F221800 0x100>;
+ clocks = <&xtal>;
+ };
+
+
+ timer_clocksource: timer@16000200 {
+ compatible = "mstar,arm-gt-clocksource";
+ reg = <0x16000200 0x100>;
+ clocks = <&cpuclk 1>;
+ };
+
+
+ timer_clockevent: timer@1F006040 {
+ compatible = "mstar,piu-clockevent";
+ reg = <0x1F006040 0x100>;
+ interrupts=;
+ clocks = <&xtal>;
+ };
+
+ uart0: uart@1F201300 {
+ compatible = "mstar,uart";
+ reg = <0x1F201300 0x100>;
+ interrupts= ;
+ clocks = <&uart0clk>;
+ tolerance = <2>;
+ status = "ok";
+ };
+
+ emmc:emmc0{
+ compatible = "mstar,emmc-cedric";
+// reg = <0x1F201300 0x100>;
+ interrupts=;
+ };
+
+ sd0: sd@0 {
+ compatible = "mstar,sdmmc-cedric";
+// reg = <0x1F201300 0x100>;
+ interrupts=,;
+ };
+
+ sd1: sd@1 {
+ compatible = "mstar,sdmmc-cedric";
+// reg = <0x1F201300 0x100>;
+ interrupts=,;
+ };
+
+ sd2: sd@2 {
+ compatible = "mstar,sdmmc-cedric";
+// reg = <0x1F201300 0x100>;
+ interrupts=,;
+ };
+
+ sound {
+ compatible = "mstar,bach-audio";
+// reg = <0x1F000000 0x1000000>;
+ interrupts=;
+ playback-volume-level=<64>; //0~76
+ capture-volume-level=<64>;
+ micin-gain-level=<0>; //0~5
+ linein-gain-level=<1>;//0~6
+ lineout-gain-level=<1>;//0~2
+ };
+
+ mpll_442M: mpll_442M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&xtal>;
+ clock-mult = <34>;
+ clock-div = <2>;
+ };
+
+ mpll_221M: mpll_221M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&xtal>;
+ clock-mult = <34>;
+ clock-div = <4>;
+ };
+
+ mpll_176M: mpll_176M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&xtal>;
+ clock-mult = <34>;
+ clock-div = <5>;
+ };
+
+ mpll_147M: mpll_147M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&xtal>;
+ clock-mult = <34>;
+ clock-div = <6>;
+ };
+
+ mpll_126M: mpll_126M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&xtal>;
+ clock-mult = <34>;
+ clock-div = <7>;
+ };
+
+ mpll_110M: mpll_110M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&xtal>;
+ clock-mult = <34>;
+ clock-div = <8>;
+ };
+
+ usbpll_480M: usbpll_480M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <480000000>;
+ };
+
+ usbpll_160M: usbpll_160M {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&usbpll_480M>;
+ clock-mult = <1>;
+ clock-div = <3>;
+ };
+
+ uart0clk: uart0clk {
+ #clock-cells = <0>;
+ compatible = "mstar,cedric-uartclk";
+ clocks = <&mpll_176M>, <&usbpll_160M>, <&mpll_147M>, <&mpll_126M>, <&mpll_110M>;
+ reg = <0x1F20164C 0x4>;
+ mux-shift = <10>;
+ mux-width = <3>;
+ gate-shift = <8>;
+ };
+
+ mfe: mfe {
+ compatible = "mstar,mfe";
+ reg = <0x1F206600 0x100>,<0x1F222000 0x200>;
+ };
+
+ isp: isp {
+ compatible = "isp";
+ banks = <0x1F2A0C00>,<0x1F2A0E00>,<0x1F2A1000>,<0x1F2A1200>,<0x1F2A1400 >,<0x1F2A1600 >,<0x1F2A1800 >,<0x1F2A1A00 >;
+ interrupts=;
+ };
+ ir:ir0{
+ compatible = "mstar,ir";
+ reg = <0x1F007A00 0x100>;
+ interrupts=,;
+ };
+
+ clks: clocks{
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ i2c0: i2c@0{
+ compatible = "mstar,i2c";
+ reg = <0x1F223000 0x200>,<0x1F203400 0x200>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-group = <0>;
+ i2c-speed = <2>;//0~6
+
+ 24c02@54 {
+ compatible = "mstar,24c02";
+ reg = <0x54>;
+ };
+ };
+
+ i2c1: i2c@1{
+ compatible = "mstar,i2c";
+ reg = <0x1F223200 0x200>,<0x1F203c00 0x200>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-group = <1>;
+ i2c-speed = <2>;//0~6
+ status = "disable";
+ };
+
+
+ gpio:gpio{
+ compatible = "mstar,gpio";
+ reg = <0x1F207800 0x200>,<0x1F203C00 0x200>;
+ gpio-num = <183>;
+ };
+
+ };
+};
+
+
+/include/ "cedric-clks.dtsi"
diff --git a/arch/arm/boot/dts/chicago.dts b/arch/arm/boot/dts/chicago.dts
new file mode 100644
index 00000000..d3ca9ad2
--- /dev/null
+++ b/arch/arm/boot/dts/chicago.dts
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "chicago.dtsi"
+
+/ {
+ model = "CHICAGO XXXXX Board";
+ compatible = "mstar,chicago";
+
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/ram rootwait";
+ linux,initrd-start = <0x25000000>;
+ linux,initrd-end = <0x25040000>;
+ };
+
+ memory {
+ reg = <0x20000000 0x07000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/chicago.dtsi b/arch/arm/boot/dts/chicago.dtsi
new file mode 100644
index 00000000..db25e6c9
--- /dev/null
+++ b/arch/arm/boot/dts/chicago.dtsi
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <../../../drivers/mstar/include/chicago/irqs.h>
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "mstar,chicago";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ clock-frequency = <800000000>;
+ };
+
+ };
+
+ xtal: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ aliases {
+ console = &uart0;
+ serial0 = &uart0;
+ //sdmmc0 = &sd0;
+ };
+
+
+
+ soc {
+
+ compatible = "simple-bus";
+ interrupt-parent = <&intrctl>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xFFFFFFFF>;
+
+ intrctl: interrupt-controller@0 {
+ compatible = "mstar,intrctl-chicago";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ /*
+ cpuclk: clk@1F221800 {
+ compatible = "mstar,chicago-cpuclk";
+ #clock-cells = <1>;
+ reg = <0x1F221800 0x100>;
+ clocks = <&xtal>;
+ };*/
+
+
+ arch_timer {
+ compatible = "arm,cortex-a7-timer", "arm,armv7-timer";
+ /*interrupts = ,
+ ,
+ ,
+ ;*/
+ clock-frequency = <400000000>; /* arch_timer must use clock-frequency*/
+ };
+
+ timer_clocksource: timer@1F007780 {
+ compatible = "mstar,piu-clocksource";
+ reg = <0x1F007780 0x40>;
+ clocks = <&xtal>;
+ };
+
+
+ timer_clockevent: timer@1F0069C0 {
+ compatible = "mstar,piu-clockevent";
+ reg = <0x1F0069C0 0x40>;
+ interrupts=;
+ clocks = <&xtal>;
+ };
+
+ uart0: uart@1F007600 {
+ compatible = "mstar,uart";
+ reg = <0x1F007600 0x100>;
+ interrupts= ;
+ clocks = <&xtal>;
+ tolerance = <2>;
+ status = "ok";
+ };
+
+ };
+};
diff --git a/arch/arm/boot/dts/infinity-MSC315.dts b/arch/arm/boot/dts/infinity-MSC315.dts
new file mode 100644
index 00000000..0505cf53
--- /dev/null
+++ b/arch/arm/boot/dts/infinity-MSC315.dts
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "infinity.dtsi"
+
+/ {
+ model = "INFINITY MSC315";
+ compatible = "mstar,infinity";
+
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/ram rootwait";
+ linux,initrd-start = <0x20FE0000>;
+ linux,initrd-end = <0x21000000>;
+ };
+/*
+ sysp:rammtd@0 {
+ compatible = "mtd-ram";
+ reg= <0x14380000 0x00400000>;
+ bank-width = <1>;
+ };
+*/
+ memory {
+ reg = <0x20000000 0x04000000>;
+ };
+
+
+/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ miu_bist_mem: miu_bist_mem@27F80000 {
+ reg = <0x23F00000 0x00100000>;
+ no-map ;
+ status = "okay";
+ };
+ cma0 {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x02800000>;
+ linux,cma-default;
+ };
+
+ };
+};
diff --git a/arch/arm/boot/dts/infinity-MSC316.dts b/arch/arm/boot/dts/infinity-MSC316.dts
new file mode 100644
index 00000000..bb16c8d6
--- /dev/null
+++ b/arch/arm/boot/dts/infinity-MSC316.dts
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "infinity.dtsi"
+
+/ {
+ model = "INFINITY MSC316";
+ compatible = "mstar,infinity";
+
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/ram rootwait";
+ linux,initrd-start = <0x20FE0000>;
+ linux,initrd-end = <0x21000000>;
+ };
+/*
+ sysp:rammtd@0 {
+ compatible = "mtd-ram";
+ reg= <0x14380000 0x00400000>;
+ bank-width = <1>;
+ };
+*/
+ memory {
+ reg = <0x20000000 0x08000000>;
+ };
+
+
+/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ miu_bist_mem: miu_bist_mem@27F80000 {
+ reg = <0x27F00000 0x00100000>;
+ no-map ;
+ status = "okay";
+ };
+ cma0 {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x06000000>;
+ linux,cma-default;
+ };
+
+ };
+};
diff --git a/arch/arm/boot/dts/infinity-MST240A-256M.dts b/arch/arm/boot/dts/infinity-MST240A-256M.dts
new file mode 100644
index 00000000..e156626e
--- /dev/null
+++ b/arch/arm/boot/dts/infinity-MST240A-256M.dts
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "infinity.dtsi"
+
+/ {
+ model = "MST240A MSC316Q";
+ compatible = "mstar,infinity";
+
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8r root=/dev/ram rootwait";
+ linux,initrd-start = <0x20FE0000>;
+ linux,initrd-end = <0x21000000>;
+ };
+
+ memory {
+ reg = <0x20000000 0x10000000>;
+ };
+
+/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ miu_bist_mem: miu_bist_mem@2FF00000 {
+ reg = <0x2FF00000 0x00100000>;
+ no-map ;
+ status = "okay";
+ };
+
+ cma0 {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x05000000>;
+ linux,cma-default;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/infinity-MST240A.dts b/arch/arm/boot/dts/infinity-MST240A.dts
new file mode 100644
index 00000000..edd7cf3c
--- /dev/null
+++ b/arch/arm/boot/dts/infinity-MST240A.dts
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "infinity.dtsi"
+
+/ {
+ model = "MST240A MSC316D";
+ compatible = "mstar,infinity";
+
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8r root=/dev/ram rootwait";
+ linux,initrd-start = <0x20FE0000>;
+ linux,initrd-end = <0x21000000>;
+ };
+
+ memory {
+ reg = <0x20000000 0x08000000>;
+ };
+
+/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ miu_bist_mem: miu_bist_mem@27F00000 {
+ reg = <0x27F00000 0x00100000>;
+ no-map ;
+ status = "okay";
+ };
+
+ cma0 {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x05000000>;
+ alignment = <0x1000>;
+ linux,cma-default;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/infinity-MST240B.dts b/arch/arm/boot/dts/infinity-MST240B.dts
new file mode 100644
index 00000000..31ccf43b
--- /dev/null
+++ b/arch/arm/boot/dts/infinity-MST240B.dts
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "infinity.dtsi"
+
+/ {
+ model = "MST240B MSC315";
+ compatible = "mstar,infinity";
+
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8r root=/dev/ram rootwait";
+ linux,initrd-start = <0x20FE0000>;
+ linux,initrd-end = <0x21000000>;
+ };
+
+ memory {
+ reg = <0x20000000 0x04000000>;
+ };
+
+/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ cma0 {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x02000000>;
+ linux,cma-default;
+ };
+
+ };
+};
diff --git a/arch/arm/boot/dts/infinity-MST240C.dts b/arch/arm/boot/dts/infinity-MST240C.dts
new file mode 100644
index 00000000..e8b4d205
--- /dev/null
+++ b/arch/arm/boot/dts/infinity-MST240C.dts
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "infinity.dtsi"
+
+/ {
+ model = "MST240C MSC313";
+ compatible = "mstar,infinity";
+
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8r root=/dev/ram rootwait isp_flag=0x0";
+ linux,initrd-start = <0x20FE0000>;
+ linux,initrd-end = <0x21000000>;
+ };
+
+ memory {
+ reg = <0x20000000 0x04000000>;
+ };
+
+/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ cma0 {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x02000000>;
+ linux,cma-default;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/infinity-clks.dtsi b/arch/arm/boot/dts/infinity-clks.dtsi
new file mode 100644
index 00000000..0374f3cb
--- /dev/null
+++ b/arch/arm/boot/dts/infinity-clks.dtsi
@@ -0,0 +1,1473 @@
+/* generated by CLK_DT_GEN_4 */
+/* CLK FILENAME: I1\20151127\iNfinity_Clock_Table_20151127.xls */
+/* REG FILENAME: I1\20151127\iNfinity_reg_CLKGEN_20151127.xls */
+
+CLK_VOID: CLK_VOID {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <1>;
+};
+
+CLK_utmi: CLK_utmi {
+ #clock-cells = <0>;
+ compatible = "mstar,complex-clock";
+ clocks = <&CLK_xtali_12m>;
+};
+
+CLK_usb: CLK_usb {
+ #clock-cells = <0>;
+ compatible = "mstar,complex-clock";
+ clocks = <&CLK_utmi>;
+};
+
+CLK_mpll_432m: CLK_mpll_432m {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <432000000>;
+};
+
+CLK_mpll_288m: CLK_mpll_288m {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <288000000>;
+};
+
+CLK_utmi_240m: CLK_utmi_240m {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_utmi>;
+ clock-div = <2>;
+ clock-mult = <1>;
+};
+
+CLK_mpll_216m: CLK_mpll_216m {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <216000000>;
+};
+
+CLK_utmi_192m: CLK_utmi_192m {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_utmi>;
+ clock-div = <5>;
+ clock-mult = <2>;
+};
+
+CLK_mpll_172m: CLK_mpll_172m {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <172000000>;
+};
+
+CLK_utmi_160m: CLK_utmi_160m {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_utmi>;
+ clock-div = <3>;
+ clock-mult = <1>;
+};
+
+CLK_mpll_144m: CLK_mpll_144m {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <144000000>;
+};
+
+CLK_mpll_123m: CLK_mpll_123m {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <123000000>;
+};
+
+CLK_mpll_86m: CLK_mpll_86m {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <86000000>;
+};
+
+CLK_mpll_288m_div2: CLK_mpll_288m_div2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mpll_288m>;
+ clock-div = <2>;
+ clock-mult = <1>;
+};
+
+CLK_mpll_288m_div4: CLK_mpll_288m_div4 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mpll_288m>;
+ clock-div = <4>;
+ clock-mult = <1>;
+};
+
+CLK_mpll_288m_div8: CLK_mpll_288m_div8 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mpll_288m>;
+ clock-div = <8>;
+ clock-mult = <1>;
+};
+
+CLK_mpll_216m_div2: CLK_mpll_216m_div2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mpll_216m>;
+ clock-div = <2>;
+ clock-mult = <1>;
+};
+
+CLK_mpll_216m_div4: CLK_mpll_216m_div4 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mpll_216m>;
+ clock-div = <4>;
+ clock-mult = <1>;
+};
+
+CLK_mpll_216m_div8: CLK_mpll_216m_div8 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mpll_216m>;
+ clock-div = <8>;
+ clock-mult = <1>;
+};
+
+CLK_mpll_144m_div2: CLK_mpll_144m_div2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mpll_144m>;
+ clock-div = <2>;
+ clock-mult = <1>;
+};
+
+CLK_mpll_144m_div4: CLK_mpll_144m_div4 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mpll_144m>;
+ clock-div = <4>;
+ clock-mult = <1>;
+};
+
+CLK_mpll_123m_div2: CLK_mpll_123m_div2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mpll_123m>;
+ clock-div = <2>;
+ clock-mult = <1>;
+};
+
+CLK_mpll_86m_div2: CLK_mpll_86m_div2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mpll_86m>;
+ clock-div = <2>;
+ clock-mult = <1>;
+};
+
+CLK_mpll_86m_div4: CLK_mpll_86m_div4 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mpll_86m>;
+ clock-div = <4>;
+ clock-mult = <1>;
+};
+
+CLK_mpll_86m_div16: CLK_mpll_86m_div16 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mpll_86m>;
+ clock-div = <16>;
+ clock-mult = <1>;
+};
+
+CLK_utmi_192m_div4: CLK_utmi_192m_div4 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_utmi_192m>;
+ clock-div = <4>;
+ clock-mult = <1>;
+};
+
+CLK_utmi_160m_div4: CLK_utmi_160m_div4 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_utmi_160m>;
+ clock-div = <4>;
+ clock-mult = <1>;
+};
+
+CLK_utmi_160m_div5: CLK_utmi_160m_div5 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_utmi_160m>;
+ clock-div = <5>;
+ clock-mult = <1>;
+};
+
+CLK_utmi_160m_div8: CLK_utmi_160m_div8 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_utmi_160m>;
+ clock-div = <8>;
+ clock-mult = <1>;
+};
+
+CLK_xtali_24m: CLK_xtali_24m {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+};
+
+CLK_xtali_12m: CLK_xtali_12m {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+CLK_xtali_12m_div2: CLK_xtali_12m_div2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_xtali_12m>;
+ clock-div = <2>;
+ clock-mult = <1>;
+};
+
+CLK_xtali_12m_div4: CLK_xtali_12m_div4 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_xtali_12m>;
+ clock-div = <4>;
+ clock-mult = <1>;
+};
+
+CLK_xtali_12m_div8: CLK_xtali_12m_div8 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_xtali_12m>;
+ clock-div = <8>;
+ clock-mult = <1>;
+};
+
+CLK_xtali_12m_div12: CLK_xtali_12m_div12 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_xtali_12m>;
+ clock-div = <12>;
+ clock-mult = <1>;
+};
+
+CLK_xtali_12m_div16: CLK_xtali_12m_div16 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_xtali_12m>;
+ clock-div = <16>;
+ clock-mult = <1>;
+};
+
+CLK_xtali_12m_div40: CLK_xtali_12m_div40 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_xtali_12m>;
+ clock-div = <40>;
+ clock-mult = <1>;
+};
+
+CLK_xtali_12m_div64: CLK_xtali_12m_div64 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_xtali_12m>;
+ clock-div = <64>;
+ clock-mult = <1>;
+};
+
+CLK_xtali_12m_div128: CLK_xtali_12m_div128 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_xtali_12m>;
+ clock-div = <128>;
+ clock-mult = <1>;
+};
+
+CLK_rtc_32k: CLK_rtc_32k {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+};
+
+CLK_rtc_32k_div4: CLK_rtc_32k_div4 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_rtc_32k>;
+ clock-div = <4>;
+ clock-mult = <1>;
+};
+
+CLK_pm_riu_w_clk_in: CLK_pm_riu_w_clk_in {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mcu>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu_w_clk_in: CLK_riu_w_clk_in {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mcu>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu_w_clk_top: CLK_riu_w_clk_top {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mcu>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu_w_clk_sc_gp: CLK_riu_w_clk_sc_gp {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mcu>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu_w_clk_vhe_gp: CLK_riu_w_clk_vhe_gp {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mcu>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu_w_clk_hemcu_gp: CLK_riu_w_clk_hemcu_gp {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mcu>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu_w_clk_mipi_if_gp: CLK_riu_w_clk_mipi_if_gp {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mcu>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu_w_clk_mcu_if_gp: CLK_riu_w_clk_mcu_if_gp {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mcu>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_p: CLK_miu_p {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_vhe_gp_p: CLK_miu_vhe_gp_p {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_vhe_gp>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_sc_gp_p: CLK_miu_sc_gp_p {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu2x_p: CLK_miu2x_p {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu2x>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_mcu_p: CLK_mcu_p {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mcu>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_mcu_pm_p: CLK_mcu_pm_p {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mcu_pm>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_isp_p: CLK_isp_p {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_isp>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_fclk1_p: CLK_fclk1_p {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_fclk1>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_sdio_p: CLK_sdio_p {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_sdio>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_fcie_p: CLK_fcie_p {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_fcie>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_tck_buf: CLK_tck_buf {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <1>;
+};
+
+CLK_pad2isp_sr_pclk: CLK_pad2isp_sr_pclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <1>;
+};
+
+CLK_ccir_in_clk: CLK_ccir_in_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <1>;
+};
+
+CLK_emac_tx_in_lan: CLK_emac_tx_in_lan {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <1>;
+};
+
+CLK_emac_rx_in_lan: CLK_emac_rx_in_lan {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <1>;
+};
+
+CLK_mii_tx: CLK_mii_tx {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <1>;
+};
+
+CLK_mii_rx: CLK_mii_rx {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <1>;
+};
+
+CLK_emac_tx_reg_pad: CLK_emac_tx_reg_pad {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <1>;
+};
+
+CLK_miu_ff: CLK_miu_ff {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_sc_gp: CLK_miu_sc_gp {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_vhe_gp: CLK_miu_vhe_gp {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_dig: CLK_miu_dig {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_xd2miu: CLK_miu_xd2miu {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_urdma: CLK_miu_urdma {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_bdma: CLK_miu_bdma {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_vhe: CLK_miu_vhe {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_vhe_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_mfeh: CLK_miu_mfeh {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_mfe: CLK_miu_mfe {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_jpe1: CLK_miu_jpe1 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_jpe0: CLK_miu_jpe0 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_bach: CLK_miu_bach {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_file: CLK_miu_file {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_uhc0: CLK_miu_uhc0 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_emac: CLK_miu_emac {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_cmdq: CLK_miu_cmdq {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_isp_dnr: CLK_miu_isp_dnr {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_isp_rot: CLK_miu_isp_rot {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_isp_dma: CLK_miu_isp_dma {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_isp_sta: CLK_miu_isp_sta {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_gop: CLK_miu_gop {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_sc_dnr: CLK_miu_sc_dnr {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_sc_dnr_sad: CLK_miu_sc_dnr_sad {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_sc_crop: CLK_miu_sc_crop {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_sc1_frm: CLK_miu_sc1_frm {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_sc1_snp: CLK_miu_sc1_snp {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_sc1_snpi: CLK_miu_sc1_snpi {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_sc1_dbg: CLK_miu_sc1_dbg {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_sc2_frm: CLK_miu_sc2_frm {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_sc2_snpi: CLK_miu_sc2_snpi {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_sc3_frm: CLK_miu_sc3_frm {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_fcie: CLK_miu_fcie {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_sdio: CLK_miu_sdio {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu: CLK_riu {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_riu_w_clk_in>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu_top: CLK_riu_top {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_riu_w_clk_top>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu_sc_gp: CLK_riu_sc_gp {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_riu_w_clk_sc_gp>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu_vhe_gp: CLK_riu_vhe_gp {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_riu_w_clk_vhe_gp>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu_hemcu_gp: CLK_riu_hemcu_gp {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_riu_w_clk_hemcu_gp>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu_mipi_gp: CLK_riu_mipi_gp {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_riu_w_clk_mipi_if_gp>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu_mcu_if: CLK_riu_mcu_if {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_riu_w_clk_mcu_if_gp>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu2x: CLK_miu2x {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_ddrpll_clk>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_axi2x: CLK_axi2x {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu2x_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_tck: CLK_tck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_tck_buf>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_gop: CLK_gop {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_fclk1_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_live_pm: CLK_live_pm {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_xtali_24m>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu_pm: CLK_riu_pm {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_pm_riu_w_clk_in>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miupll_clk: CLK_miupll_clk {
+ #clock-cells = <0>;
+ compatible = "mstar,complex-clock";
+ clocks = <&CLK_xtali_24m>;
+};
+
+CLK_ddrpll_clk: CLK_ddrpll_clk {
+ #clock-cells = <0>;
+ compatible = "mstar,complex-clock";
+ clocks = <&CLK_ddr_syn>;
+};
+
+CLK_lpll_clk: CLK_lpll_clk {
+ #clock-cells = <0>;
+ compatible = "mstar,complex-clock";
+ clocks = <&CLK_mpll_432m>;
+};
+
+CLK_cpupll_clk: CLK_cpupll_clk {
+ #clock-cells = <0>;
+ compatible = "mstar,complex-clock";
+ clocks = <&CLK_mpll_432m>;
+};
+
+CLK_fuart0_synth_out: CLK_fuart0_synth_out {
+ #clock-cells = <0>;
+ compatible = "mstar,complex-clock";
+ clocks = <&CLK_fuart0_synth_in>;
+};
+
+CLK_csi2_mac_p: CLK_csi2_mac_p {
+ #clock-cells = <0>;
+ compatible = "mstar,complex-clock";
+ clocks = <&CLK_csi_mac>;
+};
+
+CLK_miu: CLK_miu {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_ddrpll_clk>,<&CLK_VOID>,<&CLK_miupll_clk>,<&CLK_mpll_216m>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_MIU_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_MIU_OFFSET
+ glitch-shift = <4>; //4+REG_CKG_MIU_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_ddr_syn: CLK_ddr_syn {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_432m>,<&CLK_mpll_216m>,<&CLK_xtali_12m>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_DDR_SYN_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_DDR_SYN_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_miu_rec: CLK_miu_rec {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div64>,<&CLK_xtali_12m_div128>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_MIU_REC_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_MIU_REC_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_mcu: CLK_mcu {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_216m>,<&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_216m_div2>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_MCU_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_MCU_OFFSET
+ glitch-shift = <4>; //4+REG_CKG_MCU_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_riubrdg: CLK_riubrdg {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mcu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_RIUBRDG_OFFSET
+ mux-width = <2>;
+ gate-shift = <8>; //0+REG_CKG_RIUBRDG_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_bdma: CLK_bdma {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_miu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_BDMA_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_BDMA_OFFSET
+};
+
+CLK_spi: CLK_spi {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_216m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_86m>,<&CLK_mpll_288m_div4>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_SPI_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_SPI_OFFSET
+ glitch-shift = <4>; //4+REG_CKG_SPI_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_uart0: CLK_uart0 {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_UART0_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_UART0_OFFSET
+};
+
+CLK_uart1: CLK_uart1 {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_UART1_OFFSET
+ mux-width = <2>;
+ gate-shift = <8>; //0+REG_CKG_UART1_OFFSET
+};
+
+CLK_fuart0_synth_in: CLK_fuart0_synth_in {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_432m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <6>; //2+REG_CKG_FUART0_SYNTH_IN_OFFSET
+ mux-width = <2>;
+ gate-shift = <4>; //0+REG_CKG_FUART0_SYNTH_IN_OFFSET
+};
+
+CLK_fuart: CLK_fuart {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_fuart0_synth_out>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_FUART_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_FUART_OFFSET
+};
+
+CLK_mspi0: CLK_mspi0 {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_MSPI0_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_MSPI0_OFFSET
+};
+
+CLK_mspi1: CLK_mspi1 {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_MSPI1_OFFSET
+ mux-width = <2>;
+ gate-shift = <8>; //0+REG_CKG_MSPI1_OFFSET
+};
+
+CLK_miic0: CLK_miic0 {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_MIIC0_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_MIIC0_OFFSET
+};
+
+CLK_miic1: CLK_miic1 {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_MIIC1_OFFSET
+ mux-width = <2>;
+ gate-shift = <8>; //0+REG_CKG_MIIC1_OFFSET
+};
+
+CLK_bist: CLK_bist {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_BIST_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_BIST_OFFSET
+};
+
+CLK_xtali: CLK_xtali {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_XTALI_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_XTALI_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_live: CLK_live {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_LIVE_OFFSET
+ mux-width = <2>;
+ gate-shift = <8>; //0+REG_CKG_LIVE_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_sr_mclk: CLK_sr_mclk {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_216m_div8>,<&CLK_mpll_86m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_86m_div16>,<&CLK_mpll_288m_div8>,<&CLK_mpll_216m_div4>,<&CLK_mpll_86m_div2>,<&CLK_mpll_123m_div2>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_SR_MCLK_OFFSET
+ mux-width = <3>;
+ gate-shift = <8>; //0+REG_CKG_SR_MCLK_OFFSET
+};
+
+CLK_bist_pm: CLK_bist_pm {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_BIST_PM_OFFSET
+ mux-width = <2>;
+ gate-shift = <8>; //0+REG_CKG_BIST_PM_OFFSET
+};
+
+CLK_bist_vhe_gp: CLK_bist_vhe_gp {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_86m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_BIST_VHE_GP_OFFSET
+ mux-width = <2>;
+ gate-shift = <8>; //0+REG_CKG_BIST_VHE_GP_OFFSET
+};
+
+CLK_vhe: CLK_vhe {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_VOID>,<&CLK_mpll_216m>,<&CLK_utmi_192m>,<&CLK_utmi_160m>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_VHE_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_VHE_OFFSET
+};
+
+CLK_xtali_sc_gp: CLK_xtali_sc_gp {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <6>; //2+REG_CKG_XTALI_SC_GP_OFFSET
+ mux-width = <2>;
+ gate-shift = <4>; //0+REG_CKG_XTALI_SC_GP_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_bist_sc_gp: CLK_bist_sc_gp {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_BIST_SC_GP_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_BIST_SC_GP_OFFSET
+};
+
+CLK_imi: CLK_imi {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_miu_p>;
+ reg = ;
+ gate-shift = <0>; //0+REG_CKG_IMI_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_emac_ahb: CLK_emac_ahb {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_288m_div2>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_EMAC_AHB_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_EMAC_AHB_OFFSET
+};
+
+CLK_mfe: CLK_mfe {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_288m>,<&CLK_utmi_240m>,<&CLK_utmi_192m>,<&CLK_mpll_123m>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_MFE_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_MFE_OFFSET
+};
+
+CLK_jpe: CLK_jpe {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_288m>,<&CLK_mpll_216m>,<&CLK_mpll_216m_div4>,<&CLK_mpll_216m_div8>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_JPE_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_JPE_OFFSET
+};
+
+CLK_aesdma: CLK_aesdma {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_86m>,<&CLK_mpll_172m>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_AESDMA_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_AESDMA_OFFSET
+ glitch-shift = <4>; //4+REG_CKG_AESDMA_OFFSET
+};
+
+CLK_sdio: CLK_sdio {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_utmi_160m_div4>,<&CLK_mpll_288m_div8>,<&CLK_utmi_160m_div5>,<&CLK_utmi_160m_div8>,<&CLK_xtali_12m>,<&CLK_xtali_12m_div40>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_SDIO_OFFSET
+ mux-width = <3>;
+ gate-shift = <0>; //0+REG_CKG_SDIO_OFFSET
+};
+
+CLK_fcie: CLK_fcie {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_123m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_86m>,<&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_utmi_160m_div4>,<&CLK_mpll_288m_div8>,<&CLK_utmi_160m_div5>,<&CLK_utmi_160m_div8>,<&CLK_mpll_86m_div16>,<&CLK_xtali_12m_div40>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_FCIE_OFFSET
+ mux-width = <4>;
+ gate-shift = <0>; //0+REG_CKG_FCIE_OFFSET
+};
+
+CLK_ecc: CLK_ecc {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_utmi_160m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_ECC_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_ECC_OFFSET
+};
+
+CLK_sr: CLK_sr {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_pad2isp_sr_pclk>,<&CLK_csi2_mac_p>,<&CLK_utmi_160m_div4>,<&CLK_mpll_86m>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_SR_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_SR_OFFSET
+};
+
+CLK_isp: CLK_isp {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_ISP_OFFSET
+ mux-width = <2>;
+ gate-shift = <8>; //0+REG_CKG_ISP_OFFSET
+};
+
+CLK_idclk: CLK_idclk {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_isp_p>,<&CLK_ccir_in_clk>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_IDCLK_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_IDCLK_OFFSET
+};
+
+CLK_fclk1: CLK_fclk1 {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_172m>,<&CLK_mpll_86m>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_FCLK1_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_FCLK1_OFFSET
+};
+
+CLK_fclk2: CLK_fclk2 {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_172m>,<&CLK_mpll_86m>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_FCLK2_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_FCLK2_OFFSET
+};
+
+CLK_odclk: CLK_odclk {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_86m>,<&CLK_mpll_86m_div2>,<&CLK_mpll_86m_div4>,<&CLK_lpll_clk>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_ODCLK_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_ODCLK_OFFSET
+};
+
+CLK_gop_psram: CLK_gop_psram {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_miu_p>,<&CLK_fclk1_p>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_GOP_PSRAM_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_GOP_PSRAM_OFFSET
+};
+
+CLK_nlm: CLK_nlm {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_miu_p>,<&CLK_fclk1_p>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_NLM_OFFSET
+ mux-width = <1>;
+ gate-shift = <8>; //0+REG_CKG_NLM_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_emac_tx: CLK_emac_tx {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_emac_tx_in_lan>,<&CLK_mii_tx>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_EMAC_TX_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_EMAC_TX_OFFSET
+};
+
+CLK_emac_rx: CLK_emac_rx {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_emac_rx_in_lan>,<&CLK_mii_rx>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_EMAC_RX_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_EMAC_RX_OFFSET
+};
+
+CLK_emac_tx_ref: CLK_emac_tx_ref {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_emac_tx_reg_pad>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_EMAC_TX_REF_OFFSET
+ mux-width = <2>;
+ gate-shift = <8>; //0+REG_CKG_EMAC_TX_REF_OFFSET
+};
+
+CLK_emac_rx_ref: CLK_emac_rx_ref {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_emac_tx_reg_pad>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_EMAC_RX_REF_OFFSET
+ mux-width = <2>;
+ gate-shift = <8>; //0+REG_CKG_EMAC_RX_REF_OFFSET
+};
+
+CLK_hemcu_216m: CLK_hemcu_216m {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_216m>;
+ reg = ;
+ gate-shift = <0>; //0+REG_CKG_HEMCU_216M_OFFSET
+};
+
+CLK_csi_mac: CLK_csi_mac {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_xtali_12m>,<&CLK_mpll_216m>,<&CLK_mpll_288m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_CSI_MAC_OFFSET
+ mux-width = <3>;
+ gate-shift = <0>; //0+REG_CKG_CSI_MAC_OFFSET
+};
+
+CLK_mac_lptx: CLK_mac_lptx {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_xtali_12m>,<&CLK_mpll_216m>,<&CLK_mpll_288m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_MAC_LPTX_OFFSET
+ mux-width = <3>;
+ gate-shift = <8>; //0+REG_CKG_MAC_LPTX_OFFSET
+};
+
+CLK_ns: CLK_ns {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_xtali_12m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_NS_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_NS_OFFSET
+};
+
+CLK_mcu_pm: CLK_mcu_pm {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_216m>,<&CLK_utmi_192m>,<&CLK_mpll_172m>,<&CLK_utmi_160m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_123m>,<&CLK_mpll_216m_div2>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_24m>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_MCU_PM_OFFSET
+ mux-width = <4>;
+ gate-shift = <0>; //0+REG_CKG_MCU_PM_OFFSET
+ glitch-shift = <7>; //7+REG_CKG_MCU_PM_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_spi_pm: CLK_spi_pm {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_rtc_32k>,<&CLK_mpll_216m_div8>,<&CLK_mpll_144m_div4>,<&CLK_mpll_86m_div2>,<&CLK_mpll_216m_div4>,<&CLK_mpll_144m_div2>,<&CLK_mpll_86m>,<&CLK_mpll_216m_div2>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>,<&CLK_xtali_12m>,<&CLK_xtali_24m>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_SPI_PM_OFFSET
+ mux-width = <4>;
+ gate-shift = <8>; //0+REG_CKG_SPI_PM_OFFSET
+ glitch-shift = <14>; //6+REG_CKG_SPI_PM_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_pm_sleep: CLK_pm_sleep {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>;
+ reg = ;
+ mux-shift = <12>; //2+REG_CKG_PM_SLEEP_OFFSET
+ mux-width = <3>;
+};
+
+CLK_sar: CLK_sar {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>;
+ reg = ;
+ mux-shift = <7>; //2+REG_CKG_SAR_OFFSET
+ mux-width = <3>;
+ gate-shift = <5>; //0+REG_CKG_SAR_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_rtc: CLK_rtc {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_RTC_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_RTC_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_ir: CLK_ir {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>;
+ reg = ;
+ mux-shift = <7>; //2+REG_CKG_IR_OFFSET
+ mux-width = <3>;
+ gate-shift = <5>; //0+REG_CKG_IR_OFFSET
+ auto-enable = <1>;
+};
+
+usclk: usclk {
+ compatible = "usclk";
+ clocks = <&CLK_VOID>, <&CLK_aesdma>, <&CLK_axi2x>, <&CLK_bdma>, <&CLK_bist>, <&CLK_bist_pm>, <&CLK_bist_sc_gp>, <&CLK_bist_vhe_gp>, <&CLK_ccir_in_clk>, <&CLK_cpupll_clk>, <&CLK_csi2_mac_p>, <&CLK_csi_mac>, <&CLK_ddr_syn>, <&CLK_ddrpll_clk>, <&CLK_ecc>, <&CLK_emac_ahb>, <&CLK_emac_rx>, <&CLK_emac_rx_in_lan>, <&CLK_emac_rx_ref>, <&CLK_emac_tx>, <&CLK_emac_tx_in_lan>, <&CLK_emac_tx_ref>, <&CLK_emac_tx_reg_pad>, <&CLK_fcie>, <&CLK_fcie_p>, <&CLK_fclk1>, <&CLK_fclk1_p>, <&CLK_fclk2>, <&CLK_fuart>, <&CLK_fuart0_synth_in>, <&CLK_fuart0_synth_out>, <&CLK_gop>, <&CLK_gop_psram>, <&CLK_hemcu_216m>, <&CLK_idclk>, <&CLK_imi>, <&CLK_ir>, <&CLK_isp>, <&CLK_isp_p>, <&CLK_jpe>, <&CLK_live>, <&CLK_live_pm>, <&CLK_lpll_clk>, <&CLK_mac_lptx>, <&CLK_mcu>, <&CLK_mcu_p>, <&CLK_mcu_pm>, <&CLK_mcu_pm_p>, <&CLK_mfe>, <&CLK_mii_rx>, <&CLK_mii_tx>, <&CLK_miic0>, <&CLK_miic1>, <&CLK_miu>, <&CLK_miu2x>, <&CLK_miu2x_p>, <&CLK_miu_bach>, <&CLK_miu_bdma>, <&CLK_miu_cmdq>, <&CLK_miu_dig>, <&CLK_miu_emac>, <&CLK_miu_fcie>, <&CLK_miu_ff>, <&CLK_miu_file>, <&CLK_miu_gop>, <&CLK_miu_isp_dma>, <&CLK_miu_isp_dnr>, <&CLK_miu_isp_rot>, <&CLK_miu_isp_sta>, <&CLK_miu_jpe0>, <&CLK_miu_jpe1>, <&CLK_miu_mfe>, <&CLK_miu_mfeh>, <&CLK_miu_p>, <&CLK_miu_rec>, <&CLK_miu_sc1_dbg>, <&CLK_miu_sc1_frm>, <&CLK_miu_sc1_snp>, <&CLK_miu_sc1_snpi>, <&CLK_miu_sc2_frm>, <&CLK_miu_sc2_snpi>, <&CLK_miu_sc3_frm>, <&CLK_miu_sc_crop>, <&CLK_miu_sc_dnr>, <&CLK_miu_sc_dnr_sad>, <&CLK_miu_sc_gp>, <&CLK_miu_sc_gp_p>, <&CLK_miu_sdio>, <&CLK_miu_uhc0>, <&CLK_miu_urdma>, <&CLK_miu_vhe>, <&CLK_miu_vhe_gp>, <&CLK_miu_vhe_gp_p>, <&CLK_miu_xd2miu>, <&CLK_miupll_clk>, <&CLK_mpll_123m>, <&CLK_mpll_123m_div2>, <&CLK_mpll_144m>, <&CLK_mpll_144m_div2>, <&CLK_mpll_144m_div4>, <&CLK_mpll_172m>, <&CLK_mpll_216m>, <&CLK_mpll_216m_div2>, <&CLK_mpll_216m_div4>, <&CLK_mpll_216m_div8>, <&CLK_mpll_288m>, <&CLK_mpll_288m_div2>, <&CLK_mpll_288m_div4>, <&CLK_mpll_288m_div8>, <&CLK_mpll_432m>, <&CLK_mpll_86m>, <&CLK_mpll_86m_div16>, <&CLK_mpll_86m_div2>, <&CLK_mpll_86m_div4>, <&CLK_mspi0>, <&CLK_mspi1>, <&CLK_nlm>, <&CLK_ns>, <&CLK_odclk>, <&CLK_pad2isp_sr_pclk>, <&CLK_pm_riu_w_clk_in>, <&CLK_pm_sleep>, <&CLK_riu>, <&CLK_riu_hemcu_gp>, <&CLK_riu_mcu_if>, <&CLK_riu_mipi_gp>, <&CLK_riu_pm>, <&CLK_riu_sc_gp>, <&CLK_riu_top>, <&CLK_riu_vhe_gp>, <&CLK_riu_w_clk_hemcu_gp>, <&CLK_riu_w_clk_in>, <&CLK_riu_w_clk_mcu_if_gp>, <&CLK_riu_w_clk_mipi_if_gp>, <&CLK_riu_w_clk_sc_gp>, <&CLK_riu_w_clk_top>, <&CLK_riu_w_clk_vhe_gp>, <&CLK_riubrdg>, <&CLK_rtc>, <&CLK_rtc_32k>, <&CLK_rtc_32k_div4>, <&CLK_sar>, <&CLK_sdio>, <&CLK_sdio_p>, <&CLK_spi>, <&CLK_spi_pm>, <&CLK_sr>, <&CLK_sr_mclk>, <&CLK_tck>, <&CLK_tck_buf>, <&CLK_uart0>, <&CLK_uart1>, <&CLK_utmi>, <&CLK_utmi_160m>, <&CLK_utmi_160m_div4>, <&CLK_utmi_160m_div5>, <&CLK_utmi_160m_div8>, <&CLK_utmi_192m>, <&CLK_utmi_192m_div4>, <&CLK_utmi_240m>, <&CLK_vhe>, <&CLK_xtali>, <&CLK_xtali_12m>, <&CLK_xtali_12m_div12>, <&CLK_xtali_12m_div128>, <&CLK_xtali_12m_div16>, <&CLK_xtali_12m_div2>, <&CLK_xtali_12m_div4>, <&CLK_xtali_12m_div40>, <&CLK_xtali_12m_div64>, <&CLK_xtali_12m_div8>, <&CLK_xtali_24m>, <&CLK_xtali_sc_gp>, <&CLK_usb>;
+ clock-count = <174>;
+};
+
diff --git a/arch/arm/boot/dts/infinity-fpga.dts b/arch/arm/boot/dts/infinity-fpga.dts
new file mode 100644
index 00000000..bb4ee66a
--- /dev/null
+++ b/arch/arm/boot/dts/infinity-fpga.dts
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "infinity-fpga.dtsi"
+
+/ {
+ model = "INFINITY XXXXX Board";
+ compatible = "mstar,infinity";
+
+ chosen {
+ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/ram rootwait sysp=squashfs:/dev/block/mtdblock0 datap=jffs2:/dev/block/mtdblock1";
+ linux,initrd-start = <0x25000000>;
+ linux,initrd-end = <0x25020000>;
+ };
+
+
+ sysp:rammtd@0 {
+ compatible = "mtd-ram";
+ reg= <0x26000000 0x01F00000>;
+ bank-width = <1>;
+ };
+
+ /* Size of this partition must be identical to the size of data.jffs2 due to JFFS2 limitation */
+ datap:rammtd@1 {
+ compatible = "mtd-ram";
+ reg= <0x27F00000 0x00020000>;
+ bank-width = <1>;
+ };
+
+
+ memory {
+ reg = <0x20000000 0x06000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/infinity-fpga.dtsi b/arch/arm/boot/dts/infinity-fpga.dtsi
new file mode 100644
index 00000000..3081ff91
--- /dev/null
+++ b/arch/arm/boot/dts/infinity-fpga.dtsi
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <../../../../drivers/mstar/include/infinity/irqs.h>
+#include
+#include
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "mstar,infninity";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ clocks = <&xtal>;
+ };
+ };
+
+ xtal: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12000000>;
+ };
+
+ aliases {
+ console = &uart0;
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xFFFFFFFF>;
+
+
+ gic: interrupt-controller@16000000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
+ reg = <0x16001000 0x1000>,
+ <0x16002000 0x1000>;
+ };
+
+ arch_timer {
+ compatible = "arm,cortex-a7-timer", "arm,armv7-timer";
+ interrupts = ,
+ ,
+ ,
+ ;
+ clock-frequency = <12000000>; /* arch_timer must use clock-frequency*/
+ };
+
+ mfe: mfe {
+ compatible = "mstar,mfe";
+ reg = <0x1F207000 0x100>,<0x1F264800 0x200>;
+ };
+
+ vhe: vhe {
+ compatible = "mstar,vhe";
+ reg = <0x1F207000 0x100>,<0x1F265200 0x200>,<0x1F265000 0x100>;
+ };
+
+ uart0: uart@1F221000 {
+ compatible = "mstar,uart";
+ reg = <0x1F221000 0x100>;
+ interrupts= ;
+ status = "ok";
+ clocks = <&xtal>;
+ };
+
+ emac {
+ compatible = "mstar-emac";
+ interrupts = ;
+ status = "disabled";
+ };
+
+ isp: isp {
+ compatible = "isp";
+ io_phy_addr = <0x1f000000>;
+ banks = <0x1302>,<0x1303>,<0x1304>,<0x1305>,<0x1306>,<0x1307>,<0x1308>,<0x1309>;
+ interrupts= ;
+ };
+
+ sound {
+ compatible = "mstar,infinity-audio";
+// reg = <0x1F000000 0x1000000>;
+ interrupts=;
+ playback-volume-level=<64>; //0~76
+ capture-volume-level=<64>;
+ micin-gain-level=<0>; //0~5
+ linein-gain-level=<1>;//0~6
+ lineout-gain-level=<1>;//0~2
+ };
+
+ csi: csi {
+ compatible = "csi";
+ io_phy_addr = <0x1f000000>;
+ banks = <0x1204>;
+ interrupts= ;
+ };
+
+ rtc {
+ compatible = "mstar,infinity-rtc";
+ reg = <0x1F002400 0x100>;
+ clocks = <&xtal>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/infinity-gates.dtsi b/arch/arm/boot/dts/infinity-gates.dtsi
new file mode 100644
index 00000000..fee27904
--- /dev/null
+++ b/arch/arm/boot/dts/infinity-gates.dtsi
@@ -0,0 +1,158 @@
+GATE_MCM_vhe: GATE_MCM_vhe {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ reg = <0x1F226800 0x4>;
+ gate-shift = <0>;
+};
+
+GATE_MCM_mfe: GATE_MCM_mfe {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ reg = <0x1F226400 0x4>;
+ gate-shift = <0>;
+};
+
+GATE_MCM_jpe: GATE_MCM_jpe {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ reg = <0x1F226400 0x4>;
+ gate-shift = <8>;
+};
+
+GATE_MCM_aesdma: GATE_MCM_aesdma {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ reg = <0x1F226404 0x4>;
+ gate-shift = <8>;
+};
+
+GATE_MCM_emac: GATE_MCM_emac {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ reg = <0x1F226408 0x4>;
+ gate-shift = <8>;
+};
+
+GATE_MCM_gop: GATE_MCM_gop {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ reg = <0x1F226410 0x4>;
+ gate-shift = <8>;
+};
+
+GATE_MCM_bach: GATE_MCM_bach {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ reg = <0x1F226404 0x4>;
+ gate-shift = <0>;
+};
+
+GATE_MCM_usb: GATE_MCM_usb {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ reg = <0x1F226408 0x4>;
+ gate-shift = <0>;
+};
+
+
+GATE_MCM_fcie: GATE_MCM_fcie {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ reg = <0x1F226424 0x4>;
+ gate-shift = <0>;
+};
+
+GATE_MCM_sdio: GATE_MCM_sdio {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ reg = <0x1F226424 0x4>;
+ gate-shift = <8>;
+};
+
+/*
+GATE_MCM_urdma: GATE_MCM_urdma {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ reg = <0x1F226000 0x4>;
+ gate-shift = <8>;
+};
+*/
+
+GATE_SRAM_vhe: GATE_SRAM_vhe {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ reg = <0x1F226A40 0x4>;
+ gate-shift = <0>;
+};
+
+GATE_SRAM_mfe: GATE_SRAM_mfe {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ reg = <0x1F226640 0x4>;
+ gate-shift = <9>;
+};
+
+GATE_SRAM_jpe: GATE_SRAM_jpe {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ reg = <0x1F226640 0x4>;
+ gate-shift = <8>;
+};
+
+GATE_SRAM_aesdma: GATE_SRAM_aesdma {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ reg = <0x1F226640 0x4>;
+ gate-shift = <1>;
+};
+
+GATE_SRAM_emac: GATE_SRAM_emac {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ reg = <0x1F226640 0x4>;
+ gate-shift = <3>;
+};
+
+GATE_SRAM_gop: GATE_SRAM_gop {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ reg = <0x1F226640 0x4>;
+ gate-shift = <5>;
+};
+
+GATE_SRAM_bach: GATE_SRAM_bach {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ reg = <0x1F226640 0x4>;
+ gate-shift = <0>;
+};
+
+GATE_SRAM_usb: GATE_SRAM_usb {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ reg = <0x1F226640 0x4>;
+ gate-shift = <11>;
+};
+
+
+GATE_SRAM_fcie: GATE_SRAM_fcie {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ reg = <0x1F226640 0x4>;
+ gate-shift = <4>;
+};
+
+GATE_SRAM_sdio: GATE_SRAM_sdio {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ reg = <0x1F226640 0x4>;
+ gate-shift = <10>;
+};
+
+
+GATE_SRAM_mailbox: GATE_SRAM_mailbox {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ reg = <0x1F226240 0x4>;
+ gate-shift = <2>;
+};
diff --git a/arch/arm/boot/dts/infinity-zebu.dts b/arch/arm/boot/dts/infinity-zebu.dts
new file mode 100644
index 00000000..86028d5d
--- /dev/null
+++ b/arch/arm/boot/dts/infinity-zebu.dts
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "infinity-zebu.dtsi"
+
+/ {
+ model = "INFINITY XXXXX Board";
+ compatible = "mstar,infinity";
+
+
+ chosen {
+ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/ram rootwait sysp=squashfs:/dev/block/mtdblock0 datap=jffs2:/dev/block/mtdblock1";
+// bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/ram rootwait";
+ linux,initrd-start = <0x25000000>;
+ linux,initrd-end = <0x25020000>;
+ };
+
+
+ sysp:rammtd@0 {
+ compatible = "mtd-ram";
+// reg= <0x26000000 0x02000000>;
+ reg= <0x28000000 0x02000000>;
+ bank-width = <1>;
+ };
+
+ /* Size of this partition must be identical to the size of data.jffs2 due to JFFS2 limitation */
+ datap:rammtd@1 {
+ compatible = "mtd-ram";
+// reg= <0x25F00000 0x00100000>;
+ reg= <0x2A000000 0x00020000>;
+ bank-width = <1>;
+ };
+
+ memory {
+ reg = <0x20000000 0x08000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/infinity-zebu.dtsi b/arch/arm/boot/dts/infinity-zebu.dtsi
new file mode 100644
index 00000000..acc614b0
--- /dev/null
+++ b/arch/arm/boot/dts/infinity-zebu.dtsi
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <../../../../drivers/mstar/include/infinity/irqs.h>
+#include
+#include
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "mstar,infninity";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ clocks = <&xtal>;
+ };
+ };
+
+ xtal: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12000000>;
+ };
+
+ aliases {
+ console = &uart0;
+ serial0 = &uart0;
+ };
+
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xFFFFFFFF>;
+
+
+ gic: interrupt-controller@16000000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
+ reg = <0x16001000 0x1000>,
+ <0x16002000 0x1000>;
+ };
+
+ arch_timer {
+ compatible = "arm,cortex-a7-timer", "arm,armv7-timer";
+ interrupts = ,
+ ,
+ ,
+ ;
+ clock-frequency = <500000000>; /* arch_timer must use clock-frequency*/
+ };
+
+/*
+ timer_clockevent: timer@1F006040 {
+ compatible = "mstar,piu-clockevent";
+ reg = <0x1F006040 0x100>;
+ interrupts = ;
+ clocks = <&xtal>;
+ };
+*/
+ uart0: uart@1F220400 {
+ compatible = "mstar,uart";
+ reg = <0x1F220400 0x100>;
+ interrupts= ;
+ status = "ok";
+ clocks = <&xtal>;
+ };
+
+ isp: isp {
+ compatible = "isp";
+ io_phy_addr = <0x1f000000>;
+ banks = <0x1302>,<0x1303>,<0x1304>,<0x1305>,<0x1306>,<0x1307>,<0x1308>,<0x1309>;
+ interrupts= ;
+ };
+
+ csi: csi {
+ compatible = "csi";
+ io_phy_addr = <0x1f000000>;
+ banks = <0x1204>;
+ interrupts= ;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/infinity.dtsi b/arch/arm/boot/dts/infinity.dtsi
new file mode 100644
index 00000000..aa95aec7
--- /dev/null
+++ b/arch/arm/boot/dts/infinity.dtsi
@@ -0,0 +1,395 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <../../../../drivers/mstar/include/infinity/irqs.h>
+#include <../../../../drivers/mstar/include/infinity/gpio.h>
+#include
+#include
+#include "skeleton.dtsi"
+
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ clocks = <&CLK_cpupll_clk>;
+ };
+ };
+
+ aliases {
+ console = &uart0;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &fuart;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gic: interrupt-controller@16000000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
+ reg = <0x16001000 0x1000>,
+ <0x16002000 0x1000>;
+ };
+
+ ms_pmsleep_intr: interrupt-controller@0 {
+ compatible = "mstar,pmsleep-intr";
+ #interrupt-cells = <1>;
+ interrupt-parent=<&gic>;
+ interrupt-controller;
+ };
+
+
+ arch_timer {
+ compatible = "arm,cortex-a7-timer", "arm,armv7-timer";
+ interrupts = ,
+ ,
+ ,
+ ;
+ clock-frequency = <6000000>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = ,
+ ,
+ ,
+ ;
+ };
+
+ clks: clocks{
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ };
+
+/*
+ timer_clockevent: timer@1F006040 {
+ compatible = "mstar,piu-clockevent";
+ reg = <0x1F006040 0x100>;
+ interrupts=;
+ clocks = <&CLK_xtali_12m>;
+ };
+*/
+ mfe: mfe {
+ compatible = "mstar,mfe";
+ reg = <0x1F264800 0x200>;
+ interrupts=;
+ clocks = <&CLK_mfe>,<&GATE_MCM_mfe>, <&GATE_SRAM_mfe>;
+ clock-names = "CKG_mfe";
+ status = "ok";
+ };
+
+ vhe: vhe {
+ compatible = "mstar,vhe";
+ reg = <0x1F265200 0x200>,<0x1F265000 0x100>;
+ interrupts=;
+ clocks = <&CLK_vhe>,<&GATE_MCM_vhe>, <&GATE_SRAM_vhe>;
+ clock-names = "CKG_vhe";
+ status = "ok";
+ };
+
+ hvsp1: hvsp1 {
+ compatible = "mstar,hvsp1";
+ //reg = <0x1F000000 0x100>;
+ //clk,chiptop,hvsp0,sc0,dnr,ldc
+ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>;
+ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk";
+ status = "ok";
+ interrupts = , ;
+ };
+
+ hvsp2: hvsp2 {
+ compatible = "mstar,hvsp2";
+ //reg = <0x1F000000 0x100>;
+ //clk,chiptop,hvsp0,sc0,dnr,ldc
+ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>;
+ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk";
+ status = "ok";
+ interrupts = , ;
+ };
+
+ hvsp3: hvsp3 {
+ compatible = "mstar,hvsp3";
+ //reg = <0x1F000000 0x100>;
+ //clk,chiptop,hvsp0,sc0,dnr,ldc
+ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>;
+ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk";
+ status = "ok";
+ interrupts = , ;
+ };
+
+ scldma1: scldma1 {
+ compatible = "mstar,scldma1";
+ //reg = <0x1F000000 0x100>;
+ //clk,chiptop,scldma
+ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>;
+ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk";
+ status = "ok";
+ interrupts = ;
+ };
+ scldma2: scldma2 {
+ compatible = "mstar,scldma2";
+ //reg = <0x1F000000 0x100>;
+ //clk,chiptop,scldma
+ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>;
+ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk";
+ status = "ok";
+ interrupts = ;
+ };
+ scldma3: scldma3 {
+ compatible = "mstar,scldma3";
+ //reg = <0x1F000000 0x100>;
+ //clk,chiptop,scldma
+ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>;
+ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk";
+ status = "ok";
+ interrupts = ;
+ };
+ scldma4: scldma4 {
+ compatible = "mstar,scldma4";
+ //reg = <0x1F000000 0x100>;
+ //clk,chiptop,scldma
+ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>;
+ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk";
+ status = "ok";
+ interrupts = ;
+ };
+
+ vip: vip {
+ compatible = "mstar,vip";
+ status = "ok";
+
+ //reg = <0x1F224000 0x200>;
+ };
+
+ pnl: pnl {
+ compatible = "mstar,pnl";
+ status = "ok";
+
+ //Reg = <0x1F224000 0x200>;
+ };
+
+ uart0: uart@1F221000 {
+ compatible = "mstar,uart";
+ reg = <0x1F221000 0x100>;
+ interrupts = ;
+ clocks = <&CLK_uart0>;
+ status = "ok";
+ };
+ uart1: uart@1F221200 {
+ compatible = "mstar,uart";
+ reg = <0x1F221200 0x100>;
+ interrupts = ;
+ clocks = <&CLK_uart1>;
+ status = "ok";
+ };
+ fuart: uart@1F220400 {
+ compatible = "mstar,uart";
+ reg = <0x1F220400 0x100>, <0x1F220600 0x100>;
+ interrupts = , ;
+ clocks = <&CLK_fuart>;
+ dma = <1>;
+ status = "ok";
+ };
+
+ emac {
+ compatible = "mstar-emac";
+ interrupts = , ;
+ clocks = <&CLK_emac_ahb>,<&CLK_emac_tx>,<&CLK_emac_rx>,<&GATE_MCM_emac>, <&GATE_SRAM_emac>;
+ };
+
+ flashisp {
+ compatible = "mtd-flashisp";
+ clocks = <&CLK_bdma>;
+ quadread = <0>;
+ };
+
+ nandflash {
+ compatible = "ms-nand";
+ clocks =<&CLK_fcie>, <&CLK_ecc>, <&GATE_MCM_fcie>, <&GATE_SRAM_fcie>;
+ interrupts = ;
+ };
+
+ spinandflash {
+ compatible = "ms-spinand";
+ clocks =<&CLK_bdma>;
+ };
+
+ Mstar-ehci-1 {
+ compatible = "Mstar-ehci-1";
+ clocks = <&CLK_usb>, <&GATE_MCM_usb>, <&GATE_SRAM_usb>;
+ interrupts = ;
+ };
+
+ isp: isp {
+ compatible = "isp";
+ io_phy_addr = <0x1f000000>;
+ banks = <0x1302>,<0x1303>,<0x1304>,<0x1305>,<0x1306>,<0x1307>,<0x1308>,<0x1309>;
+ interrupts = ;
+ clocks = <&CLK_isp>,<&CLK_sr_mclk>,<&CLK_sr>,<&CLK_csi_mac>;
+ };
+ spi: spi {
+ compatible = "mstar_spi";
+ io_phy_addr = <0x1f000000>;
+ banks = <0x1110>,<0x1111>,<0x1038>,<0x101E>;
+ interrupts = ,;
+ };
+ spidev: spidev {
+ compatible = "spidev";
+ };
+ csi: csi {
+ compatible = "csi";
+ io_phy_addr = <0x1f000000>;
+ banks = <0x1204>;
+ interrupts = ;
+ };
+
+ jpe0: jpe@0x1F264000 {
+ compatible = "mstar,cedric-jpe";
+ reg = <0x1F264000 0x100>;
+ interrupts = ;
+ clocks = <&CLK_jpe>,<&GATE_MCM_jpe>, <&GATE_SRAM_jpe>;
+ clk-select = <0>; // 0: 288MHz 1: 216MHz 2: 54MHz 3: 27MHz
+ status = "ok";
+ };
+
+ i2c0: i2c@0{
+ compatible = "mstar,i2c";
+ reg = <0x1F223000 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&CLK_miic0>;
+ i2c-group = <0>;
+ i2c-speed = <2>;//0~6
+ status = "disable";
+ };
+
+ i2c1: i2c@1{
+ compatible = "mstar,i2c";
+ reg = <0x1F223200 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&CLK_miic1>;
+ i2c-group = <1>;
+ i2c-speed = <2>;//0~6
+ 24c512@54 {
+ compatible = "mstar,24c512";
+ reg = <0x54>;
+ };
+ };
+
+ gpio:gpio{
+ compatible = "mstar,gpio";
+ reg = <0x1F207800 0x200>,<0x1F203C00 0x200>,<0x1F001E00 0x200>,<0x1F001C00 0x200>;
+ gpio-num = <102>;
+ };
+
+ sound {
+ compatible = "mstar,infinity-audio";
+// reg = <0x1F000000 0x1000000>;
+ interrupts=;
+ playback-volume-level=<64>; //0~76
+ capture-volume-level=<64>;
+ micin-gain-sel=<11>; //0~31
+ linein-gain-level=<2>;//0~7
+ clocks = <&CLK_usb>, <&GATE_MCM_bach>, <&GATE_SRAM_bach>;
+ };
+
+ sdmmc {
+ compatible = "mstar,sdmmc";
+ interrupts=,
+ ,
+ ,
+ ;
+ //,,.... fice1->fice2->fice3 setting
+ clocks = <&CLK_sdio>,<&GATE_MCM_sdio>,<&GATE_SRAM_sdio>,<&CLK_fcie>,<&GATE_MCM_fcie>,<&GATE_SRAM_fcie>;
+ };
+
+ aesdma {
+ compatible = "mstar,infinity-aes";
+ clocks = <&CLK_aesdma>,<&GATE_MCM_aesdma>, <&GATE_SRAM_aesdma>;
+ };
+
+ gop{
+ compatible = "mstar,infinity-gop";
+ clocks = <&CLK_gop_psram>,<&CLK_fclk1>,<&GATE_MCM_gop>, <&GATE_SRAM_gop>;
+ };
+
+ rtc {
+ compatible = "mstar,infinity-rtc";
+ reg = <0x1F002400 0x40>;
+ interrupts=;
+ clocks = <&CLK_rtc>;
+ };
+
+ cpufreq {
+ compatible = "mstar,infinity-cpufreq";
+ };
+
+ watchdog: watchdog {
+ compatible = "mstar,infinity-wdt";
+ reg = <0x1F006000 0x40>;
+ };
+
+ sar: sar {
+ compatible = "mstar,infinity-sar";
+ reg = <0x1F002800 0x200>;
+ };
+
+ ircut {
+ compatible = "mstar,infinity-ircut";
+ ircut-gpio-num = ;///PM_GPIO_IRIN
+ interrupt-parent = <&ms_pmsleep_intr>;
+ interrupts = ;
+ };
+
+ pwm {
+ compatible = "mstar,infinity-pwm";
+ };
+
+ gpioi2c {
+ compatible = "mstar,infinity-gpioi2c";
+ sda-gpio = ;
+ scl-gpio = ;
+ };
+
+ pm {
+ compatible = "mstar,infinity-pm";
+ interrupt-parent = <&ms_pmsleep_intr>;
+ interrupts = ;
+ detect-gpio = ;
+ };
+ };
+};
+
+&clks {
+ #include <../../../../drivers/mstar/include/infinity/reg_clks.h>
+ #include "infinity-clks.dtsi"
+ #include "infinity-gates.dtsi"
+};
+
diff --git a/arch/arm/boot/dts/infinity3-BGA128M.dts b/arch/arm/boot/dts/infinity3-BGA128M.dts
new file mode 100644
index 00000000..523f4a75
--- /dev/null
+++ b/arch/arm/boot/dts/infinity3-BGA128M.dts
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "infinity3.dtsi"
+
+/ {
+ model = "INFINITY3 MSC000A-S01A";
+ compatible = "mstar,infinity3";
+
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/ram rootwait";
+ linux,initrd-start = <0x20FE0000>;
+ linux,initrd-end = <0x21000000>;
+ };
+
+ memory {
+ reg = <0x20000000 0x08000000>;
+ };
+
+/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+/*
+ miu_bist_mem: miu_bist_mem@27F00000 {
+ reg = <0x27F00000 0x00100000>;
+ no-map ;
+ status = "okay";
+ };
+*/
+ cma0 {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x05000000>;
+ alignment = <0x1000>;
+ linux,cma-default;
+ };
+
+ };
+
+ soc{
+ //Mstar-ehci-1 {
+ // dpdm_swap=<1>;
+ //};
+
+ //Mstar-ehci-2 {
+ // dpdm_swap=<1>;
+ //};
+ isp: isp {
+ //clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads
+ isp-flag = <0x3>; //enable DNR and ROT
+ isp-res = <0x5>; //max image size 5M
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/infinity3-BGA256M.dts b/arch/arm/boot/dts/infinity3-BGA256M.dts
new file mode 100644
index 00000000..baffffa7
--- /dev/null
+++ b/arch/arm/boot/dts/infinity3-BGA256M.dts
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "infinity3.dtsi"
+
+/ {
+ model = "INFINITY3 MSC000A-S01A-256M";
+ compatible = "mstar,infinity3";
+
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/ram rootwait";
+ linux,initrd-start = <0x20FE0000>;
+ linux,initrd-end = <0x21000000>;
+ };
+
+ memory {
+ reg = <0x20000000 0x10000000>;
+ };
+
+/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ miu_bist_mem: miu_bist_mem@27F00000 {
+ reg = <0x2FF00000 0x00100000>;
+ no-map ;
+ status = "okay";
+ };
+
+ cma0 {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x9000000>;
+ alignment = <0x1000>;
+ linux,cma-default;
+ };
+ };
+
+ soc {
+ isp: isp {
+ //clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads
+ isp-flag = <0x3>; //enable DNR and ROT
+ isp-res = <0x4>; //max image size 4M
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/infinity3-EXT256M.dts b/arch/arm/boot/dts/infinity3-EXT256M.dts
new file mode 100644
index 00000000..dc3e2e80
--- /dev/null
+++ b/arch/arm/boot/dts/infinity3-EXT256M.dts
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "infinity3.dtsi"
+
+/ {
+ model = "INFINITY3 MSC000A-S02A-256M";
+ compatible = "mstar,infinity3";
+
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/ram rootwait";
+ linux,initrd-start = <0x20FE0000>;
+ linux,initrd-end = <0x21000000>;
+ };
+
+ memory {
+ reg = <0x20000000 0x10000000>;
+ };
+
+/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ miu_bist_mem: miu_bist_mem@27F00000 {
+ reg = <0x2FF00000 0x00100000>;
+ no-map ;
+ status = "okay";
+ };
+
+ cma0 {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x9000000>;
+ alignment = <0x1000>;
+ linux,cma-default;
+ };
+ };
+
+ soc {
+ isp: isp {
+ //clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads
+ isp-flag = <0x3>; //enable DNR and ROT
+ isp-res = <0x5>; //max image size 5M
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/infinity3-EXT512M.dts b/arch/arm/boot/dts/infinity3-EXT512M.dts
new file mode 100644
index 00000000..513fd301
--- /dev/null
+++ b/arch/arm/boot/dts/infinity3-EXT512M.dts
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "infinity3.dtsi"
+
+/ {
+ model = "INFINITY3 MSC000A-S02A-512M";
+ compatible = "mstar,infinity3";
+
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/ram rootwait";
+ linux,initrd-start = <0x20FE0000>;
+ linux,initrd-end = <0x21000000>;
+ };
+
+ memory {
+ reg = <0x20000000 0x10000000>;
+ };
+
+ temp0:rammtd@0 {
+ compatible = "mtd-ram";
+ reg= <0x30000000 0x10000000>;
+ bank-width = <1>;
+ erase-size = <0x10000>;
+ linux,mtd-name = "temp0";
+ };
+
+/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ miu_bist_mem: miu_bist_mem@27F00000 {
+ reg = <0x2FF00000 0x00100000>;
+ no-map ;
+ status = "okay";
+ };
+
+ cma0 {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x7000000>;
+ alignment = <0x1000>;
+ linux,cma-default;
+ };
+ };
+
+ soc {
+ isp: isp {
+ //clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads
+ isp-flag = <0x3>; //enable DNR and ROT
+ isp-res = <0x5>; //max image size 5M
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/infinity3-QFN128M.dts b/arch/arm/boot/dts/infinity3-QFN128M.dts
new file mode 100644
index 00000000..fdcf9844
--- /dev/null
+++ b/arch/arm/boot/dts/infinity3-QFN128M.dts
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "infinity3.dtsi"
+
+/ {
+ model = "INFINITY3 MSC000A-S04A";
+ compatible = "mstar,infinity3";
+
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/ram rootwait";
+ linux,initrd-start = <0x20FE0000>;
+ linux,initrd-end = <0x21000000>;
+ };
+
+ memory {
+ reg = <0x20000000 0x08000000>;
+ };
+
+/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+/*
+ miu_bist_mem: miu_bist_mem@27F00000 {
+ reg = <0x27F00000 0x00100000>;
+ no-map ;
+ status = "okay";
+ };
+*/
+ cma0 {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x05000000>;
+ alignment = <0x1000>;
+ linux,cma-default;
+ };
+
+ };
+
+ soc {
+ isp: isp {
+ //clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads
+ isp-flag = <0x2>; //enable DNR and disable ROT
+ isp-res = <0x5>; //max image size 4M
+ };
+ Mstar-ehci-1 {
+ power-enable-pad = ;
+ };
+ cpufreq {
+ compatible = "mstar,infinity-cpufreq";
+ vid1-gpio = ;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/infinity3-QFN128MDC.dts b/arch/arm/boot/dts/infinity3-QFN128MDC.dts
new file mode 100644
index 00000000..39f920b7
--- /dev/null
+++ b/arch/arm/boot/dts/infinity3-QFN128MDC.dts
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "infinity3.dtsi"
+
+/ {
+ model = "INFINITY3 MSC000A-S04A";
+ compatible = "mstar,infinity3";
+
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/ram rootwait";
+ linux,initrd-start = <0x20FE0000>;
+ linux,initrd-end = <0x21000000>;
+ };
+
+ memory {
+ reg = <0x20000000 0x08000000>;
+ };
+
+/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+/*
+ miu_bist_mem: miu_bist_mem@27F00000 {
+ reg = <0x27F00000 0x00100000>;
+ no-map ;
+ status = "okay";
+ };
+*/
+ cma0 {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x05000000>;
+ alignment = <0x1000>;
+ linux,cma-default;
+ };
+
+ };
+
+ soc {
+ isp: isp {
+ //clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads
+ isp-flag = <0x3>; //enable DNR and ROT
+ isp-res = <0x5>; //max image size 5M
+ };
+ Mstar-ehci-1 {
+ power-enable-pad = ;
+ };
+ cpufreq {
+ compatible = "mstar,infinity-cpufreq";
+ vid1-gpio = ;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/infinity3-QFN64M.dts b/arch/arm/boot/dts/infinity3-QFN64M.dts
new file mode 100644
index 00000000..4823cd09
--- /dev/null
+++ b/arch/arm/boot/dts/infinity3-QFN64M.dts
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "infinity3.dtsi"
+
+/ {
+ model = "INFINITY3 MSC000A-S03A-64M";
+ compatible = "mstar,infinity3";
+
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8r root=/dev/ram rootwait isp_flag=0x0";
+ linux,initrd-start = <0x20FE0000>;
+ linux,initrd-end = <0x21000000>;
+ };
+
+ memory {
+ reg = <0x20000000 0x04000000>;
+ };
+
+/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+/*
+ miu_bist_mem: miu_bist_mem@23F00000 {
+ reg = <0x23F00000 0x00100000>;
+ no-map ;
+ status = "okay";
+ };
+*/
+ cma0 {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x01C00000>;
+ linux,cma-default;
+ };
+ };
+
+ soc {
+ isp: isp {
+ //clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads
+ isp-flag = <0x0>; //Disable DNR and ROT
+ isp-res = <0x1>; //max image size 2M
+ };
+ Mstar-ehci-1 {
+ power-enable-pad = ;
+ };
+ vip: vip {
+ CMDQ-mode = <0>;
+ };
+ cpufreq {
+ compatible = "mstar,infinity-cpufreq";
+ vid1-gpio = ;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/infinity3-QFN64MC.dts b/arch/arm/boot/dts/infinity3-QFN64MC.dts
new file mode 100644
index 00000000..9af07782
--- /dev/null
+++ b/arch/arm/boot/dts/infinity3-QFN64MC.dts
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "infinity3.dtsi"
+
+/ {
+ model = "INFINITY3 MSC000A-S03A-64M C313";
+ compatible = "mstar,infinity3";
+
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8r root=/dev/ram rootwait isp_flag=0x0";
+ linux,initrd-start = <0x20FE0000>;
+ linux,initrd-end = <0x21000000>;
+ };
+
+ memory {
+ reg = <0x20000000 0x04000000>;
+ };
+
+/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+/*
+ miu_bist_mem: miu_bist_mem@23F00000 {
+ reg = <0x23F00000 0x00100000>;
+ no-map ;
+ status = "okay";
+ };
+*/
+ cma0 {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x01C00000>;
+ linux,cma-default;
+ };
+ };
+
+ soc {
+ isp: isp {
+ //clk-pad = ;
+ clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads
+ isp-flag = <0>; //disable DNR and ROT
+ isp-res = <1>; //max image size 2M
+ };
+ Mstar-ehci-1 {
+ power-enable-pad = ;
+ };
+ vip: vip {
+ CMDQ-mode = <0>;
+ };
+ cpufreq {
+ compatible = "mstar,infinity-cpufreq";
+ vid1-gpio = ;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/infinity3-clks.dtsi b/arch/arm/boot/dts/infinity3-clks.dtsi
new file mode 100644
index 00000000..a56653c6
--- /dev/null
+++ b/arch/arm/boot/dts/infinity3-clks.dtsi
@@ -0,0 +1,1519 @@
+/* generated by CLK_DT_GEN_5 */
+/* CLK FILENAME: I3\iNfinity3e_Clock_Table_20161111_v0p2.xls */
+/* REG FILENAME: I3\20161109\iNfinity3e_reg_CLKGEN.xls, I3\20161109\iNfinity3e_reg_pm_sleep.xls, I3\20161109\iNfinity3e_reg_block.xls */
+
+CLK_VOID: CLK_VOID {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <1>;
+};
+
+CLK_mpll_432m: CLK_mpll_432m {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <432000000>;
+};
+
+CLK_upll_384m: CLK_upll_384m {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_upll>;
+ clock-div = <5>;
+ clock-mult = <4>;
+};
+
+CLK_upll_320m: CLK_upll_320m {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_upll>;
+ clock-div = <3>;
+ clock-mult = <2>;
+};
+
+CLK_mpll_288m: CLK_mpll_288m {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <288000000>;
+};
+
+CLK_utmi_240m: CLK_utmi_240m {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_utmi>;
+ clock-div = <2>;
+ clock-mult = <1>;
+};
+
+CLK_mpll_216m: CLK_mpll_216m {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <216000000>;
+};
+
+CLK_utmi_192m: CLK_utmi_192m {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_utmi>;
+ clock-div = <5>;
+ clock-mult = <2>;
+};
+
+CLK_mpll_172m: CLK_mpll_172m {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <172000000>;
+};
+
+CLK_utmi_160m: CLK_utmi_160m {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_utmi>;
+ clock-div = <3>;
+ clock-mult = <1>;
+};
+
+CLK_mpll_123m: CLK_mpll_123m {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <123000000>;
+};
+
+CLK_mpll_86m: CLK_mpll_86m {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <86000000>;
+};
+
+CLK_mpll_288m_div2: CLK_mpll_288m_div2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mpll_288m>;
+ clock-div = <2>;
+ clock-mult = <1>;
+};
+
+CLK_mpll_288m_div4: CLK_mpll_288m_div4 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mpll_288m>;
+ clock-div = <4>;
+ clock-mult = <1>;
+};
+
+CLK_mpll_288m_div8: CLK_mpll_288m_div8 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mpll_288m>;
+ clock-div = <8>;
+ clock-mult = <1>;
+};
+
+CLK_mpll_216m_div2: CLK_mpll_216m_div2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mpll_216m>;
+ clock-div = <2>;
+ clock-mult = <1>;
+};
+
+CLK_mpll_216m_div4: CLK_mpll_216m_div4 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mpll_216m>;
+ clock-div = <4>;
+ clock-mult = <1>;
+};
+
+CLK_mpll_216m_div8: CLK_mpll_216m_div8 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mpll_216m>;
+ clock-div = <8>;
+ clock-mult = <1>;
+};
+
+CLK_mpll_123m_div2: CLK_mpll_123m_div2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mpll_123m>;
+ clock-div = <2>;
+ clock-mult = <1>;
+};
+
+CLK_mpll_86m_div2: CLK_mpll_86m_div2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mpll_86m>;
+ clock-div = <2>;
+ clock-mult = <1>;
+};
+
+CLK_mpll_86m_div4: CLK_mpll_86m_div4 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mpll_86m>;
+ clock-div = <4>;
+ clock-mult = <1>;
+};
+
+CLK_mpll_86m_div16: CLK_mpll_86m_div16 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mpll_86m>;
+ clock-div = <16>;
+ clock-mult = <1>;
+};
+
+CLK_utmi_192m_div4: CLK_utmi_192m_div4 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_utmi_192m>;
+ clock-div = <4>;
+ clock-mult = <1>;
+};
+
+CLK_utmi_160m_div4: CLK_utmi_160m_div4 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_utmi_160m>;
+ clock-div = <4>;
+ clock-mult = <1>;
+};
+
+CLK_utmi_160m_div5: CLK_utmi_160m_div5 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_utmi_160m>;
+ clock-div = <5>;
+ clock-mult = <1>;
+};
+
+CLK_utmi_160m_div8: CLK_utmi_160m_div8 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_utmi_160m>;
+ clock-div = <8>;
+ clock-mult = <1>;
+};
+
+CLK_xtali_12m: CLK_xtali_12m {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <12000000>;
+};
+
+CLK_xtali_12m_div8: CLK_xtali_12m_div8 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_xtali_12m>;
+ clock-div = <8>;
+ clock-mult = <1>;
+};
+
+CLK_xtali_12m_div16: CLK_xtali_12m_div16 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_xtali_12m>;
+ clock-div = <16>;
+ clock-mult = <1>;
+};
+
+CLK_xtali_12m_div40: CLK_xtali_12m_div40 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_xtali_12m>;
+ clock-div = <40>;
+ clock-mult = <1>;
+};
+
+CLK_xtali_12m_div64: CLK_xtali_12m_div64 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_xtali_12m>;
+ clock-div = <64>;
+ clock-mult = <1>;
+};
+
+CLK_xtali_12m_div128: CLK_xtali_12m_div128 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_xtali_12m>;
+ clock-div = <128>;
+ clock-mult = <1>;
+};
+
+CLK_RTC_CLK_32K: CLK_RTC_CLK_32K {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+};
+
+CLK_pm_riu_w_clk_in: CLK_pm_riu_w_clk_in {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mcu>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu_w_clk_in: CLK_riu_w_clk_in {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mcu>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu_w_clk_top: CLK_riu_w_clk_top {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mcu>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu_w_clk_sc_gp: CLK_riu_w_clk_sc_gp {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mcu>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu_w_clk_vhe_gp: CLK_riu_w_clk_vhe_gp {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mcu>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu_w_clk_hemcu_gp: CLK_riu_w_clk_hemcu_gp {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mcu>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu_w_clk_mipi_if_gp: CLK_riu_w_clk_mipi_if_gp {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mcu>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu_w_clk_mcu_if_gp: CLK_riu_w_clk_mcu_if_gp {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mcu>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_p: CLK_miu_p {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_vhe_gp_p: CLK_miu_vhe_gp_p {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_vhe_gp>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_sc_gp_p: CLK_miu_sc_gp_p {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu2x_p: CLK_miu2x_p {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu2x>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_mcu_p: CLK_mcu_p {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mcu>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_mcu_pm_p: CLK_mcu_pm_p {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mcu_pm>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_isp_p: CLK_isp_p {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_isp>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_fclk1_p: CLK_fclk1_p {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_fclk1>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_fclk2_p: CLK_fclk2_p {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_fclk2>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_sdio_p: CLK_sdio_p {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_sdio>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_fcie_p: CLK_fcie_p {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_fcie>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_tck_buf: CLK_tck_buf {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <1>;
+};
+
+CLK_pad2isp_sr_pclk: CLK_pad2isp_sr_pclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <1>;
+};
+
+CLK_ccir_in_clk: CLK_ccir_in_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <1>;
+};
+
+CLK_eth_buf: CLK_eth_buf {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <1>;
+};
+
+CLK_rmii_buf: CLK_rmii_buf {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <1>;
+};
+
+CLK_emac_testrx125_in_lan: CLK_emac_testrx125_in_lan {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <1>;
+};
+
+CLK_miu_ff: CLK_miu_ff {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_sc_gp: CLK_miu_sc_gp {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_vhe_gp: CLK_miu_vhe_gp {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_dig: CLK_miu_dig {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_xd2miu: CLK_miu_xd2miu {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_urdma: CLK_miu_urdma {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_bdma: CLK_miu_bdma {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_vhe: CLK_miu_vhe {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_vhe_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_mfeh: CLK_miu_mfeh {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_mfe: CLK_miu_mfe {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_jpe1: CLK_miu_jpe1 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_jpe0: CLK_miu_jpe0 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_bach: CLK_miu_bach {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_file: CLK_miu_file {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_uhc0: CLK_miu_uhc0 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_emac: CLK_miu_emac {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_cmdq: CLK_miu_cmdq {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_isp_dnr: CLK_miu_isp_dnr {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_isp_rot: CLK_miu_isp_rot {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_isp_dma: CLK_miu_isp_dma {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_isp_sta: CLK_miu_isp_sta {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_gop: CLK_miu_gop {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_sc_dnr: CLK_miu_sc_dnr {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_sc_dnr_sad: CLK_miu_sc_dnr_sad {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_sc_crop: CLK_miu_sc_crop {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_sc1_frm: CLK_miu_sc1_frm {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_sc1_snp: CLK_miu_sc1_snp {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_sc1_snpi: CLK_miu_sc1_snpi {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_sc1_dbg: CLK_miu_sc1_dbg {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_sc2_frm: CLK_miu_sc2_frm {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_sc2_snpi: CLK_miu_sc2_snpi {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_sc3_frm: CLK_miu_sc3_frm {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_fcie: CLK_miu_fcie {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_sdio: CLK_miu_sdio {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu_ive: CLK_miu_ive {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_sc_gp_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu: CLK_riu {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_riu_w_clk_top>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu_nogating: CLK_riu_nogating {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_riu_w_clk_in>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu_sc_gp: CLK_riu_sc_gp {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_riu_w_clk_sc_gp>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu_vhe_gp: CLK_riu_vhe_gp {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_riu_w_clk_vhe_gp>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu_hemcu_gp: CLK_riu_hemcu_gp {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_riu_w_clk_hemcu_gp>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu_mipi_gp: CLK_riu_mipi_gp {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_riu_w_clk_mipi_if_gp>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu_mcu_if: CLK_riu_mcu_if {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_riu_w_clk_mcu_if_gp>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miu2x: CLK_miu2x {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_ddrpll_clk>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_axi2x: CLK_axi2x {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu2x_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_tck: CLK_tck {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_tck_buf>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_imi: CLK_imi {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_miu_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_gop0: CLK_gop0 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_fclk1_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_gop1: CLK_gop1 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_fclk1_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_gop2: CLK_gop2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_fclk2_p>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_mpll_144m: CLK_mpll_144m {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <144000000>;
+};
+
+CLK_mpll_144m_div2: CLK_mpll_144m_div2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mpll_144m>;
+ clock-div = <2>;
+ clock-mult = <1>;
+};
+
+CLK_mpll_144m_div4: CLK_mpll_144m_div4 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_mpll_144m>;
+ clock-div = <4>;
+ clock-mult = <1>;
+};
+
+CLK_xtali_24m: CLK_xtali_24m {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+};
+
+CLK_xtali_12m_div2: CLK_xtali_12m_div2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_xtali_12m>;
+ clock-div = <2>;
+ clock-mult = <1>;
+};
+
+CLK_xtali_12m_div4: CLK_xtali_12m_div4 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_xtali_12m>;
+ clock-div = <4>;
+ clock-mult = <1>;
+};
+
+CLK_xtali_12m_div12: CLK_xtali_12m_div12 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_xtali_12m>;
+ clock-div = <12>;
+ clock-mult = <1>;
+};
+
+CLK_rtc_32k: CLK_rtc_32k {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+};
+
+CLK_rtc_32k_div4: CLK_rtc_32k_div4 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_rtc_32k>;
+ clock-div = <4>;
+ clock-mult = <1>;
+};
+
+CLK_live_pm: CLK_live_pm {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_xtali_24m>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_riu_pm: CLK_riu_pm {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&CLK_pm_riu_w_clk_in>;
+ clock-div = <1>;
+ clock-mult = <1>;
+};
+
+CLK_miupll_clk: CLK_miupll_clk {
+ #clock-cells = <0>;
+ compatible = "mstar,complex-clock";
+ clocks = <&CLK_xtali_24m>;
+};
+
+CLK_ddrpll_clk: CLK_ddrpll_clk {
+ #clock-cells = <0>;
+ compatible = "mstar,complex-clock";
+ clocks = <&CLK_ddr_syn>;
+};
+
+CLK_lpll_clk: CLK_lpll_clk {
+ #clock-cells = <0>;
+ compatible = "mstar,complex-clock";
+ clocks = <&CLK_mpll_432m>;
+};
+
+CLK_cpupll_clk: CLK_cpupll_clk {
+ #clock-cells = <0>;
+ compatible = "mstar,complex-clock";
+ clocks = <&CLK_mpll_432m>;
+};
+
+CLK_utmi: CLK_utmi {
+ #clock-cells = <0>;
+// compatible = "mstar,complex-clock";
+// clocks = <&CLK_upll>;
+ compatible = "fixed-clock";
+ clock-frequency = <480000000>;
+};
+
+CLK_upll: CLK_upll {
+ #clock-cells = <0>;
+// compatible = "mstar,complex-clock";
+// clocks = <&CLK_xtali_24m>;
+ compatible = "fixed-clock";
+ clock-frequency = <480000000>;
+};
+
+CLK_fuart0_synth_out: CLK_fuart0_synth_out {
+ #clock-cells = <0>;
+ compatible = "mstar,complex-clock";
+ clocks = <&CLK_fuart0_synth_in>;
+};
+
+CLK_csi2_mac_p: CLK_csi2_mac_p {
+ #clock-cells = <0>;
+ compatible = "mstar,complex-clock";
+ clocks = <&CLK_csi_mac>;
+};
+
+CLK_miu: CLK_miu {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_216m>,<&CLK_miupll_clk>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_MIU_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_MIU_OFFSET
+ glitch-shift = <4>; //4+REG_CKG_MIU_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_ddr_syn: CLK_ddr_syn {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_432m>,<&CLK_mpll_216m>,<&CLK_xtali_12m>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_DDR_SYN_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_DDR_SYN_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_miu_rec: CLK_miu_rec {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div64>,<&CLK_xtali_12m_div128>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_MIU_REC_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_MIU_REC_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_mcu: CLK_mcu {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_216m>,<&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_216m_div2>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_MCU_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_MCU_OFFSET
+ glitch-shift = <4>; //4+REG_CKG_MCU_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_riubrdg: CLK_riubrdg {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mcu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_RIUBRDG_OFFSET
+ mux-width = <2>;
+ gate-shift = <8>; //0+REG_CKG_RIUBRDG_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_bdma: CLK_bdma {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_miu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_BDMA_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_BDMA_OFFSET
+};
+
+CLK_spi: CLK_spi {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_216m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_86m>,<&CLK_mpll_288m_div4>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_SPI_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_SPI_OFFSET
+ glitch-shift = <4>; //4+REG_CKG_SPI_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_uart0: CLK_uart0 {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_UART0_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_UART0_OFFSET
+};
+
+CLK_uart1: CLK_uart1 {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_UART1_OFFSET
+ mux-width = <2>;
+ gate-shift = <8>; //0+REG_CKG_UART1_OFFSET
+};
+
+CLK_fuart0_synth_in: CLK_fuart0_synth_in {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_432m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <6>; //2+REG_CKG_FUART0_SYNTH_IN_OFFSET
+ mux-width = <2>;
+ gate-shift = <4>; //0+REG_CKG_FUART0_SYNTH_IN_OFFSET
+};
+
+CLK_fuart: CLK_fuart {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_fuart0_synth_out>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_FUART_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_FUART_OFFSET
+};
+
+CLK_mspi0: CLK_mspi0 {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_MSPI0_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_MSPI0_OFFSET
+};
+
+CLK_mspi1: CLK_mspi1 {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_MSPI1_OFFSET
+ mux-width = <2>;
+ gate-shift = <8>; //0+REG_CKG_MSPI1_OFFSET
+};
+
+CLK_miic0: CLK_miic0 {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_MIIC0_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_MIIC0_OFFSET
+};
+
+CLK_miic1: CLK_miic1 {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_MIIC1_OFFSET
+ mux-width = <2>;
+ gate-shift = <8>; //0+REG_CKG_MIIC1_OFFSET
+};
+
+CLK_bist: CLK_bist {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_BIST_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_BIST_OFFSET
+};
+
+CLK_xtali: CLK_xtali {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_XTALI_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_XTALI_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_live: CLK_live {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_LIVE_OFFSET
+ mux-width = <2>;
+ gate-shift = <8>; //0+REG_CKG_LIVE_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_sr_mclk: CLK_sr_mclk {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_216m_div8>,<&CLK_mpll_86m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_86m_div16>,<&CLK_mpll_288m_div8>,<&CLK_mpll_216m_div4>,<&CLK_mpll_86m_div2>,<&CLK_mpll_123m_div2>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_SR_MCLK_OFFSET
+ mux-width = <3>;
+ gate-shift = <8>; //0+REG_CKG_SR_MCLK_OFFSET
+};
+
+CLK_bist_pm: CLK_bist_pm {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_BIST_PM_OFFSET
+ mux-width = <2>;
+ gate-shift = <8>; //0+REG_CKG_BIST_PM_OFFSET
+};
+
+CLK_bist_vhe_gp: CLK_bist_vhe_gp {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_BIST_VHE_GP_OFFSET
+ mux-width = <2>;
+ gate-shift = <8>; //0+REG_CKG_BIST_VHE_GP_OFFSET
+};
+
+CLK_vhe: CLK_vhe {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_utmi_240m>,<&CLK_mpll_216m>,<&CLK_utmi_192m>,<&CLK_utmi_160m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_VHE_OFFSET
+ mux-width = <3>;
+ gate-shift = <0>; //0+REG_CKG_VHE_OFFSET
+};
+
+CLK_xtali_sc_gp: CLK_xtali_sc_gp {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <6>; //2+REG_CKG_XTALI_SC_GP_OFFSET
+ mux-width = <2>;
+ gate-shift = <4>; //0+REG_CKG_XTALI_SC_GP_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_bist_sc_gp: CLK_bist_sc_gp {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_BIST_SC_GP_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_BIST_SC_GP_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_emac_ahb: CLK_emac_ahb {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_288m_div2>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_emac_testrx125_in_lan>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_EMAC_AHB_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_EMAC_AHB_OFFSET
+};
+
+CLK_mfe: CLK_mfe {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_288m>,<&CLK_utmi_240m>,<&CLK_utmi_192m>,<&CLK_mpll_123m>,<&CLK_upll_384m>,<&CLK_upll_320m>,<&CLK_mpll_172m>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_MFE_OFFSET
+ mux-width = <3>;
+ gate-shift = <0>; //0+REG_CKG_MFE_OFFSET
+};
+
+CLK_jpe: CLK_jpe {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_288m>,<&CLK_mpll_216m>,<&CLK_mpll_216m_div4>,<&CLK_mpll_216m_div8>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_JPE_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_JPE_OFFSET
+};
+
+CLK_aesdma: CLK_aesdma {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_86m>,<&CLK_mpll_172m>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_AESDMA_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_AESDMA_OFFSET
+ glitch-shift = <4>; //4+REG_CKG_AESDMA_OFFSET
+};
+
+CLK_sdio: CLK_sdio {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_utmi_160m_div4>,<&CLK_mpll_288m_div8>,<&CLK_utmi_160m_div5>,<&CLK_utmi_160m_div8>,<&CLK_xtali_12m>,<&CLK_xtali_12m_div40>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_SDIO_OFFSET
+ mux-width = <3>;
+ gate-shift = <0>; //0+REG_CKG_SDIO_OFFSET
+};
+
+CLK_fcie: CLK_fcie {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_123m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_86m>,<&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_utmi_160m_div4>,<&CLK_mpll_288m_div8>,<&CLK_utmi_160m_div5>,<&CLK_utmi_160m_div8>,<&CLK_mpll_86m_div16>,<&CLK_xtali_12m_div40>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_FCIE_OFFSET
+ mux-width = <4>;
+ gate-shift = <0>; //0+REG_CKG_FCIE_OFFSET
+};
+
+CLK_ecc: CLK_ecc {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_utmi_160m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_ECC_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_ECC_OFFSET
+};
+
+CLK_sr: CLK_sr {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_pad2isp_sr_pclk>,<&CLK_csi2_mac_p>,<&CLK_utmi_160m_div4>,<&CLK_mpll_86m>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_SR_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_SR_OFFSET
+};
+
+CLK_isp: CLK_isp {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_mpll_288m_div2>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_ISP_OFFSET
+ mux-width = <3>;
+ gate-shift = <8>; //0+REG_CKG_ISP_OFFSET
+};
+
+CLK_idclk: CLK_idclk {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_isp_p>,<&CLK_ccir_in_clk>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_IDCLK_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_IDCLK_OFFSET
+};
+
+CLK_fclk1: CLK_fclk1 {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_172m>,<&CLK_mpll_86m>,<&CLK_mpll_216m>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_FCLK1_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_FCLK1_OFFSET
+};
+
+CLK_fclk2: CLK_fclk2 {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_172m>,<&CLK_mpll_86m>,<&CLK_mpll_216m>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_FCLK2_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_FCLK2_OFFSET
+};
+
+CLK_odclk: CLK_odclk {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_86m>,<&CLK_mpll_86m_div2>,<&CLK_mpll_86m_div4>,<&CLK_lpll_clk>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_ODCLK_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_ODCLK_OFFSET
+};
+
+CLK_ive: CLK_ive {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_216m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>,<&CLK_mpll_86m>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_IVE_OFFSET
+ mux-width = <2>;
+ gate-shift = <8>; //0+REG_CKG_IVE_OFFSET
+};
+
+CLK_nlm: CLK_nlm {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_miu_p>,<&CLK_fclk1_p>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_NLM_OFFSET
+ mux-width = <1>;
+ gate-shift = <8>; //0+REG_CKG_NLM_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_emac_tx: CLK_emac_tx {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_EMAC_TX_OFFSET
+ mux-width = <1>;
+ gate-shift = <0>; //0+REG_CKG_EMAC_TX_OFFSET
+};
+
+CLK_emac_rx: CLK_emac_rx {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_EMAC_RX_OFFSET
+ mux-width = <1>;
+ gate-shift = <0>; //0+REG_CKG_EMAC_RX_OFFSET
+};
+
+CLK_emac_tx_ref: CLK_emac_tx_ref {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_rmii_buf>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_EMAC_TX_REF_OFFSET
+ mux-width = <1>;
+ gate-shift = <8>; //0+REG_CKG_EMAC_TX_REF_OFFSET
+};
+
+CLK_emac_rx_ref: CLK_emac_rx_ref {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_rmii_buf>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_EMAC_RX_REF_OFFSET
+ mux-width = <1>;
+ gate-shift = <8>; //0+REG_CKG_EMAC_RX_REF_OFFSET
+};
+
+CLK_hemcu_216m: CLK_hemcu_216m {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_216m>;
+ reg = ;
+ gate-shift = <0>; //0+REG_CKG_HEMCU_216M_OFFSET
+};
+
+CLK_csi_mac: CLK_csi_mac {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_xtali_12m>,<&CLK_mpll_216m>,<&CLK_mpll_288m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_CSI_MAC_OFFSET
+ mux-width = <3>;
+ gate-shift = <0>; //0+REG_CKG_CSI_MAC_OFFSET
+};
+
+CLK_mac_lptx: CLK_mac_lptx {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_xtali_12m>,<&CLK_mpll_216m>,<&CLK_mpll_288m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_MAC_LPTX_OFFSET
+ mux-width = <3>;
+ gate-shift = <8>; //0+REG_CKG_MAC_LPTX_OFFSET
+};
+
+CLK_ns: CLK_ns {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_xtali_12m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_NS_OFFSET
+ mux-width = <2>;
+ gate-shift = <0>; //0+REG_CKG_NS_OFFSET
+};
+
+CLK_mcu_pm: CLK_mcu_pm {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_mpll_216m>,<&CLK_utmi_192m>,<&CLK_mpll_172m>,<&CLK_utmi_160m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_123m>,<&CLK_mpll_216m_div2>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_24m>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_MCU_PM_OFFSET
+ mux-width = <4>;
+ gate-shift = <0>; //0+REG_CKG_MCU_PM_OFFSET
+ glitch-shift = <7>; //7+REG_CKG_MCU_PM_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_spi_pm: CLK_spi_pm {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_rtc_32k>,<&CLK_mpll_216m_div8>,<&CLK_mpll_144m_div4>,<&CLK_mpll_86m_div2>,<&CLK_mpll_216m_div4>,<&CLK_mpll_144m_div2>,<&CLK_mpll_86m>,<&CLK_mpll_216m_div2>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>,<&CLK_xtali_12m>,<&CLK_xtali_24m>;
+ reg = ;
+ mux-shift = <10>; //2+REG_CKG_SPI_PM_OFFSET
+ mux-width = <4>;
+ gate-shift = <8>; //0+REG_CKG_SPI_PM_OFFSET
+ glitch-shift = <14>; //6+REG_CKG_SPI_PM_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_pm_sleep: CLK_pm_sleep {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>;
+ reg = ;
+ mux-shift = <12>; //2+REG_CKG_PM_SLEEP_OFFSET
+ mux-width = <3>;
+};
+
+CLK_sar: CLK_sar {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>;
+ reg = ;
+ mux-shift = <7>; //2+REG_CKG_SAR_OFFSET
+ mux-width = <3>;
+ gate-shift = <5>; //0+REG_CKG_SAR_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_rtc: CLK_rtc {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>;
+ reg = ;
+ mux-shift = <2>; //2+REG_CKG_RTC_OFFSET
+ mux-width = <3>;
+ gate-shift = <0>; //0+REG_CKG_RTC_OFFSET
+ auto-enable = <1>;
+};
+
+CLK_ir: CLK_ir {
+ #clock-cells = <0>;
+ compatible = "mstar,composite-clock";
+ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>;
+ reg = ;
+ mux-shift = <7>; //2+REG_CKG_IR_OFFSET
+ mux-width = <3>;
+ gate-shift = <5>; //0+REG_CKG_IR_OFFSET
+ auto-enable = <1>;
+};
+
+usclk: usclk {
+ compatible = "usclk";
+ clocks = <&CLK_RTC_CLK_32K>, <&CLK_VOID>, <&CLK_aesdma>, <&CLK_axi2x>, <&CLK_bdma>, <&CLK_bist>, <&CLK_bist_pm>, <&CLK_bist_sc_gp>, <&CLK_bist_vhe_gp>, <&CLK_ccir_in_clk>, <&CLK_cpupll_clk>, <&CLK_csi2_mac_p>, <&CLK_csi_mac>, <&CLK_ddr_syn>, <&CLK_ddrpll_clk>, <&CLK_ecc>, <&CLK_emac_ahb>, <&CLK_emac_rx>, <&CLK_emac_rx_ref>, <&CLK_emac_testrx125_in_lan>, <&CLK_emac_tx>, <&CLK_emac_tx_ref>, <&CLK_eth_buf>, <&CLK_fcie>, <&CLK_fcie_p>, <&CLK_fclk1>, <&CLK_fclk1_p>, <&CLK_fclk2>, <&CLK_fclk2_p>, <&CLK_fuart>, <&CLK_fuart0_synth_in>, <&CLK_fuart0_synth_out>, <&CLK_gop0>, <&CLK_gop1>, <&CLK_gop2>, <&CLK_hemcu_216m>, <&CLK_idclk>, <&CLK_imi>, <&CLK_ir>, <&CLK_isp>, <&CLK_isp_p>, <&CLK_ive>, <&CLK_jpe>, <&CLK_live>, <&CLK_live_pm>, <&CLK_lpll_clk>, <&CLK_mac_lptx>, <&CLK_mcu>, <&CLK_mcu_p>, <&CLK_mcu_pm>, <&CLK_mcu_pm_p>, <&CLK_mfe>, <&CLK_miic0>, <&CLK_miic1>, <&CLK_miu>, <&CLK_miu2x>, <&CLK_miu2x_p>, <&CLK_miu_bach>, <&CLK_miu_bdma>, <&CLK_miu_cmdq>, <&CLK_miu_dig>, <&CLK_miu_emac>, <&CLK_miu_fcie>, <&CLK_miu_ff>, <&CLK_miu_file>, <&CLK_miu_gop>, <&CLK_miu_isp_dma>, <&CLK_miu_isp_dnr>, <&CLK_miu_isp_rot>, <&CLK_miu_isp_sta>, <&CLK_miu_ive>, <&CLK_miu_jpe0>, <&CLK_miu_jpe1>, <&CLK_miu_mfe>, <&CLK_miu_mfeh>, <&CLK_miu_p>, <&CLK_miu_rec>, <&CLK_miu_sc1_dbg>, <&CLK_miu_sc1_frm>, <&CLK_miu_sc1_snp>, <&CLK_miu_sc1_snpi>, <&CLK_miu_sc2_frm>, <&CLK_miu_sc2_snpi>, <&CLK_miu_sc3_frm>, <&CLK_miu_sc_crop>, <&CLK_miu_sc_dnr>, <&CLK_miu_sc_dnr_sad>, <&CLK_miu_sc_gp>, <&CLK_miu_sc_gp_p>, <&CLK_miu_sdio>, <&CLK_miu_uhc0>, <&CLK_miu_urdma>, <&CLK_miu_vhe>, <&CLK_miu_vhe_gp>, <&CLK_miu_vhe_gp_p>, <&CLK_miu_xd2miu>, <&CLK_miupll_clk>, <&CLK_mpll_123m>, <&CLK_mpll_123m_div2>, <&CLK_mpll_144m>, <&CLK_mpll_144m_div2>, <&CLK_mpll_144m_div4>, <&CLK_mpll_172m>, <&CLK_mpll_216m>, <&CLK_mpll_216m_div2>, <&CLK_mpll_216m_div4>, <&CLK_mpll_216m_div8>, <&CLK_mpll_288m>, <&CLK_mpll_288m_div2>, <&CLK_mpll_288m_div4>, <&CLK_mpll_288m_div8>, <&CLK_mpll_432m>, <&CLK_mpll_86m>, <&CLK_mpll_86m_div16>, <&CLK_mpll_86m_div2>, <&CLK_mpll_86m_div4>, <&CLK_mspi0>, <&CLK_mspi1>, <&CLK_nlm>, <&CLK_ns>, <&CLK_odclk>, <&CLK_pad2isp_sr_pclk>, <&CLK_pm_riu_w_clk_in>, <&CLK_pm_sleep>, <&CLK_riu>, <&CLK_riu_hemcu_gp>, <&CLK_riu_mcu_if>, <&CLK_riu_mipi_gp>, <&CLK_riu_nogating>, <&CLK_riu_pm>, <&CLK_riu_sc_gp>, <&CLK_riu_vhe_gp>, <&CLK_riu_w_clk_hemcu_gp>, <&CLK_riu_w_clk_in>, <&CLK_riu_w_clk_mcu_if_gp>, <&CLK_riu_w_clk_mipi_if_gp>, <&CLK_riu_w_clk_sc_gp>, <&CLK_riu_w_clk_top>, <&CLK_riu_w_clk_vhe_gp>, <&CLK_riubrdg>, <&CLK_rmii_buf>, <&CLK_rtc>, <&CLK_rtc_32k>, <&CLK_rtc_32k_div4>, <&CLK_sar>, <&CLK_sdio>, <&CLK_sdio_p>, <&CLK_spi>, <&CLK_spi_pm>, <&CLK_sr>, <&CLK_sr_mclk>, <&CLK_tck>, <&CLK_tck_buf>, <&CLK_uart0>, <&CLK_uart1>, <&CLK_upll>, <&CLK_upll_320m>, <&CLK_upll_384m>, <&CLK_utmi>, <&CLK_utmi_160m>, <&CLK_utmi_160m_div4>, <&CLK_utmi_160m_div5>, <&CLK_utmi_160m_div8>, <&CLK_utmi_192m>, <&CLK_utmi_192m_div4>, <&CLK_utmi_240m>, <&CLK_vhe>, <&CLK_xtali>, <&CLK_xtali_12m>, <&CLK_xtali_12m_div12>, <&CLK_xtali_12m_div128>, <&CLK_xtali_12m_div16>, <&CLK_xtali_12m_div2>, <&CLK_xtali_12m_div4>, <&CLK_xtali_12m_div40>, <&CLK_xtali_12m_div64>, <&CLK_xtali_12m_div8>, <&CLK_xtali_24m>, <&CLK_xtali_sc_gp>;
+ clock-count = <179>;
+};
+
diff --git a/arch/arm/boot/dts/infinity3-fpga.dts b/arch/arm/boot/dts/infinity3-fpga.dts
new file mode 100644
index 00000000..fd77cd11
--- /dev/null
+++ b/arch/arm/boot/dts/infinity3-fpga.dts
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+ /*
+ * Memory Layout
+ * 0x20000000-0x24000000 64M Kernel
+ * 0x24000000-0x24800000 8M system
+ * 0x24800000-0x24900000 1M data
+ * 0x24900000-0x25000000 7M temp0
+ * 0x25000000-0x28000000 48M temp1
+ */
+/dts-v1/;
+#include "infinity3-fpga.dtsi"
+
+/ {
+ model = "INFINITY3 FPGA";
+ compatible = "mstar,infinity3";
+
+ memory {
+ reg = <0x20000000 0x05000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/ram rootwait";
+ linux,initrd-start = <0x23000000>;
+ linux,initrd-end = <0x23040000>;
+ };
+
+ sysp:rammtd@0 {
+ compatible = "mtd-ram";
+ reg= <0x27000000 0x00400000>;
+ bank-width = <1>;
+ linux,mtd-name = "SYSTEM";
+ };
+
+ /* Size of this partition must be identical to the size of data.jffs2 due to JFFS2 limitation */
+ datap:rammtd@1 {
+ compatible = "mtd-ram";
+ reg= <0x27400000 0x00100000>;
+ bank-width = <1>;
+ linux,mtd-name = "DATA";
+ erase-size = <0x10000>;
+ };
+
+ extp:rammtd@2 {
+ compatible = "mtd-ram";
+ reg= <0x27600000 0x00300000>;
+ bank-width = <1>;
+ linux,mtd-name = "EXT";
+ erase-size = <0x10000>;
+ };
+
+ temp0:rammtd@3 {
+ compatible = "mtd-ram";
+ reg= <0x27900000 0x00700000>;
+ bank-width = <1>;
+ linux,mtd-name = "temp0";
+ };
+
+ temp1:rammtd@4 {
+ compatible = "mtd-ram";
+ reg= <0x25000000 0x01000000>;
+ bank-width = <1>;
+ linux,mtd-name = "temp1";
+ };
+
+ temp2:rammtd@5 {
+ compatible = "mtd-ram";
+ reg= <0x26000000 0x01000000>;
+ bank-width = <1>;
+ linux,mtd-name = "temp2";
+ };
+
+/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ cma0 {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x02000000>;
+ alignment = <0x1000>;
+ linux,cma-default;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/infinity3-fpga.dtsi b/arch/arm/boot/dts/infinity3-fpga.dtsi
new file mode 100644
index 00000000..540e057f
--- /dev/null
+++ b/arch/arm/boot/dts/infinity3-fpga.dtsi
@@ -0,0 +1,298 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <../../../../drivers/mstar/include/infinity3/irqs.h>
+#include <../../../../drivers/mstar/include/infinity3/gpio.h>
+#include
+#include
+#include "skeleton.dtsi"
+
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ clocks = <&xtal>;
+ };
+ };
+
+ xtal: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <54000000>;
+ };
+
+ aliases {
+ console = &uart0;
+ serial0 = &uart0;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xFFFFFFFF>;
+
+
+ gic: interrupt-controller@16000000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
+ reg = <0x16001000 0x1000>,
+ <0x16002000 0x1000>;
+ };
+
+ ms_pmsleep_intr: interrupt-controller@0 {
+ compatible = "mstar,pmsleep-intr";
+ #interrupt-cells = <1>;
+ interrupt-parent=<&gic>;
+ interrupt-controller;
+ };
+
+
+ arch_timer {
+ compatible = "arm,cortex-a7-timer", "arm,armv7-timer";
+ interrupts = ,
+ ,
+ ,
+ ;
+ clock-frequency = <54000000>; /* arch_timer must use clock-frequency*/
+ };
+
+ clks: clocks{
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ };
+
+/*
+ timer_clockevent: timer@1F006040 {
+ compatible = "mstar,piu-clockevent";
+ reg = <0x1F006040 0x100>;
+ interrupts=;
+ clocks = <&CLK_xtali_12m>;
+ };
+*/
+ mfe: mfe {
+ compatible = "mstar,mfe";
+ reg = <0x1F264800 0x400>;
+ interrupts=;
+ clocks = <&xtal>;
+ clock-names = "CKG_mfe";
+ status = "ok";
+ };
+
+ vhe: vhe {
+ compatible = "mstar,vhe";
+ reg = <0x1F265200 0x600>,<0x1F265000 0x200>;
+ interrupts=;
+ clocks = <&xtal>;
+ clock-names = "CKG_vhe";
+ status = "ok";
+ };
+
+ hvsp1: hvsp1 {
+ compatible = "mstar,hvsp1";
+ //reg = <0x1F000000 0x100>;
+ //clk,chiptop,hvsp0,sc0,dnr,ldc
+ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>;
+ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk";
+ status = "ok";
+ interrupts = , ;
+ };
+
+ hvsp2: hvsp2 {
+ compatible = "mstar,hvsp2";
+ //reg = <0x1F000000 0x100>;
+ //clk,chiptop,hvsp0,sc0,dnr,ldc
+ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>;
+ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk";
+ status = "ok";
+ interrupts = , ;
+ };
+
+ hvsp3: hvsp3 {
+ compatible = "mstar,hvsp3";
+ //reg = <0x1F000000 0x100>;
+ //clk,chiptop,hvsp0,sc0,dnr,ldc
+ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>;
+ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk";
+ status = "ok";
+ interrupts =