diff -drupN a/include/dt-bindings/clock/ingenic-x2000-v12-fpga.h b/include/dt-bindings/clock/ingenic-x2000-v12-fpga.h
--- a/include/dt-bindings/clock/ingenic-x2000-v12-fpga.h	1970-01-01 03:00:00.000000000 +0300
+++ b/include/dt-bindings/clock/ingenic-x2000-v12-fpga.h	2022-06-09 05:02:35.000000000 +0300
@@ -0,0 +1,130 @@
+#ifndef _DT_BINDINGS_CLOCK_M200_H
+#define _DT_BINDINGS_CLOCK_M200_H
+
+/* Fixed Clk */
+#define CLK_ID_FIEXED	0
+#define	CLK_EXT		(CLK_ID_FIEXED + 0)
+#define	CLK_RTC_EXT	(CLK_ID_FIEXED + 1)
+#define CLK_NR_FIXED	(2)
+
+/* PLL clk */
+#define CLK_ID_PLL	(CLK_ID_FIEXED + CLK_NR_FIXED)
+#define CLK_PLL_APLL	(CLK_ID_PLL + 0)
+#define CLK_PLL_MPLL	(CLK_ID_PLL + 1)
+#define CLK_PLL_EPLL	(CLK_ID_PLL + 2)
+#define CLK_NR_PLL	(3)
+
+/* CPU Clocks */
+#define CLK_ID_CPCCR		(CLK_ID_PLL + CLK_NR_PLL)
+#define CLK_MUX_SCLKA		(CLK_ID_CPCCR + 0)
+#define CLK_MUX_CPLL		(CLK_ID_CPCCR + 1)
+#define CLK_MUX_H0PLL		(CLK_ID_CPCCR + 2)
+#define CLK_MUX_H2PLL		(CLK_ID_CPCCR + 3)
+#define CLK_RATE_CPUCLK		(CLK_ID_CPCCR + 4)
+#define CLK_RATE_L2CCLK		(CLK_ID_CPCCR + 5)
+#define CLK_RATE_H0CLK		(CLK_ID_CPCCR + 6)
+#define CLK_RATE_H2CLK		(CLK_ID_CPCCR + 7)
+#define CLK_RATE_PCLK		(CLK_ID_CPCCR + 8)
+#define CLK_NR_CPCCR		(9)
+
+/* CGU clocks */
+#define CLK_ID_CGU		(CLK_ID_CPCCR + CLK_NR_CPCCR)
+#define CLK_CGU_DDR		(CLK_ID_CGU + 0)
+#define CLK_CGU_MAC0		(CLK_ID_CGU + 1)
+#define CLK_CGU_LCD		(CLK_ID_CGU + 2)
+#define CLK_CGU_MSC0		(CLK_ID_CGU + 3)
+#define CLK_CGU_MSC1		(CLK_ID_CGU + 4)
+#define CLK_CGU_SFC		(CLK_ID_CGU + 5)
+#define CLK_CGU_CIM		(CLK_ID_CGU + 6)
+#define CLK_CGU_PWM		(CLK_ID_CGU + 7)
+#define CLK_CGU_OST		(CLK_ID_CGU + 8)
+#define CLK_CGU_UART4		(CLK_ID_CGU + 9)
+#define CLK_CGU_UART3		(CLK_ID_CGU + 10)
+#define CLK_CGU_UART2		(CLK_ID_CGU + 11)
+#define CLK_CGU_UART1		(CLK_ID_CGU + 12)
+#define CLK_CGU_UART0		(CLK_ID_CGU + 13)
+#define CLK_CGU_SMB3		(CLK_ID_CGU + 14)
+#define CLK_CGU_SMB2		(CLK_ID_CGU + 15)
+#define CLK_CGU_SMB1		(CLK_ID_CGU + 16)
+#define CLK_CGU_SMB0		(CLK_ID_CGU + 17)
+#define CLK_CGU_SSI1		(CLK_ID_CGU + 18)
+#define CLK_CGU_SSI0		(CLK_ID_CGU + 19)
+#define CLK_CGU_PDMA		(CLK_ID_CGU + 20)
+#define CLK_CGU_MAC1		(CLK_ID_CGU + 21)
+#define CLK_CGU_MSC2		(CLK_ID_CGU + 22)
+#define CLK_CGU_SMB4		(CLK_ID_CGU + 23)
+#define CLK_NR_CGU		(24)
+
+#define CLK_ID_CGU_AUDIO	(CLK_ID_CGU + CLK_NR_CGU)
+#define CLK_CGU_I2S0		(CLK_ID_CGU_AUDIO + 0)
+#define CLK_CGU_I2S1		(CLK_ID_CGU_AUDIO + 1)
+#define CLK_CGU_I2S2		(CLK_ID_CGU_AUDIO + 2)
+#define CLK_CGU_I2S3		(CLK_ID_CGU_AUDIO + 3)
+#define CLK_CGU_SPDIF		(CLK_ID_CGU_AUDIO + 4)
+#define CLK_CGU_PCM		(CLK_ID_CGU_AUDIO + 5)
+#define CLK_CGU_DMIC		(CLK_ID_CGU_AUDIO + 6)
+#define CLK_NR_CGU_AUDIO	(7)
+
+/* Gate Clocks */
+#define CLK_ID_GATE		(CLK_ID_CGU_AUDIO + CLK_NR_CGU_AUDIO)
+#define CLK_GATE_DDR		(CLK_ID_GATE + 0)
+#define CLK_GATE_CPU1		(CLK_ID_GATE + 1)
+#define CLK_GATE_AHB0		(CLK_ID_GATE + 2)
+#define CLK_GATE_APB0		(CLK_ID_GATE + 3)
+#define CLK_GATE_RTC		(CLK_ID_GATE + 4)
+#define CLK_GATE_SSI1		(CLK_ID_GATE + 5)
+#define CLK_GATE_MAC0		(CLK_ID_GATE + 6)
+#define CLK_GATE_AES		(CLK_ID_GATE + 7)
+#define CLK_GATE_LCD		(CLK_ID_GATE + 8)
+#define CLK_GATE_CIM		(CLK_ID_GATE + 9)
+#define CLK_GATE_PDMA		(CLK_ID_GATE + 10)
+#define CLK_GATE_OST		(CLK_ID_GATE + 11)
+#define CLK_GATE_SSI0		(CLK_ID_GATE + 12)
+#define CLK_GATE_TCU		(CLK_ID_GATE + 13)
+#define CLK_GATE_DTRNG		(CLK_ID_GATE + 14)
+#define CLK_GATE_UART2		(CLK_ID_GATE + 15)
+#define CLK_GATE_UART1		(CLK_ID_GATE + 16)
+#define CLK_GATE_UART0		(CLK_ID_GATE + 17)
+#define CLK_GATE_SADC		(CLK_ID_GATE + 18)
+#define CLK_GATE_JPEG		(CLK_ID_GATE + 19)
+#define CLK_GATE_AUDIO		(CLK_ID_GATE + 20)
+#define CLK_GATE_SMB3		(CLK_ID_GATE + 21)
+#define CLK_GATE_SMB2		(CLK_ID_GATE + 22)
+#define CLK_GATE_SMB1		(CLK_ID_GATE + 23)
+#define CLK_GATE_SMB0		(CLK_ID_GATE + 24)
+#define CLK_GATE_SCC		(CLK_ID_GATE + 25)
+#define CLK_GATE_MSC1		(CLK_ID_GATE + 26)
+#define CLK_GATE_MSC0		(CLK_ID_GATE + 27)
+#define CLK_GATE_OTG		(CLK_ID_GATE + 28)
+#define CLK_GATE_SFC		(CLK_ID_GATE + 29)
+#define CLK_GATE_EFUSE		(CLK_ID_GATE + 30)
+#define CLK_GATE_NEMC		(CLK_ID_GATE + 31)
+#define CLK_GATE_ARB		(CLK_ID_GATE + 32)
+#define CLK_GATE_MIPI		(CLK_ID_GATE + 33)
+#define CLK_GATE_CPU		(CLK_ID_GATE + 34)
+#define CLK_GATE_INTC		(CLK_ID_GATE + 35)
+#define CLK_GATE_GPIO		(CLK_ID_GATE + 36)
+#define CLK_GATE_SPDIF		(CLK_ID_GATE + 37)
+#define CLK_GATE_DMIC		(CLK_ID_GATE + 38)
+#define CLK_GATE_PCM		(CLK_ID_GATE + 39)
+#define CLK_GATE_I2S3		(CLK_ID_GATE + 40)
+#define CLK_GATE_I2S2		(CLK_ID_GATE + 41)
+#define CLK_GATE_I2S1		(CLK_ID_GATE + 42)
+#define CLK_GATE_I2S0		(CLK_ID_GATE + 43)
+#define CLK_GATE_ROT		(CLK_ID_GATE + 44)
+#define CLK_GATE_HASH		(CLK_ID_GATE + 45)
+#define CLK_GATE_PWM		(CLK_ID_GATE + 46)
+#define CLK_GATE_UART5		(CLK_ID_GATE + 47)
+#define CLK_GATE_UART4		(CLK_ID_GATE + 48)
+#define CLK_GATE_UART3		(CLK_ID_GATE + 49)
+#define CLK_GATE_SMB5		(CLK_ID_GATE + 50)
+#define CLK_GATE_SMB4		(CLK_ID_GATE + 51)
+#define CLK_GATE_USBPHY		(CLK_ID_GATE + 52)
+#define CLK_GATE_MAC1		(CLK_ID_GATE + 53)
+#define CLK_GATE_MSC2		(CLK_ID_GATE + 54)
+#define CLK_GATE_VPU		(CLK_ID_GATE + 55)
+#define CLK_NR_GATE		(56)
+#define CLK_ID_OTHER		(CLK_ID_GATE + CLK_NR_GATE)
+
+#define NR_CLKS		(CLK_NR_FIXED + CLK_NR_PLL + CLK_NR_CPCCR + CLK_NR_CGU + CLK_NR_CGU_AUDIO + CLK_NR_GATE)
+#endif