diff -drupN a/drivers/leds/leds-is31fl3736.h b/drivers/leds/leds-is31fl3736.h
--- a/drivers/leds/leds-is31fl3736.h	1970-01-01 03:00:00.000000000 +0300
+++ b/drivers/leds/leds-is31fl3736.h	2022-06-12 05:28:14.000000000 +0300
@@ -0,0 +1,113 @@
+/*
+ * drivers/leds/is31fl3736.h
+ * Driver for ISSI is31fl3736 of I2C LED controllers
+ *
+ * Copyright (C) 2018 Allwinner Technology Limited. All rights reserved.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef IS31FL3736_H_
+#define IS31FL3736_H_
+
+#ifndef BIT
+#define BIT(x) (1 << (x))
+#endif
+
+/**< contorl regs */
+/*!< Available page 0 to page 3 registers */
+#define IS31FL3736_REG_CMD         0xfd
+/*!< to lock/unlock command reg */
+#define IS31FL3736_RET_CMD_LOCK    0xfe
+ /*!< configure the interrupt func */
+#define IS31FL3736_REG_INTR_MASK   0XF0
+/*!< show the interrupt status */
+#define IS31FL3736_REG_INTR_STATUS 0XF1
+
+//CS-X 1~8; SW-Y 1 ~ 12; all == 8 * 12 == 96
+
+/**< when REG_CMD is 0x00, control page 0 regs */
+/*i: 0--24*/
+/*!< Set on or off state for each LED R(0~17h) (W) */
+#define IS31FL3736_REG_PG0_SWITCH(i)       (0x00 + (i))
+/*!< Store open state for each LED R(0~17h) (R) */
+#define IS31FL3736_REG_PG0_OPEN_STATUS(i)  (0x18 + (i))
+ /*!< Store short state for each LED R(0~17h) (R) */
+#define IS31FL3736_REG_PG0_SHORT_STATUS(i) (0x30 + (i))
+
+/**< when REG_CMD is 0x01, control page 1 regs */
+/*!< Set PWM duty for LED R(0~BEh) (W) */
+#define IS31FL3736_REG_PG1_PWM(i)    (i)
+
+/**< when REG_CMD is 0x02, control page 2 regs */
+/*!< Set operating mode of each dot R(0~BEh) (W) */
+#define IS31FL3736_REG_PG2_BREATH(i) (i)
+
+/**< when REG_CMD is 0x03, control page 3 regs */
+/*!< Configure the operation mode (W) */
+#define IS31FL3736_REG_PG3_CONFIG  0X00
+
+/* is31fl3736_NORMAL_EN_M : W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: When SSD is "0"*/
+/*IS31FL3736 works in software shutdown mode and to */
+/*normal operate the SSD bit should set to "1".*/
+#define IS31FL3736_NORMAL_EN_M  (BIT(0))
+#define IS31FL3736_NORMAL_EN_V  (0x1)
+#define IS31FL3736_NORMAL_EN_S  (0)
+
+/* is31fl3736_BREATH_EN_M : W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: those dots select working in ABM-x mode will*/
+/*start to run the pre-established timing. */
+/*If it is disabled, all dots work in PWM mode. */
+#define IS31FL3736_BREATH_EN_M  (BIT(1))
+#define IS31FL3736_BREATH_EN_V  (0x1)
+#define IS31FL3736_BREATH_EN_S  (1)
+
+#define IS31FL3736_SYNC_EN_M  ((IS31FL3736_SYNC_EN_V) << (IS31FL3736_SYNC_EN_S))
+#define IS31FL3736_SYNC_EN_V  (0x3)
+#define IS31FL3736_SYNC_EN_S  (6)
+
+/*!< Set the global current (W) */
+#define IS31FL3736_REG_PG3_CURR        0X01
+/*!< Set fade in and hold time for breath function of ABMi R(1~3) (W) */
+#define IS31FL3736_REG_PG3_FADE_IN(i)  (0x02 + (i - 1) * 4)
+/*!< Set fade out and hold time for breath function of ABMi R(1~3) (W) */
+#define IS31FL3736_REG_PG3_FADE_OUT(i) (0x03 + (i - 1) * 4)
+
+#define IS31FL3736_ABM_T1_V  (0x7)
+#define IS31FL3736_ABM_T1_S  (5)
+
+#define IS31FL3736_ABM_T2_V  (0x7)
+#define IS31FL3736_ABM_T2_S  (1)
+
+#define IS31FL3736_ABM_T3_V  (0x7)
+#define IS31FL3736_ABM_T3_S  (5)
+
+#define IS31FL3736_ABM_T4_V  (0x7)
+#define IS31FL3736_ABM_T4_S  (1)
+
+/*!< Set loop characters of ABM-i R(1~3) (W) */
+#define IS31FL3736_REG_PG3_LOOP1(i)  (0x04 + (i - 1) * 4)
+/*!< Set loop characters of ABM-i R(1~3) (W) */
+#define IS31FL3736_REG_PG3_LOOP2(i)  (0x05 + (i - 1) * 4)
+
+#define IS31FL3736_ABM_LTA_V  (0xf)
+#define IS31FL3736_ABM_LTA_S  (0)
+
+#define IS31FL3736_ABM_LTB_V  (0xff)
+#define IS31FL3736_ABM_LTB_S  (0)
+
+/*!< Update the setting of 02h ~ 0Dh registers (W) */
+#define IS31FL3736_REG_PG3_UPDATE      0X0E
+/*!< Set the pull-up resistor for SWy (W) */
+#define IS31FL3736_REG_PG3_SW_PULLUP   0X0F
+ /*!< Set the pull-down resistor for CSx (W) */
+#define IS31FL3736_REG_PG3_CS_PULLDOWN 0X10
+ /*!< Reset all register to POR state (R) */
+#define IS31FL3736_REG_PG3_RESET       0X11
+
+#endif
+