diff -drupN a/arch/arm/mach-sunxi/platsmp-v2.h b/arch/arm/mach-sunxi/platsmp-v2.h
--- a/arch/arm/mach-sunxi/platsmp-v2.h	1970-01-01 03:00:00.000000000 +0300
+++ b/arch/arm/mach-sunxi/platsmp-v2.h	2022-06-12 05:28:14.000000000 +0300
@@ -0,0 +1,147 @@
+/*
+ * arch/arm/mach-sunxi/platsmp-v2.h
+ *
+ * Copyright(c) 2013-2015 Allwinnertech Co., Ltd.
+ *      http://www.allwinnertech.com
+ *
+ * Author: east_yang <yangdong@allwinnertech.com>
+ *
+ * sunxi smp ops header file for platform v2
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __PLATSMP_V2_H__
+#define __PLATSMP_V2_H__
+
+#define C0_RST_CTRL			(0x00)
+#define C0_CTRL_REG0			(0x10)
+#define C0_CPU_STATUS			(0X80)
+#define DBG_REG0			(0xc0)
+
+#define C0_CPUX_RESET_REG		(0x40)
+#define C0_CPUX_PWROFF_GATING		(0x44)
+#define C0_CPUX_PWR_SW(cpu)		(0x50 + cpu * 4)
+
+#define CORE_RESET_OFFSET		(0x00)
+#define C0_CPUX_RESET_OFFSET		(0x00)
+#define L1_RST_DISABLE_OFFSET		(0x00)
+#define POROFF_GATING_CPUX_OFFSET	(0x00)
+#define C_DBGPWRDUP_OFFSET		(0x00)
+#define STANDBYWFI_OFFSET		(0x10)
+
+static inline int sunxi_is_wfi_mode(int cpu)
+{
+	return readl(sunxi_cpucfg_base + C0_CPU_STATUS) &
+			(1 << (STANDBYWFI_OFFSET + cpu));
+}
+
+static inline void sunxi_enable_cpu(int cpu)
+{
+	unsigned int value;
+
+	pr_debug("[%s]: start\n", __func__);
+
+	/* assert cpu core reset low */
+	value = readl(sunxi_cpucfg_base + C0_RST_CTRL);
+	value &= (~(0x1 << (CORE_RESET_OFFSET + cpu)));
+	writel(value, sunxi_cpucfg_base + C0_RST_CTRL);
+
+	/* assert power on reset low */
+	value = readl(sunxi_cpuscfg_base + C0_CPUX_RESET_REG);
+	value &= (~(0x1 << (C0_CPUX_RESET_OFFSET + cpu)));
+	writel(value, sunxi_cpuscfg_base + C0_CPUX_RESET_REG);
+
+	/* L1RSTDISABLE hold low */
+	value = readl(sunxi_cpucfg_base + C0_CTRL_REG0);
+	value &= (~(0x1 << (L1_RST_DISABLE_OFFSET + cpu)));
+	writel(value, sunxi_cpucfg_base + C0_CTRL_REG0);
+
+	/* DBGPWRDUPx hold low */
+	value = readl(sunxi_cpucfg_base + DBG_REG0);
+	value &= (~(0x1 << (C_DBGPWRDUP_OFFSET + cpu)));
+	writel(value, sunxi_cpucfg_base + DBG_REG0);
+
+	/* hold power-off gating */
+	value = readl(sunxi_cpuscfg_base + C0_CPUX_PWROFF_GATING);
+	value |= ((0x1 << (POROFF_GATING_CPUX_OFFSET + cpu)));
+	writel(value, (sunxi_cpuscfg_base + C0_CPUX_PWROFF_GATING));
+
+	/* Release power switch */
+	writel(0xFE, sunxi_cpuscfg_base + C0_CPUX_PWR_SW(cpu));
+	udelay(20);
+	writel(0xFC, sunxi_cpuscfg_base + C0_CPUX_PWR_SW(cpu));
+	udelay(10);
+	writel(0xF8, sunxi_cpuscfg_base + C0_CPUX_PWR_SW(cpu));
+	udelay(10);
+	writel(0xF0, sunxi_cpuscfg_base + C0_CPUX_PWR_SW(cpu));
+	udelay(10);
+	writel(0xC0, sunxi_cpuscfg_base + C0_CPUX_PWR_SW(cpu));
+	udelay(10);
+	writel(0x00, sunxi_cpuscfg_base + C0_CPUX_PWR_SW(cpu));
+	udelay(20);
+	while (readl(sunxi_cpuscfg_base + C0_CPUX_PWR_SW(cpu)) != 0x00)
+		;
+
+	/* Clear power-off gating */
+	value = readl(sunxi_cpuscfg_base + C0_CPUX_PWROFF_GATING);
+	value &= (~(0x1 << (POROFF_GATING_CPUX_OFFSET + cpu)));
+	writel(value, (sunxi_cpuscfg_base + C0_CPUX_PWROFF_GATING));
+
+	udelay(20);
+
+	/* Deassert power on reset high */
+	value = readl(sunxi_cpuscfg_base + C0_CPUX_RESET_REG);
+	value |= (0x1 << (C0_CPUX_RESET_OFFSET + cpu));
+	writel(value, sunxi_cpuscfg_base + C0_CPUX_RESET_REG);
+
+	/* Deassert core reset high */
+	value = readl(sunxi_cpucfg_base + C0_RST_CTRL);
+	value |= (0x1 << (CORE_RESET_OFFSET + cpu));
+	writel(value, sunxi_cpucfg_base + C0_RST_CTRL);
+
+	/* Assert DBGPWRDUPx high */
+	value = readl(sunxi_cpucfg_base + DBG_REG0);
+	value |= (0x1 << (C_DBGPWRDUP_OFFSET + cpu));
+	writel(value, sunxi_cpucfg_base + DBG_REG0);
+
+	pr_debug("[%s]: end\n", __func__);
+}
+
+static inline void sunxi_disable_cpu(int cpu)
+{
+	unsigned int value;
+
+	pr_debug("[%s]: start\n", __func__);
+
+	/* assert cpu core reset */
+	value = readl(sunxi_cpucfg_base + C0_RST_CTRL);
+	value &= (~(0x1 << (CORE_RESET_OFFSET + cpu)));
+	writel(value, sunxi_cpucfg_base + C0_RST_CTRL);
+
+	/* Deassert DBGPWRDUPx low */
+	value = readl(sunxi_cpucfg_base + DBG_REG0);
+	value &= (~(0x1 << (C_DBGPWRDUP_OFFSET + cpu)));
+	writel(value, sunxi_cpucfg_base + DBG_REG0);
+
+	/* power gating off */
+	value = readl(sunxi_cpuscfg_base + C0_CPUX_PWROFF_GATING);
+	value |= (0x1 << (POROFF_GATING_CPUX_OFFSET + cpu));
+	writel(value, (sunxi_cpuscfg_base + C0_CPUX_PWROFF_GATING));
+
+	udelay(20);
+
+	/* power switch off */
+	writel(0xff, sunxi_cpuscfg_base + C0_CPUX_PWR_SW(cpu));
+
+	udelay(30);
+
+	while (readl(sunxi_cpuscfg_base + C0_CPUX_PWR_SW(cpu)) != 0xff)
+		;
+
+	pr_debug("[%s]: end\n", __func__);
+}
+#endif /* __PLATSMP_V2_H__ */