diff --git a/Documentation/devicetree/bindings/arm/fh.txt b/Documentation/devicetree/bindings/arm/fh.txt new file mode 100644 index 00000000..e69de29b diff --git a/Documentation/devicetree/bindings/fh,fh_rtc.txt b/Documentation/devicetree/bindings/fh,fh_rtc.txt new file mode 100644 index 00000000..65d26208 --- /dev/null +++ b/Documentation/devicetree/bindings/fh,fh_rtc.txt @@ -0,0 +1,6 @@ +Example: + rtc: rtc@f1500000 { + compatible = "fh,fh_rtc"; + reg = <0xf1500000 0xc00>; + + }; \ No newline at end of file diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index bceffffb..388647a0 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -100,6 +100,7 @@ everspin Everspin Technologies, Inc. excito Excito ezchip EZchip Semiconductor fcs Fairchild Semiconductor +fh Fullhan Microelectronic Co.,Ltd firefly Firefly focaltech FocalTech Systems Co.,Ltd friendlyarm Guangzhou FriendlyARM Computer Tech Co., Ltd diff --git a/Makefile b/Makefile index 3f3c3403..95dc9f0a 100644 --- a/Makefile +++ b/Makefile @@ -638,10 +638,19 @@ KBUILD_CFLAGS += $(call cc-disable-warning, format-overflow) KBUILD_CFLAGS += $(call cc-disable-warning, int-in-bool-context) KBUILD_CFLAGS += $(call cc-disable-warning, attribute-alias) +ifneq ($(findstring -DCONFIG_EMULATION, $(EXTRA_CFLAGS)),) +$(info ### EMULATION ENVIRONMENT, use EXTRA_CFLAGS: $(EXTRA_CFLAGS)) +export CONFIG_EMULATION := y +export CONFIG_KERNEL_NO_COMPRESS := y +endif + ifdef CONFIG_LD_DEAD_CODE_DATA_ELIMINATION +# only enable these options when build kernel +ifeq ($(KBUILD_EXTMOD),) KBUILD_CFLAGS += $(call cc-option,-ffunction-sections,) KBUILD_CFLAGS += $(call cc-option,-fdata-sections,) endif +endif ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE KBUILD_CFLAGS += -Os $(call cc-disable-warning,maybe-uninitialized,) @@ -1600,7 +1609,7 @@ export_report: endif #ifeq ($(config-targets),1) endif #ifeq ($(mixed-targets),1) -PHONY += checkstack kernelrelease kernelversion image_name +PHONY += checkstack kernelrelease kernelversion image_name fhdtbimage # UML needs a little special treatment here. It wants to use the host # toolchain, so needs $(SUBARCH) passed to checkstack.pl. Everyone @@ -1611,6 +1620,14 @@ CHECKSTACK_ARCH := $(SUBARCH) else CHECKSTACK_ARCH := $(ARCH) endif + +PROJECT_NAME=$(shell grep -e '^CONFIG_MACH_FH.*' .config|sed 's/CONFIG_MACH_\(.*\)=y/\1/'|awk '{print tolower($$0)}') + +fhdtbimage: dtbs uImage + echo $(PROJECT_NAME) + cat arch/arm/boot/uImage arch/arm/boot/dts/${PROJECT_NAME}.dtb > arch/arm/boot/uImage_${PROJECT_NAME} + + checkstack: $(OBJDUMP) -d vmlinux $$(find . -name '*.ko') | \ $(PERL) $(src)/scripts/checkstack.pl $(CHECKSTACK_ARCH) diff --git a/arch/Kconfig b/arch/Kconfig index b39d0f93..e675fadd 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -477,21 +477,6 @@ config THIN_ARCHIVES Select this if the architecture wants to use thin archives instead of ld -r to create the built-in.o files. -config LD_DEAD_CODE_DATA_ELIMINATION - bool - help - Select this if the architecture wants to do dead code and - data elimination with the linker by compiling with - -ffunction-sections -fdata-sections and linking with - --gc-sections. - - This requires that the arch annotates or otherwise protects - its external entry points from being discarded. Linker scripts - must also merge .text.*, .data.*, and .bss.* correctly into - output sections. Care must be taken not to pull in unrelated - sections (e.g., '.text.init'). Typically '.' in section names - is used to distinguish them from label names / C identifiers. - config HAVE_ARCH_WITHIN_STACK_FRAMES bool help diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b5d529fd..402f22c3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -68,6 +68,7 @@ config ARM select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M select HAVE_KRETPROBES if (HAVE_KPROBES) select HAVE_MEMBLOCK + select HAVE_LD_DEAD_CODE_DATA_ELIMINATION if !FUNCTION_TRACER select HAVE_MOD_ARCH_SPECIFIC select HAVE_NMI select HAVE_OPROFILE if (HAVE_PERF_EVENTS) @@ -402,6 +403,17 @@ config ARCH_FOOTBRIDGE help Support for systems based on the DC21285 companion chip ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. + +config ARCH_FULLHAN + select SPARSE_IRQ + select MULTI_IRQ_HANDLER + select COMMON_CLK + select GENERIC_CLOCKEVENTS + select CLKSRC_OF if OF + select ARM_PATCH_PHYS_VIRT + bool "Fullhan SoC Support" + select ARCH_WANT_OPTIONAL_GPIOLIB + select ARCH_REQUIRE_GPIOLIB config ARCH_NETX bool "Hilscher NetX based" @@ -740,6 +752,7 @@ source "arch/arm/mach-dove/Kconfig" source "arch/arm/mach-ep93xx/Kconfig" source "arch/arm/mach-footbridge/Kconfig" +source "arch/arm/mach-fh/Kconfig" source "arch/arm/mach-gemini/Kconfig" @@ -947,7 +960,7 @@ endif config PJ4B_ERRATA_4742 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" - depends on CPU_PJ4B && MACH_ARMADA_370 + depends on CPU_PJ4B && MACH_ARMADA_370 || ARCH_FULLHAN default y help When coming out of either a Wait for Interrupt (WFI) or a Wait for diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index d83f7c36..736e9fff 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -270,6 +270,12 @@ choice help Say Y here if you want the debug print routines to direct their output to the 8250 at PCI COM1. + config DEBUG_FH_UART + bool "Fullhan Debug UART" + depends on ARCH_FULLHAN + help + Say Y here if you want kernel low-level debugging support + on FULLHAN UART. config DEBUG_GEMINI bool "Kernel low-level debugging messages via Cortina Systems Gemini UART" @@ -1432,6 +1438,8 @@ config DEBUG_LL_INCLUDE default "debug/bcm63xx.S" if DEBUG_BCM63XX_UART default "debug/digicolor.S" if DEBUG_DIGICOLOR_UA0 default "debug/brcmstb.S" if DEBUG_BRCMSTB_UART + default "debug/fh.S" if DEBUG_FH_UART + default "mach/debug-macro.S" # Compatibility options for PL01x @@ -1528,6 +1536,7 @@ config DEBUG_UART_PHYS default 0xf8020000 if DEBUG_AT91_SAMA5D2_UART1 default 0xf8b00000 if DEBUG_HIX5HD2_UART default 0xf991e000 if DEBUG_QCOM_UARTDM + default 0xf0700000 if DEBUG_FH_UART default 0xfc00c000 if DEBUG_AT91_SAMA5D4_USART3 default 0xfcb00000 if DEBUG_HI3620_UART default 0xfd883000 if DEBUG_ALPINE_UART0 @@ -1559,7 +1568,7 @@ config DEBUG_UART_PHYS DEBUG_S3C64XX_UART || \ DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \ DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0 || \ - DEBUG_AT91_UART + DEBUG_AT91_UART || DEBUG_FH_UART config DEBUG_UART_VIRT hex "Virtual base address of debug UART" @@ -1618,6 +1627,7 @@ config DEBUG_UART_VIRT default 0xfe230000 if DEBUG_PICOXCELL_UART default 0xfe300000 if DEBUG_BCM_KONA_UART default 0xfe800000 if ARCH_IOP32X + default 0xfe020000 if DEBUG_FH_UART default 0xfeb00000 if DEBUG_HI3620_UART || DEBUG_HIX5HD2_UART default 0xfeb24000 if DEBUG_RK3X_UART0 default 0xfeb26000 if DEBUG_RK3X_UART1 @@ -1658,7 +1668,7 @@ config DEBUG_UART_VIRT DEBUG_S3C64XX_UART || \ DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \ DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0 || \ - DEBUG_AT91_UART + DEBUG_AT91_UART || DEBUG_FH_UART config DEBUG_UART_8250_SHIFT int "Register offset shift for the 8250 debug UART" @@ -1712,7 +1722,7 @@ config DEBUG_UNCOMPRESS config UNCOMPRESS_INCLUDE string default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM || \ - PLAT_SAMSUNG || ARM_SINGLE_ARMV7M + PLAT_SAMSUNG || ARM_SINGLE_ARMV7M || ARCH_FULLHAN default "mach/uncompress.h" config EARLY_PRINTK diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 6be9ee14..84e44cf6 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -167,6 +167,7 @@ machine-$(CONFIG_ARCH_EFM32) += efm32 machine-$(CONFIG_ARCH_EP93XX) += ep93xx machine-$(CONFIG_ARCH_EXYNOS) += exynos machine-$(CONFIG_ARCH_FOOTBRIDGE) += footbridge +machine-$(CONFIG_ARCH_FULLHAN) += fh machine-$(CONFIG_ARCH_GEMINI) += gemini machine-$(CONFIG_ARCH_HIGHBANK) += highbank machine-$(CONFIG_ARCH_HISI) += hisi @@ -258,12 +259,23 @@ endif machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) platdirs := $(patsubst %,arch/arm/plat-%/,$(sort $(plat-y))) +ifeq ($(CONFIG_ARCH_FULLHAN),y) +CONFIG_FH_CHIP_NAME := $(subst ",,$(CONFIG_FH_CHIP_NAME)) +fhdirs := $(patsubst %,arch/arm/mach-fh/%,$(CONFIG_FH_CHIP_NAME)) +endif + ifneq ($(CONFIG_ARCH_MULTIPLATFORM),y) ifneq ($(CONFIG_ARM_SINGLE_ARMV7M),y) ifeq ($(KBUILD_SRC),) KBUILD_CPPFLAGS += $(patsubst %,-I%include,$(machdirs) $(platdirs)) +ifeq ($(CONFIG_ARCH_FULLHAN),y) +KBUILD_CPPFLAGS += $(patsubst %,-I%,$(fhdirs)) +endif else KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs) $(platdirs)) +ifeq ($(CONFIG_ARCH_FULLHAN),y) +KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%,$(fhdirs)) +endif endif endif endif diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile index 50f8d1be..a8829f8c 100644 --- a/arch/arm/boot/Makefile +++ b/arch/arm/boot/Makefile @@ -49,11 +49,17 @@ $(obj)/xipImage: FORCE $(obj)/Image: vmlinux FORCE $(call if_changed,objcopy) +# just copy Image to zImage when build a no compressed uImage +ifeq ($(CONFIG_KERNEL_NO_COMPRESS),y) +$(obj)/zImage: $(obj)/Image FORCE + @cp $(obj)/Image $(obj)/zImage +else $(obj)/compressed/vmlinux: $(obj)/Image FORCE $(Q)$(MAKE) $(build)=$(obj)/compressed $@ $(obj)/zImage: $(obj)/compressed/vmlinux FORCE $(call if_changed,objcopy) +endif endif diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index fc6d5415..8c828e36 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -218,6 +218,12 @@ not_angel: addcc r0, r0, pc cmpcc r4, r0 orrcc r4, r4, #1 @ remember we skipped cache_on +#if defined (CONFIG_CPU_V7) + /* remember in arm cortex-a7 all mmu facility is based on SMP bit */ + mrc p15, 0, r0, c1, c0, 1 + orr r0, #(1 << 6) + mcr p15, 0, r0, c1, c0, 1 +#endif blcs cache_on restart: adr r0, LC0 diff --git a/arch/arm/boot/compressed/vmlinux.lds.S b/arch/arm/boot/compressed/vmlinux.lds.S index 81c49315..61ae411f 100644 --- a/arch/arm/boot/compressed/vmlinux.lds.S +++ b/arch/arm/boot/compressed/vmlinux.lds.S @@ -78,7 +78,7 @@ SECTIONS . = BSS_START; __bss_start = .; - .bss : { *(.bss) } + .bss : { *(.bss) *(.bss.*) } _end = .; . = ALIGN(8); /* the stack must be 64-bit aligned */ diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7037201c..e6323859 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -161,6 +161,12 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \ exynos5440-sd5v1.dtb \ exynos5440-ssdk5440.dtb \ exynos5800-peach-pi.dtb +dtb-$(CONFIG_MACH_FH8856V200) += fh8856v200.dtb +dtb-$(CONFIG_MACH_FH8852V200) += fh8852v200.dtb +dtb-$(CONFIG_MACH_FH8858V200) += fh8858v200.dtb +dtb-$(CONFIG_MACH_FH8856V210) += fh8856v210.dtb +dtb-$(CONFIG_MACH_FH8852V210) += fh8852v210.dtb +dtb-$(CONFIG_MACH_FH8858V210) += fh8858v210.dtb dtb-$(CONFIG_ARCH_HI3xxx) += \ hi3620-hi4511.dtb dtb-$(CONFIG_ARCH_HIGHBANK) += \ diff --git a/arch/arm/boot/dts/fh8852v200.dts b/arch/arm/boot/dts/fh8852v200.dts new file mode 100644 index 00000000..31f53cbd --- /dev/null +++ b/arch/arm/boot/dts/fh8852v200.dts @@ -0,0 +1,956 @@ +/* + * Copyright (C) 2017 Fullhan Micorelectonics Co.,Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "skeleton.dtsi" +/include/ "fh8852v200_pinctrl.dtsi" +/ { + + + model = "FULLHAN FH8852V200"; + compatible = "fh,fh8852v200"; + interrupt-parent = <&intc>; + aliases { + i2c0 = &i2cbus0; + i2c1 = &i2cbus1; + i2c2 = &i2cbus2; + spi0 = &spi_bus0; + spi1 = &spi_bus1; + ttyS0 = &serial0; + ttyS1 = &serial1; + ttyS2 = &serial2; + }; + + cpus { + cpu@0 { + device_type = "cpu"; + compatible = "arm,arm1176jzf-s"; + }; + }; + + chosen { + bootargs = "coherent_pool=2M"; + }; + + intc: interrupt-controller@E0200000 { + compatible = "fh,fh-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xE0200000 0x1000>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pmu@f0000000 { + compatible = "fh,fh-pmu"; + reg = <0xf0000000 0x2100>; + SWRST_MAIN_CTRL = <0x40>; + }; + timer0: timer@f0c00000 { + compatible = "fh,fh-timer"; + interrupts = <3>; + clock-frequency = <1000000>; + reg = <0xf0c00000 0x14>; + }; + + timer1: timer@f0c00014 { + compatible = "fh,fh-timer"; + interrupts = <3>; + clock-frequency = <1000000>; + reg = <0xf0c00014 0x14>; + }; + + gpio0: gpio@f0300000 { + compatible = "fh,fh-gpio"; + reg = <0xf0300000 0x1000>; + #gpio_controller; + interrupt-controller; + interrupt-parent = <&intc>; + interrupts = <26>; + id = <0>; + ngpio = <32>; + base = <0>; + }; + + gpio1: gpio@f4000000 { + compatible = "fh,fh-gpio"; + reg = <0xf4000000 0x1000>; + #gpio_controller; + interrupt-controller; + interrupt-parent = <&intc>; + interrupts = <40>; + id = <1>; + ngpio = <32>; + base = <32>; + }; + + fhdma0: dma@e0300000 { + compatible = "fh,fh-axi-dmac"; + reg = <0xe0300000 0x1000>; + interrupts = <23>; + chan_allocation_order = <0>; + chan_priority = <1>; + block_size = <0x800>; + data_width = <2 0 0 0>; + clocks = <&ahb_clk>; + }; + + aes: aes@0xe8200000 { + compatible = "fh,fh-aes"; + reg = <0xe8200000 0x1000>; + interrupts = <16>; + }; + rtc: rtc@f1500000 { + compatible = "fh,fh_rtc"; + reg = <0xf1500000 0x1000>; + interrupts = <33>; + clocks = <&rtc_hclk_gate>; + lut_cof = <58>; + lut_offset = <0xff>; + tsensor_cp_default_out = <0x993>; + }; + sadc: sadc@f1200000 { + compatible = "fh,fh-sadc"; + reg = <0xf1200000 0x1000>; + interrupts = <20>; + ref-vol = <1800>; + active-bit = <0xfff>; + }; + efuse: efuse@0xf1600000 { + compatible = "fh,fh-efuse"; + reg = <0xf1600000 0x1000>; + key_switch = "enable"; + indep_power = "enable"; + }; + fh_perf: fh_perf@0xf0002018 { + compatible = "fh,fh-perf"; + reg = <0xf0000000 0x4000>; + interrupts = < 5 >; + + }; + spi_bus0: spi@f0500000 { + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + compatible = "fh,fh-spi"; + reg = <0xf0500000 0x4000>; + clk_in = <100000000>; + clock_source = <100000000>; + clock_source_num = <1>; + num-cs = <2>; + cs0_gpio = <6>; + cs1_gpio = <55>; + dma_enable = "disable"; + swap_support = "enable"; + rx_hs_no = <4>; + tx_hs_no = <5>; + bus_no = <0>; + multi_wire_size = <2>; + clk_name = "spi0_clk"; + rx_dma_channel = <0>; + tx_dma_channel = <1>; + increase_support = "disable"; + data_field_size = <0x1000>; + data_reg_offset = <0x1000>; + dma_protctl_enable = "disable"; + dma_protctl_data = <6>; + dma_master_sel_enable = "disable"; + dma_master_ctl_sel = <0>; + dma_master_mem_sel = <0>; + spidma_xfer_mode = "rx_only"; + interrupts = <28>; + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fh,m25p80"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + reg = <0x0 0>; //first value means which slave bind to the master. 0 means chip 0. 1 means chip 1 + partition@0 { + reg = <0x0 0x40000>; + label = "bootstrap"; + }; + partition@40000 { + reg = <0x40000 0x10000>; + label = "uboot-env"; + }; + partition@50000 { + reg = <0x50000 0x30000>; + label = "uboot"; + }; + partition@80000 { + reg = <0x80000 0x400000>; + label = "kernel"; + }; + partition@480000 { + reg = <0x480000 0x80000>; + label = "rootfs"; + }; + partition@500000 { + reg = <0x500000 0x300000>; + label = "app"; + }; + + }; + spidev0: spi@0 { + compatible = "rohm,dh2228fv"; + reg = <0x1 0>; + spi-max-frequency = <50000000>; + }; + }; + spi_bus1: spi@f0600000 { + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + compatible = "fh,fh-spi"; + reg = <0xf0600000 0x4000>; + clk_in = <100000000>; + clock_source = <100000000>; + clock_source_num = <1>; + num-cs = <2>; + cs0_gpio = <14>; + cs1_gpio = <57>; + dma_enable = "disable"; + swap_support = "disable"; + rx_hs_no = <2>; + tx_hs_no = <3>; + bus_no = <1>; + clk_name = "spi1_clk"; + rx_dma_channel = <2>; + tx_dma_channel = <3>; + increase_support = "disable"; + data_field_size = <0x1000>; + data_reg_offset = <0x1000>; + dma_protctl_enable = "disable"; + dma_protctl_data = <6>; + dma_master_sel_enable = "disable"; + dma_master_ctl_sel = <0>; + dma_master_mem_sel = <0>; + spidma_xfer_mode = "rx_only"; + interrupts = <21>; + spidev1: spi@1 { + compatible = "rohm,dh2228fv"; + reg = <0x0 0>; + spi-max-frequency = <50000000>; + }; + spidev2: spi@2 { + compatible = "rohm,dh2228fv"; + reg = <0x1 0>; + spi-max-frequency = <50000000>; + }; + }; + fhdwi2s: i2s@f0900000 { + compatible = "fh,fh-dw_i2s"; + reg = <0xf0900000 0x1000>; + interrupts = <25>; + clocks = <&i2s_clk>, <&ac_clk>; + clock-names = "i2s_clk", "acodec_mclk"; + rx_dma_channel = <2>; + tx_dma_channel = <3>; + dma_master = <0>; + dma_rx_hs_num = <10>; + dma_tx_hs_num = <11>; + }; + + fhacw: acw@f0a00000 { + compatible = "fh,fh-acw"; + reg = <0xf0a00000 0x1000>; + interrupts = <19>; + clocks = <&ac_clk>; + clock-names = "ac_clk"; + rx_dma_channel = <4>; + tx_dma_channel = <5>; + dma_master = <0>; + dma_rx_hs_num = <0>; + dma_tx_hs_num = <1>; + }; + + pwm: pwm@f0400000{ + compatible = "fh,fh-pwm"; + reg = <0xf0400000 0x1000>; + interrupts = <36>; + npwm = <14>; + }; + serial0: serial@f0700000 { + compatible = "fh,fh-serial"; + reg = <0xf0700000 0x1000>; + interrupts = <30>; + clock-frequency = <16666667>; + fifo-size = <32>; + }; + serial1: serial@f0800000 { + compatible = "fh,fh-serial"; + reg = <0xf0800000 0x1000>; + interrupts = <31>; + clock-frequency = <16666667>; + fifo-size = <64>; + }; + serial2: serial@f1300000 { + compatible = "fh,fh-serial"; + reg = <0xf1300000 0x1000>; + interrupts = <41>; + clock-frequency = <16666667>; + fifo-size = <64>; + }; + gmac0: gmac@e0600000 { + compatible = "fh,fh-gmac"; + reg = <0xe0600000 0x2000>; + interrupts = <44>; + phyreset-gpio = <29>; + }; + sdc0: sdc0@e2000000 { + compatible = "fh,fh-sdc"; + reg = <0xe2000000 0x4000>; + interrupts = <42>; + id = <0>; + buswidth = <4>; + wp-fixed = <1>; + cd-fixed = <0>; + drv-degree = <8>; + sam-degree = <0>; + scan-mux = <0>; + }; + sdc1: sdc1@e2200000 { + compatible = "fh,fh-sdc"; + reg = <0xe2200000 0x4000>; + interrupts = <43>; + id = <1>; + buswidth = <4>; + wp-fixed = <1>; + cd-fixed = <1>; + drv-degree = <8>; + sam-degree = <0>; + scan-mux = <2>; + }; + wdt: wdt@f0d00000{ + compatible = "fh,fh-wdt"; + reg = <0xf0d00000 0x1000>; + interrupts = <2>; + mode = <1>; + }; + i2cbus0: i2c@f0200000 { + compatible = "fh,fh-i2c"; + reg = <0xf0200000 0x2000>; + interrupts = <11>; + }; + i2cbus1: i2c@f0b00000 { + compatible = "fh,fh-i2c"; + reg = <0xf0b00000 0x2000>; + interrupts = <12>; + }; + i2cbus2: i2c@0xF0100000 { + compatible = "fh,fh-i2c"; + reg = <0xF0100000 0x2000>; + interrupts = <46>; + }; + clocks: src_clk@0xf0000000{ + compatible = "fh,fh-clk"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf0000000 0x80>; + ranges; + + osc_clk: mxtal@24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc_clk"; + }; + + pll_ddr_rclk: pllddrr{ + #clock-cells = <0>; + compatible = "fh pll-ddr-rclk"; + reg = <0xf0000010 0x4>,<0xf0000018 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f000000>; + divcop = <0xf000>; + clocks = <&osc_clk>; + clock-output-names = "pll_ddr_rclk"; + }; + pll_cpu_pclk: pllcpup{ + #clock-cells = <0>; + compatible = "fh pll-cpu-pclk"; + reg = <0xf0000014 0x4>,<0xf000006c 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f0000>; + divcop = <0xf00>; + clocks = <&osc_clk>; + clock-output-names = "pll_cpu_pclk"; + }; + pll_cpu_rclk: pllcpur{ + #clock-cells = <0>; + compatible = "fh pll-cpu-rclk"; + reg = <0xf0000014 0x4>,<0xf000006c 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f000000>; + divcop = <0xf000>; + clocks = <&osc_clk>; + clock-output-names = "pll_cpu_rclk"; + }; + pll_sys_pclk: pllsysp{ + #clock-cells = <0>; + compatible = "fh pll-sys-pclk"; + reg = <0xf0000064 0x4>,<0xf0000068 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f0000>; + divcop = <0xf00>; + clocks = <&osc_clk>; + clock-output-names = "pll_sys_pclk"; + }; + pll_sys_rclk: pllsysr{ + #clock-cells = <0>; + compatible = "fh pll-sys-rclk"; + reg = <0xf0000064 0x4>,<0xf0000068 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f000000>; + divcop = <0xf000>; + clocks = <&osc_clk>; + clock-output-names = "pll_sys_rclk"; + }; + sysp_div12_clk: syspdiv12clk{ + #clock-cells = <0>; + compatible = "fh sysp-div12-clk"; + reg = <0xf0000038 0x4>,<0x0 0x4>,<0x0 0x4>; + div = <0xf000000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "sysp_div12_clk"; + }; + ddr_clk: ddrclk{ + #clock-cells = <0>; + compatible = "fh fh-ddr-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x4000000>; + clocks = <&pll_ddr_rclk>; + clock-output-names = "ddr_clk"; + }; + arm_clk: armclk{ + #clock-cells = <0>; + compatible = "fh fh-arm-clk"; + reg = <0x0 0x4>,<0x0 0x4>,<0xf000000c 0x4>; + mux = <0x1>; + clocks = <&osc_clk>,<&pll_cpu_pclk>; + clock-output-names = "arm_clk"; + }; + arc_clk: arcclk{ + #clock-cells = <0>; + compatible = "fh fh-arc-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0xf000000c 0x4>; + gate = <0x4000000>; + mux = <0x1>; + clocks = <&osc_clk>,<&pll_cpu_rclk>; + clock-output-names = "arc_clk"; + }; + ahb_clk: ahbclk{ + #clock-cells = <0>; + compatible = "fh fh-ahb-clk"; + reg = <0xf0000024 0x4>,<0x0 0x4>,<0xf000000c 0x4>; + div = <0xf0000>; + mux = <0x1>; + clocks = <&osc_clk>,<&pll_sys_pclk>; + clock-output-names = "ahb_clk"; + }; + isp_aclk: ispaclk{ + #clock-cells = <0>; + compatible = "fh fh-ispa-clk"; + reg = <0xf0000024 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xf00>; + gate = <0x1>; + clocks = <&pll_sys_pclk>; + clock-output-names = "isp_aclk"; + }; + ispb_aclk: ispbclk{ + #clock-cells = <0>; + compatible = "fh fh-ispb-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + gate = <0x4>; + clocks = <&isp_aclk>; + clock-output-names = "ispb_aclk"; + }; + vpu_clk: vpuclk{ + #clock-cells = <0>; + compatible = "fh fh-vpu-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x80000000>; + clocks = <&isp_aclk>; + clock-output-names = "vpu_clk"; + }; + pix_clk: pixclk{ + #clock-cells = <0>; + compatible = "fh fh-pix-clk"; + reg = <0xf000002c 0x4>,<0x0 0x4>,<0x0 0x4>; + div = <0xf000000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "pix_clk"; + }; + jpeg_clk: jpegclk{ + #clock-cells = <0>; + compatible = "fh fh-jpeg-clk"; + reg = <0xf000005c 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + div = <0xf00000>; + gate = <0x40000000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "jpeg_clk"; + }; + bgm_clk: bgmclk{ + #clock-cells = <0>; + compatible = "fh fh-bgm-clk"; + reg = <0xf000005c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xf00000>; + gate = <0x40000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "bgm_clk"; + }; + jpeg_adapt_clk: jpegadaptclk{ + #clock-cells = <0>; + compatible = "fh fh-jpeg-adapt-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x2>; + clocks = <&jpeg_clk>; + clock-output-names = "jpeg_adapt_clk"; + }; + spi0_clk: spi0clk{ + #clock-cells = <0>; + compatible = "fh fh-spi0-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff>; + gate = <0x80>; + clocks = <&pll_sys_pclk>; + clock-output-names = "spi0_clk"; + }; + sdc0_clk: sdc0clk{ + #clock-cells = <0>; + compatible = "fh fh-sdc0-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + prediv =<8>; + div = <0xf00>; + gate = <0x200>; + clocks = <&pll_sys_pclk>; + clock-output-names = "sdc0_clk"; + }; + spi2_clk: spi2clk{ + #clock-cells = <0>; + compatible = "fh fh-spi2-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xf000>; + gate = <0x2>; + clocks = <&pll_sys_pclk>; + clock-output-names = "spi2_clk"; + }; + spi1_clk: spi1clk{ + #clock-cells = <0>; + compatible = "fh fh-spi1-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff0000>; + gate = <0x100>; + clocks = <&pll_sys_pclk>; + clock-output-names = "spi1_clk"; + }; + sdc1_clk: sdc1clk{ + #clock-cells = <0>; + compatible = "fh fh-sdc1-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + prediv =<8>; + div = <0xf000000>; + gate = <0x400>; + clocks = <&pll_sys_pclk>; + clock-output-names = "sdc1_clk"; + }; + veu_clk: veuclk{ + #clock-cells = <0>; + compatible = "fh fh-veu-clk"; + reg = <0xf0000024 0x4>,<0xf000001c 0x4>,<0xf000000c 0x4>; + div = <0x7000000>; + gate = <0x10>; + mux = <0x4>; + clocks = <&pll_sys_pclk>,<&pll_sys_rclk>; + clock-output-names = "veu_clk"; + }; + veu_adapt_clk: veuadaptclk{ + #clock-cells = <0>; + compatible = "fh fh-veu-adapt-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + gate = <0x20000000>; + clocks = <&veu_clk>; + clock-output-names = "veu_adapt_clk"; + }; + cis_clk_out: cisclk{ + #clock-cells = <0>; + compatible = "fh fh-cis-clk-out"; + reg = <0xf0000028 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff0000>; + gate = <0x800000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "cis_clk_out"; + }; + eth_clk: ethclk{ + #clock-cells = <0>; + compatible = "fh fh-eth-clk"; + reg = <0xf000003c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xf000000>; + gate = <0x2000000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "eth_clk"; + }; + eth_rmii_clk: ethrmiiclk { + #clock-cells = <0>; + compatible = "fh fh-ethrmii-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + gate = <0x10000000>; + clock-output-names = "eth_rmii_clk"; + }; + i2c0_clk: i2c0clk { + #clock-cells = <0>; + compatible = "fh fh-i2c0-clk"; + reg = <0xf0000034 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f0000>; + gate = <0x1000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "i2c0_clk"; + }; + + i2c1_clk: i2c1clk { + #clock-cells = <0>; + compatible = "fh fh-i2c1-clk"; + reg = <0xf0000034 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f000000>; + gate = <0x8000000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "i2c1_clk"; + }; + i2c2_clk: i2c2clk { + #clock-cells = <0>; + compatible = "fh fh-i2c2-clk"; + reg = <0xf000005c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f00>; + gate = <0x00000008>; + clocks = <&sysp_div12_clk>; + clock-output-names = "i2c2_clk"; + }; + + uart0_clk: uart0clk { + #clock-cells = <0>; + compatible = "fh fh-uart0-clk"; + reg = <0xf0000034 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x1f>; + gate = <0x2000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "uart0_clk"; + }; + + uart1_clk: uart1clk { + #clock-cells = <0>; + compatible = "fh fh-uart1-clk"; + reg = <0xf0000034 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x1f00>; + gate = <0x4000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "uart1_clk"; + }; + uart2_clk: uart2clk { + #clock-cells = <0>; + compatible = "fh fh-uart2-clk"; + reg = <0xf000005c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x7f>; + gate = <0x8000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "uart2_clk"; + }; + pwm_clk: pwmclk { + #clock-cells = <0>; + compatible = "fh fh-pwm-clk"; + reg = <0xf0000038 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff>; + gate = <0x10000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "pwm_clk"; + }; + efuse_clk: efuseclk { + #clock-cells = <0>; + compatible = "fh fh-efuse-clk"; + reg = <0xf0000028 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f000000>; + gate = <0x200000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "efuse_clk"; + }; + pts_clk: ptsclk { + #clock-cells = <0>; + compatible = "fh fh-pts-clk"; + reg = <0xf000002c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x1ff>; + gate = <0x80000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "pts_clk"; + }; + tmr0_clk: tmr0clk { + #clock-cells = <0>; + compatible = "fh fh-tmr0-clk"; + reg = <0xf0000038 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff0000>; + gate = <0x20000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "tmr0_clk"; + }; + + sadc_clk: sadcclk { + #clock-cells = <0>; + compatible = "fh fh-sadc-clk"; + reg = <0xf000003c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x7f0000>; + gate = <0x4000000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "sadc_clk"; + }; + gpio0_dbclk: gpio0dbclk { + #clock-cells = <0>; + compatible = "fh fh-gpio0-dbclk"; + reg = <0xf0000060 0x4>,<0xf0000060 0x4>,<0x0 0x4>; + div = <0x7fff>; + gate = <0x8000>; + prediv = <100>; + clocks = <&sysp_div12_clk>; + clock-output-names = "gpio0_dbclk"; + }; + gpio1_dbclk: gpio1dbclk { + #clock-cells = <0>; + compatible = "fh fh-gpio1-dbclk"; + reg = <0xf0000060 0x4>,<0xf0000060 0x4>,<0x0 0x4>; + div = <0x7fff0000>; + gate = <0x80000000>; + prediv = <100>; + clocks = <&sysp_div12_clk>; + clock-output-names = "gpio1_dbclk"; + }; + wdt_clk: wdtclk { + #clock-cells = <0>; + compatible = "fh fh-wdt-clk"; + reg = <0xf0000038 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + div = <0xff00>; + gate = <0x8000000>; + clocks = <&ahb_clk>; + clock-output-names = "wdt_clk"; + }; + ac_clk: acclk{ + #clock-cells = <0>; + compatible = "fh fh-ac-clk"; + reg = <0xf000003c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f>; + gate = <0x800>; + clocks = <&osc_clk>; + clock-output-names = "ac_clk"; + }; + i2s_clk: i2sclk{ + #clock-cells = <0>; + compatible = "fh fh-i2s-clk"; + reg = <0xf000003c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f00>; + gate = <0x1000000>; + clocks = <&ac_clk>; + clock-output-names = "i2s_clk"; + }; + mipi_dphy_clk: mipidphyclk { + #clock-cells = <0>; + compatible = "fh fh-mipi-dphy-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + gate = <0x100000>; + clock-output-names = "mipi_dphy_clk"; + }; + mipi_wrap_gate: mipiwrapclk { + #clock-cells = <0>; + compatible = "fh fh-mipi-wrap-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x20000000>; + clock-output-names = "mipi_wrap_gate"; + }; + rtc_hclk_gate: rtchclk { + #clock-cells = <0>; + compatible = "fh fh-rtc-hclk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x10000000>; + clock-output-names = "rtc_hclk_gate"; + }; + emac_hclk_gate: emachclk { + #clock-cells = <0>; + compatible = "fh fh-emac-hclk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x2000000>; + clock-output-names = "emac_hclk_gate"; + }; + usb_clk: usbclk { + #clock-cells = <0>; + compatible = "fh fh-usb-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x1000000>; + clock-output-names = "usb_clk"; + }; + aes_hclk_gate: aeshclk { + #clock-cells = <0>; + compatible = "fh fh-aes-hclk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x80>; + clock-output-names = "aes_hclk_gate"; + }; + ephy_clk_gate: ephyclk { + #clock-cells = <0>; + compatible = "fh fh-ephy-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x1>; + clock-output-names = "ephy_clk_gate"; + }; + sdc0_clk8x_gate: sdc08xclk { + #clock-cells = <0>; + compatible = "fh fh-sdc08x-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x4>; + clock-output-names = "sdc0_clk8x_gate"; + }; + sdc1_clk8x_gate: sdc18xclk { + #clock-cells = <0>; + compatible = "fh fh-sdc18x-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x8>; + clock-output-names = "sdc1_clk8x_gate"; + }; + mipic_pclk_gate: mipicpclk { + #clock-cells = <0>; + compatible = "fh fh-mipic-pclk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x10>; + clock-output-names = "mipic_pclk_gate"; + }; + gpio0_pclk_gate: gpio0pclk { + #clock-cells = <0>; + compatible = "fh fh-gpio0-pclk"; + reg = <0x0 0x4>,<0xf0000060 0x4>,<0x0 0x4>; + gate = <0x4000>; + clock-output-names = "gpio0_pclk_gate"; + }; + gpio1_pclk_gate: gpio1pclk { + #clock-cells = <0>; + compatible = "fh fh-gpio1-pclk"; + reg = <0x0 0x4>,<0xf0000060 0x4>,<0x0 0x4>; + gate = <0x40000000>; + clock-output-names = "gpio1_pclk_gate"; + }; + isp_hclk_gate: isphclk { + #clock-cells = <0>; + compatible = "fh fh-isp-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x1000000>; + clock-output-names = "isp_hclk_gate"; + }; + veu_hclk_gate: veuhclk { + #clock-cells = <0>; + compatible = "fh fh-veu-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x2000000>; + clock-output-names = "veu_hclk_gate"; + }; + bgm_hclk_gate: bgmhclk { + #clock-cells = <0>; + compatible = "fh fh-bgm-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x4000000>; + clock-output-names = "bgm_hclk_gate"; + }; + adapt_hclk_gate: adapthclk { + #clock-cells = <0>; + compatible = "fh fh-adapt-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x8000000>; + clock-output-names = "adapt_hclk_gate"; + }; + jpg_hclk_gate: jpghclk { + #clock-cells = <0>; + compatible = "fh fh-jpg-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x10000000>; + clock-output-names = "jpg_hclk_gate"; + }; + jpg_adapt_gate: jpgadaptclk { + #clock-cells = <0>; + compatible = "fh fh-jpg-adapt-clk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x20000000>; + clock-output-names = "jpg_adapt_gate"; + }; + vpu_hclk_gate: vpuhclk { + #clock-cells = <0>; + compatible = "fh fh-vpu-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x40000000>; + clock-output-names = "vpu_hclk_gate"; + }; + sdc0_clk_sample: sdc0clksample { + #clock-cells = <0>; + compatible = "fh fh-sdc0-clk_sample"; + reg = <0xf0000020 0x4>; + mux = <0xf0000>; + clocks = <&sdc0_clk>; + clock-output-names = "sdc0_clk_sample"; + }; + sdc0_clk_drv: sdc0clkdrv { + #clock-cells = <0>; + compatible = "fh fh-sdc0-clk_drv"; + reg = <0xf0000020 0x4>; + mux = <0xf00000>; + clocks = <&sdc0_clk>; + clock-output-names = "sdc0_clk_drv"; + }; + + sdc1_clk_sample: sdc1clksample { + #clock-cells = <0>; + compatible = "fh fh-sdc1-clk_sample"; + reg = <0xf0000020 0x4>; + mux = <0xf00>; + clocks = <&sdc1_clk>; + clock-output-names = "sdc1_clk_sample"; + }; + + sdc1_clk_drv: sdc1clkdrv { + #clock-cells = <0>; + compatible = "fh fh-sdc1-clk_drv"; + reg = <0xf0000020 0x4>; + mux = <0xf000>; + clocks = <&sdc1_clk>; + clock-output-names = "sdc1_clk_drv"; + }; + }; + }; + + usb_otg@e0700000 { + compatible = "fh_usb"; + reg = <0xe0700000 100000>; + interrupts = <39>; + clocks = <&usb_clk>; + dr_mode = "host"; + vbus_pwren = <47>; + clock-names = "otg"; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + }; + + usb2_phy: usbphy { + compatible = "fh,fh-usb2-phy"; + #phy-cells = <0>; + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/fh8852v200_pinctrl.dtsi b/arch/arm/boot/dts/fh8852v200_pinctrl.dtsi new file mode 100644 index 00000000..195479e3 --- /dev/null +++ b/arch/arm/boot/dts/fh8852v200_pinctrl.dtsi @@ -0,0 +1,2386 @@ +/* + * Copyright (C) 2020 Fullhan Micorelectonics Co.,Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + #define PUPD_NONE (0) + #define PUPD_UP (1) + #define PUPD_DOWN (2) +*/ + +/ { + pinctrl: pinctrl@f0000080 { + compatible = "fh,fh-pinctrl"; + reg = <0xf0000080 0x104>; + pad-num = <65>; + max-mux = <9>; + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_ETH + &pinctrl_I2C0 + &pinctrl_PWM2 + &pinctrl_PWM3 + &pinctrl_PWM4 + &pinctrl_PWM5 + &pinctrl_PWM6 + &pinctrl_PWM7 + &pinctrl_PWM8 + &pinctrl_PWM9 + &pinctrl_SADC_XAIN0 + &pinctrl_SADC_XAIN1 + &pinctrl_SD0_NO_WP + &pinctrl_SENSOR_CLK + &pinctrl_SSI0_4BIT + &pinctrl_UART0 + &pinctrl_UART1 + &pinctrl_GPIO4 + &pinctrl_GPIO13 + &pinctrl_GPIO30 + &pinctrl_GPIO31 + &pinctrl_GPIO32 + &pinctrl_GPIO43 + &pinctrl_GPIO44 + &pinctrl_GPIO47 + + &pinctrl_GPIO11 + &pinctrl_GPIO14 + &pinctrl_GPIO15 + &pinctrl_GPIO16 + &pinctrl_GPIO24 + &pinctrl_GPIO25 + &pinctrl_GPIO45 + &pinctrl_GPIO46 + &pinctrl_GPIO48 + &pinctrl_GPIO49 + &pinctrl_GPIO50 + &pinctrl_GPIO51 + &pinctrl_GPIO52 + &pinctrl_GPIO53 + &pinctrl_GPIO54 + &pinctrl_GPIO55 + &pinctrl_GPIO56 + &pinctrl_GPIO57 + &pinctrl_GPIO58 + &pinctrl_GPIO59 + &pinctrl_GPIO60 + &pinctrl_GPIO61 + &pinctrl_GPIO62 + &pinctrl_GPIO63 + >; + pinctrl_groups { + pinctrl_ACI2S: ACI2S { + fh,pins = < + &mux_AC_I2S_CLK 0 + &mux_AC_I2S_DI 0 + &mux_AC_I2S_DO 0 + &mux_AC_I2S_WS 0 + &mux_AC_MCLK 0 + >; + }; + pinctrl_AC_MCLK: AC_MCLK { + fh,pins = < + &mux_AC_MCLK 0 + >; + }; + pinctrl_ARCJTAG: ARCJTAG { + fh,pins = < + &mux_ARC_JTAG_TCK 0 + &mux_ARC_JTAG_TDI 0 + &mux_ARC_JTAG_TDO 0 + &mux_ARC_JTAG_TMS 0 + &mux_ARC_JTAG_TRSTN 0 + >; + }; + pinctrl_ARMJTAG: ARMJTAG { + fh,pins = < + &mux_ARM_JTAG_TCK 0 + &mux_ARM_JTAG_TDI 0 + &mux_ARM_JTAG_TDO 0 + &mux_ARM_JTAG_TMS 0 + &mux_ARM_JTAG_TRSTN 0 + >; + }; + pinctrl_DWI2S: DWI2S { + fh,pins = < + &mux_DW_I2S_CLK 0 + &mux_DW_I2S_DI 0 + &mux_DW_I2S_DO 0 + &mux_DW_I2S_WS 0 + >; + }; + pinctrl_ETH: ETH { + fh,pins = < + &mux_ETH_LINK_ACT 1 + &mux_ETH_LINK_STA 1 + >; + }; + pinctrl_I2C0: I2C0 { + fh,pins = < + &mux_I2C0_SCL 0 + &mux_I2C0_SDA 0 + >; + }; + pinctrl_I2C1: I2C1 { + fh,pins = < + &mux_I2C1_SCL 2 + &mux_I2C1_SDA 2 + >; + }; + pinctrl_I2C2: I2C2 { + fh,pins = < + &mux_I2C2_SCL 1 + &mux_I2C2_SDA 1 + >; + }; + pinctrl_PAEJTAG: PAEJTAG { + fh,pins = < + &mux_PAE_JTAG_TCK 0 + &mux_PAE_JTAG_TDI 0 + &mux_PAE_JTAG_TDO 0 + &mux_PAE_JTAG_TMS 0 + &mux_PAE_JTAG_TRSTN 0 + >; + }; + pinctrl_PWM0: PWM0 { + fh,pins = < + &mux_PWM0 0 + >; + }; + pinctrl_PWM1: PWM1 { + fh,pins = < + &mux_PWM1 0 + >; + }; + pinctrl_PWM10: PWM10 { + fh,pins = < + &mux_PWM10 0 + >; + }; + pinctrl_PWM11: PWM11 { + fh,pins = < + &mux_PWM11 0 + >; + }; + pinctrl_PWM2: PWM2 { + fh,pins = < + &mux_PWM2 0 + >; + }; + pinctrl_PWM3: PWM3 { + fh,pins = < + &mux_PWM3 0 + >; + }; + pinctrl_PWM4: PWM4 { + fh,pins = < + &mux_PWM4 0 + >; + }; + pinctrl_PWM5: PWM5 { + fh,pins = < + &mux_PWM5 0 + >; + }; + pinctrl_PWM6: PWM6 { + fh,pins = < + &mux_PWM6 1 + >; + }; + pinctrl_PWM7: PWM7 { + fh,pins = < + &mux_PWM7 1 + >; + }; + pinctrl_PWM8: PWM8 { + fh,pins = < + &mux_PWM8 1 + >; + }; + pinctrl_PWM9: PWM9 { + fh,pins = < + &mux_PWM9 1 + >; + }; + pinctrl_RMII: RMII { + fh,pins = < + &mux_MAC_MDC 1 + &mux_MAC_MDIO 1 + &mux_MAC_REF_CLK 0 + &mux_MAC_RMII_CLK 0 + &mux_MAC_RXDV 0 + &mux_MAC_RXD_0 0 + &mux_MAC_RXD_1 0 + &mux_MAC_TXD_0 0 + &mux_MAC_TXD_1 0 + &mux_MAC_TXEN 0 + >; + }; + pinctrl_RTC: RTC { + fh,pins = < + &mux_RTC_CLK 0 + >; + }; + pinctrl_SADC_XAIN0: SADC_XAIN0 { + fh,pins = < + &mux_SADC_XAIN0 0 + >; + }; + pinctrl_SADC_XAIN1: SADC_XAIN1 { + fh,pins = < + &mux_SADC_XAIN1 0 + >; + }; + pinctrl_SADC_XAIN2: SADC_XAIN2 { + fh,pins = < + &mux_SADC_XAIN2 0 + >; + }; + pinctrl_SADC_XAIN3: SADC_XAIN3 { + fh,pins = < + &mux_SADC_XAIN3 0 + >; + }; + pinctrl_SD0: SD0 { + fh,pins = < + &mux_SD0_CD 0 + &mux_SD0_CLK 0 + &mux_SD0_CMD_RSP 0 + &mux_SD0_DATA_0 0 + &mux_SD0_DATA_1 0 + &mux_SD0_DATA_2 0 + &mux_SD0_DATA_3 0 + >; + }; + pinctrl_SD0_1BIT_NO_WP: SD0_1BIT_NO_WP { + fh,pins = < + &mux_SD0_CD 0 + &mux_SD0_CLK 0 + &mux_SD0_CMD_RSP 0 + &mux_SD0_DATA_0 0 + >; + }; + pinctrl_SD0_NO_WP: SD0_NO_WP { + fh,pins = < + &mux_SD0_CD 0 + &mux_SD0_CLK 0 + &mux_SD0_CMD_RSP 0 + &mux_SD0_DATA_0 0 + &mux_SD0_DATA_1 0 + &mux_SD0_DATA_2 0 + &mux_SD0_DATA_3 0 + >; + }; + pinctrl_SD0_WIFI: SD0_WIFI { + fh,pins = < + &mux_SD0_CLK 0 + &mux_SD0_CMD_RSP 0 + &mux_SD0_DATA_0 0 + &mux_SD0_DATA_1 0 + &mux_SD0_DATA_2 0 + &mux_SD0_DATA_3 0 + >; + }; + pinctrl_SD1: SD1 { + fh,pins = < + &mux_SD1_CD 0 + &mux_SD1_CLK 0 + &mux_SD1_CMD_RSP 0 + &mux_SD1_DATA_0 0 + &mux_SD1_DATA_1 0 + &mux_SD1_DATA_2 0 + &mux_SD1_DATA_3 0 + >; + }; + pinctrl_SD1_1BIT_NO_WP: SD1_1BIT_NO_WP { + fh,pins = < + &mux_SD1_CD 0 + &mux_SD1_CLK 0 + &mux_SD1_CMD_RSP 0 + &mux_SD1_DATA_0 0 + >; + }; + pinctrl_SD1_NO_WP: SD1_NO_WP { + fh,pins = < + &mux_SD1_CD 0 + &mux_SD1_CLK 0 + &mux_SD1_CMD_RSP 0 + &mux_SD1_DATA_0 0 + &mux_SD1_DATA_1 0 + &mux_SD1_DATA_2 0 + &mux_SD1_DATA_3 0 + >; + }; + pinctrl_SD1_WIFI: SD1_WIFI { + fh,pins = < + &mux_SD1_CLK 0 + &mux_SD1_CMD_RSP 0 + &mux_SD1_DATA_0 0 + &mux_SD1_DATA_1 0 + &mux_SD1_DATA_2 0 + &mux_SD1_DATA_3 0 + >; + }; + pinctrl_SENSOR_CLK: SENSOR_CLK { + fh,pins = < + &mux_SENSOR_CLK 0 + >; + }; + pinctrl_SSI0: SSI0 { + fh,pins = < + &mux_GPIO6 0 + &mux_SSI0_CLK 0 + &mux_SSI0_RXD 0 + &mux_SSI0_TXD 0 + >; + }; + pinctrl_SSI0_4BIT: SSI0_4BIT { + fh,pins = < + &mux_GPIO6 0 + &mux_SSI0_CLK 0 + &mux_SSI0_D2 0 + &mux_SSI0_D3 0 + &mux_SSI0_RXD 0 + &mux_SSI0_TXD 0 + >; + }; + pinctrl_SSI1: SSI1 { + fh,pins = < + &mux_GPIO14 0 + &mux_SSI1_CLK 2 + &mux_SSI1_RXD 2 + &mux_SSI1_TXD 2 + >; + }; + pinctrl_SSI2: SSI2 { + fh,pins = < + &mux_SSI2_CLK 1 + &mux_SSI2_CSN_0 1 + &mux_SSI2_RXD 1 + &mux_SSI2_TXD 1 + >; + }; + pinctrl_UART0: UART0 { + fh,pins = < + &mux_UART0_RX 0 + &mux_UART0_TX 0 + >; + }; + pinctrl_UART1: UART1 { + fh,pins = < + &mux_UART1_RX 0 + &mux_UART1_TX 0 + >; + }; + pinctrl_UART2: UART2 { + fh,pins = < + &mux_UART2_RX 0 + &mux_UART2_TX 0 + >; + }; + pinctrl_USB: USB { + fh,pins = < + &mux_USB_PWREN 0 + >; + }; + pinctrl_GPIO0: GPIO0 { + fh,pins = < + &mux_GPIO0 0 + >; + }; + pinctrl_GPIO1: GPIO1 { + fh,pins = < + &mux_GPIO1 0 + >; + }; + pinctrl_GPIO2: GPIO2 { + fh,pins = < + &mux_GPIO2 0 + >; + }; + pinctrl_GPIO3: GPIO3 { + fh,pins = < + &mux_GPIO3 0 + >; + }; + pinctrl_GPIO4: GPIO4 { + fh,pins = < + &mux_GPIO4 0 + >; + }; + pinctrl_GPIO5: GPIO5 { + fh,pins = < + &mux_GPIO5 0 + >; + }; + pinctrl_GPIO6: GPIO6 { + fh,pins = < + &mux_GPIO6 0 + >; + }; + pinctrl_GPIO7: GPIO7 { + fh,pins = < + &mux_GPIO7 0 + >; + }; + pinctrl_GPIO8: GPIO8 { + fh,pins = < + &mux_GPIO8 0 + >; + }; + pinctrl_GPIO9: GPIO9 { + fh,pins = < + &mux_GPIO9 0 + >; + }; + pinctrl_GPIO10: GPIO10 { + fh,pins = < + &mux_GPIO10 0 + >; + }; + pinctrl_GPIO11: GPIO11 { + fh,pins = < + &mux_GPIO11 0 + >; + }; + pinctrl_GPIO12: GPIO12 { + fh,pins = < + &mux_GPIO12 0 + >; + }; + pinctrl_GPIO13: GPIO13 { + fh,pins = < + &mux_GPIO13 0 + >; + }; + pinctrl_GPIO14: GPIO14 { + fh,pins = < + &mux_GPIO14 0 + >; + }; + pinctrl_GPIO15: GPIO15 { + fh,pins = < + &mux_GPIO15 0 + >; + }; + pinctrl_GPIO16: GPIO16 { + fh,pins = < + &mux_GPIO16 0 + >; + }; + pinctrl_GPIO17: GPIO17 { + fh,pins = < + &mux_GPIO17 0 + >; + }; + pinctrl_GPIO18: GPIO18 { + fh,pins = < + &mux_GPIO18 0 + >; + }; + pinctrl_GPIO19: GPIO19 { + fh,pins = < + &mux_GPIO19 0 + >; + }; + pinctrl_GPIO20: GPIO20 { + fh,pins = < + &mux_GPIO20 0 + >; + }; + pinctrl_GPIO21: GPIO21 { + fh,pins = < + &mux_GPIO21 0 + >; + }; + pinctrl_GPIO22: GPIO22 { + fh,pins = < + &mux_GPIO22 0 + >; + }; + pinctrl_GPIO23: GPIO23 { + fh,pins = < + &mux_GPIO23 0 + >; + }; + pinctrl_GPIO24: GPIO24 { + fh,pins = < + &mux_GPIO24 0 + >; + }; + pinctrl_GPIO25: GPIO25 { + fh,pins = < + &mux_GPIO25 0 + >; + }; + pinctrl_GPIO26: GPIO26 { + fh,pins = < + &mux_GPIO26 0 + >; + }; + pinctrl_GPIO27: GPIO27 { + fh,pins = < + &mux_GPIO27 0 + >; + }; + pinctrl_GPIO28: GPIO28 { + fh,pins = < + &mux_GPIO28 0 + >; + }; + pinctrl_GPIO29: GPIO29 { + fh,pins = < + &mux_GPIO29 0 + >; + }; + pinctrl_GPIO30: GPIO30 { + fh,pins = < + &mux_GPIO30 0 + >; + }; + pinctrl_GPIO31: GPIO31 { + fh,pins = < + &mux_GPIO31 0 + >; + }; + pinctrl_GPIO32: GPIO32 { + fh,pins = < + &mux_GPIO32 0 + >; + }; + pinctrl_GPIO33: GPIO33 { + fh,pins = < + &mux_GPIO33 0 + >; + }; + pinctrl_GPIO34: GPIO34 { + fh,pins = < + &mux_GPIO34 0 + >; + }; + pinctrl_GPIO35: GPIO35 { + fh,pins = < + &mux_GPIO35 0 + >; + }; + pinctrl_GPIO36: GPIO36 { + fh,pins = < + &mux_GPIO36 0 + >; + }; + pinctrl_GPIO37: GPIO37 { + fh,pins = < + &mux_GPIO37 0 + >; + }; + pinctrl_GPIO38: GPIO38 { + fh,pins = < + &mux_GPIO38 0 + >; + }; + pinctrl_GPIO39: GPIO39 { + fh,pins = < + &mux_GPIO39 0 + >; + }; + pinctrl_GPIO40: GPIO40 { + fh,pins = < + &mux_GPIO40 0 + >; + }; + pinctrl_GPIO41: GPIO41 { + fh,pins = < + &mux_GPIO41 0 + >; + }; + pinctrl_GPIO42: GPIO42 { + fh,pins = < + &mux_GPIO42 0 + >; + }; + pinctrl_GPIO43: GPIO43 { + fh,pins = < + &mux_GPIO43 0 + >; + }; + pinctrl_GPIO44: GPIO44 { + fh,pins = < + &mux_GPIO44 0 + >; + }; + pinctrl_GPIO45: GPIO45 { + fh,pins = < + &mux_GPIO45 0 + >; + }; + pinctrl_GPIO46: GPIO46 { + fh,pins = < + &mux_GPIO46 0 + >; + }; + pinctrl_GPIO47: GPIO47 { + fh,pins = < + &mux_GPIO47 0 + >; + }; + pinctrl_GPIO48: GPIO48 { + fh,pins = < + &mux_GPIO48 0 + >; + }; + pinctrl_GPIO49: GPIO49 { + fh,pins = < + &mux_GPIO49 0 + >; + }; + pinctrl_GPIO50: GPIO50 { + fh,pins = < + &mux_GPIO50 0 + >; + }; + pinctrl_GPIO51: GPIO51 { + fh,pins = < + &mux_GPIO51 0 + >; + }; + pinctrl_GPIO52: GPIO52 { + fh,pins = < + &mux_GPIO52 0 + >; + }; + pinctrl_GPIO53: GPIO53 { + fh,pins = < + &mux_GPIO53 0 + >; + }; + pinctrl_GPIO54: GPIO54 { + fh,pins = < + &mux_GPIO54 0 + >; + }; + pinctrl_GPIO55: GPIO55 { + fh,pins = < + &mux_GPIO55 0 + >; + }; + pinctrl_GPIO56: GPIO56 { + fh,pins = < + &mux_GPIO56 0 + >; + }; + pinctrl_GPIO57: GPIO57 { + fh,pins = < + &mux_GPIO57 0 + >; + }; + pinctrl_GPIO58: GPIO58 { + fh,pins = < + &mux_GPIO58 0 + >; + }; + pinctrl_GPIO59: GPIO59 { + fh,pins = < + &mux_GPIO59 0 + >; + }; + pinctrl_GPIO60: GPIO60 { + fh,pins = < + &mux_GPIO60 0 + >; + }; + pinctrl_GPIO61: GPIO61 { + fh,pins = < + &mux_GPIO61 0 + >; + }; + pinctrl_GPIO62: GPIO62 { + fh,pins = < + &mux_GPIO62 0 + >; + }; + pinctrl_GPIO63: GPIO63 { + fh,pins = < + &mux_GPIO63 0 + >; + }; + pinctrl_SD1_EMMC: SD1_EMMC { + fh,pins = < + &mux_SD1_CD 3 + &mux_SD1_CLK 3 + &mux_SD1_CMD_RSP 3 + &mux_SD1_DATA_0 3 + &mux_SD1_DATA_1 3 + &mux_SD1_DATA_2 3 + &mux_SD1_DATA_3 3 + >; + }; + }; + pinmux: pinmux { + compatible = "fh,fh-pinmux"; + #list-cells = <1>; + mux_AC_I2S_CLK: AC_I2S_CLK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad39 + >; + }; + mux_AC_I2S_DI: AC_I2S_DI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad38 + >; + }; + mux_AC_I2S_DO: AC_I2S_DO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad37 + >; + }; + mux_AC_I2S_WS: AC_I2S_WS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad40 + >; + }; + mux_AC_MCLK: AC_MCLK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad41 + >; + }; + + mux_ARC_JTAG_TCK: ARC_JTAG_TCK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad55 + >; + }; + mux_ARC_JTAG_TDI: ARC_JTAG_TDI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad54 + >; + }; + mux_ARC_JTAG_TDO: ARC_JTAG_TDO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad53 + >; + }; + mux_ARC_JTAG_TMS: ARC_JTAG_TMS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad56 + >; + }; + mux_ARC_JTAG_TRSTN: ARC_JTAG_TRSTN { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad52 + >; + }; + + mux_ARM_JTAG_TCK: ARM_JTAG_TCK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad40 + >; + }; + mux_ARM_JTAG_TDI: ARM_JTAG_TDI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad39 + >; + }; + mux_ARM_JTAG_TDO: ARM_JTAG_TDO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad38 + >; + }; + mux_ARM_JTAG_TMS: ARM_JTAG_TMS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad41 + >; + }; + mux_ARM_JTAG_TRSTN: ARM_JTAG_TRSTN { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad37 + >; + }; + + mux_DW_I2S_CLK: DW_I2S_CLK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad39 + >; + }; + mux_DW_I2S_DI: DW_I2S_DI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad38 + >; + }; + mux_DW_I2S_DO: DW_I2S_DO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad37 + >; + }; + mux_DW_I2S_WS: DW_I2S_WS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad40 + >; + }; + + mux_ETH_LINK_ACT: ETH_LINK_ACT { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad1 + &pad63 + >; + }; + mux_ETH_LINK_SPD: ETH_LINK_SPD { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad2 + &pad64 + >; + }; + mux_ETH_LINK_STA: ETH_LINK_STA { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad2 + &pad64 + >; + }; + + mux_I2C0_SCL: I2C0_SCL { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad5 + >; + }; + mux_I2C0_SDA: I2C0_SDA { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad6 + >; + }; + + mux_I2C1_SCL: I2C1_SCL { + #list-cells = <1>; + select = <2>; + fh,pads = < + &pad11 + &pad30 + &pad46 + >; + }; + mux_I2C1_SDA: I2C1_SDA { + #list-cells = <1>; + select = <2>; + fh,pads = < + &pad12 + &pad31 + &pad47 + >; + }; + + mux_I2C2_SCL: I2C2_SCL { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad16 + &pad57 + >; + }; + mux_I2C2_SDA: I2C2_SDA { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad17 + &pad58 + >; + }; + + mux_MAC_MDC: MAC_MDC { + #list-cells = <1>; + select = <1>; + ds = <0>; + fh,pads = < + &pad28 + &pad63 + >; + }; + mux_MAC_MDIO: MAC_MDIO { + #list-cells = <1>; + select = <1>; + ds = <0>; + fh,pads = < + &pad29 + &pad64 + >; + }; + mux_MAC_REF_CLK: MAC_REF_CLK { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad21 + >; + }; + mux_MAC_RMII_CLK: MAC_RMII_CLK { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad20 + >; + }; + mux_MAC_RXDV: MAC_RXDV { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad27 + >; + }; + mux_MAC_RXD_0: MAC_RXD_0 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad25 + >; + }; + mux_MAC_RXD_1: MAC_RXD_1 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad26 + >; + }; + mux_MAC_TXD_0: MAC_TXD_0 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad22 + >; + }; + mux_MAC_TXD_1: MAC_TXD_1 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad23 + >; + }; + mux_MAC_TXEN: MAC_TXEN { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad24 + >; + }; + + mux_PAE_JTAG_TCK: PAE_JTAG_TCK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad55 + >; + }; + mux_PAE_JTAG_TDI: PAE_JTAG_TDI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad54 + >; + }; + mux_PAE_JTAG_TDO: PAE_JTAG_TDO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad53 + >; + }; + mux_PAE_JTAG_TMS: PAE_JTAG_TMS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad56 + >; + }; + mux_PAE_JTAG_TRSTN: PAE_JTAG_TRSTN { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad52 + >; + }; + + mux_PWM0: PWM0 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad16 + >; + }; + mux_PWM1: PWM1 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad17 + >; + }; + mux_PWM10: PWM10 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad63 + >; + }; + mux_PWM11: PWM11 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad64 + >; + }; + mux_PWM2: PWM2 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad11 + &pad18 + &pad20 + >; + }; + mux_PWM3: PWM3 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad12 + &pad19 + &pad22 + >; + }; + mux_PWM4: PWM4 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad13 + &pad23 + >; + }; + mux_PWM5: PWM5 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad14 + &pad24 + >; + }; + mux_PWM6: PWM6 { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad25 + &pad37 + >; + }; + mux_PWM7: PWM7 { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad26 + &pad38 + >; + }; + mux_PWM8: PWM8 { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad27 + &pad39 + >; + }; + mux_PWM9: PWM9 { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad28 + &pad40 + >; + }; + + mux_RTC_CLK: RTC_CLK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad64 + >; + }; + + mux_SADC_XAIN0: SADC_XAIN0 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad59 + >; + }; + mux_SADC_XAIN1: SADC_XAIN1 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad60 + >; + }; + mux_SADC_XAIN2: SADC_XAIN2 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad61 + >; + }; + mux_SADC_XAIN3: SADC_XAIN3 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad62 + >; + }; + + mux_SD0_CD: SD0_CD { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad52 + >; + }; + mux_SD0_CLK: SD0_CLK { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad53 + >; + }; + mux_SD0_CMD_RSP: SD0_CMD_RSP { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad54 + >; + }; + mux_SD0_DATA_0: SD0_DATA_0 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad55 + >; + }; + mux_SD0_DATA_1: SD0_DATA_1 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad56 + >; + }; + mux_SD0_DATA_2: SD0_DATA_2 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad57 + >; + }; + mux_SD0_DATA_3: SD0_DATA_3 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad58 + >; + }; + + mux_SD1_CD: SD1_CD { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad10 + &pad22 + &pad31 + &pad41 + &pad63 + >; + }; + mux_SD1_CLK: SD1_CLK { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad9 + &pad20 + &pad30 + &pad42 + >; + }; + mux_SD1_CMD_RSP: SD1_CMD_RSP { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad11 + &pad23 + &pad32 + &pad43 + >; + }; + mux_SD1_DATA_0: SD1_DATA_0 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad12 + &pad24 + &pad33 + &pad44 + >; + }; + mux_SD1_DATA_1: SD1_DATA_1 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad13 + &pad25 + &pad34 + &pad45 + >; + }; + mux_SD1_DATA_2: SD1_DATA_2 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad14 + &pad26 + &pad35 + &pad46 + >; + }; + mux_SD1_DATA_3: SD1_DATA_3 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad15 + &pad27 + &pad36 + &pad47 + >; + }; + + mux_SENSOR_CLK: SENSOR_CLK { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad7 + >; + }; + + mux_SSI0_CLK: SSI0_CLK { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad42 + >; + }; + mux_SSI0_D2: SSI0_D2 { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad46 + >; + }; + mux_SSI0_D3: SSI0_D3 { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad47 + >; + }; + mux_SSI0_RXD: SSI0_RXD { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad45 + >; + }; + mux_SSI0_TXD: SSI0_TXD { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad44 + >; + }; + + mux_SSI1_CLK: SSI1_CLK { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad11 + &pad37 + &pad48 + &pad53 + >; + }; + mux_SSI1_RXD: SSI1_RXD { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad14 + &pad40 + &pad51 + &pad55 + >; + }; + mux_SSI1_TXD: SSI1_TXD { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad13 + &pad39 + &pad50 + &pad54 + >; + }; + + mux_SSI2_CLK: SSI2_CLK { + #list-cells = <1>; + select = <1>; + ds = <2>; + fh,pads = < + &pad37 + &pad48 + >; + }; + mux_SSI2_CSN_0: SSI2_CSN_0 { + #list-cells = <1>; + select = <1>; + ds = <2>; + fh,pads = < + &pad38 + &pad49 + >; + }; + mux_SSI2_RXD: SSI2_RXD { + #list-cells = <1>; + select = <1>; + ds = <2>; + fh,pads = < + &pad40 + &pad51 + >; + }; + mux_SSI2_TXD: SSI2_TXD { + #list-cells = <1>; + select = <1>; + ds = <2>; + fh,pads = < + &pad39 + &pad50 + >; + }; + + mux_UART0_RX: UART0_RX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad4 + >; + }; + mux_UART0_TX: UART0_TX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad3 + >; + }; + + mux_UART1_RX: UART1_RX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad10 + &pad33 + &pad47 + >; + }; + mux_UART1_TX: UART1_TX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad9 + &pad32 + &pad46 + >; + }; + + mux_UART2_RX: UART2_RX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad14 + &pad17 + &pad35 + &pad58 + >; + }; + mux_UART2_TX: UART2_TX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad13 + &pad16 + &pad34 + &pad57 + >; + }; + + mux_USB_PWREN: USB_PWREN { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad15 + &pad41 + >; + }; + + mux_GPIO0: GPIO0 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad37 + >; + }; + mux_GPIO1: GPIO1 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad38 + >; + }; + mux_GPIO2: GPIO2 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad39 + >; + }; + mux_GPIO3: GPIO3 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad40 + >; + }; + mux_GPIO4: GPIO4 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad41 + >; + }; + mux_GPIO5: GPIO5 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad42 + >; + }; + mux_GPIO6: GPIO6 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad43 + >; + }; + mux_GPIO7: GPIO7 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad44 + >; + }; + mux_GPIO8: GPIO8 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad45 + >; + }; + mux_GPIO9: GPIO9 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad46 + >; + }; + mux_GPIO10: GPIO10 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad47 + >; + }; + mux_GPIO11: GPIO11 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad48 + >; + }; + mux_GPIO12: GPIO12 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad7 + >; + }; + mux_GPIO13: GPIO13 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad8 + >; + }; + mux_GPIO14: GPIO14 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad49 + >; + }; + mux_GPIO15: GPIO15 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad50 + >; + }; + mux_GPIO16: GPIO16 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad51 + >; + }; + mux_GPIO17: GPIO17 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad52 + >; + }; + mux_GPIO18: GPIO18 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad53 + >; + }; + mux_GPIO19: GPIO19 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad54 + >; + }; + mux_GPIO20: GPIO20 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad55 + >; + }; + mux_GPIO21: GPIO21 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad56 + >; + }; + mux_GPIO22: GPIO22 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad57 + >; + }; + mux_GPIO23: GPIO23 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad58 + >; + }; + mux_GPIO24: GPIO24 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad61 + >; + }; + mux_GPIO25: GPIO25 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad62 + >; + }; + mux_GPIO26: GPIO26 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad59 + >; + }; + mux_GPIO27: GPIO27 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad60 + >; + }; + mux_GPIO28: GPIO28 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad63 + >; + }; + mux_GPIO29: GPIO29 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad64 + >; + }; + mux_GPIO30: GPIO30 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad0 + >; + }; + mux_GPIO31: GPIO31 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad1 + >; + }; + mux_GPIO32: GPIO32 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad2 + >; + }; + mux_GPIO33: GPIO33 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad3 + >; + }; + mux_GPIO34: GPIO34 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad4 + >; + }; + mux_GPIO35: GPIO35 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad5 + >; + }; + mux_GPIO36: GPIO36 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad6 + >; + }; + mux_GPIO37: GPIO37 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad11 + >; + }; + mux_GPIO38: GPIO38 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad12 + >; + }; + mux_GPIO39: GPIO39 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad9 + >; + }; + mux_GPIO40: GPIO40 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad10 + >; + }; + mux_GPIO41: GPIO41 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad13 + >; + }; + mux_GPIO42: GPIO42 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad14 + >; + }; + mux_GPIO43: GPIO43 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad16 + >; + }; + mux_GPIO44: GPIO44 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad17 + >; + }; + mux_GPIO45: GPIO45 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad18 + >; + }; + mux_GPIO46: GPIO46 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad19 + >; + }; + mux_GPIO47: GPIO47 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad15 + >; + }; + mux_GPIO48: GPIO48 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad20 + >; + }; + mux_GPIO49: GPIO49 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad22 + >; + }; + mux_GPIO50: GPIO50 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad23 + >; + }; + mux_GPIO51: GPIO51 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad24 + >; + }; + mux_GPIO52: GPIO52 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad25 + >; + }; + mux_GPIO53: GPIO53 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad26 + >; + }; + mux_GPIO54: GPIO54 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad27 + >; + }; + mux_GPIO55: GPIO55 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad28 + >; + }; + mux_GPIO56: GPIO56 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad29 + >; + }; + mux_GPIO57: GPIO57 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad30 + >; + }; + mux_GPIO58: GPIO58 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad31 + >; + }; + mux_GPIO59: GPIO59 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad32 + >; + }; + mux_GPIO60: GPIO60 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad33 + >; + }; + mux_GPIO61: GPIO61 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad34 + >; + }; + mux_GPIO62: GPIO62 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad35 + >; + }; + mux_GPIO63: GPIO63 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad36 + >; + }; + }; + pinpad: pinpad { + compatible = "fh,fh-pinpad"; + pad0: PAD_BOOT_MODE_CFG { + index = <0>; + funcs = "GPIO30"; + pupd = <1>; + ds = <0>; + }; + pad1: PAD_BOOT_SEL1_CFG { + index = <1>; + funcs = "GPIO31", "ETH_LINK_ACT"; + pupd = <1>; + ds = <0>; + }; + pad2: PAD_BOOT_SEL0_CFG { + index = <2>; + funcs = "GPIO32", "ETH_LINK_STA", "ETH_LINK_SPD"; + pupd = <1>; + ds = <0>; + }; + pad3: PAD_UART0_TX_CFG { + index = <3>; + funcs = "UART0_TX", "GPIO33"; + pupd = <0>; + ds = <0>; + }; + pad4: PAD_UART0_RX_CFG { + index = <4>; + funcs = "UART0_RX", "GPIO34"; + pupd = <0>; + ds = <0>; + }; + pad5: PAD_I2C0_SCL_CFG { + index = <5>; + funcs = "I2C0_SCL", "GPIO35"; + pupd = <1>; + ds = <0>; + }; + pad6: PAD_I2C0_SDA_CFG { + index = <6>; + funcs = "I2C0_SDA", "GPIO36"; + pupd = <1>; + ds = <0>; + }; + pad7: PAD_SENSOR_CLK_CFG { + index = <7>; + funcs = "SENSOR_CLK", "GPIO12"; + pupd = <0>; + ds = <0>; + }; + pad8: PAD_SENSOR_RSTN_CFG { + index = <8>; + funcs = "GPIO13"; + pupd = <0>; + ds = <0>; + }; + pad9: PAD_UART1_TX_CFG { + index = <9>; + funcs = "UART1_TX", "GPIO39", "", "SD1_CLK", "", "", + "TEST_O_INT_RMII_CLK"; + pupd = <0>; + ds = <0>; + }; + pad10: PAD_UART1_RX_CFG { + index = <10>; + funcs = "UART1_RX", "GPIO40", "", "SD1_CD", "", "", + "TEST_INT_RMII_TXD_0"; + pupd = <0>; + ds = <0>; + }; + pad11: PAD_I2C1_SCL_CFG { + index = <11>; + funcs = "I2C1_SCL", "GPIO37", "PWM2", "SD1_CMD_RSP", "", + "SSI1_CLK", "TEST_INT_RMII_TXD_1"; + pupd = <0>; + ds = <0>; + }; + pad12: PAD_I2C1_SDA_CFG { + index = <12>; + funcs = "I2C1_SDA", "GPIO38", "PWM3", "SD1_DATA_0", "", + "SSI1_CSN_0", "TEST_INT_RMII_TXEN"; + pupd = <0>; + ds = <0>; + }; + pad13: PAD_UART2_TX_CFG { + index = <13>; + funcs = "UART2_TX", "GPIO41", "PWM4", "SD1_DATA_1", "", + "SSI1_TXD", "TEST_O_INT_RMII_RXD_0"; + pupd = <0>; + ds = <0>; + }; + pad14: PAD_UART2_RX_CFG { + index = <14>; + funcs = "UART2_RX", "GPIO42", "PWM5", "SD1_DATA_2", "", + "SSI1_RXD", "TEST_O_INT_RMII_RXD_1"; + pupd = <0>; + ds = <0>; + }; + pad15: PAD_USB_PWREN_CFG { + index = <15>; + funcs = "USB_PWREN", "GPIO47", "", "SD1_DATA_3", "", "", + "TEST_O_INT_RMII_CRSDV"; + pupd = <0>; + ds = <0>; + }; + pad16: PAD_PWM0_CFG { + index = <16>; + funcs = "PWM0", "GPIO43", "I2C2_SCL", "UART2_TX", "", "", + "TEST_O_INT_RMII_TXD_0"; + pupd = <0>; + ds = <0>; + }; + pad17: PAD_PWM1_CFG { + index = <17>; + funcs = "PWM1", "GPIO44", "I2C2_SDA", "UART2_RX", "", "", + "TEST_O_INT_RMII_TXD_1"; + pupd = <0>; + ds = <0>; + }; + pad18: PAD_PWM2_CFG { + index = <18>; + funcs = "PWM2", "GPIO45"; + pupd = <0>; + ds = <0>; + }; + pad19: PAD_PWM3_CFG { + index = <19>; + funcs = "PWM3", "GPIO46"; + pupd = <0>; + ds = <0>; + }; + pad20: PAD_MAC_RMII_CLK_CFG { + index = <20>; + funcs = "MAC_RMII_CLK", "GPIO48", "SD1_CLK", "PWM2"; + pupd = <0>; + ds = <0>; + }; + pad21: PAD_MAC_REF_CLK_CFG { + index = <21>; + funcs = "MAC_REF_CLK"; + pupd = <0>; + ds = <2>; + }; + pad22: PAD_MAC_TXD0_CFG { + index = <22>; + funcs = "MAC_TXD_0", "GPIO49", "SD1_CD", "PWM3"; + pupd = <0>; + ds = <0>; + }; + pad23: PAD_MAC_TXD1_CFG { + index = <23>; + funcs = "MAC_TXD_1", "GPIO50", "SD1_CMD_RSP", "PWM4"; + pupd = <0>; + ds = <0>; + }; + pad24: PAD_MAC_TXEN_CFG { + index = <24>; + funcs = "MAC_TXEN", "GPIO51", "SD1_DATA_0", "PWM5"; + pupd = <0>; + ds = <0>; + }; + pad25: PAD_MAC_RXD0_CFG { + index = <25>; + funcs = "MAC_RXD_0", "GPIO52", "SD1_DATA_1", "PWM6"; + pupd = <0>; + ds = <0>; + }; + pad26: PAD_MAC_RXD1_CFG { + index = <26>; + funcs = "MAC_RXD_1", "GPIO53", "SD1_DATA_2", "PWM7"; + pupd = <0>; + ds = <0>; + }; + pad27: PAD_MAC_RXDV_CFG { + index = <27>; + funcs = "MAC_RXDV", "GPIO54", "SD1_DATA_3", "PWM8"; + pupd = <0>; + ds = <0>; + }; + pad28: PAD_MAC_MDC_CFG { + index = <28>; + funcs = "MAC_MDC", "GPIO55", "", "PWM9"; + pupd = <0>; + ds = <0>; + }; + pad29: PAD_MAC_MDIO_CFG { + index = <29>; + funcs = "MAC_MDIO", "GPIO56"; + pupd = <0>; + ds = <0>; + }; + pad30: PAD_SD1_CLK_CFG { + index = <30>; + funcs = "SD1_CLK", "GPIO57", "I2C1_SCL"; + pupd = <0>; + ds = <0>; + }; + pad31: PAD_SD1_CD_CFG { + index = <31>; + funcs = "SD1_CD", "GPIO58", "I2C1_SDA"; + pupd = <0>; + ds = <0>; + }; + pad32: PAD_SD1_CMD_RSP_CFG { + index = <32>; + funcs = "SD1_CMD_RSP", "GPIO59", "UART1_TX"; + pupd = <0>; + ds = <0>; + }; + pad33: PAD_SD1_DATA_0_CFG { + index = <33>; + funcs = "SD1_DATA_0", "GPIO60", "UART1_RX"; + pupd = <0>; + ds = <0>; + }; + pad34: PAD_SD1_DATA_1_CFG { + index = <34>; + funcs = "SD1_DATA_1", "GPIO61", "UART2_TX"; + pupd = <0>; + ds = <0>; + }; + pad35: PAD_SD1_DATA_2_CFG { + index = <35>; + funcs = "SD1_DATA_2", "GPIO62", "UART2_RX"; + pupd = <0>; + ds = <0>; + }; + pad36: PAD_SD1_DATA_3_CFG { + index = <36>; + funcs = "SD1_DATA_3", "GPIO63"; + pupd = <0>; + ds = <0>; + }; + pad37: PAD_GPIO_0_CFG { + index = <37>; + funcs = "ARM_JTAG_TRSTN", "GPIO0", "AC_I2S_DO", "DW_I2S_DO", + "SSI1_CLK", "SSI2_CLK", "ACIP_ADDAT", "PWM6", + "TEST_O_INT_SMI_MDC"; + pupd = <0>; + ds = <0>; + }; + pad38: PAD_GPIO_1_CFG { + index = <38>; + funcs = "ARM_JTAG_TDO", "GPIO1", "AC_I2S_DI", "DW_I2S_DI", + "SSI1_CSN_0", "SSI2_CSN_0", "ACIP_DADAT", "PWM7", + "TEST_O_INT_SMI_MDIO_I"; + pupd = <0>; + ds = <0>; + }; + pad39: PAD_GPIO_2_CFG { + index = <39>; + funcs = "ARM_JTAG_TDI", "GPIO2", "AC_I2S_CLK", "DW_I2S_CLK", + "SSI1_TXD", "SSI2_TXD", "ACIP_ADBCLK", "PWM8", + "TEST_O_INT_SMI_MDIO_O"; + pupd = <0>; + ds = <0>; + }; + pad40: PAD_GPIO_3_CFG { + index = <40>; + funcs = "ARM_JTAG_TCK", "GPIO3", "AC_I2S_WS", "DW_I2S_WS", + "SSI1_RXD", "SSI2_RXD", "ACIP_ADLRC", "PWM9", + "TEST_I_INT_SMI_MDIO_I"; + pupd = <0>; + ds = <0>; + }; + pad41: PAD_GPIO_4_CFG { + index = <41>; + funcs = "ARM_JTAG_TMS", "GPIO4", "AC_MCLK", "USB_PWREN", + "SD1_CD", "TEST_I_INT_SMI_MDC"; + pupd = <0>; + ds = <0>; + }; + pad42: PAD_SSI0_CLK_CFG { + index = <42>; + funcs = "SSI0_CLK", "GPIO5", "", "", "SD1_CLK"; + pupd = <0>; + ds = <2>; + }; + pad43: PAD_SSI0_CSN_0_CFG { + index = <43>; + funcs = "SSI0_CSN_0", "GPIO6", "", "", "SD1_CMD_RSP"; + pupd = <0>; + ds = <2>; + }; + pad44: PAD_SSI0_TXD_CFG { + index = <44>; + funcs = "SSI0_TXD", "GPIO7", "", "", "SD1_DATA_0"; + pupd = <0>; + ds = <2>; + }; + pad45: PAD_SSI0_RXD_CFG { + index = <45>; + funcs = "SSI0_RXD", "GPIO8", "", "", "SD1_DATA_1"; + pupd = <0>; + ds = <2>; + }; + pad46: PAD_SSI0_D2_CFG { + index = <46>; + funcs = "SSI0_D2", "GPIO9", "UART1_TX", "I2C1_SCL", + "SD1_DATA_2"; + pupd = <0>; + ds = <2>; + }; + pad47: PAD_SSI0_D3_CFG { + index = <47>; + funcs = "SSI0_D3", "GPIO10", "UART1_RX", "I2C1_SDA", + "SD1_DATA_3"; + pupd = <0>; + ds = <2>; + }; + pad48: PAD_SSI1_CLK_CFG { + index = <48>; + funcs = "SSI1_CLK", "GPIO11", "SSI2_CLK"; + pupd = <0>; + ds = <0>; + }; + pad49: PAD_SSI1_CSN_0_CFG { + index = <49>; + funcs = "SSI1_CSN_0", "GPIO14", "SSI2_CSN_0"; + pupd = <0>; + ds = <0>; + }; + pad50: PAD_SSI1_TXD_CFG { + index = <50>; + funcs = "SSI1_TXD", "GPIO15", "SSI2_TXD"; + pupd = <0>; + ds = <0>; + }; + pad51: PAD_SSI1_RXD_CFG { + index = <51>; + funcs = "SSI1_RXD", "GPIO16", "SSI2_RXD"; + pupd = <0>; + ds = <0>; + }; + pad52: PAD_SD0_CD_CFG { + index = <52>; + funcs = "SD0_CD", "GPIO17", "", "ARC_JTAG_TRSTN", + "PAE_JTAG_TRSTN"; + pupd = <0>; + ds = <0>; + }; + pad53: PAD_SD0_CLK_CFG { + index = <53>; + funcs = "SD0_CLK", "GPIO18", "SSI1_CLK", "ARC_JTAG_TDO", + "PAE_JTAG_TDO"; + pupd = <0>; + ds = <2>; + }; + pad54: PAD_SD0_CMD_RSP_CFG { + index = <54>; + funcs = "SD0_CMD_RSP", "GPIO19", "SSI1_TXD", "ARC_JTAG_TDI", + "PAE_JTAG_TDI"; + pupd = <0>; + ds = <2>; + }; + pad55: PAD_SD0_DATA_0_CFG { + index = <55>; + funcs = "SD0_DATA_0", "GPIO20", "SSI1_RXD", "ARC_JTAG_TCK", + "PAE_JTAG_TCK"; + pupd = <0>; + ds = <2>; + }; + pad56: PAD_SD0_DATA_1_CFG { + index = <56>; + funcs = "SD0_DATA_1", "GPIO21", "SSI1_CSN_0", "ARC_JTAG_TMS", + "PAE_JTAG_TMS"; + pupd = <0>; + ds = <2>; + }; + pad57: PAD_SD0_DATA_2_CFG { + index = <57>; + funcs = "SD0_DATA_2", "GPIO22", "", "UART2_TX", "I2C2_SCL", "", + "ACIP_DABCLK"; + pupd = <0>; + ds = <2>; + }; + pad58: PAD_SD0_DATA_3_CFG { + index = <58>; + funcs = "SD0_DATA_3", "GPIO23", "SSI1_CSN_0", "UART2_RX", + "I2C2_SDA", "", "ACIP_DALRC"; + pupd = <0>; + ds = <2>; + }; + pad59: PAD_SADC_XAIN0_CFG { + index = <59>; + funcs = "SADC_XAIN0", "GPIO26"; + pupd = <0>; + ds = <0>; + }; + pad60: PAD_SADC_XAIN1_CFG { + index = <60>; + funcs = "SADC_XAIN1", "GPIO27"; + pupd = <0>; + ds = <0>; + }; + pad61: PAD_SADC_XAIN2_CFG { + index = <61>; + funcs = "SADC_XAIN2", "GPIO24"; + pupd = <0>; + ds = <0>; + }; + pad62: PAD_SADC_XAIN3_CFG { + index = <62>; + funcs = "SADC_XAIN3", "GPIO25"; + pupd = <0>; + ds = <0>; + }; + pad63: PAD_GPIO_28_CFG { + index = <63>; + funcs = "GPIO28", "", "ETH_LINK_ACT", "PWM10", + "USB_DBG_CLK", "SD1_CD", "TEST_O_INT_RMII_TXEN", + "MAC_MDC"; + pupd = <0>; + ds = <0>; + }; + pad64: PAD_GPIO_29_CFG { + index = <64>; + funcs = "GPIO29", "", "ETH_LINK_STA", "PWM11", "RTC_CLK", + "ETH_LINK_SPD", "TEST_O_INT_SMI_MDIO_OE", + "MAC_MDIO"; + pupd = <0>; + ds = <0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/fh8852v210.dts b/arch/arm/boot/dts/fh8852v210.dts new file mode 100644 index 00000000..703df11e --- /dev/null +++ b/arch/arm/boot/dts/fh8852v210.dts @@ -0,0 +1,956 @@ +/* + * Copyright (C) 2017 Fullhan Micorelectonics Co.,Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "skeleton.dtsi" +/include/ "fh8852v210_pinctrl.dtsi" +/ { + + + model = "FULLHAN FH8852V210"; + compatible = "fh,fh8852v210"; + interrupt-parent = <&intc>; + aliases { + i2c0 = &i2cbus0; + i2c1 = &i2cbus1; + i2c2 = &i2cbus2; + spi0 = &spi_bus0; + spi1 = &spi_bus1; + ttyS0 = &serial0; + ttyS1 = &serial1; + ttyS2 = &serial2; + }; + + cpus { + cpu@0 { + device_type = "cpu"; + compatible = "arm,arm1176jzf-s"; + }; + }; + + chosen { + bootargs = "coherent_pool=2M"; + }; + + intc: interrupt-controller@E0200000 { + compatible = "fh,fh-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xE0200000 0x1000>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pmu@f0000000 { + compatible = "fh,fh-pmu"; + reg = <0xf0000000 0x2100>; + SWRST_MAIN_CTRL = <0x40>; + }; + timer0: timer@f0c00000 { + compatible = "fh,fh-timer"; + interrupts = <3>; + clock-frequency = <1000000>; + reg = <0xf0c00000 0x14>; + }; + + timer1: timer@f0c00014 { + compatible = "fh,fh-timer"; + interrupts = <3>; + clock-frequency = <1000000>; + reg = <0xf0c00014 0x14>; + }; + + gpio0: gpio@f0300000 { + compatible = "fh,fh-gpio"; + reg = <0xf0300000 0x1000>; + #gpio_controller; + interrupt-controller; + interrupt-parent = <&intc>; + interrupts = <26>; + id = <0>; + ngpio = <32>; + base = <0>; + }; + + gpio1: gpio@f4000000 { + compatible = "fh,fh-gpio"; + reg = <0xf4000000 0x1000>; + #gpio_controller; + interrupt-controller; + interrupt-parent = <&intc>; + interrupts = <40>; + id = <1>; + ngpio = <32>; + base = <32>; + }; + + fhdma0: dma@e0300000 { + compatible = "fh,fh-axi-dmac"; + reg = <0xe0300000 0x1000>; + interrupts = <23>; + chan_allocation_order = <0>; + chan_priority = <1>; + block_size = <0x800>; + data_width = <2 0 0 0>; + clocks = <&ahb_clk>; + }; + + aes: aes@0xe8200000 { + compatible = "fh,fh-aes"; + reg = <0xe8200000 0x1000>; + interrupts = <16>; + }; + rtc: rtc@f1500000 { + compatible = "fh,fh_rtc"; + reg = <0xf1500000 0x1000>; + interrupts = <33>; + clocks = <&rtc_hclk_gate>; + lut_cof = <71>; + lut_offset = <0xf6>; + tsensor_cp_default_out = <0x9cc>; + }; + sadc: sadc@f1200000 { + compatible = "fh,fh-sadc"; + reg = <0xf1200000 0x1000>; + interrupts = <20>; + ref-vol = <1800>; + active-bit = <0xfff>; + }; + efuse: efuse@0xf1600000 { + compatible = "fh,fh-efuse"; + reg = <0xf1600000 0x1000>; + key_switch = "enable"; + indep_power = "enable"; + }; + fh_perf: fh_perf@0xf0002018 { + compatible = "fh,fh-perf"; + reg = <0xf0000000 0x4000>; + interrupts = < 5 >; + + }; + spi_bus0: spi@f0500000 { + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + compatible = "fh,fh-spi"; + reg = <0xf0500000 0x4000>; + clk_in = <100000000>; + clock_source = <100000000>; + clock_source_num = <1>; + num-cs = <2>; + cs0_gpio = <6>; + cs1_gpio = <55>; + dma_enable = "disable"; + swap_support = "enable"; + rx_hs_no = <4>; + tx_hs_no = <5>; + bus_no = <0>; + multi_wire_size = <2>; + clk_name = "spi0_clk"; + rx_dma_channel = <0>; + tx_dma_channel = <1>; + increase_support = "disable"; + data_field_size = <0x1000>; + data_reg_offset = <0x1000>; + dma_protctl_enable = "disable"; + dma_protctl_data = <6>; + dma_master_sel_enable = "disable"; + dma_master_ctl_sel = <0>; + dma_master_mem_sel = <0>; + spidma_xfer_mode = "rx_only"; + interrupts = <28>; + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fh,m25p80"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + reg = <0x0 0>; //first value means which slave bind to the master. 0 means chip 0. 1 means chip 1 + partition@0 { + reg = <0x0 0x40000>; + label = "bootstrap"; + }; + partition@40000 { + reg = <0x40000 0x10000>; + label = "uboot-env"; + }; + partition@50000 { + reg = <0x50000 0x30000>; + label = "uboot"; + }; + partition@80000 { + reg = <0x80000 0x400000>; + label = "kernel"; + }; + partition@480000 { + reg = <0x480000 0x80000>; + label = "rootfs"; + }; + partition@500000 { + reg = <0x500000 0x300000>; + label = "app"; + }; + + }; + spidev0: spi@0 { + compatible = "rohm,dh2228fv"; + reg = <0x1 0>; + spi-max-frequency = <50000000>; + }; + }; + spi_bus1: spi@f0600000 { + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + compatible = "fh,fh-spi"; + reg = <0xf0600000 0x4000>; + clk_in = <100000000>; + clock_source = <100000000>; + clock_source_num = <1>; + num-cs = <2>; + cs0_gpio = <14>; + cs1_gpio = <57>; + dma_enable = "disable"; + swap_support = "disable"; + rx_hs_no = <2>; + tx_hs_no = <3>; + bus_no = <1>; + clk_name = "spi1_clk"; + rx_dma_channel = <2>; + tx_dma_channel = <3>; + increase_support = "disable"; + data_field_size = <0x1000>; + data_reg_offset = <0x1000>; + dma_protctl_enable = "disable"; + dma_protctl_data = <6>; + dma_master_sel_enable = "disable"; + dma_master_ctl_sel = <0>; + dma_master_mem_sel = <0>; + spidma_xfer_mode = "rx_only"; + interrupts = <21>; + spidev1: spi@1 { + compatible = "rohm,dh2228fv"; + reg = <0x0 0>; + spi-max-frequency = <50000000>; + }; + spidev2: spi@2 { + compatible = "rohm,dh2228fv"; + reg = <0x1 0>; + spi-max-frequency = <50000000>; + }; + }; + fhdwi2s: i2s@f0900000 { + compatible = "fh,fh-dw_i2s"; + reg = <0xf0900000 0x1000>; + interrupts = <25>; + clocks = <&i2s_clk>, <&ac_clk>; + clock-names = "i2s_clk", "acodec_mclk"; + rx_dma_channel = <2>; + tx_dma_channel = <3>; + dma_master = <0>; + dma_rx_hs_num = <10>; + dma_tx_hs_num = <11>; + }; + + fhacw: acw@f0a00000 { + compatible = "fh,fh-acw"; + reg = <0xf0a00000 0x1000>; + interrupts = <19>; + clocks = <&ac_clk>; + clock-names = "ac_clk"; + rx_dma_channel = <4>; + tx_dma_channel = <5>; + dma_master = <0>; + dma_rx_hs_num = <0>; + dma_tx_hs_num = <1>; + }; + + pwm: pwm@f0400000{ + compatible = "fh,fh-pwm"; + reg = <0xf0400000 0x1000>; + interrupts = <36>; + npwm = <14>; + }; + serial0: serial@f0700000 { + compatible = "fh,fh-serial"; + reg = <0xf0700000 0x1000>; + interrupts = <30>; + clock-frequency = <16666667>; + fifo-size = <32>; + }; + serial1: serial@f0800000 { + compatible = "fh,fh-serial"; + reg = <0xf0800000 0x1000>; + interrupts = <31>; + clock-frequency = <16666667>; + fifo-size = <64>; + }; + serial2: serial@f1300000 { + compatible = "fh,fh-serial"; + reg = <0xf1300000 0x1000>; + interrupts = <41>; + clock-frequency = <16666667>; + fifo-size = <64>; + }; + gmac0: gmac@e0600000 { + compatible = "fh,fh-gmac"; + reg = <0xe0600000 0x2000>; + interrupts = <44>; + phyreset-gpio = <29>; + }; + sdc0: sdc0@e2000000 { + compatible = "fh,fh-sdc"; + reg = <0xe2000000 0x4000>; + interrupts = <42>; + id = <0>; + buswidth = <4>; + wp-fixed = <1>; + cd-fixed = <0>; + drv-degree = <8>; + sam-degree = <0>; + scan-mux = <0>; + }; + sdc1: sdc1@e2200000 { + compatible = "fh,fh-sdc"; + reg = <0xe2200000 0x4000>; + interrupts = <43>; + id = <1>; + buswidth = <4>; + wp-fixed = <1>; + cd-fixed = <1>; + drv-degree = <8>; + sam-degree = <0>; + scan-mux = <2>; + }; + wdt: wdt@f0d00000{ + compatible = "fh,fh-wdt"; + reg = <0xf0d00000 0x1000>; + interrupts = <2>; + mode = <1>; + }; + i2cbus0: i2c@f0200000 { + compatible = "fh,fh-i2c"; + reg = <0xf0200000 0x2000>; + interrupts = <11>; + }; + i2cbus1: i2c@f0b00000 { + compatible = "fh,fh-i2c"; + reg = <0xf0b00000 0x2000>; + interrupts = <12>; + }; + i2cbus2: i2c@0xF0100000 { + compatible = "fh,fh-i2c"; + reg = <0xF0100000 0x2000>; + interrupts = <46>; + }; + clocks: src_clk@0xf0000000{ + compatible = "fh,fh-clk"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf0000000 0x80>; + ranges; + + osc_clk: mxtal@24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc_clk"; + }; + + pll_ddr_rclk: pllddrr{ + #clock-cells = <0>; + compatible = "fh pll-ddr-rclk"; + reg = <0xf0000010 0x4>,<0xf0000018 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f000000>; + divcop = <0xf000>; + clocks = <&osc_clk>; + clock-output-names = "pll_ddr_rclk"; + }; + pll_cpu_pclk: pllcpup{ + #clock-cells = <0>; + compatible = "fh pll-cpu-pclk"; + reg = <0xf0000014 0x4>,<0xf000006c 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f0000>; + divcop = <0xf00>; + clocks = <&osc_clk>; + clock-output-names = "pll_cpu_pclk"; + }; + pll_cpu_rclk: pllcpur{ + #clock-cells = <0>; + compatible = "fh pll-cpu-rclk"; + reg = <0xf0000014 0x4>,<0xf000006c 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f000000>; + divcop = <0xf000>; + clocks = <&osc_clk>; + clock-output-names = "pll_cpu_rclk"; + }; + pll_sys_pclk: pllsysp{ + #clock-cells = <0>; + compatible = "fh pll-sys-pclk"; + reg = <0xf0000064 0x4>,<0xf0000068 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f0000>; + divcop = <0xf00>; + clocks = <&osc_clk>; + clock-output-names = "pll_sys_pclk"; + }; + pll_sys_rclk: pllsysr{ + #clock-cells = <0>; + compatible = "fh pll-sys-rclk"; + reg = <0xf0000064 0x4>,<0xf0000068 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f000000>; + divcop = <0xf000>; + clocks = <&osc_clk>; + clock-output-names = "pll_sys_rclk"; + }; + sysp_div12_clk: syspdiv12clk{ + #clock-cells = <0>; + compatible = "fh sysp-div12-clk"; + reg = <0xf0000038 0x4>,<0x0 0x4>,<0x0 0x4>; + div = <0xf000000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "sysp_div12_clk"; + }; + ddr_clk: ddrclk{ + #clock-cells = <0>; + compatible = "fh fh-ddr-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x4000000>; + clocks = <&pll_ddr_rclk>; + clock-output-names = "ddr_clk"; + }; + arm_clk: armclk{ + #clock-cells = <0>; + compatible = "fh fh-arm-clk"; + reg = <0x0 0x4>,<0x0 0x4>,<0xf000000c 0x4>; + mux = <0x1>; + clocks = <&osc_clk>,<&pll_cpu_pclk>; + clock-output-names = "arm_clk"; + }; + arc_clk: arcclk{ + #clock-cells = <0>; + compatible = "fh fh-arc-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0xf000000c 0x4>; + gate = <0x4000000>; + mux = <0x1>; + clocks = <&osc_clk>,<&pll_cpu_rclk>; + clock-output-names = "arc_clk"; + }; + ahb_clk: ahbclk{ + #clock-cells = <0>; + compatible = "fh fh-ahb-clk"; + reg = <0xf0000024 0x4>,<0x0 0x4>,<0xf000000c 0x4>; + div = <0xf0000>; + mux = <0x1>; + clocks = <&osc_clk>,<&pll_sys_pclk>; + clock-output-names = "ahb_clk"; + }; + isp_aclk: ispaclk{ + #clock-cells = <0>; + compatible = "fh fh-ispa-clk"; + reg = <0xf0000024 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xf00>; + gate = <0x1>; + clocks = <&pll_sys_pclk>; + clock-output-names = "isp_aclk"; + }; + ispb_aclk: ispbclk{ + #clock-cells = <0>; + compatible = "fh fh-ispb-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + gate = <0x4>; + clocks = <&isp_aclk>; + clock-output-names = "ispb_aclk"; + }; + vpu_clk: vpuclk{ + #clock-cells = <0>; + compatible = "fh fh-vpu-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x80000000>; + clocks = <&isp_aclk>; + clock-output-names = "vpu_clk"; + }; + pix_clk: pixclk{ + #clock-cells = <0>; + compatible = "fh fh-pix-clk"; + reg = <0xf000002c 0x4>,<0x0 0x4>,<0x0 0x4>; + div = <0xf000000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "pix_clk"; + }; + jpeg_clk: jpegclk{ + #clock-cells = <0>; + compatible = "fh fh-jpeg-clk"; + reg = <0xf000005c 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + div = <0xf00000>; + gate = <0x40000000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "jpeg_clk"; + }; + bgm_clk: bgmclk{ + #clock-cells = <0>; + compatible = "fh fh-bgm-clk"; + reg = <0xf000005c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xf00000>; + gate = <0x40000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "bgm_clk"; + }; + jpeg_adapt_clk: jpegadaptclk{ + #clock-cells = <0>; + compatible = "fh fh-jpeg-adapt-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x2>; + clocks = <&jpeg_clk>; + clock-output-names = "jpeg_adapt_clk"; + }; + spi0_clk: spi0clk{ + #clock-cells = <0>; + compatible = "fh fh-spi0-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff>; + gate = <0x80>; + clocks = <&pll_sys_pclk>; + clock-output-names = "spi0_clk"; + }; + sdc0_clk: sdc0clk{ + #clock-cells = <0>; + compatible = "fh fh-sdc0-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + prediv =<8>; + div = <0xf00>; + gate = <0x200>; + clocks = <&pll_sys_pclk>; + clock-output-names = "sdc0_clk"; + }; + spi2_clk: spi2clk{ + #clock-cells = <0>; + compatible = "fh fh-spi2-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xf000>; + gate = <0x2>; + clocks = <&pll_sys_pclk>; + clock-output-names = "spi2_clk"; + }; + spi1_clk: spi1clk{ + #clock-cells = <0>; + compatible = "fh fh-spi1-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff0000>; + gate = <0x100>; + clocks = <&pll_sys_pclk>; + clock-output-names = "spi1_clk"; + }; + sdc1_clk: sdc1clk{ + #clock-cells = <0>; + compatible = "fh fh-sdc1-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + prediv =<8>; + div = <0xf000000>; + gate = <0x400>; + clocks = <&pll_sys_pclk>; + clock-output-names = "sdc1_clk"; + }; + veu_clk: veuclk{ + #clock-cells = <0>; + compatible = "fh fh-veu-clk"; + reg = <0xf0000024 0x4>,<0xf000001c 0x4>,<0xf000000c 0x4>; + div = <0x7000000>; + gate = <0x10>; + mux = <0x4>; + clocks = <&pll_sys_pclk>,<&pll_sys_rclk>; + clock-output-names = "veu_clk"; + }; + veu_adapt_clk: veuadaptclk{ + #clock-cells = <0>; + compatible = "fh fh-veu-adapt-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + gate = <0x20000000>; + clocks = <&veu_clk>; + clock-output-names = "veu_adapt_clk"; + }; + cis_clk_out: cisclk{ + #clock-cells = <0>; + compatible = "fh fh-cis-clk-out"; + reg = <0xf0000028 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff0000>; + gate = <0x800000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "cis_clk_out"; + }; + eth_clk: ethclk{ + #clock-cells = <0>; + compatible = "fh fh-eth-clk"; + reg = <0xf000003c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xf000000>; + gate = <0x2000000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "eth_clk"; + }; + eth_rmii_clk: ethrmiiclk { + #clock-cells = <0>; + compatible = "fh fh-ethrmii-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + gate = <0x10000000>; + clock-output-names = "eth_rmii_clk"; + }; + i2c0_clk: i2c0clk { + #clock-cells = <0>; + compatible = "fh fh-i2c0-clk"; + reg = <0xf0000034 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f0000>; + gate = <0x1000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "i2c0_clk"; + }; + + i2c1_clk: i2c1clk { + #clock-cells = <0>; + compatible = "fh fh-i2c1-clk"; + reg = <0xf0000034 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f000000>; + gate = <0x8000000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "i2c1_clk"; + }; + i2c2_clk: i2c2clk { + #clock-cells = <0>; + compatible = "fh fh-i2c2-clk"; + reg = <0xf000005c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f00>; + gate = <0x00000008>; + clocks = <&sysp_div12_clk>; + clock-output-names = "i2c2_clk"; + }; + + uart0_clk: uart0clk { + #clock-cells = <0>; + compatible = "fh fh-uart0-clk"; + reg = <0xf0000034 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x1f>; + gate = <0x2000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "uart0_clk"; + }; + + uart1_clk: uart1clk { + #clock-cells = <0>; + compatible = "fh fh-uart1-clk"; + reg = <0xf0000034 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x1f00>; + gate = <0x4000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "uart1_clk"; + }; + uart2_clk: uart2clk { + #clock-cells = <0>; + compatible = "fh fh-uart2-clk"; + reg = <0xf000005c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x7f>; + gate = <0x8000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "uart2_clk"; + }; + pwm_clk: pwmclk { + #clock-cells = <0>; + compatible = "fh fh-pwm-clk"; + reg = <0xf0000038 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff>; + gate = <0x10000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "pwm_clk"; + }; + efuse_clk: efuseclk { + #clock-cells = <0>; + compatible = "fh fh-efuse-clk"; + reg = <0xf0000028 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f000000>; + gate = <0x200000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "efuse_clk"; + }; + pts_clk: ptsclk { + #clock-cells = <0>; + compatible = "fh fh-pts-clk"; + reg = <0xf000002c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x1ff>; + gate = <0x80000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "pts_clk"; + }; + tmr0_clk: tmr0clk { + #clock-cells = <0>; + compatible = "fh fh-tmr0-clk"; + reg = <0xf0000038 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff0000>; + gate = <0x20000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "tmr0_clk"; + }; + + sadc_clk: sadcclk { + #clock-cells = <0>; + compatible = "fh fh-sadc-clk"; + reg = <0xf000003c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x7f0000>; + gate = <0x4000000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "sadc_clk"; + }; + gpio0_dbclk: gpio0dbclk { + #clock-cells = <0>; + compatible = "fh fh-gpio0-dbclk"; + reg = <0xf0000060 0x4>,<0xf0000060 0x4>,<0x0 0x4>; + div = <0x7fff>; + gate = <0x8000>; + prediv = <100>; + clocks = <&sysp_div12_clk>; + clock-output-names = "gpio0_dbclk"; + }; + gpio1_dbclk: gpio1dbclk { + #clock-cells = <0>; + compatible = "fh fh-gpio1-dbclk"; + reg = <0xf0000060 0x4>,<0xf0000060 0x4>,<0x0 0x4>; + div = <0x7fff0000>; + gate = <0x80000000>; + prediv = <100>; + clocks = <&sysp_div12_clk>; + clock-output-names = "gpio1_dbclk"; + }; + wdt_clk: wdtclk { + #clock-cells = <0>; + compatible = "fh fh-wdt-clk"; + reg = <0xf0000038 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + div = <0xff00>; + gate = <0x8000000>; + clocks = <&ahb_clk>; + clock-output-names = "wdt_clk"; + }; + ac_clk: acclk{ + #clock-cells = <0>; + compatible = "fh fh-ac-clk"; + reg = <0xf000003c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f>; + gate = <0x800>; + clocks = <&osc_clk>; + clock-output-names = "ac_clk"; + }; + i2s_clk: i2sclk{ + #clock-cells = <0>; + compatible = "fh fh-i2s-clk"; + reg = <0xf000003c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f00>; + gate = <0x1000000>; + clocks = <&ac_clk>; + clock-output-names = "i2s_clk"; + }; + mipi_dphy_clk: mipidphyclk { + #clock-cells = <0>; + compatible = "fh fh-mipi-dphy-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + gate = <0x100000>; + clock-output-names = "mipi_dphy_clk"; + }; + mipi_wrap_gate: mipiwrapclk { + #clock-cells = <0>; + compatible = "fh fh-mipi-wrap-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x20000000>; + clock-output-names = "mipi_wrap_gate"; + }; + rtc_hclk_gate: rtchclk { + #clock-cells = <0>; + compatible = "fh fh-rtc-hclk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x10000000>; + clock-output-names = "rtc_hclk_gate"; + }; + emac_hclk_gate: emachclk { + #clock-cells = <0>; + compatible = "fh fh-emac-hclk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x2000000>; + clock-output-names = "emac_hclk_gate"; + }; + usb_clk: usbclk { + #clock-cells = <0>; + compatible = "fh fh-usb-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x1000000>; + clock-output-names = "usb_clk"; + }; + aes_hclk_gate: aeshclk { + #clock-cells = <0>; + compatible = "fh fh-aes-hclk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x80>; + clock-output-names = "aes_hclk_gate"; + }; + ephy_clk_gate: ephyclk { + #clock-cells = <0>; + compatible = "fh fh-ephy-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x1>; + clock-output-names = "ephy_clk_gate"; + }; + sdc0_clk8x_gate: sdc08xclk { + #clock-cells = <0>; + compatible = "fh fh-sdc08x-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x4>; + clock-output-names = "sdc0_clk8x_gate"; + }; + sdc1_clk8x_gate: sdc18xclk { + #clock-cells = <0>; + compatible = "fh fh-sdc18x-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x8>; + clock-output-names = "sdc1_clk8x_gate"; + }; + mipic_pclk_gate: mipicpclk { + #clock-cells = <0>; + compatible = "fh fh-mipic-pclk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x10>; + clock-output-names = "mipic_pclk_gate"; + }; + gpio0_pclk_gate: gpio0pclk { + #clock-cells = <0>; + compatible = "fh fh-gpio0-pclk"; + reg = <0x0 0x4>,<0xf0000060 0x4>,<0x0 0x4>; + gate = <0x4000>; + clock-output-names = "gpio0_pclk_gate"; + }; + gpio1_pclk_gate: gpio1pclk { + #clock-cells = <0>; + compatible = "fh fh-gpio1-pclk"; + reg = <0x0 0x4>,<0xf0000060 0x4>,<0x0 0x4>; + gate = <0x40000000>; + clock-output-names = "gpio1_pclk_gate"; + }; + isp_hclk_gate: isphclk { + #clock-cells = <0>; + compatible = "fh fh-isp-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x1000000>; + clock-output-names = "isp_hclk_gate"; + }; + veu_hclk_gate: veuhclk { + #clock-cells = <0>; + compatible = "fh fh-veu-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x2000000>; + clock-output-names = "veu_hclk_gate"; + }; + bgm_hclk_gate: bgmhclk { + #clock-cells = <0>; + compatible = "fh fh-bgm-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x4000000>; + clock-output-names = "bgm_hclk_gate"; + }; + adapt_hclk_gate: adapthclk { + #clock-cells = <0>; + compatible = "fh fh-adapt-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x8000000>; + clock-output-names = "adapt_hclk_gate"; + }; + jpg_hclk_gate: jpghclk { + #clock-cells = <0>; + compatible = "fh fh-jpg-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x10000000>; + clock-output-names = "jpg_hclk_gate"; + }; + jpg_adapt_gate: jpgadaptclk { + #clock-cells = <0>; + compatible = "fh fh-jpg-adapt-clk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x20000000>; + clock-output-names = "jpg_adapt_gate"; + }; + vpu_hclk_gate: vpuhclk { + #clock-cells = <0>; + compatible = "fh fh-vpu-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x40000000>; + clock-output-names = "vpu_hclk_gate"; + }; + sdc0_clk_sample: sdc0clksample { + #clock-cells = <0>; + compatible = "fh fh-sdc0-clk_sample"; + reg = <0xf0000020 0x4>; + mux = <0xf0000>; + clocks = <&sdc0_clk>; + clock-output-names = "sdc0_clk_sample"; + }; + sdc0_clk_drv: sdc0clkdrv { + #clock-cells = <0>; + compatible = "fh fh-sdc0-clk_drv"; + reg = <0xf0000020 0x4>; + mux = <0xf00000>; + clocks = <&sdc0_clk>; + clock-output-names = "sdc0_clk_drv"; + }; + + sdc1_clk_sample: sdc1clksample { + #clock-cells = <0>; + compatible = "fh fh-sdc1-clk_sample"; + reg = <0xf0000020 0x4>; + mux = <0xf00>; + clocks = <&sdc1_clk>; + clock-output-names = "sdc1_clk_sample"; + }; + + sdc1_clk_drv: sdc1clkdrv { + #clock-cells = <0>; + compatible = "fh fh-sdc1-clk_drv"; + reg = <0xf0000020 0x4>; + mux = <0xf000>; + clocks = <&sdc1_clk>; + clock-output-names = "sdc1_clk_drv"; + }; + }; + }; + + usb_otg@e0700000 { + compatible = "fh_usb"; + reg = <0xe0700000 100000>; + interrupts = <39>; + clocks = <&usb_clk>; + dr_mode = "host"; + vbus_pwren = <47>; + clock-names = "otg"; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + }; + + usb2_phy: usbphy { + compatible = "fh,fh-usb2-phy"; + #phy-cells = <0>; + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/fh8852v210_pinctrl.dtsi b/arch/arm/boot/dts/fh8852v210_pinctrl.dtsi new file mode 100644 index 00000000..cc0129ca --- /dev/null +++ b/arch/arm/boot/dts/fh8852v210_pinctrl.dtsi @@ -0,0 +1,2386 @@ +/* + * Copyright (C) 2020 Fullhan Micorelectonics Co.,Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + #define PUPD_NONE (0) + #define PUPD_UP (1) + #define PUPD_DOWN (2) +*/ + +/ { + pinctrl: pinctrl@f0000080 { + compatible = "fh,fh-pinctrl"; + reg = <0xf0000080 0x104>; + pad-num = <65>; + max-mux = <9>; + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_ETH + &pinctrl_I2C0 + &pinctrl_PWM2 + &pinctrl_PWM3 + &pinctrl_PWM4 + &pinctrl_PWM5 + &pinctrl_PWM6 + &pinctrl_PWM7 + &pinctrl_PWM8 + &pinctrl_PWM9 + &pinctrl_SADC_XAIN0 + &pinctrl_SADC_XAIN1 + &pinctrl_SD0_NO_WP + &pinctrl_SENSOR_CLK + &pinctrl_SSI0_4BIT + &pinctrl_UART0 + &pinctrl_UART1 + &pinctrl_GPIO4 + &pinctrl_GPIO13 + &pinctrl_GPIO30 + &pinctrl_GPIO31 + &pinctrl_GPIO32 + &pinctrl_GPIO43 + &pinctrl_GPIO44 + &pinctrl_GPIO47 + + &pinctrl_GPIO11 + &pinctrl_GPIO14 + &pinctrl_GPIO15 + &pinctrl_GPIO16 + &pinctrl_GPIO24 + &pinctrl_GPIO25 + &pinctrl_GPIO45 + &pinctrl_GPIO46 + &pinctrl_GPIO48 + &pinctrl_GPIO49 + &pinctrl_GPIO50 + &pinctrl_GPIO51 + &pinctrl_GPIO52 + &pinctrl_GPIO53 + &pinctrl_GPIO54 + &pinctrl_GPIO55 + &pinctrl_GPIO56 + &pinctrl_GPIO57 + &pinctrl_GPIO58 + &pinctrl_GPIO59 + &pinctrl_GPIO60 + &pinctrl_GPIO61 + &pinctrl_GPIO62 + &pinctrl_GPIO63 + >; + pinctrl_groups { + pinctrl_ACI2S: ACI2S { + fh,pins = < + &mux_AC_I2S_CLK 0 + &mux_AC_I2S_DI 0 + &mux_AC_I2S_DO 0 + &mux_AC_I2S_WS 0 + &mux_AC_MCLK 0 + >; + }; + pinctrl_AC_MCLK: AC_MCLK { + fh,pins = < + &mux_AC_MCLK 0 + >; + }; + pinctrl_ARCJTAG: ARCJTAG { + fh,pins = < + &mux_ARC_JTAG_TCK 0 + &mux_ARC_JTAG_TDI 0 + &mux_ARC_JTAG_TDO 0 + &mux_ARC_JTAG_TMS 0 + &mux_ARC_JTAG_TRSTN 0 + >; + }; + pinctrl_ARMJTAG: ARMJTAG { + fh,pins = < + &mux_ARM_JTAG_TCK 0 + &mux_ARM_JTAG_TDI 0 + &mux_ARM_JTAG_TDO 0 + &mux_ARM_JTAG_TMS 0 + &mux_ARM_JTAG_TRSTN 0 + >; + }; + pinctrl_DWI2S: DWI2S { + fh,pins = < + &mux_DW_I2S_CLK 0 + &mux_DW_I2S_DI 0 + &mux_DW_I2S_DO 0 + &mux_DW_I2S_WS 0 + >; + }; + pinctrl_ETH: ETH { + fh,pins = < + &mux_ETH_LINK_ACT 1 + &mux_ETH_LINK_STA 1 + >; + }; + pinctrl_I2C0: I2C0 { + fh,pins = < + &mux_I2C0_SCL 0 + &mux_I2C0_SDA 0 + >; + }; + pinctrl_I2C1: I2C1 { + fh,pins = < + &mux_I2C1_SCL 2 + &mux_I2C1_SDA 2 + >; + }; + pinctrl_I2C2: I2C2 { + fh,pins = < + &mux_I2C2_SCL 1 + &mux_I2C2_SDA 1 + >; + }; + pinctrl_PAEJTAG: PAEJTAG { + fh,pins = < + &mux_PAE_JTAG_TCK 0 + &mux_PAE_JTAG_TDI 0 + &mux_PAE_JTAG_TDO 0 + &mux_PAE_JTAG_TMS 0 + &mux_PAE_JTAG_TRSTN 0 + >; + }; + pinctrl_PWM0: PWM0 { + fh,pins = < + &mux_PWM0 0 + >; + }; + pinctrl_PWM1: PWM1 { + fh,pins = < + &mux_PWM1 0 + >; + }; + pinctrl_PWM10: PWM10 { + fh,pins = < + &mux_PWM10 0 + >; + }; + pinctrl_PWM11: PWM11 { + fh,pins = < + &mux_PWM11 0 + >; + }; + pinctrl_PWM2: PWM2 { + fh,pins = < + &mux_PWM2 0 + >; + }; + pinctrl_PWM3: PWM3 { + fh,pins = < + &mux_PWM3 0 + >; + }; + pinctrl_PWM4: PWM4 { + fh,pins = < + &mux_PWM4 0 + >; + }; + pinctrl_PWM5: PWM5 { + fh,pins = < + &mux_PWM5 0 + >; + }; + pinctrl_PWM6: PWM6 { + fh,pins = < + &mux_PWM6 1 + >; + }; + pinctrl_PWM7: PWM7 { + fh,pins = < + &mux_PWM7 1 + >; + }; + pinctrl_PWM8: PWM8 { + fh,pins = < + &mux_PWM8 1 + >; + }; + pinctrl_PWM9: PWM9 { + fh,pins = < + &mux_PWM9 1 + >; + }; + pinctrl_RMII: RMII { + fh,pins = < + &mux_MAC_MDC 1 + &mux_MAC_MDIO 1 + &mux_MAC_REF_CLK 0 + &mux_MAC_RMII_CLK 0 + &mux_MAC_RXDV 0 + &mux_MAC_RXD_0 0 + &mux_MAC_RXD_1 0 + &mux_MAC_TXD_0 0 + &mux_MAC_TXD_1 0 + &mux_MAC_TXEN 0 + >; + }; + pinctrl_RTC: RTC { + fh,pins = < + &mux_RTC_CLK 0 + >; + }; + pinctrl_SADC_XAIN0: SADC_XAIN0 { + fh,pins = < + &mux_SADC_XAIN0 0 + >; + }; + pinctrl_SADC_XAIN1: SADC_XAIN1 { + fh,pins = < + &mux_SADC_XAIN1 0 + >; + }; + pinctrl_SADC_XAIN2: SADC_XAIN2 { + fh,pins = < + &mux_SADC_XAIN2 0 + >; + }; + pinctrl_SADC_XAIN3: SADC_XAIN3 { + fh,pins = < + &mux_SADC_XAIN3 0 + >; + }; + pinctrl_SD0: SD0 { + fh,pins = < + &mux_SD0_CD 0 + &mux_SD0_CLK 0 + &mux_SD0_CMD_RSP 0 + &mux_SD0_DATA_0 0 + &mux_SD0_DATA_1 0 + &mux_SD0_DATA_2 0 + &mux_SD0_DATA_3 0 + >; + }; + pinctrl_SD0_1BIT_NO_WP: SD0_1BIT_NO_WP { + fh,pins = < + &mux_SD0_CD 0 + &mux_SD0_CLK 0 + &mux_SD0_CMD_RSP 0 + &mux_SD0_DATA_0 0 + >; + }; + pinctrl_SD0_NO_WP: SD0_NO_WP { + fh,pins = < + &mux_SD0_CD 0 + &mux_SD0_CLK 0 + &mux_SD0_CMD_RSP 0 + &mux_SD0_DATA_0 0 + &mux_SD0_DATA_1 0 + &mux_SD0_DATA_2 0 + &mux_SD0_DATA_3 0 + >; + }; + pinctrl_SD0_WIFI: SD0_WIFI { + fh,pins = < + &mux_SD0_CLK 0 + &mux_SD0_CMD_RSP 0 + &mux_SD0_DATA_0 0 + &mux_SD0_DATA_1 0 + &mux_SD0_DATA_2 0 + &mux_SD0_DATA_3 0 + >; + }; + pinctrl_SD1: SD1 { + fh,pins = < + &mux_SD1_CD 0 + &mux_SD1_CLK 0 + &mux_SD1_CMD_RSP 0 + &mux_SD1_DATA_0 0 + &mux_SD1_DATA_1 0 + &mux_SD1_DATA_2 0 + &mux_SD1_DATA_3 0 + >; + }; + pinctrl_SD1_1BIT_NO_WP: SD1_1BIT_NO_WP { + fh,pins = < + &mux_SD1_CD 0 + &mux_SD1_CLK 0 + &mux_SD1_CMD_RSP 0 + &mux_SD1_DATA_0 0 + >; + }; + pinctrl_SD1_NO_WP: SD1_NO_WP { + fh,pins = < + &mux_SD1_CD 0 + &mux_SD1_CLK 0 + &mux_SD1_CMD_RSP 0 + &mux_SD1_DATA_0 0 + &mux_SD1_DATA_1 0 + &mux_SD1_DATA_2 0 + &mux_SD1_DATA_3 0 + >; + }; + pinctrl_SD1_WIFI: SD1_WIFI { + fh,pins = < + &mux_SD1_CLK 0 + &mux_SD1_CMD_RSP 0 + &mux_SD1_DATA_0 0 + &mux_SD1_DATA_1 0 + &mux_SD1_DATA_2 0 + &mux_SD1_DATA_3 0 + >; + }; + pinctrl_SENSOR_CLK: SENSOR_CLK { + fh,pins = < + &mux_SENSOR_CLK 0 + >; + }; + pinctrl_SSI0: SSI0 { + fh,pins = < + &mux_GPIO6 0 + &mux_SSI0_CLK 0 + &mux_SSI0_RXD 0 + &mux_SSI0_TXD 0 + >; + }; + pinctrl_SSI0_4BIT: SSI0_4BIT { + fh,pins = < + &mux_GPIO6 0 + &mux_SSI0_CLK 0 + &mux_SSI0_D2 0 + &mux_SSI0_D3 0 + &mux_SSI0_RXD 0 + &mux_SSI0_TXD 0 + >; + }; + pinctrl_SSI1: SSI1 { + fh,pins = < + &mux_GPIO14 0 + &mux_SSI1_CLK 2 + &mux_SSI1_RXD 2 + &mux_SSI1_TXD 2 + >; + }; + pinctrl_SSI2: SSI2 { + fh,pins = < + &mux_SSI2_CLK 1 + &mux_SSI2_CSN_0 1 + &mux_SSI2_RXD 1 + &mux_SSI2_TXD 1 + >; + }; + pinctrl_UART0: UART0 { + fh,pins = < + &mux_UART0_RX 0 + &mux_UART0_TX 0 + >; + }; + pinctrl_UART1: UART1 { + fh,pins = < + &mux_UART1_RX 0 + &mux_UART1_TX 0 + >; + }; + pinctrl_UART2: UART2 { + fh,pins = < + &mux_UART2_RX 0 + &mux_UART2_TX 0 + >; + }; + pinctrl_USB: USB { + fh,pins = < + &mux_USB_PWREN 0 + >; + }; + pinctrl_GPIO0: GPIO0 { + fh,pins = < + &mux_GPIO0 0 + >; + }; + pinctrl_GPIO1: GPIO1 { + fh,pins = < + &mux_GPIO1 0 + >; + }; + pinctrl_GPIO2: GPIO2 { + fh,pins = < + &mux_GPIO2 0 + >; + }; + pinctrl_GPIO3: GPIO3 { + fh,pins = < + &mux_GPIO3 0 + >; + }; + pinctrl_GPIO4: GPIO4 { + fh,pins = < + &mux_GPIO4 0 + >; + }; + pinctrl_GPIO5: GPIO5 { + fh,pins = < + &mux_GPIO5 0 + >; + }; + pinctrl_GPIO6: GPIO6 { + fh,pins = < + &mux_GPIO6 0 + >; + }; + pinctrl_GPIO7: GPIO7 { + fh,pins = < + &mux_GPIO7 0 + >; + }; + pinctrl_GPIO8: GPIO8 { + fh,pins = < + &mux_GPIO8 0 + >; + }; + pinctrl_GPIO9: GPIO9 { + fh,pins = < + &mux_GPIO9 0 + >; + }; + pinctrl_GPIO10: GPIO10 { + fh,pins = < + &mux_GPIO10 0 + >; + }; + pinctrl_GPIO11: GPIO11 { + fh,pins = < + &mux_GPIO11 0 + >; + }; + pinctrl_GPIO12: GPIO12 { + fh,pins = < + &mux_GPIO12 0 + >; + }; + pinctrl_GPIO13: GPIO13 { + fh,pins = < + &mux_GPIO13 0 + >; + }; + pinctrl_GPIO14: GPIO14 { + fh,pins = < + &mux_GPIO14 0 + >; + }; + pinctrl_GPIO15: GPIO15 { + fh,pins = < + &mux_GPIO15 0 + >; + }; + pinctrl_GPIO16: GPIO16 { + fh,pins = < + &mux_GPIO16 0 + >; + }; + pinctrl_GPIO17: GPIO17 { + fh,pins = < + &mux_GPIO17 0 + >; + }; + pinctrl_GPIO18: GPIO18 { + fh,pins = < + &mux_GPIO18 0 + >; + }; + pinctrl_GPIO19: GPIO19 { + fh,pins = < + &mux_GPIO19 0 + >; + }; + pinctrl_GPIO20: GPIO20 { + fh,pins = < + &mux_GPIO20 0 + >; + }; + pinctrl_GPIO21: GPIO21 { + fh,pins = < + &mux_GPIO21 0 + >; + }; + pinctrl_GPIO22: GPIO22 { + fh,pins = < + &mux_GPIO22 0 + >; + }; + pinctrl_GPIO23: GPIO23 { + fh,pins = < + &mux_GPIO23 0 + >; + }; + pinctrl_GPIO24: GPIO24 { + fh,pins = < + &mux_GPIO24 0 + >; + }; + pinctrl_GPIO25: GPIO25 { + fh,pins = < + &mux_GPIO25 0 + >; + }; + pinctrl_GPIO26: GPIO26 { + fh,pins = < + &mux_GPIO26 0 + >; + }; + pinctrl_GPIO27: GPIO27 { + fh,pins = < + &mux_GPIO27 0 + >; + }; + pinctrl_GPIO28: GPIO28 { + fh,pins = < + &mux_GPIO28 0 + >; + }; + pinctrl_GPIO29: GPIO29 { + fh,pins = < + &mux_GPIO29 0 + >; + }; + pinctrl_GPIO30: GPIO30 { + fh,pins = < + &mux_GPIO30 0 + >; + }; + pinctrl_GPIO31: GPIO31 { + fh,pins = < + &mux_GPIO31 0 + >; + }; + pinctrl_GPIO32: GPIO32 { + fh,pins = < + &mux_GPIO32 0 + >; + }; + pinctrl_GPIO33: GPIO33 { + fh,pins = < + &mux_GPIO33 0 + >; + }; + pinctrl_GPIO34: GPIO34 { + fh,pins = < + &mux_GPIO34 0 + >; + }; + pinctrl_GPIO35: GPIO35 { + fh,pins = < + &mux_GPIO35 0 + >; + }; + pinctrl_GPIO36: GPIO36 { + fh,pins = < + &mux_GPIO36 0 + >; + }; + pinctrl_GPIO37: GPIO37 { + fh,pins = < + &mux_GPIO37 0 + >; + }; + pinctrl_GPIO38: GPIO38 { + fh,pins = < + &mux_GPIO38 0 + >; + }; + pinctrl_GPIO39: GPIO39 { + fh,pins = < + &mux_GPIO39 0 + >; + }; + pinctrl_GPIO40: GPIO40 { + fh,pins = < + &mux_GPIO40 0 + >; + }; + pinctrl_GPIO41: GPIO41 { + fh,pins = < + &mux_GPIO41 0 + >; + }; + pinctrl_GPIO42: GPIO42 { + fh,pins = < + &mux_GPIO42 0 + >; + }; + pinctrl_GPIO43: GPIO43 { + fh,pins = < + &mux_GPIO43 0 + >; + }; + pinctrl_GPIO44: GPIO44 { + fh,pins = < + &mux_GPIO44 0 + >; + }; + pinctrl_GPIO45: GPIO45 { + fh,pins = < + &mux_GPIO45 0 + >; + }; + pinctrl_GPIO46: GPIO46 { + fh,pins = < + &mux_GPIO46 0 + >; + }; + pinctrl_GPIO47: GPIO47 { + fh,pins = < + &mux_GPIO47 0 + >; + }; + pinctrl_GPIO48: GPIO48 { + fh,pins = < + &mux_GPIO48 0 + >; + }; + pinctrl_GPIO49: GPIO49 { + fh,pins = < + &mux_GPIO49 0 + >; + }; + pinctrl_GPIO50: GPIO50 { + fh,pins = < + &mux_GPIO50 0 + >; + }; + pinctrl_GPIO51: GPIO51 { + fh,pins = < + &mux_GPIO51 0 + >; + }; + pinctrl_GPIO52: GPIO52 { + fh,pins = < + &mux_GPIO52 0 + >; + }; + pinctrl_GPIO53: GPIO53 { + fh,pins = < + &mux_GPIO53 0 + >; + }; + pinctrl_GPIO54: GPIO54 { + fh,pins = < + &mux_GPIO54 0 + >; + }; + pinctrl_GPIO55: GPIO55 { + fh,pins = < + &mux_GPIO55 0 + >; + }; + pinctrl_GPIO56: GPIO56 { + fh,pins = < + &mux_GPIO56 0 + >; + }; + pinctrl_GPIO57: GPIO57 { + fh,pins = < + &mux_GPIO57 0 + >; + }; + pinctrl_GPIO58: GPIO58 { + fh,pins = < + &mux_GPIO58 0 + >; + }; + pinctrl_GPIO59: GPIO59 { + fh,pins = < + &mux_GPIO59 0 + >; + }; + pinctrl_GPIO60: GPIO60 { + fh,pins = < + &mux_GPIO60 0 + >; + }; + pinctrl_GPIO61: GPIO61 { + fh,pins = < + &mux_GPIO61 0 + >; + }; + pinctrl_GPIO62: GPIO62 { + fh,pins = < + &mux_GPIO62 0 + >; + }; + pinctrl_GPIO63: GPIO63 { + fh,pins = < + &mux_GPIO63 0 + >; + }; + pinctrl_SD1_EMMC: SD1_EMMC { + fh,pins = < + &mux_SD1_CD 3 + &mux_SD1_CLK 3 + &mux_SD1_CMD_RSP 3 + &mux_SD1_DATA_0 3 + &mux_SD1_DATA_1 3 + &mux_SD1_DATA_2 3 + &mux_SD1_DATA_3 3 + >; + }; + }; + pinmux: pinmux { + compatible = "fh,fh-pinmux"; + #list-cells = <1>; + mux_AC_I2S_CLK: AC_I2S_CLK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad39 + >; + }; + mux_AC_I2S_DI: AC_I2S_DI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad38 + >; + }; + mux_AC_I2S_DO: AC_I2S_DO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad37 + >; + }; + mux_AC_I2S_WS: AC_I2S_WS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad40 + >; + }; + mux_AC_MCLK: AC_MCLK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad41 + >; + }; + + mux_ARC_JTAG_TCK: ARC_JTAG_TCK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad55 + >; + }; + mux_ARC_JTAG_TDI: ARC_JTAG_TDI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad54 + >; + }; + mux_ARC_JTAG_TDO: ARC_JTAG_TDO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad53 + >; + }; + mux_ARC_JTAG_TMS: ARC_JTAG_TMS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad56 + >; + }; + mux_ARC_JTAG_TRSTN: ARC_JTAG_TRSTN { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad52 + >; + }; + + mux_ARM_JTAG_TCK: ARM_JTAG_TCK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad40 + >; + }; + mux_ARM_JTAG_TDI: ARM_JTAG_TDI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad39 + >; + }; + mux_ARM_JTAG_TDO: ARM_JTAG_TDO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad38 + >; + }; + mux_ARM_JTAG_TMS: ARM_JTAG_TMS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad41 + >; + }; + mux_ARM_JTAG_TRSTN: ARM_JTAG_TRSTN { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad37 + >; + }; + + mux_DW_I2S_CLK: DW_I2S_CLK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad39 + >; + }; + mux_DW_I2S_DI: DW_I2S_DI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad38 + >; + }; + mux_DW_I2S_DO: DW_I2S_DO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad37 + >; + }; + mux_DW_I2S_WS: DW_I2S_WS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad40 + >; + }; + + mux_ETH_LINK_ACT: ETH_LINK_ACT { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad1 + &pad63 + >; + }; + mux_ETH_LINK_SPD: ETH_LINK_SPD { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad2 + &pad64 + >; + }; + mux_ETH_LINK_STA: ETH_LINK_STA { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad2 + &pad64 + >; + }; + + mux_I2C0_SCL: I2C0_SCL { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad5 + >; + }; + mux_I2C0_SDA: I2C0_SDA { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad6 + >; + }; + + mux_I2C1_SCL: I2C1_SCL { + #list-cells = <1>; + select = <2>; + fh,pads = < + &pad11 + &pad30 + &pad46 + >; + }; + mux_I2C1_SDA: I2C1_SDA { + #list-cells = <1>; + select = <2>; + fh,pads = < + &pad12 + &pad31 + &pad47 + >; + }; + + mux_I2C2_SCL: I2C2_SCL { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad16 + &pad57 + >; + }; + mux_I2C2_SDA: I2C2_SDA { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad17 + &pad58 + >; + }; + + mux_MAC_MDC: MAC_MDC { + #list-cells = <1>; + select = <1>; + ds = <0>; + fh,pads = < + &pad28 + &pad63 + >; + }; + mux_MAC_MDIO: MAC_MDIO { + #list-cells = <1>; + select = <1>; + ds = <0>; + fh,pads = < + &pad29 + &pad64 + >; + }; + mux_MAC_REF_CLK: MAC_REF_CLK { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad21 + >; + }; + mux_MAC_RMII_CLK: MAC_RMII_CLK { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad20 + >; + }; + mux_MAC_RXDV: MAC_RXDV { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad27 + >; + }; + mux_MAC_RXD_0: MAC_RXD_0 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad25 + >; + }; + mux_MAC_RXD_1: MAC_RXD_1 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad26 + >; + }; + mux_MAC_TXD_0: MAC_TXD_0 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad22 + >; + }; + mux_MAC_TXD_1: MAC_TXD_1 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad23 + >; + }; + mux_MAC_TXEN: MAC_TXEN { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad24 + >; + }; + + mux_PAE_JTAG_TCK: PAE_JTAG_TCK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad55 + >; + }; + mux_PAE_JTAG_TDI: PAE_JTAG_TDI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad54 + >; + }; + mux_PAE_JTAG_TDO: PAE_JTAG_TDO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad53 + >; + }; + mux_PAE_JTAG_TMS: PAE_JTAG_TMS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad56 + >; + }; + mux_PAE_JTAG_TRSTN: PAE_JTAG_TRSTN { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad52 + >; + }; + + mux_PWM0: PWM0 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad16 + >; + }; + mux_PWM1: PWM1 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad17 + >; + }; + mux_PWM10: PWM10 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad63 + >; + }; + mux_PWM11: PWM11 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad64 + >; + }; + mux_PWM2: PWM2 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad11 + &pad18 + &pad20 + >; + }; + mux_PWM3: PWM3 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad12 + &pad19 + &pad22 + >; + }; + mux_PWM4: PWM4 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad13 + &pad23 + >; + }; + mux_PWM5: PWM5 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad14 + &pad24 + >; + }; + mux_PWM6: PWM6 { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad25 + &pad37 + >; + }; + mux_PWM7: PWM7 { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad26 + &pad38 + >; + }; + mux_PWM8: PWM8 { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad27 + &pad39 + >; + }; + mux_PWM9: PWM9 { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad28 + &pad40 + >; + }; + + mux_RTC_CLK: RTC_CLK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad64 + >; + }; + + mux_SADC_XAIN0: SADC_XAIN0 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad59 + >; + }; + mux_SADC_XAIN1: SADC_XAIN1 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad60 + >; + }; + mux_SADC_XAIN2: SADC_XAIN2 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad61 + >; + }; + mux_SADC_XAIN3: SADC_XAIN3 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad62 + >; + }; + + mux_SD0_CD: SD0_CD { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad52 + >; + }; + mux_SD0_CLK: SD0_CLK { + #list-cells = <1>; + select = <0>; + ds = <3>; + fh,pads = < + &pad53 + >; + }; + mux_SD0_CMD_RSP: SD0_CMD_RSP { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad54 + >; + }; + mux_SD0_DATA_0: SD0_DATA_0 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad55 + >; + }; + mux_SD0_DATA_1: SD0_DATA_1 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad56 + >; + }; + mux_SD0_DATA_2: SD0_DATA_2 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad57 + >; + }; + mux_SD0_DATA_3: SD0_DATA_3 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad58 + >; + }; + + mux_SD1_CD: SD1_CD { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad10 + &pad22 + &pad31 + &pad41 + &pad63 + >; + }; + mux_SD1_CLK: SD1_CLK { + #list-cells = <1>; + select = <0>; + ds = <3>; + fh,pads = < + &pad9 + &pad20 + &pad30 + &pad42 + >; + }; + mux_SD1_CMD_RSP: SD1_CMD_RSP { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad11 + &pad23 + &pad32 + &pad43 + >; + }; + mux_SD1_DATA_0: SD1_DATA_0 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad12 + &pad24 + &pad33 + &pad44 + >; + }; + mux_SD1_DATA_1: SD1_DATA_1 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad13 + &pad25 + &pad34 + &pad45 + >; + }; + mux_SD1_DATA_2: SD1_DATA_2 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad14 + &pad26 + &pad35 + &pad46 + >; + }; + mux_SD1_DATA_3: SD1_DATA_3 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad15 + &pad27 + &pad36 + &pad47 + >; + }; + + mux_SENSOR_CLK: SENSOR_CLK { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad7 + >; + }; + + mux_SSI0_CLK: SSI0_CLK { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad42 + >; + }; + mux_SSI0_D2: SSI0_D2 { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad46 + >; + }; + mux_SSI0_D3: SSI0_D3 { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad47 + >; + }; + mux_SSI0_RXD: SSI0_RXD { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad45 + >; + }; + mux_SSI0_TXD: SSI0_TXD { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad44 + >; + }; + + mux_SSI1_CLK: SSI1_CLK { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad11 + &pad37 + &pad48 + &pad53 + >; + }; + mux_SSI1_RXD: SSI1_RXD { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad14 + &pad40 + &pad51 + &pad55 + >; + }; + mux_SSI1_TXD: SSI1_TXD { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad13 + &pad39 + &pad50 + &pad54 + >; + }; + + mux_SSI2_CLK: SSI2_CLK { + #list-cells = <1>; + select = <1>; + ds = <2>; + fh,pads = < + &pad37 + &pad48 + >; + }; + mux_SSI2_CSN_0: SSI2_CSN_0 { + #list-cells = <1>; + select = <1>; + ds = <2>; + fh,pads = < + &pad38 + &pad49 + >; + }; + mux_SSI2_RXD: SSI2_RXD { + #list-cells = <1>; + select = <1>; + ds = <2>; + fh,pads = < + &pad40 + &pad51 + >; + }; + mux_SSI2_TXD: SSI2_TXD { + #list-cells = <1>; + select = <1>; + ds = <2>; + fh,pads = < + &pad39 + &pad50 + >; + }; + + mux_UART0_RX: UART0_RX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad4 + >; + }; + mux_UART0_TX: UART0_TX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad3 + >; + }; + + mux_UART1_RX: UART1_RX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad10 + &pad33 + &pad47 + >; + }; + mux_UART1_TX: UART1_TX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad9 + &pad32 + &pad46 + >; + }; + + mux_UART2_RX: UART2_RX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad14 + &pad17 + &pad35 + &pad58 + >; + }; + mux_UART2_TX: UART2_TX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad13 + &pad16 + &pad34 + &pad57 + >; + }; + + mux_USB_PWREN: USB_PWREN { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad15 + &pad41 + >; + }; + + mux_GPIO0: GPIO0 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad37 + >; + }; + mux_GPIO1: GPIO1 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad38 + >; + }; + mux_GPIO2: GPIO2 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad39 + >; + }; + mux_GPIO3: GPIO3 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad40 + >; + }; + mux_GPIO4: GPIO4 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad41 + >; + }; + mux_GPIO5: GPIO5 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad42 + >; + }; + mux_GPIO6: GPIO6 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad43 + >; + }; + mux_GPIO7: GPIO7 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad44 + >; + }; + mux_GPIO8: GPIO8 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad45 + >; + }; + mux_GPIO9: GPIO9 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad46 + >; + }; + mux_GPIO10: GPIO10 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad47 + >; + }; + mux_GPIO11: GPIO11 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad48 + >; + }; + mux_GPIO12: GPIO12 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad7 + >; + }; + mux_GPIO13: GPIO13 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad8 + >; + }; + mux_GPIO14: GPIO14 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad49 + >; + }; + mux_GPIO15: GPIO15 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad50 + >; + }; + mux_GPIO16: GPIO16 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad51 + >; + }; + mux_GPIO17: GPIO17 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad52 + >; + }; + mux_GPIO18: GPIO18 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad53 + >; + }; + mux_GPIO19: GPIO19 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad54 + >; + }; + mux_GPIO20: GPIO20 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad55 + >; + }; + mux_GPIO21: GPIO21 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad56 + >; + }; + mux_GPIO22: GPIO22 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad57 + >; + }; + mux_GPIO23: GPIO23 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad58 + >; + }; + mux_GPIO24: GPIO24 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad61 + >; + }; + mux_GPIO25: GPIO25 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad62 + >; + }; + mux_GPIO26: GPIO26 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad59 + >; + }; + mux_GPIO27: GPIO27 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad60 + >; + }; + mux_GPIO28: GPIO28 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad63 + >; + }; + mux_GPIO29: GPIO29 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad64 + >; + }; + mux_GPIO30: GPIO30 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad0 + >; + }; + mux_GPIO31: GPIO31 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad1 + >; + }; + mux_GPIO32: GPIO32 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad2 + >; + }; + mux_GPIO33: GPIO33 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad3 + >; + }; + mux_GPIO34: GPIO34 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad4 + >; + }; + mux_GPIO35: GPIO35 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad5 + >; + }; + mux_GPIO36: GPIO36 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad6 + >; + }; + mux_GPIO37: GPIO37 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad11 + >; + }; + mux_GPIO38: GPIO38 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad12 + >; + }; + mux_GPIO39: GPIO39 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad9 + >; + }; + mux_GPIO40: GPIO40 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad10 + >; + }; + mux_GPIO41: GPIO41 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad13 + >; + }; + mux_GPIO42: GPIO42 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad14 + >; + }; + mux_GPIO43: GPIO43 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad16 + >; + }; + mux_GPIO44: GPIO44 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad17 + >; + }; + mux_GPIO45: GPIO45 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad18 + >; + }; + mux_GPIO46: GPIO46 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad19 + >; + }; + mux_GPIO47: GPIO47 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad15 + >; + }; + mux_GPIO48: GPIO48 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad20 + >; + }; + mux_GPIO49: GPIO49 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad22 + >; + }; + mux_GPIO50: GPIO50 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad23 + >; + }; + mux_GPIO51: GPIO51 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad24 + >; + }; + mux_GPIO52: GPIO52 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad25 + >; + }; + mux_GPIO53: GPIO53 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad26 + >; + }; + mux_GPIO54: GPIO54 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad27 + >; + }; + mux_GPIO55: GPIO55 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad28 + >; + }; + mux_GPIO56: GPIO56 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad29 + >; + }; + mux_GPIO57: GPIO57 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad30 + >; + }; + mux_GPIO58: GPIO58 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad31 + >; + }; + mux_GPIO59: GPIO59 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad32 + >; + }; + mux_GPIO60: GPIO60 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad33 + >; + }; + mux_GPIO61: GPIO61 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad34 + >; + }; + mux_GPIO62: GPIO62 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad35 + >; + }; + mux_GPIO63: GPIO63 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad36 + >; + }; + }; + pinpad: pinpad { + compatible = "fh,fh-pinpad"; + pad0: PAD_BOOT_MODE_CFG { + index = <0>; + funcs = "GPIO30"; + pupd = <1>; + ds = <0>; + }; + pad1: PAD_BOOT_SEL1_CFG { + index = <1>; + funcs = "GPIO31", "ETH_LINK_ACT"; + pupd = <1>; + ds = <0>; + }; + pad2: PAD_BOOT_SEL0_CFG { + index = <2>; + funcs = "GPIO32", "ETH_LINK_STA", "ETH_LINK_SPD"; + pupd = <1>; + ds = <0>; + }; + pad3: PAD_UART0_TX_CFG { + index = <3>; + funcs = "UART0_TX", "GPIO33"; + pupd = <0>; + ds = <0>; + }; + pad4: PAD_UART0_RX_CFG { + index = <4>; + funcs = "UART0_RX", "GPIO34"; + pupd = <0>; + ds = <0>; + }; + pad5: PAD_I2C0_SCL_CFG { + index = <5>; + funcs = "I2C0_SCL", "GPIO35"; + pupd = <1>; + ds = <0>; + }; + pad6: PAD_I2C0_SDA_CFG { + index = <6>; + funcs = "I2C0_SDA", "GPIO36"; + pupd = <1>; + ds = <0>; + }; + pad7: PAD_SENSOR_CLK_CFG { + index = <7>; + funcs = "SENSOR_CLK", "GPIO12"; + pupd = <0>; + ds = <0>; + }; + pad8: PAD_SENSOR_RSTN_CFG { + index = <8>; + funcs = "GPIO13"; + pupd = <0>; + ds = <0>; + }; + pad9: PAD_UART1_TX_CFG { + index = <9>; + funcs = "UART1_TX", "GPIO39", "", "SD1_CLK", "", "", + "TEST_O_INT_RMII_CLK"; + pupd = <0>; + ds = <0>; + }; + pad10: PAD_UART1_RX_CFG { + index = <10>; + funcs = "UART1_RX", "GPIO40", "", "SD1_CD", "", "", + "TEST_INT_RMII_TXD_0"; + pupd = <0>; + ds = <0>; + }; + pad11: PAD_I2C1_SCL_CFG { + index = <11>; + funcs = "I2C1_SCL", "GPIO37", "PWM2", "SD1_CMD_RSP", "", + "SSI1_CLK", "TEST_INT_RMII_TXD_1"; + pupd = <0>; + ds = <0>; + }; + pad12: PAD_I2C1_SDA_CFG { + index = <12>; + funcs = "I2C1_SDA", "GPIO38", "PWM3", "SD1_DATA_0", "", + "SSI1_CSN_0", "TEST_INT_RMII_TXEN"; + pupd = <0>; + ds = <0>; + }; + pad13: PAD_UART2_TX_CFG { + index = <13>; + funcs = "UART2_TX", "GPIO41", "PWM4", "SD1_DATA_1", "", + "SSI1_TXD", "TEST_O_INT_RMII_RXD_0"; + pupd = <0>; + ds = <0>; + }; + pad14: PAD_UART2_RX_CFG { + index = <14>; + funcs = "UART2_RX", "GPIO42", "PWM5", "SD1_DATA_2", "", + "SSI1_RXD", "TEST_O_INT_RMII_RXD_1"; + pupd = <0>; + ds = <0>; + }; + pad15: PAD_USB_PWREN_CFG { + index = <15>; + funcs = "USB_PWREN", "GPIO47", "", "SD1_DATA_3", "", "", + "TEST_O_INT_RMII_CRSDV"; + pupd = <0>; + ds = <0>; + }; + pad16: PAD_PWM0_CFG { + index = <16>; + funcs = "PWM0", "GPIO43", "I2C2_SCL", "UART2_TX", "", "", + "TEST_O_INT_RMII_TXD_0"; + pupd = <0>; + ds = <0>; + }; + pad17: PAD_PWM1_CFG { + index = <17>; + funcs = "PWM1", "GPIO44", "I2C2_SDA", "UART2_RX", "", "", + "TEST_O_INT_RMII_TXD_1"; + pupd = <0>; + ds = <0>; + }; + pad18: PAD_PWM2_CFG { + index = <18>; + funcs = "PWM2", "GPIO45"; + pupd = <0>; + ds = <0>; + }; + pad19: PAD_PWM3_CFG { + index = <19>; + funcs = "PWM3", "GPIO46"; + pupd = <0>; + ds = <0>; + }; + pad20: PAD_MAC_RMII_CLK_CFG { + index = <20>; + funcs = "MAC_RMII_CLK", "GPIO48", "SD1_CLK", "PWM2"; + pupd = <0>; + ds = <0>; + }; + pad21: PAD_MAC_REF_CLK_CFG { + index = <21>; + funcs = "MAC_REF_CLK"; + pupd = <0>; + ds = <2>; + }; + pad22: PAD_MAC_TXD0_CFG { + index = <22>; + funcs = "MAC_TXD_0", "GPIO49", "SD1_CD", "PWM3"; + pupd = <0>; + ds = <0>; + }; + pad23: PAD_MAC_TXD1_CFG { + index = <23>; + funcs = "MAC_TXD_1", "GPIO50", "SD1_CMD_RSP", "PWM4"; + pupd = <0>; + ds = <0>; + }; + pad24: PAD_MAC_TXEN_CFG { + index = <24>; + funcs = "MAC_TXEN", "GPIO51", "SD1_DATA_0", "PWM5"; + pupd = <0>; + ds = <0>; + }; + pad25: PAD_MAC_RXD0_CFG { + index = <25>; + funcs = "MAC_RXD_0", "GPIO52", "SD1_DATA_1", "PWM6"; + pupd = <0>; + ds = <0>; + }; + pad26: PAD_MAC_RXD1_CFG { + index = <26>; + funcs = "MAC_RXD_1", "GPIO53", "SD1_DATA_2", "PWM7"; + pupd = <0>; + ds = <0>; + }; + pad27: PAD_MAC_RXDV_CFG { + index = <27>; + funcs = "MAC_RXDV", "GPIO54", "SD1_DATA_3", "PWM8"; + pupd = <0>; + ds = <0>; + }; + pad28: PAD_MAC_MDC_CFG { + index = <28>; + funcs = "MAC_MDC", "GPIO55", "", "PWM9"; + pupd = <0>; + ds = <0>; + }; + pad29: PAD_MAC_MDIO_CFG { + index = <29>; + funcs = "MAC_MDIO", "GPIO56"; + pupd = <0>; + ds = <0>; + }; + pad30: PAD_SD1_CLK_CFG { + index = <30>; + funcs = "SD1_CLK", "GPIO57", "I2C1_SCL"; + pupd = <0>; + ds = <0>; + }; + pad31: PAD_SD1_CD_CFG { + index = <31>; + funcs = "SD1_CD", "GPIO58", "I2C1_SDA"; + pupd = <0>; + ds = <0>; + }; + pad32: PAD_SD1_CMD_RSP_CFG { + index = <32>; + funcs = "SD1_CMD_RSP", "GPIO59", "UART1_TX"; + pupd = <0>; + ds = <0>; + }; + pad33: PAD_SD1_DATA_0_CFG { + index = <33>; + funcs = "SD1_DATA_0", "GPIO60", "UART1_RX"; + pupd = <0>; + ds = <0>; + }; + pad34: PAD_SD1_DATA_1_CFG { + index = <34>; + funcs = "SD1_DATA_1", "GPIO61", "UART2_TX"; + pupd = <0>; + ds = <0>; + }; + pad35: PAD_SD1_DATA_2_CFG { + index = <35>; + funcs = "SD1_DATA_2", "GPIO62", "UART2_RX"; + pupd = <0>; + ds = <0>; + }; + pad36: PAD_SD1_DATA_3_CFG { + index = <36>; + funcs = "SD1_DATA_3", "GPIO63"; + pupd = <0>; + ds = <0>; + }; + pad37: PAD_GPIO_0_CFG { + index = <37>; + funcs = "ARM_JTAG_TRSTN", "GPIO0", "AC_I2S_DO", "DW_I2S_DO", + "SSI1_CLK", "SSI2_CLK", "ACIP_ADDAT", "PWM6", + "TEST_O_INT_SMI_MDC"; + pupd = <0>; + ds = <0>; + }; + pad38: PAD_GPIO_1_CFG { + index = <38>; + funcs = "ARM_JTAG_TDO", "GPIO1", "AC_I2S_DI", "DW_I2S_DI", + "SSI1_CSN_0", "SSI2_CSN_0", "ACIP_DADAT", "PWM7", + "TEST_O_INT_SMI_MDIO_I"; + pupd = <0>; + ds = <0>; + }; + pad39: PAD_GPIO_2_CFG { + index = <39>; + funcs = "ARM_JTAG_TDI", "GPIO2", "AC_I2S_CLK", "DW_I2S_CLK", + "SSI1_TXD", "SSI2_TXD", "ACIP_ADBCLK", "PWM8", + "TEST_O_INT_SMI_MDIO_O"; + pupd = <0>; + ds = <0>; + }; + pad40: PAD_GPIO_3_CFG { + index = <40>; + funcs = "ARM_JTAG_TCK", "GPIO3", "AC_I2S_WS", "DW_I2S_WS", + "SSI1_RXD", "SSI2_RXD", "ACIP_ADLRC", "PWM9", + "TEST_I_INT_SMI_MDIO_I"; + pupd = <0>; + ds = <0>; + }; + pad41: PAD_GPIO_4_CFG { + index = <41>; + funcs = "ARM_JTAG_TMS", "GPIO4", "AC_MCLK", "USB_PWREN", + "SD1_CD", "TEST_I_INT_SMI_MDC"; + pupd = <0>; + ds = <0>; + }; + pad42: PAD_SSI0_CLK_CFG { + index = <42>; + funcs = "SSI0_CLK", "GPIO5", "", "", "SD1_CLK"; + pupd = <0>; + ds = <2>; + }; + pad43: PAD_SSI0_CSN_0_CFG { + index = <43>; + funcs = "SSI0_CSN_0", "GPIO6", "", "", "SD1_CMD_RSP"; + pupd = <0>; + ds = <2>; + }; + pad44: PAD_SSI0_TXD_CFG { + index = <44>; + funcs = "SSI0_TXD", "GPIO7", "", "", "SD1_DATA_0"; + pupd = <0>; + ds = <2>; + }; + pad45: PAD_SSI0_RXD_CFG { + index = <45>; + funcs = "SSI0_RXD", "GPIO8", "", "", "SD1_DATA_1"; + pupd = <0>; + ds = <2>; + }; + pad46: PAD_SSI0_D2_CFG { + index = <46>; + funcs = "SSI0_D2", "GPIO9", "UART1_TX", "I2C1_SCL", + "SD1_DATA_2"; + pupd = <0>; + ds = <2>; + }; + pad47: PAD_SSI0_D3_CFG { + index = <47>; + funcs = "SSI0_D3", "GPIO10", "UART1_RX", "I2C1_SDA", + "SD1_DATA_3"; + pupd = <0>; + ds = <2>; + }; + pad48: PAD_SSI1_CLK_CFG { + index = <48>; + funcs = "SSI1_CLK", "GPIO11", "SSI2_CLK"; + pupd = <0>; + ds = <0>; + }; + pad49: PAD_SSI1_CSN_0_CFG { + index = <49>; + funcs = "SSI1_CSN_0", "GPIO14", "SSI2_CSN_0"; + pupd = <0>; + ds = <0>; + }; + pad50: PAD_SSI1_TXD_CFG { + index = <50>; + funcs = "SSI1_TXD", "GPIO15", "SSI2_TXD"; + pupd = <0>; + ds = <0>; + }; + pad51: PAD_SSI1_RXD_CFG { + index = <51>; + funcs = "SSI1_RXD", "GPIO16", "SSI2_RXD"; + pupd = <0>; + ds = <0>; + }; + pad52: PAD_SD0_CD_CFG { + index = <52>; + funcs = "SD0_CD", "GPIO17", "", "ARC_JTAG_TRSTN", + "PAE_JTAG_TRSTN"; + pupd = <0>; + ds = <0>; + }; + pad53: PAD_SD0_CLK_CFG { + index = <53>; + funcs = "SD0_CLK", "GPIO18", "SSI1_CLK", "ARC_JTAG_TDO", + "PAE_JTAG_TDO"; + pupd = <0>; + ds = <2>; + }; + pad54: PAD_SD0_CMD_RSP_CFG { + index = <54>; + funcs = "SD0_CMD_RSP", "GPIO19", "SSI1_TXD", "ARC_JTAG_TDI", + "PAE_JTAG_TDI"; + pupd = <0>; + ds = <2>; + }; + pad55: PAD_SD0_DATA_0_CFG { + index = <55>; + funcs = "SD0_DATA_0", "GPIO20", "SSI1_RXD", "ARC_JTAG_TCK", + "PAE_JTAG_TCK"; + pupd = <0>; + ds = <2>; + }; + pad56: PAD_SD0_DATA_1_CFG { + index = <56>; + funcs = "SD0_DATA_1", "GPIO21", "SSI1_CSN_0", "ARC_JTAG_TMS", + "PAE_JTAG_TMS"; + pupd = <0>; + ds = <2>; + }; + pad57: PAD_SD0_DATA_2_CFG { + index = <57>; + funcs = "SD0_DATA_2", "GPIO22", "", "UART2_TX", "I2C2_SCL", "", + "ACIP_DABCLK"; + pupd = <0>; + ds = <2>; + }; + pad58: PAD_SD0_DATA_3_CFG { + index = <58>; + funcs = "SD0_DATA_3", "GPIO23", "SSI1_CSN_0", "UART2_RX", + "I2C2_SDA", "", "ACIP_DALRC"; + pupd = <0>; + ds = <2>; + }; + pad59: PAD_SADC_XAIN0_CFG { + index = <59>; + funcs = "SADC_XAIN0", "GPIO26"; + pupd = <0>; + ds = <0>; + }; + pad60: PAD_SADC_XAIN1_CFG { + index = <60>; + funcs = "SADC_XAIN1", "GPIO27"; + pupd = <0>; + ds = <0>; + }; + pad61: PAD_SADC_XAIN2_CFG { + index = <61>; + funcs = "SADC_XAIN2", "GPIO24"; + pupd = <0>; + ds = <0>; + }; + pad62: PAD_SADC_XAIN3_CFG { + index = <62>; + funcs = "SADC_XAIN3", "GPIO25"; + pupd = <0>; + ds = <0>; + }; + pad63: PAD_GPIO_28_CFG { + index = <63>; + funcs = "GPIO28", "", "ETH_LINK_ACT", "PWM10", + "USB_DBG_CLK", "SD1_CD", "TEST_O_INT_RMII_TXEN", + "MAC_MDC"; + pupd = <0>; + ds = <0>; + }; + pad64: PAD_GPIO_29_CFG { + index = <64>; + funcs = "GPIO29", "", "ETH_LINK_STA", "PWM11", "RTC_CLK", + "ETH_LINK_SPD", "TEST_O_INT_SMI_MDIO_OE", + "MAC_MDIO"; + pupd = <0>; + ds = <0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/fh8856v200.dts b/arch/arm/boot/dts/fh8856v200.dts new file mode 100644 index 00000000..2a75d423 --- /dev/null +++ b/arch/arm/boot/dts/fh8856v200.dts @@ -0,0 +1,956 @@ +/* + * Copyright (C) 2017 Fullhan Micorelectonics Co.,Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "skeleton.dtsi" +/include/ "fh8856v200_pinctrl.dtsi" +/ { + + + model = "FULLHAN FH8856V200"; + compatible = "fh,fh8856v200"; + interrupt-parent = <&intc>; + aliases { + i2c0 = &i2cbus0; + i2c1 = &i2cbus1; + i2c2 = &i2cbus2; + spi0 = &spi_bus0; + spi1 = &spi_bus1; + ttyS0 = &serial0; + ttyS1 = &serial1; + ttyS2 = &serial2; + }; + + cpus { + cpu@0 { + device_type = "cpu"; + compatible = "arm,arm1176jzf-s"; + }; + }; + + chosen { + bootargs = "coherent_pool=2M"; + }; + + intc: interrupt-controller@E0200000 { + compatible = "fh,fh-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xE0200000 0x1000>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pmu@f0000000 { + compatible = "fh,fh-pmu"; + reg = <0xf0000000 0x2100>; + SWRST_MAIN_CTRL = <0x40>; + }; + timer0: timer@f0c00000 { + compatible = "fh,fh-timer"; + interrupts = <3>; + clock-frequency = <1000000>; + reg = <0xf0c00000 0x14>; + }; + + timer1: timer@f0c00014 { + compatible = "fh,fh-timer"; + interrupts = <3>; + clock-frequency = <1000000>; + reg = <0xf0c00014 0x14>; + }; + + gpio0: gpio@f0300000 { + compatible = "fh,fh-gpio"; + reg = <0xf0300000 0x1000>; + #gpio_controller; + interrupt-controller; + interrupt-parent = <&intc>; + interrupts = <26>; + id = <0>; + ngpio = <32>; + base = <0>; + }; + + gpio1: gpio@f4000000 { + compatible = "fh,fh-gpio"; + reg = <0xf4000000 0x1000>; + #gpio_controller; + interrupt-controller; + interrupt-parent = <&intc>; + interrupts = <40>; + id = <1>; + ngpio = <32>; + base = <32>; + }; + + fhdma0: dma@e0300000 { + compatible = "fh,fh-axi-dmac"; + reg = <0xe0300000 0x1000>; + interrupts = <23>; + chan_allocation_order = <0>; + chan_priority = <1>; + block_size = <0x800>; + data_width = <2 0 0 0>; + clocks = <&ahb_clk>; + }; + + aes: aes@0xe8200000 { + compatible = "fh,fh-aes"; + reg = <0xe8200000 0x1000>; + interrupts = <16>; + }; + rtc: rtc@f1500000 { + compatible = "fh,fh_rtc"; + reg = <0xf1500000 0x1000>; + interrupts = <33>; + clocks = <&rtc_hclk_gate>; + lut_cof = <58>; + lut_offset = <0xff>; + tsensor_cp_default_out = <0x993>; + }; + sadc: sadc@f1200000 { + compatible = "fh,fh-sadc"; + reg = <0xf1200000 0x1000>; + interrupts = <20>; + ref-vol = <1800>; + active-bit = <0xfff>; + }; + efuse: efuse@0xf1600000 { + compatible = "fh,fh-efuse"; + reg = <0xf1600000 0x1000>; + key_switch = "enable"; + indep_power = "enable"; + }; + fh_perf: fh_perf@0xf0002018 { + compatible = "fh,fh-perf"; + reg = <0xf0000000 0x4000>; + interrupts = < 5 >; + + }; + spi_bus0: spi@f0500000 { + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + compatible = "fh,fh-spi"; + reg = <0xf0500000 0x4000>; + clk_in = <100000000>; + clock_source = <100000000>; + clock_source_num = <1>; + num-cs = <2>; + cs0_gpio = <6>; + cs1_gpio = <55>; + dma_enable = "disable"; + swap_support = "enable"; + rx_hs_no = <4>; + tx_hs_no = <5>; + bus_no = <0>; + multi_wire_size = <2>; + clk_name = "spi0_clk"; + rx_dma_channel = <0>; + tx_dma_channel = <1>; + increase_support = "disable"; + data_field_size = <0x1000>; + data_reg_offset = <0x1000>; + dma_protctl_enable = "disable"; + dma_protctl_data = <6>; + dma_master_sel_enable = "disable"; + dma_master_ctl_sel = <0>; + dma_master_mem_sel = <0>; + spidma_xfer_mode = "rx_only"; + interrupts = <28>; + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fh,m25p80"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + reg = <0x0 0>; //first value means which slave bind to the master. 0 means chip 0. 1 means chip 1 + partition@0 { + reg = <0x0 0x40000>; + label = "bootstrap"; + }; + partition@40000 { + reg = <0x40000 0x10000>; + label = "uboot-env"; + }; + partition@50000 { + reg = <0x50000 0x30000>; + label = "uboot"; + }; + partition@80000 { + reg = <0x80000 0x400000>; + label = "kernel"; + }; + partition@480000 { + reg = <0x480000 0x80000>; + label = "rootfs"; + }; + partition@500000 { + reg = <0x500000 0x300000>; + label = "app"; + }; + + }; + spidev0: spi@0 { + compatible = "rohm,dh2228fv"; + reg = <0x1 0>; + spi-max-frequency = <50000000>; + }; + }; + spi_bus1: spi@f0600000 { + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + compatible = "fh,fh-spi"; + reg = <0xf0600000 0x4000>; + clk_in = <100000000>; + clock_source = <100000000>; + clock_source_num = <1>; + num-cs = <2>; + cs0_gpio = <14>; + cs1_gpio = <57>; + dma_enable = "disable"; + swap_support = "disable"; + rx_hs_no = <2>; + tx_hs_no = <3>; + bus_no = <1>; + clk_name = "spi1_clk"; + rx_dma_channel = <2>; + tx_dma_channel = <3>; + increase_support = "disable"; + data_field_size = <0x1000>; + data_reg_offset = <0x1000>; + dma_protctl_enable = "disable"; + dma_protctl_data = <6>; + dma_master_sel_enable = "disable"; + dma_master_ctl_sel = <0>; + dma_master_mem_sel = <0>; + spidma_xfer_mode = "rx_only"; + interrupts = <21>; + spidev1: spi@1 { + compatible = "rohm,dh2228fv"; + reg = <0x0 0>; + spi-max-frequency = <50000000>; + }; + spidev2: spi@2 { + compatible = "rohm,dh2228fv"; + reg = <0x1 0>; + spi-max-frequency = <50000000>; + }; + }; + fhdwi2s: i2s@f0900000 { + compatible = "fh,fh-dw_i2s"; + reg = <0xf0900000 0x1000>; + interrupts = <25>; + clocks = <&i2s_clk>, <&ac_clk>; + clock-names = "i2s_clk", "acodec_mclk"; + rx_dma_channel = <2>; + tx_dma_channel = <3>; + dma_master = <0>; + dma_rx_hs_num = <10>; + dma_tx_hs_num = <11>; + }; + + fhacw: acw@f0a00000 { + compatible = "fh,fh-acw"; + reg = <0xf0a00000 0x1000>; + interrupts = <19>; + clocks = <&ac_clk>; + clock-names = "ac_clk"; + rx_dma_channel = <4>; + tx_dma_channel = <5>; + dma_master = <0>; + dma_rx_hs_num = <0>; + dma_tx_hs_num = <1>; + }; + + pwm: pwm@f0400000{ + compatible = "fh,fh-pwm"; + reg = <0xf0400000 0x1000>; + interrupts = <36>; + npwm = <14>; + }; + serial0: serial@f0700000 { + compatible = "fh,fh-serial"; + reg = <0xf0700000 0x1000>; + interrupts = <30>; + clock-frequency = <16666667>; + fifo-size = <32>; + }; + serial1: serial@f0800000 { + compatible = "fh,fh-serial"; + reg = <0xf0800000 0x1000>; + interrupts = <31>; + clock-frequency = <16666667>; + fifo-size = <64>; + }; + serial2: serial@f1300000 { + compatible = "fh,fh-serial"; + reg = <0xf1300000 0x1000>; + interrupts = <41>; + clock-frequency = <16666667>; + fifo-size = <64>; + }; + gmac0: gmac@e0600000 { + compatible = "fh,fh-gmac"; + reg = <0xe0600000 0x2000>; + interrupts = <44>; + phyreset-gpio = <29>; + }; + sdc0: sdc0@e2000000 { + compatible = "fh,fh-sdc"; + reg = <0xe2000000 0x4000>; + interrupts = <42>; + id = <0>; + buswidth = <4>; + wp-fixed = <1>; + cd-fixed = <0>; + drv-degree = <8>; + sam-degree = <0>; + scan-mux = <0>; + }; + sdc1: sdc1@e2200000 { + compatible = "fh,fh-sdc"; + reg = <0xe2200000 0x4000>; + interrupts = <43>; + id = <1>; + buswidth = <4>; + wp-fixed = <1>; + cd-fixed = <1>; + drv-degree = <8>; + sam-degree = <0>; + scan-mux = <2>; + }; + wdt: wdt@f0d00000{ + compatible = "fh,fh-wdt"; + reg = <0xf0d00000 0x1000>; + interrupts = <2>; + mode = <1>; + }; + i2cbus0: i2c@f0200000 { + compatible = "fh,fh-i2c"; + reg = <0xf0200000 0x2000>; + interrupts = <11>; + }; + i2cbus1: i2c@f0b00000 { + compatible = "fh,fh-i2c"; + reg = <0xf0b00000 0x2000>; + interrupts = <12>; + }; + i2cbus2: i2c@0xF0100000 { + compatible = "fh,fh-i2c"; + reg = <0xF0100000 0x2000>; + interrupts = <46>; + }; + clocks: src_clk@0xf0000000{ + compatible = "fh,fh-clk"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf0000000 0x80>; + ranges; + + osc_clk: mxtal@24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc_clk"; + }; + + pll_ddr_rclk: pllddrr{ + #clock-cells = <0>; + compatible = "fh pll-ddr-rclk"; + reg = <0xf0000010 0x4>,<0xf0000018 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f000000>; + divcop = <0xf000>; + clocks = <&osc_clk>; + clock-output-names = "pll_ddr_rclk"; + }; + pll_cpu_pclk: pllcpup{ + #clock-cells = <0>; + compatible = "fh pll-cpu-pclk"; + reg = <0xf0000014 0x4>,<0xf000006c 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f0000>; + divcop = <0xf00>; + clocks = <&osc_clk>; + clock-output-names = "pll_cpu_pclk"; + }; + pll_cpu_rclk: pllcpur{ + #clock-cells = <0>; + compatible = "fh pll-cpu-rclk"; + reg = <0xf0000014 0x4>,<0xf000006c 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f000000>; + divcop = <0xf000>; + clocks = <&osc_clk>; + clock-output-names = "pll_cpu_rclk"; + }; + pll_sys_pclk: pllsysp{ + #clock-cells = <0>; + compatible = "fh pll-sys-pclk"; + reg = <0xf0000064 0x4>,<0xf0000068 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f0000>; + divcop = <0xf00>; + clocks = <&osc_clk>; + clock-output-names = "pll_sys_pclk"; + }; + pll_sys_rclk: pllsysr{ + #clock-cells = <0>; + compatible = "fh pll-sys-rclk"; + reg = <0xf0000064 0x4>,<0xf0000068 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f000000>; + divcop = <0xf000>; + clocks = <&osc_clk>; + clock-output-names = "pll_sys_rclk"; + }; + sysp_div12_clk: syspdiv12clk{ + #clock-cells = <0>; + compatible = "fh sysp-div12-clk"; + reg = <0xf0000038 0x4>,<0x0 0x4>,<0x0 0x4>; + div = <0xf000000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "sysp_div12_clk"; + }; + ddr_clk: ddrclk{ + #clock-cells = <0>; + compatible = "fh fh-ddr-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x4000000>; + clocks = <&pll_ddr_rclk>; + clock-output-names = "ddr_clk"; + }; + arm_clk: armclk{ + #clock-cells = <0>; + compatible = "fh fh-arm-clk"; + reg = <0x0 0x4>,<0x0 0x4>,<0xf000000c 0x4>; + mux = <0x1>; + clocks = <&osc_clk>,<&pll_cpu_pclk>; + clock-output-names = "arm_clk"; + }; + arc_clk: arcclk{ + #clock-cells = <0>; + compatible = "fh fh-arc-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0xf000000c 0x4>; + gate = <0x4000000>; + mux = <0x1>; + clocks = <&osc_clk>,<&pll_cpu_rclk>; + clock-output-names = "arc_clk"; + }; + ahb_clk: ahbclk{ + #clock-cells = <0>; + compatible = "fh fh-ahb-clk"; + reg = <0xf0000024 0x4>,<0x0 0x4>,<0xf000000c 0x4>; + div = <0xf0000>; + mux = <0x1>; + clocks = <&osc_clk>,<&pll_sys_pclk>; + clock-output-names = "ahb_clk"; + }; + isp_aclk: ispaclk{ + #clock-cells = <0>; + compatible = "fh fh-ispa-clk"; + reg = <0xf0000024 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xf00>; + gate = <0x1>; + clocks = <&pll_sys_pclk>; + clock-output-names = "isp_aclk"; + }; + ispb_aclk: ispbclk{ + #clock-cells = <0>; + compatible = "fh fh-ispb-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + gate = <0x4>; + clocks = <&isp_aclk>; + clock-output-names = "ispb_aclk"; + }; + vpu_clk: vpuclk{ + #clock-cells = <0>; + compatible = "fh fh-vpu-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x80000000>; + clocks = <&isp_aclk>; + clock-output-names = "vpu_clk"; + }; + pix_clk: pixclk{ + #clock-cells = <0>; + compatible = "fh fh-pix-clk"; + reg = <0xf000002c 0x4>,<0x0 0x4>,<0x0 0x4>; + div = <0xf000000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "pix_clk"; + }; + jpeg_clk: jpegclk{ + #clock-cells = <0>; + compatible = "fh fh-jpeg-clk"; + reg = <0xf000005c 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + div = <0xf00000>; + gate = <0x40000000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "jpeg_clk"; + }; + bgm_clk: bgmclk{ + #clock-cells = <0>; + compatible = "fh fh-bgm-clk"; + reg = <0xf000005c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xf00000>; + gate = <0x40000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "bgm_clk"; + }; + jpeg_adapt_clk: jpegadaptclk{ + #clock-cells = <0>; + compatible = "fh fh-jpeg-adapt-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x2>; + clocks = <&jpeg_clk>; + clock-output-names = "jpeg_adapt_clk"; + }; + spi0_clk: spi0clk{ + #clock-cells = <0>; + compatible = "fh fh-spi0-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff>; + gate = <0x80>; + clocks = <&pll_sys_pclk>; + clock-output-names = "spi0_clk"; + }; + sdc0_clk: sdc0clk{ + #clock-cells = <0>; + compatible = "fh fh-sdc0-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + prediv =<8>; + div = <0xf00>; + gate = <0x200>; + clocks = <&pll_sys_pclk>; + clock-output-names = "sdc0_clk"; + }; + spi2_clk: spi2clk{ + #clock-cells = <0>; + compatible = "fh fh-spi2-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xf000>; + gate = <0x2>; + clocks = <&pll_sys_pclk>; + clock-output-names = "spi2_clk"; + }; + spi1_clk: spi1clk{ + #clock-cells = <0>; + compatible = "fh fh-spi1-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff0000>; + gate = <0x100>; + clocks = <&pll_sys_pclk>; + clock-output-names = "spi1_clk"; + }; + sdc1_clk: sdc1clk{ + #clock-cells = <0>; + compatible = "fh fh-sdc1-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + prediv =<8>; + div = <0xf000000>; + gate = <0x400>; + clocks = <&pll_sys_pclk>; + clock-output-names = "sdc1_clk"; + }; + veu_clk: veuclk{ + #clock-cells = <0>; + compatible = "fh fh-veu-clk"; + reg = <0xf0000024 0x4>,<0xf000001c 0x4>,<0xf000000c 0x4>; + div = <0x7000000>; + gate = <0x10>; + mux = <0x4>; + clocks = <&pll_sys_pclk>,<&pll_sys_rclk>; + clock-output-names = "veu_clk"; + }; + veu_adapt_clk: veuadaptclk{ + #clock-cells = <0>; + compatible = "fh fh-veu-adapt-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + gate = <0x20000000>; + clocks = <&veu_clk>; + clock-output-names = "veu_adapt_clk"; + }; + cis_clk_out: cisclk{ + #clock-cells = <0>; + compatible = "fh fh-cis-clk-out"; + reg = <0xf0000028 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff0000>; + gate = <0x800000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "cis_clk_out"; + }; + eth_clk: ethclk{ + #clock-cells = <0>; + compatible = "fh fh-eth-clk"; + reg = <0xf000003c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xf000000>; + gate = <0x2000000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "eth_clk"; + }; + eth_rmii_clk: ethrmiiclk { + #clock-cells = <0>; + compatible = "fh fh-ethrmii-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + gate = <0x10000000>; + clock-output-names = "eth_rmii_clk"; + }; + i2c0_clk: i2c0clk { + #clock-cells = <0>; + compatible = "fh fh-i2c0-clk"; + reg = <0xf0000034 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f0000>; + gate = <0x1000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "i2c0_clk"; + }; + + i2c1_clk: i2c1clk { + #clock-cells = <0>; + compatible = "fh fh-i2c1-clk"; + reg = <0xf0000034 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f000000>; + gate = <0x8000000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "i2c1_clk"; + }; + i2c2_clk: i2c2clk { + #clock-cells = <0>; + compatible = "fh fh-i2c2-clk"; + reg = <0xf000005c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f00>; + gate = <0x00000008>; + clocks = <&sysp_div12_clk>; + clock-output-names = "i2c2_clk"; + }; + + uart0_clk: uart0clk { + #clock-cells = <0>; + compatible = "fh fh-uart0-clk"; + reg = <0xf0000034 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x1f>; + gate = <0x2000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "uart0_clk"; + }; + + uart1_clk: uart1clk { + #clock-cells = <0>; + compatible = "fh fh-uart1-clk"; + reg = <0xf0000034 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x1f00>; + gate = <0x4000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "uart1_clk"; + }; + uart2_clk: uart2clk { + #clock-cells = <0>; + compatible = "fh fh-uart2-clk"; + reg = <0xf000005c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x7f>; + gate = <0x8000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "uart2_clk"; + }; + pwm_clk: pwmclk { + #clock-cells = <0>; + compatible = "fh fh-pwm-clk"; + reg = <0xf0000038 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff>; + gate = <0x10000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "pwm_clk"; + }; + efuse_clk: efuseclk { + #clock-cells = <0>; + compatible = "fh fh-efuse-clk"; + reg = <0xf0000028 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f000000>; + gate = <0x200000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "efuse_clk"; + }; + pts_clk: ptsclk { + #clock-cells = <0>; + compatible = "fh fh-pts-clk"; + reg = <0xf000002c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x1ff>; + gate = <0x80000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "pts_clk"; + }; + tmr0_clk: tmr0clk { + #clock-cells = <0>; + compatible = "fh fh-tmr0-clk"; + reg = <0xf0000038 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff0000>; + gate = <0x20000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "tmr0_clk"; + }; + + sadc_clk: sadcclk { + #clock-cells = <0>; + compatible = "fh fh-sadc-clk"; + reg = <0xf000003c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x7f0000>; + gate = <0x4000000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "sadc_clk"; + }; + gpio0_dbclk: gpio0dbclk { + #clock-cells = <0>; + compatible = "fh fh-gpio0-dbclk"; + reg = <0xf0000060 0x4>,<0xf0000060 0x4>,<0x0 0x4>; + div = <0x7fff>; + gate = <0x8000>; + prediv = <100>; + clocks = <&sysp_div12_clk>; + clock-output-names = "gpio0_dbclk"; + }; + gpio1_dbclk: gpio1dbclk { + #clock-cells = <0>; + compatible = "fh fh-gpio1-dbclk"; + reg = <0xf0000060 0x4>,<0xf0000060 0x4>,<0x0 0x4>; + div = <0x7fff0000>; + gate = <0x80000000>; + prediv = <100>; + clocks = <&sysp_div12_clk>; + clock-output-names = "gpio1_dbclk"; + }; + wdt_clk: wdtclk { + #clock-cells = <0>; + compatible = "fh fh-wdt-clk"; + reg = <0xf0000038 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + div = <0xff00>; + gate = <0x8000000>; + clocks = <&ahb_clk>; + clock-output-names = "wdt_clk"; + }; + ac_clk: acclk{ + #clock-cells = <0>; + compatible = "fh fh-ac-clk"; + reg = <0xf000003c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f>; + gate = <0x800>; + clocks = <&osc_clk>; + clock-output-names = "ac_clk"; + }; + i2s_clk: i2sclk{ + #clock-cells = <0>; + compatible = "fh fh-i2s-clk"; + reg = <0xf000003c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f00>; + gate = <0x1000000>; + clocks = <&ac_clk>; + clock-output-names = "i2s_clk"; + }; + mipi_dphy_clk: mipidphyclk { + #clock-cells = <0>; + compatible = "fh fh-mipi-dphy-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + gate = <0x100000>; + clock-output-names = "mipi_dphy_clk"; + }; + mipi_wrap_gate: mipiwrapclk { + #clock-cells = <0>; + compatible = "fh fh-mipi-wrap-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x20000000>; + clock-output-names = "mipi_wrap_gate"; + }; + rtc_hclk_gate: rtchclk { + #clock-cells = <0>; + compatible = "fh fh-rtc-hclk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x10000000>; + clock-output-names = "rtc_hclk_gate"; + }; + emac_hclk_gate: emachclk { + #clock-cells = <0>; + compatible = "fh fh-emac-hclk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x2000000>; + clock-output-names = "emac_hclk_gate"; + }; + usb_clk: usbclk { + #clock-cells = <0>; + compatible = "fh fh-usb-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x1000000>; + clock-output-names = "usb_clk"; + }; + aes_hclk_gate: aeshclk { + #clock-cells = <0>; + compatible = "fh fh-aes-hclk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x80>; + clock-output-names = "aes_hclk_gate"; + }; + ephy_clk_gate: ephyclk { + #clock-cells = <0>; + compatible = "fh fh-ephy-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x1>; + clock-output-names = "ephy_clk_gate"; + }; + sdc0_clk8x_gate: sdc08xclk { + #clock-cells = <0>; + compatible = "fh fh-sdc08x-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x4>; + clock-output-names = "sdc0_clk8x_gate"; + }; + sdc1_clk8x_gate: sdc18xclk { + #clock-cells = <0>; + compatible = "fh fh-sdc18x-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x8>; + clock-output-names = "sdc1_clk8x_gate"; + }; + mipic_pclk_gate: mipicpclk { + #clock-cells = <0>; + compatible = "fh fh-mipic-pclk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x10>; + clock-output-names = "mipic_pclk_gate"; + }; + gpio0_pclk_gate: gpio0pclk { + #clock-cells = <0>; + compatible = "fh fh-gpio0-pclk"; + reg = <0x0 0x4>,<0xf0000060 0x4>,<0x0 0x4>; + gate = <0x4000>; + clock-output-names = "gpio0_pclk_gate"; + }; + gpio1_pclk_gate: gpio1pclk { + #clock-cells = <0>; + compatible = "fh fh-gpio1-pclk"; + reg = <0x0 0x4>,<0xf0000060 0x4>,<0x0 0x4>; + gate = <0x40000000>; + clock-output-names = "gpio1_pclk_gate"; + }; + isp_hclk_gate: isphclk { + #clock-cells = <0>; + compatible = "fh fh-isp-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x1000000>; + clock-output-names = "isp_hclk_gate"; + }; + veu_hclk_gate: veuhclk { + #clock-cells = <0>; + compatible = "fh fh-veu-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x2000000>; + clock-output-names = "veu_hclk_gate"; + }; + bgm_hclk_gate: bgmhclk { + #clock-cells = <0>; + compatible = "fh fh-bgm-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x4000000>; + clock-output-names = "bgm_hclk_gate"; + }; + adapt_hclk_gate: adapthclk { + #clock-cells = <0>; + compatible = "fh fh-adapt-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x8000000>; + clock-output-names = "adapt_hclk_gate"; + }; + jpg_hclk_gate: jpghclk { + #clock-cells = <0>; + compatible = "fh fh-jpg-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x10000000>; + clock-output-names = "jpg_hclk_gate"; + }; + jpg_adapt_gate: jpgadaptclk { + #clock-cells = <0>; + compatible = "fh fh-jpg-adapt-clk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x20000000>; + clock-output-names = "jpg_adapt_gate"; + }; + vpu_hclk_gate: vpuhclk { + #clock-cells = <0>; + compatible = "fh fh-vpu-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x40000000>; + clock-output-names = "vpu_hclk_gate"; + }; + sdc0_clk_sample: sdc0clksample { + #clock-cells = <0>; + compatible = "fh fh-sdc0-clk_sample"; + reg = <0xf0000020 0x4>; + mux = <0xf0000>; + clocks = <&sdc0_clk>; + clock-output-names = "sdc0_clk_sample"; + }; + sdc0_clk_drv: sdc0clkdrv { + #clock-cells = <0>; + compatible = "fh fh-sdc0-clk_drv"; + reg = <0xf0000020 0x4>; + mux = <0xf00000>; + clocks = <&sdc0_clk>; + clock-output-names = "sdc0_clk_drv"; + }; + + sdc1_clk_sample: sdc1clksample { + #clock-cells = <0>; + compatible = "fh fh-sdc1-clk_sample"; + reg = <0xf0000020 0x4>; + mux = <0xf00>; + clocks = <&sdc1_clk>; + clock-output-names = "sdc1_clk_sample"; + }; + + sdc1_clk_drv: sdc1clkdrv { + #clock-cells = <0>; + compatible = "fh fh-sdc1-clk_drv"; + reg = <0xf0000020 0x4>; + mux = <0xf000>; + clocks = <&sdc1_clk>; + clock-output-names = "sdc1_clk_drv"; + }; + }; + }; + + usb_otg@e0700000 { + compatible = "fh_usb"; + reg = <0xe0700000 100000>; + interrupts = <39>; + clocks = <&usb_clk>; + dr_mode = "host"; + vbus_pwren = <47>; + clock-names = "otg"; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + }; + + usb2_phy: usbphy { + compatible = "fh,fh-usb2-phy"; + #phy-cells = <0>; + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/fh8856v200_pinctrl.dtsi b/arch/arm/boot/dts/fh8856v200_pinctrl.dtsi new file mode 100644 index 00000000..195479e3 --- /dev/null +++ b/arch/arm/boot/dts/fh8856v200_pinctrl.dtsi @@ -0,0 +1,2386 @@ +/* + * Copyright (C) 2020 Fullhan Micorelectonics Co.,Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + #define PUPD_NONE (0) + #define PUPD_UP (1) + #define PUPD_DOWN (2) +*/ + +/ { + pinctrl: pinctrl@f0000080 { + compatible = "fh,fh-pinctrl"; + reg = <0xf0000080 0x104>; + pad-num = <65>; + max-mux = <9>; + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_ETH + &pinctrl_I2C0 + &pinctrl_PWM2 + &pinctrl_PWM3 + &pinctrl_PWM4 + &pinctrl_PWM5 + &pinctrl_PWM6 + &pinctrl_PWM7 + &pinctrl_PWM8 + &pinctrl_PWM9 + &pinctrl_SADC_XAIN0 + &pinctrl_SADC_XAIN1 + &pinctrl_SD0_NO_WP + &pinctrl_SENSOR_CLK + &pinctrl_SSI0_4BIT + &pinctrl_UART0 + &pinctrl_UART1 + &pinctrl_GPIO4 + &pinctrl_GPIO13 + &pinctrl_GPIO30 + &pinctrl_GPIO31 + &pinctrl_GPIO32 + &pinctrl_GPIO43 + &pinctrl_GPIO44 + &pinctrl_GPIO47 + + &pinctrl_GPIO11 + &pinctrl_GPIO14 + &pinctrl_GPIO15 + &pinctrl_GPIO16 + &pinctrl_GPIO24 + &pinctrl_GPIO25 + &pinctrl_GPIO45 + &pinctrl_GPIO46 + &pinctrl_GPIO48 + &pinctrl_GPIO49 + &pinctrl_GPIO50 + &pinctrl_GPIO51 + &pinctrl_GPIO52 + &pinctrl_GPIO53 + &pinctrl_GPIO54 + &pinctrl_GPIO55 + &pinctrl_GPIO56 + &pinctrl_GPIO57 + &pinctrl_GPIO58 + &pinctrl_GPIO59 + &pinctrl_GPIO60 + &pinctrl_GPIO61 + &pinctrl_GPIO62 + &pinctrl_GPIO63 + >; + pinctrl_groups { + pinctrl_ACI2S: ACI2S { + fh,pins = < + &mux_AC_I2S_CLK 0 + &mux_AC_I2S_DI 0 + &mux_AC_I2S_DO 0 + &mux_AC_I2S_WS 0 + &mux_AC_MCLK 0 + >; + }; + pinctrl_AC_MCLK: AC_MCLK { + fh,pins = < + &mux_AC_MCLK 0 + >; + }; + pinctrl_ARCJTAG: ARCJTAG { + fh,pins = < + &mux_ARC_JTAG_TCK 0 + &mux_ARC_JTAG_TDI 0 + &mux_ARC_JTAG_TDO 0 + &mux_ARC_JTAG_TMS 0 + &mux_ARC_JTAG_TRSTN 0 + >; + }; + pinctrl_ARMJTAG: ARMJTAG { + fh,pins = < + &mux_ARM_JTAG_TCK 0 + &mux_ARM_JTAG_TDI 0 + &mux_ARM_JTAG_TDO 0 + &mux_ARM_JTAG_TMS 0 + &mux_ARM_JTAG_TRSTN 0 + >; + }; + pinctrl_DWI2S: DWI2S { + fh,pins = < + &mux_DW_I2S_CLK 0 + &mux_DW_I2S_DI 0 + &mux_DW_I2S_DO 0 + &mux_DW_I2S_WS 0 + >; + }; + pinctrl_ETH: ETH { + fh,pins = < + &mux_ETH_LINK_ACT 1 + &mux_ETH_LINK_STA 1 + >; + }; + pinctrl_I2C0: I2C0 { + fh,pins = < + &mux_I2C0_SCL 0 + &mux_I2C0_SDA 0 + >; + }; + pinctrl_I2C1: I2C1 { + fh,pins = < + &mux_I2C1_SCL 2 + &mux_I2C1_SDA 2 + >; + }; + pinctrl_I2C2: I2C2 { + fh,pins = < + &mux_I2C2_SCL 1 + &mux_I2C2_SDA 1 + >; + }; + pinctrl_PAEJTAG: PAEJTAG { + fh,pins = < + &mux_PAE_JTAG_TCK 0 + &mux_PAE_JTAG_TDI 0 + &mux_PAE_JTAG_TDO 0 + &mux_PAE_JTAG_TMS 0 + &mux_PAE_JTAG_TRSTN 0 + >; + }; + pinctrl_PWM0: PWM0 { + fh,pins = < + &mux_PWM0 0 + >; + }; + pinctrl_PWM1: PWM1 { + fh,pins = < + &mux_PWM1 0 + >; + }; + pinctrl_PWM10: PWM10 { + fh,pins = < + &mux_PWM10 0 + >; + }; + pinctrl_PWM11: PWM11 { + fh,pins = < + &mux_PWM11 0 + >; + }; + pinctrl_PWM2: PWM2 { + fh,pins = < + &mux_PWM2 0 + >; + }; + pinctrl_PWM3: PWM3 { + fh,pins = < + &mux_PWM3 0 + >; + }; + pinctrl_PWM4: PWM4 { + fh,pins = < + &mux_PWM4 0 + >; + }; + pinctrl_PWM5: PWM5 { + fh,pins = < + &mux_PWM5 0 + >; + }; + pinctrl_PWM6: PWM6 { + fh,pins = < + &mux_PWM6 1 + >; + }; + pinctrl_PWM7: PWM7 { + fh,pins = < + &mux_PWM7 1 + >; + }; + pinctrl_PWM8: PWM8 { + fh,pins = < + &mux_PWM8 1 + >; + }; + pinctrl_PWM9: PWM9 { + fh,pins = < + &mux_PWM9 1 + >; + }; + pinctrl_RMII: RMII { + fh,pins = < + &mux_MAC_MDC 1 + &mux_MAC_MDIO 1 + &mux_MAC_REF_CLK 0 + &mux_MAC_RMII_CLK 0 + &mux_MAC_RXDV 0 + &mux_MAC_RXD_0 0 + &mux_MAC_RXD_1 0 + &mux_MAC_TXD_0 0 + &mux_MAC_TXD_1 0 + &mux_MAC_TXEN 0 + >; + }; + pinctrl_RTC: RTC { + fh,pins = < + &mux_RTC_CLK 0 + >; + }; + pinctrl_SADC_XAIN0: SADC_XAIN0 { + fh,pins = < + &mux_SADC_XAIN0 0 + >; + }; + pinctrl_SADC_XAIN1: SADC_XAIN1 { + fh,pins = < + &mux_SADC_XAIN1 0 + >; + }; + pinctrl_SADC_XAIN2: SADC_XAIN2 { + fh,pins = < + &mux_SADC_XAIN2 0 + >; + }; + pinctrl_SADC_XAIN3: SADC_XAIN3 { + fh,pins = < + &mux_SADC_XAIN3 0 + >; + }; + pinctrl_SD0: SD0 { + fh,pins = < + &mux_SD0_CD 0 + &mux_SD0_CLK 0 + &mux_SD0_CMD_RSP 0 + &mux_SD0_DATA_0 0 + &mux_SD0_DATA_1 0 + &mux_SD0_DATA_2 0 + &mux_SD0_DATA_3 0 + >; + }; + pinctrl_SD0_1BIT_NO_WP: SD0_1BIT_NO_WP { + fh,pins = < + &mux_SD0_CD 0 + &mux_SD0_CLK 0 + &mux_SD0_CMD_RSP 0 + &mux_SD0_DATA_0 0 + >; + }; + pinctrl_SD0_NO_WP: SD0_NO_WP { + fh,pins = < + &mux_SD0_CD 0 + &mux_SD0_CLK 0 + &mux_SD0_CMD_RSP 0 + &mux_SD0_DATA_0 0 + &mux_SD0_DATA_1 0 + &mux_SD0_DATA_2 0 + &mux_SD0_DATA_3 0 + >; + }; + pinctrl_SD0_WIFI: SD0_WIFI { + fh,pins = < + &mux_SD0_CLK 0 + &mux_SD0_CMD_RSP 0 + &mux_SD0_DATA_0 0 + &mux_SD0_DATA_1 0 + &mux_SD0_DATA_2 0 + &mux_SD0_DATA_3 0 + >; + }; + pinctrl_SD1: SD1 { + fh,pins = < + &mux_SD1_CD 0 + &mux_SD1_CLK 0 + &mux_SD1_CMD_RSP 0 + &mux_SD1_DATA_0 0 + &mux_SD1_DATA_1 0 + &mux_SD1_DATA_2 0 + &mux_SD1_DATA_3 0 + >; + }; + pinctrl_SD1_1BIT_NO_WP: SD1_1BIT_NO_WP { + fh,pins = < + &mux_SD1_CD 0 + &mux_SD1_CLK 0 + &mux_SD1_CMD_RSP 0 + &mux_SD1_DATA_0 0 + >; + }; + pinctrl_SD1_NO_WP: SD1_NO_WP { + fh,pins = < + &mux_SD1_CD 0 + &mux_SD1_CLK 0 + &mux_SD1_CMD_RSP 0 + &mux_SD1_DATA_0 0 + &mux_SD1_DATA_1 0 + &mux_SD1_DATA_2 0 + &mux_SD1_DATA_3 0 + >; + }; + pinctrl_SD1_WIFI: SD1_WIFI { + fh,pins = < + &mux_SD1_CLK 0 + &mux_SD1_CMD_RSP 0 + &mux_SD1_DATA_0 0 + &mux_SD1_DATA_1 0 + &mux_SD1_DATA_2 0 + &mux_SD1_DATA_3 0 + >; + }; + pinctrl_SENSOR_CLK: SENSOR_CLK { + fh,pins = < + &mux_SENSOR_CLK 0 + >; + }; + pinctrl_SSI0: SSI0 { + fh,pins = < + &mux_GPIO6 0 + &mux_SSI0_CLK 0 + &mux_SSI0_RXD 0 + &mux_SSI0_TXD 0 + >; + }; + pinctrl_SSI0_4BIT: SSI0_4BIT { + fh,pins = < + &mux_GPIO6 0 + &mux_SSI0_CLK 0 + &mux_SSI0_D2 0 + &mux_SSI0_D3 0 + &mux_SSI0_RXD 0 + &mux_SSI0_TXD 0 + >; + }; + pinctrl_SSI1: SSI1 { + fh,pins = < + &mux_GPIO14 0 + &mux_SSI1_CLK 2 + &mux_SSI1_RXD 2 + &mux_SSI1_TXD 2 + >; + }; + pinctrl_SSI2: SSI2 { + fh,pins = < + &mux_SSI2_CLK 1 + &mux_SSI2_CSN_0 1 + &mux_SSI2_RXD 1 + &mux_SSI2_TXD 1 + >; + }; + pinctrl_UART0: UART0 { + fh,pins = < + &mux_UART0_RX 0 + &mux_UART0_TX 0 + >; + }; + pinctrl_UART1: UART1 { + fh,pins = < + &mux_UART1_RX 0 + &mux_UART1_TX 0 + >; + }; + pinctrl_UART2: UART2 { + fh,pins = < + &mux_UART2_RX 0 + &mux_UART2_TX 0 + >; + }; + pinctrl_USB: USB { + fh,pins = < + &mux_USB_PWREN 0 + >; + }; + pinctrl_GPIO0: GPIO0 { + fh,pins = < + &mux_GPIO0 0 + >; + }; + pinctrl_GPIO1: GPIO1 { + fh,pins = < + &mux_GPIO1 0 + >; + }; + pinctrl_GPIO2: GPIO2 { + fh,pins = < + &mux_GPIO2 0 + >; + }; + pinctrl_GPIO3: GPIO3 { + fh,pins = < + &mux_GPIO3 0 + >; + }; + pinctrl_GPIO4: GPIO4 { + fh,pins = < + &mux_GPIO4 0 + >; + }; + pinctrl_GPIO5: GPIO5 { + fh,pins = < + &mux_GPIO5 0 + >; + }; + pinctrl_GPIO6: GPIO6 { + fh,pins = < + &mux_GPIO6 0 + >; + }; + pinctrl_GPIO7: GPIO7 { + fh,pins = < + &mux_GPIO7 0 + >; + }; + pinctrl_GPIO8: GPIO8 { + fh,pins = < + &mux_GPIO8 0 + >; + }; + pinctrl_GPIO9: GPIO9 { + fh,pins = < + &mux_GPIO9 0 + >; + }; + pinctrl_GPIO10: GPIO10 { + fh,pins = < + &mux_GPIO10 0 + >; + }; + pinctrl_GPIO11: GPIO11 { + fh,pins = < + &mux_GPIO11 0 + >; + }; + pinctrl_GPIO12: GPIO12 { + fh,pins = < + &mux_GPIO12 0 + >; + }; + pinctrl_GPIO13: GPIO13 { + fh,pins = < + &mux_GPIO13 0 + >; + }; + pinctrl_GPIO14: GPIO14 { + fh,pins = < + &mux_GPIO14 0 + >; + }; + pinctrl_GPIO15: GPIO15 { + fh,pins = < + &mux_GPIO15 0 + >; + }; + pinctrl_GPIO16: GPIO16 { + fh,pins = < + &mux_GPIO16 0 + >; + }; + pinctrl_GPIO17: GPIO17 { + fh,pins = < + &mux_GPIO17 0 + >; + }; + pinctrl_GPIO18: GPIO18 { + fh,pins = < + &mux_GPIO18 0 + >; + }; + pinctrl_GPIO19: GPIO19 { + fh,pins = < + &mux_GPIO19 0 + >; + }; + pinctrl_GPIO20: GPIO20 { + fh,pins = < + &mux_GPIO20 0 + >; + }; + pinctrl_GPIO21: GPIO21 { + fh,pins = < + &mux_GPIO21 0 + >; + }; + pinctrl_GPIO22: GPIO22 { + fh,pins = < + &mux_GPIO22 0 + >; + }; + pinctrl_GPIO23: GPIO23 { + fh,pins = < + &mux_GPIO23 0 + >; + }; + pinctrl_GPIO24: GPIO24 { + fh,pins = < + &mux_GPIO24 0 + >; + }; + pinctrl_GPIO25: GPIO25 { + fh,pins = < + &mux_GPIO25 0 + >; + }; + pinctrl_GPIO26: GPIO26 { + fh,pins = < + &mux_GPIO26 0 + >; + }; + pinctrl_GPIO27: GPIO27 { + fh,pins = < + &mux_GPIO27 0 + >; + }; + pinctrl_GPIO28: GPIO28 { + fh,pins = < + &mux_GPIO28 0 + >; + }; + pinctrl_GPIO29: GPIO29 { + fh,pins = < + &mux_GPIO29 0 + >; + }; + pinctrl_GPIO30: GPIO30 { + fh,pins = < + &mux_GPIO30 0 + >; + }; + pinctrl_GPIO31: GPIO31 { + fh,pins = < + &mux_GPIO31 0 + >; + }; + pinctrl_GPIO32: GPIO32 { + fh,pins = < + &mux_GPIO32 0 + >; + }; + pinctrl_GPIO33: GPIO33 { + fh,pins = < + &mux_GPIO33 0 + >; + }; + pinctrl_GPIO34: GPIO34 { + fh,pins = < + &mux_GPIO34 0 + >; + }; + pinctrl_GPIO35: GPIO35 { + fh,pins = < + &mux_GPIO35 0 + >; + }; + pinctrl_GPIO36: GPIO36 { + fh,pins = < + &mux_GPIO36 0 + >; + }; + pinctrl_GPIO37: GPIO37 { + fh,pins = < + &mux_GPIO37 0 + >; + }; + pinctrl_GPIO38: GPIO38 { + fh,pins = < + &mux_GPIO38 0 + >; + }; + pinctrl_GPIO39: GPIO39 { + fh,pins = < + &mux_GPIO39 0 + >; + }; + pinctrl_GPIO40: GPIO40 { + fh,pins = < + &mux_GPIO40 0 + >; + }; + pinctrl_GPIO41: GPIO41 { + fh,pins = < + &mux_GPIO41 0 + >; + }; + pinctrl_GPIO42: GPIO42 { + fh,pins = < + &mux_GPIO42 0 + >; + }; + pinctrl_GPIO43: GPIO43 { + fh,pins = < + &mux_GPIO43 0 + >; + }; + pinctrl_GPIO44: GPIO44 { + fh,pins = < + &mux_GPIO44 0 + >; + }; + pinctrl_GPIO45: GPIO45 { + fh,pins = < + &mux_GPIO45 0 + >; + }; + pinctrl_GPIO46: GPIO46 { + fh,pins = < + &mux_GPIO46 0 + >; + }; + pinctrl_GPIO47: GPIO47 { + fh,pins = < + &mux_GPIO47 0 + >; + }; + pinctrl_GPIO48: GPIO48 { + fh,pins = < + &mux_GPIO48 0 + >; + }; + pinctrl_GPIO49: GPIO49 { + fh,pins = < + &mux_GPIO49 0 + >; + }; + pinctrl_GPIO50: GPIO50 { + fh,pins = < + &mux_GPIO50 0 + >; + }; + pinctrl_GPIO51: GPIO51 { + fh,pins = < + &mux_GPIO51 0 + >; + }; + pinctrl_GPIO52: GPIO52 { + fh,pins = < + &mux_GPIO52 0 + >; + }; + pinctrl_GPIO53: GPIO53 { + fh,pins = < + &mux_GPIO53 0 + >; + }; + pinctrl_GPIO54: GPIO54 { + fh,pins = < + &mux_GPIO54 0 + >; + }; + pinctrl_GPIO55: GPIO55 { + fh,pins = < + &mux_GPIO55 0 + >; + }; + pinctrl_GPIO56: GPIO56 { + fh,pins = < + &mux_GPIO56 0 + >; + }; + pinctrl_GPIO57: GPIO57 { + fh,pins = < + &mux_GPIO57 0 + >; + }; + pinctrl_GPIO58: GPIO58 { + fh,pins = < + &mux_GPIO58 0 + >; + }; + pinctrl_GPIO59: GPIO59 { + fh,pins = < + &mux_GPIO59 0 + >; + }; + pinctrl_GPIO60: GPIO60 { + fh,pins = < + &mux_GPIO60 0 + >; + }; + pinctrl_GPIO61: GPIO61 { + fh,pins = < + &mux_GPIO61 0 + >; + }; + pinctrl_GPIO62: GPIO62 { + fh,pins = < + &mux_GPIO62 0 + >; + }; + pinctrl_GPIO63: GPIO63 { + fh,pins = < + &mux_GPIO63 0 + >; + }; + pinctrl_SD1_EMMC: SD1_EMMC { + fh,pins = < + &mux_SD1_CD 3 + &mux_SD1_CLK 3 + &mux_SD1_CMD_RSP 3 + &mux_SD1_DATA_0 3 + &mux_SD1_DATA_1 3 + &mux_SD1_DATA_2 3 + &mux_SD1_DATA_3 3 + >; + }; + }; + pinmux: pinmux { + compatible = "fh,fh-pinmux"; + #list-cells = <1>; + mux_AC_I2S_CLK: AC_I2S_CLK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad39 + >; + }; + mux_AC_I2S_DI: AC_I2S_DI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad38 + >; + }; + mux_AC_I2S_DO: AC_I2S_DO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad37 + >; + }; + mux_AC_I2S_WS: AC_I2S_WS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad40 + >; + }; + mux_AC_MCLK: AC_MCLK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad41 + >; + }; + + mux_ARC_JTAG_TCK: ARC_JTAG_TCK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad55 + >; + }; + mux_ARC_JTAG_TDI: ARC_JTAG_TDI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad54 + >; + }; + mux_ARC_JTAG_TDO: ARC_JTAG_TDO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad53 + >; + }; + mux_ARC_JTAG_TMS: ARC_JTAG_TMS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad56 + >; + }; + mux_ARC_JTAG_TRSTN: ARC_JTAG_TRSTN { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad52 + >; + }; + + mux_ARM_JTAG_TCK: ARM_JTAG_TCK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad40 + >; + }; + mux_ARM_JTAG_TDI: ARM_JTAG_TDI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad39 + >; + }; + mux_ARM_JTAG_TDO: ARM_JTAG_TDO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad38 + >; + }; + mux_ARM_JTAG_TMS: ARM_JTAG_TMS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad41 + >; + }; + mux_ARM_JTAG_TRSTN: ARM_JTAG_TRSTN { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad37 + >; + }; + + mux_DW_I2S_CLK: DW_I2S_CLK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad39 + >; + }; + mux_DW_I2S_DI: DW_I2S_DI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad38 + >; + }; + mux_DW_I2S_DO: DW_I2S_DO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad37 + >; + }; + mux_DW_I2S_WS: DW_I2S_WS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad40 + >; + }; + + mux_ETH_LINK_ACT: ETH_LINK_ACT { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad1 + &pad63 + >; + }; + mux_ETH_LINK_SPD: ETH_LINK_SPD { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad2 + &pad64 + >; + }; + mux_ETH_LINK_STA: ETH_LINK_STA { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad2 + &pad64 + >; + }; + + mux_I2C0_SCL: I2C0_SCL { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad5 + >; + }; + mux_I2C0_SDA: I2C0_SDA { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad6 + >; + }; + + mux_I2C1_SCL: I2C1_SCL { + #list-cells = <1>; + select = <2>; + fh,pads = < + &pad11 + &pad30 + &pad46 + >; + }; + mux_I2C1_SDA: I2C1_SDA { + #list-cells = <1>; + select = <2>; + fh,pads = < + &pad12 + &pad31 + &pad47 + >; + }; + + mux_I2C2_SCL: I2C2_SCL { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad16 + &pad57 + >; + }; + mux_I2C2_SDA: I2C2_SDA { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad17 + &pad58 + >; + }; + + mux_MAC_MDC: MAC_MDC { + #list-cells = <1>; + select = <1>; + ds = <0>; + fh,pads = < + &pad28 + &pad63 + >; + }; + mux_MAC_MDIO: MAC_MDIO { + #list-cells = <1>; + select = <1>; + ds = <0>; + fh,pads = < + &pad29 + &pad64 + >; + }; + mux_MAC_REF_CLK: MAC_REF_CLK { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad21 + >; + }; + mux_MAC_RMII_CLK: MAC_RMII_CLK { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad20 + >; + }; + mux_MAC_RXDV: MAC_RXDV { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad27 + >; + }; + mux_MAC_RXD_0: MAC_RXD_0 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad25 + >; + }; + mux_MAC_RXD_1: MAC_RXD_1 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad26 + >; + }; + mux_MAC_TXD_0: MAC_TXD_0 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad22 + >; + }; + mux_MAC_TXD_1: MAC_TXD_1 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad23 + >; + }; + mux_MAC_TXEN: MAC_TXEN { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad24 + >; + }; + + mux_PAE_JTAG_TCK: PAE_JTAG_TCK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad55 + >; + }; + mux_PAE_JTAG_TDI: PAE_JTAG_TDI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad54 + >; + }; + mux_PAE_JTAG_TDO: PAE_JTAG_TDO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad53 + >; + }; + mux_PAE_JTAG_TMS: PAE_JTAG_TMS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad56 + >; + }; + mux_PAE_JTAG_TRSTN: PAE_JTAG_TRSTN { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad52 + >; + }; + + mux_PWM0: PWM0 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad16 + >; + }; + mux_PWM1: PWM1 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad17 + >; + }; + mux_PWM10: PWM10 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad63 + >; + }; + mux_PWM11: PWM11 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad64 + >; + }; + mux_PWM2: PWM2 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad11 + &pad18 + &pad20 + >; + }; + mux_PWM3: PWM3 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad12 + &pad19 + &pad22 + >; + }; + mux_PWM4: PWM4 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad13 + &pad23 + >; + }; + mux_PWM5: PWM5 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad14 + &pad24 + >; + }; + mux_PWM6: PWM6 { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad25 + &pad37 + >; + }; + mux_PWM7: PWM7 { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad26 + &pad38 + >; + }; + mux_PWM8: PWM8 { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad27 + &pad39 + >; + }; + mux_PWM9: PWM9 { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad28 + &pad40 + >; + }; + + mux_RTC_CLK: RTC_CLK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad64 + >; + }; + + mux_SADC_XAIN0: SADC_XAIN0 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad59 + >; + }; + mux_SADC_XAIN1: SADC_XAIN1 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad60 + >; + }; + mux_SADC_XAIN2: SADC_XAIN2 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad61 + >; + }; + mux_SADC_XAIN3: SADC_XAIN3 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad62 + >; + }; + + mux_SD0_CD: SD0_CD { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad52 + >; + }; + mux_SD0_CLK: SD0_CLK { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad53 + >; + }; + mux_SD0_CMD_RSP: SD0_CMD_RSP { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad54 + >; + }; + mux_SD0_DATA_0: SD0_DATA_0 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad55 + >; + }; + mux_SD0_DATA_1: SD0_DATA_1 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad56 + >; + }; + mux_SD0_DATA_2: SD0_DATA_2 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad57 + >; + }; + mux_SD0_DATA_3: SD0_DATA_3 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad58 + >; + }; + + mux_SD1_CD: SD1_CD { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad10 + &pad22 + &pad31 + &pad41 + &pad63 + >; + }; + mux_SD1_CLK: SD1_CLK { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad9 + &pad20 + &pad30 + &pad42 + >; + }; + mux_SD1_CMD_RSP: SD1_CMD_RSP { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad11 + &pad23 + &pad32 + &pad43 + >; + }; + mux_SD1_DATA_0: SD1_DATA_0 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad12 + &pad24 + &pad33 + &pad44 + >; + }; + mux_SD1_DATA_1: SD1_DATA_1 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad13 + &pad25 + &pad34 + &pad45 + >; + }; + mux_SD1_DATA_2: SD1_DATA_2 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad14 + &pad26 + &pad35 + &pad46 + >; + }; + mux_SD1_DATA_3: SD1_DATA_3 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad15 + &pad27 + &pad36 + &pad47 + >; + }; + + mux_SENSOR_CLK: SENSOR_CLK { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad7 + >; + }; + + mux_SSI0_CLK: SSI0_CLK { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad42 + >; + }; + mux_SSI0_D2: SSI0_D2 { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad46 + >; + }; + mux_SSI0_D3: SSI0_D3 { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad47 + >; + }; + mux_SSI0_RXD: SSI0_RXD { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad45 + >; + }; + mux_SSI0_TXD: SSI0_TXD { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad44 + >; + }; + + mux_SSI1_CLK: SSI1_CLK { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad11 + &pad37 + &pad48 + &pad53 + >; + }; + mux_SSI1_RXD: SSI1_RXD { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad14 + &pad40 + &pad51 + &pad55 + >; + }; + mux_SSI1_TXD: SSI1_TXD { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad13 + &pad39 + &pad50 + &pad54 + >; + }; + + mux_SSI2_CLK: SSI2_CLK { + #list-cells = <1>; + select = <1>; + ds = <2>; + fh,pads = < + &pad37 + &pad48 + >; + }; + mux_SSI2_CSN_0: SSI2_CSN_0 { + #list-cells = <1>; + select = <1>; + ds = <2>; + fh,pads = < + &pad38 + &pad49 + >; + }; + mux_SSI2_RXD: SSI2_RXD { + #list-cells = <1>; + select = <1>; + ds = <2>; + fh,pads = < + &pad40 + &pad51 + >; + }; + mux_SSI2_TXD: SSI2_TXD { + #list-cells = <1>; + select = <1>; + ds = <2>; + fh,pads = < + &pad39 + &pad50 + >; + }; + + mux_UART0_RX: UART0_RX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad4 + >; + }; + mux_UART0_TX: UART0_TX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad3 + >; + }; + + mux_UART1_RX: UART1_RX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad10 + &pad33 + &pad47 + >; + }; + mux_UART1_TX: UART1_TX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad9 + &pad32 + &pad46 + >; + }; + + mux_UART2_RX: UART2_RX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad14 + &pad17 + &pad35 + &pad58 + >; + }; + mux_UART2_TX: UART2_TX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad13 + &pad16 + &pad34 + &pad57 + >; + }; + + mux_USB_PWREN: USB_PWREN { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad15 + &pad41 + >; + }; + + mux_GPIO0: GPIO0 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad37 + >; + }; + mux_GPIO1: GPIO1 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad38 + >; + }; + mux_GPIO2: GPIO2 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad39 + >; + }; + mux_GPIO3: GPIO3 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad40 + >; + }; + mux_GPIO4: GPIO4 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad41 + >; + }; + mux_GPIO5: GPIO5 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad42 + >; + }; + mux_GPIO6: GPIO6 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad43 + >; + }; + mux_GPIO7: GPIO7 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad44 + >; + }; + mux_GPIO8: GPIO8 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad45 + >; + }; + mux_GPIO9: GPIO9 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad46 + >; + }; + mux_GPIO10: GPIO10 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad47 + >; + }; + mux_GPIO11: GPIO11 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad48 + >; + }; + mux_GPIO12: GPIO12 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad7 + >; + }; + mux_GPIO13: GPIO13 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad8 + >; + }; + mux_GPIO14: GPIO14 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad49 + >; + }; + mux_GPIO15: GPIO15 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad50 + >; + }; + mux_GPIO16: GPIO16 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad51 + >; + }; + mux_GPIO17: GPIO17 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad52 + >; + }; + mux_GPIO18: GPIO18 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad53 + >; + }; + mux_GPIO19: GPIO19 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad54 + >; + }; + mux_GPIO20: GPIO20 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad55 + >; + }; + mux_GPIO21: GPIO21 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad56 + >; + }; + mux_GPIO22: GPIO22 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad57 + >; + }; + mux_GPIO23: GPIO23 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad58 + >; + }; + mux_GPIO24: GPIO24 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad61 + >; + }; + mux_GPIO25: GPIO25 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad62 + >; + }; + mux_GPIO26: GPIO26 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad59 + >; + }; + mux_GPIO27: GPIO27 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad60 + >; + }; + mux_GPIO28: GPIO28 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad63 + >; + }; + mux_GPIO29: GPIO29 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad64 + >; + }; + mux_GPIO30: GPIO30 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad0 + >; + }; + mux_GPIO31: GPIO31 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad1 + >; + }; + mux_GPIO32: GPIO32 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad2 + >; + }; + mux_GPIO33: GPIO33 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad3 + >; + }; + mux_GPIO34: GPIO34 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad4 + >; + }; + mux_GPIO35: GPIO35 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad5 + >; + }; + mux_GPIO36: GPIO36 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad6 + >; + }; + mux_GPIO37: GPIO37 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad11 + >; + }; + mux_GPIO38: GPIO38 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad12 + >; + }; + mux_GPIO39: GPIO39 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad9 + >; + }; + mux_GPIO40: GPIO40 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad10 + >; + }; + mux_GPIO41: GPIO41 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad13 + >; + }; + mux_GPIO42: GPIO42 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad14 + >; + }; + mux_GPIO43: GPIO43 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad16 + >; + }; + mux_GPIO44: GPIO44 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad17 + >; + }; + mux_GPIO45: GPIO45 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad18 + >; + }; + mux_GPIO46: GPIO46 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad19 + >; + }; + mux_GPIO47: GPIO47 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad15 + >; + }; + mux_GPIO48: GPIO48 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad20 + >; + }; + mux_GPIO49: GPIO49 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad22 + >; + }; + mux_GPIO50: GPIO50 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad23 + >; + }; + mux_GPIO51: GPIO51 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad24 + >; + }; + mux_GPIO52: GPIO52 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad25 + >; + }; + mux_GPIO53: GPIO53 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad26 + >; + }; + mux_GPIO54: GPIO54 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad27 + >; + }; + mux_GPIO55: GPIO55 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad28 + >; + }; + mux_GPIO56: GPIO56 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad29 + >; + }; + mux_GPIO57: GPIO57 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad30 + >; + }; + mux_GPIO58: GPIO58 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad31 + >; + }; + mux_GPIO59: GPIO59 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad32 + >; + }; + mux_GPIO60: GPIO60 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad33 + >; + }; + mux_GPIO61: GPIO61 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad34 + >; + }; + mux_GPIO62: GPIO62 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad35 + >; + }; + mux_GPIO63: GPIO63 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad36 + >; + }; + }; + pinpad: pinpad { + compatible = "fh,fh-pinpad"; + pad0: PAD_BOOT_MODE_CFG { + index = <0>; + funcs = "GPIO30"; + pupd = <1>; + ds = <0>; + }; + pad1: PAD_BOOT_SEL1_CFG { + index = <1>; + funcs = "GPIO31", "ETH_LINK_ACT"; + pupd = <1>; + ds = <0>; + }; + pad2: PAD_BOOT_SEL0_CFG { + index = <2>; + funcs = "GPIO32", "ETH_LINK_STA", "ETH_LINK_SPD"; + pupd = <1>; + ds = <0>; + }; + pad3: PAD_UART0_TX_CFG { + index = <3>; + funcs = "UART0_TX", "GPIO33"; + pupd = <0>; + ds = <0>; + }; + pad4: PAD_UART0_RX_CFG { + index = <4>; + funcs = "UART0_RX", "GPIO34"; + pupd = <0>; + ds = <0>; + }; + pad5: PAD_I2C0_SCL_CFG { + index = <5>; + funcs = "I2C0_SCL", "GPIO35"; + pupd = <1>; + ds = <0>; + }; + pad6: PAD_I2C0_SDA_CFG { + index = <6>; + funcs = "I2C0_SDA", "GPIO36"; + pupd = <1>; + ds = <0>; + }; + pad7: PAD_SENSOR_CLK_CFG { + index = <7>; + funcs = "SENSOR_CLK", "GPIO12"; + pupd = <0>; + ds = <0>; + }; + pad8: PAD_SENSOR_RSTN_CFG { + index = <8>; + funcs = "GPIO13"; + pupd = <0>; + ds = <0>; + }; + pad9: PAD_UART1_TX_CFG { + index = <9>; + funcs = "UART1_TX", "GPIO39", "", "SD1_CLK", "", "", + "TEST_O_INT_RMII_CLK"; + pupd = <0>; + ds = <0>; + }; + pad10: PAD_UART1_RX_CFG { + index = <10>; + funcs = "UART1_RX", "GPIO40", "", "SD1_CD", "", "", + "TEST_INT_RMII_TXD_0"; + pupd = <0>; + ds = <0>; + }; + pad11: PAD_I2C1_SCL_CFG { + index = <11>; + funcs = "I2C1_SCL", "GPIO37", "PWM2", "SD1_CMD_RSP", "", + "SSI1_CLK", "TEST_INT_RMII_TXD_1"; + pupd = <0>; + ds = <0>; + }; + pad12: PAD_I2C1_SDA_CFG { + index = <12>; + funcs = "I2C1_SDA", "GPIO38", "PWM3", "SD1_DATA_0", "", + "SSI1_CSN_0", "TEST_INT_RMII_TXEN"; + pupd = <0>; + ds = <0>; + }; + pad13: PAD_UART2_TX_CFG { + index = <13>; + funcs = "UART2_TX", "GPIO41", "PWM4", "SD1_DATA_1", "", + "SSI1_TXD", "TEST_O_INT_RMII_RXD_0"; + pupd = <0>; + ds = <0>; + }; + pad14: PAD_UART2_RX_CFG { + index = <14>; + funcs = "UART2_RX", "GPIO42", "PWM5", "SD1_DATA_2", "", + "SSI1_RXD", "TEST_O_INT_RMII_RXD_1"; + pupd = <0>; + ds = <0>; + }; + pad15: PAD_USB_PWREN_CFG { + index = <15>; + funcs = "USB_PWREN", "GPIO47", "", "SD1_DATA_3", "", "", + "TEST_O_INT_RMII_CRSDV"; + pupd = <0>; + ds = <0>; + }; + pad16: PAD_PWM0_CFG { + index = <16>; + funcs = "PWM0", "GPIO43", "I2C2_SCL", "UART2_TX", "", "", + "TEST_O_INT_RMII_TXD_0"; + pupd = <0>; + ds = <0>; + }; + pad17: PAD_PWM1_CFG { + index = <17>; + funcs = "PWM1", "GPIO44", "I2C2_SDA", "UART2_RX", "", "", + "TEST_O_INT_RMII_TXD_1"; + pupd = <0>; + ds = <0>; + }; + pad18: PAD_PWM2_CFG { + index = <18>; + funcs = "PWM2", "GPIO45"; + pupd = <0>; + ds = <0>; + }; + pad19: PAD_PWM3_CFG { + index = <19>; + funcs = "PWM3", "GPIO46"; + pupd = <0>; + ds = <0>; + }; + pad20: PAD_MAC_RMII_CLK_CFG { + index = <20>; + funcs = "MAC_RMII_CLK", "GPIO48", "SD1_CLK", "PWM2"; + pupd = <0>; + ds = <0>; + }; + pad21: PAD_MAC_REF_CLK_CFG { + index = <21>; + funcs = "MAC_REF_CLK"; + pupd = <0>; + ds = <2>; + }; + pad22: PAD_MAC_TXD0_CFG { + index = <22>; + funcs = "MAC_TXD_0", "GPIO49", "SD1_CD", "PWM3"; + pupd = <0>; + ds = <0>; + }; + pad23: PAD_MAC_TXD1_CFG { + index = <23>; + funcs = "MAC_TXD_1", "GPIO50", "SD1_CMD_RSP", "PWM4"; + pupd = <0>; + ds = <0>; + }; + pad24: PAD_MAC_TXEN_CFG { + index = <24>; + funcs = "MAC_TXEN", "GPIO51", "SD1_DATA_0", "PWM5"; + pupd = <0>; + ds = <0>; + }; + pad25: PAD_MAC_RXD0_CFG { + index = <25>; + funcs = "MAC_RXD_0", "GPIO52", "SD1_DATA_1", "PWM6"; + pupd = <0>; + ds = <0>; + }; + pad26: PAD_MAC_RXD1_CFG { + index = <26>; + funcs = "MAC_RXD_1", "GPIO53", "SD1_DATA_2", "PWM7"; + pupd = <0>; + ds = <0>; + }; + pad27: PAD_MAC_RXDV_CFG { + index = <27>; + funcs = "MAC_RXDV", "GPIO54", "SD1_DATA_3", "PWM8"; + pupd = <0>; + ds = <0>; + }; + pad28: PAD_MAC_MDC_CFG { + index = <28>; + funcs = "MAC_MDC", "GPIO55", "", "PWM9"; + pupd = <0>; + ds = <0>; + }; + pad29: PAD_MAC_MDIO_CFG { + index = <29>; + funcs = "MAC_MDIO", "GPIO56"; + pupd = <0>; + ds = <0>; + }; + pad30: PAD_SD1_CLK_CFG { + index = <30>; + funcs = "SD1_CLK", "GPIO57", "I2C1_SCL"; + pupd = <0>; + ds = <0>; + }; + pad31: PAD_SD1_CD_CFG { + index = <31>; + funcs = "SD1_CD", "GPIO58", "I2C1_SDA"; + pupd = <0>; + ds = <0>; + }; + pad32: PAD_SD1_CMD_RSP_CFG { + index = <32>; + funcs = "SD1_CMD_RSP", "GPIO59", "UART1_TX"; + pupd = <0>; + ds = <0>; + }; + pad33: PAD_SD1_DATA_0_CFG { + index = <33>; + funcs = "SD1_DATA_0", "GPIO60", "UART1_RX"; + pupd = <0>; + ds = <0>; + }; + pad34: PAD_SD1_DATA_1_CFG { + index = <34>; + funcs = "SD1_DATA_1", "GPIO61", "UART2_TX"; + pupd = <0>; + ds = <0>; + }; + pad35: PAD_SD1_DATA_2_CFG { + index = <35>; + funcs = "SD1_DATA_2", "GPIO62", "UART2_RX"; + pupd = <0>; + ds = <0>; + }; + pad36: PAD_SD1_DATA_3_CFG { + index = <36>; + funcs = "SD1_DATA_3", "GPIO63"; + pupd = <0>; + ds = <0>; + }; + pad37: PAD_GPIO_0_CFG { + index = <37>; + funcs = "ARM_JTAG_TRSTN", "GPIO0", "AC_I2S_DO", "DW_I2S_DO", + "SSI1_CLK", "SSI2_CLK", "ACIP_ADDAT", "PWM6", + "TEST_O_INT_SMI_MDC"; + pupd = <0>; + ds = <0>; + }; + pad38: PAD_GPIO_1_CFG { + index = <38>; + funcs = "ARM_JTAG_TDO", "GPIO1", "AC_I2S_DI", "DW_I2S_DI", + "SSI1_CSN_0", "SSI2_CSN_0", "ACIP_DADAT", "PWM7", + "TEST_O_INT_SMI_MDIO_I"; + pupd = <0>; + ds = <0>; + }; + pad39: PAD_GPIO_2_CFG { + index = <39>; + funcs = "ARM_JTAG_TDI", "GPIO2", "AC_I2S_CLK", "DW_I2S_CLK", + "SSI1_TXD", "SSI2_TXD", "ACIP_ADBCLK", "PWM8", + "TEST_O_INT_SMI_MDIO_O"; + pupd = <0>; + ds = <0>; + }; + pad40: PAD_GPIO_3_CFG { + index = <40>; + funcs = "ARM_JTAG_TCK", "GPIO3", "AC_I2S_WS", "DW_I2S_WS", + "SSI1_RXD", "SSI2_RXD", "ACIP_ADLRC", "PWM9", + "TEST_I_INT_SMI_MDIO_I"; + pupd = <0>; + ds = <0>; + }; + pad41: PAD_GPIO_4_CFG { + index = <41>; + funcs = "ARM_JTAG_TMS", "GPIO4", "AC_MCLK", "USB_PWREN", + "SD1_CD", "TEST_I_INT_SMI_MDC"; + pupd = <0>; + ds = <0>; + }; + pad42: PAD_SSI0_CLK_CFG { + index = <42>; + funcs = "SSI0_CLK", "GPIO5", "", "", "SD1_CLK"; + pupd = <0>; + ds = <2>; + }; + pad43: PAD_SSI0_CSN_0_CFG { + index = <43>; + funcs = "SSI0_CSN_0", "GPIO6", "", "", "SD1_CMD_RSP"; + pupd = <0>; + ds = <2>; + }; + pad44: PAD_SSI0_TXD_CFG { + index = <44>; + funcs = "SSI0_TXD", "GPIO7", "", "", "SD1_DATA_0"; + pupd = <0>; + ds = <2>; + }; + pad45: PAD_SSI0_RXD_CFG { + index = <45>; + funcs = "SSI0_RXD", "GPIO8", "", "", "SD1_DATA_1"; + pupd = <0>; + ds = <2>; + }; + pad46: PAD_SSI0_D2_CFG { + index = <46>; + funcs = "SSI0_D2", "GPIO9", "UART1_TX", "I2C1_SCL", + "SD1_DATA_2"; + pupd = <0>; + ds = <2>; + }; + pad47: PAD_SSI0_D3_CFG { + index = <47>; + funcs = "SSI0_D3", "GPIO10", "UART1_RX", "I2C1_SDA", + "SD1_DATA_3"; + pupd = <0>; + ds = <2>; + }; + pad48: PAD_SSI1_CLK_CFG { + index = <48>; + funcs = "SSI1_CLK", "GPIO11", "SSI2_CLK"; + pupd = <0>; + ds = <0>; + }; + pad49: PAD_SSI1_CSN_0_CFG { + index = <49>; + funcs = "SSI1_CSN_0", "GPIO14", "SSI2_CSN_0"; + pupd = <0>; + ds = <0>; + }; + pad50: PAD_SSI1_TXD_CFG { + index = <50>; + funcs = "SSI1_TXD", "GPIO15", "SSI2_TXD"; + pupd = <0>; + ds = <0>; + }; + pad51: PAD_SSI1_RXD_CFG { + index = <51>; + funcs = "SSI1_RXD", "GPIO16", "SSI2_RXD"; + pupd = <0>; + ds = <0>; + }; + pad52: PAD_SD0_CD_CFG { + index = <52>; + funcs = "SD0_CD", "GPIO17", "", "ARC_JTAG_TRSTN", + "PAE_JTAG_TRSTN"; + pupd = <0>; + ds = <0>; + }; + pad53: PAD_SD0_CLK_CFG { + index = <53>; + funcs = "SD0_CLK", "GPIO18", "SSI1_CLK", "ARC_JTAG_TDO", + "PAE_JTAG_TDO"; + pupd = <0>; + ds = <2>; + }; + pad54: PAD_SD0_CMD_RSP_CFG { + index = <54>; + funcs = "SD0_CMD_RSP", "GPIO19", "SSI1_TXD", "ARC_JTAG_TDI", + "PAE_JTAG_TDI"; + pupd = <0>; + ds = <2>; + }; + pad55: PAD_SD0_DATA_0_CFG { + index = <55>; + funcs = "SD0_DATA_0", "GPIO20", "SSI1_RXD", "ARC_JTAG_TCK", + "PAE_JTAG_TCK"; + pupd = <0>; + ds = <2>; + }; + pad56: PAD_SD0_DATA_1_CFG { + index = <56>; + funcs = "SD0_DATA_1", "GPIO21", "SSI1_CSN_0", "ARC_JTAG_TMS", + "PAE_JTAG_TMS"; + pupd = <0>; + ds = <2>; + }; + pad57: PAD_SD0_DATA_2_CFG { + index = <57>; + funcs = "SD0_DATA_2", "GPIO22", "", "UART2_TX", "I2C2_SCL", "", + "ACIP_DABCLK"; + pupd = <0>; + ds = <2>; + }; + pad58: PAD_SD0_DATA_3_CFG { + index = <58>; + funcs = "SD0_DATA_3", "GPIO23", "SSI1_CSN_0", "UART2_RX", + "I2C2_SDA", "", "ACIP_DALRC"; + pupd = <0>; + ds = <2>; + }; + pad59: PAD_SADC_XAIN0_CFG { + index = <59>; + funcs = "SADC_XAIN0", "GPIO26"; + pupd = <0>; + ds = <0>; + }; + pad60: PAD_SADC_XAIN1_CFG { + index = <60>; + funcs = "SADC_XAIN1", "GPIO27"; + pupd = <0>; + ds = <0>; + }; + pad61: PAD_SADC_XAIN2_CFG { + index = <61>; + funcs = "SADC_XAIN2", "GPIO24"; + pupd = <0>; + ds = <0>; + }; + pad62: PAD_SADC_XAIN3_CFG { + index = <62>; + funcs = "SADC_XAIN3", "GPIO25"; + pupd = <0>; + ds = <0>; + }; + pad63: PAD_GPIO_28_CFG { + index = <63>; + funcs = "GPIO28", "", "ETH_LINK_ACT", "PWM10", + "USB_DBG_CLK", "SD1_CD", "TEST_O_INT_RMII_TXEN", + "MAC_MDC"; + pupd = <0>; + ds = <0>; + }; + pad64: PAD_GPIO_29_CFG { + index = <64>; + funcs = "GPIO29", "", "ETH_LINK_STA", "PWM11", "RTC_CLK", + "ETH_LINK_SPD", "TEST_O_INT_SMI_MDIO_OE", + "MAC_MDIO"; + pupd = <0>; + ds = <0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/fh8856v210.dts b/arch/arm/boot/dts/fh8856v210.dts new file mode 100644 index 00000000..f9ebb035 --- /dev/null +++ b/arch/arm/boot/dts/fh8856v210.dts @@ -0,0 +1,956 @@ +/* + * Copyright (C) 2017 Fullhan Micorelectonics Co.,Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "skeleton.dtsi" +/include/ "fh8856v210_pinctrl.dtsi" +/ { + + + model = "FULLHAN FH8856V210"; + compatible = "fh,fh8856v210"; + interrupt-parent = <&intc>; + aliases { + i2c0 = &i2cbus0; + i2c1 = &i2cbus1; + i2c2 = &i2cbus2; + spi0 = &spi_bus0; + spi1 = &spi_bus1; + ttyS0 = &serial0; + ttyS1 = &serial1; + ttyS2 = &serial2; + }; + + cpus { + cpu@0 { + device_type = "cpu"; + compatible = "arm,arm1176jzf-s"; + }; + }; + + chosen { + bootargs = "coherent_pool=2M"; + }; + + intc: interrupt-controller@E0200000 { + compatible = "fh,fh-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xE0200000 0x1000>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pmu@f0000000 { + compatible = "fh,fh-pmu"; + reg = <0xf0000000 0x2100>; + SWRST_MAIN_CTRL = <0x40>; + }; + timer0: timer@f0c00000 { + compatible = "fh,fh-timer"; + interrupts = <3>; + clock-frequency = <1000000>; + reg = <0xf0c00000 0x14>; + }; + + timer1: timer@f0c00014 { + compatible = "fh,fh-timer"; + interrupts = <3>; + clock-frequency = <1000000>; + reg = <0xf0c00014 0x14>; + }; + + gpio0: gpio@f0300000 { + compatible = "fh,fh-gpio"; + reg = <0xf0300000 0x1000>; + #gpio_controller; + interrupt-controller; + interrupt-parent = <&intc>; + interrupts = <26>; + id = <0>; + ngpio = <32>; + base = <0>; + }; + + gpio1: gpio@f4000000 { + compatible = "fh,fh-gpio"; + reg = <0xf4000000 0x1000>; + #gpio_controller; + interrupt-controller; + interrupt-parent = <&intc>; + interrupts = <40>; + id = <1>; + ngpio = <32>; + base = <32>; + }; + + fhdma0: dma@e0300000 { + compatible = "fh,fh-axi-dmac"; + reg = <0xe0300000 0x1000>; + interrupts = <23>; + chan_allocation_order = <0>; + chan_priority = <1>; + block_size = <0x800>; + data_width = <2 0 0 0>; + clocks = <&ahb_clk>; + }; + + aes: aes@0xe8200000 { + compatible = "fh,fh-aes"; + reg = <0xe8200000 0x1000>; + interrupts = <16>; + }; + rtc: rtc@f1500000 { + compatible = "fh,fh_rtc"; + reg = <0xf1500000 0x1000>; + interrupts = <33>; + clocks = <&rtc_hclk_gate>; + lut_cof = <71>; + lut_offset = <0xf6>; + tsensor_cp_default_out = <0x9cc>; + }; + sadc: sadc@f1200000 { + compatible = "fh,fh-sadc"; + reg = <0xf1200000 0x1000>; + interrupts = <20>; + ref-vol = <1800>; + active-bit = <0xfff>; + }; + efuse: efuse@0xf1600000 { + compatible = "fh,fh-efuse"; + reg = <0xf1600000 0x1000>; + key_switch = "enable"; + indep_power = "enable"; + }; + fh_perf: fh_perf@0xf0002018 { + compatible = "fh,fh-perf"; + reg = <0xf0000000 0x4000>; + interrupts = < 5 >; + + }; + spi_bus0: spi@f0500000 { + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + compatible = "fh,fh-spi"; + reg = <0xf0500000 0x4000>; + clk_in = <100000000>; + clock_source = <100000000>; + clock_source_num = <1>; + num-cs = <2>; + cs0_gpio = <6>; + cs1_gpio = <55>; + dma_enable = "disable"; + swap_support = "enable"; + rx_hs_no = <4>; + tx_hs_no = <5>; + bus_no = <0>; + multi_wire_size = <2>; + clk_name = "spi0_clk"; + rx_dma_channel = <0>; + tx_dma_channel = <1>; + increase_support = "disable"; + data_field_size = <0x1000>; + data_reg_offset = <0x1000>; + dma_protctl_enable = "disable"; + dma_protctl_data = <6>; + dma_master_sel_enable = "disable"; + dma_master_ctl_sel = <0>; + dma_master_mem_sel = <0>; + spidma_xfer_mode = "rx_only"; + interrupts = <28>; + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fh,m25p80"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + reg = <0x0 0>; //first value means which slave bind to the master. 0 means chip 0. 1 means chip 1 + partition@0 { + reg = <0x0 0x40000>; + label = "bootstrap"; + }; + partition@40000 { + reg = <0x40000 0x10000>; + label = "uboot-env"; + }; + partition@50000 { + reg = <0x50000 0x30000>; + label = "uboot"; + }; + partition@80000 { + reg = <0x80000 0x400000>; + label = "kernel"; + }; + partition@480000 { + reg = <0x480000 0x80000>; + label = "rootfs"; + }; + partition@500000 { + reg = <0x500000 0x300000>; + label = "app"; + }; + + }; + spidev0: spi@0 { + compatible = "rohm,dh2228fv"; + reg = <0x1 0>; + spi-max-frequency = <50000000>; + }; + }; + spi_bus1: spi@f0600000 { + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + compatible = "fh,fh-spi"; + reg = <0xf0600000 0x4000>; + clk_in = <100000000>; + clock_source = <100000000>; + clock_source_num = <1>; + num-cs = <2>; + cs0_gpio = <14>; + cs1_gpio = <57>; + dma_enable = "disable"; + swap_support = "disable"; + rx_hs_no = <2>; + tx_hs_no = <3>; + bus_no = <1>; + clk_name = "spi1_clk"; + rx_dma_channel = <2>; + tx_dma_channel = <3>; + increase_support = "disable"; + data_field_size = <0x1000>; + data_reg_offset = <0x1000>; + dma_protctl_enable = "disable"; + dma_protctl_data = <6>; + dma_master_sel_enable = "disable"; + dma_master_ctl_sel = <0>; + dma_master_mem_sel = <0>; + spidma_xfer_mode = "rx_only"; + interrupts = <21>; + spidev1: spi@1 { + compatible = "rohm,dh2228fv"; + reg = <0x0 0>; + spi-max-frequency = <50000000>; + }; + spidev2: spi@2 { + compatible = "rohm,dh2228fv"; + reg = <0x1 0>; + spi-max-frequency = <50000000>; + }; + }; + fhdwi2s: i2s@f0900000 { + compatible = "fh,fh-dw_i2s"; + reg = <0xf0900000 0x1000>; + interrupts = <25>; + clocks = <&i2s_clk>, <&ac_clk>; + clock-names = "i2s_clk", "acodec_mclk"; + rx_dma_channel = <2>; + tx_dma_channel = <3>; + dma_master = <0>; + dma_rx_hs_num = <10>; + dma_tx_hs_num = <11>; + }; + + fhacw: acw@f0a00000 { + compatible = "fh,fh-acw"; + reg = <0xf0a00000 0x1000>; + interrupts = <19>; + clocks = <&ac_clk>; + clock-names = "ac_clk"; + rx_dma_channel = <4>; + tx_dma_channel = <5>; + dma_master = <0>; + dma_rx_hs_num = <0>; + dma_tx_hs_num = <1>; + }; + + pwm: pwm@f0400000{ + compatible = "fh,fh-pwm"; + reg = <0xf0400000 0x1000>; + interrupts = <36>; + npwm = <14>; + }; + serial0: serial@f0700000 { + compatible = "fh,fh-serial"; + reg = <0xf0700000 0x1000>; + interrupts = <30>; + clock-frequency = <16666667>; + fifo-size = <32>; + }; + serial1: serial@f0800000 { + compatible = "fh,fh-serial"; + reg = <0xf0800000 0x1000>; + interrupts = <31>; + clock-frequency = <16666667>; + fifo-size = <64>; + }; + serial2: serial@f1300000 { + compatible = "fh,fh-serial"; + reg = <0xf1300000 0x1000>; + interrupts = <41>; + clock-frequency = <16666667>; + fifo-size = <64>; + }; + gmac0: gmac@e0600000 { + compatible = "fh,fh-gmac"; + reg = <0xe0600000 0x2000>; + interrupts = <44>; + phyreset-gpio = <29>; + }; + sdc0: sdc0@e2000000 { + compatible = "fh,fh-sdc"; + reg = <0xe2000000 0x4000>; + interrupts = <42>; + id = <0>; + buswidth = <4>; + wp-fixed = <1>; + cd-fixed = <0>; + drv-degree = <8>; + sam-degree = <0>; + scan-mux = <0>; + }; + sdc1: sdc1@e2200000 { + compatible = "fh,fh-sdc"; + reg = <0xe2200000 0x4000>; + interrupts = <43>; + id = <1>; + buswidth = <4>; + wp-fixed = <1>; + cd-fixed = <1>; + drv-degree = <8>; + sam-degree = <0>; + scan-mux = <2>; + }; + wdt: wdt@f0d00000{ + compatible = "fh,fh-wdt"; + reg = <0xf0d00000 0x1000>; + interrupts = <2>; + mode = <1>; + }; + i2cbus0: i2c@f0200000 { + compatible = "fh,fh-i2c"; + reg = <0xf0200000 0x2000>; + interrupts = <11>; + }; + i2cbus1: i2c@f0b00000 { + compatible = "fh,fh-i2c"; + reg = <0xf0b00000 0x2000>; + interrupts = <12>; + }; + i2cbus2: i2c@0xF0100000 { + compatible = "fh,fh-i2c"; + reg = <0xF0100000 0x2000>; + interrupts = <46>; + }; + clocks: src_clk@0xf0000000{ + compatible = "fh,fh-clk"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf0000000 0x80>; + ranges; + + osc_clk: mxtal@24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc_clk"; + }; + + pll_ddr_rclk: pllddrr{ + #clock-cells = <0>; + compatible = "fh pll-ddr-rclk"; + reg = <0xf0000010 0x4>,<0xf0000018 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f000000>; + divcop = <0xf000>; + clocks = <&osc_clk>; + clock-output-names = "pll_ddr_rclk"; + }; + pll_cpu_pclk: pllcpup{ + #clock-cells = <0>; + compatible = "fh pll-cpu-pclk"; + reg = <0xf0000014 0x4>,<0xf000006c 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f0000>; + divcop = <0xf00>; + clocks = <&osc_clk>; + clock-output-names = "pll_cpu_pclk"; + }; + pll_cpu_rclk: pllcpur{ + #clock-cells = <0>; + compatible = "fh pll-cpu-rclk"; + reg = <0xf0000014 0x4>,<0xf000006c 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f000000>; + divcop = <0xf000>; + clocks = <&osc_clk>; + clock-output-names = "pll_cpu_rclk"; + }; + pll_sys_pclk: pllsysp{ + #clock-cells = <0>; + compatible = "fh pll-sys-pclk"; + reg = <0xf0000064 0x4>,<0xf0000068 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f0000>; + divcop = <0xf00>; + clocks = <&osc_clk>; + clock-output-names = "pll_sys_pclk"; + }; + pll_sys_rclk: pllsysr{ + #clock-cells = <0>; + compatible = "fh pll-sys-rclk"; + reg = <0xf0000064 0x4>,<0xf0000068 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f000000>; + divcop = <0xf000>; + clocks = <&osc_clk>; + clock-output-names = "pll_sys_rclk"; + }; + sysp_div12_clk: syspdiv12clk{ + #clock-cells = <0>; + compatible = "fh sysp-div12-clk"; + reg = <0xf0000038 0x4>,<0x0 0x4>,<0x0 0x4>; + div = <0xf000000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "sysp_div12_clk"; + }; + ddr_clk: ddrclk{ + #clock-cells = <0>; + compatible = "fh fh-ddr-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x4000000>; + clocks = <&pll_ddr_rclk>; + clock-output-names = "ddr_clk"; + }; + arm_clk: armclk{ + #clock-cells = <0>; + compatible = "fh fh-arm-clk"; + reg = <0x0 0x4>,<0x0 0x4>,<0xf000000c 0x4>; + mux = <0x1>; + clocks = <&osc_clk>,<&pll_cpu_pclk>; + clock-output-names = "arm_clk"; + }; + arc_clk: arcclk{ + #clock-cells = <0>; + compatible = "fh fh-arc-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0xf000000c 0x4>; + gate = <0x4000000>; + mux = <0x1>; + clocks = <&osc_clk>,<&pll_cpu_rclk>; + clock-output-names = "arc_clk"; + }; + ahb_clk: ahbclk{ + #clock-cells = <0>; + compatible = "fh fh-ahb-clk"; + reg = <0xf0000024 0x4>,<0x0 0x4>,<0xf000000c 0x4>; + div = <0xf0000>; + mux = <0x1>; + clocks = <&osc_clk>,<&pll_sys_pclk>; + clock-output-names = "ahb_clk"; + }; + isp_aclk: ispaclk{ + #clock-cells = <0>; + compatible = "fh fh-ispa-clk"; + reg = <0xf0000024 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xf00>; + gate = <0x1>; + clocks = <&pll_sys_pclk>; + clock-output-names = "isp_aclk"; + }; + ispb_aclk: ispbclk{ + #clock-cells = <0>; + compatible = "fh fh-ispb-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + gate = <0x4>; + clocks = <&isp_aclk>; + clock-output-names = "ispb_aclk"; + }; + vpu_clk: vpuclk{ + #clock-cells = <0>; + compatible = "fh fh-vpu-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x80000000>; + clocks = <&isp_aclk>; + clock-output-names = "vpu_clk"; + }; + pix_clk: pixclk{ + #clock-cells = <0>; + compatible = "fh fh-pix-clk"; + reg = <0xf000002c 0x4>,<0x0 0x4>,<0x0 0x4>; + div = <0xf000000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "pix_clk"; + }; + jpeg_clk: jpegclk{ + #clock-cells = <0>; + compatible = "fh fh-jpeg-clk"; + reg = <0xf000005c 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + div = <0xf00000>; + gate = <0x40000000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "jpeg_clk"; + }; + bgm_clk: bgmclk{ + #clock-cells = <0>; + compatible = "fh fh-bgm-clk"; + reg = <0xf000005c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xf00000>; + gate = <0x40000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "bgm_clk"; + }; + jpeg_adapt_clk: jpegadaptclk{ + #clock-cells = <0>; + compatible = "fh fh-jpeg-adapt-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x2>; + clocks = <&jpeg_clk>; + clock-output-names = "jpeg_adapt_clk"; + }; + spi0_clk: spi0clk{ + #clock-cells = <0>; + compatible = "fh fh-spi0-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff>; + gate = <0x80>; + clocks = <&pll_sys_pclk>; + clock-output-names = "spi0_clk"; + }; + sdc0_clk: sdc0clk{ + #clock-cells = <0>; + compatible = "fh fh-sdc0-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + prediv =<8>; + div = <0xf00>; + gate = <0x200>; + clocks = <&pll_sys_pclk>; + clock-output-names = "sdc0_clk"; + }; + spi2_clk: spi2clk{ + #clock-cells = <0>; + compatible = "fh fh-spi2-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xf000>; + gate = <0x2>; + clocks = <&pll_sys_pclk>; + clock-output-names = "spi2_clk"; + }; + spi1_clk: spi1clk{ + #clock-cells = <0>; + compatible = "fh fh-spi1-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff0000>; + gate = <0x100>; + clocks = <&pll_sys_pclk>; + clock-output-names = "spi1_clk"; + }; + sdc1_clk: sdc1clk{ + #clock-cells = <0>; + compatible = "fh fh-sdc1-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + prediv =<8>; + div = <0xf000000>; + gate = <0x400>; + clocks = <&pll_sys_pclk>; + clock-output-names = "sdc1_clk"; + }; + veu_clk: veuclk{ + #clock-cells = <0>; + compatible = "fh fh-veu-clk"; + reg = <0xf0000024 0x4>,<0xf000001c 0x4>,<0xf000000c 0x4>; + div = <0x7000000>; + gate = <0x10>; + mux = <0x4>; + clocks = <&pll_sys_pclk>,<&pll_sys_rclk>; + clock-output-names = "veu_clk"; + }; + veu_adapt_clk: veuadaptclk{ + #clock-cells = <0>; + compatible = "fh fh-veu-adapt-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + gate = <0x20000000>; + clocks = <&veu_clk>; + clock-output-names = "veu_adapt_clk"; + }; + cis_clk_out: cisclk{ + #clock-cells = <0>; + compatible = "fh fh-cis-clk-out"; + reg = <0xf0000028 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff0000>; + gate = <0x800000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "cis_clk_out"; + }; + eth_clk: ethclk{ + #clock-cells = <0>; + compatible = "fh fh-eth-clk"; + reg = <0xf000003c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xf000000>; + gate = <0x2000000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "eth_clk"; + }; + eth_rmii_clk: ethrmiiclk { + #clock-cells = <0>; + compatible = "fh fh-ethrmii-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + gate = <0x10000000>; + clock-output-names = "eth_rmii_clk"; + }; + i2c0_clk: i2c0clk { + #clock-cells = <0>; + compatible = "fh fh-i2c0-clk"; + reg = <0xf0000034 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f0000>; + gate = <0x1000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "i2c0_clk"; + }; + + i2c1_clk: i2c1clk { + #clock-cells = <0>; + compatible = "fh fh-i2c1-clk"; + reg = <0xf0000034 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f000000>; + gate = <0x8000000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "i2c1_clk"; + }; + i2c2_clk: i2c2clk { + #clock-cells = <0>; + compatible = "fh fh-i2c2-clk"; + reg = <0xf000005c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f00>; + gate = <0x00000008>; + clocks = <&sysp_div12_clk>; + clock-output-names = "i2c2_clk"; + }; + + uart0_clk: uart0clk { + #clock-cells = <0>; + compatible = "fh fh-uart0-clk"; + reg = <0xf0000034 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x1f>; + gate = <0x2000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "uart0_clk"; + }; + + uart1_clk: uart1clk { + #clock-cells = <0>; + compatible = "fh fh-uart1-clk"; + reg = <0xf0000034 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x1f00>; + gate = <0x4000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "uart1_clk"; + }; + uart2_clk: uart2clk { + #clock-cells = <0>; + compatible = "fh fh-uart2-clk"; + reg = <0xf000005c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x7f>; + gate = <0x8000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "uart2_clk"; + }; + pwm_clk: pwmclk { + #clock-cells = <0>; + compatible = "fh fh-pwm-clk"; + reg = <0xf0000038 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff>; + gate = <0x10000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "pwm_clk"; + }; + efuse_clk: efuseclk { + #clock-cells = <0>; + compatible = "fh fh-efuse-clk"; + reg = <0xf0000028 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f000000>; + gate = <0x200000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "efuse_clk"; + }; + pts_clk: ptsclk { + #clock-cells = <0>; + compatible = "fh fh-pts-clk"; + reg = <0xf000002c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x1ff>; + gate = <0x80000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "pts_clk"; + }; + tmr0_clk: tmr0clk { + #clock-cells = <0>; + compatible = "fh fh-tmr0-clk"; + reg = <0xf0000038 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff0000>; + gate = <0x20000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "tmr0_clk"; + }; + + sadc_clk: sadcclk { + #clock-cells = <0>; + compatible = "fh fh-sadc-clk"; + reg = <0xf000003c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x7f0000>; + gate = <0x4000000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "sadc_clk"; + }; + gpio0_dbclk: gpio0dbclk { + #clock-cells = <0>; + compatible = "fh fh-gpio0-dbclk"; + reg = <0xf0000060 0x4>,<0xf0000060 0x4>,<0x0 0x4>; + div = <0x7fff>; + gate = <0x8000>; + prediv = <100>; + clocks = <&sysp_div12_clk>; + clock-output-names = "gpio0_dbclk"; + }; + gpio1_dbclk: gpio1dbclk { + #clock-cells = <0>; + compatible = "fh fh-gpio1-dbclk"; + reg = <0xf0000060 0x4>,<0xf0000060 0x4>,<0x0 0x4>; + div = <0x7fff0000>; + gate = <0x80000000>; + prediv = <100>; + clocks = <&sysp_div12_clk>; + clock-output-names = "gpio1_dbclk"; + }; + wdt_clk: wdtclk { + #clock-cells = <0>; + compatible = "fh fh-wdt-clk"; + reg = <0xf0000038 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + div = <0xff00>; + gate = <0x8000000>; + clocks = <&ahb_clk>; + clock-output-names = "wdt_clk"; + }; + ac_clk: acclk{ + #clock-cells = <0>; + compatible = "fh fh-ac-clk"; + reg = <0xf000003c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f>; + gate = <0x800>; + clocks = <&osc_clk>; + clock-output-names = "ac_clk"; + }; + i2s_clk: i2sclk{ + #clock-cells = <0>; + compatible = "fh fh-i2s-clk"; + reg = <0xf000003c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f00>; + gate = <0x1000000>; + clocks = <&ac_clk>; + clock-output-names = "i2s_clk"; + }; + mipi_dphy_clk: mipidphyclk { + #clock-cells = <0>; + compatible = "fh fh-mipi-dphy-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + gate = <0x100000>; + clock-output-names = "mipi_dphy_clk"; + }; + mipi_wrap_gate: mipiwrapclk { + #clock-cells = <0>; + compatible = "fh fh-mipi-wrap-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x20000000>; + clock-output-names = "mipi_wrap_gate"; + }; + rtc_hclk_gate: rtchclk { + #clock-cells = <0>; + compatible = "fh fh-rtc-hclk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x10000000>; + clock-output-names = "rtc_hclk_gate"; + }; + emac_hclk_gate: emachclk { + #clock-cells = <0>; + compatible = "fh fh-emac-hclk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x2000000>; + clock-output-names = "emac_hclk_gate"; + }; + usb_clk: usbclk { + #clock-cells = <0>; + compatible = "fh fh-usb-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x1000000>; + clock-output-names = "usb_clk"; + }; + aes_hclk_gate: aeshclk { + #clock-cells = <0>; + compatible = "fh fh-aes-hclk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x80>; + clock-output-names = "aes_hclk_gate"; + }; + ephy_clk_gate: ephyclk { + #clock-cells = <0>; + compatible = "fh fh-ephy-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x1>; + clock-output-names = "ephy_clk_gate"; + }; + sdc0_clk8x_gate: sdc08xclk { + #clock-cells = <0>; + compatible = "fh fh-sdc08x-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x4>; + clock-output-names = "sdc0_clk8x_gate"; + }; + sdc1_clk8x_gate: sdc18xclk { + #clock-cells = <0>; + compatible = "fh fh-sdc18x-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x8>; + clock-output-names = "sdc1_clk8x_gate"; + }; + mipic_pclk_gate: mipicpclk { + #clock-cells = <0>; + compatible = "fh fh-mipic-pclk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x10>; + clock-output-names = "mipic_pclk_gate"; + }; + gpio0_pclk_gate: gpio0pclk { + #clock-cells = <0>; + compatible = "fh fh-gpio0-pclk"; + reg = <0x0 0x4>,<0xf0000060 0x4>,<0x0 0x4>; + gate = <0x4000>; + clock-output-names = "gpio0_pclk_gate"; + }; + gpio1_pclk_gate: gpio1pclk { + #clock-cells = <0>; + compatible = "fh fh-gpio1-pclk"; + reg = <0x0 0x4>,<0xf0000060 0x4>,<0x0 0x4>; + gate = <0x40000000>; + clock-output-names = "gpio1_pclk_gate"; + }; + isp_hclk_gate: isphclk { + #clock-cells = <0>; + compatible = "fh fh-isp-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x1000000>; + clock-output-names = "isp_hclk_gate"; + }; + veu_hclk_gate: veuhclk { + #clock-cells = <0>; + compatible = "fh fh-veu-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x2000000>; + clock-output-names = "veu_hclk_gate"; + }; + bgm_hclk_gate: bgmhclk { + #clock-cells = <0>; + compatible = "fh fh-bgm-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x4000000>; + clock-output-names = "bgm_hclk_gate"; + }; + adapt_hclk_gate: adapthclk { + #clock-cells = <0>; + compatible = "fh fh-adapt-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x8000000>; + clock-output-names = "adapt_hclk_gate"; + }; + jpg_hclk_gate: jpghclk { + #clock-cells = <0>; + compatible = "fh fh-jpg-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x10000000>; + clock-output-names = "jpg_hclk_gate"; + }; + jpg_adapt_gate: jpgadaptclk { + #clock-cells = <0>; + compatible = "fh fh-jpg-adapt-clk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x20000000>; + clock-output-names = "jpg_adapt_gate"; + }; + vpu_hclk_gate: vpuhclk { + #clock-cells = <0>; + compatible = "fh fh-vpu-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x40000000>; + clock-output-names = "vpu_hclk_gate"; + }; + sdc0_clk_sample: sdc0clksample { + #clock-cells = <0>; + compatible = "fh fh-sdc0-clk_sample"; + reg = <0xf0000020 0x4>; + mux = <0xf0000>; + clocks = <&sdc0_clk>; + clock-output-names = "sdc0_clk_sample"; + }; + sdc0_clk_drv: sdc0clkdrv { + #clock-cells = <0>; + compatible = "fh fh-sdc0-clk_drv"; + reg = <0xf0000020 0x4>; + mux = <0xf00000>; + clocks = <&sdc0_clk>; + clock-output-names = "sdc0_clk_drv"; + }; + + sdc1_clk_sample: sdc1clksample { + #clock-cells = <0>; + compatible = "fh fh-sdc1-clk_sample"; + reg = <0xf0000020 0x4>; + mux = <0xf00>; + clocks = <&sdc1_clk>; + clock-output-names = "sdc1_clk_sample"; + }; + + sdc1_clk_drv: sdc1clkdrv { + #clock-cells = <0>; + compatible = "fh fh-sdc1-clk_drv"; + reg = <0xf0000020 0x4>; + mux = <0xf000>; + clocks = <&sdc1_clk>; + clock-output-names = "sdc1_clk_drv"; + }; + }; + }; + + usb_otg@e0700000 { + compatible = "fh_usb"; + reg = <0xe0700000 100000>; + interrupts = <39>; + clocks = <&usb_clk>; + dr_mode = "host"; + vbus_pwren = <47>; + clock-names = "otg"; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + }; + + usb2_phy: usbphy { + compatible = "fh,fh-usb2-phy"; + #phy-cells = <0>; + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/fh8856v210_pinctrl.dtsi b/arch/arm/boot/dts/fh8856v210_pinctrl.dtsi new file mode 100644 index 00000000..cc0129ca --- /dev/null +++ b/arch/arm/boot/dts/fh8856v210_pinctrl.dtsi @@ -0,0 +1,2386 @@ +/* + * Copyright (C) 2020 Fullhan Micorelectonics Co.,Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + #define PUPD_NONE (0) + #define PUPD_UP (1) + #define PUPD_DOWN (2) +*/ + +/ { + pinctrl: pinctrl@f0000080 { + compatible = "fh,fh-pinctrl"; + reg = <0xf0000080 0x104>; + pad-num = <65>; + max-mux = <9>; + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_ETH + &pinctrl_I2C0 + &pinctrl_PWM2 + &pinctrl_PWM3 + &pinctrl_PWM4 + &pinctrl_PWM5 + &pinctrl_PWM6 + &pinctrl_PWM7 + &pinctrl_PWM8 + &pinctrl_PWM9 + &pinctrl_SADC_XAIN0 + &pinctrl_SADC_XAIN1 + &pinctrl_SD0_NO_WP + &pinctrl_SENSOR_CLK + &pinctrl_SSI0_4BIT + &pinctrl_UART0 + &pinctrl_UART1 + &pinctrl_GPIO4 + &pinctrl_GPIO13 + &pinctrl_GPIO30 + &pinctrl_GPIO31 + &pinctrl_GPIO32 + &pinctrl_GPIO43 + &pinctrl_GPIO44 + &pinctrl_GPIO47 + + &pinctrl_GPIO11 + &pinctrl_GPIO14 + &pinctrl_GPIO15 + &pinctrl_GPIO16 + &pinctrl_GPIO24 + &pinctrl_GPIO25 + &pinctrl_GPIO45 + &pinctrl_GPIO46 + &pinctrl_GPIO48 + &pinctrl_GPIO49 + &pinctrl_GPIO50 + &pinctrl_GPIO51 + &pinctrl_GPIO52 + &pinctrl_GPIO53 + &pinctrl_GPIO54 + &pinctrl_GPIO55 + &pinctrl_GPIO56 + &pinctrl_GPIO57 + &pinctrl_GPIO58 + &pinctrl_GPIO59 + &pinctrl_GPIO60 + &pinctrl_GPIO61 + &pinctrl_GPIO62 + &pinctrl_GPIO63 + >; + pinctrl_groups { + pinctrl_ACI2S: ACI2S { + fh,pins = < + &mux_AC_I2S_CLK 0 + &mux_AC_I2S_DI 0 + &mux_AC_I2S_DO 0 + &mux_AC_I2S_WS 0 + &mux_AC_MCLK 0 + >; + }; + pinctrl_AC_MCLK: AC_MCLK { + fh,pins = < + &mux_AC_MCLK 0 + >; + }; + pinctrl_ARCJTAG: ARCJTAG { + fh,pins = < + &mux_ARC_JTAG_TCK 0 + &mux_ARC_JTAG_TDI 0 + &mux_ARC_JTAG_TDO 0 + &mux_ARC_JTAG_TMS 0 + &mux_ARC_JTAG_TRSTN 0 + >; + }; + pinctrl_ARMJTAG: ARMJTAG { + fh,pins = < + &mux_ARM_JTAG_TCK 0 + &mux_ARM_JTAG_TDI 0 + &mux_ARM_JTAG_TDO 0 + &mux_ARM_JTAG_TMS 0 + &mux_ARM_JTAG_TRSTN 0 + >; + }; + pinctrl_DWI2S: DWI2S { + fh,pins = < + &mux_DW_I2S_CLK 0 + &mux_DW_I2S_DI 0 + &mux_DW_I2S_DO 0 + &mux_DW_I2S_WS 0 + >; + }; + pinctrl_ETH: ETH { + fh,pins = < + &mux_ETH_LINK_ACT 1 + &mux_ETH_LINK_STA 1 + >; + }; + pinctrl_I2C0: I2C0 { + fh,pins = < + &mux_I2C0_SCL 0 + &mux_I2C0_SDA 0 + >; + }; + pinctrl_I2C1: I2C1 { + fh,pins = < + &mux_I2C1_SCL 2 + &mux_I2C1_SDA 2 + >; + }; + pinctrl_I2C2: I2C2 { + fh,pins = < + &mux_I2C2_SCL 1 + &mux_I2C2_SDA 1 + >; + }; + pinctrl_PAEJTAG: PAEJTAG { + fh,pins = < + &mux_PAE_JTAG_TCK 0 + &mux_PAE_JTAG_TDI 0 + &mux_PAE_JTAG_TDO 0 + &mux_PAE_JTAG_TMS 0 + &mux_PAE_JTAG_TRSTN 0 + >; + }; + pinctrl_PWM0: PWM0 { + fh,pins = < + &mux_PWM0 0 + >; + }; + pinctrl_PWM1: PWM1 { + fh,pins = < + &mux_PWM1 0 + >; + }; + pinctrl_PWM10: PWM10 { + fh,pins = < + &mux_PWM10 0 + >; + }; + pinctrl_PWM11: PWM11 { + fh,pins = < + &mux_PWM11 0 + >; + }; + pinctrl_PWM2: PWM2 { + fh,pins = < + &mux_PWM2 0 + >; + }; + pinctrl_PWM3: PWM3 { + fh,pins = < + &mux_PWM3 0 + >; + }; + pinctrl_PWM4: PWM4 { + fh,pins = < + &mux_PWM4 0 + >; + }; + pinctrl_PWM5: PWM5 { + fh,pins = < + &mux_PWM5 0 + >; + }; + pinctrl_PWM6: PWM6 { + fh,pins = < + &mux_PWM6 1 + >; + }; + pinctrl_PWM7: PWM7 { + fh,pins = < + &mux_PWM7 1 + >; + }; + pinctrl_PWM8: PWM8 { + fh,pins = < + &mux_PWM8 1 + >; + }; + pinctrl_PWM9: PWM9 { + fh,pins = < + &mux_PWM9 1 + >; + }; + pinctrl_RMII: RMII { + fh,pins = < + &mux_MAC_MDC 1 + &mux_MAC_MDIO 1 + &mux_MAC_REF_CLK 0 + &mux_MAC_RMII_CLK 0 + &mux_MAC_RXDV 0 + &mux_MAC_RXD_0 0 + &mux_MAC_RXD_1 0 + &mux_MAC_TXD_0 0 + &mux_MAC_TXD_1 0 + &mux_MAC_TXEN 0 + >; + }; + pinctrl_RTC: RTC { + fh,pins = < + &mux_RTC_CLK 0 + >; + }; + pinctrl_SADC_XAIN0: SADC_XAIN0 { + fh,pins = < + &mux_SADC_XAIN0 0 + >; + }; + pinctrl_SADC_XAIN1: SADC_XAIN1 { + fh,pins = < + &mux_SADC_XAIN1 0 + >; + }; + pinctrl_SADC_XAIN2: SADC_XAIN2 { + fh,pins = < + &mux_SADC_XAIN2 0 + >; + }; + pinctrl_SADC_XAIN3: SADC_XAIN3 { + fh,pins = < + &mux_SADC_XAIN3 0 + >; + }; + pinctrl_SD0: SD0 { + fh,pins = < + &mux_SD0_CD 0 + &mux_SD0_CLK 0 + &mux_SD0_CMD_RSP 0 + &mux_SD0_DATA_0 0 + &mux_SD0_DATA_1 0 + &mux_SD0_DATA_2 0 + &mux_SD0_DATA_3 0 + >; + }; + pinctrl_SD0_1BIT_NO_WP: SD0_1BIT_NO_WP { + fh,pins = < + &mux_SD0_CD 0 + &mux_SD0_CLK 0 + &mux_SD0_CMD_RSP 0 + &mux_SD0_DATA_0 0 + >; + }; + pinctrl_SD0_NO_WP: SD0_NO_WP { + fh,pins = < + &mux_SD0_CD 0 + &mux_SD0_CLK 0 + &mux_SD0_CMD_RSP 0 + &mux_SD0_DATA_0 0 + &mux_SD0_DATA_1 0 + &mux_SD0_DATA_2 0 + &mux_SD0_DATA_3 0 + >; + }; + pinctrl_SD0_WIFI: SD0_WIFI { + fh,pins = < + &mux_SD0_CLK 0 + &mux_SD0_CMD_RSP 0 + &mux_SD0_DATA_0 0 + &mux_SD0_DATA_1 0 + &mux_SD0_DATA_2 0 + &mux_SD0_DATA_3 0 + >; + }; + pinctrl_SD1: SD1 { + fh,pins = < + &mux_SD1_CD 0 + &mux_SD1_CLK 0 + &mux_SD1_CMD_RSP 0 + &mux_SD1_DATA_0 0 + &mux_SD1_DATA_1 0 + &mux_SD1_DATA_2 0 + &mux_SD1_DATA_3 0 + >; + }; + pinctrl_SD1_1BIT_NO_WP: SD1_1BIT_NO_WP { + fh,pins = < + &mux_SD1_CD 0 + &mux_SD1_CLK 0 + &mux_SD1_CMD_RSP 0 + &mux_SD1_DATA_0 0 + >; + }; + pinctrl_SD1_NO_WP: SD1_NO_WP { + fh,pins = < + &mux_SD1_CD 0 + &mux_SD1_CLK 0 + &mux_SD1_CMD_RSP 0 + &mux_SD1_DATA_0 0 + &mux_SD1_DATA_1 0 + &mux_SD1_DATA_2 0 + &mux_SD1_DATA_3 0 + >; + }; + pinctrl_SD1_WIFI: SD1_WIFI { + fh,pins = < + &mux_SD1_CLK 0 + &mux_SD1_CMD_RSP 0 + &mux_SD1_DATA_0 0 + &mux_SD1_DATA_1 0 + &mux_SD1_DATA_2 0 + &mux_SD1_DATA_3 0 + >; + }; + pinctrl_SENSOR_CLK: SENSOR_CLK { + fh,pins = < + &mux_SENSOR_CLK 0 + >; + }; + pinctrl_SSI0: SSI0 { + fh,pins = < + &mux_GPIO6 0 + &mux_SSI0_CLK 0 + &mux_SSI0_RXD 0 + &mux_SSI0_TXD 0 + >; + }; + pinctrl_SSI0_4BIT: SSI0_4BIT { + fh,pins = < + &mux_GPIO6 0 + &mux_SSI0_CLK 0 + &mux_SSI0_D2 0 + &mux_SSI0_D3 0 + &mux_SSI0_RXD 0 + &mux_SSI0_TXD 0 + >; + }; + pinctrl_SSI1: SSI1 { + fh,pins = < + &mux_GPIO14 0 + &mux_SSI1_CLK 2 + &mux_SSI1_RXD 2 + &mux_SSI1_TXD 2 + >; + }; + pinctrl_SSI2: SSI2 { + fh,pins = < + &mux_SSI2_CLK 1 + &mux_SSI2_CSN_0 1 + &mux_SSI2_RXD 1 + &mux_SSI2_TXD 1 + >; + }; + pinctrl_UART0: UART0 { + fh,pins = < + &mux_UART0_RX 0 + &mux_UART0_TX 0 + >; + }; + pinctrl_UART1: UART1 { + fh,pins = < + &mux_UART1_RX 0 + &mux_UART1_TX 0 + >; + }; + pinctrl_UART2: UART2 { + fh,pins = < + &mux_UART2_RX 0 + &mux_UART2_TX 0 + >; + }; + pinctrl_USB: USB { + fh,pins = < + &mux_USB_PWREN 0 + >; + }; + pinctrl_GPIO0: GPIO0 { + fh,pins = < + &mux_GPIO0 0 + >; + }; + pinctrl_GPIO1: GPIO1 { + fh,pins = < + &mux_GPIO1 0 + >; + }; + pinctrl_GPIO2: GPIO2 { + fh,pins = < + &mux_GPIO2 0 + >; + }; + pinctrl_GPIO3: GPIO3 { + fh,pins = < + &mux_GPIO3 0 + >; + }; + pinctrl_GPIO4: GPIO4 { + fh,pins = < + &mux_GPIO4 0 + >; + }; + pinctrl_GPIO5: GPIO5 { + fh,pins = < + &mux_GPIO5 0 + >; + }; + pinctrl_GPIO6: GPIO6 { + fh,pins = < + &mux_GPIO6 0 + >; + }; + pinctrl_GPIO7: GPIO7 { + fh,pins = < + &mux_GPIO7 0 + >; + }; + pinctrl_GPIO8: GPIO8 { + fh,pins = < + &mux_GPIO8 0 + >; + }; + pinctrl_GPIO9: GPIO9 { + fh,pins = < + &mux_GPIO9 0 + >; + }; + pinctrl_GPIO10: GPIO10 { + fh,pins = < + &mux_GPIO10 0 + >; + }; + pinctrl_GPIO11: GPIO11 { + fh,pins = < + &mux_GPIO11 0 + >; + }; + pinctrl_GPIO12: GPIO12 { + fh,pins = < + &mux_GPIO12 0 + >; + }; + pinctrl_GPIO13: GPIO13 { + fh,pins = < + &mux_GPIO13 0 + >; + }; + pinctrl_GPIO14: GPIO14 { + fh,pins = < + &mux_GPIO14 0 + >; + }; + pinctrl_GPIO15: GPIO15 { + fh,pins = < + &mux_GPIO15 0 + >; + }; + pinctrl_GPIO16: GPIO16 { + fh,pins = < + &mux_GPIO16 0 + >; + }; + pinctrl_GPIO17: GPIO17 { + fh,pins = < + &mux_GPIO17 0 + >; + }; + pinctrl_GPIO18: GPIO18 { + fh,pins = < + &mux_GPIO18 0 + >; + }; + pinctrl_GPIO19: GPIO19 { + fh,pins = < + &mux_GPIO19 0 + >; + }; + pinctrl_GPIO20: GPIO20 { + fh,pins = < + &mux_GPIO20 0 + >; + }; + pinctrl_GPIO21: GPIO21 { + fh,pins = < + &mux_GPIO21 0 + >; + }; + pinctrl_GPIO22: GPIO22 { + fh,pins = < + &mux_GPIO22 0 + >; + }; + pinctrl_GPIO23: GPIO23 { + fh,pins = < + &mux_GPIO23 0 + >; + }; + pinctrl_GPIO24: GPIO24 { + fh,pins = < + &mux_GPIO24 0 + >; + }; + pinctrl_GPIO25: GPIO25 { + fh,pins = < + &mux_GPIO25 0 + >; + }; + pinctrl_GPIO26: GPIO26 { + fh,pins = < + &mux_GPIO26 0 + >; + }; + pinctrl_GPIO27: GPIO27 { + fh,pins = < + &mux_GPIO27 0 + >; + }; + pinctrl_GPIO28: GPIO28 { + fh,pins = < + &mux_GPIO28 0 + >; + }; + pinctrl_GPIO29: GPIO29 { + fh,pins = < + &mux_GPIO29 0 + >; + }; + pinctrl_GPIO30: GPIO30 { + fh,pins = < + &mux_GPIO30 0 + >; + }; + pinctrl_GPIO31: GPIO31 { + fh,pins = < + &mux_GPIO31 0 + >; + }; + pinctrl_GPIO32: GPIO32 { + fh,pins = < + &mux_GPIO32 0 + >; + }; + pinctrl_GPIO33: GPIO33 { + fh,pins = < + &mux_GPIO33 0 + >; + }; + pinctrl_GPIO34: GPIO34 { + fh,pins = < + &mux_GPIO34 0 + >; + }; + pinctrl_GPIO35: GPIO35 { + fh,pins = < + &mux_GPIO35 0 + >; + }; + pinctrl_GPIO36: GPIO36 { + fh,pins = < + &mux_GPIO36 0 + >; + }; + pinctrl_GPIO37: GPIO37 { + fh,pins = < + &mux_GPIO37 0 + >; + }; + pinctrl_GPIO38: GPIO38 { + fh,pins = < + &mux_GPIO38 0 + >; + }; + pinctrl_GPIO39: GPIO39 { + fh,pins = < + &mux_GPIO39 0 + >; + }; + pinctrl_GPIO40: GPIO40 { + fh,pins = < + &mux_GPIO40 0 + >; + }; + pinctrl_GPIO41: GPIO41 { + fh,pins = < + &mux_GPIO41 0 + >; + }; + pinctrl_GPIO42: GPIO42 { + fh,pins = < + &mux_GPIO42 0 + >; + }; + pinctrl_GPIO43: GPIO43 { + fh,pins = < + &mux_GPIO43 0 + >; + }; + pinctrl_GPIO44: GPIO44 { + fh,pins = < + &mux_GPIO44 0 + >; + }; + pinctrl_GPIO45: GPIO45 { + fh,pins = < + &mux_GPIO45 0 + >; + }; + pinctrl_GPIO46: GPIO46 { + fh,pins = < + &mux_GPIO46 0 + >; + }; + pinctrl_GPIO47: GPIO47 { + fh,pins = < + &mux_GPIO47 0 + >; + }; + pinctrl_GPIO48: GPIO48 { + fh,pins = < + &mux_GPIO48 0 + >; + }; + pinctrl_GPIO49: GPIO49 { + fh,pins = < + &mux_GPIO49 0 + >; + }; + pinctrl_GPIO50: GPIO50 { + fh,pins = < + &mux_GPIO50 0 + >; + }; + pinctrl_GPIO51: GPIO51 { + fh,pins = < + &mux_GPIO51 0 + >; + }; + pinctrl_GPIO52: GPIO52 { + fh,pins = < + &mux_GPIO52 0 + >; + }; + pinctrl_GPIO53: GPIO53 { + fh,pins = < + &mux_GPIO53 0 + >; + }; + pinctrl_GPIO54: GPIO54 { + fh,pins = < + &mux_GPIO54 0 + >; + }; + pinctrl_GPIO55: GPIO55 { + fh,pins = < + &mux_GPIO55 0 + >; + }; + pinctrl_GPIO56: GPIO56 { + fh,pins = < + &mux_GPIO56 0 + >; + }; + pinctrl_GPIO57: GPIO57 { + fh,pins = < + &mux_GPIO57 0 + >; + }; + pinctrl_GPIO58: GPIO58 { + fh,pins = < + &mux_GPIO58 0 + >; + }; + pinctrl_GPIO59: GPIO59 { + fh,pins = < + &mux_GPIO59 0 + >; + }; + pinctrl_GPIO60: GPIO60 { + fh,pins = < + &mux_GPIO60 0 + >; + }; + pinctrl_GPIO61: GPIO61 { + fh,pins = < + &mux_GPIO61 0 + >; + }; + pinctrl_GPIO62: GPIO62 { + fh,pins = < + &mux_GPIO62 0 + >; + }; + pinctrl_GPIO63: GPIO63 { + fh,pins = < + &mux_GPIO63 0 + >; + }; + pinctrl_SD1_EMMC: SD1_EMMC { + fh,pins = < + &mux_SD1_CD 3 + &mux_SD1_CLK 3 + &mux_SD1_CMD_RSP 3 + &mux_SD1_DATA_0 3 + &mux_SD1_DATA_1 3 + &mux_SD1_DATA_2 3 + &mux_SD1_DATA_3 3 + >; + }; + }; + pinmux: pinmux { + compatible = "fh,fh-pinmux"; + #list-cells = <1>; + mux_AC_I2S_CLK: AC_I2S_CLK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad39 + >; + }; + mux_AC_I2S_DI: AC_I2S_DI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad38 + >; + }; + mux_AC_I2S_DO: AC_I2S_DO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad37 + >; + }; + mux_AC_I2S_WS: AC_I2S_WS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad40 + >; + }; + mux_AC_MCLK: AC_MCLK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad41 + >; + }; + + mux_ARC_JTAG_TCK: ARC_JTAG_TCK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad55 + >; + }; + mux_ARC_JTAG_TDI: ARC_JTAG_TDI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad54 + >; + }; + mux_ARC_JTAG_TDO: ARC_JTAG_TDO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad53 + >; + }; + mux_ARC_JTAG_TMS: ARC_JTAG_TMS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad56 + >; + }; + mux_ARC_JTAG_TRSTN: ARC_JTAG_TRSTN { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad52 + >; + }; + + mux_ARM_JTAG_TCK: ARM_JTAG_TCK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad40 + >; + }; + mux_ARM_JTAG_TDI: ARM_JTAG_TDI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad39 + >; + }; + mux_ARM_JTAG_TDO: ARM_JTAG_TDO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad38 + >; + }; + mux_ARM_JTAG_TMS: ARM_JTAG_TMS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad41 + >; + }; + mux_ARM_JTAG_TRSTN: ARM_JTAG_TRSTN { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad37 + >; + }; + + mux_DW_I2S_CLK: DW_I2S_CLK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad39 + >; + }; + mux_DW_I2S_DI: DW_I2S_DI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad38 + >; + }; + mux_DW_I2S_DO: DW_I2S_DO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad37 + >; + }; + mux_DW_I2S_WS: DW_I2S_WS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad40 + >; + }; + + mux_ETH_LINK_ACT: ETH_LINK_ACT { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad1 + &pad63 + >; + }; + mux_ETH_LINK_SPD: ETH_LINK_SPD { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad2 + &pad64 + >; + }; + mux_ETH_LINK_STA: ETH_LINK_STA { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad2 + &pad64 + >; + }; + + mux_I2C0_SCL: I2C0_SCL { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad5 + >; + }; + mux_I2C0_SDA: I2C0_SDA { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad6 + >; + }; + + mux_I2C1_SCL: I2C1_SCL { + #list-cells = <1>; + select = <2>; + fh,pads = < + &pad11 + &pad30 + &pad46 + >; + }; + mux_I2C1_SDA: I2C1_SDA { + #list-cells = <1>; + select = <2>; + fh,pads = < + &pad12 + &pad31 + &pad47 + >; + }; + + mux_I2C2_SCL: I2C2_SCL { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad16 + &pad57 + >; + }; + mux_I2C2_SDA: I2C2_SDA { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad17 + &pad58 + >; + }; + + mux_MAC_MDC: MAC_MDC { + #list-cells = <1>; + select = <1>; + ds = <0>; + fh,pads = < + &pad28 + &pad63 + >; + }; + mux_MAC_MDIO: MAC_MDIO { + #list-cells = <1>; + select = <1>; + ds = <0>; + fh,pads = < + &pad29 + &pad64 + >; + }; + mux_MAC_REF_CLK: MAC_REF_CLK { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad21 + >; + }; + mux_MAC_RMII_CLK: MAC_RMII_CLK { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad20 + >; + }; + mux_MAC_RXDV: MAC_RXDV { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad27 + >; + }; + mux_MAC_RXD_0: MAC_RXD_0 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad25 + >; + }; + mux_MAC_RXD_1: MAC_RXD_1 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad26 + >; + }; + mux_MAC_TXD_0: MAC_TXD_0 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad22 + >; + }; + mux_MAC_TXD_1: MAC_TXD_1 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad23 + >; + }; + mux_MAC_TXEN: MAC_TXEN { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad24 + >; + }; + + mux_PAE_JTAG_TCK: PAE_JTAG_TCK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad55 + >; + }; + mux_PAE_JTAG_TDI: PAE_JTAG_TDI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad54 + >; + }; + mux_PAE_JTAG_TDO: PAE_JTAG_TDO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad53 + >; + }; + mux_PAE_JTAG_TMS: PAE_JTAG_TMS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad56 + >; + }; + mux_PAE_JTAG_TRSTN: PAE_JTAG_TRSTN { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad52 + >; + }; + + mux_PWM0: PWM0 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad16 + >; + }; + mux_PWM1: PWM1 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad17 + >; + }; + mux_PWM10: PWM10 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad63 + >; + }; + mux_PWM11: PWM11 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad64 + >; + }; + mux_PWM2: PWM2 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad11 + &pad18 + &pad20 + >; + }; + mux_PWM3: PWM3 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad12 + &pad19 + &pad22 + >; + }; + mux_PWM4: PWM4 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad13 + &pad23 + >; + }; + mux_PWM5: PWM5 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad14 + &pad24 + >; + }; + mux_PWM6: PWM6 { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad25 + &pad37 + >; + }; + mux_PWM7: PWM7 { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad26 + &pad38 + >; + }; + mux_PWM8: PWM8 { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad27 + &pad39 + >; + }; + mux_PWM9: PWM9 { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad28 + &pad40 + >; + }; + + mux_RTC_CLK: RTC_CLK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad64 + >; + }; + + mux_SADC_XAIN0: SADC_XAIN0 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad59 + >; + }; + mux_SADC_XAIN1: SADC_XAIN1 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad60 + >; + }; + mux_SADC_XAIN2: SADC_XAIN2 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad61 + >; + }; + mux_SADC_XAIN3: SADC_XAIN3 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad62 + >; + }; + + mux_SD0_CD: SD0_CD { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad52 + >; + }; + mux_SD0_CLK: SD0_CLK { + #list-cells = <1>; + select = <0>; + ds = <3>; + fh,pads = < + &pad53 + >; + }; + mux_SD0_CMD_RSP: SD0_CMD_RSP { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad54 + >; + }; + mux_SD0_DATA_0: SD0_DATA_0 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad55 + >; + }; + mux_SD0_DATA_1: SD0_DATA_1 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad56 + >; + }; + mux_SD0_DATA_2: SD0_DATA_2 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad57 + >; + }; + mux_SD0_DATA_3: SD0_DATA_3 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad58 + >; + }; + + mux_SD1_CD: SD1_CD { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad10 + &pad22 + &pad31 + &pad41 + &pad63 + >; + }; + mux_SD1_CLK: SD1_CLK { + #list-cells = <1>; + select = <0>; + ds = <3>; + fh,pads = < + &pad9 + &pad20 + &pad30 + &pad42 + >; + }; + mux_SD1_CMD_RSP: SD1_CMD_RSP { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad11 + &pad23 + &pad32 + &pad43 + >; + }; + mux_SD1_DATA_0: SD1_DATA_0 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad12 + &pad24 + &pad33 + &pad44 + >; + }; + mux_SD1_DATA_1: SD1_DATA_1 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad13 + &pad25 + &pad34 + &pad45 + >; + }; + mux_SD1_DATA_2: SD1_DATA_2 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad14 + &pad26 + &pad35 + &pad46 + >; + }; + mux_SD1_DATA_3: SD1_DATA_3 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad15 + &pad27 + &pad36 + &pad47 + >; + }; + + mux_SENSOR_CLK: SENSOR_CLK { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad7 + >; + }; + + mux_SSI0_CLK: SSI0_CLK { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad42 + >; + }; + mux_SSI0_D2: SSI0_D2 { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad46 + >; + }; + mux_SSI0_D3: SSI0_D3 { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad47 + >; + }; + mux_SSI0_RXD: SSI0_RXD { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad45 + >; + }; + mux_SSI0_TXD: SSI0_TXD { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad44 + >; + }; + + mux_SSI1_CLK: SSI1_CLK { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad11 + &pad37 + &pad48 + &pad53 + >; + }; + mux_SSI1_RXD: SSI1_RXD { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad14 + &pad40 + &pad51 + &pad55 + >; + }; + mux_SSI1_TXD: SSI1_TXD { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad13 + &pad39 + &pad50 + &pad54 + >; + }; + + mux_SSI2_CLK: SSI2_CLK { + #list-cells = <1>; + select = <1>; + ds = <2>; + fh,pads = < + &pad37 + &pad48 + >; + }; + mux_SSI2_CSN_0: SSI2_CSN_0 { + #list-cells = <1>; + select = <1>; + ds = <2>; + fh,pads = < + &pad38 + &pad49 + >; + }; + mux_SSI2_RXD: SSI2_RXD { + #list-cells = <1>; + select = <1>; + ds = <2>; + fh,pads = < + &pad40 + &pad51 + >; + }; + mux_SSI2_TXD: SSI2_TXD { + #list-cells = <1>; + select = <1>; + ds = <2>; + fh,pads = < + &pad39 + &pad50 + >; + }; + + mux_UART0_RX: UART0_RX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad4 + >; + }; + mux_UART0_TX: UART0_TX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad3 + >; + }; + + mux_UART1_RX: UART1_RX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad10 + &pad33 + &pad47 + >; + }; + mux_UART1_TX: UART1_TX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad9 + &pad32 + &pad46 + >; + }; + + mux_UART2_RX: UART2_RX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad14 + &pad17 + &pad35 + &pad58 + >; + }; + mux_UART2_TX: UART2_TX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad13 + &pad16 + &pad34 + &pad57 + >; + }; + + mux_USB_PWREN: USB_PWREN { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad15 + &pad41 + >; + }; + + mux_GPIO0: GPIO0 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad37 + >; + }; + mux_GPIO1: GPIO1 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad38 + >; + }; + mux_GPIO2: GPIO2 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad39 + >; + }; + mux_GPIO3: GPIO3 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad40 + >; + }; + mux_GPIO4: GPIO4 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad41 + >; + }; + mux_GPIO5: GPIO5 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad42 + >; + }; + mux_GPIO6: GPIO6 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad43 + >; + }; + mux_GPIO7: GPIO7 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad44 + >; + }; + mux_GPIO8: GPIO8 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad45 + >; + }; + mux_GPIO9: GPIO9 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad46 + >; + }; + mux_GPIO10: GPIO10 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad47 + >; + }; + mux_GPIO11: GPIO11 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad48 + >; + }; + mux_GPIO12: GPIO12 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad7 + >; + }; + mux_GPIO13: GPIO13 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad8 + >; + }; + mux_GPIO14: GPIO14 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad49 + >; + }; + mux_GPIO15: GPIO15 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad50 + >; + }; + mux_GPIO16: GPIO16 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad51 + >; + }; + mux_GPIO17: GPIO17 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad52 + >; + }; + mux_GPIO18: GPIO18 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad53 + >; + }; + mux_GPIO19: GPIO19 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad54 + >; + }; + mux_GPIO20: GPIO20 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad55 + >; + }; + mux_GPIO21: GPIO21 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad56 + >; + }; + mux_GPIO22: GPIO22 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad57 + >; + }; + mux_GPIO23: GPIO23 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad58 + >; + }; + mux_GPIO24: GPIO24 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad61 + >; + }; + mux_GPIO25: GPIO25 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad62 + >; + }; + mux_GPIO26: GPIO26 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad59 + >; + }; + mux_GPIO27: GPIO27 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad60 + >; + }; + mux_GPIO28: GPIO28 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad63 + >; + }; + mux_GPIO29: GPIO29 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad64 + >; + }; + mux_GPIO30: GPIO30 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad0 + >; + }; + mux_GPIO31: GPIO31 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad1 + >; + }; + mux_GPIO32: GPIO32 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad2 + >; + }; + mux_GPIO33: GPIO33 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad3 + >; + }; + mux_GPIO34: GPIO34 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad4 + >; + }; + mux_GPIO35: GPIO35 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad5 + >; + }; + mux_GPIO36: GPIO36 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad6 + >; + }; + mux_GPIO37: GPIO37 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad11 + >; + }; + mux_GPIO38: GPIO38 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad12 + >; + }; + mux_GPIO39: GPIO39 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad9 + >; + }; + mux_GPIO40: GPIO40 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad10 + >; + }; + mux_GPIO41: GPIO41 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad13 + >; + }; + mux_GPIO42: GPIO42 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad14 + >; + }; + mux_GPIO43: GPIO43 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad16 + >; + }; + mux_GPIO44: GPIO44 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad17 + >; + }; + mux_GPIO45: GPIO45 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad18 + >; + }; + mux_GPIO46: GPIO46 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad19 + >; + }; + mux_GPIO47: GPIO47 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad15 + >; + }; + mux_GPIO48: GPIO48 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad20 + >; + }; + mux_GPIO49: GPIO49 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad22 + >; + }; + mux_GPIO50: GPIO50 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad23 + >; + }; + mux_GPIO51: GPIO51 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad24 + >; + }; + mux_GPIO52: GPIO52 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad25 + >; + }; + mux_GPIO53: GPIO53 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad26 + >; + }; + mux_GPIO54: GPIO54 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad27 + >; + }; + mux_GPIO55: GPIO55 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad28 + >; + }; + mux_GPIO56: GPIO56 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad29 + >; + }; + mux_GPIO57: GPIO57 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad30 + >; + }; + mux_GPIO58: GPIO58 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad31 + >; + }; + mux_GPIO59: GPIO59 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad32 + >; + }; + mux_GPIO60: GPIO60 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad33 + >; + }; + mux_GPIO61: GPIO61 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad34 + >; + }; + mux_GPIO62: GPIO62 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad35 + >; + }; + mux_GPIO63: GPIO63 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad36 + >; + }; + }; + pinpad: pinpad { + compatible = "fh,fh-pinpad"; + pad0: PAD_BOOT_MODE_CFG { + index = <0>; + funcs = "GPIO30"; + pupd = <1>; + ds = <0>; + }; + pad1: PAD_BOOT_SEL1_CFG { + index = <1>; + funcs = "GPIO31", "ETH_LINK_ACT"; + pupd = <1>; + ds = <0>; + }; + pad2: PAD_BOOT_SEL0_CFG { + index = <2>; + funcs = "GPIO32", "ETH_LINK_STA", "ETH_LINK_SPD"; + pupd = <1>; + ds = <0>; + }; + pad3: PAD_UART0_TX_CFG { + index = <3>; + funcs = "UART0_TX", "GPIO33"; + pupd = <0>; + ds = <0>; + }; + pad4: PAD_UART0_RX_CFG { + index = <4>; + funcs = "UART0_RX", "GPIO34"; + pupd = <0>; + ds = <0>; + }; + pad5: PAD_I2C0_SCL_CFG { + index = <5>; + funcs = "I2C0_SCL", "GPIO35"; + pupd = <1>; + ds = <0>; + }; + pad6: PAD_I2C0_SDA_CFG { + index = <6>; + funcs = "I2C0_SDA", "GPIO36"; + pupd = <1>; + ds = <0>; + }; + pad7: PAD_SENSOR_CLK_CFG { + index = <7>; + funcs = "SENSOR_CLK", "GPIO12"; + pupd = <0>; + ds = <0>; + }; + pad8: PAD_SENSOR_RSTN_CFG { + index = <8>; + funcs = "GPIO13"; + pupd = <0>; + ds = <0>; + }; + pad9: PAD_UART1_TX_CFG { + index = <9>; + funcs = "UART1_TX", "GPIO39", "", "SD1_CLK", "", "", + "TEST_O_INT_RMII_CLK"; + pupd = <0>; + ds = <0>; + }; + pad10: PAD_UART1_RX_CFG { + index = <10>; + funcs = "UART1_RX", "GPIO40", "", "SD1_CD", "", "", + "TEST_INT_RMII_TXD_0"; + pupd = <0>; + ds = <0>; + }; + pad11: PAD_I2C1_SCL_CFG { + index = <11>; + funcs = "I2C1_SCL", "GPIO37", "PWM2", "SD1_CMD_RSP", "", + "SSI1_CLK", "TEST_INT_RMII_TXD_1"; + pupd = <0>; + ds = <0>; + }; + pad12: PAD_I2C1_SDA_CFG { + index = <12>; + funcs = "I2C1_SDA", "GPIO38", "PWM3", "SD1_DATA_0", "", + "SSI1_CSN_0", "TEST_INT_RMII_TXEN"; + pupd = <0>; + ds = <0>; + }; + pad13: PAD_UART2_TX_CFG { + index = <13>; + funcs = "UART2_TX", "GPIO41", "PWM4", "SD1_DATA_1", "", + "SSI1_TXD", "TEST_O_INT_RMII_RXD_0"; + pupd = <0>; + ds = <0>; + }; + pad14: PAD_UART2_RX_CFG { + index = <14>; + funcs = "UART2_RX", "GPIO42", "PWM5", "SD1_DATA_2", "", + "SSI1_RXD", "TEST_O_INT_RMII_RXD_1"; + pupd = <0>; + ds = <0>; + }; + pad15: PAD_USB_PWREN_CFG { + index = <15>; + funcs = "USB_PWREN", "GPIO47", "", "SD1_DATA_3", "", "", + "TEST_O_INT_RMII_CRSDV"; + pupd = <0>; + ds = <0>; + }; + pad16: PAD_PWM0_CFG { + index = <16>; + funcs = "PWM0", "GPIO43", "I2C2_SCL", "UART2_TX", "", "", + "TEST_O_INT_RMII_TXD_0"; + pupd = <0>; + ds = <0>; + }; + pad17: PAD_PWM1_CFG { + index = <17>; + funcs = "PWM1", "GPIO44", "I2C2_SDA", "UART2_RX", "", "", + "TEST_O_INT_RMII_TXD_1"; + pupd = <0>; + ds = <0>; + }; + pad18: PAD_PWM2_CFG { + index = <18>; + funcs = "PWM2", "GPIO45"; + pupd = <0>; + ds = <0>; + }; + pad19: PAD_PWM3_CFG { + index = <19>; + funcs = "PWM3", "GPIO46"; + pupd = <0>; + ds = <0>; + }; + pad20: PAD_MAC_RMII_CLK_CFG { + index = <20>; + funcs = "MAC_RMII_CLK", "GPIO48", "SD1_CLK", "PWM2"; + pupd = <0>; + ds = <0>; + }; + pad21: PAD_MAC_REF_CLK_CFG { + index = <21>; + funcs = "MAC_REF_CLK"; + pupd = <0>; + ds = <2>; + }; + pad22: PAD_MAC_TXD0_CFG { + index = <22>; + funcs = "MAC_TXD_0", "GPIO49", "SD1_CD", "PWM3"; + pupd = <0>; + ds = <0>; + }; + pad23: PAD_MAC_TXD1_CFG { + index = <23>; + funcs = "MAC_TXD_1", "GPIO50", "SD1_CMD_RSP", "PWM4"; + pupd = <0>; + ds = <0>; + }; + pad24: PAD_MAC_TXEN_CFG { + index = <24>; + funcs = "MAC_TXEN", "GPIO51", "SD1_DATA_0", "PWM5"; + pupd = <0>; + ds = <0>; + }; + pad25: PAD_MAC_RXD0_CFG { + index = <25>; + funcs = "MAC_RXD_0", "GPIO52", "SD1_DATA_1", "PWM6"; + pupd = <0>; + ds = <0>; + }; + pad26: PAD_MAC_RXD1_CFG { + index = <26>; + funcs = "MAC_RXD_1", "GPIO53", "SD1_DATA_2", "PWM7"; + pupd = <0>; + ds = <0>; + }; + pad27: PAD_MAC_RXDV_CFG { + index = <27>; + funcs = "MAC_RXDV", "GPIO54", "SD1_DATA_3", "PWM8"; + pupd = <0>; + ds = <0>; + }; + pad28: PAD_MAC_MDC_CFG { + index = <28>; + funcs = "MAC_MDC", "GPIO55", "", "PWM9"; + pupd = <0>; + ds = <0>; + }; + pad29: PAD_MAC_MDIO_CFG { + index = <29>; + funcs = "MAC_MDIO", "GPIO56"; + pupd = <0>; + ds = <0>; + }; + pad30: PAD_SD1_CLK_CFG { + index = <30>; + funcs = "SD1_CLK", "GPIO57", "I2C1_SCL"; + pupd = <0>; + ds = <0>; + }; + pad31: PAD_SD1_CD_CFG { + index = <31>; + funcs = "SD1_CD", "GPIO58", "I2C1_SDA"; + pupd = <0>; + ds = <0>; + }; + pad32: PAD_SD1_CMD_RSP_CFG { + index = <32>; + funcs = "SD1_CMD_RSP", "GPIO59", "UART1_TX"; + pupd = <0>; + ds = <0>; + }; + pad33: PAD_SD1_DATA_0_CFG { + index = <33>; + funcs = "SD1_DATA_0", "GPIO60", "UART1_RX"; + pupd = <0>; + ds = <0>; + }; + pad34: PAD_SD1_DATA_1_CFG { + index = <34>; + funcs = "SD1_DATA_1", "GPIO61", "UART2_TX"; + pupd = <0>; + ds = <0>; + }; + pad35: PAD_SD1_DATA_2_CFG { + index = <35>; + funcs = "SD1_DATA_2", "GPIO62", "UART2_RX"; + pupd = <0>; + ds = <0>; + }; + pad36: PAD_SD1_DATA_3_CFG { + index = <36>; + funcs = "SD1_DATA_3", "GPIO63"; + pupd = <0>; + ds = <0>; + }; + pad37: PAD_GPIO_0_CFG { + index = <37>; + funcs = "ARM_JTAG_TRSTN", "GPIO0", "AC_I2S_DO", "DW_I2S_DO", + "SSI1_CLK", "SSI2_CLK", "ACIP_ADDAT", "PWM6", + "TEST_O_INT_SMI_MDC"; + pupd = <0>; + ds = <0>; + }; + pad38: PAD_GPIO_1_CFG { + index = <38>; + funcs = "ARM_JTAG_TDO", "GPIO1", "AC_I2S_DI", "DW_I2S_DI", + "SSI1_CSN_0", "SSI2_CSN_0", "ACIP_DADAT", "PWM7", + "TEST_O_INT_SMI_MDIO_I"; + pupd = <0>; + ds = <0>; + }; + pad39: PAD_GPIO_2_CFG { + index = <39>; + funcs = "ARM_JTAG_TDI", "GPIO2", "AC_I2S_CLK", "DW_I2S_CLK", + "SSI1_TXD", "SSI2_TXD", "ACIP_ADBCLK", "PWM8", + "TEST_O_INT_SMI_MDIO_O"; + pupd = <0>; + ds = <0>; + }; + pad40: PAD_GPIO_3_CFG { + index = <40>; + funcs = "ARM_JTAG_TCK", "GPIO3", "AC_I2S_WS", "DW_I2S_WS", + "SSI1_RXD", "SSI2_RXD", "ACIP_ADLRC", "PWM9", + "TEST_I_INT_SMI_MDIO_I"; + pupd = <0>; + ds = <0>; + }; + pad41: PAD_GPIO_4_CFG { + index = <41>; + funcs = "ARM_JTAG_TMS", "GPIO4", "AC_MCLK", "USB_PWREN", + "SD1_CD", "TEST_I_INT_SMI_MDC"; + pupd = <0>; + ds = <0>; + }; + pad42: PAD_SSI0_CLK_CFG { + index = <42>; + funcs = "SSI0_CLK", "GPIO5", "", "", "SD1_CLK"; + pupd = <0>; + ds = <2>; + }; + pad43: PAD_SSI0_CSN_0_CFG { + index = <43>; + funcs = "SSI0_CSN_0", "GPIO6", "", "", "SD1_CMD_RSP"; + pupd = <0>; + ds = <2>; + }; + pad44: PAD_SSI0_TXD_CFG { + index = <44>; + funcs = "SSI0_TXD", "GPIO7", "", "", "SD1_DATA_0"; + pupd = <0>; + ds = <2>; + }; + pad45: PAD_SSI0_RXD_CFG { + index = <45>; + funcs = "SSI0_RXD", "GPIO8", "", "", "SD1_DATA_1"; + pupd = <0>; + ds = <2>; + }; + pad46: PAD_SSI0_D2_CFG { + index = <46>; + funcs = "SSI0_D2", "GPIO9", "UART1_TX", "I2C1_SCL", + "SD1_DATA_2"; + pupd = <0>; + ds = <2>; + }; + pad47: PAD_SSI0_D3_CFG { + index = <47>; + funcs = "SSI0_D3", "GPIO10", "UART1_RX", "I2C1_SDA", + "SD1_DATA_3"; + pupd = <0>; + ds = <2>; + }; + pad48: PAD_SSI1_CLK_CFG { + index = <48>; + funcs = "SSI1_CLK", "GPIO11", "SSI2_CLK"; + pupd = <0>; + ds = <0>; + }; + pad49: PAD_SSI1_CSN_0_CFG { + index = <49>; + funcs = "SSI1_CSN_0", "GPIO14", "SSI2_CSN_0"; + pupd = <0>; + ds = <0>; + }; + pad50: PAD_SSI1_TXD_CFG { + index = <50>; + funcs = "SSI1_TXD", "GPIO15", "SSI2_TXD"; + pupd = <0>; + ds = <0>; + }; + pad51: PAD_SSI1_RXD_CFG { + index = <51>; + funcs = "SSI1_RXD", "GPIO16", "SSI2_RXD"; + pupd = <0>; + ds = <0>; + }; + pad52: PAD_SD0_CD_CFG { + index = <52>; + funcs = "SD0_CD", "GPIO17", "", "ARC_JTAG_TRSTN", + "PAE_JTAG_TRSTN"; + pupd = <0>; + ds = <0>; + }; + pad53: PAD_SD0_CLK_CFG { + index = <53>; + funcs = "SD0_CLK", "GPIO18", "SSI1_CLK", "ARC_JTAG_TDO", + "PAE_JTAG_TDO"; + pupd = <0>; + ds = <2>; + }; + pad54: PAD_SD0_CMD_RSP_CFG { + index = <54>; + funcs = "SD0_CMD_RSP", "GPIO19", "SSI1_TXD", "ARC_JTAG_TDI", + "PAE_JTAG_TDI"; + pupd = <0>; + ds = <2>; + }; + pad55: PAD_SD0_DATA_0_CFG { + index = <55>; + funcs = "SD0_DATA_0", "GPIO20", "SSI1_RXD", "ARC_JTAG_TCK", + "PAE_JTAG_TCK"; + pupd = <0>; + ds = <2>; + }; + pad56: PAD_SD0_DATA_1_CFG { + index = <56>; + funcs = "SD0_DATA_1", "GPIO21", "SSI1_CSN_0", "ARC_JTAG_TMS", + "PAE_JTAG_TMS"; + pupd = <0>; + ds = <2>; + }; + pad57: PAD_SD0_DATA_2_CFG { + index = <57>; + funcs = "SD0_DATA_2", "GPIO22", "", "UART2_TX", "I2C2_SCL", "", + "ACIP_DABCLK"; + pupd = <0>; + ds = <2>; + }; + pad58: PAD_SD0_DATA_3_CFG { + index = <58>; + funcs = "SD0_DATA_3", "GPIO23", "SSI1_CSN_0", "UART2_RX", + "I2C2_SDA", "", "ACIP_DALRC"; + pupd = <0>; + ds = <2>; + }; + pad59: PAD_SADC_XAIN0_CFG { + index = <59>; + funcs = "SADC_XAIN0", "GPIO26"; + pupd = <0>; + ds = <0>; + }; + pad60: PAD_SADC_XAIN1_CFG { + index = <60>; + funcs = "SADC_XAIN1", "GPIO27"; + pupd = <0>; + ds = <0>; + }; + pad61: PAD_SADC_XAIN2_CFG { + index = <61>; + funcs = "SADC_XAIN2", "GPIO24"; + pupd = <0>; + ds = <0>; + }; + pad62: PAD_SADC_XAIN3_CFG { + index = <62>; + funcs = "SADC_XAIN3", "GPIO25"; + pupd = <0>; + ds = <0>; + }; + pad63: PAD_GPIO_28_CFG { + index = <63>; + funcs = "GPIO28", "", "ETH_LINK_ACT", "PWM10", + "USB_DBG_CLK", "SD1_CD", "TEST_O_INT_RMII_TXEN", + "MAC_MDC"; + pupd = <0>; + ds = <0>; + }; + pad64: PAD_GPIO_29_CFG { + index = <64>; + funcs = "GPIO29", "", "ETH_LINK_STA", "PWM11", "RTC_CLK", + "ETH_LINK_SPD", "TEST_O_INT_SMI_MDIO_OE", + "MAC_MDIO"; + pupd = <0>; + ds = <0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/fh8858v200.dts b/arch/arm/boot/dts/fh8858v200.dts new file mode 100644 index 00000000..35499672 --- /dev/null +++ b/arch/arm/boot/dts/fh8858v200.dts @@ -0,0 +1,956 @@ +/* + * Copyright (C) 2017 Fullhan Micorelectonics Co.,Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "skeleton.dtsi" +/include/ "fh8858v200_pinctrl.dtsi" +/ { + + + model = "FULLHAN FH8858V200"; + compatible = "fh,fh8858v200"; + interrupt-parent = <&intc>; + aliases { + i2c0 = &i2cbus0; + i2c1 = &i2cbus1; + i2c2 = &i2cbus2; + spi0 = &spi_bus0; + spi1 = &spi_bus1; + ttyS0 = &serial0; + ttyS1 = &serial1; + ttyS2 = &serial2; + }; + + cpus { + cpu@0 { + device_type = "cpu"; + compatible = "arm,arm1176jzf-s"; + }; + }; + + chosen { + bootargs = "coherent_pool=2M"; + }; + + intc: interrupt-controller@E0200000 { + compatible = "fh,fh-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xE0200000 0x1000>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pmu@f0000000 { + compatible = "fh,fh-pmu"; + reg = <0xf0000000 0x2100>; + SWRST_MAIN_CTRL = <0x40>; + }; + timer0: timer@f0c00000 { + compatible = "fh,fh-timer"; + interrupts = <3>; + clock-frequency = <1000000>; + reg = <0xf0c00000 0x14>; + }; + + timer1: timer@f0c00014 { + compatible = "fh,fh-timer"; + interrupts = <3>; + clock-frequency = <1000000>; + reg = <0xf0c00014 0x14>; + }; + + gpio0: gpio@f0300000 { + compatible = "fh,fh-gpio"; + reg = <0xf0300000 0x1000>; + #gpio_controller; + interrupt-controller; + interrupt-parent = <&intc>; + interrupts = <26>; + id = <0>; + ngpio = <32>; + base = <0>; + }; + + gpio1: gpio@f4000000 { + compatible = "fh,fh-gpio"; + reg = <0xf4000000 0x1000>; + #gpio_controller; + interrupt-controller; + interrupt-parent = <&intc>; + interrupts = <40>; + id = <1>; + ngpio = <32>; + base = <32>; + }; + + fhdma0: dma@e0300000 { + compatible = "fh,fh-axi-dmac"; + reg = <0xe0300000 0x1000>; + interrupts = <23>; + chan_allocation_order = <0>; + chan_priority = <1>; + block_size = <0x800>; + data_width = <2 0 0 0>; + clocks = <&ahb_clk>; + }; + + aes: aes@0xe8200000 { + compatible = "fh,fh-aes"; + reg = <0xe8200000 0x1000>; + interrupts = <16>; + }; + rtc: rtc@f1500000 { + compatible = "fh,fh_rtc"; + reg = <0xf1500000 0x1000>; + interrupts = <33>; + clocks = <&rtc_hclk_gate>; + lut_cof = <58>; + lut_offset = <0xff>; + tsensor_cp_default_out = <0x993>; + }; + sadc: sadc@f1200000 { + compatible = "fh,fh-sadc"; + reg = <0xf1200000 0x1000>; + interrupts = <20>; + ref-vol = <1800>; + active-bit = <0xfff>; + }; + efuse: efuse@0xf1600000 { + compatible = "fh,fh-efuse"; + reg = <0xf1600000 0x1000>; + key_switch = "enable"; + indep_power = "enable"; + }; + fh_perf: fh_perf@0xf0002018 { + compatible = "fh,fh-perf"; + reg = <0xf0000000 0x4000>; + interrupts = < 5 >; + + }; + spi_bus0: spi@f0500000 { + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + compatible = "fh,fh-spi"; + reg = <0xf0500000 0x4000>; + clk_in = <100000000>; + clock_source = <100000000>; + clock_source_num = <1>; + num-cs = <2>; + cs0_gpio = <6>; + cs1_gpio = <55>; + dma_enable = "disable"; + swap_support = "enable"; + rx_hs_no = <4>; + tx_hs_no = <5>; + bus_no = <0>; + multi_wire_size = <2>; + clk_name = "spi0_clk"; + rx_dma_channel = <0>; + tx_dma_channel = <1>; + increase_support = "disable"; + data_field_size = <0x1000>; + data_reg_offset = <0x1000>; + dma_protctl_enable = "disable"; + dma_protctl_data = <6>; + dma_master_sel_enable = "disable"; + dma_master_ctl_sel = <0>; + dma_master_mem_sel = <0>; + spidma_xfer_mode = "rx_only"; + interrupts = <28>; + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fh,m25p80"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + reg = <0x0 0>; //first value means which slave bind to the master. 0 means chip 0. 1 means chip 1 + partition@0 { + reg = <0x0 0x40000>; + label = "bootstrap"; + }; + partition@40000 { + reg = <0x40000 0x10000>; + label = "uboot-env"; + }; + partition@50000 { + reg = <0x50000 0x30000>; + label = "uboot"; + }; + partition@80000 { + reg = <0x80000 0x400000>; + label = "kernel"; + }; + partition@480000 { + reg = <0x480000 0x80000>; + label = "rootfs"; + }; + partition@500000 { + reg = <0x500000 0x300000>; + label = "app"; + }; + + }; + spidev0: spi@0 { + compatible = "rohm,dh2228fv"; + reg = <0x1 0>; + spi-max-frequency = <50000000>; + }; + }; + spi_bus1: spi@f0600000 { + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + compatible = "fh,fh-spi"; + reg = <0xf0600000 0x4000>; + clk_in = <100000000>; + clock_source = <100000000>; + clock_source_num = <1>; + num-cs = <2>; + cs0_gpio = <14>; + cs1_gpio = <57>; + dma_enable = "disable"; + swap_support = "disable"; + rx_hs_no = <2>; + tx_hs_no = <3>; + bus_no = <1>; + clk_name = "spi1_clk"; + rx_dma_channel = <2>; + tx_dma_channel = <3>; + increase_support = "disable"; + data_field_size = <0x1000>; + data_reg_offset = <0x1000>; + dma_protctl_enable = "disable"; + dma_protctl_data = <6>; + dma_master_sel_enable = "disable"; + dma_master_ctl_sel = <0>; + dma_master_mem_sel = <0>; + spidma_xfer_mode = "rx_only"; + interrupts = <21>; + spidev1: spi@1 { + compatible = "rohm,dh2228fv"; + reg = <0x0 0>; + spi-max-frequency = <50000000>; + }; + spidev2: spi@2 { + compatible = "rohm,dh2228fv"; + reg = <0x1 0>; + spi-max-frequency = <50000000>; + }; + }; + fhdwi2s: i2s@f0900000 { + compatible = "fh,fh-dw_i2s"; + reg = <0xf0900000 0x1000>; + interrupts = <25>; + clocks = <&i2s_clk>, <&ac_clk>; + clock-names = "i2s_clk", "acodec_mclk"; + rx_dma_channel = <2>; + tx_dma_channel = <3>; + dma_master = <0>; + dma_rx_hs_num = <10>; + dma_tx_hs_num = <11>; + }; + + fhacw: acw@f0a00000 { + compatible = "fh,fh-acw"; + reg = <0xf0a00000 0x1000>; + interrupts = <19>; + clocks = <&ac_clk>; + clock-names = "ac_clk"; + rx_dma_channel = <4>; + tx_dma_channel = <5>; + dma_master = <0>; + dma_rx_hs_num = <0>; + dma_tx_hs_num = <1>; + }; + + pwm: pwm@f0400000{ + compatible = "fh,fh-pwm"; + reg = <0xf0400000 0x1000>; + interrupts = <36>; + npwm = <14>; + }; + serial0: serial@f0700000 { + compatible = "fh,fh-serial"; + reg = <0xf0700000 0x1000>; + interrupts = <30>; + clock-frequency = <16666667>; + fifo-size = <32>; + }; + serial1: serial@f0800000 { + compatible = "fh,fh-serial"; + reg = <0xf0800000 0x1000>; + interrupts = <31>; + clock-frequency = <16666667>; + fifo-size = <64>; + }; + serial2: serial@f1300000 { + compatible = "fh,fh-serial"; + reg = <0xf1300000 0x1000>; + interrupts = <41>; + clock-frequency = <16666667>; + fifo-size = <64>; + }; + gmac0: gmac@e0600000 { + compatible = "fh,fh-gmac"; + reg = <0xe0600000 0x2000>; + interrupts = <44>; + phyreset-gpio = <29>; + }; + sdc0: sdc0@e2000000 { + compatible = "fh,fh-sdc"; + reg = <0xe2000000 0x4000>; + interrupts = <42>; + id = <0>; + buswidth = <4>; + wp-fixed = <1>; + cd-fixed = <0>; + drv-degree = <8>; + sam-degree = <0>; + scan-mux = <0>; + }; + sdc1: sdc1@e2200000 { + compatible = "fh,fh-sdc"; + reg = <0xe2200000 0x4000>; + interrupts = <43>; + id = <1>; + buswidth = <4>; + wp-fixed = <1>; + cd-fixed = <1>; + drv-degree = <8>; + sam-degree = <0>; + scan-mux = <2>; + }; + wdt: wdt@f0d00000{ + compatible = "fh,fh-wdt"; + reg = <0xf0d00000 0x1000>; + interrupts = <2>; + mode = <1>; + }; + i2cbus0: i2c@f0200000 { + compatible = "fh,fh-i2c"; + reg = <0xf0200000 0x2000>; + interrupts = <11>; + }; + i2cbus1: i2c@f0b00000 { + compatible = "fh,fh-i2c"; + reg = <0xf0b00000 0x2000>; + interrupts = <12>; + }; + i2cbus2: i2c@0xF0100000 { + compatible = "fh,fh-i2c"; + reg = <0xF0100000 0x2000>; + interrupts = <46>; + }; + clocks: src_clk@0xf0000000{ + compatible = "fh,fh-clk"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf0000000 0x80>; + ranges; + + osc_clk: mxtal@24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc_clk"; + }; + + pll_ddr_rclk: pllddrr{ + #clock-cells = <0>; + compatible = "fh pll-ddr-rclk"; + reg = <0xf0000010 0x4>,<0xf0000018 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f000000>; + divcop = <0xf000>; + clocks = <&osc_clk>; + clock-output-names = "pll_ddr_rclk"; + }; + pll_cpu_pclk: pllcpup{ + #clock-cells = <0>; + compatible = "fh pll-cpu-pclk"; + reg = <0xf0000014 0x4>,<0xf000006c 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f0000>; + divcop = <0xf00>; + clocks = <&osc_clk>; + clock-output-names = "pll_cpu_pclk"; + }; + pll_cpu_rclk: pllcpur{ + #clock-cells = <0>; + compatible = "fh pll-cpu-rclk"; + reg = <0xf0000014 0x4>,<0xf000006c 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f000000>; + divcop = <0xf000>; + clocks = <&osc_clk>; + clock-output-names = "pll_cpu_rclk"; + }; + pll_sys_pclk: pllsysp{ + #clock-cells = <0>; + compatible = "fh pll-sys-pclk"; + reg = <0xf0000064 0x4>,<0xf0000068 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f0000>; + divcop = <0xf00>; + clocks = <&osc_clk>; + clock-output-names = "pll_sys_pclk"; + }; + pll_sys_rclk: pllsysr{ + #clock-cells = <0>; + compatible = "fh pll-sys-rclk"; + reg = <0xf0000064 0x4>,<0xf0000068 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f000000>; + divcop = <0xf000>; + clocks = <&osc_clk>; + clock-output-names = "pll_sys_rclk"; + }; + sysp_div12_clk: syspdiv12clk{ + #clock-cells = <0>; + compatible = "fh sysp-div12-clk"; + reg = <0xf0000038 0x4>,<0x0 0x4>,<0x0 0x4>; + div = <0xf000000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "sysp_div12_clk"; + }; + ddr_clk: ddrclk{ + #clock-cells = <0>; + compatible = "fh fh-ddr-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x4000000>; + clocks = <&pll_ddr_rclk>; + clock-output-names = "ddr_clk"; + }; + arm_clk: armclk{ + #clock-cells = <0>; + compatible = "fh fh-arm-clk"; + reg = <0x0 0x4>,<0x0 0x4>,<0xf000000c 0x4>; + mux = <0x1>; + clocks = <&osc_clk>,<&pll_cpu_pclk>; + clock-output-names = "arm_clk"; + }; + arc_clk: arcclk{ + #clock-cells = <0>; + compatible = "fh fh-arc-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0xf000000c 0x4>; + gate = <0x4000000>; + mux = <0x1>; + clocks = <&osc_clk>,<&pll_cpu_rclk>; + clock-output-names = "arc_clk"; + }; + ahb_clk: ahbclk{ + #clock-cells = <0>; + compatible = "fh fh-ahb-clk"; + reg = <0xf0000024 0x4>,<0x0 0x4>,<0xf000000c 0x4>; + div = <0xf0000>; + mux = <0x1>; + clocks = <&osc_clk>,<&pll_sys_pclk>; + clock-output-names = "ahb_clk"; + }; + isp_aclk: ispaclk{ + #clock-cells = <0>; + compatible = "fh fh-ispa-clk"; + reg = <0xf0000024 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xf00>; + gate = <0x1>; + clocks = <&pll_sys_pclk>; + clock-output-names = "isp_aclk"; + }; + ispb_aclk: ispbclk{ + #clock-cells = <0>; + compatible = "fh fh-ispb-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + gate = <0x4>; + clocks = <&isp_aclk>; + clock-output-names = "ispb_aclk"; + }; + vpu_clk: vpuclk{ + #clock-cells = <0>; + compatible = "fh fh-vpu-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x80000000>; + clocks = <&isp_aclk>; + clock-output-names = "vpu_clk"; + }; + pix_clk: pixclk{ + #clock-cells = <0>; + compatible = "fh fh-pix-clk"; + reg = <0xf000002c 0x4>,<0x0 0x4>,<0x0 0x4>; + div = <0xf000000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "pix_clk"; + }; + jpeg_clk: jpegclk{ + #clock-cells = <0>; + compatible = "fh fh-jpeg-clk"; + reg = <0xf000005c 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + div = <0xf00000>; + gate = <0x40000000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "jpeg_clk"; + }; + bgm_clk: bgmclk{ + #clock-cells = <0>; + compatible = "fh fh-bgm-clk"; + reg = <0xf000005c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xf00000>; + gate = <0x40000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "bgm_clk"; + }; + jpeg_adapt_clk: jpegadaptclk{ + #clock-cells = <0>; + compatible = "fh fh-jpeg-adapt-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x2>; + clocks = <&jpeg_clk>; + clock-output-names = "jpeg_adapt_clk"; + }; + spi0_clk: spi0clk{ + #clock-cells = <0>; + compatible = "fh fh-spi0-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff>; + gate = <0x80>; + clocks = <&pll_sys_pclk>; + clock-output-names = "spi0_clk"; + }; + sdc0_clk: sdc0clk{ + #clock-cells = <0>; + compatible = "fh fh-sdc0-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + prediv =<8>; + div = <0xf00>; + gate = <0x200>; + clocks = <&pll_sys_pclk>; + clock-output-names = "sdc0_clk"; + }; + spi2_clk: spi2clk{ + #clock-cells = <0>; + compatible = "fh fh-spi2-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xf000>; + gate = <0x2>; + clocks = <&pll_sys_pclk>; + clock-output-names = "spi2_clk"; + }; + spi1_clk: spi1clk{ + #clock-cells = <0>; + compatible = "fh fh-spi1-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff0000>; + gate = <0x100>; + clocks = <&pll_sys_pclk>; + clock-output-names = "spi1_clk"; + }; + sdc1_clk: sdc1clk{ + #clock-cells = <0>; + compatible = "fh fh-sdc1-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + prediv =<8>; + div = <0xf000000>; + gate = <0x400>; + clocks = <&pll_sys_pclk>; + clock-output-names = "sdc1_clk"; + }; + veu_clk: veuclk{ + #clock-cells = <0>; + compatible = "fh fh-veu-clk"; + reg = <0xf0000024 0x4>,<0xf000001c 0x4>,<0xf000000c 0x4>; + div = <0x7000000>; + gate = <0x10>; + mux = <0x4>; + clocks = <&pll_sys_pclk>,<&pll_sys_rclk>; + clock-output-names = "veu_clk"; + }; + veu_adapt_clk: veuadaptclk{ + #clock-cells = <0>; + compatible = "fh fh-veu-adapt-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + gate = <0x20000000>; + clocks = <&veu_clk>; + clock-output-names = "veu_adapt_clk"; + }; + cis_clk_out: cisclk{ + #clock-cells = <0>; + compatible = "fh fh-cis-clk-out"; + reg = <0xf0000028 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff0000>; + gate = <0x800000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "cis_clk_out"; + }; + eth_clk: ethclk{ + #clock-cells = <0>; + compatible = "fh fh-eth-clk"; + reg = <0xf000003c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xf000000>; + gate = <0x2000000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "eth_clk"; + }; + eth_rmii_clk: ethrmiiclk { + #clock-cells = <0>; + compatible = "fh fh-ethrmii-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + gate = <0x10000000>; + clock-output-names = "eth_rmii_clk"; + }; + i2c0_clk: i2c0clk { + #clock-cells = <0>; + compatible = "fh fh-i2c0-clk"; + reg = <0xf0000034 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f0000>; + gate = <0x1000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "i2c0_clk"; + }; + + i2c1_clk: i2c1clk { + #clock-cells = <0>; + compatible = "fh fh-i2c1-clk"; + reg = <0xf0000034 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f000000>; + gate = <0x8000000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "i2c1_clk"; + }; + i2c2_clk: i2c2clk { + #clock-cells = <0>; + compatible = "fh fh-i2c2-clk"; + reg = <0xf000005c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f00>; + gate = <0x00000008>; + clocks = <&sysp_div12_clk>; + clock-output-names = "i2c2_clk"; + }; + + uart0_clk: uart0clk { + #clock-cells = <0>; + compatible = "fh fh-uart0-clk"; + reg = <0xf0000034 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x1f>; + gate = <0x2000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "uart0_clk"; + }; + + uart1_clk: uart1clk { + #clock-cells = <0>; + compatible = "fh fh-uart1-clk"; + reg = <0xf0000034 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x1f00>; + gate = <0x4000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "uart1_clk"; + }; + uart2_clk: uart2clk { + #clock-cells = <0>; + compatible = "fh fh-uart2-clk"; + reg = <0xf000005c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x7f>; + gate = <0x8000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "uart2_clk"; + }; + pwm_clk: pwmclk { + #clock-cells = <0>; + compatible = "fh fh-pwm-clk"; + reg = <0xf0000038 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff>; + gate = <0x10000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "pwm_clk"; + }; + efuse_clk: efuseclk { + #clock-cells = <0>; + compatible = "fh fh-efuse-clk"; + reg = <0xf0000028 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f000000>; + gate = <0x200000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "efuse_clk"; + }; + pts_clk: ptsclk { + #clock-cells = <0>; + compatible = "fh fh-pts-clk"; + reg = <0xf000002c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x1ff>; + gate = <0x80000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "pts_clk"; + }; + tmr0_clk: tmr0clk { + #clock-cells = <0>; + compatible = "fh fh-tmr0-clk"; + reg = <0xf0000038 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff0000>; + gate = <0x20000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "tmr0_clk"; + }; + + sadc_clk: sadcclk { + #clock-cells = <0>; + compatible = "fh fh-sadc-clk"; + reg = <0xf000003c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x7f0000>; + gate = <0x4000000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "sadc_clk"; + }; + gpio0_dbclk: gpio0dbclk { + #clock-cells = <0>; + compatible = "fh fh-gpio0-dbclk"; + reg = <0xf0000060 0x4>,<0xf0000060 0x4>,<0x0 0x4>; + div = <0x7fff>; + gate = <0x8000>; + prediv = <100>; + clocks = <&sysp_div12_clk>; + clock-output-names = "gpio0_dbclk"; + }; + gpio1_dbclk: gpio1dbclk { + #clock-cells = <0>; + compatible = "fh fh-gpio1-dbclk"; + reg = <0xf0000060 0x4>,<0xf0000060 0x4>,<0x0 0x4>; + div = <0x7fff0000>; + gate = <0x80000000>; + prediv = <100>; + clocks = <&sysp_div12_clk>; + clock-output-names = "gpio1_dbclk"; + }; + wdt_clk: wdtclk { + #clock-cells = <0>; + compatible = "fh fh-wdt-clk"; + reg = <0xf0000038 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + div = <0xff00>; + gate = <0x8000000>; + clocks = <&ahb_clk>; + clock-output-names = "wdt_clk"; + }; + ac_clk: acclk{ + #clock-cells = <0>; + compatible = "fh fh-ac-clk"; + reg = <0xf000003c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f>; + gate = <0x800>; + clocks = <&osc_clk>; + clock-output-names = "ac_clk"; + }; + i2s_clk: i2sclk{ + #clock-cells = <0>; + compatible = "fh fh-i2s-clk"; + reg = <0xf000003c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f00>; + gate = <0x1000000>; + clocks = <&ac_clk>; + clock-output-names = "i2s_clk"; + }; + mipi_dphy_clk: mipidphyclk { + #clock-cells = <0>; + compatible = "fh fh-mipi-dphy-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + gate = <0x100000>; + clock-output-names = "mipi_dphy_clk"; + }; + mipi_wrap_gate: mipiwrapclk { + #clock-cells = <0>; + compatible = "fh fh-mipi-wrap-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x20000000>; + clock-output-names = "mipi_wrap_gate"; + }; + rtc_hclk_gate: rtchclk { + #clock-cells = <0>; + compatible = "fh fh-rtc-hclk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x10000000>; + clock-output-names = "rtc_hclk_gate"; + }; + emac_hclk_gate: emachclk { + #clock-cells = <0>; + compatible = "fh fh-emac-hclk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x2000000>; + clock-output-names = "emac_hclk_gate"; + }; + usb_clk: usbclk { + #clock-cells = <0>; + compatible = "fh fh-usb-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x1000000>; + clock-output-names = "usb_clk"; + }; + aes_hclk_gate: aeshclk { + #clock-cells = <0>; + compatible = "fh fh-aes-hclk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x80>; + clock-output-names = "aes_hclk_gate"; + }; + ephy_clk_gate: ephyclk { + #clock-cells = <0>; + compatible = "fh fh-ephy-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x1>; + clock-output-names = "ephy_clk_gate"; + }; + sdc0_clk8x_gate: sdc08xclk { + #clock-cells = <0>; + compatible = "fh fh-sdc08x-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x4>; + clock-output-names = "sdc0_clk8x_gate"; + }; + sdc1_clk8x_gate: sdc18xclk { + #clock-cells = <0>; + compatible = "fh fh-sdc18x-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x8>; + clock-output-names = "sdc1_clk8x_gate"; + }; + mipic_pclk_gate: mipicpclk { + #clock-cells = <0>; + compatible = "fh fh-mipic-pclk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x10>; + clock-output-names = "mipic_pclk_gate"; + }; + gpio0_pclk_gate: gpio0pclk { + #clock-cells = <0>; + compatible = "fh fh-gpio0-pclk"; + reg = <0x0 0x4>,<0xf0000060 0x4>,<0x0 0x4>; + gate = <0x4000>; + clock-output-names = "gpio0_pclk_gate"; + }; + gpio1_pclk_gate: gpio1pclk { + #clock-cells = <0>; + compatible = "fh fh-gpio1-pclk"; + reg = <0x0 0x4>,<0xf0000060 0x4>,<0x0 0x4>; + gate = <0x40000000>; + clock-output-names = "gpio1_pclk_gate"; + }; + isp_hclk_gate: isphclk { + #clock-cells = <0>; + compatible = "fh fh-isp-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x1000000>; + clock-output-names = "isp_hclk_gate"; + }; + veu_hclk_gate: veuhclk { + #clock-cells = <0>; + compatible = "fh fh-veu-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x2000000>; + clock-output-names = "veu_hclk_gate"; + }; + bgm_hclk_gate: bgmhclk { + #clock-cells = <0>; + compatible = "fh fh-bgm-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x4000000>; + clock-output-names = "bgm_hclk_gate"; + }; + adapt_hclk_gate: adapthclk { + #clock-cells = <0>; + compatible = "fh fh-adapt-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x8000000>; + clock-output-names = "adapt_hclk_gate"; + }; + jpg_hclk_gate: jpghclk { + #clock-cells = <0>; + compatible = "fh fh-jpg-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x10000000>; + clock-output-names = "jpg_hclk_gate"; + }; + jpg_adapt_gate: jpgadaptclk { + #clock-cells = <0>; + compatible = "fh fh-jpg-adapt-clk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x20000000>; + clock-output-names = "jpg_adapt_gate"; + }; + vpu_hclk_gate: vpuhclk { + #clock-cells = <0>; + compatible = "fh fh-vpu-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x40000000>; + clock-output-names = "vpu_hclk_gate"; + }; + sdc0_clk_sample: sdc0clksample { + #clock-cells = <0>; + compatible = "fh fh-sdc0-clk_sample"; + reg = <0xf0000020 0x4>; + mux = <0xf0000>; + clocks = <&sdc0_clk>; + clock-output-names = "sdc0_clk_sample"; + }; + sdc0_clk_drv: sdc0clkdrv { + #clock-cells = <0>; + compatible = "fh fh-sdc0-clk_drv"; + reg = <0xf0000020 0x4>; + mux = <0xf00000>; + clocks = <&sdc0_clk>; + clock-output-names = "sdc0_clk_drv"; + }; + + sdc1_clk_sample: sdc1clksample { + #clock-cells = <0>; + compatible = "fh fh-sdc1-clk_sample"; + reg = <0xf0000020 0x4>; + mux = <0xf00>; + clocks = <&sdc1_clk>; + clock-output-names = "sdc1_clk_sample"; + }; + + sdc1_clk_drv: sdc1clkdrv { + #clock-cells = <0>; + compatible = "fh fh-sdc1-clk_drv"; + reg = <0xf0000020 0x4>; + mux = <0xf000>; + clocks = <&sdc1_clk>; + clock-output-names = "sdc1_clk_drv"; + }; + }; + }; + + usb_otg@e0700000 { + compatible = "fh_usb"; + reg = <0xe0700000 100000>; + interrupts = <39>; + clocks = <&usb_clk>; + dr_mode = "host"; + vbus_pwren = <47>; + clock-names = "otg"; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + }; + + usb2_phy: usbphy { + compatible = "fh,fh-usb2-phy"; + #phy-cells = <0>; + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/fh8858v200_pinctrl.dtsi b/arch/arm/boot/dts/fh8858v200_pinctrl.dtsi new file mode 100644 index 00000000..f4cd0f03 --- /dev/null +++ b/arch/arm/boot/dts/fh8858v200_pinctrl.dtsi @@ -0,0 +1,2379 @@ +/* + * Copyright (C) 2020 Fullhan Micorelectonics Co.,Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + #define PUPD_NONE (0) + #define PUPD_UP (1) + #define PUPD_DOWN (2) +*/ + +/ { + pinctrl: pinctrl@f0000080 { + compatible = "fh,fh-pinctrl"; + reg = <0xf0000080 0x104>; + pad-num = <65>; + max-mux = <9>; + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_AC_MCLK + &pinctrl_ETH + &pinctrl_I2C0 + &pinctrl_PWM2 + &pinctrl_PWM3 + &pinctrl_PWM4 + &pinctrl_PWM5 + &pinctrl_PWM6 + &pinctrl_PWM7 + &pinctrl_PWM8 + &pinctrl_PWM9 + &pinctrl_SADC_XAIN0 + &pinctrl_SADC_XAIN1 + &pinctrl_SADC_XAIN2 + &pinctrl_SADC_XAIN3 + &pinctrl_SD0_NO_WP + &pinctrl_SD1_NO_WP + &pinctrl_SENSOR_CLK + &pinctrl_SSI0_4BIT + &pinctrl_SSI1 + &pinctrl_UART0 + &pinctrl_UART1 + &pinctrl_GPIO13 + &pinctrl_GPIO28 + &pinctrl_GPIO29 + &pinctrl_GPIO30 + &pinctrl_GPIO31 + &pinctrl_GPIO32 + &pinctrl_GPIO43 + &pinctrl_GPIO44 + &pinctrl_GPIO47 + &pinctrl_GPIO48 + &pinctrl_GPIO49 + &pinctrl_GPIO50 + &pinctrl_GPIO51 + &pinctrl_GPIO52 + &pinctrl_GPIO53 + &pinctrl_GPIO54 + &pinctrl_GPIO55 + &pinctrl_GPIO56 + + &pinctrl_GPIO45 + &pinctrl_GPIO46 + >; + pinctrl_groups { + pinctrl_ACI2S: ACI2S { + fh,pins = < + &mux_AC_I2S_CLK 0 + &mux_AC_I2S_DI 0 + &mux_AC_I2S_DO 0 + &mux_AC_I2S_WS 0 + &mux_AC_MCLK 0 + >; + }; + pinctrl_AC_MCLK: AC_MCLK { + fh,pins = < + &mux_AC_MCLK 0 + >; + }; + pinctrl_ARCJTAG: ARCJTAG { + fh,pins = < + &mux_ARC_JTAG_TCK 0 + &mux_ARC_JTAG_TDI 0 + &mux_ARC_JTAG_TDO 0 + &mux_ARC_JTAG_TMS 0 + &mux_ARC_JTAG_TRSTN 0 + >; + }; + pinctrl_ARMJTAG: ARMJTAG { + fh,pins = < + &mux_ARM_JTAG_TCK 0 + &mux_ARM_JTAG_TDI 0 + &mux_ARM_JTAG_TDO 0 + &mux_ARM_JTAG_TMS 0 + &mux_ARM_JTAG_TRSTN 0 + >; + }; + pinctrl_DWI2S: DWI2S { + fh,pins = < + &mux_DW_I2S_CLK 0 + &mux_DW_I2S_DI 0 + &mux_DW_I2S_DO 0 + &mux_DW_I2S_WS 0 + >; + }; + pinctrl_ETH: ETH { + fh,pins = < + &mux_ETH_LINK_ACT 1 + &mux_ETH_LINK_STA 1 + >; + }; + pinctrl_I2C0: I2C0 { + fh,pins = < + &mux_I2C0_SCL 0 + &mux_I2C0_SDA 0 + >; + }; + pinctrl_I2C1: I2C1 { + fh,pins = < + &mux_I2C1_SCL 2 + &mux_I2C1_SDA 2 + >; + }; + pinctrl_I2C2: I2C2 { + fh,pins = < + &mux_I2C2_SCL 1 + &mux_I2C2_SDA 1 + >; + }; + pinctrl_PAEJTAG: PAEJTAG { + fh,pins = < + &mux_PAE_JTAG_TCK 0 + &mux_PAE_JTAG_TDI 0 + &mux_PAE_JTAG_TDO 0 + &mux_PAE_JTAG_TMS 0 + &mux_PAE_JTAG_TRSTN 0 + >; + }; + pinctrl_PWM0: PWM0 { + fh,pins = < + &mux_PWM0 0 + >; + }; + pinctrl_PWM1: PWM1 { + fh,pins = < + &mux_PWM1 0 + >; + }; + pinctrl_PWM10: PWM10 { + fh,pins = < + &mux_PWM10 0 + >; + }; + pinctrl_PWM11: PWM11 { + fh,pins = < + &mux_PWM11 0 + >; + }; + pinctrl_PWM2: PWM2 { + fh,pins = < + &mux_PWM2 0 + >; + }; + pinctrl_PWM3: PWM3 { + fh,pins = < + &mux_PWM3 0 + >; + }; + pinctrl_PWM4: PWM4 { + fh,pins = < + &mux_PWM4 0 + >; + }; + pinctrl_PWM5: PWM5 { + fh,pins = < + &mux_PWM5 0 + >; + }; + pinctrl_PWM6: PWM6 { + fh,pins = < + &mux_PWM6 1 + >; + }; + pinctrl_PWM7: PWM7 { + fh,pins = < + &mux_PWM7 1 + >; + }; + pinctrl_PWM8: PWM8 { + fh,pins = < + &mux_PWM8 1 + >; + }; + pinctrl_PWM9: PWM9 { + fh,pins = < + &mux_PWM9 1 + >; + }; + pinctrl_RMII: RMII { + fh,pins = < + &mux_MAC_MDC 0 + &mux_MAC_MDIO 0 + &mux_MAC_REF_CLK 0 + &mux_MAC_RMII_CLK 0 + &mux_MAC_RXDV 0 + &mux_MAC_RXD_0 0 + &mux_MAC_RXD_1 0 + &mux_MAC_TXD_0 0 + &mux_MAC_TXD_1 0 + &mux_MAC_TXEN 0 + >; + }; + pinctrl_RTC: RTC { + fh,pins = < + &mux_RTC_CLK 0 + >; + }; + pinctrl_SADC_XAIN0: SADC_XAIN0 { + fh,pins = < + &mux_SADC_XAIN0 0 + >; + }; + pinctrl_SADC_XAIN1: SADC_XAIN1 { + fh,pins = < + &mux_SADC_XAIN1 0 + >; + }; + pinctrl_SADC_XAIN2: SADC_XAIN2 { + fh,pins = < + &mux_SADC_XAIN2 0 + >; + }; + pinctrl_SADC_XAIN3: SADC_XAIN3 { + fh,pins = < + &mux_SADC_XAIN3 0 + >; + }; + pinctrl_SD0: SD0 { + fh,pins = < + &mux_SD0_CD 0 + &mux_SD0_CLK 0 + &mux_SD0_CMD_RSP 0 + &mux_SD0_DATA_0 0 + &mux_SD0_DATA_1 0 + &mux_SD0_DATA_2 0 + &mux_SD0_DATA_3 0 + >; + }; + pinctrl_SD0_1BIT_NO_WP: SD0_1BIT_NO_WP { + fh,pins = < + &mux_SD0_CD 0 + &mux_SD0_CLK 0 + &mux_SD0_CMD_RSP 0 + &mux_SD0_DATA_0 0 + >; + }; + pinctrl_SD0_NO_WP: SD0_NO_WP { + fh,pins = < + &mux_SD0_CD 0 + &mux_SD0_CLK 0 + &mux_SD0_CMD_RSP 0 + &mux_SD0_DATA_0 0 + &mux_SD0_DATA_1 0 + &mux_SD0_DATA_2 0 + &mux_SD0_DATA_3 0 + >; + }; + pinctrl_SD0_WIFI: SD0_WIFI { + fh,pins = < + &mux_SD0_CLK 0 + &mux_SD0_CMD_RSP 0 + &mux_SD0_DATA_0 0 + &mux_SD0_DATA_1 0 + &mux_SD0_DATA_2 0 + &mux_SD0_DATA_3 0 + >; + }; + pinctrl_SD1: SD1 { + fh,pins = < + &mux_SD1_CD 2 + &mux_SD1_CLK 2 + &mux_SD1_CMD_RSP 2 + &mux_SD1_DATA_0 2 + &mux_SD1_DATA_1 2 + &mux_SD1_DATA_2 2 + &mux_SD1_DATA_3 2 + >; + }; + pinctrl_SD1_1BIT_NO_WP: SD1_1BIT_NO_WP { + fh,pins = < + &mux_SD1_CD 2 + &mux_SD1_CLK 2 + &mux_SD1_CMD_RSP 2 + &mux_SD1_DATA_0 2 + >; + }; + pinctrl_SD1_NO_WP: SD1_NO_WP { + fh,pins = < + &mux_SD1_CD 2 + &mux_SD1_CLK 2 + &mux_SD1_CMD_RSP 2 + &mux_SD1_DATA_0 2 + &mux_SD1_DATA_1 2 + &mux_SD1_DATA_2 2 + &mux_SD1_DATA_3 2 + >; + }; + pinctrl_SD1_WIFI: SD1_WIFI { + fh,pins = < + &mux_SD1_CLK 2 + &mux_SD1_CMD_RSP 2 + &mux_SD1_DATA_0 2 + &mux_SD1_DATA_1 2 + &mux_SD1_DATA_2 2 + &mux_SD1_DATA_3 2 + >; + }; + pinctrl_SENSOR_CLK: SENSOR_CLK { + fh,pins = < + &mux_SENSOR_CLK 0 + >; + }; + pinctrl_SSI0: SSI0 { + fh,pins = < + &mux_GPIO6 0 + &mux_SSI0_CLK 0 + &mux_SSI0_RXD 0 + &mux_SSI0_TXD 0 + >; + }; + pinctrl_SSI0_4BIT: SSI0_4BIT { + fh,pins = < + &mux_GPIO6 0 + &mux_SSI0_CLK 0 + &mux_SSI0_D2 0 + &mux_SSI0_D3 0 + &mux_SSI0_RXD 0 + &mux_SSI0_TXD 0 + >; + }; + pinctrl_SSI1: SSI1 { + fh,pins = < + &mux_GPIO14 0 + &mux_SSI1_CLK 2 + &mux_SSI1_RXD 2 + &mux_SSI1_TXD 2 + >; + }; + pinctrl_SSI2: SSI2 { + fh,pins = < + &mux_SSI2_CLK 1 + &mux_SSI2_CSN_0 1 + &mux_SSI2_RXD 1 + &mux_SSI2_TXD 1 + >; + }; + pinctrl_UART0: UART0 { + fh,pins = < + &mux_UART0_RX 0 + &mux_UART0_TX 0 + >; + }; + pinctrl_UART1: UART1 { + fh,pins = < + &mux_UART1_RX 0 + &mux_UART1_TX 0 + >; + }; + pinctrl_UART2: UART2 { + fh,pins = < + &mux_UART2_RX 0 + &mux_UART2_TX 0 + >; + }; + pinctrl_USB: USB { + fh,pins = < + &mux_USB_PWREN 0 + >; + }; + pinctrl_GPIO0: GPIO0 { + fh,pins = < + &mux_GPIO0 0 + >; + }; + pinctrl_GPIO1: GPIO1 { + fh,pins = < + &mux_GPIO1 0 + >; + }; + pinctrl_GPIO2: GPIO2 { + fh,pins = < + &mux_GPIO2 0 + >; + }; + pinctrl_GPIO3: GPIO3 { + fh,pins = < + &mux_GPIO3 0 + >; + }; + pinctrl_GPIO4: GPIO4 { + fh,pins = < + &mux_GPIO4 0 + >; + }; + pinctrl_GPIO5: GPIO5 { + fh,pins = < + &mux_GPIO5 0 + >; + }; + pinctrl_GPIO6: GPIO6 { + fh,pins = < + &mux_GPIO6 0 + >; + }; + pinctrl_GPIO7: GPIO7 { + fh,pins = < + &mux_GPIO7 0 + >; + }; + pinctrl_GPIO8: GPIO8 { + fh,pins = < + &mux_GPIO8 0 + >; + }; + pinctrl_GPIO9: GPIO9 { + fh,pins = < + &mux_GPIO9 0 + >; + }; + pinctrl_GPIO10: GPIO10 { + fh,pins = < + &mux_GPIO10 0 + >; + }; + pinctrl_GPIO11: GPIO11 { + fh,pins = < + &mux_GPIO11 0 + >; + }; + pinctrl_GPIO12: GPIO12 { + fh,pins = < + &mux_GPIO12 0 + >; + }; + pinctrl_GPIO13: GPIO13 { + fh,pins = < + &mux_GPIO13 0 + >; + }; + pinctrl_GPIO14: GPIO14 { + fh,pins = < + &mux_GPIO14 0 + >; + }; + pinctrl_GPIO15: GPIO15 { + fh,pins = < + &mux_GPIO15 0 + >; + }; + pinctrl_GPIO16: GPIO16 { + fh,pins = < + &mux_GPIO16 0 + >; + }; + pinctrl_GPIO17: GPIO17 { + fh,pins = < + &mux_GPIO17 0 + >; + }; + pinctrl_GPIO18: GPIO18 { + fh,pins = < + &mux_GPIO18 0 + >; + }; + pinctrl_GPIO19: GPIO19 { + fh,pins = < + &mux_GPIO19 0 + >; + }; + pinctrl_GPIO20: GPIO20 { + fh,pins = < + &mux_GPIO20 0 + >; + }; + pinctrl_GPIO21: GPIO21 { + fh,pins = < + &mux_GPIO21 0 + >; + }; + pinctrl_GPIO22: GPIO22 { + fh,pins = < + &mux_GPIO22 0 + >; + }; + pinctrl_GPIO23: GPIO23 { + fh,pins = < + &mux_GPIO23 0 + >; + }; + pinctrl_GPIO24: GPIO24 { + fh,pins = < + &mux_GPIO24 0 + >; + }; + pinctrl_GPIO25: GPIO25 { + fh,pins = < + &mux_GPIO25 0 + >; + }; + pinctrl_GPIO26: GPIO26 { + fh,pins = < + &mux_GPIO26 0 + >; + }; + pinctrl_GPIO27: GPIO27 { + fh,pins = < + &mux_GPIO27 0 + >; + }; + pinctrl_GPIO28: GPIO28 { + fh,pins = < + &mux_GPIO28 0 + >; + }; + pinctrl_GPIO29: GPIO29 { + fh,pins = < + &mux_GPIO29 0 + >; + }; + pinctrl_GPIO30: GPIO30 { + fh,pins = < + &mux_GPIO30 0 + >; + }; + pinctrl_GPIO31: GPIO31 { + fh,pins = < + &mux_GPIO31 0 + >; + }; + pinctrl_GPIO32: GPIO32 { + fh,pins = < + &mux_GPIO32 0 + >; + }; + pinctrl_GPIO33: GPIO33 { + fh,pins = < + &mux_GPIO33 0 + >; + }; + pinctrl_GPIO34: GPIO34 { + fh,pins = < + &mux_GPIO34 0 + >; + }; + pinctrl_GPIO35: GPIO35 { + fh,pins = < + &mux_GPIO35 0 + >; + }; + pinctrl_GPIO36: GPIO36 { + fh,pins = < + &mux_GPIO36 0 + >; + }; + pinctrl_GPIO37: GPIO37 { + fh,pins = < + &mux_GPIO37 0 + >; + }; + pinctrl_GPIO38: GPIO38 { + fh,pins = < + &mux_GPIO38 0 + >; + }; + pinctrl_GPIO39: GPIO39 { + fh,pins = < + &mux_GPIO39 0 + >; + }; + pinctrl_GPIO40: GPIO40 { + fh,pins = < + &mux_GPIO40 0 + >; + }; + pinctrl_GPIO41: GPIO41 { + fh,pins = < + &mux_GPIO41 0 + >; + }; + pinctrl_GPIO42: GPIO42 { + fh,pins = < + &mux_GPIO42 0 + >; + }; + pinctrl_GPIO43: GPIO43 { + fh,pins = < + &mux_GPIO43 0 + >; + }; + pinctrl_GPIO44: GPIO44 { + fh,pins = < + &mux_GPIO44 0 + >; + }; + pinctrl_GPIO45: GPIO45 { + fh,pins = < + &mux_GPIO45 0 + >; + }; + pinctrl_GPIO46: GPIO46 { + fh,pins = < + &mux_GPIO46 0 + >; + }; + pinctrl_GPIO47: GPIO47 { + fh,pins = < + &mux_GPIO47 0 + >; + }; + pinctrl_GPIO48: GPIO48 { + fh,pins = < + &mux_GPIO48 0 + >; + }; + pinctrl_GPIO49: GPIO49 { + fh,pins = < + &mux_GPIO49 0 + >; + }; + pinctrl_GPIO50: GPIO50 { + fh,pins = < + &mux_GPIO50 0 + >; + }; + pinctrl_GPIO51: GPIO51 { + fh,pins = < + &mux_GPIO51 0 + >; + }; + pinctrl_GPIO52: GPIO52 { + fh,pins = < + &mux_GPIO52 0 + >; + }; + pinctrl_GPIO53: GPIO53 { + fh,pins = < + &mux_GPIO53 0 + >; + }; + pinctrl_GPIO54: GPIO54 { + fh,pins = < + &mux_GPIO54 0 + >; + }; + pinctrl_GPIO55: GPIO55 { + fh,pins = < + &mux_GPIO55 0 + >; + }; + pinctrl_GPIO56: GPIO56 { + fh,pins = < + &mux_GPIO56 0 + >; + }; + pinctrl_GPIO57: GPIO57 { + fh,pins = < + &mux_GPIO57 0 + >; + }; + pinctrl_GPIO58: GPIO58 { + fh,pins = < + &mux_GPIO58 0 + >; + }; + pinctrl_GPIO59: GPIO59 { + fh,pins = < + &mux_GPIO59 0 + >; + }; + pinctrl_GPIO60: GPIO60 { + fh,pins = < + &mux_GPIO60 0 + >; + }; + pinctrl_GPIO61: GPIO61 { + fh,pins = < + &mux_GPIO61 0 + >; + }; + pinctrl_GPIO62: GPIO62 { + fh,pins = < + &mux_GPIO62 0 + >; + }; + pinctrl_GPIO63: GPIO63 { + fh,pins = < + &mux_GPIO63 0 + >; + }; + pinctrl_SD1_EMMC: SD1_EMMC { + fh,pins = < + &mux_SD1_CD 3 + &mux_SD1_CLK 3 + &mux_SD1_CMD_RSP 3 + &mux_SD1_DATA_0 3 + &mux_SD1_DATA_1 3 + &mux_SD1_DATA_2 3 + &mux_SD1_DATA_3 3 + >; + }; + }; + pinmux: pinmux { + compatible = "fh,fh-pinmux"; + #list-cells = <1>; + mux_AC_I2S_CLK: AC_I2S_CLK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad39 + >; + }; + mux_AC_I2S_DI: AC_I2S_DI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad38 + >; + }; + mux_AC_I2S_DO: AC_I2S_DO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad37 + >; + }; + mux_AC_I2S_WS: AC_I2S_WS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad40 + >; + }; + mux_AC_MCLK: AC_MCLK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad41 + >; + }; + + mux_ARC_JTAG_TCK: ARC_JTAG_TCK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad55 + >; + }; + mux_ARC_JTAG_TDI: ARC_JTAG_TDI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad54 + >; + }; + mux_ARC_JTAG_TDO: ARC_JTAG_TDO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad53 + >; + }; + mux_ARC_JTAG_TMS: ARC_JTAG_TMS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad56 + >; + }; + mux_ARC_JTAG_TRSTN: ARC_JTAG_TRSTN { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad52 + >; + }; + + mux_ARM_JTAG_TCK: ARM_JTAG_TCK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad40 + >; + }; + mux_ARM_JTAG_TDI: ARM_JTAG_TDI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad39 + >; + }; + mux_ARM_JTAG_TDO: ARM_JTAG_TDO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad38 + >; + }; + mux_ARM_JTAG_TMS: ARM_JTAG_TMS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad41 + >; + }; + mux_ARM_JTAG_TRSTN: ARM_JTAG_TRSTN { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad37 + >; + }; + + mux_DW_I2S_CLK: DW_I2S_CLK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad39 + >; + }; + mux_DW_I2S_DI: DW_I2S_DI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad38 + >; + }; + mux_DW_I2S_DO: DW_I2S_DO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad37 + >; + }; + mux_DW_I2S_WS: DW_I2S_WS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad40 + >; + }; + + mux_ETH_LINK_ACT: ETH_LINK_ACT { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad1 + &pad63 + >; + }; + mux_ETH_LINK_SPD: ETH_LINK_SPD { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad2 + &pad64 + >; + }; + mux_ETH_LINK_STA: ETH_LINK_STA { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad2 + &pad64 + >; + }; + + mux_I2C0_SCL: I2C0_SCL { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad5 + >; + }; + mux_I2C0_SDA: I2C0_SDA { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad6 + >; + }; + + mux_I2C1_SCL: I2C1_SCL { + #list-cells = <1>; + select = <2>; + fh,pads = < + &pad11 + &pad30 + &pad46 + >; + }; + mux_I2C1_SDA: I2C1_SDA { + #list-cells = <1>; + select = <2>; + fh,pads = < + &pad12 + &pad31 + &pad47 + >; + }; + + mux_I2C2_SCL: I2C2_SCL { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad16 + &pad57 + >; + }; + mux_I2C2_SDA: I2C2_SDA { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad17 + &pad58 + >; + }; + + mux_MAC_MDC: MAC_MDC { + #list-cells = <1>; + select = <0>; + ds = <0>; + fh,pads = < + &pad28 + &pad63 + >; + }; + mux_MAC_MDIO: MAC_MDIO { + #list-cells = <1>; + select = <0>; + ds = <0>; + fh,pads = < + &pad29 + &pad64 + >; + }; + mux_MAC_REF_CLK: MAC_REF_CLK { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad21 + >; + }; + mux_MAC_RMII_CLK: MAC_RMII_CLK { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad20 + >; + }; + mux_MAC_RXDV: MAC_RXDV { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad27 + >; + }; + mux_MAC_RXD_0: MAC_RXD_0 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad25 + >; + }; + mux_MAC_RXD_1: MAC_RXD_1 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad26 + >; + }; + mux_MAC_TXD_0: MAC_TXD_0 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad22 + >; + }; + mux_MAC_TXD_1: MAC_TXD_1 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad23 + >; + }; + mux_MAC_TXEN: MAC_TXEN { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad24 + >; + }; + + mux_PAE_JTAG_TCK: PAE_JTAG_TCK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad55 + >; + }; + mux_PAE_JTAG_TDI: PAE_JTAG_TDI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad54 + >; + }; + mux_PAE_JTAG_TDO: PAE_JTAG_TDO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad53 + >; + }; + mux_PAE_JTAG_TMS: PAE_JTAG_TMS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad56 + >; + }; + mux_PAE_JTAG_TRSTN: PAE_JTAG_TRSTN { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad52 + >; + }; + + mux_PWM0: PWM0 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad16 + >; + }; + mux_PWM1: PWM1 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad17 + >; + }; + mux_PWM10: PWM10 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad63 + >; + }; + mux_PWM11: PWM11 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad64 + >; + }; + mux_PWM2: PWM2 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad11 + &pad18 + &pad20 + >; + }; + mux_PWM3: PWM3 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad12 + &pad19 + &pad22 + >; + }; + mux_PWM4: PWM4 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad13 + &pad23 + >; + }; + mux_PWM5: PWM5 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad14 + &pad24 + >; + }; + mux_PWM6: PWM6 { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad25 + &pad37 + >; + }; + mux_PWM7: PWM7 { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad26 + &pad38 + >; + }; + mux_PWM8: PWM8 { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad27 + &pad39 + >; + }; + mux_PWM9: PWM9 { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad28 + &pad40 + >; + }; + + mux_RTC_CLK: RTC_CLK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad64 + >; + }; + + mux_SADC_XAIN0: SADC_XAIN0 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad59 + >; + }; + mux_SADC_XAIN1: SADC_XAIN1 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad60 + >; + }; + mux_SADC_XAIN2: SADC_XAIN2 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad61 + >; + }; + mux_SADC_XAIN3: SADC_XAIN3 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad62 + >; + }; + + mux_SD0_CD: SD0_CD { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad52 + >; + }; + mux_SD0_CLK: SD0_CLK { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad53 + >; + }; + mux_SD0_CMD_RSP: SD0_CMD_RSP { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad54 + >; + }; + mux_SD0_DATA_0: SD0_DATA_0 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad55 + >; + }; + mux_SD0_DATA_1: SD0_DATA_1 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad56 + >; + }; + mux_SD0_DATA_2: SD0_DATA_2 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad57 + >; + }; + mux_SD0_DATA_3: SD0_DATA_3 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad58 + >; + }; + + mux_SD1_CD: SD1_CD { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad10 + &pad22 + &pad31 + &pad41 + &pad63 + >; + }; + mux_SD1_CLK: SD1_CLK { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad9 + &pad20 + &pad30 + &pad42 + >; + }; + mux_SD1_CMD_RSP: SD1_CMD_RSP { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad11 + &pad23 + &pad32 + &pad43 + >; + }; + mux_SD1_DATA_0: SD1_DATA_0 { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad12 + &pad24 + &pad33 + &pad44 + >; + }; + mux_SD1_DATA_1: SD1_DATA_1 { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad13 + &pad25 + &pad34 + &pad45 + >; + }; + mux_SD1_DATA_2: SD1_DATA_2 { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad14 + &pad26 + &pad35 + &pad46 + >; + }; + mux_SD1_DATA_3: SD1_DATA_3 { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad15 + &pad27 + &pad36 + &pad47 + >; + }; + + mux_SENSOR_CLK: SENSOR_CLK { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad7 + >; + }; + + mux_SSI0_CLK: SSI0_CLK { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad42 + >; + }; + mux_SSI0_D2: SSI0_D2 { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad46 + >; + }; + mux_SSI0_D3: SSI0_D3 { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad47 + >; + }; + mux_SSI0_RXD: SSI0_RXD { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad45 + >; + }; + mux_SSI0_TXD: SSI0_TXD { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad44 + >; + }; + + mux_SSI1_CLK: SSI1_CLK { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad11 + &pad37 + &pad48 + &pad53 + >; + }; + mux_SSI1_RXD: SSI1_RXD { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad14 + &pad40 + &pad51 + &pad55 + >; + }; + mux_SSI1_TXD: SSI1_TXD { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad13 + &pad39 + &pad50 + &pad54 + >; + }; + + mux_SSI2_CLK: SSI2_CLK { + #list-cells = <1>; + select = <1>; + ds = <2>; + fh,pads = < + &pad37 + &pad48 + >; + }; + mux_SSI2_CSN_0: SSI2_CSN_0 { + #list-cells = <1>; + select = <1>; + ds = <2>; + fh,pads = < + &pad38 + &pad49 + >; + }; + mux_SSI2_RXD: SSI2_RXD { + #list-cells = <1>; + select = <1>; + ds = <2>; + fh,pads = < + &pad40 + &pad51 + >; + }; + mux_SSI2_TXD: SSI2_TXD { + #list-cells = <1>; + select = <1>; + ds = <2>; + fh,pads = < + &pad39 + &pad50 + >; + }; + + mux_UART0_RX: UART0_RX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad4 + >; + }; + mux_UART0_TX: UART0_TX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad3 + >; + }; + + mux_UART1_RX: UART1_RX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad10 + &pad33 + &pad47 + >; + }; + mux_UART1_TX: UART1_TX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad9 + &pad32 + &pad46 + >; + }; + + mux_UART2_RX: UART2_RX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad14 + &pad17 + &pad35 + &pad58 + >; + }; + mux_UART2_TX: UART2_TX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad13 + &pad16 + &pad34 + &pad57 + >; + }; + + mux_USB_PWREN: USB_PWREN { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad15 + &pad41 + >; + }; + + mux_GPIO0: GPIO0 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad37 + >; + }; + mux_GPIO1: GPIO1 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad38 + >; + }; + mux_GPIO2: GPIO2 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad39 + >; + }; + mux_GPIO3: GPIO3 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad40 + >; + }; + mux_GPIO4: GPIO4 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad41 + >; + }; + mux_GPIO5: GPIO5 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad42 + >; + }; + mux_GPIO6: GPIO6 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad43 + >; + }; + mux_GPIO7: GPIO7 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad44 + >; + }; + mux_GPIO8: GPIO8 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad45 + >; + }; + mux_GPIO9: GPIO9 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad46 + >; + }; + mux_GPIO10: GPIO10 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad47 + >; + }; + mux_GPIO11: GPIO11 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad48 + >; + }; + mux_GPIO12: GPIO12 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad7 + >; + }; + mux_GPIO13: GPIO13 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad8 + >; + }; + mux_GPIO14: GPIO14 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad49 + >; + }; + mux_GPIO15: GPIO15 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad50 + >; + }; + mux_GPIO16: GPIO16 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad51 + >; + }; + mux_GPIO17: GPIO17 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad52 + >; + }; + mux_GPIO18: GPIO18 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad53 + >; + }; + mux_GPIO19: GPIO19 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad54 + >; + }; + mux_GPIO20: GPIO20 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad55 + >; + }; + mux_GPIO21: GPIO21 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad56 + >; + }; + mux_GPIO22: GPIO22 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad57 + >; + }; + mux_GPIO23: GPIO23 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad58 + >; + }; + mux_GPIO24: GPIO24 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad61 + >; + }; + mux_GPIO25: GPIO25 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad62 + >; + }; + mux_GPIO26: GPIO26 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad59 + >; + }; + mux_GPIO27: GPIO27 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad60 + >; + }; + mux_GPIO28: GPIO28 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad63 + >; + }; + mux_GPIO29: GPIO29 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad64 + >; + }; + mux_GPIO30: GPIO30 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad0 + >; + }; + mux_GPIO31: GPIO31 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad1 + >; + }; + mux_GPIO32: GPIO32 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad2 + >; + }; + mux_GPIO33: GPIO33 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad3 + >; + }; + mux_GPIO34: GPIO34 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad4 + >; + }; + mux_GPIO35: GPIO35 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad5 + >; + }; + mux_GPIO36: GPIO36 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad6 + >; + }; + mux_GPIO37: GPIO37 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad11 + >; + }; + mux_GPIO38: GPIO38 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad12 + >; + }; + mux_GPIO39: GPIO39 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad9 + >; + }; + mux_GPIO40: GPIO40 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad10 + >; + }; + mux_GPIO41: GPIO41 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad13 + >; + }; + mux_GPIO42: GPIO42 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad14 + >; + }; + mux_GPIO43: GPIO43 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad16 + >; + }; + mux_GPIO44: GPIO44 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad17 + >; + }; + mux_GPIO45: GPIO45 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad18 + >; + }; + mux_GPIO46: GPIO46 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad19 + >; + }; + mux_GPIO47: GPIO47 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad15 + >; + }; + mux_GPIO48: GPIO48 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad20 + >; + }; + mux_GPIO49: GPIO49 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad22 + >; + }; + mux_GPIO50: GPIO50 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad23 + >; + }; + mux_GPIO51: GPIO51 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad24 + >; + }; + mux_GPIO52: GPIO52 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad25 + >; + }; + mux_GPIO53: GPIO53 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad26 + >; + }; + mux_GPIO54: GPIO54 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad27 + >; + }; + mux_GPIO55: GPIO55 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad28 + >; + }; + mux_GPIO56: GPIO56 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad29 + >; + }; + mux_GPIO57: GPIO57 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad30 + >; + }; + mux_GPIO58: GPIO58 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad31 + >; + }; + mux_GPIO59: GPIO59 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad32 + >; + }; + mux_GPIO60: GPIO60 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad33 + >; + }; + mux_GPIO61: GPIO61 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad34 + >; + }; + mux_GPIO62: GPIO62 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad35 + >; + }; + mux_GPIO63: GPIO63 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad36 + >; + }; + }; + pinpad: pinpad { + compatible = "fh,fh-pinpad"; + pad0: PAD_BOOT_MODE_CFG { + index = <0>; + funcs = "GPIO30"; + pupd = <1>; + ds = <0>; + }; + pad1: PAD_BOOT_SEL1_CFG { + index = <1>; + funcs = "GPIO31", "ETH_LINK_ACT"; + pupd = <1>; + ds = <0>; + }; + pad2: PAD_BOOT_SEL0_CFG { + index = <2>; + funcs = "GPIO32", "ETH_LINK_STA", "ETH_LINK_SPD"; + pupd = <1>; + ds = <0>; + }; + pad3: PAD_UART0_TX_CFG { + index = <3>; + funcs = "UART0_TX", "GPIO33"; + pupd = <0>; + ds = <0>; + }; + pad4: PAD_UART0_RX_CFG { + index = <4>; + funcs = "UART0_RX", "GPIO34"; + pupd = <0>; + ds = <0>; + }; + pad5: PAD_I2C0_SCL_CFG { + index = <5>; + funcs = "I2C0_SCL", "GPIO35"; + pupd = <1>; + ds = <0>; + }; + pad6: PAD_I2C0_SDA_CFG { + index = <6>; + funcs = "I2C0_SDA", "GPIO36"; + pupd = <1>; + ds = <0>; + }; + pad7: PAD_SENSOR_CLK_CFG { + index = <7>; + funcs = "SENSOR_CLK", "GPIO12"; + pupd = <0>; + ds = <0>; + }; + pad8: PAD_SENSOR_RSTN_CFG { + index = <8>; + funcs = "GPIO13"; + pupd = <0>; + ds = <0>; + }; + pad9: PAD_UART1_TX_CFG { + index = <9>; + funcs = "UART1_TX", "GPIO39", "", "SD1_CLK", "", "", + "TEST_O_INT_RMII_CLK"; + pupd = <0>; + ds = <0>; + }; + pad10: PAD_UART1_RX_CFG { + index = <10>; + funcs = "UART1_RX", "GPIO40", "", "SD1_CD", "", "", + "TEST_INT_RMII_TXD_0"; + pupd = <0>; + ds = <0>; + }; + pad11: PAD_I2C1_SCL_CFG { + index = <11>; + funcs = "I2C1_SCL", "GPIO37", "PWM2", "SD1_CMD_RSP", "", + "SSI1_CLK", "TEST_INT_RMII_TXD_1"; + pupd = <0>; + ds = <0>; + }; + pad12: PAD_I2C1_SDA_CFG { + index = <12>; + funcs = "I2C1_SDA", "GPIO38", "PWM3", "SD1_DATA_0", "", + "SSI1_CSN_0", "TEST_INT_RMII_TXEN"; + pupd = <0>; + ds = <0>; + }; + pad13: PAD_UART2_TX_CFG { + index = <13>; + funcs = "UART2_TX", "GPIO41", "PWM4", "SD1_DATA_1", "", + "SSI1_TXD", "TEST_O_INT_RMII_RXD_0"; + pupd = <0>; + ds = <0>; + }; + pad14: PAD_UART2_RX_CFG { + index = <14>; + funcs = "UART2_RX", "GPIO42", "PWM5", "SD1_DATA_2", "", + "SSI1_RXD", "TEST_O_INT_RMII_RXD_1"; + pupd = <0>; + ds = <0>; + }; + pad15: PAD_USB_PWREN_CFG { + index = <15>; + funcs = "USB_PWREN", "GPIO47", "", "SD1_DATA_3", "", "", + "TEST_O_INT_RMII_CRSDV"; + pupd = <0>; + ds = <0>; + }; + pad16: PAD_PWM0_CFG { + index = <16>; + funcs = "PWM0", "GPIO43", "I2C2_SCL", "UART2_TX", "", "", + "TEST_O_INT_RMII_TXD_0"; + pupd = <0>; + ds = <0>; + }; + pad17: PAD_PWM1_CFG { + index = <17>; + funcs = "PWM1", "GPIO44", "I2C2_SDA", "UART2_RX", "", "", + "TEST_O_INT_RMII_TXD_1"; + pupd = <0>; + ds = <0>; + }; + pad18: PAD_PWM2_CFG { + index = <18>; + funcs = "PWM2", "GPIO45"; + pupd = <0>; + ds = <0>; + }; + pad19: PAD_PWM3_CFG { + index = <19>; + funcs = "PWM3", "GPIO46"; + pupd = <0>; + ds = <0>; + }; + pad20: PAD_MAC_RMII_CLK_CFG { + index = <20>; + funcs = "MAC_RMII_CLK", "GPIO48", "SD1_CLK", "PWM2"; + pupd = <0>; + ds = <0>; + }; + pad21: PAD_MAC_REF_CLK_CFG { + index = <21>; + funcs = "MAC_REF_CLK"; + pupd = <0>; + ds = <2>; + }; + pad22: PAD_MAC_TXD0_CFG { + index = <22>; + funcs = "MAC_TXD_0", "GPIO49", "SD1_CD", "PWM3"; + pupd = <0>; + ds = <0>; + }; + pad23: PAD_MAC_TXD1_CFG { + index = <23>; + funcs = "MAC_TXD_1", "GPIO50", "SD1_CMD_RSP", "PWM4"; + pupd = <0>; + ds = <0>; + }; + pad24: PAD_MAC_TXEN_CFG { + index = <24>; + funcs = "MAC_TXEN", "GPIO51", "SD1_DATA_0", "PWM5"; + pupd = <0>; + ds = <0>; + }; + pad25: PAD_MAC_RXD0_CFG { + index = <25>; + funcs = "MAC_RXD_0", "GPIO52", "SD1_DATA_1", "PWM6"; + pupd = <0>; + ds = <0>; + }; + pad26: PAD_MAC_RXD1_CFG { + index = <26>; + funcs = "MAC_RXD_1", "GPIO53", "SD1_DATA_2", "PWM7"; + pupd = <0>; + ds = <0>; + }; + pad27: PAD_MAC_RXDV_CFG { + index = <27>; + funcs = "MAC_RXDV", "GPIO54", "SD1_DATA_3", "PWM8"; + pupd = <0>; + ds = <0>; + }; + pad28: PAD_MAC_MDC_CFG { + index = <28>; + funcs = "MAC_MDC", "GPIO55", "", "PWM9"; + pupd = <0>; + ds = <0>; + }; + pad29: PAD_MAC_MDIO_CFG { + index = <29>; + funcs = "MAC_MDIO", "GPIO56"; + pupd = <0>; + ds = <0>; + }; + pad30: PAD_SD1_CLK_CFG { + index = <30>; + funcs = "SD1_CLK", "GPIO57", "I2C1_SCL"; + pupd = <0>; + ds = <0>; + }; + pad31: PAD_SD1_CD_CFG { + index = <31>; + funcs = "SD1_CD", "GPIO58", "I2C1_SDA"; + pupd = <0>; + ds = <0>; + }; + pad32: PAD_SD1_CMD_RSP_CFG { + index = <32>; + funcs = "SD1_CMD_RSP", "GPIO59", "UART1_TX"; + pupd = <0>; + ds = <0>; + }; + pad33: PAD_SD1_DATA_0_CFG { + index = <33>; + funcs = "SD1_DATA_0", "GPIO60", "UART1_RX"; + pupd = <0>; + ds = <0>; + }; + pad34: PAD_SD1_DATA_1_CFG { + index = <34>; + funcs = "SD1_DATA_1", "GPIO61", "UART2_TX"; + pupd = <0>; + ds = <0>; + }; + pad35: PAD_SD1_DATA_2_CFG { + index = <35>; + funcs = "SD1_DATA_2", "GPIO62", "UART2_RX"; + pupd = <0>; + ds = <0>; + }; + pad36: PAD_SD1_DATA_3_CFG { + index = <36>; + funcs = "SD1_DATA_3", "GPIO63"; + pupd = <0>; + ds = <0>; + }; + pad37: PAD_GPIO_0_CFG { + index = <37>; + funcs = "ARM_JTAG_TRSTN", "GPIO0", "AC_I2S_DO", "DW_I2S_DO", + "SSI1_CLK", "SSI2_CLK", "ACIP_ADDAT", "PWM6", + "TEST_O_INT_SMI_MDC"; + pupd = <0>; + ds = <0>; + }; + pad38: PAD_GPIO_1_CFG { + index = <38>; + funcs = "ARM_JTAG_TDO", "GPIO1", "AC_I2S_DI", "DW_I2S_DI", + "SSI1_CSN_0", "SSI2_CSN_0", "ACIP_DADAT", "PWM7", + "TEST_O_INT_SMI_MDIO_I"; + pupd = <0>; + ds = <0>; + }; + pad39: PAD_GPIO_2_CFG { + index = <39>; + funcs = "ARM_JTAG_TDI", "GPIO2", "AC_I2S_CLK", "DW_I2S_CLK", + "SSI1_TXD", "SSI2_TXD", "ACIP_ADBCLK", "PWM8", + "TEST_O_INT_SMI_MDIO_O"; + pupd = <0>; + ds = <0>; + }; + pad40: PAD_GPIO_3_CFG { + index = <40>; + funcs = "ARM_JTAG_TCK", "GPIO3", "AC_I2S_WS", "DW_I2S_WS", + "SSI1_RXD", "SSI2_RXD", "ACIP_ADLRC", "PWM9", + "TEST_I_INT_SMI_MDIO_I"; + pupd = <0>; + ds = <0>; + }; + pad41: PAD_GPIO_4_CFG { + index = <41>; + funcs = "ARM_JTAG_TMS", "GPIO4", "AC_MCLK", "USB_PWREN", + "SD1_CD", "TEST_I_INT_SMI_MDC"; + pupd = <0>; + ds = <0>; + }; + pad42: PAD_SSI0_CLK_CFG { + index = <42>; + funcs = "SSI0_CLK", "GPIO5", "", "", "SD1_CLK"; + pupd = <0>; + ds = <2>; + }; + pad43: PAD_SSI0_CSN_0_CFG { + index = <43>; + funcs = "SSI0_CSN_0", "GPIO6", "", "", "SD1_CMD_RSP"; + pupd = <0>; + ds = <2>; + }; + pad44: PAD_SSI0_TXD_CFG { + index = <44>; + funcs = "SSI0_TXD", "GPIO7", "", "", "SD1_DATA_0"; + pupd = <0>; + ds = <2>; + }; + pad45: PAD_SSI0_RXD_CFG { + index = <45>; + funcs = "SSI0_RXD", "GPIO8", "", "", "SD1_DATA_1"; + pupd = <0>; + ds = <2>; + }; + pad46: PAD_SSI0_D2_CFG { + index = <46>; + funcs = "SSI0_D2", "GPIO9", "UART1_TX", "I2C1_SCL", + "SD1_DATA_2"; + pupd = <0>; + ds = <2>; + }; + pad47: PAD_SSI0_D3_CFG { + index = <47>; + funcs = "SSI0_D3", "GPIO10", "UART1_RX", "I2C1_SDA", + "SD1_DATA_3"; + pupd = <0>; + ds = <2>; + }; + pad48: PAD_SSI1_CLK_CFG { + index = <48>; + funcs = "SSI1_CLK", "GPIO11", "SSI2_CLK"; + pupd = <0>; + ds = <0>; + }; + pad49: PAD_SSI1_CSN_0_CFG { + index = <49>; + funcs = "SSI1_CSN_0", "GPIO14", "SSI2_CSN_0"; + pupd = <0>; + ds = <0>; + }; + pad50: PAD_SSI1_TXD_CFG { + index = <50>; + funcs = "SSI1_TXD", "GPIO15", "SSI2_TXD"; + pupd = <0>; + ds = <0>; + }; + pad51: PAD_SSI1_RXD_CFG { + index = <51>; + funcs = "SSI1_RXD", "GPIO16", "SSI2_RXD"; + pupd = <0>; + ds = <0>; + }; + pad52: PAD_SD0_CD_CFG { + index = <52>; + funcs = "SD0_CD", "GPIO17", "", "ARC_JTAG_TRSTN", + "PAE_JTAG_TRSTN"; + pupd = <0>; + ds = <0>; + }; + pad53: PAD_SD0_CLK_CFG { + index = <53>; + funcs = "SD0_CLK", "GPIO18", "SSI1_CLK", "ARC_JTAG_TDO", + "PAE_JTAG_TDO"; + pupd = <0>; + ds = <2>; + }; + pad54: PAD_SD0_CMD_RSP_CFG { + index = <54>; + funcs = "SD0_CMD_RSP", "GPIO19", "SSI1_TXD", "ARC_JTAG_TDI", + "PAE_JTAG_TDI"; + pupd = <0>; + ds = <2>; + }; + pad55: PAD_SD0_DATA_0_CFG { + index = <55>; + funcs = "SD0_DATA_0", "GPIO20", "SSI1_RXD", "ARC_JTAG_TCK", + "PAE_JTAG_TCK"; + pupd = <0>; + ds = <2>; + }; + pad56: PAD_SD0_DATA_1_CFG { + index = <56>; + funcs = "SD0_DATA_1", "GPIO21", "SSI1_CSN_0", "ARC_JTAG_TMS", + "PAE_JTAG_TMS"; + pupd = <0>; + ds = <2>; + }; + pad57: PAD_SD0_DATA_2_CFG { + index = <57>; + funcs = "SD0_DATA_2", "GPIO22", "", "UART2_TX", "I2C2_SCL", "", + "ACIP_DABCLK"; + pupd = <0>; + ds = <2>; + }; + pad58: PAD_SD0_DATA_3_CFG { + index = <58>; + funcs = "SD0_DATA_3", "GPIO23", "SSI1_CSN_0", "UART2_RX", + "I2C2_SDA", "", "ACIP_DALRC"; + pupd = <0>; + ds = <2>; + }; + pad59: PAD_SADC_XAIN0_CFG { + index = <59>; + funcs = "SADC_XAIN0", "GPIO26"; + pupd = <0>; + ds = <0>; + }; + pad60: PAD_SADC_XAIN1_CFG { + index = <60>; + funcs = "SADC_XAIN1", "GPIO27"; + pupd = <0>; + ds = <0>; + }; + pad61: PAD_SADC_XAIN2_CFG { + index = <61>; + funcs = "SADC_XAIN2", "GPIO24"; + pupd = <0>; + ds = <0>; + }; + pad62: PAD_SADC_XAIN3_CFG { + index = <62>; + funcs = "SADC_XAIN3", "GPIO25"; + pupd = <0>; + ds = <0>; + }; + pad63: PAD_GPIO_28_CFG { + index = <63>; + funcs = "GPIO28", "", "ETH_LINK_ACT", "PWM10", + "USB_DBG_CLK", "SD1_CD", "TEST_O_INT_RMII_TXEN", + "MAC_MDC"; + pupd = <0>; + ds = <0>; + }; + pad64: PAD_GPIO_29_CFG { + index = <64>; + funcs = "GPIO29", "", "ETH_LINK_STA", "PWM11", "RTC_CLK", + "ETH_LINK_SPD", "TEST_O_INT_SMI_MDIO_OE", + "MAC_MDIO"; + pupd = <0>; + ds = <0>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/fh8858v210.dts b/arch/arm/boot/dts/fh8858v210.dts new file mode 100644 index 00000000..5a16fce3 --- /dev/null +++ b/arch/arm/boot/dts/fh8858v210.dts @@ -0,0 +1,956 @@ +/* + * Copyright (C) 2017 Fullhan Micorelectonics Co.,Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "skeleton.dtsi" +/include/ "fh8858v210_pinctrl.dtsi" +/ { + + + model = "FULLHAN FH8858V210"; + compatible = "fh,fh8858v210"; + interrupt-parent = <&intc>; + aliases { + i2c0 = &i2cbus0; + i2c1 = &i2cbus1; + i2c2 = &i2cbus2; + spi0 = &spi_bus0; + spi1 = &spi_bus1; + ttyS0 = &serial0; + ttyS1 = &serial1; + ttyS2 = &serial2; + }; + + cpus { + cpu@0 { + device_type = "cpu"; + compatible = "arm,arm1176jzf-s"; + }; + }; + + chosen { + bootargs = "coherent_pool=2M"; + }; + + intc: interrupt-controller@E0200000 { + compatible = "fh,fh-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xE0200000 0x1000>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pmu@f0000000 { + compatible = "fh,fh-pmu"; + reg = <0xf0000000 0x2100>; + SWRST_MAIN_CTRL = <0x40>; + }; + timer0: timer@f0c00000 { + compatible = "fh,fh-timer"; + interrupts = <3>; + clock-frequency = <1000000>; + reg = <0xf0c00000 0x14>; + }; + + timer1: timer@f0c00014 { + compatible = "fh,fh-timer"; + interrupts = <3>; + clock-frequency = <1000000>; + reg = <0xf0c00014 0x14>; + }; + + gpio0: gpio@f0300000 { + compatible = "fh,fh-gpio"; + reg = <0xf0300000 0x1000>; + #gpio_controller; + interrupt-controller; + interrupt-parent = <&intc>; + interrupts = <26>; + id = <0>; + ngpio = <32>; + base = <0>; + }; + + gpio1: gpio@f4000000 { + compatible = "fh,fh-gpio"; + reg = <0xf4000000 0x1000>; + #gpio_controller; + interrupt-controller; + interrupt-parent = <&intc>; + interrupts = <40>; + id = <1>; + ngpio = <32>; + base = <32>; + }; + + fhdma0: dma@e0300000 { + compatible = "fh,fh-axi-dmac"; + reg = <0xe0300000 0x1000>; + interrupts = <23>; + chan_allocation_order = <0>; + chan_priority = <1>; + block_size = <0x800>; + data_width = <2 0 0 0>; + clocks = <&ahb_clk>; + }; + + aes: aes@0xe8200000 { + compatible = "fh,fh-aes"; + reg = <0xe8200000 0x1000>; + interrupts = <16>; + }; + rtc: rtc@f1500000 { + compatible = "fh,fh_rtc"; + reg = <0xf1500000 0x1000>; + interrupts = <33>; + clocks = <&rtc_hclk_gate>; + lut_cof = <71>; + lut_offset = <0xf6>; + tsensor_cp_default_out = <0x9cc>; + }; + sadc: sadc@f1200000 { + compatible = "fh,fh-sadc"; + reg = <0xf1200000 0x1000>; + interrupts = <20>; + ref-vol = <1800>; + active-bit = <0xfff>; + }; + efuse: efuse@0xf1600000 { + compatible = "fh,fh-efuse"; + reg = <0xf1600000 0x1000>; + key_switch = "enable"; + indep_power = "enable"; + }; + fh_perf: fh_perf@0xf0002018 { + compatible = "fh,fh-perf"; + reg = <0xf0000000 0x4000>; + interrupts = < 5 >; + + }; + spi_bus0: spi@f0500000 { + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + compatible = "fh,fh-spi"; + reg = <0xf0500000 0x4000>; + clk_in = <100000000>; + clock_source = <100000000>; + clock_source_num = <1>; + num-cs = <2>; + cs0_gpio = <6>; + cs1_gpio = <55>; + dma_enable = "disable"; + swap_support = "enable"; + rx_hs_no = <4>; + tx_hs_no = <5>; + bus_no = <0>; + multi_wire_size = <2>; + clk_name = "spi0_clk"; + rx_dma_channel = <0>; + tx_dma_channel = <1>; + increase_support = "disable"; + data_field_size = <0x1000>; + data_reg_offset = <0x1000>; + dma_protctl_enable = "disable"; + dma_protctl_data = <6>; + dma_master_sel_enable = "disable"; + dma_master_ctl_sel = <0>; + dma_master_mem_sel = <0>; + spidma_xfer_mode = "rx_only"; + interrupts = <28>; + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fh,m25p80"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + reg = <0x0 0>; //first value means which slave bind to the master. 0 means chip 0. 1 means chip 1 + partition@0 { + reg = <0x0 0x40000>; + label = "bootstrap"; + }; + partition@40000 { + reg = <0x40000 0x10000>; + label = "uboot-env"; + }; + partition@50000 { + reg = <0x50000 0x30000>; + label = "uboot"; + }; + partition@80000 { + reg = <0x80000 0x400000>; + label = "kernel"; + }; + partition@480000 { + reg = <0x480000 0x80000>; + label = "rootfs"; + }; + partition@500000 { + reg = <0x500000 0x300000>; + label = "app"; + }; + + }; + spidev0: spi@0 { + compatible = "rohm,dh2228fv"; + reg = <0x1 0>; + spi-max-frequency = <50000000>; + }; + }; + spi_bus1: spi@f0600000 { + #address-cells = <1>; + #size-cells = <1>; + status = "okay"; + compatible = "fh,fh-spi"; + reg = <0xf0600000 0x4000>; + clk_in = <100000000>; + clock_source = <100000000>; + clock_source_num = <1>; + num-cs = <2>; + cs0_gpio = <14>; + cs1_gpio = <57>; + dma_enable = "disable"; + swap_support = "disable"; + rx_hs_no = <2>; + tx_hs_no = <3>; + bus_no = <1>; + clk_name = "spi1_clk"; + rx_dma_channel = <2>; + tx_dma_channel = <3>; + increase_support = "disable"; + data_field_size = <0x1000>; + data_reg_offset = <0x1000>; + dma_protctl_enable = "disable"; + dma_protctl_data = <6>; + dma_master_sel_enable = "disable"; + dma_master_ctl_sel = <0>; + dma_master_mem_sel = <0>; + spidma_xfer_mode = "rx_only"; + interrupts = <21>; + spidev1: spi@1 { + compatible = "rohm,dh2228fv"; + reg = <0x0 0>; + spi-max-frequency = <50000000>; + }; + spidev2: spi@2 { + compatible = "rohm,dh2228fv"; + reg = <0x1 0>; + spi-max-frequency = <50000000>; + }; + }; + fhdwi2s: i2s@f0900000 { + compatible = "fh,fh-dw_i2s"; + reg = <0xf0900000 0x1000>; + interrupts = <25>; + clocks = <&i2s_clk>, <&ac_clk>; + clock-names = "i2s_clk", "acodec_mclk"; + rx_dma_channel = <2>; + tx_dma_channel = <3>; + dma_master = <0>; + dma_rx_hs_num = <10>; + dma_tx_hs_num = <11>; + }; + + fhacw: acw@f0a00000 { + compatible = "fh,fh-acw"; + reg = <0xf0a00000 0x1000>; + interrupts = <19>; + clocks = <&ac_clk>; + clock-names = "ac_clk"; + rx_dma_channel = <4>; + tx_dma_channel = <5>; + dma_master = <0>; + dma_rx_hs_num = <0>; + dma_tx_hs_num = <1>; + }; + + pwm: pwm@f0400000{ + compatible = "fh,fh-pwm"; + reg = <0xf0400000 0x1000>; + interrupts = <36>; + npwm = <14>; + }; + serial0: serial@f0700000 { + compatible = "fh,fh-serial"; + reg = <0xf0700000 0x1000>; + interrupts = <30>; + clock-frequency = <16666667>; + fifo-size = <32>; + }; + serial1: serial@f0800000 { + compatible = "fh,fh-serial"; + reg = <0xf0800000 0x1000>; + interrupts = <31>; + clock-frequency = <16666667>; + fifo-size = <64>; + }; + serial2: serial@f1300000 { + compatible = "fh,fh-serial"; + reg = <0xf1300000 0x1000>; + interrupts = <41>; + clock-frequency = <16666667>; + fifo-size = <64>; + }; + gmac0: gmac@e0600000 { + compatible = "fh,fh-gmac"; + reg = <0xe0600000 0x2000>; + interrupts = <44>; + phyreset-gpio = <29>; + }; + sdc0: sdc0@e2000000 { + compatible = "fh,fh-sdc"; + reg = <0xe2000000 0x4000>; + interrupts = <42>; + id = <0>; + buswidth = <4>; + wp-fixed = <1>; + cd-fixed = <0>; + drv-degree = <8>; + sam-degree = <0>; + scan-mux = <0>; + }; + sdc1: sdc1@e2200000 { + compatible = "fh,fh-sdc"; + reg = <0xe2200000 0x4000>; + interrupts = <43>; + id = <1>; + buswidth = <4>; + wp-fixed = <1>; + cd-fixed = <1>; + drv-degree = <8>; + sam-degree = <0>; + scan-mux = <2>; + }; + wdt: wdt@f0d00000{ + compatible = "fh,fh-wdt"; + reg = <0xf0d00000 0x1000>; + interrupts = <2>; + mode = <1>; + }; + i2cbus0: i2c@f0200000 { + compatible = "fh,fh-i2c"; + reg = <0xf0200000 0x2000>; + interrupts = <11>; + }; + i2cbus1: i2c@f0b00000 { + compatible = "fh,fh-i2c"; + reg = <0xf0b00000 0x2000>; + interrupts = <12>; + }; + i2cbus2: i2c@0xF0100000 { + compatible = "fh,fh-i2c"; + reg = <0xF0100000 0x2000>; + interrupts = <46>; + }; + clocks: src_clk@0xf0000000{ + compatible = "fh,fh-clk"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xf0000000 0x80>; + ranges; + + osc_clk: mxtal@24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc_clk"; + }; + + pll_ddr_rclk: pllddrr{ + #clock-cells = <0>; + compatible = "fh pll-ddr-rclk"; + reg = <0xf0000010 0x4>,<0xf0000018 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f000000>; + divcop = <0xf000>; + clocks = <&osc_clk>; + clock-output-names = "pll_ddr_rclk"; + }; + pll_cpu_pclk: pllcpup{ + #clock-cells = <0>; + compatible = "fh pll-cpu-pclk"; + reg = <0xf0000014 0x4>,<0xf000006c 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f0000>; + divcop = <0xf00>; + clocks = <&osc_clk>; + clock-output-names = "pll_cpu_pclk"; + }; + pll_cpu_rclk: pllcpur{ + #clock-cells = <0>; + compatible = "fh pll-cpu-rclk"; + reg = <0xf0000014 0x4>,<0xf000006c 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f000000>; + divcop = <0xf000>; + clocks = <&osc_clk>; + clock-output-names = "pll_cpu_rclk"; + }; + pll_sys_pclk: pllsysp{ + #clock-cells = <0>; + compatible = "fh pll-sys-pclk"; + reg = <0xf0000064 0x4>,<0xf0000068 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f0000>; + divcop = <0xf00>; + clocks = <&osc_clk>; + clock-output-names = "pll_sys_pclk"; + }; + pll_sys_rclk: pllsysr{ + #clock-cells = <0>; + compatible = "fh pll-sys-rclk"; + reg = <0xf0000064 0x4>,<0xf0000068 0x4>; + m = <0x7f>; + n = <0x1f00>; + pr = <0x3f000000>; + divcop = <0xf000>; + clocks = <&osc_clk>; + clock-output-names = "pll_sys_rclk"; + }; + sysp_div12_clk: syspdiv12clk{ + #clock-cells = <0>; + compatible = "fh sysp-div12-clk"; + reg = <0xf0000038 0x4>,<0x0 0x4>,<0x0 0x4>; + div = <0xf000000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "sysp_div12_clk"; + }; + ddr_clk: ddrclk{ + #clock-cells = <0>; + compatible = "fh fh-ddr-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x4000000>; + clocks = <&pll_ddr_rclk>; + clock-output-names = "ddr_clk"; + }; + arm_clk: armclk{ + #clock-cells = <0>; + compatible = "fh fh-arm-clk"; + reg = <0x0 0x4>,<0x0 0x4>,<0xf000000c 0x4>; + mux = <0x1>; + clocks = <&osc_clk>,<&pll_cpu_pclk>; + clock-output-names = "arm_clk"; + }; + arc_clk: arcclk{ + #clock-cells = <0>; + compatible = "fh fh-arc-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0xf000000c 0x4>; + gate = <0x4000000>; + mux = <0x1>; + clocks = <&osc_clk>,<&pll_cpu_rclk>; + clock-output-names = "arc_clk"; + }; + ahb_clk: ahbclk{ + #clock-cells = <0>; + compatible = "fh fh-ahb-clk"; + reg = <0xf0000024 0x4>,<0x0 0x4>,<0xf000000c 0x4>; + div = <0xf0000>; + mux = <0x1>; + clocks = <&osc_clk>,<&pll_sys_pclk>; + clock-output-names = "ahb_clk"; + }; + isp_aclk: ispaclk{ + #clock-cells = <0>; + compatible = "fh fh-ispa-clk"; + reg = <0xf0000024 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xf00>; + gate = <0x1>; + clocks = <&pll_sys_pclk>; + clock-output-names = "isp_aclk"; + }; + ispb_aclk: ispbclk{ + #clock-cells = <0>; + compatible = "fh fh-ispb-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + gate = <0x4>; + clocks = <&isp_aclk>; + clock-output-names = "ispb_aclk"; + }; + vpu_clk: vpuclk{ + #clock-cells = <0>; + compatible = "fh fh-vpu-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x80000000>; + clocks = <&isp_aclk>; + clock-output-names = "vpu_clk"; + }; + pix_clk: pixclk{ + #clock-cells = <0>; + compatible = "fh fh-pix-clk"; + reg = <0xf000002c 0x4>,<0x0 0x4>,<0x0 0x4>; + div = <0xf000000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "pix_clk"; + }; + jpeg_clk: jpegclk{ + #clock-cells = <0>; + compatible = "fh fh-jpeg-clk"; + reg = <0xf000005c 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + div = <0xf00000>; + gate = <0x40000000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "jpeg_clk"; + }; + bgm_clk: bgmclk{ + #clock-cells = <0>; + compatible = "fh fh-bgm-clk"; + reg = <0xf000005c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xf00000>; + gate = <0x40000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "bgm_clk"; + }; + jpeg_adapt_clk: jpegadaptclk{ + #clock-cells = <0>; + compatible = "fh fh-jpeg-adapt-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x2>; + clocks = <&jpeg_clk>; + clock-output-names = "jpeg_adapt_clk"; + }; + spi0_clk: spi0clk{ + #clock-cells = <0>; + compatible = "fh fh-spi0-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff>; + gate = <0x80>; + clocks = <&pll_sys_pclk>; + clock-output-names = "spi0_clk"; + }; + sdc0_clk: sdc0clk{ + #clock-cells = <0>; + compatible = "fh fh-sdc0-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + prediv =<8>; + div = <0xf00>; + gate = <0x200>; + clocks = <&pll_sys_pclk>; + clock-output-names = "sdc0_clk"; + }; + spi2_clk: spi2clk{ + #clock-cells = <0>; + compatible = "fh fh-spi2-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xf000>; + gate = <0x2>; + clocks = <&pll_sys_pclk>; + clock-output-names = "spi2_clk"; + }; + spi1_clk: spi1clk{ + #clock-cells = <0>; + compatible = "fh fh-spi1-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff0000>; + gate = <0x100>; + clocks = <&pll_sys_pclk>; + clock-output-names = "spi1_clk"; + }; + sdc1_clk: sdc1clk{ + #clock-cells = <0>; + compatible = "fh fh-sdc1-clk"; + reg = <0xf0000030 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + prediv =<8>; + div = <0xf000000>; + gate = <0x400>; + clocks = <&pll_sys_pclk>; + clock-output-names = "sdc1_clk"; + }; + veu_clk: veuclk{ + #clock-cells = <0>; + compatible = "fh fh-veu-clk"; + reg = <0xf0000024 0x4>,<0xf000001c 0x4>,<0xf000000c 0x4>; + div = <0x7000000>; + gate = <0x10>; + mux = <0x4>; + clocks = <&pll_sys_pclk>,<&pll_sys_rclk>; + clock-output-names = "veu_clk"; + }; + veu_adapt_clk: veuadaptclk{ + #clock-cells = <0>; + compatible = "fh fh-veu-adapt-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + gate = <0x20000000>; + clocks = <&veu_clk>; + clock-output-names = "veu_adapt_clk"; + }; + cis_clk_out: cisclk{ + #clock-cells = <0>; + compatible = "fh fh-cis-clk-out"; + reg = <0xf0000028 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff0000>; + gate = <0x800000>; + clocks = <&pll_sys_pclk>; + clock-output-names = "cis_clk_out"; + }; + eth_clk: ethclk{ + #clock-cells = <0>; + compatible = "fh fh-eth-clk"; + reg = <0xf000003c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xf000000>; + gate = <0x2000000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "eth_clk"; + }; + eth_rmii_clk: ethrmiiclk { + #clock-cells = <0>; + compatible = "fh fh-ethrmii-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + gate = <0x10000000>; + clock-output-names = "eth_rmii_clk"; + }; + i2c0_clk: i2c0clk { + #clock-cells = <0>; + compatible = "fh fh-i2c0-clk"; + reg = <0xf0000034 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f0000>; + gate = <0x1000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "i2c0_clk"; + }; + + i2c1_clk: i2c1clk { + #clock-cells = <0>; + compatible = "fh fh-i2c1-clk"; + reg = <0xf0000034 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f000000>; + gate = <0x8000000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "i2c1_clk"; + }; + i2c2_clk: i2c2clk { + #clock-cells = <0>; + compatible = "fh fh-i2c2-clk"; + reg = <0xf000005c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f00>; + gate = <0x00000008>; + clocks = <&sysp_div12_clk>; + clock-output-names = "i2c2_clk"; + }; + + uart0_clk: uart0clk { + #clock-cells = <0>; + compatible = "fh fh-uart0-clk"; + reg = <0xf0000034 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x1f>; + gate = <0x2000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "uart0_clk"; + }; + + uart1_clk: uart1clk { + #clock-cells = <0>; + compatible = "fh fh-uart1-clk"; + reg = <0xf0000034 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x1f00>; + gate = <0x4000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "uart1_clk"; + }; + uart2_clk: uart2clk { + #clock-cells = <0>; + compatible = "fh fh-uart2-clk"; + reg = <0xf000005c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x7f>; + gate = <0x8000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "uart2_clk"; + }; + pwm_clk: pwmclk { + #clock-cells = <0>; + compatible = "fh fh-pwm-clk"; + reg = <0xf0000038 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff>; + gate = <0x10000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "pwm_clk"; + }; + efuse_clk: efuseclk { + #clock-cells = <0>; + compatible = "fh fh-efuse-clk"; + reg = <0xf0000028 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f000000>; + gate = <0x200000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "efuse_clk"; + }; + pts_clk: ptsclk { + #clock-cells = <0>; + compatible = "fh fh-pts-clk"; + reg = <0xf000002c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x1ff>; + gate = <0x80000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "pts_clk"; + }; + tmr0_clk: tmr0clk { + #clock-cells = <0>; + compatible = "fh fh-tmr0-clk"; + reg = <0xf0000038 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0xff0000>; + gate = <0x20000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "tmr0_clk"; + }; + + sadc_clk: sadcclk { + #clock-cells = <0>; + compatible = "fh fh-sadc-clk"; + reg = <0xf000003c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x7f0000>; + gate = <0x4000000>; + clocks = <&sysp_div12_clk>; + clock-output-names = "sadc_clk"; + }; + gpio0_dbclk: gpio0dbclk { + #clock-cells = <0>; + compatible = "fh fh-gpio0-dbclk"; + reg = <0xf0000060 0x4>,<0xf0000060 0x4>,<0x0 0x4>; + div = <0x7fff>; + gate = <0x8000>; + prediv = <100>; + clocks = <&sysp_div12_clk>; + clock-output-names = "gpio0_dbclk"; + }; + gpio1_dbclk: gpio1dbclk { + #clock-cells = <0>; + compatible = "fh fh-gpio1-dbclk"; + reg = <0xf0000060 0x4>,<0xf0000060 0x4>,<0x0 0x4>; + div = <0x7fff0000>; + gate = <0x80000000>; + prediv = <100>; + clocks = <&sysp_div12_clk>; + clock-output-names = "gpio1_dbclk"; + }; + wdt_clk: wdtclk { + #clock-cells = <0>; + compatible = "fh fh-wdt-clk"; + reg = <0xf0000038 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + div = <0xff00>; + gate = <0x8000000>; + clocks = <&ahb_clk>; + clock-output-names = "wdt_clk"; + }; + ac_clk: acclk{ + #clock-cells = <0>; + compatible = "fh fh-ac-clk"; + reg = <0xf000003c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f>; + gate = <0x800>; + clocks = <&osc_clk>; + clock-output-names = "ac_clk"; + }; + i2s_clk: i2sclk{ + #clock-cells = <0>; + compatible = "fh fh-i2s-clk"; + reg = <0xf000003c 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + div = <0x3f00>; + gate = <0x1000000>; + clocks = <&ac_clk>; + clock-output-names = "i2s_clk"; + }; + mipi_dphy_clk: mipidphyclk { + #clock-cells = <0>; + compatible = "fh fh-mipi-dphy-clk"; + reg = <0x0 0x4>,<0xf000001c 0x4>,<0x0 0x4>; + gate = <0x100000>; + clock-output-names = "mipi_dphy_clk"; + }; + mipi_wrap_gate: mipiwrapclk { + #clock-cells = <0>; + compatible = "fh fh-mipi-wrap-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x20000000>; + clock-output-names = "mipi_wrap_gate"; + }; + rtc_hclk_gate: rtchclk { + #clock-cells = <0>; + compatible = "fh fh-rtc-hclk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x10000000>; + clock-output-names = "rtc_hclk_gate"; + }; + emac_hclk_gate: emachclk { + #clock-cells = <0>; + compatible = "fh fh-emac-hclk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x2000000>; + clock-output-names = "emac_hclk_gate"; + }; + usb_clk: usbclk { + #clock-cells = <0>; + compatible = "fh fh-usb-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x1000000>; + clock-output-names = "usb_clk"; + }; + aes_hclk_gate: aeshclk { + #clock-cells = <0>; + compatible = "fh fh-aes-hclk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x80>; + clock-output-names = "aes_hclk_gate"; + }; + ephy_clk_gate: ephyclk { + #clock-cells = <0>; + compatible = "fh fh-ephy-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x1>; + clock-output-names = "ephy_clk_gate"; + }; + sdc0_clk8x_gate: sdc08xclk { + #clock-cells = <0>; + compatible = "fh fh-sdc08x-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x4>; + clock-output-names = "sdc0_clk8x_gate"; + }; + sdc1_clk8x_gate: sdc18xclk { + #clock-cells = <0>; + compatible = "fh fh-sdc18x-clk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x8>; + clock-output-names = "sdc1_clk8x_gate"; + }; + mipic_pclk_gate: mipicpclk { + #clock-cells = <0>; + compatible = "fh fh-mipic-pclk"; + reg = <0x0 0x4>,<0xf0000020 0x4>,<0x0 0x4>; + gate = <0x10>; + clock-output-names = "mipic_pclk_gate"; + }; + gpio0_pclk_gate: gpio0pclk { + #clock-cells = <0>; + compatible = "fh fh-gpio0-pclk"; + reg = <0x0 0x4>,<0xf0000060 0x4>,<0x0 0x4>; + gate = <0x4000>; + clock-output-names = "gpio0_pclk_gate"; + }; + gpio1_pclk_gate: gpio1pclk { + #clock-cells = <0>; + compatible = "fh fh-gpio1-pclk"; + reg = <0x0 0x4>,<0xf0000060 0x4>,<0x0 0x4>; + gate = <0x40000000>; + clock-output-names = "gpio1_pclk_gate"; + }; + isp_hclk_gate: isphclk { + #clock-cells = <0>; + compatible = "fh fh-isp-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x1000000>; + clock-output-names = "isp_hclk_gate"; + }; + veu_hclk_gate: veuhclk { + #clock-cells = <0>; + compatible = "fh fh-veu-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x2000000>; + clock-output-names = "veu_hclk_gate"; + }; + bgm_hclk_gate: bgmhclk { + #clock-cells = <0>; + compatible = "fh fh-bgm-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x4000000>; + clock-output-names = "bgm_hclk_gate"; + }; + adapt_hclk_gate: adapthclk { + #clock-cells = <0>; + compatible = "fh fh-adapt-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x8000000>; + clock-output-names = "adapt_hclk_gate"; + }; + jpg_hclk_gate: jpghclk { + #clock-cells = <0>; + compatible = "fh fh-jpg-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x10000000>; + clock-output-names = "jpg_hclk_gate"; + }; + jpg_adapt_gate: jpgadaptclk { + #clock-cells = <0>; + compatible = "fh fh-jpg-adapt-clk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x20000000>; + clock-output-names = "jpg_adapt_gate"; + }; + vpu_hclk_gate: vpuhclk { + #clock-cells = <0>; + compatible = "fh fh-vpu-hclk"; + reg = <0x0 0x4>,<0xf000005c 0x4>,<0x0 0x4>; + gate = <0x40000000>; + clock-output-names = "vpu_hclk_gate"; + }; + sdc0_clk_sample: sdc0clksample { + #clock-cells = <0>; + compatible = "fh fh-sdc0-clk_sample"; + reg = <0xf0000020 0x4>; + mux = <0xf0000>; + clocks = <&sdc0_clk>; + clock-output-names = "sdc0_clk_sample"; + }; + sdc0_clk_drv: sdc0clkdrv { + #clock-cells = <0>; + compatible = "fh fh-sdc0-clk_drv"; + reg = <0xf0000020 0x4>; + mux = <0xf00000>; + clocks = <&sdc0_clk>; + clock-output-names = "sdc0_clk_drv"; + }; + + sdc1_clk_sample: sdc1clksample { + #clock-cells = <0>; + compatible = "fh fh-sdc1-clk_sample"; + reg = <0xf0000020 0x4>; + mux = <0xf00>; + clocks = <&sdc1_clk>; + clock-output-names = "sdc1_clk_sample"; + }; + + sdc1_clk_drv: sdc1clkdrv { + #clock-cells = <0>; + compatible = "fh fh-sdc1-clk_drv"; + reg = <0xf0000020 0x4>; + mux = <0xf000>; + clocks = <&sdc1_clk>; + clock-output-names = "sdc1_clk_drv"; + }; + }; + }; + + usb_otg@e0700000 { + compatible = "fh_usb"; + reg = <0xe0700000 100000>; + interrupts = <39>; + clocks = <&usb_clk>; + dr_mode = "host"; + vbus_pwren = <47>; + clock-names = "otg"; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + }; + + usb2_phy: usbphy { + compatible = "fh,fh-usb2-phy"; + #phy-cells = <0>; + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/fh8858v210_pinctrl.dtsi b/arch/arm/boot/dts/fh8858v210_pinctrl.dtsi new file mode 100644 index 00000000..731caa02 --- /dev/null +++ b/arch/arm/boot/dts/fh8858v210_pinctrl.dtsi @@ -0,0 +1,2379 @@ +/* + * Copyright (C) 2020 Fullhan Micorelectonics Co.,Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + #define PUPD_NONE (0) + #define PUPD_UP (1) + #define PUPD_DOWN (2) +*/ + +/ { + pinctrl: pinctrl@f0000080 { + compatible = "fh,fh-pinctrl"; + reg = <0xf0000080 0x104>; + pad-num = <65>; + max-mux = <9>; + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_AC_MCLK + &pinctrl_ETH + &pinctrl_I2C0 + &pinctrl_PWM2 + &pinctrl_PWM3 + &pinctrl_PWM4 + &pinctrl_PWM5 + &pinctrl_PWM6 + &pinctrl_PWM7 + &pinctrl_PWM8 + &pinctrl_PWM9 + &pinctrl_SADC_XAIN0 + &pinctrl_SADC_XAIN1 + &pinctrl_SADC_XAIN2 + &pinctrl_SADC_XAIN3 + &pinctrl_SD0_NO_WP + &pinctrl_SD1_NO_WP + &pinctrl_SENSOR_CLK + &pinctrl_SSI0_4BIT + &pinctrl_SSI1 + &pinctrl_UART0 + &pinctrl_UART1 + &pinctrl_GPIO13 + &pinctrl_GPIO28 + &pinctrl_GPIO29 + &pinctrl_GPIO30 + &pinctrl_GPIO31 + &pinctrl_GPIO32 + &pinctrl_GPIO43 + &pinctrl_GPIO44 + &pinctrl_GPIO47 + &pinctrl_GPIO48 + &pinctrl_GPIO49 + &pinctrl_GPIO50 + &pinctrl_GPIO51 + &pinctrl_GPIO52 + &pinctrl_GPIO53 + &pinctrl_GPIO54 + &pinctrl_GPIO55 + &pinctrl_GPIO56 + + &pinctrl_GPIO45 + &pinctrl_GPIO46 + >; + pinctrl_groups { + pinctrl_ACI2S: ACI2S { + fh,pins = < + &mux_AC_I2S_CLK 0 + &mux_AC_I2S_DI 0 + &mux_AC_I2S_DO 0 + &mux_AC_I2S_WS 0 + &mux_AC_MCLK 0 + >; + }; + pinctrl_AC_MCLK: AC_MCLK { + fh,pins = < + &mux_AC_MCLK 0 + >; + }; + pinctrl_ARCJTAG: ARCJTAG { + fh,pins = < + &mux_ARC_JTAG_TCK 0 + &mux_ARC_JTAG_TDI 0 + &mux_ARC_JTAG_TDO 0 + &mux_ARC_JTAG_TMS 0 + &mux_ARC_JTAG_TRSTN 0 + >; + }; + pinctrl_ARMJTAG: ARMJTAG { + fh,pins = < + &mux_ARM_JTAG_TCK 0 + &mux_ARM_JTAG_TDI 0 + &mux_ARM_JTAG_TDO 0 + &mux_ARM_JTAG_TMS 0 + &mux_ARM_JTAG_TRSTN 0 + >; + }; + pinctrl_DWI2S: DWI2S { + fh,pins = < + &mux_DW_I2S_CLK 0 + &mux_DW_I2S_DI 0 + &mux_DW_I2S_DO 0 + &mux_DW_I2S_WS 0 + >; + }; + pinctrl_ETH: ETH { + fh,pins = < + &mux_ETH_LINK_ACT 1 + &mux_ETH_LINK_STA 1 + >; + }; + pinctrl_I2C0: I2C0 { + fh,pins = < + &mux_I2C0_SCL 0 + &mux_I2C0_SDA 0 + >; + }; + pinctrl_I2C1: I2C1 { + fh,pins = < + &mux_I2C1_SCL 2 + &mux_I2C1_SDA 2 + >; + }; + pinctrl_I2C2: I2C2 { + fh,pins = < + &mux_I2C2_SCL 1 + &mux_I2C2_SDA 1 + >; + }; + pinctrl_PAEJTAG: PAEJTAG { + fh,pins = < + &mux_PAE_JTAG_TCK 0 + &mux_PAE_JTAG_TDI 0 + &mux_PAE_JTAG_TDO 0 + &mux_PAE_JTAG_TMS 0 + &mux_PAE_JTAG_TRSTN 0 + >; + }; + pinctrl_PWM0: PWM0 { + fh,pins = < + &mux_PWM0 0 + >; + }; + pinctrl_PWM1: PWM1 { + fh,pins = < + &mux_PWM1 0 + >; + }; + pinctrl_PWM10: PWM10 { + fh,pins = < + &mux_PWM10 0 + >; + }; + pinctrl_PWM11: PWM11 { + fh,pins = < + &mux_PWM11 0 + >; + }; + pinctrl_PWM2: PWM2 { + fh,pins = < + &mux_PWM2 0 + >; + }; + pinctrl_PWM3: PWM3 { + fh,pins = < + &mux_PWM3 0 + >; + }; + pinctrl_PWM4: PWM4 { + fh,pins = < + &mux_PWM4 0 + >; + }; + pinctrl_PWM5: PWM5 { + fh,pins = < + &mux_PWM5 0 + >; + }; + pinctrl_PWM6: PWM6 { + fh,pins = < + &mux_PWM6 1 + >; + }; + pinctrl_PWM7: PWM7 { + fh,pins = < + &mux_PWM7 1 + >; + }; + pinctrl_PWM8: PWM8 { + fh,pins = < + &mux_PWM8 1 + >; + }; + pinctrl_PWM9: PWM9 { + fh,pins = < + &mux_PWM9 1 + >; + }; + pinctrl_RMII: RMII { + fh,pins = < + &mux_MAC_MDC 0 + &mux_MAC_MDIO 0 + &mux_MAC_REF_CLK 0 + &mux_MAC_RMII_CLK 0 + &mux_MAC_RXDV 0 + &mux_MAC_RXD_0 0 + &mux_MAC_RXD_1 0 + &mux_MAC_TXD_0 0 + &mux_MAC_TXD_1 0 + &mux_MAC_TXEN 0 + >; + }; + pinctrl_RTC: RTC { + fh,pins = < + &mux_RTC_CLK 0 + >; + }; + pinctrl_SADC_XAIN0: SADC_XAIN0 { + fh,pins = < + &mux_SADC_XAIN0 0 + >; + }; + pinctrl_SADC_XAIN1: SADC_XAIN1 { + fh,pins = < + &mux_SADC_XAIN1 0 + >; + }; + pinctrl_SADC_XAIN2: SADC_XAIN2 { + fh,pins = < + &mux_SADC_XAIN2 0 + >; + }; + pinctrl_SADC_XAIN3: SADC_XAIN3 { + fh,pins = < + &mux_SADC_XAIN3 0 + >; + }; + pinctrl_SD0: SD0 { + fh,pins = < + &mux_SD0_CD 0 + &mux_SD0_CLK 0 + &mux_SD0_CMD_RSP 0 + &mux_SD0_DATA_0 0 + &mux_SD0_DATA_1 0 + &mux_SD0_DATA_2 0 + &mux_SD0_DATA_3 0 + >; + }; + pinctrl_SD0_1BIT_NO_WP: SD0_1BIT_NO_WP { + fh,pins = < + &mux_SD0_CD 0 + &mux_SD0_CLK 0 + &mux_SD0_CMD_RSP 0 + &mux_SD0_DATA_0 0 + >; + }; + pinctrl_SD0_NO_WP: SD0_NO_WP { + fh,pins = < + &mux_SD0_CD 0 + &mux_SD0_CLK 0 + &mux_SD0_CMD_RSP 0 + &mux_SD0_DATA_0 0 + &mux_SD0_DATA_1 0 + &mux_SD0_DATA_2 0 + &mux_SD0_DATA_3 0 + >; + }; + pinctrl_SD0_WIFI: SD0_WIFI { + fh,pins = < + &mux_SD0_CLK 0 + &mux_SD0_CMD_RSP 0 + &mux_SD0_DATA_0 0 + &mux_SD0_DATA_1 0 + &mux_SD0_DATA_2 0 + &mux_SD0_DATA_3 0 + >; + }; + pinctrl_SD1: SD1 { + fh,pins = < + &mux_SD1_CD 2 + &mux_SD1_CLK 2 + &mux_SD1_CMD_RSP 2 + &mux_SD1_DATA_0 2 + &mux_SD1_DATA_1 2 + &mux_SD1_DATA_2 2 + &mux_SD1_DATA_3 2 + >; + }; + pinctrl_SD1_1BIT_NO_WP: SD1_1BIT_NO_WP { + fh,pins = < + &mux_SD1_CD 2 + &mux_SD1_CLK 2 + &mux_SD1_CMD_RSP 2 + &mux_SD1_DATA_0 2 + >; + }; + pinctrl_SD1_NO_WP: SD1_NO_WP { + fh,pins = < + &mux_SD1_CD 2 + &mux_SD1_CLK 2 + &mux_SD1_CMD_RSP 2 + &mux_SD1_DATA_0 2 + &mux_SD1_DATA_1 2 + &mux_SD1_DATA_2 2 + &mux_SD1_DATA_3 2 + >; + }; + pinctrl_SD1_WIFI: SD1_WIFI { + fh,pins = < + &mux_SD1_CLK 2 + &mux_SD1_CMD_RSP 2 + &mux_SD1_DATA_0 2 + &mux_SD1_DATA_1 2 + &mux_SD1_DATA_2 2 + &mux_SD1_DATA_3 2 + >; + }; + pinctrl_SENSOR_CLK: SENSOR_CLK { + fh,pins = < + &mux_SENSOR_CLK 0 + >; + }; + pinctrl_SSI0: SSI0 { + fh,pins = < + &mux_GPIO6 0 + &mux_SSI0_CLK 0 + &mux_SSI0_RXD 0 + &mux_SSI0_TXD 0 + >; + }; + pinctrl_SSI0_4BIT: SSI0_4BIT { + fh,pins = < + &mux_GPIO6 0 + &mux_SSI0_CLK 0 + &mux_SSI0_D2 0 + &mux_SSI0_D3 0 + &mux_SSI0_RXD 0 + &mux_SSI0_TXD 0 + >; + }; + pinctrl_SSI1: SSI1 { + fh,pins = < + &mux_GPIO14 0 + &mux_SSI1_CLK 2 + &mux_SSI1_RXD 2 + &mux_SSI1_TXD 2 + >; + }; + pinctrl_SSI2: SSI2 { + fh,pins = < + &mux_SSI2_CLK 1 + &mux_SSI2_CSN_0 1 + &mux_SSI2_RXD 1 + &mux_SSI2_TXD 1 + >; + }; + pinctrl_UART0: UART0 { + fh,pins = < + &mux_UART0_RX 0 + &mux_UART0_TX 0 + >; + }; + pinctrl_UART1: UART1 { + fh,pins = < + &mux_UART1_RX 0 + &mux_UART1_TX 0 + >; + }; + pinctrl_UART2: UART2 { + fh,pins = < + &mux_UART2_RX 0 + &mux_UART2_TX 0 + >; + }; + pinctrl_USB: USB { + fh,pins = < + &mux_USB_PWREN 0 + >; + }; + pinctrl_GPIO0: GPIO0 { + fh,pins = < + &mux_GPIO0 0 + >; + }; + pinctrl_GPIO1: GPIO1 { + fh,pins = < + &mux_GPIO1 0 + >; + }; + pinctrl_GPIO2: GPIO2 { + fh,pins = < + &mux_GPIO2 0 + >; + }; + pinctrl_GPIO3: GPIO3 { + fh,pins = < + &mux_GPIO3 0 + >; + }; + pinctrl_GPIO4: GPIO4 { + fh,pins = < + &mux_GPIO4 0 + >; + }; + pinctrl_GPIO5: GPIO5 { + fh,pins = < + &mux_GPIO5 0 + >; + }; + pinctrl_GPIO6: GPIO6 { + fh,pins = < + &mux_GPIO6 0 + >; + }; + pinctrl_GPIO7: GPIO7 { + fh,pins = < + &mux_GPIO7 0 + >; + }; + pinctrl_GPIO8: GPIO8 { + fh,pins = < + &mux_GPIO8 0 + >; + }; + pinctrl_GPIO9: GPIO9 { + fh,pins = < + &mux_GPIO9 0 + >; + }; + pinctrl_GPIO10: GPIO10 { + fh,pins = < + &mux_GPIO10 0 + >; + }; + pinctrl_GPIO11: GPIO11 { + fh,pins = < + &mux_GPIO11 0 + >; + }; + pinctrl_GPIO12: GPIO12 { + fh,pins = < + &mux_GPIO12 0 + >; + }; + pinctrl_GPIO13: GPIO13 { + fh,pins = < + &mux_GPIO13 0 + >; + }; + pinctrl_GPIO14: GPIO14 { + fh,pins = < + &mux_GPIO14 0 + >; + }; + pinctrl_GPIO15: GPIO15 { + fh,pins = < + &mux_GPIO15 0 + >; + }; + pinctrl_GPIO16: GPIO16 { + fh,pins = < + &mux_GPIO16 0 + >; + }; + pinctrl_GPIO17: GPIO17 { + fh,pins = < + &mux_GPIO17 0 + >; + }; + pinctrl_GPIO18: GPIO18 { + fh,pins = < + &mux_GPIO18 0 + >; + }; + pinctrl_GPIO19: GPIO19 { + fh,pins = < + &mux_GPIO19 0 + >; + }; + pinctrl_GPIO20: GPIO20 { + fh,pins = < + &mux_GPIO20 0 + >; + }; + pinctrl_GPIO21: GPIO21 { + fh,pins = < + &mux_GPIO21 0 + >; + }; + pinctrl_GPIO22: GPIO22 { + fh,pins = < + &mux_GPIO22 0 + >; + }; + pinctrl_GPIO23: GPIO23 { + fh,pins = < + &mux_GPIO23 0 + >; + }; + pinctrl_GPIO24: GPIO24 { + fh,pins = < + &mux_GPIO24 0 + >; + }; + pinctrl_GPIO25: GPIO25 { + fh,pins = < + &mux_GPIO25 0 + >; + }; + pinctrl_GPIO26: GPIO26 { + fh,pins = < + &mux_GPIO26 0 + >; + }; + pinctrl_GPIO27: GPIO27 { + fh,pins = < + &mux_GPIO27 0 + >; + }; + pinctrl_GPIO28: GPIO28 { + fh,pins = < + &mux_GPIO28 0 + >; + }; + pinctrl_GPIO29: GPIO29 { + fh,pins = < + &mux_GPIO29 0 + >; + }; + pinctrl_GPIO30: GPIO30 { + fh,pins = < + &mux_GPIO30 0 + >; + }; + pinctrl_GPIO31: GPIO31 { + fh,pins = < + &mux_GPIO31 0 + >; + }; + pinctrl_GPIO32: GPIO32 { + fh,pins = < + &mux_GPIO32 0 + >; + }; + pinctrl_GPIO33: GPIO33 { + fh,pins = < + &mux_GPIO33 0 + >; + }; + pinctrl_GPIO34: GPIO34 { + fh,pins = < + &mux_GPIO34 0 + >; + }; + pinctrl_GPIO35: GPIO35 { + fh,pins = < + &mux_GPIO35 0 + >; + }; + pinctrl_GPIO36: GPIO36 { + fh,pins = < + &mux_GPIO36 0 + >; + }; + pinctrl_GPIO37: GPIO37 { + fh,pins = < + &mux_GPIO37 0 + >; + }; + pinctrl_GPIO38: GPIO38 { + fh,pins = < + &mux_GPIO38 0 + >; + }; + pinctrl_GPIO39: GPIO39 { + fh,pins = < + &mux_GPIO39 0 + >; + }; + pinctrl_GPIO40: GPIO40 { + fh,pins = < + &mux_GPIO40 0 + >; + }; + pinctrl_GPIO41: GPIO41 { + fh,pins = < + &mux_GPIO41 0 + >; + }; + pinctrl_GPIO42: GPIO42 { + fh,pins = < + &mux_GPIO42 0 + >; + }; + pinctrl_GPIO43: GPIO43 { + fh,pins = < + &mux_GPIO43 0 + >; + }; + pinctrl_GPIO44: GPIO44 { + fh,pins = < + &mux_GPIO44 0 + >; + }; + pinctrl_GPIO45: GPIO45 { + fh,pins = < + &mux_GPIO45 0 + >; + }; + pinctrl_GPIO46: GPIO46 { + fh,pins = < + &mux_GPIO46 0 + >; + }; + pinctrl_GPIO47: GPIO47 { + fh,pins = < + &mux_GPIO47 0 + >; + }; + pinctrl_GPIO48: GPIO48 { + fh,pins = < + &mux_GPIO48 0 + >; + }; + pinctrl_GPIO49: GPIO49 { + fh,pins = < + &mux_GPIO49 0 + >; + }; + pinctrl_GPIO50: GPIO50 { + fh,pins = < + &mux_GPIO50 0 + >; + }; + pinctrl_GPIO51: GPIO51 { + fh,pins = < + &mux_GPIO51 0 + >; + }; + pinctrl_GPIO52: GPIO52 { + fh,pins = < + &mux_GPIO52 0 + >; + }; + pinctrl_GPIO53: GPIO53 { + fh,pins = < + &mux_GPIO53 0 + >; + }; + pinctrl_GPIO54: GPIO54 { + fh,pins = < + &mux_GPIO54 0 + >; + }; + pinctrl_GPIO55: GPIO55 { + fh,pins = < + &mux_GPIO55 0 + >; + }; + pinctrl_GPIO56: GPIO56 { + fh,pins = < + &mux_GPIO56 0 + >; + }; + pinctrl_GPIO57: GPIO57 { + fh,pins = < + &mux_GPIO57 0 + >; + }; + pinctrl_GPIO58: GPIO58 { + fh,pins = < + &mux_GPIO58 0 + >; + }; + pinctrl_GPIO59: GPIO59 { + fh,pins = < + &mux_GPIO59 0 + >; + }; + pinctrl_GPIO60: GPIO60 { + fh,pins = < + &mux_GPIO60 0 + >; + }; + pinctrl_GPIO61: GPIO61 { + fh,pins = < + &mux_GPIO61 0 + >; + }; + pinctrl_GPIO62: GPIO62 { + fh,pins = < + &mux_GPIO62 0 + >; + }; + pinctrl_GPIO63: GPIO63 { + fh,pins = < + &mux_GPIO63 0 + >; + }; + pinctrl_SD1_EMMC: SD1_EMMC { + fh,pins = < + &mux_SD1_CD 3 + &mux_SD1_CLK 3 + &mux_SD1_CMD_RSP 3 + &mux_SD1_DATA_0 3 + &mux_SD1_DATA_1 3 + &mux_SD1_DATA_2 3 + &mux_SD1_DATA_3 3 + >; + }; + }; + pinmux: pinmux { + compatible = "fh,fh-pinmux"; + #list-cells = <1>; + mux_AC_I2S_CLK: AC_I2S_CLK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad39 + >; + }; + mux_AC_I2S_DI: AC_I2S_DI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad38 + >; + }; + mux_AC_I2S_DO: AC_I2S_DO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad37 + >; + }; + mux_AC_I2S_WS: AC_I2S_WS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad40 + >; + }; + mux_AC_MCLK: AC_MCLK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad41 + >; + }; + + mux_ARC_JTAG_TCK: ARC_JTAG_TCK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad55 + >; + }; + mux_ARC_JTAG_TDI: ARC_JTAG_TDI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad54 + >; + }; + mux_ARC_JTAG_TDO: ARC_JTAG_TDO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad53 + >; + }; + mux_ARC_JTAG_TMS: ARC_JTAG_TMS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad56 + >; + }; + mux_ARC_JTAG_TRSTN: ARC_JTAG_TRSTN { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad52 + >; + }; + + mux_ARM_JTAG_TCK: ARM_JTAG_TCK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad40 + >; + }; + mux_ARM_JTAG_TDI: ARM_JTAG_TDI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad39 + >; + }; + mux_ARM_JTAG_TDO: ARM_JTAG_TDO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad38 + >; + }; + mux_ARM_JTAG_TMS: ARM_JTAG_TMS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad41 + >; + }; + mux_ARM_JTAG_TRSTN: ARM_JTAG_TRSTN { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad37 + >; + }; + + mux_DW_I2S_CLK: DW_I2S_CLK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad39 + >; + }; + mux_DW_I2S_DI: DW_I2S_DI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad38 + >; + }; + mux_DW_I2S_DO: DW_I2S_DO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad37 + >; + }; + mux_DW_I2S_WS: DW_I2S_WS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad40 + >; + }; + + mux_ETH_LINK_ACT: ETH_LINK_ACT { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad1 + &pad63 + >; + }; + mux_ETH_LINK_SPD: ETH_LINK_SPD { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad2 + &pad64 + >; + }; + mux_ETH_LINK_STA: ETH_LINK_STA { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad2 + &pad64 + >; + }; + + mux_I2C0_SCL: I2C0_SCL { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad5 + >; + }; + mux_I2C0_SDA: I2C0_SDA { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad6 + >; + }; + + mux_I2C1_SCL: I2C1_SCL { + #list-cells = <1>; + select = <2>; + fh,pads = < + &pad11 + &pad30 + &pad46 + >; + }; + mux_I2C1_SDA: I2C1_SDA { + #list-cells = <1>; + select = <2>; + fh,pads = < + &pad12 + &pad31 + &pad47 + >; + }; + + mux_I2C2_SCL: I2C2_SCL { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad16 + &pad57 + >; + }; + mux_I2C2_SDA: I2C2_SDA { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad17 + &pad58 + >; + }; + + mux_MAC_MDC: MAC_MDC { + #list-cells = <1>; + select = <0>; + ds = <0>; + fh,pads = < + &pad28 + &pad63 + >; + }; + mux_MAC_MDIO: MAC_MDIO { + #list-cells = <1>; + select = <0>; + ds = <0>; + fh,pads = < + &pad29 + &pad64 + >; + }; + mux_MAC_REF_CLK: MAC_REF_CLK { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad21 + >; + }; + mux_MAC_RMII_CLK: MAC_RMII_CLK { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad20 + >; + }; + mux_MAC_RXDV: MAC_RXDV { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad27 + >; + }; + mux_MAC_RXD_0: MAC_RXD_0 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad25 + >; + }; + mux_MAC_RXD_1: MAC_RXD_1 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad26 + >; + }; + mux_MAC_TXD_0: MAC_TXD_0 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad22 + >; + }; + mux_MAC_TXD_1: MAC_TXD_1 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad23 + >; + }; + mux_MAC_TXEN: MAC_TXEN { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad24 + >; + }; + + mux_PAE_JTAG_TCK: PAE_JTAG_TCK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad55 + >; + }; + mux_PAE_JTAG_TDI: PAE_JTAG_TDI { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad54 + >; + }; + mux_PAE_JTAG_TDO: PAE_JTAG_TDO { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad53 + >; + }; + mux_PAE_JTAG_TMS: PAE_JTAG_TMS { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad56 + >; + }; + mux_PAE_JTAG_TRSTN: PAE_JTAG_TRSTN { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad52 + >; + }; + + mux_PWM0: PWM0 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad16 + >; + }; + mux_PWM1: PWM1 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad17 + >; + }; + mux_PWM10: PWM10 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad63 + >; + }; + mux_PWM11: PWM11 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad64 + >; + }; + mux_PWM2: PWM2 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad11 + &pad18 + &pad20 + >; + }; + mux_PWM3: PWM3 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad12 + &pad19 + &pad22 + >; + }; + mux_PWM4: PWM4 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad13 + &pad23 + >; + }; + mux_PWM5: PWM5 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad14 + &pad24 + >; + }; + mux_PWM6: PWM6 { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad25 + &pad37 + >; + }; + mux_PWM7: PWM7 { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad26 + &pad38 + >; + }; + mux_PWM8: PWM8 { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad27 + &pad39 + >; + }; + mux_PWM9: PWM9 { + #list-cells = <1>; + select = <1>; + fh,pads = < + &pad28 + &pad40 + >; + }; + + mux_RTC_CLK: RTC_CLK { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad64 + >; + }; + + mux_SADC_XAIN0: SADC_XAIN0 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad59 + >; + }; + mux_SADC_XAIN1: SADC_XAIN1 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad60 + >; + }; + mux_SADC_XAIN2: SADC_XAIN2 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad61 + >; + }; + mux_SADC_XAIN3: SADC_XAIN3 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad62 + >; + }; + + mux_SD0_CD: SD0_CD { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad52 + >; + }; + mux_SD0_CLK: SD0_CLK { + #list-cells = <1>; + select = <0>; + ds = <3>; + fh,pads = < + &pad53 + >; + }; + mux_SD0_CMD_RSP: SD0_CMD_RSP { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad54 + >; + }; + mux_SD0_DATA_0: SD0_DATA_0 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad55 + >; + }; + mux_SD0_DATA_1: SD0_DATA_1 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad56 + >; + }; + mux_SD0_DATA_2: SD0_DATA_2 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad57 + >; + }; + mux_SD0_DATA_3: SD0_DATA_3 { + #list-cells = <1>; + select = <0>; + ds = <2>; + fh,pads = < + &pad58 + >; + }; + + mux_SD1_CD: SD1_CD { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad10 + &pad22 + &pad31 + &pad41 + &pad63 + >; + }; + mux_SD1_CLK: SD1_CLK { + #list-cells = <1>; + select = <2>; + ds = <3>; + fh,pads = < + &pad9 + &pad20 + &pad30 + &pad42 + >; + }; + mux_SD1_CMD_RSP: SD1_CMD_RSP { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad11 + &pad23 + &pad32 + &pad43 + >; + }; + mux_SD1_DATA_0: SD1_DATA_0 { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad12 + &pad24 + &pad33 + &pad44 + >; + }; + mux_SD1_DATA_1: SD1_DATA_1 { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad13 + &pad25 + &pad34 + &pad45 + >; + }; + mux_SD1_DATA_2: SD1_DATA_2 { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad14 + &pad26 + &pad35 + &pad46 + >; + }; + mux_SD1_DATA_3: SD1_DATA_3 { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad15 + &pad27 + &pad36 + &pad47 + >; + }; + + mux_SENSOR_CLK: SENSOR_CLK { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad7 + >; + }; + + mux_SSI0_CLK: SSI0_CLK { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad42 + >; + }; + mux_SSI0_D2: SSI0_D2 { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad46 + >; + }; + mux_SSI0_D3: SSI0_D3 { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad47 + >; + }; + mux_SSI0_RXD: SSI0_RXD { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad45 + >; + }; + mux_SSI0_TXD: SSI0_TXD { + #list-cells = <1>; + select = <0>; + ds = <4>; + fh,pads = < + &pad44 + >; + }; + + mux_SSI1_CLK: SSI1_CLK { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad11 + &pad37 + &pad48 + &pad53 + >; + }; + mux_SSI1_RXD: SSI1_RXD { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad14 + &pad40 + &pad51 + &pad55 + >; + }; + mux_SSI1_TXD: SSI1_TXD { + #list-cells = <1>; + select = <2>; + ds = <2>; + fh,pads = < + &pad13 + &pad39 + &pad50 + &pad54 + >; + }; + + mux_SSI2_CLK: SSI2_CLK { + #list-cells = <1>; + select = <1>; + ds = <2>; + fh,pads = < + &pad37 + &pad48 + >; + }; + mux_SSI2_CSN_0: SSI2_CSN_0 { + #list-cells = <1>; + select = <1>; + ds = <2>; + fh,pads = < + &pad38 + &pad49 + >; + }; + mux_SSI2_RXD: SSI2_RXD { + #list-cells = <1>; + select = <1>; + ds = <2>; + fh,pads = < + &pad40 + &pad51 + >; + }; + mux_SSI2_TXD: SSI2_TXD { + #list-cells = <1>; + select = <1>; + ds = <2>; + fh,pads = < + &pad39 + &pad50 + >; + }; + + mux_UART0_RX: UART0_RX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad4 + >; + }; + mux_UART0_TX: UART0_TX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad3 + >; + }; + + mux_UART1_RX: UART1_RX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad10 + &pad33 + &pad47 + >; + }; + mux_UART1_TX: UART1_TX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad9 + &pad32 + &pad46 + >; + }; + + mux_UART2_RX: UART2_RX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad14 + &pad17 + &pad35 + &pad58 + >; + }; + mux_UART2_TX: UART2_TX { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad13 + &pad16 + &pad34 + &pad57 + >; + }; + + mux_USB_PWREN: USB_PWREN { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad15 + &pad41 + >; + }; + + mux_GPIO0: GPIO0 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad37 + >; + }; + mux_GPIO1: GPIO1 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad38 + >; + }; + mux_GPIO2: GPIO2 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad39 + >; + }; + mux_GPIO3: GPIO3 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad40 + >; + }; + mux_GPIO4: GPIO4 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad41 + >; + }; + mux_GPIO5: GPIO5 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad42 + >; + }; + mux_GPIO6: GPIO6 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad43 + >; + }; + mux_GPIO7: GPIO7 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad44 + >; + }; + mux_GPIO8: GPIO8 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad45 + >; + }; + mux_GPIO9: GPIO9 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad46 + >; + }; + mux_GPIO10: GPIO10 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad47 + >; + }; + mux_GPIO11: GPIO11 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad48 + >; + }; + mux_GPIO12: GPIO12 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad7 + >; + }; + mux_GPIO13: GPIO13 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad8 + >; + }; + mux_GPIO14: GPIO14 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad49 + >; + }; + mux_GPIO15: GPIO15 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad50 + >; + }; + mux_GPIO16: GPIO16 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad51 + >; + }; + mux_GPIO17: GPIO17 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad52 + >; + }; + mux_GPIO18: GPIO18 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad53 + >; + }; + mux_GPIO19: GPIO19 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad54 + >; + }; + mux_GPIO20: GPIO20 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad55 + >; + }; + mux_GPIO21: GPIO21 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad56 + >; + }; + mux_GPIO22: GPIO22 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad57 + >; + }; + mux_GPIO23: GPIO23 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad58 + >; + }; + mux_GPIO24: GPIO24 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad61 + >; + }; + mux_GPIO25: GPIO25 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad62 + >; + }; + mux_GPIO26: GPIO26 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad59 + >; + }; + mux_GPIO27: GPIO27 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad60 + >; + }; + mux_GPIO28: GPIO28 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad63 + >; + }; + mux_GPIO29: GPIO29 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad64 + >; + }; + mux_GPIO30: GPIO30 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad0 + >; + }; + mux_GPIO31: GPIO31 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad1 + >; + }; + mux_GPIO32: GPIO32 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad2 + >; + }; + mux_GPIO33: GPIO33 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad3 + >; + }; + mux_GPIO34: GPIO34 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad4 + >; + }; + mux_GPIO35: GPIO35 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad5 + >; + }; + mux_GPIO36: GPIO36 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad6 + >; + }; + mux_GPIO37: GPIO37 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad11 + >; + }; + mux_GPIO38: GPIO38 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad12 + >; + }; + mux_GPIO39: GPIO39 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad9 + >; + }; + mux_GPIO40: GPIO40 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad10 + >; + }; + mux_GPIO41: GPIO41 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad13 + >; + }; + mux_GPIO42: GPIO42 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad14 + >; + }; + mux_GPIO43: GPIO43 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad16 + >; + }; + mux_GPIO44: GPIO44 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad17 + >; + }; + mux_GPIO45: GPIO45 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad18 + >; + }; + mux_GPIO46: GPIO46 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad19 + >; + }; + mux_GPIO47: GPIO47 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad15 + >; + }; + mux_GPIO48: GPIO48 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad20 + >; + }; + mux_GPIO49: GPIO49 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad22 + >; + }; + mux_GPIO50: GPIO50 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad23 + >; + }; + mux_GPIO51: GPIO51 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad24 + >; + }; + mux_GPIO52: GPIO52 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad25 + >; + }; + mux_GPIO53: GPIO53 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad26 + >; + }; + mux_GPIO54: GPIO54 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad27 + >; + }; + mux_GPIO55: GPIO55 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad28 + >; + }; + mux_GPIO56: GPIO56 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad29 + >; + }; + mux_GPIO57: GPIO57 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad30 + >; + }; + mux_GPIO58: GPIO58 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad31 + >; + }; + mux_GPIO59: GPIO59 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad32 + >; + }; + mux_GPIO60: GPIO60 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad33 + >; + }; + mux_GPIO61: GPIO61 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad34 + >; + }; + mux_GPIO62: GPIO62 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad35 + >; + }; + mux_GPIO63: GPIO63 { + #list-cells = <1>; + select = <0>; + fh,pads = < + &pad36 + >; + }; + }; + pinpad: pinpad { + compatible = "fh,fh-pinpad"; + pad0: PAD_BOOT_MODE_CFG { + index = <0>; + funcs = "GPIO30"; + pupd = <1>; + ds = <0>; + }; + pad1: PAD_BOOT_SEL1_CFG { + index = <1>; + funcs = "GPIO31", "ETH_LINK_ACT"; + pupd = <1>; + ds = <0>; + }; + pad2: PAD_BOOT_SEL0_CFG { + index = <2>; + funcs = "GPIO32", "ETH_LINK_STA", "ETH_LINK_SPD"; + pupd = <1>; + ds = <0>; + }; + pad3: PAD_UART0_TX_CFG { + index = <3>; + funcs = "UART0_TX", "GPIO33"; + pupd = <0>; + ds = <0>; + }; + pad4: PAD_UART0_RX_CFG { + index = <4>; + funcs = "UART0_RX", "GPIO34"; + pupd = <0>; + ds = <0>; + }; + pad5: PAD_I2C0_SCL_CFG { + index = <5>; + funcs = "I2C0_SCL", "GPIO35"; + pupd = <1>; + ds = <0>; + }; + pad6: PAD_I2C0_SDA_CFG { + index = <6>; + funcs = "I2C0_SDA", "GPIO36"; + pupd = <1>; + ds = <0>; + }; + pad7: PAD_SENSOR_CLK_CFG { + index = <7>; + funcs = "SENSOR_CLK", "GPIO12"; + pupd = <0>; + ds = <0>; + }; + pad8: PAD_SENSOR_RSTN_CFG { + index = <8>; + funcs = "GPIO13"; + pupd = <0>; + ds = <0>; + }; + pad9: PAD_UART1_TX_CFG { + index = <9>; + funcs = "UART1_TX", "GPIO39", "", "SD1_CLK", "", "", + "TEST_O_INT_RMII_CLK"; + pupd = <0>; + ds = <0>; + }; + pad10: PAD_UART1_RX_CFG { + index = <10>; + funcs = "UART1_RX", "GPIO40", "", "SD1_CD", "", "", + "TEST_INT_RMII_TXD_0"; + pupd = <0>; + ds = <0>; + }; + pad11: PAD_I2C1_SCL_CFG { + index = <11>; + funcs = "I2C1_SCL", "GPIO37", "PWM2", "SD1_CMD_RSP", "", + "SSI1_CLK", "TEST_INT_RMII_TXD_1"; + pupd = <0>; + ds = <0>; + }; + pad12: PAD_I2C1_SDA_CFG { + index = <12>; + funcs = "I2C1_SDA", "GPIO38", "PWM3", "SD1_DATA_0", "", + "SSI1_CSN_0", "TEST_INT_RMII_TXEN"; + pupd = <0>; + ds = <0>; + }; + pad13: PAD_UART2_TX_CFG { + index = <13>; + funcs = "UART2_TX", "GPIO41", "PWM4", "SD1_DATA_1", "", + "SSI1_TXD", "TEST_O_INT_RMII_RXD_0"; + pupd = <0>; + ds = <0>; + }; + pad14: PAD_UART2_RX_CFG { + index = <14>; + funcs = "UART2_RX", "GPIO42", "PWM5", "SD1_DATA_2", "", + "SSI1_RXD", "TEST_O_INT_RMII_RXD_1"; + pupd = <0>; + ds = <0>; + }; + pad15: PAD_USB_PWREN_CFG { + index = <15>; + funcs = "USB_PWREN", "GPIO47", "", "SD1_DATA_3", "", "", + "TEST_O_INT_RMII_CRSDV"; + pupd = <0>; + ds = <0>; + }; + pad16: PAD_PWM0_CFG { + index = <16>; + funcs = "PWM0", "GPIO43", "I2C2_SCL", "UART2_TX", "", "", + "TEST_O_INT_RMII_TXD_0"; + pupd = <0>; + ds = <0>; + }; + pad17: PAD_PWM1_CFG { + index = <17>; + funcs = "PWM1", "GPIO44", "I2C2_SDA", "UART2_RX", "", "", + "TEST_O_INT_RMII_TXD_1"; + pupd = <0>; + ds = <0>; + }; + pad18: PAD_PWM2_CFG { + index = <18>; + funcs = "PWM2", "GPIO45"; + pupd = <0>; + ds = <0>; + }; + pad19: PAD_PWM3_CFG { + index = <19>; + funcs = "PWM3", "GPIO46"; + pupd = <0>; + ds = <0>; + }; + pad20: PAD_MAC_RMII_CLK_CFG { + index = <20>; + funcs = "MAC_RMII_CLK", "GPIO48", "SD1_CLK", "PWM2"; + pupd = <0>; + ds = <0>; + }; + pad21: PAD_MAC_REF_CLK_CFG { + index = <21>; + funcs = "MAC_REF_CLK"; + pupd = <0>; + ds = <2>; + }; + pad22: PAD_MAC_TXD0_CFG { + index = <22>; + funcs = "MAC_TXD_0", "GPIO49", "SD1_CD", "PWM3"; + pupd = <0>; + ds = <0>; + }; + pad23: PAD_MAC_TXD1_CFG { + index = <23>; + funcs = "MAC_TXD_1", "GPIO50", "SD1_CMD_RSP", "PWM4"; + pupd = <0>; + ds = <0>; + }; + pad24: PAD_MAC_TXEN_CFG { + index = <24>; + funcs = "MAC_TXEN", "GPIO51", "SD1_DATA_0", "PWM5"; + pupd = <0>; + ds = <0>; + }; + pad25: PAD_MAC_RXD0_CFG { + index = <25>; + funcs = "MAC_RXD_0", "GPIO52", "SD1_DATA_1", "PWM6"; + pupd = <0>; + ds = <0>; + }; + pad26: PAD_MAC_RXD1_CFG { + index = <26>; + funcs = "MAC_RXD_1", "GPIO53", "SD1_DATA_2", "PWM7"; + pupd = <0>; + ds = <0>; + }; + pad27: PAD_MAC_RXDV_CFG { + index = <27>; + funcs = "MAC_RXDV", "GPIO54", "SD1_DATA_3", "PWM8"; + pupd = <0>; + ds = <0>; + }; + pad28: PAD_MAC_MDC_CFG { + index = <28>; + funcs = "MAC_MDC", "GPIO55", "", "PWM9"; + pupd = <0>; + ds = <0>; + }; + pad29: PAD_MAC_MDIO_CFG { + index = <29>; + funcs = "MAC_MDIO", "GPIO56"; + pupd = <0>; + ds = <0>; + }; + pad30: PAD_SD1_CLK_CFG { + index = <30>; + funcs = "SD1_CLK", "GPIO57", "I2C1_SCL"; + pupd = <0>; + ds = <0>; + }; + pad31: PAD_SD1_CD_CFG { + index = <31>; + funcs = "SD1_CD", "GPIO58", "I2C1_SDA"; + pupd = <0>; + ds = <0>; + }; + pad32: PAD_SD1_CMD_RSP_CFG { + index = <32>; + funcs = "SD1_CMD_RSP", "GPIO59", "UART1_TX"; + pupd = <0>; + ds = <0>; + }; + pad33: PAD_SD1_DATA_0_CFG { + index = <33>; + funcs = "SD1_DATA_0", "GPIO60", "UART1_RX"; + pupd = <0>; + ds = <0>; + }; + pad34: PAD_SD1_DATA_1_CFG { + index = <34>; + funcs = "SD1_DATA_1", "GPIO61", "UART2_TX"; + pupd = <0>; + ds = <0>; + }; + pad35: PAD_SD1_DATA_2_CFG { + index = <35>; + funcs = "SD1_DATA_2", "GPIO62", "UART2_RX"; + pupd = <0>; + ds = <0>; + }; + pad36: PAD_SD1_DATA_3_CFG { + index = <36>; + funcs = "SD1_DATA_3", "GPIO63"; + pupd = <0>; + ds = <0>; + }; + pad37: PAD_GPIO_0_CFG { + index = <37>; + funcs = "ARM_JTAG_TRSTN", "GPIO0", "AC_I2S_DO", "DW_I2S_DO", + "SSI1_CLK", "SSI2_CLK", "ACIP_ADDAT", "PWM6", + "TEST_O_INT_SMI_MDC"; + pupd = <0>; + ds = <0>; + }; + pad38: PAD_GPIO_1_CFG { + index = <38>; + funcs = "ARM_JTAG_TDO", "GPIO1", "AC_I2S_DI", "DW_I2S_DI", + "SSI1_CSN_0", "SSI2_CSN_0", "ACIP_DADAT", "PWM7", + "TEST_O_INT_SMI_MDIO_I"; + pupd = <0>; + ds = <0>; + }; + pad39: PAD_GPIO_2_CFG { + index = <39>; + funcs = "ARM_JTAG_TDI", "GPIO2", "AC_I2S_CLK", "DW_I2S_CLK", + "SSI1_TXD", "SSI2_TXD", "ACIP_ADBCLK", "PWM8", + "TEST_O_INT_SMI_MDIO_O"; + pupd = <0>; + ds = <0>; + }; + pad40: PAD_GPIO_3_CFG { + index = <40>; + funcs = "ARM_JTAG_TCK", "GPIO3", "AC_I2S_WS", "DW_I2S_WS", + "SSI1_RXD", "SSI2_RXD", "ACIP_ADLRC", "PWM9", + "TEST_I_INT_SMI_MDIO_I"; + pupd = <0>; + ds = <0>; + }; + pad41: PAD_GPIO_4_CFG { + index = <41>; + funcs = "ARM_JTAG_TMS", "GPIO4", "AC_MCLK", "USB_PWREN", + "SD1_CD", "TEST_I_INT_SMI_MDC"; + pupd = <0>; + ds = <0>; + }; + pad42: PAD_SSI0_CLK_CFG { + index = <42>; + funcs = "SSI0_CLK", "GPIO5", "", "", "SD1_CLK"; + pupd = <0>; + ds = <2>; + }; + pad43: PAD_SSI0_CSN_0_CFG { + index = <43>; + funcs = "SSI0_CSN_0", "GPIO6", "", "", "SD1_CMD_RSP"; + pupd = <0>; + ds = <2>; + }; + pad44: PAD_SSI0_TXD_CFG { + index = <44>; + funcs = "SSI0_TXD", "GPIO7", "", "", "SD1_DATA_0"; + pupd = <0>; + ds = <2>; + }; + pad45: PAD_SSI0_RXD_CFG { + index = <45>; + funcs = "SSI0_RXD", "GPIO8", "", "", "SD1_DATA_1"; + pupd = <0>; + ds = <2>; + }; + pad46: PAD_SSI0_D2_CFG { + index = <46>; + funcs = "SSI0_D2", "GPIO9", "UART1_TX", "I2C1_SCL", + "SD1_DATA_2"; + pupd = <0>; + ds = <2>; + }; + pad47: PAD_SSI0_D3_CFG { + index = <47>; + funcs = "SSI0_D3", "GPIO10", "UART1_RX", "I2C1_SDA", + "SD1_DATA_3"; + pupd = <0>; + ds = <2>; + }; + pad48: PAD_SSI1_CLK_CFG { + index = <48>; + funcs = "SSI1_CLK", "GPIO11", "SSI2_CLK"; + pupd = <0>; + ds = <0>; + }; + pad49: PAD_SSI1_CSN_0_CFG { + index = <49>; + funcs = "SSI1_CSN_0", "GPIO14", "SSI2_CSN_0"; + pupd = <0>; + ds = <0>; + }; + pad50: PAD_SSI1_TXD_CFG { + index = <50>; + funcs = "SSI1_TXD", "GPIO15", "SSI2_TXD"; + pupd = <0>; + ds = <0>; + }; + pad51: PAD_SSI1_RXD_CFG { + index = <51>; + funcs = "SSI1_RXD", "GPIO16", "SSI2_RXD"; + pupd = <0>; + ds = <0>; + }; + pad52: PAD_SD0_CD_CFG { + index = <52>; + funcs = "SD0_CD", "GPIO17", "", "ARC_JTAG_TRSTN", + "PAE_JTAG_TRSTN"; + pupd = <0>; + ds = <0>; + }; + pad53: PAD_SD0_CLK_CFG { + index = <53>; + funcs = "SD0_CLK", "GPIO18", "SSI1_CLK", "ARC_JTAG_TDO", + "PAE_JTAG_TDO"; + pupd = <0>; + ds = <2>; + }; + pad54: PAD_SD0_CMD_RSP_CFG { + index = <54>; + funcs = "SD0_CMD_RSP", "GPIO19", "SSI1_TXD", "ARC_JTAG_TDI", + "PAE_JTAG_TDI"; + pupd = <0>; + ds = <2>; + }; + pad55: PAD_SD0_DATA_0_CFG { + index = <55>; + funcs = "SD0_DATA_0", "GPIO20", "SSI1_RXD", "ARC_JTAG_TCK", + "PAE_JTAG_TCK"; + pupd = <0>; + ds = <2>; + }; + pad56: PAD_SD0_DATA_1_CFG { + index = <56>; + funcs = "SD0_DATA_1", "GPIO21", "SSI1_CSN_0", "ARC_JTAG_TMS", + "PAE_JTAG_TMS"; + pupd = <0>; + ds = <2>; + }; + pad57: PAD_SD0_DATA_2_CFG { + index = <57>; + funcs = "SD0_DATA_2", "GPIO22", "", "UART2_TX", "I2C2_SCL", "", + "ACIP_DABCLK"; + pupd = <0>; + ds = <2>; + }; + pad58: PAD_SD0_DATA_3_CFG { + index = <58>; + funcs = "SD0_DATA_3", "GPIO23", "SSI1_CSN_0", "UART2_RX", + "I2C2_SDA", "", "ACIP_DALRC"; + pupd = <0>; + ds = <2>; + }; + pad59: PAD_SADC_XAIN0_CFG { + index = <59>; + funcs = "SADC_XAIN0", "GPIO26"; + pupd = <0>; + ds = <0>; + }; + pad60: PAD_SADC_XAIN1_CFG { + index = <60>; + funcs = "SADC_XAIN1", "GPIO27"; + pupd = <0>; + ds = <0>; + }; + pad61: PAD_SADC_XAIN2_CFG { + index = <61>; + funcs = "SADC_XAIN2", "GPIO24"; + pupd = <0>; + ds = <0>; + }; + pad62: PAD_SADC_XAIN3_CFG { + index = <62>; + funcs = "SADC_XAIN3", "GPIO25"; + pupd = <0>; + ds = <0>; + }; + pad63: PAD_GPIO_28_CFG { + index = <63>; + funcs = "GPIO28", "", "ETH_LINK_ACT", "PWM10", + "USB_DBG_CLK", "SD1_CD", "TEST_O_INT_RMII_TXEN", + "MAC_MDC"; + pupd = <0>; + ds = <0>; + }; + pad64: PAD_GPIO_29_CFG { + index = <64>; + funcs = "GPIO29", "", "ETH_LINK_STA", "PWM11", "RTC_CLK", + "ETH_LINK_SPD", "TEST_O_INT_SMI_MDIO_OE", + "MAC_MDIO"; + pupd = <0>; + ds = <0>; + }; + }; + }; +}; diff --git a/arch/arm/configs/fh8852v200_defconfig b/arch/arm/configs/fh8852v200_defconfig new file mode 100644 index 00000000..b8c52f46 --- /dev/null +++ b/arch/arm/configs/fh8852v200_defconfig @@ -0,0 +1,2253 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 4.9.129 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y + +# +# General setup +# +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_TINY_KERNEL=y +CONFIG_NTP=y +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_LZMA is not set +CONFIG_KERNEL_XZ=y +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_NO_COMPRESS is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_FHANDLE is not set +CONFIG_USELIB=y +# CONFIG_AUDIT is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_IRQ_DOMAIN=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_GENERIC_CLOCKEVENTS=y + +# +# Timers subsystem +# +CONFIG_HZ_PERIODIC=y +# CONFIG_NO_HZ_IDLE is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set + +# +# RCU Subsystem +# +CONFIG_TINY_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +# CONFIG_TASKS_RCU is not set +# CONFIG_RCU_STALL_COMMON is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_EXPEDITE_BOOT is not set +# CONFIG_BUILD_BIN2C is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_NMI_LOG_BUF_SHIFT=13 +CONFIG_GENERIC_SCHED_CLOCK=y +# CONFIG_CGROUPS is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SCHED_DL is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="usr/rootfs.cpio.xz" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +CONFIG_RD_XZ=y +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_HAVE_UID16=y +CONFIG_BPF=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +CONFIG_SYSFS_SYSCALL=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set +CONFIG_KALLSYMS_BASE_RELATIVE=y +CONFIG_PRINTK=y +CONFIG_PRINTK_NMI=y +# CONFIG_BUG is not set +# CONFIG_ELF_CORE is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +# CONFIG_BPF_SYSCALL is not set +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_ADVISE_SYSCALLS=y +# CONFIG_USERFAULTFD is not set +CONFIG_MEMBARRIER=y +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SYSTEM_DATA_VERIFICATION is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_UPROBES is not set +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_GCC_PLUGINS=y +# CONFIG_GCC_PLUGINS is not set +CONFIG_HAVE_CC_STACKPROTECTOR=y +# CONFIG_CC_STACKPROTECTOR is not set +CONFIG_CC_STACKPROTECTOR_NONE=y +# CONFIG_CC_STACKPROTECTOR_REGULAR is not set +# CONFIG_CC_STACKPROTECTOR_STRONG is not set +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_EXIT_THREAD=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=8 +CONFIG_ARCH_MMAP_RND_BITS_MAX=16 +CONFIG_ARCH_MMAP_RND_BITS=8 +# CONFIG_HAVE_ARCH_HASH is not set +# CONFIG_ISA_BUS_API is not set +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OLD_SIGACTION=y +# CONFIG_CPU_NO_EFFICIENT_FFS is not set +# CONFIG_HAVE_ARCH_VMAP_STACK is not set + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_CMDLINE_PARSER is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_EFI_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_MULTIPLATFORM is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +CONFIG_ARCH_FULLHAN=y +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP1 is not set + +# +# Fullhan platform type +# +# CONFIG_FH_FASTBOOT is not set +# CONFIG_ARCH_FH8833 is not set +# CONFIG_ARCH_FH8856 is not set +# CONFIG_ARCH_FH8852 is not set +# CONFIG_ARCH_FH8626V100 is not set +CONFIG_ARCH_FH885xV200=y +# CONFIG_ARCH_FH865x is not set + +CONFIG_FH_CHIP_NAME="fh8852v200" +# CONFIG_MACH_FH8856V200 is not set +CONFIG_MACH_FH8852V200=y +# CONFIG_MACH_FH8858V200 is not set + +# +# Processor Type +# +CONFIG_CPU_V6=y +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_KUSER_HELPERS=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +# CONFIG_DEBUG_RODATA is not set +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_PJ4B_ERRATA_4742=y +# CONFIG_ARM_ERRATA_326103 is not set +CONFIG_ARM_ERRATA_411920=y +# CONFIG_ARM_ERRATA_364296 is not set + +# +# Bus support +# +# CONFIG_PCI_DOMAINS_GENERIC is not set +# CONFIG_PCI_SYSCALL is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_3G_OPT is not set +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_ARCH_NR_GPIO=0 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ_FIXED=0 +CONFIG_HZ_100=y +# CONFIG_HZ_200 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_500 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +# CONFIG_SCHED_HRTICK is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +# CONFIG_HIGHMEM is not set +CONFIG_CPU_SW_DOMAIN_PAN=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +# CONFIG_ARM_MODULE_PLTS is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_NO_BOOTMEM=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_CLEANCACHE is not set +# CONFIG_CMA is not set +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +# CONFIG_ZSMALLOC is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +CONFIG_SWIOTLB=y +CONFIG_IOMMU_HELPER=y +# CONFIG_PARAVIRT is not set +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set + +# +# Boot options +# +# CONFIG_USE_OF is not set +CONFIG_ATAGS=y +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_AUTO_ZRELADDR=y + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# CPU Idle +# +# CONFIG_CPU_IDLE is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ELFCORE=y +CONFIG_BINFMT_SCRIPT=y +# CONFIG_BINFMT_FLAT is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y + +# +# Power management options +# +# CONFIG_SUSPEND is not set +# CONFIG_PM is not set +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_NET_IP_TUNNEL=y +# CONFIG_IP_MROUTE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_NET_IPVTI is not set +# CONFIG_NET_UDP_TUNNEL is not set +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_INET_DIAG_DESTROY is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +# CONFIG_IPV6_VTI is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_FOU is not set +# CONFIG_IPV6_FOU_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NET_PTP_CLASSIFY is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +CONFIG_HAVE_NET_DSA=y +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_MPLS is not set +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_NET_NCSI is not set +# CONFIG_SOCK_CGROUP_DATA is not set +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +# CONFIG_BPF_JIT is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +# CONFIG_STREAM_PARSER is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=y +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +# CONFIG_CFG80211_DEFAULT_PS is not set +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_CFG80211_WEXT=y +CONFIG_LIB80211=y +CONFIG_LIB80211_CRYPT_WEP=y +CONFIG_LIB80211_CRYPT_CCMP=y +CONFIG_LIB80211_CRYPT_TKIP=y +# CONFIG_LIB80211_DEBUG is not set +# CONFIG_MAC80211 is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +# CONFIG_RFKILL_INPUT is not set +# CONFIG_RFKILL_GPIO is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_LWTUNNEL is not set +CONFIG_DST_CACHE=y +# CONFIG_NET_DEVLINK is not set +CONFIG_MAY_USE_DEVLINK=y +CONFIG_HAVE_CBPF_JIT=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +# CONFIG_DMA_SHARED_BUFFER is not set + +# +# Bus devices +# +# CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR & LPDDR2 PCM memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_LPDDR2_NVM is not set +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_MT81xx_NOR is not set +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MTD_UBI is not set +# CONFIG_OF is not set +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_NVME_TARGET is not set + +# +# Misc devices +# +# CONFIG_FH_DW_I2S is not set +# CONFIG_FH_ACW is not set +CONFIG_FH_SADC_V3=y +CONFIG_FH_EFUSE=y +# CONFIG_FH_L2MEM is not set +CONFIG_FH_PINCTRL_MISC_DEV=y +CONFIG_FH_CLK_MISC=y +CONFIG_FH_PERF_MON=y +# CONFIG_FH_TSENSOR is not set +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_SRAM is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set + +# +# Intel MIC Bus Driver +# + +# +# SCIF Bus Driver +# + +# +# VOP Bus Driver +# + +# +# Intel MIC Host Driver +# + +# +# Intel MIC Card Driver +# + +# +# SCIF Driver +# + +# +# Intel MIC Coprocessor State Management (COSM) Drivers +# + +# +# VOP Driver +# +# CONFIG_ECHO is not set +# CONFIG_CXL_BASE is not set +# CONFIG_CXL_AFU_DRIVER_OPS is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_MACSEC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_TUN is not set +# CONFIG_TUN_VNET_CROSS_LE is not set +# CONFIG_VETH is not set +# CONFIG_NLMON is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +CONFIG_ETHERNET=y +# CONFIG_ALTERA_TSE is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_NET_VENDOR_FULLHAN=y +CONFIG_FH_GMAC=y +CONFIG_FH_GMAC_DA=y +CONFIG_PHYLIB=y +CONFIG_SWPHY=y + +# +# MDIO bus device drivers +# +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_BITBANG is not set + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_AT803X_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +CONFIG_FIXED_PHY=y +# CONFIG_ICPLUS_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +CONFIG_USB_NET_DRIVERS=y +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_RTL8152 is not set +# CONFIG_USB_LAN78XX is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_IPHETH is not set +CONFIG_WLAN=y +CONFIG_WLAN_VENDOR_ADMTEK=y +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +# CONFIG_ATH6KL is not set +CONFIG_WLAN_VENDOR_ATMEL=y +CONFIG_WLAN_VENDOR_BROADCOM=y +# CONFIG_BRCMFMAC is not set +CONFIG_WLAN_VENDOR_CISCO=y +CONFIG_WLAN_VENDOR_INTEL=y +CONFIG_WLAN_VENDOR_INTERSIL=y +CONFIG_HOSTAP=y +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +CONFIG_WLAN_VENDOR_MARVELL=y +# CONFIG_LIBERTAS is not set +# CONFIG_MWIFIEX is not set +CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_WLAN_VENDOR_REALTEK=y +CONFIG_WLAN_VENDOR_RSI=y +CONFIG_WLAN_VENDOR_ST=y +CONFIG_WLAN_VENDOR_TI=y +CONFIG_WLAN_VENDOR_ZYDAS=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_ISDN is not set +# CONFIG_NVM is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVMEM=y +# CONFIG_DEVKMEM is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set +CONFIG_SERIAL_FULLHAN=y +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_ST_ASC is not set +# CONFIG_SERIAL_STM32 is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_SMBUS is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_FH_INTERRUPT=y +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_EMEV2 is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_DESIGNWARE is not set +CONFIG_SPI_FH=y +# CONFIG_SPI_FH_SLAVE is not set + +# +# spi multi wire support +# +CONFIG_SPI_USE_MULTI_WIRE=y +CONFIG_SPI_SWAP_MAX_DATA_WIDTH=16 +# CONFIG_SPI_USE_DMA is not set +CONFIG_SPI_TINY_MEM=y +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +# CONFIG_PTP_1588_CLOCK is not set + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers +# +CONFIG_GPIO_FH=y +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_MPC8XXX is not set +# CONFIG_GPIO_ZX is not set + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_TPIC2810 is not set +# CONFIG_GPIO_TS4900 is not set + +# +# MFD GPIO expanders +# +# CONFIG_HTC_EGPIO is not set + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set + +# +# SPI or I2C GPIO expanders +# + +# +# USB GPIO expanders +# +# CONFIG_W1 is not set +# CONFIG_POWER_AVS is not set +# CONFIG_POWER_RESET is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_CORE is not set +# CONFIG_WATCHDOG_NOWAYOUT is not set +# CONFIG_WATCHDOG_SYSFS is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_FH_WATCHDOG=y +# CONFIG_MEN_A21_WDT is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set + +# +# Watchdog Pretimeout Governors +# +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_EXYNOS_LPASS is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_INTEL_SOC_PMIC is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_PM8921_CORE is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RTSX_USB is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set +# CONFIG_SOUND is not set + +# +# HID support +# +# CONFIG_HID is not set + +# +# USB HID support +# +# CONFIG_USB_HID is not set +# CONFIG_HID_PID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +CONFIG_USB_DYNAMIC_MINORS=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +CONFIG_USB_WUSB_CBAF=y +# CONFIG_USB_WUSB_CBAF_DEBUG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_MAX3421_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +CONFIG_USB_WDM=y +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_DWC3 is not set +CONFIG_USB_DWC2=y +CONFIG_USB_DWC2_HOST=y + +# +# Gadget/Dual-role mode requires USB Gadget support to be enabled +# +# CONFIG_USB_DWC2_VBVALIDOVEN is not set +# CONFIG_USB_DWC2_DEBUG is not set +# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set +# CONFIG_USB_DWC2_HOST_DMA_DESC_NUM_DYNAMIC is not set +CONFIG_USB_DWC2_DMA=y +# CONFIG_USB_DWC2_DMA_DESC is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set + +# +# USB Physical Layer drivers +# +# CONFIG_USB_PHY is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ULPI is not set +# CONFIG_USB_GADGET is not set +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_UWB is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SPI is not set +CONFIG_MMC_FH=y +CONFIG_MMC_FH_IDMAC=y +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_MTK is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +# CONFIG_EDAC is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV8803 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6916 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RX6110 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_MCP795 is not set +# CONFIG_RTC_I2C_AND_SPI is not set + +# +# SPI and I2C RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_FH=y +CONFIG_USE_TSENSOR=y +# CONFIG_USE_TSENSOR_OFFSET is not set + +# +# HID Sensor RTC drivers +# +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +# CONFIG_DW_DMAC is not set +CONFIG_CHANNEL_ALLOC_MEM_CLASSICS=y +# CONFIG_FH_DMAC is not set +CONFIG_FH_AXI_DMAC=y +CONFIG_FH_DMAC_MISC=y + +# +# dma tinyconfig +# +CONFIG_CHANNEL_ALLOC_DESC_NUM=32 +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_NBPFAXI_DMA is not set +# CONFIG_QCOM_HIDMA_MGMT is not set +# CONFIG_QCOM_HIDMA is not set + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set + +# +# DMABUF options +# +# CONFIG_SYNC_FILE is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VIRT_DRIVERS is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_STAGING is not set +# CONFIG_GOLDFISH is not set +# CONFIG_CHROME_PLATFORMS is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_COMMON_CLK_NXP is not set +# CONFIG_COMMON_CLK_PWM is not set +# CONFIG_COMMON_CLK_PXA is not set +# CONFIG_COMMON_CLK_PIC32 is not set + +# +# Hardware Spinlock drivers +# + +# +# Clock Source drivers +# +CONFIG_FULLHAN_TIMER=y +# CONFIG_FH_SIMPLE_TIMER is not set +# CONFIG_ARM_TIMER_SP804 is not set +# CONFIG_ATMEL_PIT is not set +# CONFIG_SH_TIMER_CMT is not set +# CONFIG_SH_TIMER_MTU2 is not set +# CONFIG_SH_TIMER_TMU is not set +# CONFIG_EM_TIMER_STI is not set +# CONFIG_MAILBOX is not set +# CONFIG_IOMMU_SUPPORT is not set + +# +# Remoteproc drivers +# +# CONFIG_STE_MODEM_RPROC is not set + +# +# Rpmsg drivers +# + +# +# SOC (System On Chip) specific Drivers +# + +# +# Broadcom SoC drivers +# +# CONFIG_SOC_BRCMSTB is not set +# CONFIG_SUNXI_SRAM is not set +# CONFIG_SOC_TI is not set +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +CONFIG_PWM=y +# CONFIG_PWM_SYSFS is not set +# CONFIG_DEBUG_PWM_FS is not set +CONFIG_PWM_FULLHAN=y +CONFIG_FH_PWM_NUM=14 +# CONFIG_PWM_PCA9685 is not set +CONFIG_ARM_GIC_MAX_NR=1 +CONFIG_FULLHAN_INTC=y +# CONFIG_IPACK_BUS is not set +# CONFIG_RESET_CONTROLLER is not set +# CONFIG_FMC is not set + +# +# PHY Subsystem +# +# CONFIG_GENERIC_PHY is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_FH_USB2_PHY is not set +# CONFIG_PHY_SAMSUNG_USB2 is not set +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +# CONFIG_RAS is not set + +# +# Android +# +# CONFIG_ANDROID is not set +# CONFIG_NVMEM is not set +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set + +# +# FPGA Configuration Support +# +# CONFIG_FPGA is not set + +# +# Firmware Drivers +# +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_FW_CFG_SYSFS is not set + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_FILE_LOCKING=y +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +# CONFIG_OVERLAY_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_PROC_CHILDREN is not set +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_WRITEBUFFER is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V2 is not set +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_SWAP is not set +# CONFIG_ROOT_NFS is not set +# CONFIG_NFSD is not set +CONFIG_GRACE_PERIOD=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_DYNAMIC_DEBUG is not set + +# +# Compile-time checks and compiler options +# +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_OPTIMIZE_INLINING=y +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_DEBUG_KERNEL is not set + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_MEMORY_INIT is not set + +# +# Debug Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_SCHED_INFO is not set +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +# CONFIG_STACKTRACE is not set + +# +# RCU Debugging +# +# CONFIG_PROVE_RCU is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_TORTURE_TEST is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_HWLAT_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_FTRACE_SYSCALLS is not set +# CONFIG_TRACER_SNAPSHOT is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_PROBE_EVENTS is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +CONFIG_TRACING_EVENTS_GPIO=y + +# +# Runtime Testing +# +# CONFIG_LKDTM is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_HASH is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_MEMTEST is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set +# CONFIG_UBSAN is not set +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +# CONFIG_STRICT_DEVMEM is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_UART_8250 is not set +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_DEBUG_SET_MODULE_RONX is not set +# CONFIG_CORESIGHT is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_BIG_KEYS is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEY_DH_OPERATIONS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y +# CONFIG_HARDENED_USERCOPY is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_KPP2=y +# CONFIG_CRYPTO_RSA is not set +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_ECDH is not set +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_MCRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_KEYWRAP is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_CMAC is not set +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +CONFIG_CRYPTO_MICHAEL_MIC=y +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +CONFIG_CRYPTO_SHA256=y +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG is not set +# CONFIG_CRYPTO_JITTERENTROPY is not set +CONFIG_CRYPTO_USER_API=y +# CONFIG_CRYPTO_USER_API_HASH is not set +CONFIG_CRYPTO_USER_API_SKCIPHER=y +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_FH_CESA is not set +CONFIG_CRYPTO_DEV_FH_AES=y +# CONFIG_CRYPTO_FH_AES_SUPPORT_DIRECT_MEM is not set +# CONFIG_FH_AES_SELF_TEST is not set +# CONFIG_ASYMMETRIC_KEY_TYPE is not set + +# +# Certificates for signature checking +# +# CONFIG_ARM_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_HAVE_ARCH_BITREVERSE is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_XZ=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y +# CONFIG_CORDIC is not set +# CONFIG_DDR is not set +# CONFIG_IRQ_POLL is not set +# CONFIG_SG_SPLIT is not set +# CONFIG_SG_POOL is not set +# CONFIG_ARCH_HAS_SG_CHAIN is not set +CONFIG_SBITMAP=y +# CONFIG_VIRTUALIZATION is not set diff --git a/arch/arm/configs/fh8852v200_of_defconfig b/arch/arm/configs/fh8852v200_of_defconfig new file mode 100644 index 00000000..a74ea3c9 --- /dev/null +++ b/arch/arm/configs/fh8852v200_of_defconfig @@ -0,0 +1,2332 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 4.9.129 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y + +# +# General setup +# +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_TINY_KERNEL=y +CONFIG_NTP=y +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_LZMA is not set +CONFIG_KERNEL_XZ=y +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_NO_COMPRESS is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_FHANDLE is not set +CONFIG_USELIB=y +# CONFIG_AUDIT is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_IRQ_DOMAIN=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_GENERIC_CLOCKEVENTS=y + +# +# Timers subsystem +# +CONFIG_HZ_PERIODIC=y +# CONFIG_NO_HZ_IDLE is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set + +# +# RCU Subsystem +# +CONFIG_TINY_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +# CONFIG_TASKS_RCU is not set +# CONFIG_RCU_STALL_COMMON is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_EXPEDITE_BOOT is not set +# CONFIG_BUILD_BIN2C is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_NMI_LOG_BUF_SHIFT=13 +CONFIG_GENERIC_SCHED_CLOCK=y +# CONFIG_CGROUPS is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SCHED_DL is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="usr/rootfs.cpio.xz" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +CONFIG_RD_XZ=y +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_HAVE_UID16=y +CONFIG_BPF=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +CONFIG_SYSFS_SYSCALL=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set +CONFIG_KALLSYMS_BASE_RELATIVE=y +CONFIG_PRINTK=y +CONFIG_PRINTK_NMI=y +# CONFIG_BUG is not set +# CONFIG_ELF_CORE is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +# CONFIG_BPF_SYSCALL is not set +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_ADVISE_SYSCALLS=y +# CONFIG_USERFAULTFD is not set +CONFIG_MEMBARRIER=y +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SYSTEM_DATA_VERIFICATION is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_UPROBES is not set +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_GCC_PLUGINS=y +# CONFIG_GCC_PLUGINS is not set +CONFIG_HAVE_CC_STACKPROTECTOR=y +# CONFIG_CC_STACKPROTECTOR is not set +CONFIG_CC_STACKPROTECTOR_NONE=y +# CONFIG_CC_STACKPROTECTOR_REGULAR is not set +# CONFIG_CC_STACKPROTECTOR_STRONG is not set +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_EXIT_THREAD=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=8 +CONFIG_ARCH_MMAP_RND_BITS_MAX=16 +CONFIG_ARCH_MMAP_RND_BITS=8 +# CONFIG_HAVE_ARCH_HASH is not set +# CONFIG_ISA_BUS_API is not set +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OLD_SIGACTION=y +# CONFIG_CPU_NO_EFFICIENT_FFS is not set +# CONFIG_HAVE_ARCH_VMAP_STACK is not set + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_CMDLINE_PARSER is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_EFI_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_MULTIPLATFORM is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +CONFIG_ARCH_FULLHAN=y +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP1 is not set + +# +# Fullhan platform type +# +# CONFIG_FH_FASTBOOT is not set +# CONFIG_ARCH_FH8833 is not set +# CONFIG_ARCH_FH8856 is not set +# CONFIG_ARCH_FH8626V100 is not set +CONFIG_ARCH_FH885xV200=y +# CONFIG_ARCH_FH865x is not set + +CONFIG_FH_CHIP_NAME="fh8852v200" +CONFIG_MACH_FH8852V200=y +# CONFIG_MACH_FH8856V200 is not set + +# +# Processor Type +# +CONFIG_CPU_V6=y +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_KUSER_HELPERS=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +# CONFIG_DEBUG_RODATA is not set +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_PJ4B_ERRATA_4742=y +# CONFIG_ARM_ERRATA_326103 is not set +CONFIG_ARM_ERRATA_411920=y +# CONFIG_ARM_ERRATA_364296 is not set + +# +# Bus support +# +# CONFIG_PCI_DOMAINS_GENERIC is not set +# CONFIG_PCI_SYSCALL is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_3G_OPT is not set +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_ARCH_NR_GPIO=0 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ_FIXED=0 +CONFIG_HZ_100=y +# CONFIG_HZ_200 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_500 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +# CONFIG_SCHED_HRTICK is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +# CONFIG_HIGHMEM is not set +CONFIG_CPU_SW_DOMAIN_PAN=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +# CONFIG_ARM_MODULE_PLTS is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_NO_BOOTMEM=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_CLEANCACHE is not set +# CONFIG_CMA is not set +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +# CONFIG_ZSMALLOC is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +CONFIG_SWIOTLB=y +CONFIG_IOMMU_HELPER=y +# CONFIG_PARAVIRT is not set +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set + +# +# Boot options +# +CONFIG_USE_OF=y +CONFIG_ATAGS=y +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND=y +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_AUTO_ZRELADDR=y +# CONFIG_EFI is not set + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# CPU Idle +# +# CONFIG_CPU_IDLE is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ELFCORE=y +CONFIG_BINFMT_SCRIPT=y +# CONFIG_BINFMT_FLAT is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y + +# +# Power management options +# +# CONFIG_SUSPEND is not set +# CONFIG_PM is not set +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_NET_IP_TUNNEL=y +# CONFIG_IP_MROUTE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_NET_IPVTI is not set +# CONFIG_NET_UDP_TUNNEL is not set +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_INET_DIAG_DESTROY is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +# CONFIG_IPV6_VTI is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_FOU is not set +# CONFIG_IPV6_FOU_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NET_PTP_CLASSIFY is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +CONFIG_HAVE_NET_DSA=y +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_MPLS is not set +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_NET_NCSI is not set +# CONFIG_SOCK_CGROUP_DATA is not set +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +# CONFIG_BPF_JIT is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +# CONFIG_STREAM_PARSER is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=y +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +# CONFIG_CFG80211_DEFAULT_PS is not set +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_CFG80211_WEXT=y +CONFIG_LIB80211=y +CONFIG_LIB80211_CRYPT_WEP=y +CONFIG_LIB80211_CRYPT_CCMP=y +CONFIG_LIB80211_CRYPT_TKIP=y +# CONFIG_LIB80211_DEBUG is not set +# CONFIG_MAC80211 is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +# CONFIG_RFKILL_INPUT is not set +# CONFIG_RFKILL_GPIO is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_LWTUNNEL is not set +CONFIG_DST_CACHE=y +# CONFIG_NET_DEVLINK is not set +CONFIG_MAY_USE_DEVLINK=y +CONFIG_HAVE_CBPF_JIT=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +# CONFIG_DMA_SHARED_BUFFER is not set + +# +# Bus devices +# +# CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_VEXPRESS_CONFIG is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR & LPDDR2 PCM memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_LPDDR2_NVM is not set +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_MT81xx_NOR is not set +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_MTD_UBI is not set +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_MDIO=y +CONFIG_OF_RESERVED_MEM=y +# CONFIG_OF_OVERLAY is not set +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_NVME_TARGET is not set + +# +# Misc devices +# +# CONFIG_FH_DW_I2S is not set +# CONFIG_FH_ACW is not set +CONFIG_FH_SADC_V3=y +CONFIG_FH_EFUSE=y +# CONFIG_FH_L2MEM is not set +CONFIG_FH_CLK_MISC=y +CONFIG_FH_PERF_MON=y +# CONFIG_FH_TSENSOR is not set +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_SRAM is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set + +# +# Intel MIC Bus Driver +# + +# +# SCIF Bus Driver +# + +# +# VOP Bus Driver +# + +# +# Intel MIC Host Driver +# + +# +# Intel MIC Card Driver +# + +# +# SCIF Driver +# + +# +# Intel MIC Coprocessor State Management (COSM) Drivers +# + +# +# VOP Driver +# +# CONFIG_ECHO is not set +# CONFIG_CXL_BASE is not set +# CONFIG_CXL_AFU_DRIVER_OPS is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_MACSEC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_TUN is not set +# CONFIG_TUN_VNET_CROSS_LE is not set +# CONFIG_VETH is not set +# CONFIG_NLMON is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +CONFIG_ETHERNET=y +# CONFIG_ALTERA_TSE is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_NET_VENDOR_FULLHAN=y +CONFIG_FH_GMAC=y +CONFIG_FH_GMAC_DA=y + +# +# fh inside or outside phy sel +# +CONFIG_PHYLIB=y +CONFIG_SWPHY=y + +# +# MDIO bus device drivers +# +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MDIO_HISI_FEMAC is not set + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_AT803X_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +CONFIG_FIXED_PHY=y +# CONFIG_ICPLUS_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +CONFIG_USB_NET_DRIVERS=y +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_RTL8152 is not set +# CONFIG_USB_LAN78XX is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_IPHETH is not set +CONFIG_WLAN=y +CONFIG_WLAN_VENDOR_ADMTEK=y +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +# CONFIG_ATH6KL is not set +CONFIG_WLAN_VENDOR_ATMEL=y +CONFIG_WLAN_VENDOR_BROADCOM=y +# CONFIG_BRCMFMAC is not set +CONFIG_WLAN_VENDOR_CISCO=y +CONFIG_WLAN_VENDOR_INTEL=y +CONFIG_WLAN_VENDOR_INTERSIL=y +CONFIG_HOSTAP=y +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +CONFIG_WLAN_VENDOR_MARVELL=y +# CONFIG_LIBERTAS is not set +# CONFIG_MWIFIEX is not set +CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_WLAN_VENDOR_REALTEK=y +CONFIG_WLAN_VENDOR_RSI=y +CONFIG_WLAN_VENDOR_ST=y +CONFIG_WLAN_VENDOR_TI=y +CONFIG_WLAN_VENDOR_ZYDAS=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_ISDN is not set +# CONFIG_NVM is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVMEM=y +# CONFIG_DEVKMEM is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set +CONFIG_SERIAL_FULLHAN=y +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +# CONFIG_SERIAL_ST_ASC is not set +# CONFIG_SERIAL_STM32 is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_XILLYBUS is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_SMBUS is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_FH_INTERRUPT=y +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_EMEV2 is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_RK3X is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_DESIGNWARE is not set +CONFIG_SPI_FH=y + +# +# spi multi wire support +# +CONFIG_SPI_USE_MULTI_WIRE=y +CONFIG_SPI_SWAP_MAX_DATA_WIDTH=16 +# CONFIG_SPI_USE_DMA is not set +CONFIG_SPI_TINY_MEM=y +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +# CONFIG_PTP_1588_CLOCK is not set + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_PINCTRL=y + +# +# Pin controllers +# +CONFIG_PINMUX=y +CONFIG_PINCTRL_FULLHAN=y +# CONFIG_PINCTRL_AMD is not set +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_GPIOLIB=y +CONFIG_OF_GPIO=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers +# +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ALTERA is not set +CONFIG_GPIO_FH=y +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_EM is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_MPC8XXX is not set +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_ZEVIO is not set +# CONFIG_GPIO_ZX is not set + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_TPIC2810 is not set +# CONFIG_GPIO_TS4900 is not set + +# +# MFD GPIO expanders +# +# CONFIG_HTC_EGPIO is not set + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set + +# +# SPI or I2C GPIO expanders +# +# CONFIG_GPIO_MCP23S08 is not set + +# +# USB GPIO expanders +# +# CONFIG_W1 is not set +# CONFIG_POWER_AVS is not set +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_BRCMKONA is not set +# CONFIG_POWER_RESET_GPIO is not set +# CONFIG_POWER_RESET_GPIO_RESTART is not set +CONFIG_POWER_RESET_FH=y +# CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_RESTART is not set +# CONFIG_POWER_RESET_SYSCON is not set +# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_CORE is not set +# CONFIG_WATCHDOG_NOWAYOUT is not set +# CONFIG_WATCHDOG_SYSFS is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_GPIO_WATCHDOG is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_FH_WATCHDOG=y +# CONFIG_MEN_A21_WDT is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set + +# +# Watchdog Pretimeout Governors +# +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_ACT8945A is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_EXYNOS_LPASS is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_INTEL_SOC_PMIC is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77620 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_PM8921_CORE is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RTSX_USB is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RK808 is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set +# CONFIG_SOUND is not set + +# +# HID support +# +# CONFIG_HID is not set + +# +# USB HID support +# +# CONFIG_USB_HID is not set +# CONFIG_HID_PID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +CONFIG_USB_DYNAMIC_MINORS=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +CONFIG_USB_WUSB_CBAF=y +# CONFIG_USB_WUSB_CBAF_DEBUG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_MAX3421_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +CONFIG_USB_WDM=y +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_DWC3 is not set +CONFIG_USB_DWC2=y +CONFIG_USB_DWC2_HOST=y + +# +# Gadget/Dual-role mode requires USB Gadget support to be enabled +# +# CONFIG_USB_DWC2_VBVALIDOVEN is not set +# CONFIG_USB_DWC2_DEBUG is not set +# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set +# CONFIG_USB_DWC2_HOST_DMA_DESC_NUM_DYNAMIC is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set + +# +# USB Physical Layer drivers +# +# CONFIG_USB_PHY is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ULPI is not set +# CONFIG_USB_GADGET is not set +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_UWB is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_PWRSEQ_EMMC=y +CONFIG_PWRSEQ_SIMPLE=y + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SPI is not set +CONFIG_MMC_FH=y +CONFIG_MMC_FH_IDMAC=y +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_MTK is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +# CONFIG_EDAC is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_HYM8563 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV8803 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6916 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RX6110 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_MCP795 is not set +# CONFIG_RTC_I2C_AND_SPI is not set + +# +# SPI and I2C RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_ZYNQMP is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_SNVS is not set +CONFIG_RTC_DRV_FH=y +CONFIG_USE_TSENSOR=y +# CONFIG_USE_TSENSOR_OFFSET is not set + +# +# HID Sensor RTC drivers +# +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +# CONFIG_DW_DMAC is not set +# CONFIG_FH_DMAC is not set +CONFIG_FH_AXI_DMAC=y +CONFIG_FH_DMAC_MISC=y + +# +# dma tinyconfig +# +CONFIG_CHANNEL_ALLOC_MEM_CLASSICS=y +CONFIG_CHANNEL_ALLOC_DESC_NUM=32 +# CONFIG_FSL_EDMA is not set +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_NBPFAXI_DMA is not set +# CONFIG_QCOM_HIDMA_MGMT is not set +# CONFIG_QCOM_HIDMA is not set + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set + +# +# DMABUF options +# +# CONFIG_SYNC_FILE is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VIRT_DRIVERS is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_STAGING is not set +# CONFIG_GOLDFISH is not set +# CONFIG_CHROME_PLATFORMS is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI514 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CDCE925 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_CLK_QORIQ is not set +# CONFIG_COMMON_CLK_NXP is not set +# CONFIG_COMMON_CLK_PWM is not set +# CONFIG_COMMON_CLK_PXA is not set +# CONFIG_COMMON_CLK_PIC32 is not set + +# +# Hardware Spinlock drivers +# + +# +# Clock Source drivers +# +CONFIG_CLKSRC_OF=y +CONFIG_CLKSRC_PROBE=y +CONFIG_FULLHAN_TIMER=y +# CONFIG_FH_SIMPLE_TIMER is not set +# CONFIG_ARM_TIMER_SP804 is not set +# CONFIG_ATMEL_PIT is not set +# CONFIG_SH_TIMER_CMT is not set +# CONFIG_SH_TIMER_MTU2 is not set +# CONFIG_SH_TIMER_TMU is not set +# CONFIG_EM_TIMER_STI is not set +# CONFIG_MAILBOX is not set +# CONFIG_IOMMU_SUPPORT is not set + +# +# Remoteproc drivers +# +# CONFIG_STE_MODEM_RPROC is not set + +# +# Rpmsg drivers +# + +# +# SOC (System On Chip) specific Drivers +# + +# +# Broadcom SoC drivers +# +# CONFIG_SOC_BRCMSTB is not set +# CONFIG_SUNXI_SRAM is not set +# CONFIG_SOC_TI is not set +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +CONFIG_PWM=y +# CONFIG_PWM_SYSFS is not set +# CONFIG_DEBUG_PWM_FS is not set +CONFIG_PWM_FULLHAN=y +CONFIG_FH_PWM_NUM=2 +# CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_PCA9685 is not set +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC_MAX_NR=1 +CONFIG_FULLHAN_INTC=y +# CONFIG_IPACK_BUS is not set +# CONFIG_RESET_CONTROLLER is not set +# CONFIG_FMC is not set + +# +# PHY Subsystem +# +# CONFIG_GENERIC_PHY is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_FH_USB2_PHY is not set +# CONFIG_PHY_SAMSUNG_USB2 is not set +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +# CONFIG_RAS is not set + +# +# Android +# +# CONFIG_ANDROID is not set +# CONFIG_NVMEM is not set +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set + +# +# FPGA Configuration Support +# +# CONFIG_FPGA is not set + +# +# Firmware Drivers +# +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_FW_CFG_SYSFS is not set + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_FILE_LOCKING=y +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +# CONFIG_OVERLAY_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_PROC_CHILDREN is not set +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_WRITEBUFFER is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V2 is not set +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_SWAP is not set +# CONFIG_ROOT_NFS is not set +# CONFIG_NFSD is not set +CONFIG_GRACE_PERIOD=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_DYNAMIC_DEBUG is not set + +# +# Compile-time checks and compiler options +# +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_OPTIMIZE_INLINING=y +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_DEBUG_KERNEL is not set + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_MEMORY_INIT is not set + +# +# Debug Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_SCHED_INFO is not set +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +# CONFIG_STACKTRACE is not set + +# +# RCU Debugging +# +# CONFIG_PROVE_RCU is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_TORTURE_TEST is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_HWLAT_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_FTRACE_SYSCALLS is not set +# CONFIG_TRACER_SNAPSHOT is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_PROBE_EVENTS is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +CONFIG_TRACING_EVENTS_GPIO=y + +# +# Runtime Testing +# +# CONFIG_LKDTM is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_HASH is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_MEMTEST is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set +# CONFIG_UBSAN is not set +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +# CONFIG_STRICT_DEVMEM is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_UART_8250 is not set +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_DEBUG_SET_MODULE_RONX is not set +# CONFIG_CORESIGHT is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_BIG_KEYS is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEY_DH_OPERATIONS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y +# CONFIG_HARDENED_USERCOPY is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_KPP2=y +# CONFIG_CRYPTO_RSA is not set +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_ECDH is not set +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_MCRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_KEYWRAP is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_CMAC is not set +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +CONFIG_CRYPTO_MICHAEL_MIC=y +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +CONFIG_CRYPTO_SHA256=y +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG is not set +# CONFIG_CRYPTO_JITTERENTROPY is not set +CONFIG_CRYPTO_USER_API=y +# CONFIG_CRYPTO_USER_API_HASH is not set +CONFIG_CRYPTO_USER_API_SKCIPHER=y +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_DEV_FH_AES=y +# CONFIG_CRYPTO_FH_AES_SUPPORT_DIRECT_MEM is not set +# CONFIG_FH_AES_SELF_TEST is not set +# CONFIG_ASYMMETRIC_KEY_TYPE is not set + +# +# Certificates for signature checking +# +# CONFIG_ARM_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_HAVE_ARCH_BITREVERSE is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_XZ=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y +# CONFIG_CORDIC is not set +# CONFIG_DDR is not set +# CONFIG_IRQ_POLL is not set +CONFIG_LIBFDT=y +# CONFIG_SG_SPLIT is not set +# CONFIG_SG_POOL is not set +# CONFIG_ARCH_HAS_SG_CHAIN is not set +CONFIG_SBITMAP=y +# CONFIG_VIRTUALIZATION is not set diff --git a/arch/arm/configs/fh8852v210_defconfig b/arch/arm/configs/fh8852v210_defconfig new file mode 100644 index 00000000..9e8583c1 --- /dev/null +++ b/arch/arm/configs/fh8852v210_defconfig @@ -0,0 +1,2253 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 4.9.129 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y + +# +# General setup +# +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_TINY_KERNEL=y +CONFIG_NTP=y +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_LZMA is not set +CONFIG_KERNEL_XZ=y +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_NO_COMPRESS is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_FHANDLE is not set +CONFIG_USELIB=y +# CONFIG_AUDIT is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_IRQ_DOMAIN=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_GENERIC_CLOCKEVENTS=y + +# +# Timers subsystem +# +CONFIG_HZ_PERIODIC=y +# CONFIG_NO_HZ_IDLE is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set + +# +# RCU Subsystem +# +CONFIG_TINY_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +# CONFIG_TASKS_RCU is not set +# CONFIG_RCU_STALL_COMMON is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_EXPEDITE_BOOT is not set +# CONFIG_BUILD_BIN2C is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_NMI_LOG_BUF_SHIFT=13 +CONFIG_GENERIC_SCHED_CLOCK=y +# CONFIG_CGROUPS is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SCHED_DL is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="usr/rootfs.cpio.xz" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +CONFIG_RD_XZ=y +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_HAVE_UID16=y +CONFIG_BPF=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +CONFIG_SYSFS_SYSCALL=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set +CONFIG_KALLSYMS_BASE_RELATIVE=y +CONFIG_PRINTK=y +CONFIG_PRINTK_NMI=y +# CONFIG_BUG is not set +# CONFIG_ELF_CORE is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +# CONFIG_BPF_SYSCALL is not set +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_ADVISE_SYSCALLS=y +# CONFIG_USERFAULTFD is not set +CONFIG_MEMBARRIER=y +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SYSTEM_DATA_VERIFICATION is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_UPROBES is not set +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_GCC_PLUGINS=y +# CONFIG_GCC_PLUGINS is not set +CONFIG_HAVE_CC_STACKPROTECTOR=y +# CONFIG_CC_STACKPROTECTOR is not set +CONFIG_CC_STACKPROTECTOR_NONE=y +# CONFIG_CC_STACKPROTECTOR_REGULAR is not set +# CONFIG_CC_STACKPROTECTOR_STRONG is not set +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_EXIT_THREAD=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=8 +CONFIG_ARCH_MMAP_RND_BITS_MAX=16 +CONFIG_ARCH_MMAP_RND_BITS=8 +# CONFIG_HAVE_ARCH_HASH is not set +# CONFIG_ISA_BUS_API is not set +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OLD_SIGACTION=y +# CONFIG_CPU_NO_EFFICIENT_FFS is not set +# CONFIG_HAVE_ARCH_VMAP_STACK is not set + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_CMDLINE_PARSER is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_EFI_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_MULTIPLATFORM is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +CONFIG_ARCH_FULLHAN=y +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP1 is not set + +# +# Fullhan platform type +# +# CONFIG_FH_FASTBOOT is not set +# CONFIG_ARCH_FH8833 is not set +# CONFIG_ARCH_FH8856 is not set +# CONFIG_ARCH_FH8852 is not set +# CONFIG_ARCH_FH8626V100 is not set +CONFIG_ARCH_FH885xV200=y +# CONFIG_ARCH_FH865x is not set + +CONFIG_FH_CHIP_NAME="fh8852v210" +# CONFIG_MACH_FH8856V200 is not set +CONFIG_MACH_FH8852V210=y +# CONFIG_MACH_FH8858V200 is not set + +# +# Processor Type +# +CONFIG_CPU_V6=y +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_KUSER_HELPERS=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +# CONFIG_DEBUG_RODATA is not set +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_PJ4B_ERRATA_4742=y +# CONFIG_ARM_ERRATA_326103 is not set +CONFIG_ARM_ERRATA_411920=y +# CONFIG_ARM_ERRATA_364296 is not set + +# +# Bus support +# +# CONFIG_PCI_DOMAINS_GENERIC is not set +# CONFIG_PCI_SYSCALL is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_3G_OPT is not set +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_ARCH_NR_GPIO=0 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ_FIXED=0 +CONFIG_HZ_100=y +# CONFIG_HZ_200 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_500 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +# CONFIG_SCHED_HRTICK is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +# CONFIG_HIGHMEM is not set +CONFIG_CPU_SW_DOMAIN_PAN=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +# CONFIG_ARM_MODULE_PLTS is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_NO_BOOTMEM=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_CLEANCACHE is not set +# CONFIG_CMA is not set +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +# CONFIG_ZSMALLOC is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +CONFIG_SWIOTLB=y +CONFIG_IOMMU_HELPER=y +# CONFIG_PARAVIRT is not set +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set + +# +# Boot options +# +# CONFIG_USE_OF is not set +CONFIG_ATAGS=y +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_AUTO_ZRELADDR=y + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# CPU Idle +# +# CONFIG_CPU_IDLE is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ELFCORE=y +CONFIG_BINFMT_SCRIPT=y +# CONFIG_BINFMT_FLAT is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y + +# +# Power management options +# +# CONFIG_SUSPEND is not set +# CONFIG_PM is not set +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_NET_IP_TUNNEL=y +# CONFIG_IP_MROUTE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_NET_IPVTI is not set +# CONFIG_NET_UDP_TUNNEL is not set +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_INET_DIAG_DESTROY is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +# CONFIG_IPV6_VTI is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_FOU is not set +# CONFIG_IPV6_FOU_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NET_PTP_CLASSIFY is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +CONFIG_HAVE_NET_DSA=y +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_MPLS is not set +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_NET_NCSI is not set +# CONFIG_SOCK_CGROUP_DATA is not set +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +# CONFIG_BPF_JIT is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +# CONFIG_STREAM_PARSER is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=y +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +# CONFIG_CFG80211_DEFAULT_PS is not set +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_CFG80211_WEXT=y +CONFIG_LIB80211=y +CONFIG_LIB80211_CRYPT_WEP=y +CONFIG_LIB80211_CRYPT_CCMP=y +CONFIG_LIB80211_CRYPT_TKIP=y +# CONFIG_LIB80211_DEBUG is not set +# CONFIG_MAC80211 is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +# CONFIG_RFKILL_INPUT is not set +# CONFIG_RFKILL_GPIO is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_LWTUNNEL is not set +CONFIG_DST_CACHE=y +# CONFIG_NET_DEVLINK is not set +CONFIG_MAY_USE_DEVLINK=y +CONFIG_HAVE_CBPF_JIT=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +# CONFIG_DMA_SHARED_BUFFER is not set + +# +# Bus devices +# +# CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR & LPDDR2 PCM memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_LPDDR2_NVM is not set +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_MT81xx_NOR is not set +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MTD_UBI is not set +# CONFIG_OF is not set +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_NVME_TARGET is not set + +# +# Misc devices +# +# CONFIG_FH_DW_I2S is not set +# CONFIG_FH_ACW is not set +CONFIG_FH_SADC_V3=y +CONFIG_FH_EFUSE=y +# CONFIG_FH_L2MEM is not set +CONFIG_FH_PINCTRL_MISC_DEV=y +CONFIG_FH_CLK_MISC=y +CONFIG_FH_PERF_MON=y +# CONFIG_FH_TSENSOR is not set +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_SRAM is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set + +# +# Intel MIC Bus Driver +# + +# +# SCIF Bus Driver +# + +# +# VOP Bus Driver +# + +# +# Intel MIC Host Driver +# + +# +# Intel MIC Card Driver +# + +# +# SCIF Driver +# + +# +# Intel MIC Coprocessor State Management (COSM) Drivers +# + +# +# VOP Driver +# +# CONFIG_ECHO is not set +# CONFIG_CXL_BASE is not set +# CONFIG_CXL_AFU_DRIVER_OPS is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_MACSEC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_TUN is not set +# CONFIG_TUN_VNET_CROSS_LE is not set +# CONFIG_VETH is not set +# CONFIG_NLMON is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +CONFIG_ETHERNET=y +# CONFIG_ALTERA_TSE is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_NET_VENDOR_FULLHAN=y +CONFIG_FH_GMAC=y +CONFIG_FH_GMAC_DA=y +CONFIG_PHYLIB=y +CONFIG_SWPHY=y + +# +# MDIO bus device drivers +# +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_BITBANG is not set + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_AT803X_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +CONFIG_FIXED_PHY=y +# CONFIG_ICPLUS_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +CONFIG_USB_NET_DRIVERS=y +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_RTL8152 is not set +# CONFIG_USB_LAN78XX is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_IPHETH is not set +CONFIG_WLAN=y +CONFIG_WLAN_VENDOR_ADMTEK=y +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +# CONFIG_ATH6KL is not set +CONFIG_WLAN_VENDOR_ATMEL=y +CONFIG_WLAN_VENDOR_BROADCOM=y +# CONFIG_BRCMFMAC is not set +CONFIG_WLAN_VENDOR_CISCO=y +CONFIG_WLAN_VENDOR_INTEL=y +CONFIG_WLAN_VENDOR_INTERSIL=y +CONFIG_HOSTAP=y +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +CONFIG_WLAN_VENDOR_MARVELL=y +# CONFIG_LIBERTAS is not set +# CONFIG_MWIFIEX is not set +CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_WLAN_VENDOR_REALTEK=y +CONFIG_WLAN_VENDOR_RSI=y +CONFIG_WLAN_VENDOR_ST=y +CONFIG_WLAN_VENDOR_TI=y +CONFIG_WLAN_VENDOR_ZYDAS=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_ISDN is not set +# CONFIG_NVM is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVMEM=y +# CONFIG_DEVKMEM is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set +CONFIG_SERIAL_FULLHAN=y +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_ST_ASC is not set +# CONFIG_SERIAL_STM32 is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_SMBUS is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_FH_INTERRUPT=y +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_EMEV2 is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_DESIGNWARE is not set +CONFIG_SPI_FH=y +# CONFIG_SPI_FH_SLAVE is not set + +# +# spi multi wire support +# +CONFIG_SPI_USE_MULTI_WIRE=y +CONFIG_SPI_SWAP_MAX_DATA_WIDTH=16 +# CONFIG_SPI_USE_DMA is not set +CONFIG_SPI_TINY_MEM=y +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +# CONFIG_PTP_1588_CLOCK is not set + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers +# +CONFIG_GPIO_FH=y +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_MPC8XXX is not set +# CONFIG_GPIO_ZX is not set + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_TPIC2810 is not set +# CONFIG_GPIO_TS4900 is not set + +# +# MFD GPIO expanders +# +# CONFIG_HTC_EGPIO is not set + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set + +# +# SPI or I2C GPIO expanders +# + +# +# USB GPIO expanders +# +# CONFIG_W1 is not set +# CONFIG_POWER_AVS is not set +# CONFIG_POWER_RESET is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_CORE is not set +# CONFIG_WATCHDOG_NOWAYOUT is not set +# CONFIG_WATCHDOG_SYSFS is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_FH_WATCHDOG=y +# CONFIG_MEN_A21_WDT is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set + +# +# Watchdog Pretimeout Governors +# +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_EXYNOS_LPASS is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_INTEL_SOC_PMIC is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_PM8921_CORE is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RTSX_USB is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set +# CONFIG_SOUND is not set + +# +# HID support +# +# CONFIG_HID is not set + +# +# USB HID support +# +# CONFIG_USB_HID is not set +# CONFIG_HID_PID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +CONFIG_USB_DYNAMIC_MINORS=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +CONFIG_USB_WUSB_CBAF=y +# CONFIG_USB_WUSB_CBAF_DEBUG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_MAX3421_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +CONFIG_USB_WDM=y +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_DWC3 is not set +CONFIG_USB_DWC2=y +CONFIG_USB_DWC2_HOST=y + +# +# Gadget/Dual-role mode requires USB Gadget support to be enabled +# +# CONFIG_USB_DWC2_VBVALIDOVEN is not set +# CONFIG_USB_DWC2_DEBUG is not set +# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set +# CONFIG_USB_DWC2_HOST_DMA_DESC_NUM_DYNAMIC is not set +CONFIG_USB_DWC2_DMA=y +# CONFIG_USB_DWC2_DMA_DESC is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set + +# +# USB Physical Layer drivers +# +# CONFIG_USB_PHY is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ULPI is not set +# CONFIG_USB_GADGET is not set +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_UWB is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SPI is not set +CONFIG_MMC_FH=y +CONFIG_MMC_FH_IDMAC=y +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_MTK is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +# CONFIG_EDAC is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV8803 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6916 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RX6110 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_MCP795 is not set +# CONFIG_RTC_I2C_AND_SPI is not set + +# +# SPI and I2C RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_FH=y +CONFIG_USE_TSENSOR=y +# CONFIG_USE_TSENSOR_OFFSET is not set + +# +# HID Sensor RTC drivers +# +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +# CONFIG_DW_DMAC is not set +CONFIG_CHANNEL_ALLOC_MEM_CLASSICS=y +# CONFIG_FH_DMAC is not set +CONFIG_FH_AXI_DMAC=y +CONFIG_FH_DMAC_MISC=y + +# +# dma tinyconfig +# +CONFIG_CHANNEL_ALLOC_DESC_NUM=32 +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_NBPFAXI_DMA is not set +# CONFIG_QCOM_HIDMA_MGMT is not set +# CONFIG_QCOM_HIDMA is not set + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set + +# +# DMABUF options +# +# CONFIG_SYNC_FILE is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VIRT_DRIVERS is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_STAGING is not set +# CONFIG_GOLDFISH is not set +# CONFIG_CHROME_PLATFORMS is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_COMMON_CLK_NXP is not set +# CONFIG_COMMON_CLK_PWM is not set +# CONFIG_COMMON_CLK_PXA is not set +# CONFIG_COMMON_CLK_PIC32 is not set + +# +# Hardware Spinlock drivers +# + +# +# Clock Source drivers +# +CONFIG_FULLHAN_TIMER=y +# CONFIG_FH_SIMPLE_TIMER is not set +# CONFIG_ARM_TIMER_SP804 is not set +# CONFIG_ATMEL_PIT is not set +# CONFIG_SH_TIMER_CMT is not set +# CONFIG_SH_TIMER_MTU2 is not set +# CONFIG_SH_TIMER_TMU is not set +# CONFIG_EM_TIMER_STI is not set +# CONFIG_MAILBOX is not set +# CONFIG_IOMMU_SUPPORT is not set + +# +# Remoteproc drivers +# +# CONFIG_STE_MODEM_RPROC is not set + +# +# Rpmsg drivers +# + +# +# SOC (System On Chip) specific Drivers +# + +# +# Broadcom SoC drivers +# +# CONFIG_SOC_BRCMSTB is not set +# CONFIG_SUNXI_SRAM is not set +# CONFIG_SOC_TI is not set +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +CONFIG_PWM=y +# CONFIG_PWM_SYSFS is not set +# CONFIG_DEBUG_PWM_FS is not set +CONFIG_PWM_FULLHAN=y +CONFIG_FH_PWM_NUM=14 +# CONFIG_PWM_PCA9685 is not set +CONFIG_ARM_GIC_MAX_NR=1 +CONFIG_FULLHAN_INTC=y +# CONFIG_IPACK_BUS is not set +# CONFIG_RESET_CONTROLLER is not set +# CONFIG_FMC is not set + +# +# PHY Subsystem +# +# CONFIG_GENERIC_PHY is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_FH_USB2_PHY is not set +# CONFIG_PHY_SAMSUNG_USB2 is not set +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +# CONFIG_RAS is not set + +# +# Android +# +# CONFIG_ANDROID is not set +# CONFIG_NVMEM is not set +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set + +# +# FPGA Configuration Support +# +# CONFIG_FPGA is not set + +# +# Firmware Drivers +# +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_FW_CFG_SYSFS is not set + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_FILE_LOCKING=y +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +# CONFIG_OVERLAY_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_PROC_CHILDREN is not set +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_WRITEBUFFER is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V2 is not set +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_SWAP is not set +# CONFIG_ROOT_NFS is not set +# CONFIG_NFSD is not set +CONFIG_GRACE_PERIOD=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_DYNAMIC_DEBUG is not set + +# +# Compile-time checks and compiler options +# +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_OPTIMIZE_INLINING=y +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_DEBUG_KERNEL is not set + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_MEMORY_INIT is not set + +# +# Debug Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_SCHED_INFO is not set +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +# CONFIG_STACKTRACE is not set + +# +# RCU Debugging +# +# CONFIG_PROVE_RCU is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_TORTURE_TEST is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_HWLAT_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_FTRACE_SYSCALLS is not set +# CONFIG_TRACER_SNAPSHOT is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_PROBE_EVENTS is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +CONFIG_TRACING_EVENTS_GPIO=y + +# +# Runtime Testing +# +# CONFIG_LKDTM is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_HASH is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_MEMTEST is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set +# CONFIG_UBSAN is not set +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +# CONFIG_STRICT_DEVMEM is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_UART_8250 is not set +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_DEBUG_SET_MODULE_RONX is not set +# CONFIG_CORESIGHT is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_BIG_KEYS is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEY_DH_OPERATIONS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y +# CONFIG_HARDENED_USERCOPY is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_KPP2=y +# CONFIG_CRYPTO_RSA is not set +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_ECDH is not set +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_MCRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_KEYWRAP is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_CMAC is not set +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +CONFIG_CRYPTO_MICHAEL_MIC=y +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +CONFIG_CRYPTO_SHA256=y +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG is not set +# CONFIG_CRYPTO_JITTERENTROPY is not set +CONFIG_CRYPTO_USER_API=y +# CONFIG_CRYPTO_USER_API_HASH is not set +CONFIG_CRYPTO_USER_API_SKCIPHER=y +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_FH_CESA is not set +CONFIG_CRYPTO_DEV_FH_AES=y +# CONFIG_CRYPTO_FH_AES_SUPPORT_DIRECT_MEM is not set +# CONFIG_FH_AES_SELF_TEST is not set +# CONFIG_ASYMMETRIC_KEY_TYPE is not set + +# +# Certificates for signature checking +# +# CONFIG_ARM_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_HAVE_ARCH_BITREVERSE is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_XZ=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y +# CONFIG_CORDIC is not set +# CONFIG_DDR is not set +# CONFIG_IRQ_POLL is not set +# CONFIG_SG_SPLIT is not set +# CONFIG_SG_POOL is not set +# CONFIG_ARCH_HAS_SG_CHAIN is not set +CONFIG_SBITMAP=y +# CONFIG_VIRTUALIZATION is not set diff --git a/arch/arm/configs/fh8852v210_of_defconfig b/arch/arm/configs/fh8852v210_of_defconfig new file mode 100644 index 00000000..f6a7346f --- /dev/null +++ b/arch/arm/configs/fh8852v210_of_defconfig @@ -0,0 +1,2332 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 4.9.129 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y + +# +# General setup +# +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_TINY_KERNEL=y +CONFIG_NTP=y +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_LZMA is not set +CONFIG_KERNEL_XZ=y +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_NO_COMPRESS is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_FHANDLE is not set +CONFIG_USELIB=y +# CONFIG_AUDIT is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_IRQ_DOMAIN=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_GENERIC_CLOCKEVENTS=y + +# +# Timers subsystem +# +CONFIG_HZ_PERIODIC=y +# CONFIG_NO_HZ_IDLE is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set + +# +# RCU Subsystem +# +CONFIG_TINY_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +# CONFIG_TASKS_RCU is not set +# CONFIG_RCU_STALL_COMMON is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_EXPEDITE_BOOT is not set +# CONFIG_BUILD_BIN2C is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_NMI_LOG_BUF_SHIFT=13 +CONFIG_GENERIC_SCHED_CLOCK=y +# CONFIG_CGROUPS is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SCHED_DL is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="usr/rootfs.cpio.xz" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +CONFIG_RD_XZ=y +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_HAVE_UID16=y +CONFIG_BPF=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +CONFIG_SYSFS_SYSCALL=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set +CONFIG_KALLSYMS_BASE_RELATIVE=y +CONFIG_PRINTK=y +CONFIG_PRINTK_NMI=y +# CONFIG_BUG is not set +# CONFIG_ELF_CORE is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +# CONFIG_BPF_SYSCALL is not set +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_ADVISE_SYSCALLS=y +# CONFIG_USERFAULTFD is not set +CONFIG_MEMBARRIER=y +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SYSTEM_DATA_VERIFICATION is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_UPROBES is not set +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_GCC_PLUGINS=y +# CONFIG_GCC_PLUGINS is not set +CONFIG_HAVE_CC_STACKPROTECTOR=y +# CONFIG_CC_STACKPROTECTOR is not set +CONFIG_CC_STACKPROTECTOR_NONE=y +# CONFIG_CC_STACKPROTECTOR_REGULAR is not set +# CONFIG_CC_STACKPROTECTOR_STRONG is not set +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_EXIT_THREAD=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=8 +CONFIG_ARCH_MMAP_RND_BITS_MAX=16 +CONFIG_ARCH_MMAP_RND_BITS=8 +# CONFIG_HAVE_ARCH_HASH is not set +# CONFIG_ISA_BUS_API is not set +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OLD_SIGACTION=y +# CONFIG_CPU_NO_EFFICIENT_FFS is not set +# CONFIG_HAVE_ARCH_VMAP_STACK is not set + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_CMDLINE_PARSER is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_EFI_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_MULTIPLATFORM is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +CONFIG_ARCH_FULLHAN=y +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP1 is not set + +# +# Fullhan platform type +# +# CONFIG_FH_FASTBOOT is not set +# CONFIG_ARCH_FH8833 is not set +# CONFIG_ARCH_FH8856 is not set +# CONFIG_ARCH_FH8626V100 is not set +CONFIG_ARCH_FH885xV200=y +# CONFIG_ARCH_FH865x is not set + +CONFIG_FH_CHIP_NAME="fh8852v210" +CONFIG_MACH_FH8852V210=y +# CONFIG_MACH_FH8856V200 is not set + +# +# Processor Type +# +CONFIG_CPU_V6=y +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_KUSER_HELPERS=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +# CONFIG_DEBUG_RODATA is not set +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_PJ4B_ERRATA_4742=y +# CONFIG_ARM_ERRATA_326103 is not set +CONFIG_ARM_ERRATA_411920=y +# CONFIG_ARM_ERRATA_364296 is not set + +# +# Bus support +# +# CONFIG_PCI_DOMAINS_GENERIC is not set +# CONFIG_PCI_SYSCALL is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_3G_OPT is not set +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_ARCH_NR_GPIO=0 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ_FIXED=0 +CONFIG_HZ_100=y +# CONFIG_HZ_200 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_500 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +# CONFIG_SCHED_HRTICK is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +# CONFIG_HIGHMEM is not set +CONFIG_CPU_SW_DOMAIN_PAN=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +# CONFIG_ARM_MODULE_PLTS is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_NO_BOOTMEM=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_CLEANCACHE is not set +# CONFIG_CMA is not set +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +# CONFIG_ZSMALLOC is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +CONFIG_SWIOTLB=y +CONFIG_IOMMU_HELPER=y +# CONFIG_PARAVIRT is not set +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set + +# +# Boot options +# +CONFIG_USE_OF=y +CONFIG_ATAGS=y +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND=y +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_AUTO_ZRELADDR=y +# CONFIG_EFI is not set + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# CPU Idle +# +# CONFIG_CPU_IDLE is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ELFCORE=y +CONFIG_BINFMT_SCRIPT=y +# CONFIG_BINFMT_FLAT is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y + +# +# Power management options +# +# CONFIG_SUSPEND is not set +# CONFIG_PM is not set +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_NET_IP_TUNNEL=y +# CONFIG_IP_MROUTE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_NET_IPVTI is not set +# CONFIG_NET_UDP_TUNNEL is not set +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_INET_DIAG_DESTROY is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +# CONFIG_IPV6_VTI is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_FOU is not set +# CONFIG_IPV6_FOU_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NET_PTP_CLASSIFY is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +CONFIG_HAVE_NET_DSA=y +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_MPLS is not set +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_NET_NCSI is not set +# CONFIG_SOCK_CGROUP_DATA is not set +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +# CONFIG_BPF_JIT is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +# CONFIG_STREAM_PARSER is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=y +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +# CONFIG_CFG80211_DEFAULT_PS is not set +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_CFG80211_WEXT=y +CONFIG_LIB80211=y +CONFIG_LIB80211_CRYPT_WEP=y +CONFIG_LIB80211_CRYPT_CCMP=y +CONFIG_LIB80211_CRYPT_TKIP=y +# CONFIG_LIB80211_DEBUG is not set +# CONFIG_MAC80211 is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +# CONFIG_RFKILL_INPUT is not set +# CONFIG_RFKILL_GPIO is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_LWTUNNEL is not set +CONFIG_DST_CACHE=y +# CONFIG_NET_DEVLINK is not set +CONFIG_MAY_USE_DEVLINK=y +CONFIG_HAVE_CBPF_JIT=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +# CONFIG_DMA_SHARED_BUFFER is not set + +# +# Bus devices +# +# CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_VEXPRESS_CONFIG is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR & LPDDR2 PCM memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_LPDDR2_NVM is not set +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_MT81xx_NOR is not set +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_MTD_UBI is not set +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_MDIO=y +CONFIG_OF_RESERVED_MEM=y +# CONFIG_OF_OVERLAY is not set +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_NVME_TARGET is not set + +# +# Misc devices +# +# CONFIG_FH_DW_I2S is not set +# CONFIG_FH_ACW is not set +CONFIG_FH_SADC_V3=y +CONFIG_FH_EFUSE=y +# CONFIG_FH_L2MEM is not set +CONFIG_FH_CLK_MISC=y +CONFIG_FH_PERF_MON=y +# CONFIG_FH_TSENSOR is not set +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_SRAM is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set + +# +# Intel MIC Bus Driver +# + +# +# SCIF Bus Driver +# + +# +# VOP Bus Driver +# + +# +# Intel MIC Host Driver +# + +# +# Intel MIC Card Driver +# + +# +# SCIF Driver +# + +# +# Intel MIC Coprocessor State Management (COSM) Drivers +# + +# +# VOP Driver +# +# CONFIG_ECHO is not set +# CONFIG_CXL_BASE is not set +# CONFIG_CXL_AFU_DRIVER_OPS is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_MACSEC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_TUN is not set +# CONFIG_TUN_VNET_CROSS_LE is not set +# CONFIG_VETH is not set +# CONFIG_NLMON is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +CONFIG_ETHERNET=y +# CONFIG_ALTERA_TSE is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_NET_VENDOR_FULLHAN=y +CONFIG_FH_GMAC=y +CONFIG_FH_GMAC_DA=y + +# +# fh inside or outside phy sel +# +CONFIG_PHYLIB=y +CONFIG_SWPHY=y + +# +# MDIO bus device drivers +# +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MDIO_HISI_FEMAC is not set + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_AT803X_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +CONFIG_FIXED_PHY=y +# CONFIG_ICPLUS_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +CONFIG_USB_NET_DRIVERS=y +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_RTL8152 is not set +# CONFIG_USB_LAN78XX is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_IPHETH is not set +CONFIG_WLAN=y +CONFIG_WLAN_VENDOR_ADMTEK=y +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +# CONFIG_ATH6KL is not set +CONFIG_WLAN_VENDOR_ATMEL=y +CONFIG_WLAN_VENDOR_BROADCOM=y +# CONFIG_BRCMFMAC is not set +CONFIG_WLAN_VENDOR_CISCO=y +CONFIG_WLAN_VENDOR_INTEL=y +CONFIG_WLAN_VENDOR_INTERSIL=y +CONFIG_HOSTAP=y +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +CONFIG_WLAN_VENDOR_MARVELL=y +# CONFIG_LIBERTAS is not set +# CONFIG_MWIFIEX is not set +CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_WLAN_VENDOR_REALTEK=y +CONFIG_WLAN_VENDOR_RSI=y +CONFIG_WLAN_VENDOR_ST=y +CONFIG_WLAN_VENDOR_TI=y +CONFIG_WLAN_VENDOR_ZYDAS=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_ISDN is not set +# CONFIG_NVM is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVMEM=y +# CONFIG_DEVKMEM is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set +CONFIG_SERIAL_FULLHAN=y +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +# CONFIG_SERIAL_ST_ASC is not set +# CONFIG_SERIAL_STM32 is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_XILLYBUS is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_SMBUS is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_FH_INTERRUPT=y +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_EMEV2 is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_RK3X is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_DESIGNWARE is not set +CONFIG_SPI_FH=y + +# +# spi multi wire support +# +CONFIG_SPI_USE_MULTI_WIRE=y +CONFIG_SPI_SWAP_MAX_DATA_WIDTH=16 +# CONFIG_SPI_USE_DMA is not set +CONFIG_SPI_TINY_MEM=y +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +# CONFIG_PTP_1588_CLOCK is not set + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_PINCTRL=y + +# +# Pin controllers +# +CONFIG_PINMUX=y +CONFIG_PINCTRL_FULLHAN=y +# CONFIG_PINCTRL_AMD is not set +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_GPIOLIB=y +CONFIG_OF_GPIO=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers +# +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ALTERA is not set +CONFIG_GPIO_FH=y +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_EM is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_MPC8XXX is not set +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_ZEVIO is not set +# CONFIG_GPIO_ZX is not set + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_TPIC2810 is not set +# CONFIG_GPIO_TS4900 is not set + +# +# MFD GPIO expanders +# +# CONFIG_HTC_EGPIO is not set + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set + +# +# SPI or I2C GPIO expanders +# +# CONFIG_GPIO_MCP23S08 is not set + +# +# USB GPIO expanders +# +# CONFIG_W1 is not set +# CONFIG_POWER_AVS is not set +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_BRCMKONA is not set +# CONFIG_POWER_RESET_GPIO is not set +# CONFIG_POWER_RESET_GPIO_RESTART is not set +CONFIG_POWER_RESET_FH=y +# CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_RESTART is not set +# CONFIG_POWER_RESET_SYSCON is not set +# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_CORE is not set +# CONFIG_WATCHDOG_NOWAYOUT is not set +# CONFIG_WATCHDOG_SYSFS is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_GPIO_WATCHDOG is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_FH_WATCHDOG=y +# CONFIG_MEN_A21_WDT is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set + +# +# Watchdog Pretimeout Governors +# +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_ACT8945A is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_EXYNOS_LPASS is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_INTEL_SOC_PMIC is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77620 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_PM8921_CORE is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RTSX_USB is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RK808 is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set +# CONFIG_SOUND is not set + +# +# HID support +# +# CONFIG_HID is not set + +# +# USB HID support +# +# CONFIG_USB_HID is not set +# CONFIG_HID_PID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +CONFIG_USB_DYNAMIC_MINORS=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +CONFIG_USB_WUSB_CBAF=y +# CONFIG_USB_WUSB_CBAF_DEBUG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_MAX3421_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +CONFIG_USB_WDM=y +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_DWC3 is not set +CONFIG_USB_DWC2=y +CONFIG_USB_DWC2_HOST=y + +# +# Gadget/Dual-role mode requires USB Gadget support to be enabled +# +# CONFIG_USB_DWC2_VBVALIDOVEN is not set +# CONFIG_USB_DWC2_DEBUG is not set +# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set +# CONFIG_USB_DWC2_HOST_DMA_DESC_NUM_DYNAMIC is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set + +# +# USB Physical Layer drivers +# +# CONFIG_USB_PHY is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ULPI is not set +# CONFIG_USB_GADGET is not set +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_UWB is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_PWRSEQ_EMMC=y +CONFIG_PWRSEQ_SIMPLE=y + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SPI is not set +CONFIG_MMC_FH=y +CONFIG_MMC_FH_IDMAC=y +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_MTK is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +# CONFIG_EDAC is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_HYM8563 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV8803 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6916 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RX6110 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_MCP795 is not set +# CONFIG_RTC_I2C_AND_SPI is not set + +# +# SPI and I2C RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_ZYNQMP is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_SNVS is not set +CONFIG_RTC_DRV_FH=y +CONFIG_USE_TSENSOR=y +# CONFIG_USE_TSENSOR_OFFSET is not set + +# +# HID Sensor RTC drivers +# +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +# CONFIG_DW_DMAC is not set +# CONFIG_FH_DMAC is not set +CONFIG_FH_AXI_DMAC=y +CONFIG_FH_DMAC_MISC=y + +# +# dma tinyconfig +# +CONFIG_CHANNEL_ALLOC_MEM_CLASSICS=y +CONFIG_CHANNEL_ALLOC_DESC_NUM=32 +# CONFIG_FSL_EDMA is not set +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_NBPFAXI_DMA is not set +# CONFIG_QCOM_HIDMA_MGMT is not set +# CONFIG_QCOM_HIDMA is not set + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set + +# +# DMABUF options +# +# CONFIG_SYNC_FILE is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VIRT_DRIVERS is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_STAGING is not set +# CONFIG_GOLDFISH is not set +# CONFIG_CHROME_PLATFORMS is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI514 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CDCE925 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_CLK_QORIQ is not set +# CONFIG_COMMON_CLK_NXP is not set +# CONFIG_COMMON_CLK_PWM is not set +# CONFIG_COMMON_CLK_PXA is not set +# CONFIG_COMMON_CLK_PIC32 is not set + +# +# Hardware Spinlock drivers +# + +# +# Clock Source drivers +# +CONFIG_CLKSRC_OF=y +CONFIG_CLKSRC_PROBE=y +CONFIG_FULLHAN_TIMER=y +# CONFIG_FH_SIMPLE_TIMER is not set +# CONFIG_ARM_TIMER_SP804 is not set +# CONFIG_ATMEL_PIT is not set +# CONFIG_SH_TIMER_CMT is not set +# CONFIG_SH_TIMER_MTU2 is not set +# CONFIG_SH_TIMER_TMU is not set +# CONFIG_EM_TIMER_STI is not set +# CONFIG_MAILBOX is not set +# CONFIG_IOMMU_SUPPORT is not set + +# +# Remoteproc drivers +# +# CONFIG_STE_MODEM_RPROC is not set + +# +# Rpmsg drivers +# + +# +# SOC (System On Chip) specific Drivers +# + +# +# Broadcom SoC drivers +# +# CONFIG_SOC_BRCMSTB is not set +# CONFIG_SUNXI_SRAM is not set +# CONFIG_SOC_TI is not set +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +CONFIG_PWM=y +# CONFIG_PWM_SYSFS is not set +# CONFIG_DEBUG_PWM_FS is not set +CONFIG_PWM_FULLHAN=y +CONFIG_FH_PWM_NUM=2 +# CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_PCA9685 is not set +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC_MAX_NR=1 +CONFIG_FULLHAN_INTC=y +# CONFIG_IPACK_BUS is not set +# CONFIG_RESET_CONTROLLER is not set +# CONFIG_FMC is not set + +# +# PHY Subsystem +# +# CONFIG_GENERIC_PHY is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_FH_USB2_PHY is not set +# CONFIG_PHY_SAMSUNG_USB2 is not set +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +# CONFIG_RAS is not set + +# +# Android +# +# CONFIG_ANDROID is not set +# CONFIG_NVMEM is not set +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set + +# +# FPGA Configuration Support +# +# CONFIG_FPGA is not set + +# +# Firmware Drivers +# +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_FW_CFG_SYSFS is not set + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_FILE_LOCKING=y +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +# CONFIG_OVERLAY_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_PROC_CHILDREN is not set +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_WRITEBUFFER is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V2 is not set +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_SWAP is not set +# CONFIG_ROOT_NFS is not set +# CONFIG_NFSD is not set +CONFIG_GRACE_PERIOD=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_DYNAMIC_DEBUG is not set + +# +# Compile-time checks and compiler options +# +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_OPTIMIZE_INLINING=y +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_DEBUG_KERNEL is not set + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_MEMORY_INIT is not set + +# +# Debug Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_SCHED_INFO is not set +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +# CONFIG_STACKTRACE is not set + +# +# RCU Debugging +# +# CONFIG_PROVE_RCU is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_TORTURE_TEST is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_HWLAT_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_FTRACE_SYSCALLS is not set +# CONFIG_TRACER_SNAPSHOT is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_PROBE_EVENTS is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +CONFIG_TRACING_EVENTS_GPIO=y + +# +# Runtime Testing +# +# CONFIG_LKDTM is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_HASH is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_MEMTEST is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set +# CONFIG_UBSAN is not set +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +# CONFIG_STRICT_DEVMEM is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_UART_8250 is not set +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_DEBUG_SET_MODULE_RONX is not set +# CONFIG_CORESIGHT is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_BIG_KEYS is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEY_DH_OPERATIONS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y +# CONFIG_HARDENED_USERCOPY is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_KPP2=y +# CONFIG_CRYPTO_RSA is not set +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_ECDH is not set +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_MCRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_KEYWRAP is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_CMAC is not set +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +CONFIG_CRYPTO_MICHAEL_MIC=y +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +CONFIG_CRYPTO_SHA256=y +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG is not set +# CONFIG_CRYPTO_JITTERENTROPY is not set +CONFIG_CRYPTO_USER_API=y +# CONFIG_CRYPTO_USER_API_HASH is not set +CONFIG_CRYPTO_USER_API_SKCIPHER=y +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_DEV_FH_AES=y +# CONFIG_CRYPTO_FH_AES_SUPPORT_DIRECT_MEM is not set +# CONFIG_FH_AES_SELF_TEST is not set +# CONFIG_ASYMMETRIC_KEY_TYPE is not set + +# +# Certificates for signature checking +# +# CONFIG_ARM_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_HAVE_ARCH_BITREVERSE is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_XZ=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y +# CONFIG_CORDIC is not set +# CONFIG_DDR is not set +# CONFIG_IRQ_POLL is not set +CONFIG_LIBFDT=y +# CONFIG_SG_SPLIT is not set +# CONFIG_SG_POOL is not set +# CONFIG_ARCH_HAS_SG_CHAIN is not set +CONFIG_SBITMAP=y +# CONFIG_VIRTUALIZATION is not set diff --git a/arch/arm/configs/fh8856v200_defconfig b/arch/arm/configs/fh8856v200_defconfig new file mode 100644 index 00000000..e9c4bb47 --- /dev/null +++ b/arch/arm/configs/fh8856v200_defconfig @@ -0,0 +1,2253 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 4.9.129 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y + +# +# General setup +# +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_TINY_KERNEL=y +CONFIG_NTP=y +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_LZMA is not set +CONFIG_KERNEL_XZ=y +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_NO_COMPRESS is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_FHANDLE is not set +CONFIG_USELIB=y +# CONFIG_AUDIT is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_IRQ_DOMAIN=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_GENERIC_CLOCKEVENTS=y + +# +# Timers subsystem +# +CONFIG_HZ_PERIODIC=y +# CONFIG_NO_HZ_IDLE is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set + +# +# RCU Subsystem +# +CONFIG_TINY_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +# CONFIG_TASKS_RCU is not set +# CONFIG_RCU_STALL_COMMON is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_EXPEDITE_BOOT is not set +# CONFIG_BUILD_BIN2C is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_NMI_LOG_BUF_SHIFT=13 +CONFIG_GENERIC_SCHED_CLOCK=y +# CONFIG_CGROUPS is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SCHED_DL is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="usr/rootfs.cpio.xz" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +CONFIG_RD_XZ=y +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_HAVE_UID16=y +CONFIG_BPF=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +CONFIG_SYSFS_SYSCALL=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set +CONFIG_KALLSYMS_BASE_RELATIVE=y +CONFIG_PRINTK=y +CONFIG_PRINTK_NMI=y +# CONFIG_BUG is not set +# CONFIG_ELF_CORE is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +# CONFIG_BPF_SYSCALL is not set +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_ADVISE_SYSCALLS=y +# CONFIG_USERFAULTFD is not set +CONFIG_MEMBARRIER=y +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SYSTEM_DATA_VERIFICATION is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_UPROBES is not set +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_GCC_PLUGINS=y +# CONFIG_GCC_PLUGINS is not set +CONFIG_HAVE_CC_STACKPROTECTOR=y +# CONFIG_CC_STACKPROTECTOR is not set +CONFIG_CC_STACKPROTECTOR_NONE=y +# CONFIG_CC_STACKPROTECTOR_REGULAR is not set +# CONFIG_CC_STACKPROTECTOR_STRONG is not set +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_EXIT_THREAD=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=8 +CONFIG_ARCH_MMAP_RND_BITS_MAX=16 +CONFIG_ARCH_MMAP_RND_BITS=8 +# CONFIG_HAVE_ARCH_HASH is not set +# CONFIG_ISA_BUS_API is not set +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OLD_SIGACTION=y +# CONFIG_CPU_NO_EFFICIENT_FFS is not set +# CONFIG_HAVE_ARCH_VMAP_STACK is not set + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_CMDLINE_PARSER is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_EFI_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_MULTIPLATFORM is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +CONFIG_ARCH_FULLHAN=y +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP1 is not set + +# +# Fullhan platform type +# +# CONFIG_FH_FASTBOOT is not set +# CONFIG_ARCH_FH8833 is not set +# CONFIG_ARCH_FH8856 is not set +# CONFIG_ARCH_FH8852 is not set +# CONFIG_ARCH_FH8626V100 is not set +CONFIG_ARCH_FH885xV200=y +# CONFIG_ARCH_FH865x is not set + +CONFIG_FH_CHIP_NAME="fh8856v200" +CONFIG_MACH_FH8856V200=y +# CONFIG_MACH_FH8852V200 is not set +# CONFIG_MACH_FH8858V200 is not set + +# +# Processor Type +# +CONFIG_CPU_V6=y +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_KUSER_HELPERS=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +# CONFIG_DEBUG_RODATA is not set +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_PJ4B_ERRATA_4742=y +# CONFIG_ARM_ERRATA_326103 is not set +CONFIG_ARM_ERRATA_411920=y +# CONFIG_ARM_ERRATA_364296 is not set + +# +# Bus support +# +# CONFIG_PCI_DOMAINS_GENERIC is not set +# CONFIG_PCI_SYSCALL is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_3G_OPT is not set +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_ARCH_NR_GPIO=0 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ_FIXED=0 +CONFIG_HZ_100=y +# CONFIG_HZ_200 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_500 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +# CONFIG_SCHED_HRTICK is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +# CONFIG_HIGHMEM is not set +CONFIG_CPU_SW_DOMAIN_PAN=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +# CONFIG_ARM_MODULE_PLTS is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_NO_BOOTMEM=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_CLEANCACHE is not set +# CONFIG_CMA is not set +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +# CONFIG_ZSMALLOC is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +CONFIG_SWIOTLB=y +CONFIG_IOMMU_HELPER=y +# CONFIG_PARAVIRT is not set +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set + +# +# Boot options +# +# CONFIG_USE_OF is not set +CONFIG_ATAGS=y +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_AUTO_ZRELADDR=y + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# CPU Idle +# +# CONFIG_CPU_IDLE is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ELFCORE=y +CONFIG_BINFMT_SCRIPT=y +# CONFIG_BINFMT_FLAT is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y + +# +# Power management options +# +# CONFIG_SUSPEND is not set +# CONFIG_PM is not set +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_NET_IP_TUNNEL=y +# CONFIG_IP_MROUTE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_NET_IPVTI is not set +# CONFIG_NET_UDP_TUNNEL is not set +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_INET_DIAG_DESTROY is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +# CONFIG_IPV6_VTI is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_FOU is not set +# CONFIG_IPV6_FOU_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NET_PTP_CLASSIFY is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +CONFIG_HAVE_NET_DSA=y +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_MPLS is not set +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_NET_NCSI is not set +# CONFIG_SOCK_CGROUP_DATA is not set +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +# CONFIG_BPF_JIT is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +# CONFIG_STREAM_PARSER is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=y +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +# CONFIG_CFG80211_DEFAULT_PS is not set +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_CFG80211_WEXT=y +CONFIG_LIB80211=y +CONFIG_LIB80211_CRYPT_WEP=y +CONFIG_LIB80211_CRYPT_CCMP=y +CONFIG_LIB80211_CRYPT_TKIP=y +# CONFIG_LIB80211_DEBUG is not set +# CONFIG_MAC80211 is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +# CONFIG_RFKILL_INPUT is not set +# CONFIG_RFKILL_GPIO is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_LWTUNNEL is not set +CONFIG_DST_CACHE=y +# CONFIG_NET_DEVLINK is not set +CONFIG_MAY_USE_DEVLINK=y +CONFIG_HAVE_CBPF_JIT=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +# CONFIG_DMA_SHARED_BUFFER is not set + +# +# Bus devices +# +# CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR & LPDDR2 PCM memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_LPDDR2_NVM is not set +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_MT81xx_NOR is not set +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MTD_UBI is not set +# CONFIG_OF is not set +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_NVME_TARGET is not set + +# +# Misc devices +# +# CONFIG_FH_DW_I2S is not set +# CONFIG_FH_ACW is not set +CONFIG_FH_SADC_V3=y +CONFIG_FH_EFUSE=y +# CONFIG_FH_L2MEM is not set +CONFIG_FH_PINCTRL_MISC_DEV=y +CONFIG_FH_CLK_MISC=y +CONFIG_FH_PERF_MON=y +# CONFIG_FH_TSENSOR is not set +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_SRAM is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set + +# +# Intel MIC Bus Driver +# + +# +# SCIF Bus Driver +# + +# +# VOP Bus Driver +# + +# +# Intel MIC Host Driver +# + +# +# Intel MIC Card Driver +# + +# +# SCIF Driver +# + +# +# Intel MIC Coprocessor State Management (COSM) Drivers +# + +# +# VOP Driver +# +# CONFIG_ECHO is not set +# CONFIG_CXL_BASE is not set +# CONFIG_CXL_AFU_DRIVER_OPS is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_MACSEC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_TUN is not set +# CONFIG_TUN_VNET_CROSS_LE is not set +# CONFIG_VETH is not set +# CONFIG_NLMON is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +CONFIG_ETHERNET=y +# CONFIG_ALTERA_TSE is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_NET_VENDOR_FULLHAN=y +CONFIG_FH_GMAC=y +CONFIG_FH_GMAC_DA=y +CONFIG_PHYLIB=y +CONFIG_SWPHY=y + +# +# MDIO bus device drivers +# +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_BITBANG is not set + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_AT803X_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +CONFIG_FIXED_PHY=y +# CONFIG_ICPLUS_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +CONFIG_USB_NET_DRIVERS=y +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_RTL8152 is not set +# CONFIG_USB_LAN78XX is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_IPHETH is not set +CONFIG_WLAN=y +CONFIG_WLAN_VENDOR_ADMTEK=y +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +# CONFIG_ATH6KL is not set +CONFIG_WLAN_VENDOR_ATMEL=y +CONFIG_WLAN_VENDOR_BROADCOM=y +# CONFIG_BRCMFMAC is not set +CONFIG_WLAN_VENDOR_CISCO=y +CONFIG_WLAN_VENDOR_INTEL=y +CONFIG_WLAN_VENDOR_INTERSIL=y +CONFIG_HOSTAP=y +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +CONFIG_WLAN_VENDOR_MARVELL=y +# CONFIG_LIBERTAS is not set +# CONFIG_MWIFIEX is not set +CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_WLAN_VENDOR_REALTEK=y +CONFIG_WLAN_VENDOR_RSI=y +CONFIG_WLAN_VENDOR_ST=y +CONFIG_WLAN_VENDOR_TI=y +CONFIG_WLAN_VENDOR_ZYDAS=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_ISDN is not set +# CONFIG_NVM is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVMEM=y +# CONFIG_DEVKMEM is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set +CONFIG_SERIAL_FULLHAN=y +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_ST_ASC is not set +# CONFIG_SERIAL_STM32 is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_SMBUS is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_FH_INTERRUPT=y +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_EMEV2 is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_DESIGNWARE is not set +CONFIG_SPI_FH=y +# CONFIG_SPI_FH_SLAVE is not set + +# +# spi multi wire support +# +CONFIG_SPI_USE_MULTI_WIRE=y +CONFIG_SPI_SWAP_MAX_DATA_WIDTH=16 +# CONFIG_SPI_USE_DMA is not set +CONFIG_SPI_TINY_MEM=y +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +# CONFIG_PTP_1588_CLOCK is not set + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers +# +CONFIG_GPIO_FH=y +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_MPC8XXX is not set +# CONFIG_GPIO_ZX is not set + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_TPIC2810 is not set +# CONFIG_GPIO_TS4900 is not set + +# +# MFD GPIO expanders +# +# CONFIG_HTC_EGPIO is not set + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set + +# +# SPI or I2C GPIO expanders +# + +# +# USB GPIO expanders +# +# CONFIG_W1 is not set +# CONFIG_POWER_AVS is not set +# CONFIG_POWER_RESET is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_CORE is not set +# CONFIG_WATCHDOG_NOWAYOUT is not set +# CONFIG_WATCHDOG_SYSFS is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_FH_WATCHDOG=y +# CONFIG_MEN_A21_WDT is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set + +# +# Watchdog Pretimeout Governors +# +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_EXYNOS_LPASS is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_INTEL_SOC_PMIC is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_PM8921_CORE is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RTSX_USB is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set +# CONFIG_SOUND is not set + +# +# HID support +# +# CONFIG_HID is not set + +# +# USB HID support +# +# CONFIG_USB_HID is not set +# CONFIG_HID_PID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +CONFIG_USB_DYNAMIC_MINORS=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +CONFIG_USB_WUSB_CBAF=y +# CONFIG_USB_WUSB_CBAF_DEBUG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_MAX3421_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +CONFIG_USB_WDM=y +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_DWC3 is not set +CONFIG_USB_DWC2=y +CONFIG_USB_DWC2_HOST=y + +# +# Gadget/Dual-role mode requires USB Gadget support to be enabled +# +# CONFIG_USB_DWC2_VBVALIDOVEN is not set +# CONFIG_USB_DWC2_DEBUG is not set +# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set +# CONFIG_USB_DWC2_HOST_DMA_DESC_NUM_DYNAMIC is not set +CONFIG_USB_DWC2_DMA=y +# CONFIG_USB_DWC2_DMA_DESC is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set + +# +# USB Physical Layer drivers +# +# CONFIG_USB_PHY is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ULPI is not set +# CONFIG_USB_GADGET is not set +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_UWB is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SPI is not set +CONFIG_MMC_FH=y +CONFIG_MMC_FH_IDMAC=y +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_MTK is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +# CONFIG_EDAC is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV8803 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6916 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RX6110 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_MCP795 is not set +# CONFIG_RTC_I2C_AND_SPI is not set + +# +# SPI and I2C RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_FH=y +CONFIG_USE_TSENSOR=y +# CONFIG_USE_TSENSOR_OFFSET is not set + +# +# HID Sensor RTC drivers +# +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +# CONFIG_DW_DMAC is not set +CONFIG_CHANNEL_ALLOC_MEM_CLASSICS=y +# CONFIG_FH_DMAC is not set +CONFIG_FH_AXI_DMAC=y +CONFIG_FH_DMAC_MISC=y + +# +# dma tinyconfig +# +CONFIG_CHANNEL_ALLOC_DESC_NUM=32 +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_NBPFAXI_DMA is not set +# CONFIG_QCOM_HIDMA_MGMT is not set +# CONFIG_QCOM_HIDMA is not set + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set + +# +# DMABUF options +# +# CONFIG_SYNC_FILE is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VIRT_DRIVERS is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_STAGING is not set +# CONFIG_GOLDFISH is not set +# CONFIG_CHROME_PLATFORMS is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_COMMON_CLK_NXP is not set +# CONFIG_COMMON_CLK_PWM is not set +# CONFIG_COMMON_CLK_PXA is not set +# CONFIG_COMMON_CLK_PIC32 is not set + +# +# Hardware Spinlock drivers +# + +# +# Clock Source drivers +# +CONFIG_FULLHAN_TIMER=y +# CONFIG_FH_SIMPLE_TIMER is not set +# CONFIG_ARM_TIMER_SP804 is not set +# CONFIG_ATMEL_PIT is not set +# CONFIG_SH_TIMER_CMT is not set +# CONFIG_SH_TIMER_MTU2 is not set +# CONFIG_SH_TIMER_TMU is not set +# CONFIG_EM_TIMER_STI is not set +# CONFIG_MAILBOX is not set +# CONFIG_IOMMU_SUPPORT is not set + +# +# Remoteproc drivers +# +# CONFIG_STE_MODEM_RPROC is not set + +# +# Rpmsg drivers +# + +# +# SOC (System On Chip) specific Drivers +# + +# +# Broadcom SoC drivers +# +# CONFIG_SOC_BRCMSTB is not set +# CONFIG_SUNXI_SRAM is not set +# CONFIG_SOC_TI is not set +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +CONFIG_PWM=y +# CONFIG_PWM_SYSFS is not set +# CONFIG_DEBUG_PWM_FS is not set +CONFIG_PWM_FULLHAN=y +CONFIG_FH_PWM_NUM=14 +# CONFIG_PWM_PCA9685 is not set +CONFIG_ARM_GIC_MAX_NR=1 +CONFIG_FULLHAN_INTC=y +# CONFIG_IPACK_BUS is not set +# CONFIG_RESET_CONTROLLER is not set +# CONFIG_FMC is not set + +# +# PHY Subsystem +# +# CONFIG_GENERIC_PHY is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_FH_USB2_PHY is not set +# CONFIG_PHY_SAMSUNG_USB2 is not set +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +# CONFIG_RAS is not set + +# +# Android +# +# CONFIG_ANDROID is not set +# CONFIG_NVMEM is not set +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set + +# +# FPGA Configuration Support +# +# CONFIG_FPGA is not set + +# +# Firmware Drivers +# +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_FW_CFG_SYSFS is not set + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_FILE_LOCKING=y +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +# CONFIG_OVERLAY_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_PROC_CHILDREN is not set +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_WRITEBUFFER is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V2 is not set +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_SWAP is not set +# CONFIG_ROOT_NFS is not set +# CONFIG_NFSD is not set +CONFIG_GRACE_PERIOD=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_DYNAMIC_DEBUG is not set + +# +# Compile-time checks and compiler options +# +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_OPTIMIZE_INLINING=y +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_DEBUG_KERNEL is not set + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_MEMORY_INIT is not set + +# +# Debug Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_SCHED_INFO is not set +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +# CONFIG_STACKTRACE is not set + +# +# RCU Debugging +# +# CONFIG_PROVE_RCU is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_TORTURE_TEST is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_HWLAT_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_FTRACE_SYSCALLS is not set +# CONFIG_TRACER_SNAPSHOT is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_PROBE_EVENTS is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +CONFIG_TRACING_EVENTS_GPIO=y + +# +# Runtime Testing +# +# CONFIG_LKDTM is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_HASH is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_MEMTEST is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set +# CONFIG_UBSAN is not set +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +# CONFIG_STRICT_DEVMEM is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_UART_8250 is not set +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_DEBUG_SET_MODULE_RONX is not set +# CONFIG_CORESIGHT is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_BIG_KEYS is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEY_DH_OPERATIONS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y +# CONFIG_HARDENED_USERCOPY is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_KPP2=y +# CONFIG_CRYPTO_RSA is not set +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_ECDH is not set +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_MCRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_KEYWRAP is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_CMAC is not set +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +CONFIG_CRYPTO_MICHAEL_MIC=y +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +CONFIG_CRYPTO_SHA256=y +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG is not set +# CONFIG_CRYPTO_JITTERENTROPY is not set +CONFIG_CRYPTO_USER_API=y +# CONFIG_CRYPTO_USER_API_HASH is not set +CONFIG_CRYPTO_USER_API_SKCIPHER=y +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_FH_CESA is not set +CONFIG_CRYPTO_DEV_FH_AES=y +# CONFIG_CRYPTO_FH_AES_SUPPORT_DIRECT_MEM is not set +# CONFIG_FH_AES_SELF_TEST is not set +# CONFIG_ASYMMETRIC_KEY_TYPE is not set + +# +# Certificates for signature checking +# +# CONFIG_ARM_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_HAVE_ARCH_BITREVERSE is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_XZ=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y +# CONFIG_CORDIC is not set +# CONFIG_DDR is not set +# CONFIG_IRQ_POLL is not set +# CONFIG_SG_SPLIT is not set +# CONFIG_SG_POOL is not set +# CONFIG_ARCH_HAS_SG_CHAIN is not set +CONFIG_SBITMAP=y +# CONFIG_VIRTUALIZATION is not set diff --git a/arch/arm/configs/fh8856v200_of_defconfig b/arch/arm/configs/fh8856v200_of_defconfig new file mode 100644 index 00000000..4a959402 --- /dev/null +++ b/arch/arm/configs/fh8856v200_of_defconfig @@ -0,0 +1,2332 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 4.9.129 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y + +# +# General setup +# +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_TINY_KERNEL=y +CONFIG_NTP=y +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_LZMA is not set +CONFIG_KERNEL_XZ=y +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_NO_COMPRESS is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_FHANDLE is not set +CONFIG_USELIB=y +# CONFIG_AUDIT is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_IRQ_DOMAIN=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_GENERIC_CLOCKEVENTS=y + +# +# Timers subsystem +# +CONFIG_HZ_PERIODIC=y +# CONFIG_NO_HZ_IDLE is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set + +# +# RCU Subsystem +# +CONFIG_TINY_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +# CONFIG_TASKS_RCU is not set +# CONFIG_RCU_STALL_COMMON is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_EXPEDITE_BOOT is not set +# CONFIG_BUILD_BIN2C is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_NMI_LOG_BUF_SHIFT=13 +CONFIG_GENERIC_SCHED_CLOCK=y +# CONFIG_CGROUPS is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SCHED_DL is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="usr/rootfs.cpio.xz" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +CONFIG_RD_XZ=y +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_HAVE_UID16=y +CONFIG_BPF=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +CONFIG_SYSFS_SYSCALL=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set +CONFIG_KALLSYMS_BASE_RELATIVE=y +CONFIG_PRINTK=y +CONFIG_PRINTK_NMI=y +# CONFIG_BUG is not set +# CONFIG_ELF_CORE is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +# CONFIG_BPF_SYSCALL is not set +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_ADVISE_SYSCALLS=y +# CONFIG_USERFAULTFD is not set +CONFIG_MEMBARRIER=y +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SYSTEM_DATA_VERIFICATION is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_UPROBES is not set +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_GCC_PLUGINS=y +# CONFIG_GCC_PLUGINS is not set +CONFIG_HAVE_CC_STACKPROTECTOR=y +# CONFIG_CC_STACKPROTECTOR is not set +CONFIG_CC_STACKPROTECTOR_NONE=y +# CONFIG_CC_STACKPROTECTOR_REGULAR is not set +# CONFIG_CC_STACKPROTECTOR_STRONG is not set +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_EXIT_THREAD=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=8 +CONFIG_ARCH_MMAP_RND_BITS_MAX=16 +CONFIG_ARCH_MMAP_RND_BITS=8 +# CONFIG_HAVE_ARCH_HASH is not set +# CONFIG_ISA_BUS_API is not set +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OLD_SIGACTION=y +# CONFIG_CPU_NO_EFFICIENT_FFS is not set +# CONFIG_HAVE_ARCH_VMAP_STACK is not set + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_CMDLINE_PARSER is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_EFI_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_MULTIPLATFORM is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +CONFIG_ARCH_FULLHAN=y +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP1 is not set + +# +# Fullhan platform type +# +# CONFIG_FH_FASTBOOT is not set +# CONFIG_ARCH_FH8833 is not set +# CONFIG_ARCH_FH8856 is not set +# CONFIG_ARCH_FH8626V100 is not set +CONFIG_ARCH_FH885xV200=y +# CONFIG_ARCH_FH865x is not set + +CONFIG_FH_CHIP_NAME="fh8856v200" +CONFIG_MACH_FH8856V200=y +# CONFIG_MACH_FH8852V200 is not set + +# +# Processor Type +# +CONFIG_CPU_V6=y +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_KUSER_HELPERS=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +# CONFIG_DEBUG_RODATA is not set +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_PJ4B_ERRATA_4742=y +# CONFIG_ARM_ERRATA_326103 is not set +CONFIG_ARM_ERRATA_411920=y +# CONFIG_ARM_ERRATA_364296 is not set + +# +# Bus support +# +# CONFIG_PCI_DOMAINS_GENERIC is not set +# CONFIG_PCI_SYSCALL is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_3G_OPT is not set +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_ARCH_NR_GPIO=0 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ_FIXED=0 +CONFIG_HZ_100=y +# CONFIG_HZ_200 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_500 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +# CONFIG_SCHED_HRTICK is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +# CONFIG_HIGHMEM is not set +CONFIG_CPU_SW_DOMAIN_PAN=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +# CONFIG_ARM_MODULE_PLTS is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_NO_BOOTMEM=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_CLEANCACHE is not set +# CONFIG_CMA is not set +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +# CONFIG_ZSMALLOC is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +CONFIG_SWIOTLB=y +CONFIG_IOMMU_HELPER=y +# CONFIG_PARAVIRT is not set +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set + +# +# Boot options +# +CONFIG_USE_OF=y +CONFIG_ATAGS=y +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND=y +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_AUTO_ZRELADDR=y +# CONFIG_EFI is not set + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# CPU Idle +# +# CONFIG_CPU_IDLE is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ELFCORE=y +CONFIG_BINFMT_SCRIPT=y +# CONFIG_BINFMT_FLAT is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y + +# +# Power management options +# +# CONFIG_SUSPEND is not set +# CONFIG_PM is not set +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_NET_IP_TUNNEL=y +# CONFIG_IP_MROUTE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_NET_IPVTI is not set +# CONFIG_NET_UDP_TUNNEL is not set +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_INET_DIAG_DESTROY is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +# CONFIG_IPV6_VTI is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_FOU is not set +# CONFIG_IPV6_FOU_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NET_PTP_CLASSIFY is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +CONFIG_HAVE_NET_DSA=y +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_MPLS is not set +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_NET_NCSI is not set +# CONFIG_SOCK_CGROUP_DATA is not set +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +# CONFIG_BPF_JIT is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +# CONFIG_STREAM_PARSER is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=y +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +# CONFIG_CFG80211_DEFAULT_PS is not set +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_CFG80211_WEXT=y +CONFIG_LIB80211=y +CONFIG_LIB80211_CRYPT_WEP=y +CONFIG_LIB80211_CRYPT_CCMP=y +CONFIG_LIB80211_CRYPT_TKIP=y +# CONFIG_LIB80211_DEBUG is not set +# CONFIG_MAC80211 is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +# CONFIG_RFKILL_INPUT is not set +# CONFIG_RFKILL_GPIO is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_LWTUNNEL is not set +CONFIG_DST_CACHE=y +# CONFIG_NET_DEVLINK is not set +CONFIG_MAY_USE_DEVLINK=y +CONFIG_HAVE_CBPF_JIT=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +# CONFIG_DMA_SHARED_BUFFER is not set + +# +# Bus devices +# +# CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_VEXPRESS_CONFIG is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR & LPDDR2 PCM memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_LPDDR2_NVM is not set +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_MT81xx_NOR is not set +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_MTD_UBI is not set +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_MDIO=y +CONFIG_OF_RESERVED_MEM=y +# CONFIG_OF_OVERLAY is not set +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_NVME_TARGET is not set + +# +# Misc devices +# +# CONFIG_FH_DW_I2S is not set +# CONFIG_FH_ACW is not set +CONFIG_FH_SADC_V3=y +CONFIG_FH_EFUSE=y +# CONFIG_FH_L2MEM is not set +CONFIG_FH_CLK_MISC=y +CONFIG_FH_PERF_MON=y +# CONFIG_FH_TSENSOR is not set +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_SRAM is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set + +# +# Intel MIC Bus Driver +# + +# +# SCIF Bus Driver +# + +# +# VOP Bus Driver +# + +# +# Intel MIC Host Driver +# + +# +# Intel MIC Card Driver +# + +# +# SCIF Driver +# + +# +# Intel MIC Coprocessor State Management (COSM) Drivers +# + +# +# VOP Driver +# +# CONFIG_ECHO is not set +# CONFIG_CXL_BASE is not set +# CONFIG_CXL_AFU_DRIVER_OPS is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_MACSEC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_TUN is not set +# CONFIG_TUN_VNET_CROSS_LE is not set +# CONFIG_VETH is not set +# CONFIG_NLMON is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +CONFIG_ETHERNET=y +# CONFIG_ALTERA_TSE is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_NET_VENDOR_FULLHAN=y +CONFIG_FH_GMAC=y +CONFIG_FH_GMAC_DA=y + +# +# fh inside or outside phy sel +# +CONFIG_PHYLIB=y +CONFIG_SWPHY=y + +# +# MDIO bus device drivers +# +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MDIO_HISI_FEMAC is not set + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_AT803X_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +CONFIG_FIXED_PHY=y +# CONFIG_ICPLUS_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +CONFIG_USB_NET_DRIVERS=y +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_RTL8152 is not set +# CONFIG_USB_LAN78XX is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_IPHETH is not set +CONFIG_WLAN=y +CONFIG_WLAN_VENDOR_ADMTEK=y +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +# CONFIG_ATH6KL is not set +CONFIG_WLAN_VENDOR_ATMEL=y +CONFIG_WLAN_VENDOR_BROADCOM=y +# CONFIG_BRCMFMAC is not set +CONFIG_WLAN_VENDOR_CISCO=y +CONFIG_WLAN_VENDOR_INTEL=y +CONFIG_WLAN_VENDOR_INTERSIL=y +CONFIG_HOSTAP=y +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +CONFIG_WLAN_VENDOR_MARVELL=y +# CONFIG_LIBERTAS is not set +# CONFIG_MWIFIEX is not set +CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_WLAN_VENDOR_REALTEK=y +CONFIG_WLAN_VENDOR_RSI=y +CONFIG_WLAN_VENDOR_ST=y +CONFIG_WLAN_VENDOR_TI=y +CONFIG_WLAN_VENDOR_ZYDAS=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_ISDN is not set +# CONFIG_NVM is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVMEM=y +# CONFIG_DEVKMEM is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set +CONFIG_SERIAL_FULLHAN=y +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +# CONFIG_SERIAL_ST_ASC is not set +# CONFIG_SERIAL_STM32 is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_XILLYBUS is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_SMBUS is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_FH_INTERRUPT=y +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_EMEV2 is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_RK3X is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_DESIGNWARE is not set +CONFIG_SPI_FH=y + +# +# spi multi wire support +# +CONFIG_SPI_USE_MULTI_WIRE=y +CONFIG_SPI_SWAP_MAX_DATA_WIDTH=16 +# CONFIG_SPI_USE_DMA is not set +CONFIG_SPI_TINY_MEM=y +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +# CONFIG_PTP_1588_CLOCK is not set + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_PINCTRL=y + +# +# Pin controllers +# +CONFIG_PINMUX=y +CONFIG_PINCTRL_FULLHAN=y +# CONFIG_PINCTRL_AMD is not set +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_GPIOLIB=y +CONFIG_OF_GPIO=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers +# +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ALTERA is not set +CONFIG_GPIO_FH=y +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_EM is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_MPC8XXX is not set +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_ZEVIO is not set +# CONFIG_GPIO_ZX is not set + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_TPIC2810 is not set +# CONFIG_GPIO_TS4900 is not set + +# +# MFD GPIO expanders +# +# CONFIG_HTC_EGPIO is not set + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set + +# +# SPI or I2C GPIO expanders +# +# CONFIG_GPIO_MCP23S08 is not set + +# +# USB GPIO expanders +# +# CONFIG_W1 is not set +# CONFIG_POWER_AVS is not set +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_BRCMKONA is not set +# CONFIG_POWER_RESET_GPIO is not set +# CONFIG_POWER_RESET_GPIO_RESTART is not set +CONFIG_POWER_RESET_FH=y +# CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_RESTART is not set +# CONFIG_POWER_RESET_SYSCON is not set +# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_CORE is not set +# CONFIG_WATCHDOG_NOWAYOUT is not set +# CONFIG_WATCHDOG_SYSFS is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_GPIO_WATCHDOG is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_FH_WATCHDOG=y +# CONFIG_MEN_A21_WDT is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set + +# +# Watchdog Pretimeout Governors +# +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_ACT8945A is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_EXYNOS_LPASS is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_INTEL_SOC_PMIC is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77620 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_PM8921_CORE is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RTSX_USB is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RK808 is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set +# CONFIG_SOUND is not set + +# +# HID support +# +# CONFIG_HID is not set + +# +# USB HID support +# +# CONFIG_USB_HID is not set +# CONFIG_HID_PID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +CONFIG_USB_DYNAMIC_MINORS=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +CONFIG_USB_WUSB_CBAF=y +# CONFIG_USB_WUSB_CBAF_DEBUG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_MAX3421_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +CONFIG_USB_WDM=y +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_DWC3 is not set +CONFIG_USB_DWC2=y +CONFIG_USB_DWC2_HOST=y + +# +# Gadget/Dual-role mode requires USB Gadget support to be enabled +# +# CONFIG_USB_DWC2_VBVALIDOVEN is not set +# CONFIG_USB_DWC2_DEBUG is not set +# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set +# CONFIG_USB_DWC2_HOST_DMA_DESC_NUM_DYNAMIC is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set + +# +# USB Physical Layer drivers +# +# CONFIG_USB_PHY is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ULPI is not set +# CONFIG_USB_GADGET is not set +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_UWB is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_PWRSEQ_EMMC=y +CONFIG_PWRSEQ_SIMPLE=y + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SPI is not set +CONFIG_MMC_FH=y +CONFIG_MMC_FH_IDMAC=y +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_MTK is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +# CONFIG_EDAC is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_HYM8563 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV8803 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6916 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RX6110 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_MCP795 is not set +# CONFIG_RTC_I2C_AND_SPI is not set + +# +# SPI and I2C RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_ZYNQMP is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_SNVS is not set +CONFIG_RTC_DRV_FH=y +CONFIG_USE_TSENSOR=y +# CONFIG_USE_TSENSOR_OFFSET is not set + +# +# HID Sensor RTC drivers +# +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +# CONFIG_DW_DMAC is not set +# CONFIG_FH_DMAC is not set +CONFIG_FH_AXI_DMAC=y +CONFIG_FH_DMAC_MISC=y + +# +# dma tinyconfig +# +CONFIG_CHANNEL_ALLOC_MEM_CLASSICS=y +CONFIG_CHANNEL_ALLOC_DESC_NUM=32 +# CONFIG_FSL_EDMA is not set +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_NBPFAXI_DMA is not set +# CONFIG_QCOM_HIDMA_MGMT is not set +# CONFIG_QCOM_HIDMA is not set + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set + +# +# DMABUF options +# +# CONFIG_SYNC_FILE is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VIRT_DRIVERS is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_STAGING is not set +# CONFIG_GOLDFISH is not set +# CONFIG_CHROME_PLATFORMS is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI514 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CDCE925 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_CLK_QORIQ is not set +# CONFIG_COMMON_CLK_NXP is not set +# CONFIG_COMMON_CLK_PWM is not set +# CONFIG_COMMON_CLK_PXA is not set +# CONFIG_COMMON_CLK_PIC32 is not set + +# +# Hardware Spinlock drivers +# + +# +# Clock Source drivers +# +CONFIG_CLKSRC_OF=y +CONFIG_CLKSRC_PROBE=y +CONFIG_FULLHAN_TIMER=y +# CONFIG_FH_SIMPLE_TIMER is not set +# CONFIG_ARM_TIMER_SP804 is not set +# CONFIG_ATMEL_PIT is not set +# CONFIG_SH_TIMER_CMT is not set +# CONFIG_SH_TIMER_MTU2 is not set +# CONFIG_SH_TIMER_TMU is not set +# CONFIG_EM_TIMER_STI is not set +# CONFIG_MAILBOX is not set +# CONFIG_IOMMU_SUPPORT is not set + +# +# Remoteproc drivers +# +# CONFIG_STE_MODEM_RPROC is not set + +# +# Rpmsg drivers +# + +# +# SOC (System On Chip) specific Drivers +# + +# +# Broadcom SoC drivers +# +# CONFIG_SOC_BRCMSTB is not set +# CONFIG_SUNXI_SRAM is not set +# CONFIG_SOC_TI is not set +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +CONFIG_PWM=y +# CONFIG_PWM_SYSFS is not set +# CONFIG_DEBUG_PWM_FS is not set +CONFIG_PWM_FULLHAN=y +CONFIG_FH_PWM_NUM=2 +# CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_PCA9685 is not set +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC_MAX_NR=1 +CONFIG_FULLHAN_INTC=y +# CONFIG_IPACK_BUS is not set +# CONFIG_RESET_CONTROLLER is not set +# CONFIG_FMC is not set + +# +# PHY Subsystem +# +# CONFIG_GENERIC_PHY is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_FH_USB2_PHY is not set +# CONFIG_PHY_SAMSUNG_USB2 is not set +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +# CONFIG_RAS is not set + +# +# Android +# +# CONFIG_ANDROID is not set +# CONFIG_NVMEM is not set +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set + +# +# FPGA Configuration Support +# +# CONFIG_FPGA is not set + +# +# Firmware Drivers +# +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_FW_CFG_SYSFS is not set + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_FILE_LOCKING=y +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +# CONFIG_OVERLAY_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_PROC_CHILDREN is not set +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_WRITEBUFFER is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V2 is not set +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_SWAP is not set +# CONFIG_ROOT_NFS is not set +# CONFIG_NFSD is not set +CONFIG_GRACE_PERIOD=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_DYNAMIC_DEBUG is not set + +# +# Compile-time checks and compiler options +# +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_OPTIMIZE_INLINING=y +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_DEBUG_KERNEL is not set + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_MEMORY_INIT is not set + +# +# Debug Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_SCHED_INFO is not set +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +# CONFIG_STACKTRACE is not set + +# +# RCU Debugging +# +# CONFIG_PROVE_RCU is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_TORTURE_TEST is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_HWLAT_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_FTRACE_SYSCALLS is not set +# CONFIG_TRACER_SNAPSHOT is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_PROBE_EVENTS is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +CONFIG_TRACING_EVENTS_GPIO=y + +# +# Runtime Testing +# +# CONFIG_LKDTM is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_HASH is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_MEMTEST is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set +# CONFIG_UBSAN is not set +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +# CONFIG_STRICT_DEVMEM is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_UART_8250 is not set +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_DEBUG_SET_MODULE_RONX is not set +# CONFIG_CORESIGHT is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_BIG_KEYS is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEY_DH_OPERATIONS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y +# CONFIG_HARDENED_USERCOPY is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_KPP2=y +# CONFIG_CRYPTO_RSA is not set +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_ECDH is not set +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_MCRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_KEYWRAP is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_CMAC is not set +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +CONFIG_CRYPTO_MICHAEL_MIC=y +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +CONFIG_CRYPTO_SHA256=y +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG is not set +# CONFIG_CRYPTO_JITTERENTROPY is not set +CONFIG_CRYPTO_USER_API=y +# CONFIG_CRYPTO_USER_API_HASH is not set +CONFIG_CRYPTO_USER_API_SKCIPHER=y +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_DEV_FH_AES=y +# CONFIG_CRYPTO_FH_AES_SUPPORT_DIRECT_MEM is not set +# CONFIG_FH_AES_SELF_TEST is not set +# CONFIG_ASYMMETRIC_KEY_TYPE is not set + +# +# Certificates for signature checking +# +# CONFIG_ARM_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_HAVE_ARCH_BITREVERSE is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_XZ=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y +# CONFIG_CORDIC is not set +# CONFIG_DDR is not set +# CONFIG_IRQ_POLL is not set +CONFIG_LIBFDT=y +# CONFIG_SG_SPLIT is not set +# CONFIG_SG_POOL is not set +# CONFIG_ARCH_HAS_SG_CHAIN is not set +CONFIG_SBITMAP=y +# CONFIG_VIRTUALIZATION is not set diff --git a/arch/arm/configs/fh8856v210_defconfig b/arch/arm/configs/fh8856v210_defconfig new file mode 100644 index 00000000..34856420 --- /dev/null +++ b/arch/arm/configs/fh8856v210_defconfig @@ -0,0 +1,2253 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 4.9.129 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y + +# +# General setup +# +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_TINY_KERNEL=y +CONFIG_NTP=y +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_LZMA is not set +CONFIG_KERNEL_XZ=y +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_NO_COMPRESS is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_FHANDLE is not set +CONFIG_USELIB=y +# CONFIG_AUDIT is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_IRQ_DOMAIN=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_GENERIC_CLOCKEVENTS=y + +# +# Timers subsystem +# +CONFIG_HZ_PERIODIC=y +# CONFIG_NO_HZ_IDLE is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set + +# +# RCU Subsystem +# +CONFIG_TINY_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +# CONFIG_TASKS_RCU is not set +# CONFIG_RCU_STALL_COMMON is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_EXPEDITE_BOOT is not set +# CONFIG_BUILD_BIN2C is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_NMI_LOG_BUF_SHIFT=13 +CONFIG_GENERIC_SCHED_CLOCK=y +# CONFIG_CGROUPS is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SCHED_DL is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="usr/rootfs.cpio.xz" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +CONFIG_RD_XZ=y +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_HAVE_UID16=y +CONFIG_BPF=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +CONFIG_SYSFS_SYSCALL=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set +CONFIG_KALLSYMS_BASE_RELATIVE=y +CONFIG_PRINTK=y +CONFIG_PRINTK_NMI=y +# CONFIG_BUG is not set +# CONFIG_ELF_CORE is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +# CONFIG_BPF_SYSCALL is not set +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_ADVISE_SYSCALLS=y +# CONFIG_USERFAULTFD is not set +CONFIG_MEMBARRIER=y +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SYSTEM_DATA_VERIFICATION is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_UPROBES is not set +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_GCC_PLUGINS=y +# CONFIG_GCC_PLUGINS is not set +CONFIG_HAVE_CC_STACKPROTECTOR=y +# CONFIG_CC_STACKPROTECTOR is not set +CONFIG_CC_STACKPROTECTOR_NONE=y +# CONFIG_CC_STACKPROTECTOR_REGULAR is not set +# CONFIG_CC_STACKPROTECTOR_STRONG is not set +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_EXIT_THREAD=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=8 +CONFIG_ARCH_MMAP_RND_BITS_MAX=16 +CONFIG_ARCH_MMAP_RND_BITS=8 +# CONFIG_HAVE_ARCH_HASH is not set +# CONFIG_ISA_BUS_API is not set +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OLD_SIGACTION=y +# CONFIG_CPU_NO_EFFICIENT_FFS is not set +# CONFIG_HAVE_ARCH_VMAP_STACK is not set + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_CMDLINE_PARSER is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_EFI_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_MULTIPLATFORM is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +CONFIG_ARCH_FULLHAN=y +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP1 is not set + +# +# Fullhan platform type +# +# CONFIG_FH_FASTBOOT is not set +# CONFIG_ARCH_FH8833 is not set +# CONFIG_ARCH_FH8856 is not set +# CONFIG_ARCH_FH8852 is not set +# CONFIG_ARCH_FH8626V100 is not set +CONFIG_ARCH_FH885xV200=y +# CONFIG_ARCH_FH865x is not set + +CONFIG_FH_CHIP_NAME="fh8856v210" +CONFIG_MACH_FH8856V210=y +# CONFIG_MACH_FH8852V200 is not set +# CONFIG_MACH_FH8858V200 is not set + +# +# Processor Type +# +CONFIG_CPU_V6=y +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_KUSER_HELPERS=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +# CONFIG_DEBUG_RODATA is not set +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_PJ4B_ERRATA_4742=y +# CONFIG_ARM_ERRATA_326103 is not set +CONFIG_ARM_ERRATA_411920=y +# CONFIG_ARM_ERRATA_364296 is not set + +# +# Bus support +# +# CONFIG_PCI_DOMAINS_GENERIC is not set +# CONFIG_PCI_SYSCALL is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_3G_OPT is not set +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_ARCH_NR_GPIO=0 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ_FIXED=0 +CONFIG_HZ_100=y +# CONFIG_HZ_200 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_500 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +# CONFIG_SCHED_HRTICK is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +# CONFIG_HIGHMEM is not set +CONFIG_CPU_SW_DOMAIN_PAN=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +# CONFIG_ARM_MODULE_PLTS is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_NO_BOOTMEM=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_CLEANCACHE is not set +# CONFIG_CMA is not set +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +# CONFIG_ZSMALLOC is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +CONFIG_SWIOTLB=y +CONFIG_IOMMU_HELPER=y +# CONFIG_PARAVIRT is not set +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set + +# +# Boot options +# +# CONFIG_USE_OF is not set +CONFIG_ATAGS=y +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_AUTO_ZRELADDR=y + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# CPU Idle +# +# CONFIG_CPU_IDLE is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ELFCORE=y +CONFIG_BINFMT_SCRIPT=y +# CONFIG_BINFMT_FLAT is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y + +# +# Power management options +# +# CONFIG_SUSPEND is not set +# CONFIG_PM is not set +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_NET_IP_TUNNEL=y +# CONFIG_IP_MROUTE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_NET_IPVTI is not set +# CONFIG_NET_UDP_TUNNEL is not set +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_INET_DIAG_DESTROY is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +# CONFIG_IPV6_VTI is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_FOU is not set +# CONFIG_IPV6_FOU_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NET_PTP_CLASSIFY is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +CONFIG_HAVE_NET_DSA=y +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_MPLS is not set +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_NET_NCSI is not set +# CONFIG_SOCK_CGROUP_DATA is not set +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +# CONFIG_BPF_JIT is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +# CONFIG_STREAM_PARSER is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=y +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +# CONFIG_CFG80211_DEFAULT_PS is not set +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_CFG80211_WEXT=y +CONFIG_LIB80211=y +CONFIG_LIB80211_CRYPT_WEP=y +CONFIG_LIB80211_CRYPT_CCMP=y +CONFIG_LIB80211_CRYPT_TKIP=y +# CONFIG_LIB80211_DEBUG is not set +# CONFIG_MAC80211 is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +# CONFIG_RFKILL_INPUT is not set +# CONFIG_RFKILL_GPIO is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_LWTUNNEL is not set +CONFIG_DST_CACHE=y +# CONFIG_NET_DEVLINK is not set +CONFIG_MAY_USE_DEVLINK=y +CONFIG_HAVE_CBPF_JIT=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +# CONFIG_DMA_SHARED_BUFFER is not set + +# +# Bus devices +# +# CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR & LPDDR2 PCM memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_LPDDR2_NVM is not set +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_MT81xx_NOR is not set +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MTD_UBI is not set +# CONFIG_OF is not set +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_NVME_TARGET is not set + +# +# Misc devices +# +# CONFIG_FH_DW_I2S is not set +# CONFIG_FH_ACW is not set +CONFIG_FH_SADC_V3=y +CONFIG_FH_EFUSE=y +# CONFIG_FH_L2MEM is not set +CONFIG_FH_PINCTRL_MISC_DEV=y +CONFIG_FH_CLK_MISC=y +CONFIG_FH_PERF_MON=y +# CONFIG_FH_TSENSOR is not set +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_SRAM is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set + +# +# Intel MIC Bus Driver +# + +# +# SCIF Bus Driver +# + +# +# VOP Bus Driver +# + +# +# Intel MIC Host Driver +# + +# +# Intel MIC Card Driver +# + +# +# SCIF Driver +# + +# +# Intel MIC Coprocessor State Management (COSM) Drivers +# + +# +# VOP Driver +# +# CONFIG_ECHO is not set +# CONFIG_CXL_BASE is not set +# CONFIG_CXL_AFU_DRIVER_OPS is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_MACSEC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_TUN is not set +# CONFIG_TUN_VNET_CROSS_LE is not set +# CONFIG_VETH is not set +# CONFIG_NLMON is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +CONFIG_ETHERNET=y +# CONFIG_ALTERA_TSE is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_NET_VENDOR_FULLHAN=y +CONFIG_FH_GMAC=y +CONFIG_FH_GMAC_DA=y +CONFIG_PHYLIB=y +CONFIG_SWPHY=y + +# +# MDIO bus device drivers +# +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_BITBANG is not set + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_AT803X_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +CONFIG_FIXED_PHY=y +# CONFIG_ICPLUS_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +CONFIG_USB_NET_DRIVERS=y +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_RTL8152 is not set +# CONFIG_USB_LAN78XX is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_IPHETH is not set +CONFIG_WLAN=y +CONFIG_WLAN_VENDOR_ADMTEK=y +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +# CONFIG_ATH6KL is not set +CONFIG_WLAN_VENDOR_ATMEL=y +CONFIG_WLAN_VENDOR_BROADCOM=y +# CONFIG_BRCMFMAC is not set +CONFIG_WLAN_VENDOR_CISCO=y +CONFIG_WLAN_VENDOR_INTEL=y +CONFIG_WLAN_VENDOR_INTERSIL=y +CONFIG_HOSTAP=y +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +CONFIG_WLAN_VENDOR_MARVELL=y +# CONFIG_LIBERTAS is not set +# CONFIG_MWIFIEX is not set +CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_WLAN_VENDOR_REALTEK=y +CONFIG_WLAN_VENDOR_RSI=y +CONFIG_WLAN_VENDOR_ST=y +CONFIG_WLAN_VENDOR_TI=y +CONFIG_WLAN_VENDOR_ZYDAS=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_ISDN is not set +# CONFIG_NVM is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVMEM=y +# CONFIG_DEVKMEM is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set +CONFIG_SERIAL_FULLHAN=y +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_ST_ASC is not set +# CONFIG_SERIAL_STM32 is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_SMBUS is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_FH_INTERRUPT=y +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_EMEV2 is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_DESIGNWARE is not set +CONFIG_SPI_FH=y +# CONFIG_SPI_FH_SLAVE is not set + +# +# spi multi wire support +# +CONFIG_SPI_USE_MULTI_WIRE=y +CONFIG_SPI_SWAP_MAX_DATA_WIDTH=16 +# CONFIG_SPI_USE_DMA is not set +CONFIG_SPI_TINY_MEM=y +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +# CONFIG_PTP_1588_CLOCK is not set + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers +# +CONFIG_GPIO_FH=y +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_MPC8XXX is not set +# CONFIG_GPIO_ZX is not set + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_TPIC2810 is not set +# CONFIG_GPIO_TS4900 is not set + +# +# MFD GPIO expanders +# +# CONFIG_HTC_EGPIO is not set + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set + +# +# SPI or I2C GPIO expanders +# + +# +# USB GPIO expanders +# +# CONFIG_W1 is not set +# CONFIG_POWER_AVS is not set +# CONFIG_POWER_RESET is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_CORE is not set +# CONFIG_WATCHDOG_NOWAYOUT is not set +# CONFIG_WATCHDOG_SYSFS is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_FH_WATCHDOG=y +# CONFIG_MEN_A21_WDT is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set + +# +# Watchdog Pretimeout Governors +# +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_EXYNOS_LPASS is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_INTEL_SOC_PMIC is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_PM8921_CORE is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RTSX_USB is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set +# CONFIG_SOUND is not set + +# +# HID support +# +# CONFIG_HID is not set + +# +# USB HID support +# +# CONFIG_USB_HID is not set +# CONFIG_HID_PID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +CONFIG_USB_DYNAMIC_MINORS=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +CONFIG_USB_WUSB_CBAF=y +# CONFIG_USB_WUSB_CBAF_DEBUG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_MAX3421_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +CONFIG_USB_WDM=y +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_DWC3 is not set +CONFIG_USB_DWC2=y +CONFIG_USB_DWC2_HOST=y + +# +# Gadget/Dual-role mode requires USB Gadget support to be enabled +# +# CONFIG_USB_DWC2_VBVALIDOVEN is not set +# CONFIG_USB_DWC2_DEBUG is not set +# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set +# CONFIG_USB_DWC2_HOST_DMA_DESC_NUM_DYNAMIC is not set +CONFIG_USB_DWC2_DMA=y +# CONFIG_USB_DWC2_DMA_DESC is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set + +# +# USB Physical Layer drivers +# +# CONFIG_USB_PHY is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ULPI is not set +# CONFIG_USB_GADGET is not set +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_UWB is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SPI is not set +CONFIG_MMC_FH=y +CONFIG_MMC_FH_IDMAC=y +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_MTK is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +# CONFIG_EDAC is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV8803 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6916 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RX6110 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_MCP795 is not set +# CONFIG_RTC_I2C_AND_SPI is not set + +# +# SPI and I2C RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_FH=y +CONFIG_USE_TSENSOR=y +# CONFIG_USE_TSENSOR_OFFSET is not set + +# +# HID Sensor RTC drivers +# +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +# CONFIG_DW_DMAC is not set +CONFIG_CHANNEL_ALLOC_MEM_CLASSICS=y +# CONFIG_FH_DMAC is not set +CONFIG_FH_AXI_DMAC=y +CONFIG_FH_DMAC_MISC=y + +# +# dma tinyconfig +# +CONFIG_CHANNEL_ALLOC_DESC_NUM=32 +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_NBPFAXI_DMA is not set +# CONFIG_QCOM_HIDMA_MGMT is not set +# CONFIG_QCOM_HIDMA is not set + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set + +# +# DMABUF options +# +# CONFIG_SYNC_FILE is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VIRT_DRIVERS is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_STAGING is not set +# CONFIG_GOLDFISH is not set +# CONFIG_CHROME_PLATFORMS is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_COMMON_CLK_NXP is not set +# CONFIG_COMMON_CLK_PWM is not set +# CONFIG_COMMON_CLK_PXA is not set +# CONFIG_COMMON_CLK_PIC32 is not set + +# +# Hardware Spinlock drivers +# + +# +# Clock Source drivers +# +CONFIG_FULLHAN_TIMER=y +# CONFIG_FH_SIMPLE_TIMER is not set +# CONFIG_ARM_TIMER_SP804 is not set +# CONFIG_ATMEL_PIT is not set +# CONFIG_SH_TIMER_CMT is not set +# CONFIG_SH_TIMER_MTU2 is not set +# CONFIG_SH_TIMER_TMU is not set +# CONFIG_EM_TIMER_STI is not set +# CONFIG_MAILBOX is not set +# CONFIG_IOMMU_SUPPORT is not set + +# +# Remoteproc drivers +# +# CONFIG_STE_MODEM_RPROC is not set + +# +# Rpmsg drivers +# + +# +# SOC (System On Chip) specific Drivers +# + +# +# Broadcom SoC drivers +# +# CONFIG_SOC_BRCMSTB is not set +# CONFIG_SUNXI_SRAM is not set +# CONFIG_SOC_TI is not set +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +CONFIG_PWM=y +# CONFIG_PWM_SYSFS is not set +# CONFIG_DEBUG_PWM_FS is not set +CONFIG_PWM_FULLHAN=y +CONFIG_FH_PWM_NUM=14 +# CONFIG_PWM_PCA9685 is not set +CONFIG_ARM_GIC_MAX_NR=1 +CONFIG_FULLHAN_INTC=y +# CONFIG_IPACK_BUS is not set +# CONFIG_RESET_CONTROLLER is not set +# CONFIG_FMC is not set + +# +# PHY Subsystem +# +# CONFIG_GENERIC_PHY is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_FH_USB2_PHY is not set +# CONFIG_PHY_SAMSUNG_USB2 is not set +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +# CONFIG_RAS is not set + +# +# Android +# +# CONFIG_ANDROID is not set +# CONFIG_NVMEM is not set +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set + +# +# FPGA Configuration Support +# +# CONFIG_FPGA is not set + +# +# Firmware Drivers +# +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_FW_CFG_SYSFS is not set + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_FILE_LOCKING=y +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +# CONFIG_OVERLAY_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_PROC_CHILDREN is not set +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_WRITEBUFFER is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V2 is not set +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_SWAP is not set +# CONFIG_ROOT_NFS is not set +# CONFIG_NFSD is not set +CONFIG_GRACE_PERIOD=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_DYNAMIC_DEBUG is not set + +# +# Compile-time checks and compiler options +# +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_OPTIMIZE_INLINING=y +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_DEBUG_KERNEL is not set + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_MEMORY_INIT is not set + +# +# Debug Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_SCHED_INFO is not set +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +# CONFIG_STACKTRACE is not set + +# +# RCU Debugging +# +# CONFIG_PROVE_RCU is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_TORTURE_TEST is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_HWLAT_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_FTRACE_SYSCALLS is not set +# CONFIG_TRACER_SNAPSHOT is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_PROBE_EVENTS is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +CONFIG_TRACING_EVENTS_GPIO=y + +# +# Runtime Testing +# +# CONFIG_LKDTM is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_HASH is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_MEMTEST is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set +# CONFIG_UBSAN is not set +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +# CONFIG_STRICT_DEVMEM is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_UART_8250 is not set +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_DEBUG_SET_MODULE_RONX is not set +# CONFIG_CORESIGHT is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_BIG_KEYS is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEY_DH_OPERATIONS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y +# CONFIG_HARDENED_USERCOPY is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_KPP2=y +# CONFIG_CRYPTO_RSA is not set +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_ECDH is not set +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_MCRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_KEYWRAP is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_CMAC is not set +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +CONFIG_CRYPTO_MICHAEL_MIC=y +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +CONFIG_CRYPTO_SHA256=y +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG is not set +# CONFIG_CRYPTO_JITTERENTROPY is not set +CONFIG_CRYPTO_USER_API=y +# CONFIG_CRYPTO_USER_API_HASH is not set +CONFIG_CRYPTO_USER_API_SKCIPHER=y +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_FH_CESA is not set +CONFIG_CRYPTO_DEV_FH_AES=y +# CONFIG_CRYPTO_FH_AES_SUPPORT_DIRECT_MEM is not set +# CONFIG_FH_AES_SELF_TEST is not set +# CONFIG_ASYMMETRIC_KEY_TYPE is not set + +# +# Certificates for signature checking +# +# CONFIG_ARM_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_HAVE_ARCH_BITREVERSE is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_XZ=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y +# CONFIG_CORDIC is not set +# CONFIG_DDR is not set +# CONFIG_IRQ_POLL is not set +# CONFIG_SG_SPLIT is not set +# CONFIG_SG_POOL is not set +# CONFIG_ARCH_HAS_SG_CHAIN is not set +CONFIG_SBITMAP=y +# CONFIG_VIRTUALIZATION is not set diff --git a/arch/arm/configs/fh8856v210_of_defconfig b/arch/arm/configs/fh8856v210_of_defconfig new file mode 100644 index 00000000..e80393de --- /dev/null +++ b/arch/arm/configs/fh8856v210_of_defconfig @@ -0,0 +1,2332 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 4.9.129 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y + +# +# General setup +# +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_TINY_KERNEL=y +CONFIG_NTP=y +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_LZMA is not set +CONFIG_KERNEL_XZ=y +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_NO_COMPRESS is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_FHANDLE is not set +CONFIG_USELIB=y +# CONFIG_AUDIT is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_IRQ_DOMAIN=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_GENERIC_CLOCKEVENTS=y + +# +# Timers subsystem +# +CONFIG_HZ_PERIODIC=y +# CONFIG_NO_HZ_IDLE is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set + +# +# RCU Subsystem +# +CONFIG_TINY_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +# CONFIG_TASKS_RCU is not set +# CONFIG_RCU_STALL_COMMON is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_EXPEDITE_BOOT is not set +# CONFIG_BUILD_BIN2C is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_NMI_LOG_BUF_SHIFT=13 +CONFIG_GENERIC_SCHED_CLOCK=y +# CONFIG_CGROUPS is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SCHED_DL is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="usr/rootfs.cpio.xz" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +CONFIG_RD_XZ=y +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_HAVE_UID16=y +CONFIG_BPF=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +CONFIG_SYSFS_SYSCALL=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set +CONFIG_KALLSYMS_BASE_RELATIVE=y +CONFIG_PRINTK=y +CONFIG_PRINTK_NMI=y +# CONFIG_BUG is not set +# CONFIG_ELF_CORE is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +# CONFIG_BPF_SYSCALL is not set +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_ADVISE_SYSCALLS=y +# CONFIG_USERFAULTFD is not set +CONFIG_MEMBARRIER=y +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SYSTEM_DATA_VERIFICATION is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_UPROBES is not set +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_GCC_PLUGINS=y +# CONFIG_GCC_PLUGINS is not set +CONFIG_HAVE_CC_STACKPROTECTOR=y +# CONFIG_CC_STACKPROTECTOR is not set +CONFIG_CC_STACKPROTECTOR_NONE=y +# CONFIG_CC_STACKPROTECTOR_REGULAR is not set +# CONFIG_CC_STACKPROTECTOR_STRONG is not set +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_EXIT_THREAD=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=8 +CONFIG_ARCH_MMAP_RND_BITS_MAX=16 +CONFIG_ARCH_MMAP_RND_BITS=8 +# CONFIG_HAVE_ARCH_HASH is not set +# CONFIG_ISA_BUS_API is not set +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OLD_SIGACTION=y +# CONFIG_CPU_NO_EFFICIENT_FFS is not set +# CONFIG_HAVE_ARCH_VMAP_STACK is not set + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_CMDLINE_PARSER is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_EFI_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_MULTIPLATFORM is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +CONFIG_ARCH_FULLHAN=y +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP1 is not set + +# +# Fullhan platform type +# +# CONFIG_FH_FASTBOOT is not set +# CONFIG_ARCH_FH8833 is not set +# CONFIG_ARCH_FH8856 is not set +# CONFIG_ARCH_FH8626V100 is not set +CONFIG_ARCH_FH885xV200=y +# CONFIG_ARCH_FH865x is not set + +CONFIG_FH_CHIP_NAME="fh8856v210" +CONFIG_MACH_FH8856V210=y +# CONFIG_MACH_FH8852V200 is not set + +# +# Processor Type +# +CONFIG_CPU_V6=y +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_KUSER_HELPERS=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +# CONFIG_DEBUG_RODATA is not set +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_PJ4B_ERRATA_4742=y +# CONFIG_ARM_ERRATA_326103 is not set +CONFIG_ARM_ERRATA_411920=y +# CONFIG_ARM_ERRATA_364296 is not set + +# +# Bus support +# +# CONFIG_PCI_DOMAINS_GENERIC is not set +# CONFIG_PCI_SYSCALL is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_3G_OPT is not set +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_ARCH_NR_GPIO=0 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ_FIXED=0 +CONFIG_HZ_100=y +# CONFIG_HZ_200 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_500 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +# CONFIG_SCHED_HRTICK is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +# CONFIG_HIGHMEM is not set +CONFIG_CPU_SW_DOMAIN_PAN=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +# CONFIG_ARM_MODULE_PLTS is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_NO_BOOTMEM=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_CLEANCACHE is not set +# CONFIG_CMA is not set +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +# CONFIG_ZSMALLOC is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +CONFIG_SWIOTLB=y +CONFIG_IOMMU_HELPER=y +# CONFIG_PARAVIRT is not set +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set + +# +# Boot options +# +CONFIG_USE_OF=y +CONFIG_ATAGS=y +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND=y +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_AUTO_ZRELADDR=y +# CONFIG_EFI is not set + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# CPU Idle +# +# CONFIG_CPU_IDLE is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ELFCORE=y +CONFIG_BINFMT_SCRIPT=y +# CONFIG_BINFMT_FLAT is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y + +# +# Power management options +# +# CONFIG_SUSPEND is not set +# CONFIG_PM is not set +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_NET_IP_TUNNEL=y +# CONFIG_IP_MROUTE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_NET_IPVTI is not set +# CONFIG_NET_UDP_TUNNEL is not set +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_INET_DIAG_DESTROY is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +# CONFIG_IPV6_VTI is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_FOU is not set +# CONFIG_IPV6_FOU_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NET_PTP_CLASSIFY is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +CONFIG_HAVE_NET_DSA=y +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_MPLS is not set +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_NET_NCSI is not set +# CONFIG_SOCK_CGROUP_DATA is not set +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +# CONFIG_BPF_JIT is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +# CONFIG_STREAM_PARSER is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=y +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +# CONFIG_CFG80211_DEFAULT_PS is not set +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_CFG80211_WEXT=y +CONFIG_LIB80211=y +CONFIG_LIB80211_CRYPT_WEP=y +CONFIG_LIB80211_CRYPT_CCMP=y +CONFIG_LIB80211_CRYPT_TKIP=y +# CONFIG_LIB80211_DEBUG is not set +# CONFIG_MAC80211 is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +# CONFIG_RFKILL_INPUT is not set +# CONFIG_RFKILL_GPIO is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_LWTUNNEL is not set +CONFIG_DST_CACHE=y +# CONFIG_NET_DEVLINK is not set +CONFIG_MAY_USE_DEVLINK=y +CONFIG_HAVE_CBPF_JIT=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +# CONFIG_DMA_SHARED_BUFFER is not set + +# +# Bus devices +# +# CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_VEXPRESS_CONFIG is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR & LPDDR2 PCM memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_LPDDR2_NVM is not set +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_MT81xx_NOR is not set +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_MTD_UBI is not set +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_MDIO=y +CONFIG_OF_RESERVED_MEM=y +# CONFIG_OF_OVERLAY is not set +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_NVME_TARGET is not set + +# +# Misc devices +# +# CONFIG_FH_DW_I2S is not set +# CONFIG_FH_ACW is not set +CONFIG_FH_SADC_V3=y +CONFIG_FH_EFUSE=y +# CONFIG_FH_L2MEM is not set +CONFIG_FH_CLK_MISC=y +CONFIG_FH_PERF_MON=y +# CONFIG_FH_TSENSOR is not set +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_SRAM is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set + +# +# Intel MIC Bus Driver +# + +# +# SCIF Bus Driver +# + +# +# VOP Bus Driver +# + +# +# Intel MIC Host Driver +# + +# +# Intel MIC Card Driver +# + +# +# SCIF Driver +# + +# +# Intel MIC Coprocessor State Management (COSM) Drivers +# + +# +# VOP Driver +# +# CONFIG_ECHO is not set +# CONFIG_CXL_BASE is not set +# CONFIG_CXL_AFU_DRIVER_OPS is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_MACSEC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_TUN is not set +# CONFIG_TUN_VNET_CROSS_LE is not set +# CONFIG_VETH is not set +# CONFIG_NLMON is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +CONFIG_ETHERNET=y +# CONFIG_ALTERA_TSE is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_NET_VENDOR_FULLHAN=y +CONFIG_FH_GMAC=y +CONFIG_FH_GMAC_DA=y + +# +# fh inside or outside phy sel +# +CONFIG_PHYLIB=y +CONFIG_SWPHY=y + +# +# MDIO bus device drivers +# +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MDIO_HISI_FEMAC is not set + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_AT803X_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +CONFIG_FIXED_PHY=y +# CONFIG_ICPLUS_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +CONFIG_USB_NET_DRIVERS=y +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_RTL8152 is not set +# CONFIG_USB_LAN78XX is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_IPHETH is not set +CONFIG_WLAN=y +CONFIG_WLAN_VENDOR_ADMTEK=y +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +# CONFIG_ATH6KL is not set +CONFIG_WLAN_VENDOR_ATMEL=y +CONFIG_WLAN_VENDOR_BROADCOM=y +# CONFIG_BRCMFMAC is not set +CONFIG_WLAN_VENDOR_CISCO=y +CONFIG_WLAN_VENDOR_INTEL=y +CONFIG_WLAN_VENDOR_INTERSIL=y +CONFIG_HOSTAP=y +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +CONFIG_WLAN_VENDOR_MARVELL=y +# CONFIG_LIBERTAS is not set +# CONFIG_MWIFIEX is not set +CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_WLAN_VENDOR_REALTEK=y +CONFIG_WLAN_VENDOR_RSI=y +CONFIG_WLAN_VENDOR_ST=y +CONFIG_WLAN_VENDOR_TI=y +CONFIG_WLAN_VENDOR_ZYDAS=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_ISDN is not set +# CONFIG_NVM is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVMEM=y +# CONFIG_DEVKMEM is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set +CONFIG_SERIAL_FULLHAN=y +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +# CONFIG_SERIAL_ST_ASC is not set +# CONFIG_SERIAL_STM32 is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_XILLYBUS is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_SMBUS is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_FH_INTERRUPT=y +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_EMEV2 is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_RK3X is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_DESIGNWARE is not set +CONFIG_SPI_FH=y + +# +# spi multi wire support +# +CONFIG_SPI_USE_MULTI_WIRE=y +CONFIG_SPI_SWAP_MAX_DATA_WIDTH=16 +# CONFIG_SPI_USE_DMA is not set +CONFIG_SPI_TINY_MEM=y +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +# CONFIG_PTP_1588_CLOCK is not set + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_PINCTRL=y + +# +# Pin controllers +# +CONFIG_PINMUX=y +CONFIG_PINCTRL_FULLHAN=y +# CONFIG_PINCTRL_AMD is not set +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_GPIOLIB=y +CONFIG_OF_GPIO=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers +# +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ALTERA is not set +CONFIG_GPIO_FH=y +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_EM is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_MPC8XXX is not set +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_ZEVIO is not set +# CONFIG_GPIO_ZX is not set + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_TPIC2810 is not set +# CONFIG_GPIO_TS4900 is not set + +# +# MFD GPIO expanders +# +# CONFIG_HTC_EGPIO is not set + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set + +# +# SPI or I2C GPIO expanders +# +# CONFIG_GPIO_MCP23S08 is not set + +# +# USB GPIO expanders +# +# CONFIG_W1 is not set +# CONFIG_POWER_AVS is not set +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_BRCMKONA is not set +# CONFIG_POWER_RESET_GPIO is not set +# CONFIG_POWER_RESET_GPIO_RESTART is not set +CONFIG_POWER_RESET_FH=y +# CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_RESTART is not set +# CONFIG_POWER_RESET_SYSCON is not set +# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_CORE is not set +# CONFIG_WATCHDOG_NOWAYOUT is not set +# CONFIG_WATCHDOG_SYSFS is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_GPIO_WATCHDOG is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_FH_WATCHDOG=y +# CONFIG_MEN_A21_WDT is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set + +# +# Watchdog Pretimeout Governors +# +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_ACT8945A is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_EXYNOS_LPASS is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_INTEL_SOC_PMIC is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77620 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_PM8921_CORE is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RTSX_USB is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RK808 is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set +# CONFIG_SOUND is not set + +# +# HID support +# +# CONFIG_HID is not set + +# +# USB HID support +# +# CONFIG_USB_HID is not set +# CONFIG_HID_PID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +CONFIG_USB_DYNAMIC_MINORS=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +CONFIG_USB_WUSB_CBAF=y +# CONFIG_USB_WUSB_CBAF_DEBUG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_MAX3421_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +CONFIG_USB_WDM=y +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_DWC3 is not set +CONFIG_USB_DWC2=y +CONFIG_USB_DWC2_HOST=y + +# +# Gadget/Dual-role mode requires USB Gadget support to be enabled +# +# CONFIG_USB_DWC2_VBVALIDOVEN is not set +# CONFIG_USB_DWC2_DEBUG is not set +# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set +# CONFIG_USB_DWC2_HOST_DMA_DESC_NUM_DYNAMIC is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set + +# +# USB Physical Layer drivers +# +# CONFIG_USB_PHY is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ULPI is not set +# CONFIG_USB_GADGET is not set +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_UWB is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_PWRSEQ_EMMC=y +CONFIG_PWRSEQ_SIMPLE=y + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SPI is not set +CONFIG_MMC_FH=y +CONFIG_MMC_FH_IDMAC=y +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_MTK is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +# CONFIG_EDAC is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_HYM8563 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV8803 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6916 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RX6110 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_MCP795 is not set +# CONFIG_RTC_I2C_AND_SPI is not set + +# +# SPI and I2C RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_ZYNQMP is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_SNVS is not set +CONFIG_RTC_DRV_FH=y +CONFIG_USE_TSENSOR=y +# CONFIG_USE_TSENSOR_OFFSET is not set + +# +# HID Sensor RTC drivers +# +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +# CONFIG_DW_DMAC is not set +# CONFIG_FH_DMAC is not set +CONFIG_FH_AXI_DMAC=y +CONFIG_FH_DMAC_MISC=y + +# +# dma tinyconfig +# +CONFIG_CHANNEL_ALLOC_MEM_CLASSICS=y +CONFIG_CHANNEL_ALLOC_DESC_NUM=32 +# CONFIG_FSL_EDMA is not set +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_NBPFAXI_DMA is not set +# CONFIG_QCOM_HIDMA_MGMT is not set +# CONFIG_QCOM_HIDMA is not set + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set + +# +# DMABUF options +# +# CONFIG_SYNC_FILE is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VIRT_DRIVERS is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_STAGING is not set +# CONFIG_GOLDFISH is not set +# CONFIG_CHROME_PLATFORMS is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI514 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CDCE925 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_CLK_QORIQ is not set +# CONFIG_COMMON_CLK_NXP is not set +# CONFIG_COMMON_CLK_PWM is not set +# CONFIG_COMMON_CLK_PXA is not set +# CONFIG_COMMON_CLK_PIC32 is not set + +# +# Hardware Spinlock drivers +# + +# +# Clock Source drivers +# +CONFIG_CLKSRC_OF=y +CONFIG_CLKSRC_PROBE=y +CONFIG_FULLHAN_TIMER=y +# CONFIG_FH_SIMPLE_TIMER is not set +# CONFIG_ARM_TIMER_SP804 is not set +# CONFIG_ATMEL_PIT is not set +# CONFIG_SH_TIMER_CMT is not set +# CONFIG_SH_TIMER_MTU2 is not set +# CONFIG_SH_TIMER_TMU is not set +# CONFIG_EM_TIMER_STI is not set +# CONFIG_MAILBOX is not set +# CONFIG_IOMMU_SUPPORT is not set + +# +# Remoteproc drivers +# +# CONFIG_STE_MODEM_RPROC is not set + +# +# Rpmsg drivers +# + +# +# SOC (System On Chip) specific Drivers +# + +# +# Broadcom SoC drivers +# +# CONFIG_SOC_BRCMSTB is not set +# CONFIG_SUNXI_SRAM is not set +# CONFIG_SOC_TI is not set +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +CONFIG_PWM=y +# CONFIG_PWM_SYSFS is not set +# CONFIG_DEBUG_PWM_FS is not set +CONFIG_PWM_FULLHAN=y +CONFIG_FH_PWM_NUM=2 +# CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_PCA9685 is not set +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC_MAX_NR=1 +CONFIG_FULLHAN_INTC=y +# CONFIG_IPACK_BUS is not set +# CONFIG_RESET_CONTROLLER is not set +# CONFIG_FMC is not set + +# +# PHY Subsystem +# +# CONFIG_GENERIC_PHY is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_FH_USB2_PHY is not set +# CONFIG_PHY_SAMSUNG_USB2 is not set +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +# CONFIG_RAS is not set + +# +# Android +# +# CONFIG_ANDROID is not set +# CONFIG_NVMEM is not set +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set + +# +# FPGA Configuration Support +# +# CONFIG_FPGA is not set + +# +# Firmware Drivers +# +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_FW_CFG_SYSFS is not set + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_FILE_LOCKING=y +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +# CONFIG_OVERLAY_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_PROC_CHILDREN is not set +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_WRITEBUFFER is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V2 is not set +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_SWAP is not set +# CONFIG_ROOT_NFS is not set +# CONFIG_NFSD is not set +CONFIG_GRACE_PERIOD=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_DYNAMIC_DEBUG is not set + +# +# Compile-time checks and compiler options +# +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_OPTIMIZE_INLINING=y +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_DEBUG_KERNEL is not set + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_MEMORY_INIT is not set + +# +# Debug Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_SCHED_INFO is not set +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +# CONFIG_STACKTRACE is not set + +# +# RCU Debugging +# +# CONFIG_PROVE_RCU is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_TORTURE_TEST is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_HWLAT_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_FTRACE_SYSCALLS is not set +# CONFIG_TRACER_SNAPSHOT is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_PROBE_EVENTS is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +CONFIG_TRACING_EVENTS_GPIO=y + +# +# Runtime Testing +# +# CONFIG_LKDTM is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_HASH is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_MEMTEST is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set +# CONFIG_UBSAN is not set +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +# CONFIG_STRICT_DEVMEM is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_UART_8250 is not set +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_DEBUG_SET_MODULE_RONX is not set +# CONFIG_CORESIGHT is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_BIG_KEYS is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEY_DH_OPERATIONS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y +# CONFIG_HARDENED_USERCOPY is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_KPP2=y +# CONFIG_CRYPTO_RSA is not set +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_ECDH is not set +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_MCRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_KEYWRAP is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_CMAC is not set +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +CONFIG_CRYPTO_MICHAEL_MIC=y +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +CONFIG_CRYPTO_SHA256=y +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG is not set +# CONFIG_CRYPTO_JITTERENTROPY is not set +CONFIG_CRYPTO_USER_API=y +# CONFIG_CRYPTO_USER_API_HASH is not set +CONFIG_CRYPTO_USER_API_SKCIPHER=y +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_DEV_FH_AES=y +# CONFIG_CRYPTO_FH_AES_SUPPORT_DIRECT_MEM is not set +# CONFIG_FH_AES_SELF_TEST is not set +# CONFIG_ASYMMETRIC_KEY_TYPE is not set + +# +# Certificates for signature checking +# +# CONFIG_ARM_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_HAVE_ARCH_BITREVERSE is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_XZ=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y +# CONFIG_CORDIC is not set +# CONFIG_DDR is not set +# CONFIG_IRQ_POLL is not set +CONFIG_LIBFDT=y +# CONFIG_SG_SPLIT is not set +# CONFIG_SG_POOL is not set +# CONFIG_ARCH_HAS_SG_CHAIN is not set +CONFIG_SBITMAP=y +# CONFIG_VIRTUALIZATION is not set diff --git a/arch/arm/configs/fh8858v200_defconfig b/arch/arm/configs/fh8858v200_defconfig new file mode 100644 index 00000000..00399a14 --- /dev/null +++ b/arch/arm/configs/fh8858v200_defconfig @@ -0,0 +1,2253 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 4.9.129 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y + +# +# General setup +# +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_TINY_KERNEL=y +CONFIG_NTP=y +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_LZMA is not set +CONFIG_KERNEL_XZ=y +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_NO_COMPRESS is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_FHANDLE is not set +CONFIG_USELIB=y +# CONFIG_AUDIT is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_IRQ_DOMAIN=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_GENERIC_CLOCKEVENTS=y + +# +# Timers subsystem +# +CONFIG_HZ_PERIODIC=y +# CONFIG_NO_HZ_IDLE is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set + +# +# RCU Subsystem +# +CONFIG_TINY_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +# CONFIG_TASKS_RCU is not set +# CONFIG_RCU_STALL_COMMON is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_EXPEDITE_BOOT is not set +# CONFIG_BUILD_BIN2C is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_NMI_LOG_BUF_SHIFT=13 +CONFIG_GENERIC_SCHED_CLOCK=y +# CONFIG_CGROUPS is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SCHED_DL is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="usr/rootfs.cpio.xz" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +CONFIG_RD_XZ=y +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_HAVE_UID16=y +CONFIG_BPF=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +CONFIG_SYSFS_SYSCALL=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set +CONFIG_KALLSYMS_BASE_RELATIVE=y +CONFIG_PRINTK=y +CONFIG_PRINTK_NMI=y +# CONFIG_BUG is not set +# CONFIG_ELF_CORE is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +# CONFIG_BPF_SYSCALL is not set +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_ADVISE_SYSCALLS=y +# CONFIG_USERFAULTFD is not set +CONFIG_MEMBARRIER=y +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SYSTEM_DATA_VERIFICATION is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_UPROBES is not set +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_GCC_PLUGINS=y +# CONFIG_GCC_PLUGINS is not set +CONFIG_HAVE_CC_STACKPROTECTOR=y +# CONFIG_CC_STACKPROTECTOR is not set +CONFIG_CC_STACKPROTECTOR_NONE=y +# CONFIG_CC_STACKPROTECTOR_REGULAR is not set +# CONFIG_CC_STACKPROTECTOR_STRONG is not set +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_EXIT_THREAD=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=8 +CONFIG_ARCH_MMAP_RND_BITS_MAX=16 +CONFIG_ARCH_MMAP_RND_BITS=8 +# CONFIG_HAVE_ARCH_HASH is not set +# CONFIG_ISA_BUS_API is not set +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OLD_SIGACTION=y +# CONFIG_CPU_NO_EFFICIENT_FFS is not set +# CONFIG_HAVE_ARCH_VMAP_STACK is not set + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_CMDLINE_PARSER is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_EFI_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_MULTIPLATFORM is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +CONFIG_ARCH_FULLHAN=y +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP1 is not set + +# +# Fullhan platform type +# +# CONFIG_FH_FASTBOOT is not set +# CONFIG_ARCH_FH8833 is not set +# CONFIG_ARCH_FH8856 is not set +# CONFIG_ARCH_FH8852 is not set +# CONFIG_ARCH_FH8626V100 is not set +CONFIG_ARCH_FH885xV200=y +# CONFIG_ARCH_FH865x is not set + +CONFIG_FH_CHIP_NAME="fh8858v200" +# CONFIG_MACH_FH8856V200 is not set +# CONFIG_MACH_FH8852V200 is not set +CONFIG_MACH_FH8858V200=y + +# +# Processor Type +# +CONFIG_CPU_V6=y +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_KUSER_HELPERS=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +# CONFIG_DEBUG_RODATA is not set +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_PJ4B_ERRATA_4742=y +# CONFIG_ARM_ERRATA_326103 is not set +CONFIG_ARM_ERRATA_411920=y +# CONFIG_ARM_ERRATA_364296 is not set + +# +# Bus support +# +# CONFIG_PCI_DOMAINS_GENERIC is not set +# CONFIG_PCI_SYSCALL is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_3G_OPT is not set +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_ARCH_NR_GPIO=0 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ_FIXED=0 +CONFIG_HZ_100=y +# CONFIG_HZ_200 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_500 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +# CONFIG_SCHED_HRTICK is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +# CONFIG_HIGHMEM is not set +CONFIG_CPU_SW_DOMAIN_PAN=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +# CONFIG_ARM_MODULE_PLTS is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_NO_BOOTMEM=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_CLEANCACHE is not set +# CONFIG_CMA is not set +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +# CONFIG_ZSMALLOC is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +CONFIG_SWIOTLB=y +CONFIG_IOMMU_HELPER=y +# CONFIG_PARAVIRT is not set +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set + +# +# Boot options +# +# CONFIG_USE_OF is not set +CONFIG_ATAGS=y +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_AUTO_ZRELADDR=y + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# CPU Idle +# +# CONFIG_CPU_IDLE is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ELFCORE=y +CONFIG_BINFMT_SCRIPT=y +# CONFIG_BINFMT_FLAT is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y + +# +# Power management options +# +# CONFIG_SUSPEND is not set +# CONFIG_PM is not set +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_NET_IP_TUNNEL=y +# CONFIG_IP_MROUTE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_NET_IPVTI is not set +# CONFIG_NET_UDP_TUNNEL is not set +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_INET_DIAG_DESTROY is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +# CONFIG_IPV6_VTI is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_FOU is not set +# CONFIG_IPV6_FOU_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NET_PTP_CLASSIFY is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +CONFIG_HAVE_NET_DSA=y +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_MPLS is not set +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_NET_NCSI is not set +# CONFIG_SOCK_CGROUP_DATA is not set +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +# CONFIG_BPF_JIT is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +# CONFIG_STREAM_PARSER is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=y +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +# CONFIG_CFG80211_DEFAULT_PS is not set +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_CFG80211_WEXT=y +CONFIG_LIB80211=y +CONFIG_LIB80211_CRYPT_WEP=y +CONFIG_LIB80211_CRYPT_CCMP=y +CONFIG_LIB80211_CRYPT_TKIP=y +# CONFIG_LIB80211_DEBUG is not set +# CONFIG_MAC80211 is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +# CONFIG_RFKILL_INPUT is not set +# CONFIG_RFKILL_GPIO is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_LWTUNNEL is not set +CONFIG_DST_CACHE=y +# CONFIG_NET_DEVLINK is not set +CONFIG_MAY_USE_DEVLINK=y +CONFIG_HAVE_CBPF_JIT=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +# CONFIG_DMA_SHARED_BUFFER is not set + +# +# Bus devices +# +# CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR & LPDDR2 PCM memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_LPDDR2_NVM is not set +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_MT81xx_NOR is not set +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MTD_UBI is not set +# CONFIG_OF is not set +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_NVME_TARGET is not set + +# +# Misc devices +# +# CONFIG_FH_DW_I2S is not set +# CONFIG_FH_ACW is not set +CONFIG_FH_SADC_V3=y +CONFIG_FH_EFUSE=y +# CONFIG_FH_L2MEM is not set +CONFIG_FH_PINCTRL_MISC_DEV=y +CONFIG_FH_CLK_MISC=y +CONFIG_FH_PERF_MON=y +# CONFIG_FH_TSENSOR is not set +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_SRAM is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set + +# +# Intel MIC Bus Driver +# + +# +# SCIF Bus Driver +# + +# +# VOP Bus Driver +# + +# +# Intel MIC Host Driver +# + +# +# Intel MIC Card Driver +# + +# +# SCIF Driver +# + +# +# Intel MIC Coprocessor State Management (COSM) Drivers +# + +# +# VOP Driver +# +# CONFIG_ECHO is not set +# CONFIG_CXL_BASE is not set +# CONFIG_CXL_AFU_DRIVER_OPS is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_MACSEC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_TUN is not set +# CONFIG_TUN_VNET_CROSS_LE is not set +# CONFIG_VETH is not set +# CONFIG_NLMON is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +CONFIG_ETHERNET=y +# CONFIG_ALTERA_TSE is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_NET_VENDOR_FULLHAN=y +CONFIG_FH_GMAC=y +CONFIG_FH_GMAC_DA=y +CONFIG_PHYLIB=y +CONFIG_SWPHY=y + +# +# MDIO bus device drivers +# +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_BITBANG is not set + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_AT803X_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +CONFIG_FIXED_PHY=y +# CONFIG_ICPLUS_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +CONFIG_USB_NET_DRIVERS=y +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_RTL8152 is not set +# CONFIG_USB_LAN78XX is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_IPHETH is not set +CONFIG_WLAN=y +CONFIG_WLAN_VENDOR_ADMTEK=y +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +# CONFIG_ATH6KL is not set +CONFIG_WLAN_VENDOR_ATMEL=y +CONFIG_WLAN_VENDOR_BROADCOM=y +# CONFIG_BRCMFMAC is not set +CONFIG_WLAN_VENDOR_CISCO=y +CONFIG_WLAN_VENDOR_INTEL=y +CONFIG_WLAN_VENDOR_INTERSIL=y +CONFIG_HOSTAP=y +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +CONFIG_WLAN_VENDOR_MARVELL=y +# CONFIG_LIBERTAS is not set +# CONFIG_MWIFIEX is not set +CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_WLAN_VENDOR_REALTEK=y +CONFIG_WLAN_VENDOR_RSI=y +CONFIG_WLAN_VENDOR_ST=y +CONFIG_WLAN_VENDOR_TI=y +CONFIG_WLAN_VENDOR_ZYDAS=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_ISDN is not set +# CONFIG_NVM is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVMEM=y +# CONFIG_DEVKMEM is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set +CONFIG_SERIAL_FULLHAN=y +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_ST_ASC is not set +# CONFIG_SERIAL_STM32 is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_SMBUS is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_FH_INTERRUPT=y +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_EMEV2 is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_DESIGNWARE is not set +CONFIG_SPI_FH=y +# CONFIG_SPI_FH_SLAVE is not set + +# +# spi multi wire support +# +CONFIG_SPI_USE_MULTI_WIRE=y +CONFIG_SPI_SWAP_MAX_DATA_WIDTH=16 +# CONFIG_SPI_USE_DMA is not set +CONFIG_SPI_TINY_MEM=y +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +# CONFIG_PTP_1588_CLOCK is not set + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers +# +CONFIG_GPIO_FH=y +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_MPC8XXX is not set +# CONFIG_GPIO_ZX is not set + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_TPIC2810 is not set +# CONFIG_GPIO_TS4900 is not set + +# +# MFD GPIO expanders +# +# CONFIG_HTC_EGPIO is not set + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set + +# +# SPI or I2C GPIO expanders +# + +# +# USB GPIO expanders +# +# CONFIG_W1 is not set +# CONFIG_POWER_AVS is not set +# CONFIG_POWER_RESET is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_CORE is not set +# CONFIG_WATCHDOG_NOWAYOUT is not set +# CONFIG_WATCHDOG_SYSFS is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_FH_WATCHDOG=y +# CONFIG_MEN_A21_WDT is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set + +# +# Watchdog Pretimeout Governors +# +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_EXYNOS_LPASS is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_INTEL_SOC_PMIC is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_PM8921_CORE is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RTSX_USB is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set +# CONFIG_SOUND is not set + +# +# HID support +# +# CONFIG_HID is not set + +# +# USB HID support +# +# CONFIG_USB_HID is not set +# CONFIG_HID_PID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +CONFIG_USB_DYNAMIC_MINORS=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +CONFIG_USB_WUSB_CBAF=y +# CONFIG_USB_WUSB_CBAF_DEBUG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_MAX3421_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +CONFIG_USB_WDM=y +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_DWC3 is not set +CONFIG_USB_DWC2=y +CONFIG_USB_DWC2_HOST=y + +# +# Gadget/Dual-role mode requires USB Gadget support to be enabled +# +# CONFIG_USB_DWC2_VBVALIDOVEN is not set +# CONFIG_USB_DWC2_DEBUG is not set +# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set +# CONFIG_USB_DWC2_HOST_DMA_DESC_NUM_DYNAMIC is not set +CONFIG_USB_DWC2_DMA=y +# CONFIG_USB_DWC2_DMA_DESC is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set + +# +# USB Physical Layer drivers +# +# CONFIG_USB_PHY is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ULPI is not set +# CONFIG_USB_GADGET is not set +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_UWB is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SPI is not set +CONFIG_MMC_FH=y +CONFIG_MMC_FH_IDMAC=y +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_MTK is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +# CONFIG_EDAC is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV8803 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6916 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RX6110 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_MCP795 is not set +# CONFIG_RTC_I2C_AND_SPI is not set + +# +# SPI and I2C RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_FH=y +CONFIG_USE_TSENSOR=y +# CONFIG_USE_TSENSOR_OFFSET is not set + +# +# HID Sensor RTC drivers +# +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +# CONFIG_DW_DMAC is not set +CONFIG_CHANNEL_ALLOC_MEM_CLASSICS=y +# CONFIG_FH_DMAC is not set +CONFIG_FH_AXI_DMAC=y +CONFIG_FH_DMAC_MISC=y + +# +# dma tinyconfig +# +CONFIG_CHANNEL_ALLOC_DESC_NUM=32 +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_NBPFAXI_DMA is not set +# CONFIG_QCOM_HIDMA_MGMT is not set +# CONFIG_QCOM_HIDMA is not set + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set + +# +# DMABUF options +# +# CONFIG_SYNC_FILE is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VIRT_DRIVERS is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_STAGING is not set +# CONFIG_GOLDFISH is not set +# CONFIG_CHROME_PLATFORMS is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_COMMON_CLK_NXP is not set +# CONFIG_COMMON_CLK_PWM is not set +# CONFIG_COMMON_CLK_PXA is not set +# CONFIG_COMMON_CLK_PIC32 is not set + +# +# Hardware Spinlock drivers +# + +# +# Clock Source drivers +# +CONFIG_FULLHAN_TIMER=y +# CONFIG_FH_SIMPLE_TIMER is not set +# CONFIG_ARM_TIMER_SP804 is not set +# CONFIG_ATMEL_PIT is not set +# CONFIG_SH_TIMER_CMT is not set +# CONFIG_SH_TIMER_MTU2 is not set +# CONFIG_SH_TIMER_TMU is not set +# CONFIG_EM_TIMER_STI is not set +# CONFIG_MAILBOX is not set +# CONFIG_IOMMU_SUPPORT is not set + +# +# Remoteproc drivers +# +# CONFIG_STE_MODEM_RPROC is not set + +# +# Rpmsg drivers +# + +# +# SOC (System On Chip) specific Drivers +# + +# +# Broadcom SoC drivers +# +# CONFIG_SOC_BRCMSTB is not set +# CONFIG_SUNXI_SRAM is not set +# CONFIG_SOC_TI is not set +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +CONFIG_PWM=y +# CONFIG_PWM_SYSFS is not set +# CONFIG_DEBUG_PWM_FS is not set +CONFIG_PWM_FULLHAN=y +CONFIG_FH_PWM_NUM=14 +# CONFIG_PWM_PCA9685 is not set +CONFIG_ARM_GIC_MAX_NR=1 +CONFIG_FULLHAN_INTC=y +# CONFIG_IPACK_BUS is not set +# CONFIG_RESET_CONTROLLER is not set +# CONFIG_FMC is not set + +# +# PHY Subsystem +# +# CONFIG_GENERIC_PHY is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_FH_USB2_PHY is not set +# CONFIG_PHY_SAMSUNG_USB2 is not set +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +# CONFIG_RAS is not set + +# +# Android +# +# CONFIG_ANDROID is not set +# CONFIG_NVMEM is not set +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set + +# +# FPGA Configuration Support +# +# CONFIG_FPGA is not set + +# +# Firmware Drivers +# +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_FW_CFG_SYSFS is not set + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_FILE_LOCKING=y +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +# CONFIG_OVERLAY_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_PROC_CHILDREN is not set +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_WRITEBUFFER is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V2 is not set +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_SWAP is not set +# CONFIG_ROOT_NFS is not set +# CONFIG_NFSD is not set +CONFIG_GRACE_PERIOD=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_DYNAMIC_DEBUG is not set + +# +# Compile-time checks and compiler options +# +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_OPTIMIZE_INLINING=y +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_DEBUG_KERNEL is not set + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_MEMORY_INIT is not set + +# +# Debug Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_SCHED_INFO is not set +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +# CONFIG_STACKTRACE is not set + +# +# RCU Debugging +# +# CONFIG_PROVE_RCU is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_TORTURE_TEST is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_HWLAT_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_FTRACE_SYSCALLS is not set +# CONFIG_TRACER_SNAPSHOT is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_PROBE_EVENTS is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +CONFIG_TRACING_EVENTS_GPIO=y + +# +# Runtime Testing +# +# CONFIG_LKDTM is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_HASH is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_MEMTEST is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set +# CONFIG_UBSAN is not set +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +# CONFIG_STRICT_DEVMEM is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_UART_8250 is not set +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_DEBUG_SET_MODULE_RONX is not set +# CONFIG_CORESIGHT is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_BIG_KEYS is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEY_DH_OPERATIONS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y +# CONFIG_HARDENED_USERCOPY is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_KPP2=y +# CONFIG_CRYPTO_RSA is not set +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_ECDH is not set +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_MCRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_KEYWRAP is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_CMAC is not set +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +CONFIG_CRYPTO_MICHAEL_MIC=y +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +CONFIG_CRYPTO_SHA256=y +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG is not set +# CONFIG_CRYPTO_JITTERENTROPY is not set +CONFIG_CRYPTO_USER_API=y +# CONFIG_CRYPTO_USER_API_HASH is not set +CONFIG_CRYPTO_USER_API_SKCIPHER=y +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_FH_CESA is not set +CONFIG_CRYPTO_DEV_FH_AES=y +# CONFIG_CRYPTO_FH_AES_SUPPORT_DIRECT_MEM is not set +# CONFIG_FH_AES_SELF_TEST is not set +# CONFIG_ASYMMETRIC_KEY_TYPE is not set + +# +# Certificates for signature checking +# +# CONFIG_ARM_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_HAVE_ARCH_BITREVERSE is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_XZ=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y +# CONFIG_CORDIC is not set +# CONFIG_DDR is not set +# CONFIG_IRQ_POLL is not set +# CONFIG_SG_SPLIT is not set +# CONFIG_SG_POOL is not set +# CONFIG_ARCH_HAS_SG_CHAIN is not set +CONFIG_SBITMAP=y +# CONFIG_VIRTUALIZATION is not set diff --git a/arch/arm/configs/fh8858v200_of_defconfig b/arch/arm/configs/fh8858v200_of_defconfig new file mode 100644 index 00000000..0905961c --- /dev/null +++ b/arch/arm/configs/fh8858v200_of_defconfig @@ -0,0 +1,2332 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 4.9.129 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y + +# +# General setup +# +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_TINY_KERNEL=y +CONFIG_NTP=y +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_LZMA is not set +CONFIG_KERNEL_XZ=y +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_NO_COMPRESS is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_FHANDLE is not set +CONFIG_USELIB=y +# CONFIG_AUDIT is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_IRQ_DOMAIN=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_GENERIC_CLOCKEVENTS=y + +# +# Timers subsystem +# +CONFIG_HZ_PERIODIC=y +# CONFIG_NO_HZ_IDLE is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set + +# +# RCU Subsystem +# +CONFIG_TINY_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +# CONFIG_TASKS_RCU is not set +# CONFIG_RCU_STALL_COMMON is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_EXPEDITE_BOOT is not set +# CONFIG_BUILD_BIN2C is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_NMI_LOG_BUF_SHIFT=13 +CONFIG_GENERIC_SCHED_CLOCK=y +# CONFIG_CGROUPS is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SCHED_DL is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="usr/rootfs.cpio.xz" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +CONFIG_RD_XZ=y +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_HAVE_UID16=y +CONFIG_BPF=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +CONFIG_SYSFS_SYSCALL=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set +CONFIG_KALLSYMS_BASE_RELATIVE=y +CONFIG_PRINTK=y +CONFIG_PRINTK_NMI=y +# CONFIG_BUG is not set +# CONFIG_ELF_CORE is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +# CONFIG_BPF_SYSCALL is not set +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_ADVISE_SYSCALLS=y +# CONFIG_USERFAULTFD is not set +CONFIG_MEMBARRIER=y +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SYSTEM_DATA_VERIFICATION is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_UPROBES is not set +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_GCC_PLUGINS=y +# CONFIG_GCC_PLUGINS is not set +CONFIG_HAVE_CC_STACKPROTECTOR=y +# CONFIG_CC_STACKPROTECTOR is not set +CONFIG_CC_STACKPROTECTOR_NONE=y +# CONFIG_CC_STACKPROTECTOR_REGULAR is not set +# CONFIG_CC_STACKPROTECTOR_STRONG is not set +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_EXIT_THREAD=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=8 +CONFIG_ARCH_MMAP_RND_BITS_MAX=16 +CONFIG_ARCH_MMAP_RND_BITS=8 +# CONFIG_HAVE_ARCH_HASH is not set +# CONFIG_ISA_BUS_API is not set +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OLD_SIGACTION=y +# CONFIG_CPU_NO_EFFICIENT_FFS is not set +# CONFIG_HAVE_ARCH_VMAP_STACK is not set + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_CMDLINE_PARSER is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_EFI_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_MULTIPLATFORM is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +CONFIG_ARCH_FULLHAN=y +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP1 is not set + +# +# Fullhan platform type +# +# CONFIG_FH_FASTBOOT is not set +# CONFIG_ARCH_FH8833 is not set +# CONFIG_ARCH_FH8856 is not set +# CONFIG_ARCH_FH8626V100 is not set +CONFIG_ARCH_FH885xV200=y +# CONFIG_ARCH_FH865x is not set + +CONFIG_FH_CHIP_NAME="fh8858v200" +CONFIG_MACH_FH8858V200=y +# CONFIG_MACH_FH8852V200 is not set + +# +# Processor Type +# +CONFIG_CPU_V6=y +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_KUSER_HELPERS=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +# CONFIG_DEBUG_RODATA is not set +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_PJ4B_ERRATA_4742=y +# CONFIG_ARM_ERRATA_326103 is not set +CONFIG_ARM_ERRATA_411920=y +# CONFIG_ARM_ERRATA_364296 is not set + +# +# Bus support +# +# CONFIG_PCI_DOMAINS_GENERIC is not set +# CONFIG_PCI_SYSCALL is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_3G_OPT is not set +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_ARCH_NR_GPIO=0 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ_FIXED=0 +CONFIG_HZ_100=y +# CONFIG_HZ_200 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_500 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +# CONFIG_SCHED_HRTICK is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +# CONFIG_HIGHMEM is not set +CONFIG_CPU_SW_DOMAIN_PAN=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +# CONFIG_ARM_MODULE_PLTS is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_NO_BOOTMEM=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_CLEANCACHE is not set +# CONFIG_CMA is not set +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +# CONFIG_ZSMALLOC is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +CONFIG_SWIOTLB=y +CONFIG_IOMMU_HELPER=y +# CONFIG_PARAVIRT is not set +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set + +# +# Boot options +# +CONFIG_USE_OF=y +CONFIG_ATAGS=y +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND=y +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_AUTO_ZRELADDR=y +# CONFIG_EFI is not set + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# CPU Idle +# +# CONFIG_CPU_IDLE is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ELFCORE=y +CONFIG_BINFMT_SCRIPT=y +# CONFIG_BINFMT_FLAT is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y + +# +# Power management options +# +# CONFIG_SUSPEND is not set +# CONFIG_PM is not set +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_NET_IP_TUNNEL=y +# CONFIG_IP_MROUTE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_NET_IPVTI is not set +# CONFIG_NET_UDP_TUNNEL is not set +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_INET_DIAG_DESTROY is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +# CONFIG_IPV6_VTI is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_FOU is not set +# CONFIG_IPV6_FOU_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NET_PTP_CLASSIFY is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +CONFIG_HAVE_NET_DSA=y +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_MPLS is not set +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_NET_NCSI is not set +# CONFIG_SOCK_CGROUP_DATA is not set +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +# CONFIG_BPF_JIT is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +# CONFIG_STREAM_PARSER is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=y +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +# CONFIG_CFG80211_DEFAULT_PS is not set +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_CFG80211_WEXT=y +CONFIG_LIB80211=y +CONFIG_LIB80211_CRYPT_WEP=y +CONFIG_LIB80211_CRYPT_CCMP=y +CONFIG_LIB80211_CRYPT_TKIP=y +# CONFIG_LIB80211_DEBUG is not set +# CONFIG_MAC80211 is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +# CONFIG_RFKILL_INPUT is not set +# CONFIG_RFKILL_GPIO is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_LWTUNNEL is not set +CONFIG_DST_CACHE=y +# CONFIG_NET_DEVLINK is not set +CONFIG_MAY_USE_DEVLINK=y +CONFIG_HAVE_CBPF_JIT=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +# CONFIG_DMA_SHARED_BUFFER is not set + +# +# Bus devices +# +# CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_VEXPRESS_CONFIG is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR & LPDDR2 PCM memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_LPDDR2_NVM is not set +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_MT81xx_NOR is not set +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_MTD_UBI is not set +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_MDIO=y +CONFIG_OF_RESERVED_MEM=y +# CONFIG_OF_OVERLAY is not set +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_NVME_TARGET is not set + +# +# Misc devices +# +# CONFIG_FH_DW_I2S is not set +# CONFIG_FH_ACW is not set +CONFIG_FH_SADC_V3=y +CONFIG_FH_EFUSE=y +# CONFIG_FH_L2MEM is not set +CONFIG_FH_CLK_MISC=y +CONFIG_FH_PERF_MON=y +# CONFIG_FH_TSENSOR is not set +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_SRAM is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set + +# +# Intel MIC Bus Driver +# + +# +# SCIF Bus Driver +# + +# +# VOP Bus Driver +# + +# +# Intel MIC Host Driver +# + +# +# Intel MIC Card Driver +# + +# +# SCIF Driver +# + +# +# Intel MIC Coprocessor State Management (COSM) Drivers +# + +# +# VOP Driver +# +# CONFIG_ECHO is not set +# CONFIG_CXL_BASE is not set +# CONFIG_CXL_AFU_DRIVER_OPS is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_MACSEC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_TUN is not set +# CONFIG_TUN_VNET_CROSS_LE is not set +# CONFIG_VETH is not set +# CONFIG_NLMON is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +CONFIG_ETHERNET=y +# CONFIG_ALTERA_TSE is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_NET_VENDOR_FULLHAN=y +CONFIG_FH_GMAC=y +CONFIG_FH_GMAC_DA=y + +# +# fh inside or outside phy sel +# +CONFIG_PHYLIB=y +CONFIG_SWPHY=y + +# +# MDIO bus device drivers +# +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MDIO_HISI_FEMAC is not set + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_AT803X_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +CONFIG_FIXED_PHY=y +# CONFIG_ICPLUS_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +CONFIG_USB_NET_DRIVERS=y +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_RTL8152 is not set +# CONFIG_USB_LAN78XX is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_IPHETH is not set +CONFIG_WLAN=y +CONFIG_WLAN_VENDOR_ADMTEK=y +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +# CONFIG_ATH6KL is not set +CONFIG_WLAN_VENDOR_ATMEL=y +CONFIG_WLAN_VENDOR_BROADCOM=y +# CONFIG_BRCMFMAC is not set +CONFIG_WLAN_VENDOR_CISCO=y +CONFIG_WLAN_VENDOR_INTEL=y +CONFIG_WLAN_VENDOR_INTERSIL=y +CONFIG_HOSTAP=y +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +CONFIG_WLAN_VENDOR_MARVELL=y +# CONFIG_LIBERTAS is not set +# CONFIG_MWIFIEX is not set +CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_WLAN_VENDOR_REALTEK=y +CONFIG_WLAN_VENDOR_RSI=y +CONFIG_WLAN_VENDOR_ST=y +CONFIG_WLAN_VENDOR_TI=y +CONFIG_WLAN_VENDOR_ZYDAS=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_ISDN is not set +# CONFIG_NVM is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVMEM=y +# CONFIG_DEVKMEM is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set +CONFIG_SERIAL_FULLHAN=y +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +# CONFIG_SERIAL_ST_ASC is not set +# CONFIG_SERIAL_STM32 is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_XILLYBUS is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_SMBUS is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_FH_INTERRUPT=y +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_EMEV2 is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_RK3X is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_DESIGNWARE is not set +CONFIG_SPI_FH=y + +# +# spi multi wire support +# +CONFIG_SPI_USE_MULTI_WIRE=y +CONFIG_SPI_SWAP_MAX_DATA_WIDTH=16 +# CONFIG_SPI_USE_DMA is not set +CONFIG_SPI_TINY_MEM=y +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +# CONFIG_PTP_1588_CLOCK is not set + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_PINCTRL=y + +# +# Pin controllers +# +CONFIG_PINMUX=y +CONFIG_PINCTRL_FULLHAN=y +# CONFIG_PINCTRL_AMD is not set +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_GPIOLIB=y +CONFIG_OF_GPIO=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers +# +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ALTERA is not set +CONFIG_GPIO_FH=y +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_EM is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_MPC8XXX is not set +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_ZEVIO is not set +# CONFIG_GPIO_ZX is not set + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_TPIC2810 is not set +# CONFIG_GPIO_TS4900 is not set + +# +# MFD GPIO expanders +# +# CONFIG_HTC_EGPIO is not set + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set + +# +# SPI or I2C GPIO expanders +# +# CONFIG_GPIO_MCP23S08 is not set + +# +# USB GPIO expanders +# +# CONFIG_W1 is not set +# CONFIG_POWER_AVS is not set +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_BRCMKONA is not set +# CONFIG_POWER_RESET_GPIO is not set +# CONFIG_POWER_RESET_GPIO_RESTART is not set +CONFIG_POWER_RESET_FH=y +# CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_RESTART is not set +# CONFIG_POWER_RESET_SYSCON is not set +# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_CORE is not set +# CONFIG_WATCHDOG_NOWAYOUT is not set +# CONFIG_WATCHDOG_SYSFS is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_GPIO_WATCHDOG is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_FH_WATCHDOG=y +# CONFIG_MEN_A21_WDT is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set + +# +# Watchdog Pretimeout Governors +# +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_ACT8945A is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_EXYNOS_LPASS is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_INTEL_SOC_PMIC is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77620 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_PM8921_CORE is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RTSX_USB is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RK808 is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set +# CONFIG_SOUND is not set + +# +# HID support +# +# CONFIG_HID is not set + +# +# USB HID support +# +# CONFIG_USB_HID is not set +# CONFIG_HID_PID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +CONFIG_USB_DYNAMIC_MINORS=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +CONFIG_USB_WUSB_CBAF=y +# CONFIG_USB_WUSB_CBAF_DEBUG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_MAX3421_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +CONFIG_USB_WDM=y +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_DWC3 is not set +CONFIG_USB_DWC2=y +CONFIG_USB_DWC2_HOST=y + +# +# Gadget/Dual-role mode requires USB Gadget support to be enabled +# +# CONFIG_USB_DWC2_VBVALIDOVEN is not set +# CONFIG_USB_DWC2_DEBUG is not set +# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set +# CONFIG_USB_DWC2_HOST_DMA_DESC_NUM_DYNAMIC is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set + +# +# USB Physical Layer drivers +# +# CONFIG_USB_PHY is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ULPI is not set +# CONFIG_USB_GADGET is not set +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_UWB is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_PWRSEQ_EMMC=y +CONFIG_PWRSEQ_SIMPLE=y + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SPI is not set +CONFIG_MMC_FH=y +CONFIG_MMC_FH_IDMAC=y +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_MTK is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +# CONFIG_EDAC is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_HYM8563 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV8803 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6916 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RX6110 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_MCP795 is not set +# CONFIG_RTC_I2C_AND_SPI is not set + +# +# SPI and I2C RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_ZYNQMP is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_SNVS is not set +CONFIG_RTC_DRV_FH=y +CONFIG_USE_TSENSOR=y +# CONFIG_USE_TSENSOR_OFFSET is not set + +# +# HID Sensor RTC drivers +# +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +# CONFIG_DW_DMAC is not set +# CONFIG_FH_DMAC is not set +CONFIG_FH_AXI_DMAC=y +CONFIG_FH_DMAC_MISC=y + +# +# dma tinyconfig +# +CONFIG_CHANNEL_ALLOC_MEM_CLASSICS=y +CONFIG_CHANNEL_ALLOC_DESC_NUM=32 +# CONFIG_FSL_EDMA is not set +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_NBPFAXI_DMA is not set +# CONFIG_QCOM_HIDMA_MGMT is not set +# CONFIG_QCOM_HIDMA is not set + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set + +# +# DMABUF options +# +# CONFIG_SYNC_FILE is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VIRT_DRIVERS is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_STAGING is not set +# CONFIG_GOLDFISH is not set +# CONFIG_CHROME_PLATFORMS is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI514 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CDCE925 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_CLK_QORIQ is not set +# CONFIG_COMMON_CLK_NXP is not set +# CONFIG_COMMON_CLK_PWM is not set +# CONFIG_COMMON_CLK_PXA is not set +# CONFIG_COMMON_CLK_PIC32 is not set + +# +# Hardware Spinlock drivers +# + +# +# Clock Source drivers +# +CONFIG_CLKSRC_OF=y +CONFIG_CLKSRC_PROBE=y +CONFIG_FULLHAN_TIMER=y +# CONFIG_FH_SIMPLE_TIMER is not set +# CONFIG_ARM_TIMER_SP804 is not set +# CONFIG_ATMEL_PIT is not set +# CONFIG_SH_TIMER_CMT is not set +# CONFIG_SH_TIMER_MTU2 is not set +# CONFIG_SH_TIMER_TMU is not set +# CONFIG_EM_TIMER_STI is not set +# CONFIG_MAILBOX is not set +# CONFIG_IOMMU_SUPPORT is not set + +# +# Remoteproc drivers +# +# CONFIG_STE_MODEM_RPROC is not set + +# +# Rpmsg drivers +# + +# +# SOC (System On Chip) specific Drivers +# + +# +# Broadcom SoC drivers +# +# CONFIG_SOC_BRCMSTB is not set +# CONFIG_SUNXI_SRAM is not set +# CONFIG_SOC_TI is not set +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +CONFIG_PWM=y +# CONFIG_PWM_SYSFS is not set +# CONFIG_DEBUG_PWM_FS is not set +CONFIG_PWM_FULLHAN=y +CONFIG_FH_PWM_NUM=2 +# CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_PCA9685 is not set +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC_MAX_NR=1 +CONFIG_FULLHAN_INTC=y +# CONFIG_IPACK_BUS is not set +# CONFIG_RESET_CONTROLLER is not set +# CONFIG_FMC is not set + +# +# PHY Subsystem +# +# CONFIG_GENERIC_PHY is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_FH_USB2_PHY is not set +# CONFIG_PHY_SAMSUNG_USB2 is not set +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +# CONFIG_RAS is not set + +# +# Android +# +# CONFIG_ANDROID is not set +# CONFIG_NVMEM is not set +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set + +# +# FPGA Configuration Support +# +# CONFIG_FPGA is not set + +# +# Firmware Drivers +# +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_FW_CFG_SYSFS is not set + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_FILE_LOCKING=y +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +# CONFIG_OVERLAY_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_PROC_CHILDREN is not set +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_WRITEBUFFER is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V2 is not set +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_SWAP is not set +# CONFIG_ROOT_NFS is not set +# CONFIG_NFSD is not set +CONFIG_GRACE_PERIOD=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_DYNAMIC_DEBUG is not set + +# +# Compile-time checks and compiler options +# +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_OPTIMIZE_INLINING=y +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_DEBUG_KERNEL is not set + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_MEMORY_INIT is not set + +# +# Debug Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_SCHED_INFO is not set +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +# CONFIG_STACKTRACE is not set + +# +# RCU Debugging +# +# CONFIG_PROVE_RCU is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_TORTURE_TEST is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_HWLAT_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_FTRACE_SYSCALLS is not set +# CONFIG_TRACER_SNAPSHOT is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_PROBE_EVENTS is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +CONFIG_TRACING_EVENTS_GPIO=y + +# +# Runtime Testing +# +# CONFIG_LKDTM is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_HASH is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_MEMTEST is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set +# CONFIG_UBSAN is not set +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +# CONFIG_STRICT_DEVMEM is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_UART_8250 is not set +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_DEBUG_SET_MODULE_RONX is not set +# CONFIG_CORESIGHT is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_BIG_KEYS is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEY_DH_OPERATIONS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y +# CONFIG_HARDENED_USERCOPY is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_KPP2=y +# CONFIG_CRYPTO_RSA is not set +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_ECDH is not set +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_MCRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_KEYWRAP is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_CMAC is not set +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +CONFIG_CRYPTO_MICHAEL_MIC=y +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +CONFIG_CRYPTO_SHA256=y +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG is not set +# CONFIG_CRYPTO_JITTERENTROPY is not set +CONFIG_CRYPTO_USER_API=y +# CONFIG_CRYPTO_USER_API_HASH is not set +CONFIG_CRYPTO_USER_API_SKCIPHER=y +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_DEV_FH_AES=y +# CONFIG_CRYPTO_FH_AES_SUPPORT_DIRECT_MEM is not set +# CONFIG_FH_AES_SELF_TEST is not set +# CONFIG_ASYMMETRIC_KEY_TYPE is not set + +# +# Certificates for signature checking +# +# CONFIG_ARM_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_HAVE_ARCH_BITREVERSE is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_XZ=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y +# CONFIG_CORDIC is not set +# CONFIG_DDR is not set +# CONFIG_IRQ_POLL is not set +CONFIG_LIBFDT=y +# CONFIG_SG_SPLIT is not set +# CONFIG_SG_POOL is not set +# CONFIG_ARCH_HAS_SG_CHAIN is not set +CONFIG_SBITMAP=y +# CONFIG_VIRTUALIZATION is not set diff --git a/arch/arm/configs/fh8858v210_defconfig b/arch/arm/configs/fh8858v210_defconfig new file mode 100644 index 00000000..a84c57f6 --- /dev/null +++ b/arch/arm/configs/fh8858v210_defconfig @@ -0,0 +1,2253 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 4.9.129 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y + +# +# General setup +# +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_TINY_KERNEL=y +CONFIG_NTP=y +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_LZMA is not set +CONFIG_KERNEL_XZ=y +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_NO_COMPRESS is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_FHANDLE is not set +CONFIG_USELIB=y +# CONFIG_AUDIT is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_IRQ_DOMAIN=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_GENERIC_CLOCKEVENTS=y + +# +# Timers subsystem +# +CONFIG_HZ_PERIODIC=y +# CONFIG_NO_HZ_IDLE is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set + +# +# RCU Subsystem +# +CONFIG_TINY_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +# CONFIG_TASKS_RCU is not set +# CONFIG_RCU_STALL_COMMON is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_EXPEDITE_BOOT is not set +# CONFIG_BUILD_BIN2C is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_NMI_LOG_BUF_SHIFT=13 +CONFIG_GENERIC_SCHED_CLOCK=y +# CONFIG_CGROUPS is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SCHED_DL is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="usr/rootfs.cpio.xz" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +CONFIG_RD_XZ=y +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_HAVE_UID16=y +CONFIG_BPF=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +CONFIG_SYSFS_SYSCALL=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set +CONFIG_KALLSYMS_BASE_RELATIVE=y +CONFIG_PRINTK=y +CONFIG_PRINTK_NMI=y +# CONFIG_BUG is not set +# CONFIG_ELF_CORE is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +# CONFIG_BPF_SYSCALL is not set +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_ADVISE_SYSCALLS=y +# CONFIG_USERFAULTFD is not set +CONFIG_MEMBARRIER=y +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SYSTEM_DATA_VERIFICATION is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_UPROBES is not set +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_GCC_PLUGINS=y +# CONFIG_GCC_PLUGINS is not set +CONFIG_HAVE_CC_STACKPROTECTOR=y +# CONFIG_CC_STACKPROTECTOR is not set +CONFIG_CC_STACKPROTECTOR_NONE=y +# CONFIG_CC_STACKPROTECTOR_REGULAR is not set +# CONFIG_CC_STACKPROTECTOR_STRONG is not set +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_EXIT_THREAD=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=8 +CONFIG_ARCH_MMAP_RND_BITS_MAX=16 +CONFIG_ARCH_MMAP_RND_BITS=8 +# CONFIG_HAVE_ARCH_HASH is not set +# CONFIG_ISA_BUS_API is not set +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OLD_SIGACTION=y +# CONFIG_CPU_NO_EFFICIENT_FFS is not set +# CONFIG_HAVE_ARCH_VMAP_STACK is not set + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_CMDLINE_PARSER is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_EFI_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_MULTIPLATFORM is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +CONFIG_ARCH_FULLHAN=y +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP1 is not set + +# +# Fullhan platform type +# +# CONFIG_FH_FASTBOOT is not set +# CONFIG_ARCH_FH8833 is not set +# CONFIG_ARCH_FH8856 is not set +# CONFIG_ARCH_FH8852 is not set +# CONFIG_ARCH_FH8626V100 is not set +CONFIG_ARCH_FH885xV200=y +# CONFIG_ARCH_FH865x is not set + +CONFIG_FH_CHIP_NAME="fh8858v210" +# CONFIG_MACH_FH8856V200 is not set +# CONFIG_MACH_FH8852V200 is not set +CONFIG_MACH_FH8858V210=y + +# +# Processor Type +# +CONFIG_CPU_V6=y +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_KUSER_HELPERS=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +# CONFIG_DEBUG_RODATA is not set +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_PJ4B_ERRATA_4742=y +# CONFIG_ARM_ERRATA_326103 is not set +CONFIG_ARM_ERRATA_411920=y +# CONFIG_ARM_ERRATA_364296 is not set + +# +# Bus support +# +# CONFIG_PCI_DOMAINS_GENERIC is not set +# CONFIG_PCI_SYSCALL is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_3G_OPT is not set +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_ARCH_NR_GPIO=0 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ_FIXED=0 +CONFIG_HZ_100=y +# CONFIG_HZ_200 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_500 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +# CONFIG_SCHED_HRTICK is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +# CONFIG_HIGHMEM is not set +CONFIG_CPU_SW_DOMAIN_PAN=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +# CONFIG_ARM_MODULE_PLTS is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_NO_BOOTMEM=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_CLEANCACHE is not set +# CONFIG_CMA is not set +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +# CONFIG_ZSMALLOC is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +CONFIG_SWIOTLB=y +CONFIG_IOMMU_HELPER=y +# CONFIG_PARAVIRT is not set +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set + +# +# Boot options +# +# CONFIG_USE_OF is not set +CONFIG_ATAGS=y +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_AUTO_ZRELADDR=y + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# CPU Idle +# +# CONFIG_CPU_IDLE is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ELFCORE=y +CONFIG_BINFMT_SCRIPT=y +# CONFIG_BINFMT_FLAT is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y + +# +# Power management options +# +# CONFIG_SUSPEND is not set +# CONFIG_PM is not set +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_NET_IP_TUNNEL=y +# CONFIG_IP_MROUTE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_NET_IPVTI is not set +# CONFIG_NET_UDP_TUNNEL is not set +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_INET_DIAG_DESTROY is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +# CONFIG_IPV6_VTI is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_FOU is not set +# CONFIG_IPV6_FOU_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NET_PTP_CLASSIFY is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +CONFIG_HAVE_NET_DSA=y +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_MPLS is not set +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_NET_NCSI is not set +# CONFIG_SOCK_CGROUP_DATA is not set +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +# CONFIG_BPF_JIT is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +# CONFIG_STREAM_PARSER is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=y +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +# CONFIG_CFG80211_DEFAULT_PS is not set +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_CFG80211_WEXT=y +CONFIG_LIB80211=y +CONFIG_LIB80211_CRYPT_WEP=y +CONFIG_LIB80211_CRYPT_CCMP=y +CONFIG_LIB80211_CRYPT_TKIP=y +# CONFIG_LIB80211_DEBUG is not set +# CONFIG_MAC80211 is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +# CONFIG_RFKILL_INPUT is not set +# CONFIG_RFKILL_GPIO is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_LWTUNNEL is not set +CONFIG_DST_CACHE=y +# CONFIG_NET_DEVLINK is not set +CONFIG_MAY_USE_DEVLINK=y +CONFIG_HAVE_CBPF_JIT=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +# CONFIG_DMA_SHARED_BUFFER is not set + +# +# Bus devices +# +# CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR & LPDDR2 PCM memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_LPDDR2_NVM is not set +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_MT81xx_NOR is not set +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_MTD_UBI is not set +# CONFIG_OF is not set +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_NVME_TARGET is not set + +# +# Misc devices +# +# CONFIG_FH_DW_I2S is not set +# CONFIG_FH_ACW is not set +CONFIG_FH_SADC_V3=y +CONFIG_FH_EFUSE=y +# CONFIG_FH_L2MEM is not set +CONFIG_FH_PINCTRL_MISC_DEV=y +CONFIG_FH_CLK_MISC=y +CONFIG_FH_PERF_MON=y +# CONFIG_FH_TSENSOR is not set +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_SRAM is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set + +# +# Intel MIC Bus Driver +# + +# +# SCIF Bus Driver +# + +# +# VOP Bus Driver +# + +# +# Intel MIC Host Driver +# + +# +# Intel MIC Card Driver +# + +# +# SCIF Driver +# + +# +# Intel MIC Coprocessor State Management (COSM) Drivers +# + +# +# VOP Driver +# +# CONFIG_ECHO is not set +# CONFIG_CXL_BASE is not set +# CONFIG_CXL_AFU_DRIVER_OPS is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_MACSEC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_TUN is not set +# CONFIG_TUN_VNET_CROSS_LE is not set +# CONFIG_VETH is not set +# CONFIG_NLMON is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +CONFIG_ETHERNET=y +# CONFIG_ALTERA_TSE is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_NET_VENDOR_FULLHAN=y +CONFIG_FH_GMAC=y +CONFIG_FH_GMAC_DA=y +CONFIG_PHYLIB=y +CONFIG_SWPHY=y + +# +# MDIO bus device drivers +# +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_BITBANG is not set + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_AT803X_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +CONFIG_FIXED_PHY=y +# CONFIG_ICPLUS_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +CONFIG_USB_NET_DRIVERS=y +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_RTL8152 is not set +# CONFIG_USB_LAN78XX is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_IPHETH is not set +CONFIG_WLAN=y +CONFIG_WLAN_VENDOR_ADMTEK=y +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +# CONFIG_ATH6KL is not set +CONFIG_WLAN_VENDOR_ATMEL=y +CONFIG_WLAN_VENDOR_BROADCOM=y +# CONFIG_BRCMFMAC is not set +CONFIG_WLAN_VENDOR_CISCO=y +CONFIG_WLAN_VENDOR_INTEL=y +CONFIG_WLAN_VENDOR_INTERSIL=y +CONFIG_HOSTAP=y +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +CONFIG_WLAN_VENDOR_MARVELL=y +# CONFIG_LIBERTAS is not set +# CONFIG_MWIFIEX is not set +CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_WLAN_VENDOR_REALTEK=y +CONFIG_WLAN_VENDOR_RSI=y +CONFIG_WLAN_VENDOR_ST=y +CONFIG_WLAN_VENDOR_TI=y +CONFIG_WLAN_VENDOR_ZYDAS=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_ISDN is not set +# CONFIG_NVM is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVMEM=y +# CONFIG_DEVKMEM is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set +CONFIG_SERIAL_FULLHAN=y +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_ST_ASC is not set +# CONFIG_SERIAL_STM32 is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_SMBUS is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_FH_INTERRUPT=y +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_EMEV2 is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_DESIGNWARE is not set +CONFIG_SPI_FH=y +# CONFIG_SPI_FH_SLAVE is not set + +# +# spi multi wire support +# +CONFIG_SPI_USE_MULTI_WIRE=y +CONFIG_SPI_SWAP_MAX_DATA_WIDTH=16 +# CONFIG_SPI_USE_DMA is not set +CONFIG_SPI_TINY_MEM=y +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +# CONFIG_PTP_1588_CLOCK is not set + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers +# +CONFIG_GPIO_FH=y +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_MPC8XXX is not set +# CONFIG_GPIO_ZX is not set + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_TPIC2810 is not set +# CONFIG_GPIO_TS4900 is not set + +# +# MFD GPIO expanders +# +# CONFIG_HTC_EGPIO is not set + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set + +# +# SPI or I2C GPIO expanders +# + +# +# USB GPIO expanders +# +# CONFIG_W1 is not set +# CONFIG_POWER_AVS is not set +# CONFIG_POWER_RESET is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_CORE is not set +# CONFIG_WATCHDOG_NOWAYOUT is not set +# CONFIG_WATCHDOG_SYSFS is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_FH_WATCHDOG=y +# CONFIG_MEN_A21_WDT is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set + +# +# Watchdog Pretimeout Governors +# +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_EXYNOS_LPASS is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_INTEL_SOC_PMIC is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_PM8921_CORE is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RTSX_USB is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set +# CONFIG_SOUND is not set + +# +# HID support +# +# CONFIG_HID is not set + +# +# USB HID support +# +# CONFIG_USB_HID is not set +# CONFIG_HID_PID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +CONFIG_USB_DYNAMIC_MINORS=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +CONFIG_USB_WUSB_CBAF=y +# CONFIG_USB_WUSB_CBAF_DEBUG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_MAX3421_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +CONFIG_USB_WDM=y +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_DWC3 is not set +CONFIG_USB_DWC2=y +CONFIG_USB_DWC2_HOST=y + +# +# Gadget/Dual-role mode requires USB Gadget support to be enabled +# +# CONFIG_USB_DWC2_VBVALIDOVEN is not set +# CONFIG_USB_DWC2_DEBUG is not set +# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set +# CONFIG_USB_DWC2_HOST_DMA_DESC_NUM_DYNAMIC is not set +CONFIG_USB_DWC2_DMA=y +# CONFIG_USB_DWC2_DMA_DESC is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set + +# +# USB Physical Layer drivers +# +# CONFIG_USB_PHY is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ULPI is not set +# CONFIG_USB_GADGET is not set +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_UWB is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SPI is not set +CONFIG_MMC_FH=y +CONFIG_MMC_FH_IDMAC=y +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_MTK is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +# CONFIG_EDAC is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV8803 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6916 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RX6110 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_MCP795 is not set +# CONFIG_RTC_I2C_AND_SPI is not set + +# +# SPI and I2C RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_FH=y +CONFIG_USE_TSENSOR=y +# CONFIG_USE_TSENSOR_OFFSET is not set + +# +# HID Sensor RTC drivers +# +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +# CONFIG_DW_DMAC is not set +CONFIG_CHANNEL_ALLOC_MEM_CLASSICS=y +# CONFIG_FH_DMAC is not set +CONFIG_FH_AXI_DMAC=y +CONFIG_FH_DMAC_MISC=y + +# +# dma tinyconfig +# +CONFIG_CHANNEL_ALLOC_DESC_NUM=32 +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_NBPFAXI_DMA is not set +# CONFIG_QCOM_HIDMA_MGMT is not set +# CONFIG_QCOM_HIDMA is not set + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set + +# +# DMABUF options +# +# CONFIG_SYNC_FILE is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VIRT_DRIVERS is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_STAGING is not set +# CONFIG_GOLDFISH is not set +# CONFIG_CHROME_PLATFORMS is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_COMMON_CLK_NXP is not set +# CONFIG_COMMON_CLK_PWM is not set +# CONFIG_COMMON_CLK_PXA is not set +# CONFIG_COMMON_CLK_PIC32 is not set + +# +# Hardware Spinlock drivers +# + +# +# Clock Source drivers +# +CONFIG_FULLHAN_TIMER=y +# CONFIG_FH_SIMPLE_TIMER is not set +# CONFIG_ARM_TIMER_SP804 is not set +# CONFIG_ATMEL_PIT is not set +# CONFIG_SH_TIMER_CMT is not set +# CONFIG_SH_TIMER_MTU2 is not set +# CONFIG_SH_TIMER_TMU is not set +# CONFIG_EM_TIMER_STI is not set +# CONFIG_MAILBOX is not set +# CONFIG_IOMMU_SUPPORT is not set + +# +# Remoteproc drivers +# +# CONFIG_STE_MODEM_RPROC is not set + +# +# Rpmsg drivers +# + +# +# SOC (System On Chip) specific Drivers +# + +# +# Broadcom SoC drivers +# +# CONFIG_SOC_BRCMSTB is not set +# CONFIG_SUNXI_SRAM is not set +# CONFIG_SOC_TI is not set +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +CONFIG_PWM=y +# CONFIG_PWM_SYSFS is not set +# CONFIG_DEBUG_PWM_FS is not set +CONFIG_PWM_FULLHAN=y +CONFIG_FH_PWM_NUM=14 +# CONFIG_PWM_PCA9685 is not set +CONFIG_ARM_GIC_MAX_NR=1 +CONFIG_FULLHAN_INTC=y +# CONFIG_IPACK_BUS is not set +# CONFIG_RESET_CONTROLLER is not set +# CONFIG_FMC is not set + +# +# PHY Subsystem +# +# CONFIG_GENERIC_PHY is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_FH_USB2_PHY is not set +# CONFIG_PHY_SAMSUNG_USB2 is not set +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +# CONFIG_RAS is not set + +# +# Android +# +# CONFIG_ANDROID is not set +# CONFIG_NVMEM is not set +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set + +# +# FPGA Configuration Support +# +# CONFIG_FPGA is not set + +# +# Firmware Drivers +# +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_FW_CFG_SYSFS is not set + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_FILE_LOCKING=y +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +# CONFIG_OVERLAY_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_PROC_CHILDREN is not set +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_WRITEBUFFER is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V2 is not set +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_SWAP is not set +# CONFIG_ROOT_NFS is not set +# CONFIG_NFSD is not set +CONFIG_GRACE_PERIOD=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_DYNAMIC_DEBUG is not set + +# +# Compile-time checks and compiler options +# +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_OPTIMIZE_INLINING=y +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_DEBUG_KERNEL is not set + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_MEMORY_INIT is not set + +# +# Debug Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_SCHED_INFO is not set +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +# CONFIG_STACKTRACE is not set + +# +# RCU Debugging +# +# CONFIG_PROVE_RCU is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_TORTURE_TEST is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_HWLAT_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_FTRACE_SYSCALLS is not set +# CONFIG_TRACER_SNAPSHOT is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_PROBE_EVENTS is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +CONFIG_TRACING_EVENTS_GPIO=y + +# +# Runtime Testing +# +# CONFIG_LKDTM is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_HASH is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_MEMTEST is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set +# CONFIG_UBSAN is not set +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +# CONFIG_STRICT_DEVMEM is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_UART_8250 is not set +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_DEBUG_SET_MODULE_RONX is not set +# CONFIG_CORESIGHT is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_BIG_KEYS is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEY_DH_OPERATIONS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y +# CONFIG_HARDENED_USERCOPY is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_KPP2=y +# CONFIG_CRYPTO_RSA is not set +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_ECDH is not set +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_MCRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_KEYWRAP is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_CMAC is not set +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +CONFIG_CRYPTO_MICHAEL_MIC=y +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +CONFIG_CRYPTO_SHA256=y +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG is not set +# CONFIG_CRYPTO_JITTERENTROPY is not set +CONFIG_CRYPTO_USER_API=y +# CONFIG_CRYPTO_USER_API_HASH is not set +CONFIG_CRYPTO_USER_API_SKCIPHER=y +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_FH_CESA is not set +CONFIG_CRYPTO_DEV_FH_AES=y +# CONFIG_CRYPTO_FH_AES_SUPPORT_DIRECT_MEM is not set +# CONFIG_FH_AES_SELF_TEST is not set +# CONFIG_ASYMMETRIC_KEY_TYPE is not set + +# +# Certificates for signature checking +# +# CONFIG_ARM_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_HAVE_ARCH_BITREVERSE is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_XZ=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y +# CONFIG_CORDIC is not set +# CONFIG_DDR is not set +# CONFIG_IRQ_POLL is not set +# CONFIG_SG_SPLIT is not set +# CONFIG_SG_POOL is not set +# CONFIG_ARCH_HAS_SG_CHAIN is not set +CONFIG_SBITMAP=y +# CONFIG_VIRTUALIZATION is not set diff --git a/arch/arm/configs/fh8858v210_of_defconfig b/arch/arm/configs/fh8858v210_of_defconfig new file mode 100644 index 00000000..b7ea132a --- /dev/null +++ b/arch/arm/configs/fh8858v210_of_defconfig @@ -0,0 +1,2332 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 4.9.129 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y + +# +# General setup +# +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_TINY_KERNEL=y +CONFIG_NTP=y +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_LZMA is not set +CONFIG_KERNEL_XZ=y +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_NO_COMPRESS is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_FHANDLE is not set +CONFIG_USELIB=y +# CONFIG_AUDIT is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_IRQ_DOMAIN=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_GENERIC_CLOCKEVENTS=y + +# +# Timers subsystem +# +CONFIG_HZ_PERIODIC=y +# CONFIG_NO_HZ_IDLE is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set + +# +# RCU Subsystem +# +CONFIG_TINY_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +# CONFIG_TASKS_RCU is not set +# CONFIG_RCU_STALL_COMMON is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_EXPEDITE_BOOT is not set +# CONFIG_BUILD_BIN2C is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_NMI_LOG_BUF_SHIFT=13 +CONFIG_GENERIC_SCHED_CLOCK=y +# CONFIG_CGROUPS is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SCHED_DL is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="usr/rootfs.cpio.xz" +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +CONFIG_RD_XZ=y +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_LD_DEAD_CODE_DATA_ELIMINATION=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_HAVE_UID16=y +CONFIG_BPF=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +CONFIG_SYSFS_SYSCALL=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set +CONFIG_KALLSYMS_BASE_RELATIVE=y +CONFIG_PRINTK=y +CONFIG_PRINTK_NMI=y +# CONFIG_BUG is not set +# CONFIG_ELF_CORE is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +# CONFIG_BPF_SYSCALL is not set +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_ADVISE_SYSCALLS=y +# CONFIG_USERFAULTFD is not set +CONFIG_MEMBARRIER=y +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SYSTEM_DATA_VERIFICATION is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_UPROBES is not set +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_GCC_PLUGINS=y +# CONFIG_GCC_PLUGINS is not set +CONFIG_HAVE_CC_STACKPROTECTOR=y +# CONFIG_CC_STACKPROTECTOR is not set +CONFIG_CC_STACKPROTECTOR_NONE=y +# CONFIG_CC_STACKPROTECTOR_REGULAR is not set +# CONFIG_CC_STACKPROTECTOR_STRONG is not set +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_EXIT_THREAD=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=8 +CONFIG_ARCH_MMAP_RND_BITS_MAX=16 +CONFIG_ARCH_MMAP_RND_BITS=8 +# CONFIG_HAVE_ARCH_HASH is not set +# CONFIG_ISA_BUS_API is not set +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OLD_SIGACTION=y +# CONFIG_CPU_NO_EFFICIENT_FFS is not set +# CONFIG_HAVE_ARCH_VMAP_STACK is not set + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_CMDLINE_PARSER is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_EFI_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_DEADLINE is not set +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_MULTIPLATFORM is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +CONFIG_ARCH_FULLHAN=y +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP1 is not set + +# +# Fullhan platform type +# +# CONFIG_FH_FASTBOOT is not set +# CONFIG_ARCH_FH8833 is not set +# CONFIG_ARCH_FH8856 is not set +# CONFIG_ARCH_FH8626V100 is not set +CONFIG_ARCH_FH885xV200=y +# CONFIG_ARCH_FH865x is not set + +CONFIG_FH_CHIP_NAME="fh8858v210" +CONFIG_MACH_FH8858V210=y +# CONFIG_MACH_FH8852V200 is not set + +# +# Processor Type +# +CONFIG_CPU_V6=y +CONFIG_CPU_32v6=y +CONFIG_CPU_ABRT_EV6=y +CONFIG_CPU_PABRT_V6=y +CONFIG_CPU_CACHE_V6=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V6=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_KUSER_HELPERS=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_ARM_L1_CACHE_SHIFT=5 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +# CONFIG_DEBUG_RODATA is not set +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_PJ4B_ERRATA_4742=y +# CONFIG_ARM_ERRATA_326103 is not set +CONFIG_ARM_ERRATA_411920=y +# CONFIG_ARM_ERRATA_364296 is not set + +# +# Bus support +# +# CONFIG_PCI_DOMAINS_GENERIC is not set +# CONFIG_PCI_SYSCALL is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_3G_OPT is not set +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_ARCH_NR_GPIO=0 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_HZ_FIXED=0 +CONFIG_HZ_100=y +# CONFIG_HZ_200 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_500 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +# CONFIG_SCHED_HRTICK is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +# CONFIG_HIGHMEM is not set +CONFIG_CPU_SW_DOMAIN_PAN=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +# CONFIG_ARM_MODULE_PLTS is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_NO_BOOTMEM=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_CLEANCACHE is not set +# CONFIG_CMA is not set +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +# CONFIG_ZSMALLOC is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +CONFIG_SWIOTLB=y +CONFIG_IOMMU_HELPER=y +# CONFIG_PARAVIRT is not set +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set + +# +# Boot options +# +CONFIG_USE_OF=y +CONFIG_ATAGS=y +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND=y +CONFIG_CMDLINE="" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_AUTO_ZRELADDR=y +# CONFIG_EFI is not set + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +# CONFIG_CPU_FREQ is not set + +# +# CPU Idle +# +# CONFIG_CPU_IDLE is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ELFCORE=y +CONFIG_BINFMT_SCRIPT=y +# CONFIG_BINFMT_FLAT is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y + +# +# Power management options +# +# CONFIG_SUSPEND is not set +# CONFIG_PM is not set +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_NET_IP_TUNNEL=y +# CONFIG_IP_MROUTE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_NET_IPVTI is not set +# CONFIG_NET_UDP_TUNNEL is not set +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_INET_DIAG_DESTROY is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +# CONFIG_IPV6_VTI is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_FOU is not set +# CONFIG_IPV6_FOU_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NET_PTP_CLASSIFY is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +CONFIG_HAVE_NET_DSA=y +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_MPLS is not set +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_NET_NCSI is not set +# CONFIG_SOCK_CGROUP_DATA is not set +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +# CONFIG_BPF_JIT is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +# CONFIG_STREAM_PARSER is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=y +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +# CONFIG_CFG80211_DEFAULT_PS is not set +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_CFG80211_WEXT=y +CONFIG_LIB80211=y +CONFIG_LIB80211_CRYPT_WEP=y +CONFIG_LIB80211_CRYPT_CCMP=y +CONFIG_LIB80211_CRYPT_TKIP=y +# CONFIG_LIB80211_DEBUG is not set +# CONFIG_MAC80211 is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +# CONFIG_RFKILL_INPUT is not set +# CONFIG_RFKILL_GPIO is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_LWTUNNEL is not set +CONFIG_DST_CACHE=y +# CONFIG_NET_DEVLINK is not set +CONFIG_MAY_USE_DEVLINK=y +CONFIG_HAVE_CBPF_JIT=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +# CONFIG_DMA_SHARED_BUFFER is not set + +# +# Bus devices +# +# CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_VEXPRESS_CONFIG is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR & LPDDR2 PCM memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_LPDDR2_NVM is not set +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_MT81xx_NOR is not set +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +# CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_MTD_UBI is not set +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_MDIO=y +CONFIG_OF_RESERVED_MEM=y +# CONFIG_OF_OVERLAY is not set +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_NVME_TARGET is not set + +# +# Misc devices +# +# CONFIG_FH_DW_I2S is not set +# CONFIG_FH_ACW is not set +CONFIG_FH_SADC_V3=y +CONFIG_FH_EFUSE=y +# CONFIG_FH_L2MEM is not set +CONFIG_FH_CLK_MISC=y +CONFIG_FH_PERF_MON=y +# CONFIG_FH_TSENSOR is not set +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_SRAM is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set + +# +# Intel MIC Bus Driver +# + +# +# SCIF Bus Driver +# + +# +# VOP Bus Driver +# + +# +# Intel MIC Host Driver +# + +# +# Intel MIC Card Driver +# + +# +# SCIF Driver +# + +# +# Intel MIC Coprocessor State Management (COSM) Drivers +# + +# +# VOP Driver +# +# CONFIG_ECHO is not set +# CONFIG_CXL_BASE is not set +# CONFIG_CXL_AFU_DRIVER_OPS is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_MACSEC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_TUN is not set +# CONFIG_TUN_VNET_CROSS_LE is not set +# CONFIG_VETH is not set +# CONFIG_NLMON is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +CONFIG_ETHERNET=y +# CONFIG_ALTERA_TSE is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_NET_VENDOR_FULLHAN=y +CONFIG_FH_GMAC=y +CONFIG_FH_GMAC_DA=y + +# +# fh inside or outside phy sel +# +CONFIG_PHYLIB=y +CONFIG_SWPHY=y + +# +# MDIO bus device drivers +# +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MDIO_HISI_FEMAC is not set + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_AT803X_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +CONFIG_FIXED_PHY=y +# CONFIG_ICPLUS_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +CONFIG_USB_NET_DRIVERS=y +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_RTL8152 is not set +# CONFIG_USB_LAN78XX is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_IPHETH is not set +CONFIG_WLAN=y +CONFIG_WLAN_VENDOR_ADMTEK=y +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +# CONFIG_ATH6KL is not set +CONFIG_WLAN_VENDOR_ATMEL=y +CONFIG_WLAN_VENDOR_BROADCOM=y +# CONFIG_BRCMFMAC is not set +CONFIG_WLAN_VENDOR_CISCO=y +CONFIG_WLAN_VENDOR_INTEL=y +CONFIG_WLAN_VENDOR_INTERSIL=y +CONFIG_HOSTAP=y +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +CONFIG_WLAN_VENDOR_MARVELL=y +# CONFIG_LIBERTAS is not set +# CONFIG_MWIFIEX is not set +CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_WLAN_VENDOR_REALTEK=y +CONFIG_WLAN_VENDOR_RSI=y +CONFIG_WLAN_VENDOR_ST=y +CONFIG_WLAN_VENDOR_TI=y +CONFIG_WLAN_VENDOR_ZYDAS=y +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_ISDN is not set +# CONFIG_NVM is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVMEM=y +# CONFIG_DEVKMEM is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set +CONFIG_SERIAL_FULLHAN=y +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +# CONFIG_SERIAL_ST_ASC is not set +# CONFIG_SERIAL_STM32 is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_XILLYBUS is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_SMBUS is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_FH_INTERRUPT=y +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_EMEV2 is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_RK3X is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_DESIGNWARE is not set +CONFIG_SPI_FH=y + +# +# spi multi wire support +# +CONFIG_SPI_USE_MULTI_WIRE=y +CONFIG_SPI_SWAP_MAX_DATA_WIDTH=16 +# CONFIG_SPI_USE_DMA is not set +CONFIG_SPI_TINY_MEM=y +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +# CONFIG_PTP_1588_CLOCK is not set + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_PINCTRL=y + +# +# Pin controllers +# +CONFIG_PINMUX=y +CONFIG_PINCTRL_FULLHAN=y +# CONFIG_PINCTRL_AMD is not set +# CONFIG_PINCTRL_SINGLE is not set +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_GPIOLIB=y +CONFIG_OF_GPIO=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers +# +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ALTERA is not set +CONFIG_GPIO_FH=y +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_EM is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_MPC8XXX is not set +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_ZEVIO is not set +# CONFIG_GPIO_ZX is not set + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_TPIC2810 is not set +# CONFIG_GPIO_TS4900 is not set + +# +# MFD GPIO expanders +# +# CONFIG_HTC_EGPIO is not set + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set + +# +# SPI or I2C GPIO expanders +# +# CONFIG_GPIO_MCP23S08 is not set + +# +# USB GPIO expanders +# +# CONFIG_W1 is not set +# CONFIG_POWER_AVS is not set +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_BRCMKONA is not set +# CONFIG_POWER_RESET_GPIO is not set +# CONFIG_POWER_RESET_GPIO_RESTART is not set +CONFIG_POWER_RESET_FH=y +# CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_RESTART is not set +# CONFIG_POWER_RESET_SYSCON is not set +# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_CORE is not set +# CONFIG_WATCHDOG_NOWAYOUT is not set +# CONFIG_WATCHDOG_SYSFS is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_GPIO_WATCHDOG is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_FH_WATCHDOG=y +# CONFIG_MEN_A21_WDT is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set + +# +# Watchdog Pretimeout Governors +# +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_ACT8945A is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_EXYNOS_LPASS is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_INTEL_SOC_PMIC is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77620 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_PM8921_CORE is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RTSX_USB is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RK808 is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set +# CONFIG_SOUND is not set + +# +# HID support +# +# CONFIG_HID is not set + +# +# USB HID support +# +# CONFIG_USB_HID is not set +# CONFIG_HID_PID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +CONFIG_USB_DYNAMIC_MINORS=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +CONFIG_USB_WUSB_CBAF=y +# CONFIG_USB_WUSB_CBAF_DEBUG is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_MAX3421_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +CONFIG_USB_WDM=y +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_DWC3 is not set +CONFIG_USB_DWC2=y +CONFIG_USB_DWC2_HOST=y + +# +# Gadget/Dual-role mode requires USB Gadget support to be enabled +# +# CONFIG_USB_DWC2_VBVALIDOVEN is not set +# CONFIG_USB_DWC2_DEBUG is not set +# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set +# CONFIG_USB_DWC2_HOST_DMA_DESC_NUM_DYNAMIC is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set + +# +# USB Physical Layer drivers +# +# CONFIG_USB_PHY is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ULPI is not set +# CONFIG_USB_GADGET is not set +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_UWB is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_PWRSEQ_EMMC=y +CONFIG_PWRSEQ_SIMPLE=y + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SPI is not set +CONFIG_MMC_FH=y +CONFIG_MMC_FH_IDMAC=y +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_MTK is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +# CONFIG_EDAC is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_HYM8563 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV8803 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1302 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6916 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_RX6110 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_MCP795 is not set +# CONFIG_RTC_I2C_AND_SPI is not set + +# +# SPI and I2C RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_ZYNQMP is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_SNVS is not set +CONFIG_RTC_DRV_FH=y +CONFIG_USE_TSENSOR=y +# CONFIG_USE_TSENSOR_OFFSET is not set + +# +# HID Sensor RTC drivers +# +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +# CONFIG_DW_DMAC is not set +# CONFIG_FH_DMAC is not set +CONFIG_FH_AXI_DMAC=y +CONFIG_FH_DMAC_MISC=y + +# +# dma tinyconfig +# +CONFIG_CHANNEL_ALLOC_MEM_CLASSICS=y +CONFIG_CHANNEL_ALLOC_DESC_NUM=32 +# CONFIG_FSL_EDMA is not set +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_NBPFAXI_DMA is not set +# CONFIG_QCOM_HIDMA_MGMT is not set +# CONFIG_QCOM_HIDMA is not set + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set + +# +# DMABUF options +# +# CONFIG_SYNC_FILE is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VIRT_DRIVERS is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_STAGING is not set +# CONFIG_GOLDFISH is not set +# CONFIG_CHROME_PLATFORMS is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI514 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CDCE925 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_CLK_QORIQ is not set +# CONFIG_COMMON_CLK_NXP is not set +# CONFIG_COMMON_CLK_PWM is not set +# CONFIG_COMMON_CLK_PXA is not set +# CONFIG_COMMON_CLK_PIC32 is not set + +# +# Hardware Spinlock drivers +# + +# +# Clock Source drivers +# +CONFIG_CLKSRC_OF=y +CONFIG_CLKSRC_PROBE=y +CONFIG_FULLHAN_TIMER=y +# CONFIG_FH_SIMPLE_TIMER is not set +# CONFIG_ARM_TIMER_SP804 is not set +# CONFIG_ATMEL_PIT is not set +# CONFIG_SH_TIMER_CMT is not set +# CONFIG_SH_TIMER_MTU2 is not set +# CONFIG_SH_TIMER_TMU is not set +# CONFIG_EM_TIMER_STI is not set +# CONFIG_MAILBOX is not set +# CONFIG_IOMMU_SUPPORT is not set + +# +# Remoteproc drivers +# +# CONFIG_STE_MODEM_RPROC is not set + +# +# Rpmsg drivers +# + +# +# SOC (System On Chip) specific Drivers +# + +# +# Broadcom SoC drivers +# +# CONFIG_SOC_BRCMSTB is not set +# CONFIG_SUNXI_SRAM is not set +# CONFIG_SOC_TI is not set +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +CONFIG_PWM=y +# CONFIG_PWM_SYSFS is not set +# CONFIG_DEBUG_PWM_FS is not set +CONFIG_PWM_FULLHAN=y +CONFIG_FH_PWM_NUM=2 +# CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_PCA9685 is not set +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC_MAX_NR=1 +CONFIG_FULLHAN_INTC=y +# CONFIG_IPACK_BUS is not set +# CONFIG_RESET_CONTROLLER is not set +# CONFIG_FMC is not set + +# +# PHY Subsystem +# +# CONFIG_GENERIC_PHY is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_FH_USB2_PHY is not set +# CONFIG_PHY_SAMSUNG_USB2 is not set +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +# CONFIG_RAS is not set + +# +# Android +# +# CONFIG_ANDROID is not set +# CONFIG_NVMEM is not set +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set + +# +# FPGA Configuration Support +# +# CONFIG_FPGA is not set + +# +# Firmware Drivers +# +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_FW_CFG_SYSFS is not set + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_FILE_LOCKING=y +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +# CONFIG_OVERLAY_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_PROC_CHILDREN is not set +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_WRITEBUFFER is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V2 is not set +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +# CONFIG_NFS_SWAP is not set +# CONFIG_ROOT_NFS is not set +# CONFIG_NFSD is not set +CONFIG_GRACE_PERIOD=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_DYNAMIC_DEBUG is not set + +# +# Compile-time checks and compiler options +# +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_OPTIMIZE_INLINING=y +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_DEBUG_KERNEL is not set + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_MEMORY_INIT is not set + +# +# Debug Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_SCHED_INFO is not set +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +# CONFIG_STACKTRACE is not set + +# +# RCU Debugging +# +# CONFIG_PROVE_RCU is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_TORTURE_TEST is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_HWLAT_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_FTRACE_SYSCALLS is not set +# CONFIG_TRACER_SNAPSHOT is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_PROBE_EVENTS is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +CONFIG_TRACING_EVENTS_GPIO=y + +# +# Runtime Testing +# +# CONFIG_LKDTM is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_HASH is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_MEMTEST is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set +# CONFIG_UBSAN is not set +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +# CONFIG_STRICT_DEVMEM is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_UART_8250 is not set +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_DEBUG_SET_MODULE_RONX is not set +# CONFIG_CORESIGHT is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_BIG_KEYS is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEY_DH_OPERATIONS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y +# CONFIG_HARDENED_USERCOPY is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_KPP2=y +# CONFIG_CRYPTO_RSA is not set +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_ECDH is not set +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_MCRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_KEYWRAP is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_CMAC is not set +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +CONFIG_CRYPTO_MICHAEL_MIC=y +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +CONFIG_CRYPTO_SHA256=y +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG is not set +# CONFIG_CRYPTO_JITTERENTROPY is not set +CONFIG_CRYPTO_USER_API=y +# CONFIG_CRYPTO_USER_API_HASH is not set +CONFIG_CRYPTO_USER_API_SKCIPHER=y +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_DEV_FH_AES=y +# CONFIG_CRYPTO_FH_AES_SUPPORT_DIRECT_MEM is not set +# CONFIG_FH_AES_SELF_TEST is not set +# CONFIG_ASYMMETRIC_KEY_TYPE is not set + +# +# Certificates for signature checking +# +# CONFIG_ARM_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_HAVE_ARCH_BITREVERSE is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_XZ=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y +# CONFIG_CORDIC is not set +# CONFIG_DDR is not set +# CONFIG_IRQ_POLL is not set +CONFIG_LIBFDT=y +# CONFIG_SG_SPLIT is not set +# CONFIG_SG_POOL is not set +# CONFIG_ARCH_HAS_SG_CHAIN is not set +CONFIG_SBITMAP=y +# CONFIG_VIRTUALIZATION is not set diff --git a/arch/arm/include/asm/mach/flash.h b/arch/arm/include/asm/mach/flash.h index 4ca69fe2..0eea1ab7 100644 --- a/arch/arm/include/asm/mach/flash.h +++ b/arch/arm/include/asm/mach/flash.h @@ -26,7 +26,7 @@ struct mtd_info; */ struct flash_platform_data { const char *map_name; - const char *name; + char name[16]; unsigned int width; int (*init)(void); void (*exit)(void); diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index 76cbd9c6..eaf74e04 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -98,7 +98,7 @@ #endif #ifndef END_MEM -#define END_MEM (UL(CONFIG_DRAM_BASE) + CONFIG_DRAM_SIZE) +#define END_MEM (UL(CONFIG_DRAM_BASE) + CONFIG_DRAM_SIZE) #endif /* @@ -143,8 +143,8 @@ */ #define PHYS_RELATIVE(v_data, v_text) \ (((v_data) - PAGE_OFFSET + PLAT_PHYS_OFFSET) - \ - ((v_text) - XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) + \ - CONFIG_XIP_PHYS_ADDR)) + ((v_text) - XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) + \ + CONFIG_XIP_PHYS_ADDR)) #else #define PHYS_RELATIVE(v_data, v_text) ((v_data) - (v_text)) #endif @@ -171,13 +171,13 @@ extern unsigned long __pv_phys_pfn_offset; extern u64 __pv_offset; -extern void fixup_pv_table(const void *, unsigned long); +extern void fixup_pv_table(const void *addr, unsigned long size); extern const void *__pv_table_begin, *__pv_table_end; #define PHYS_OFFSET ((phys_addr_t)__pv_phys_pfn_offset << PAGE_SHIFT) #define PHYS_PFN_OFFSET (__pv_phys_pfn_offset) -#define __pv_stub(from,to,instr,type) \ +#define __pv_stub(from, to, instr, type) \ __asm__("@ __pv_stub\n" \ "1: " instr " %0, %1, %2\n" \ " .pushsection .pv_table,\"a\"\n" \ diff --git a/arch/arm/include/asm/string.h b/arch/arm/include/asm/string.h index cf4f3aad..649b9866 100644 --- a/arch/arm/include/asm/string.h +++ b/arch/arm/include/asm/string.h @@ -26,14 +26,14 @@ extern void * memset(void *, int, __kernel_size_t); extern void __memzero(void *ptr, __kernel_size_t n); -#define memset(p,v,n) \ +#define memset(p, v, n) \ ({ \ void *__p = (p); size_t __n = n; \ if ((__n) != 0) { \ if (__builtin_constant_p((v)) && (v) == 0) \ - __memzero((__p),(__n)); \ + __memzero((__p), (__n)); \ else \ - memset((__p),(v),(__n)); \ + memset((__p), (v), (__n)); \ } \ (__p); \ }) diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h index 776757d1..9cc9e000 100644 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h @@ -16,7 +16,9 @@ #include #include + #define THREAD_SIZE_ORDER 1 + #define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER) #define THREAD_START_SP (THREAD_SIZE - 8) diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h index b7e0125c..4d8205db 100644 --- a/arch/arm/include/asm/uaccess.h +++ b/arch/arm/include/asm/uaccess.h @@ -182,11 +182,11 @@ extern int __get_user_64t_4(void *); #define __get_user_check(x, p) \ ({ \ unsigned long __limit = current_thread_info()->addr_limit - 1; \ + unsigned int __ua_flags = uaccess_save_and_enable(); \ register const typeof(*(p)) __user *__p asm("r0") = (p);\ register typeof(x) __r2 asm("r2"); \ register unsigned long __l asm("r1") = __limit; \ register int __e asm("r0"); \ - unsigned int __ua_flags = uaccess_save_and_enable(); \ switch (sizeof(*(__p))) { \ case 1: \ if (sizeof((x)) >= 8) \ @@ -214,8 +214,8 @@ extern int __get_user_64t_4(void *); break; \ default: __e = __get_user_bad(); break; \ } \ - uaccess_restore(__ua_flags); \ x = (typeof(*(p))) __r2; \ + uaccess_restore(__ua_flags); \ __e; \ }) diff --git a/arch/arm/include/debug/fh.S b/arch/arm/include/debug/fh.S new file mode 100644 index 00000000..020cd44b --- /dev/null +++ b/arch/arm/include/debug/fh.S @@ -0,0 +1,44 @@ +/* linux/arch/arm/mach-fh/include/mach/debug-macro.S + * + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/* pull in the relevant register and map files. */ + +/* note, for the boot process to work we have to keep the UART + * virtual address aligned to an 1MiB boundary for the L1 + * mapping the head code makes. We keep the UART virtual address + * aligned and add in the offset when we load the value here. + */ +#include +#include + .macro addruart, rp, rv, tmp + ldr \rp, =CONSOLE_REG_BASE + ldr \rv, =VA_CONSOLE_REG_BASE + .endm + + .macro senduart,data,addr + strb \data, [\addr, #(0x00)] @ Write to Transmitter Holding Register + .endm + + .macro waituart,data,addr +1001: + ldr \data, [\addr, #(0x14)] @ Read Status Register + tst \data, #(0x40) @when TX FIFO Full, then wait + beq 1001b + .endm + + .macro busyuart,data,addr +@ stmfd r13!, {r4} +1002: + ldr \data, [\addr, #(0x14)] + tst \data, #(0x40) + beq 1002b + .endm + + + diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 04286fd9..f9579d83 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -447,6 +447,12 @@ __secondary_data: * r13 = *virtual* address to jump to upon completion */ __enable_mmu: +#if defined (CONFIG_CPU_V7) + /* remember in arm cortex-a7 all mmu facility is based on SMP bit */ + mrc p15, 0, r5, c1, c0, 1 + orr r5, #(1 << 6) + mcr p15, 0, r5, c1, c0, 1 +#endif #if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6 orr r0, r0, #CR_A #else diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c index 4f14b5ce..3a87e2f1 100644 --- a/arch/arm/kernel/module.c +++ b/arch/arm/kernel/module.c @@ -72,7 +72,8 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, #endif offset = ELF32_R_SYM(rel->r_info); - if (offset < 0 || offset > (symsec->sh_size / sizeof(Elf32_Sym))) { + if (offset < 0 || offset > (symsec->sh_size / sizeof(Elf32_Sym)) + ) { pr_err("%s: section %u reloc %u: bad relocation sym offset\n", module->name, relindex, i); return -ENOEXEC; @@ -81,7 +82,8 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, sym = ((Elf32_Sym *)symsec->sh_addr) + offset; symname = strtab + sym->st_name; - if (rel->r_offset < 0 || rel->r_offset > dstsec->sh_size - sizeof(u32)) { + if (rel->r_offset < 0 || rel->r_offset > + dstsec->sh_size - sizeof(u32)) { pr_err("%s: section %u reloc %u sym '%s': out of bounds relocation, offset %d size %u\n", module->name, relindex, i, symname, rel->r_offset, dstsec->sh_size); @@ -145,14 +147,14 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, *(u32 *)loc |= __opcode_to_mem_arm(offset); break; - case R_ARM_V4BX: + case R_ARM_V4BX: /* Preserve Rm and the condition code. Alter * other bits to re-code instruction as * MOV PC,Rm. */ - *(u32 *)loc &= __opcode_to_mem_arm(0xf000000f); - *(u32 *)loc |= __opcode_to_mem_arm(0x01a0f000); - break; + *(u32 *)loc &= __opcode_to_mem_arm(0xf000000f); + *(u32 *)loc |= __opcode_to_mem_arm(0x01a0f000); + break; case R_ARM_PREL31: offset = *(u32 *)loc + sym->st_value - loc; @@ -364,9 +366,9 @@ int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs, if (maps[i].unw_sec && maps[i].txt_sec) mod->arch.unwind[i] = unwind_table_add(maps[i].unw_sec->sh_addr, - maps[i].unw_sec->sh_size, - maps[i].txt_sec->sh_addr, - maps[i].txt_sec->sh_size); + maps[i].unw_sec->sh_size, + maps[i].txt_sec->sh_addr, + maps[i].txt_sec->sh_size); #endif #ifdef CONFIG_ARM_PATCH_PHYS_VIRT s = find_mod_section(hdr, sechdrs, ".pv_table"); diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 7dd14e83..46377c40 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -251,7 +251,7 @@ void __cpu_die(unsigned int cpu) pr_err("CPU%u: cpu didn't die\n", cpu); return; } - pr_notice("CPU%u: shutdown\n", cpu); + pr_debug("CPU%u: shutdown\n", cpu); /* * platform_cpu_kill() is generally expected to do the powering off diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index f7f55df0..9fe15799 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S @@ -17,22 +17,22 @@ #define PROC_INFO \ . = ALIGN(4); \ VMLINUX_SYMBOL(__proc_info_begin) = .; \ - *(.proc.info.init) \ + KEEP(*(.proc.info.init)) \ VMLINUX_SYMBOL(__proc_info_end) = .; #define HYPERVISOR_TEXT \ VMLINUX_SYMBOL(__hyp_text_start) = .; \ - *(.hyp.text) \ + KEEP(*(.hyp.text)) \ VMLINUX_SYMBOL(__hyp_text_end) = .; #define IDMAP_TEXT \ ALIGN_FUNCTION(); \ VMLINUX_SYMBOL(__idmap_text_start) = .; \ - *(.idmap.text) \ + KEEP(*(.idmap.text)) \ VMLINUX_SYMBOL(__idmap_text_end) = .; \ . = ALIGN(PAGE_SIZE); \ VMLINUX_SYMBOL(__hyp_idmap_text_start) = .; \ - *(.hyp.idmap.text) \ + KEEP(*(.hyp.idmap.text)) \ VMLINUX_SYMBOL(__hyp_idmap_text_end) = .; #ifdef CONFIG_HOTPLUG_CPU @@ -134,7 +134,7 @@ SECTIONS __ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) { __start___ex_table = .; #ifdef CONFIG_MMU - *(__ex_table) + KEEP(*(__ex_table)) #endif __stop___ex_table = .; } @@ -171,14 +171,14 @@ SECTIONS */ __vectors_start = .; .vectors 0xffff0000 : AT(__vectors_start) { - *(.vectors) + KEEP(*(.vectors)) } . = __vectors_start + SIZEOF(.vectors); __vectors_end = .; __stubs_start = .; .stubs ADDR(.vectors) + 0x1000 : AT(__stubs_start) { - *(.stubs) + KEEP(*(.stubs)) } . = __stubs_start + SIZEOF(.stubs); __stubs_end = .; @@ -194,24 +194,24 @@ SECTIONS } .init.arch.info : { __arch_info_begin = .; - *(.arch.info.init) + KEEP(*(.arch.info.init)) __arch_info_end = .; } .init.tagtable : { __tagtable_begin = .; - *(.taglist.init) + KEEP(*(.taglist.init)) __tagtable_end = .; } #ifdef CONFIG_SMP_ON_UP .init.smpalt : { __smpalt_begin = .; - *(.alt.smp.init) + KEEP(*(.alt.smp.init)) __smpalt_end = .; } #endif .init.pv_table : { __pv_table_begin = .; - *(.pv_table) + KEEP(*(.pv_table)) __pv_table_end = .; } .init.data : { diff --git a/arch/arm/mach-fh/Kconfig b/arch/arm/mach-fh/Kconfig new file mode 100644 index 00000000..3518d065 --- /dev/null +++ b/arch/arm/mach-fh/Kconfig @@ -0,0 +1,142 @@ + +if ARCH_FULLHAN + +menu "Fullhan platform type" + + +menuconfig FH_FASTBOOT + bool "Fastboot configurations" + default n + help + Fullhan Fastboot configurations + +if FH_FASTBOOT +config DEFERRED_INIICALLS + bool "Enable deferred initcalls support" + default n + help + enable deferred initcalls, use deferred_initcall() to deferred some initcalls, + after kernel boot, use cat /proc/deferred_initcalls to run all deferred initcalls + +if DEFERRED_INIICALLS +config DEFERRED_INIICALLS_DEBUG + bool "Debug deferred initcalls" + default n + +config DEFERRED_INIICALLS_SLAB_SYSFS + bool "defer slab_sysfs_init" + default n + depends on SYSFS + +config DEFERRED_INIICALLS_IRQ_SYSFS + bool "defer irq_sysfs_init" + default n + depends on SYSFS + +config DEFERRED_INIICALLS_PARAM_SYSFS + bool "defer param_sysfs_init" + depends on SYSFS + default n + +config DEFERRED_INIICALLS_GMAC + bool "defer gmac driver init" + default n + depends on FH_GMAC=y + +config DEFERRED_INIICALLS_SPI + bool "defer spi driver init" + default n + depends on SPI_FH=y + +config DEFERRED_INIICALLS_MMC + bool "defer mmc driver init" + default n + depends on MMC_FH=y + +config DEFERRED_INIICALLS_USB + bool "defer usb driver init" + default n + depends on USB_DWC2=y + +config DEFERRED_INIICALLS_RTC + bool "defer rtc driver init" + default n + depends on RTC_DRV_FH=y +endif + +endif + +choice +prompt "Board" +config ARCH_FH885xV200 + bool "Fullhan FH885xV200" + select CPU_V6 + select FULLHAN_INTC + select FULLHAN_TIMER + select PINCTRL if USE_OF + help + Support for Fullhan FH885xV200 SoC + +endchoice +config FH_CHIP_NAME + string + prompt "Select chip name, keep default" + default "fh8856v200" if MACH_FH8856V200 + default "fh8852v200" if MACH_FH8852V200 + default "fh8858v200" if MACH_FH8858V200 + default "fh8856v210" if MACH_FH8856V210 + default "fh8852v210" if MACH_FH8852V210 + default "fh8858v210" if MACH_FH8858V210 + +config MACH_FH8856V200 + bool "FullHan FH8856V200 board" + default n + depends on ARCH_FH885xV200 + help + Configure this option to specify the whether the board used + for development is FH8856V200 + +config MACH_FH8852V200 + bool "FullHan FH8852V200 board" + default n + depends on ARCH_FH885xV200 + help + Configure this option to specify the whether the board used + for development is FH8852V200 + +config MACH_FH8858V200 + bool "FullHan FH8858V200 board" + default n + depends on ARCH_FH885xV200 + help + Configure this option to specify the whether the board used + for development is FH8858V200 + +config MACH_FH8856V210 + bool "FullHan FH8856V210 board" + default n + depends on ARCH_FH885xV200 + help + Configure this option to specify the whether the board used + for development is FH8856V210 + +config MACH_FH8852V210 + bool "FullHan FH8852V210 board" + default n + depends on ARCH_FH885xV210 + help + Configure this option to specify the whether the board used + for development is FH8852V200 + +config MACH_FH8858V210 + bool "FullHan FH8858V210 board" + default n + depends on ARCH_FH885xV200 + help + Configure this option to specify the whether the board used + for development is FH8858V210 + + +endmenu + +endif diff --git a/arch/arm/mach-fh/Makefile b/arch/arm/mach-fh/Makefile new file mode 100644 index 00000000..7f250d0c --- /dev/null +++ b/arch/arm/mach-fh/Makefile @@ -0,0 +1,12 @@ +CONFIG_FH_CHIP_NAME := $(subst ",,$(CONFIG_FH_CHIP_NAME)) +EXTRA_CFLAGS += -Iarch/arm/mach-fh/$(CONFIG_FH_CHIP_NAME) + +obj-y += pmu.o fullhan.o fh_common.o fh_chipid.o + +ifneq ($(CONFIG_USE_OF),y) +obj-y += pinctrl.o clock.o +obj-y += $(CONFIG_FH_CHIP_NAME)/ +endif + +obj-$(CONFIG_SMP) += platsmp.o hotplug.o +obj-$(CONFIG_ARM_FULLHAN_CPUIDLE) += cpuidle.o diff --git a/arch/arm/mach-fh/Makefile.boot b/arch/arm/mach-fh/Makefile.boot new file mode 100644 index 00000000..9703b95e --- /dev/null +++ b/arch/arm/mach-fh/Makefile.boot @@ -0,0 +1,3 @@ +zreladdr-y := 0xA0008000 +params_phys-y := 0xA0000100 +initrd_phys-y := 0xA0800000 \ No newline at end of file diff --git a/arch/arm/mach-fh/clock.c b/arch/arm/mach-fh/clock.c new file mode 100644 index 00000000..b41616b0 --- /dev/null +++ b/arch/arm/mach-fh/clock.c @@ -0,0 +1,741 @@ +/* + * Clock and PLL control for FH devices + * + * Copyright (C) 2014 Fullhan Microelectronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "soc.h" + + +#define PROC_FILE "driver/clock" + +static DEFINE_MUTEX(clocks_mutex); +static DEFINE_SPINLOCK(clocks_lock); + +struct proc_dir_entry *proc_file; + +struct fh_clk_divider { + struct clk_hw hw; + u32 reg; + u32 prediv; + u32 div_flag; + u32 div_reg_mask; + spinlock_t *lock; +}; +struct fh_clk_pllpr { + struct clk_hw hw; + u32 reg_ctrl0; + u32 reg_ctrl1; + u32 covpr_mask; + u32 flag; + spinlock_t *lock; +}; + +struct fh_clk_phase { + struct clk_hw hw; + u32 reg; + u32 mux; + spinlock_t *lock; +}; + +/*#define FH_CLK_DEBUG*/ +#define DIVVCO_ONE_DEVISION 0x0 +#define DIVVCO_TWO_DEVISION 0x8 +#define DIVVCO_FOUR_DEVISION 0xc +#define DIVVCO_EIGHT_DEVISION 0xd +#define DIVVCO_SIXTEEN_DEVISION 0xe +#define DIVVCO_THIRTYTWO_DEVISION 0xf + +static unsigned long fh_clk_get_pll_pr_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + unsigned int reg, m, n, p, r = 1; + unsigned int clk_vco, divvcop = 1, shift; + u32 rate; + struct fh_clk_pllpr *pllpr = (struct fh_clk_pllpr *)hw; + + reg = fh_pmu_get_reg(pllpr->reg_ctrl0); + + m = reg & 0x7f; + n = (reg >> 8) & 0x1f; + p = (reg >> 16) & 0x3f; + r = (reg >> 24) & 0x3f; + + /*pll databook*/ + if (m<4) + m=128+m; + + if (m==0xb) + m=0xa; + + shift = ffs(pllpr->covpr_mask)-1; + reg = fh_pmu_get_reg(pllpr->reg_ctrl1); + + switch ((reg&pllpr->covpr_mask)>>shift){ + case DIVVCO_ONE_DEVISION: + divvcop = 1; + break; + + case DIVVCO_TWO_DEVISION: + divvcop = 2; + break; + + case DIVVCO_FOUR_DEVISION: + divvcop = 4; + break; + + case DIVVCO_EIGHT_DEVISION: + divvcop = 8; + break; + + case DIVVCO_SIXTEEN_DEVISION: + divvcop = 16; + break; + + case DIVVCO_THIRTYTWO_DEVISION: + divvcop = 32; + break; + default: + pr_err("divvcop error:%x\n", divvcop); + } + + clk_vco = parent_rate * m / (n+1); + if (pllpr->flag & CLOCK_PLL_P) + rate = clk_vco / (p+1) / divvcop; + else + rate = clk_vco / (r+1) / divvcop; + return rate; +} +static const struct clk_ops clk_pll_pr_ops = { + .recalc_rate = fh_clk_get_pll_pr_rate, +}; + + +static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + unsigned int m = 0, n = 0, no = 1; + u32 reg; + u32 rate; + struct fh_clk_divider *div = (struct fh_clk_divider *)hw; + + /* Fetch the register value */ + reg = fh_pmu_get_reg(div->reg); + m = reg & 0xff; + n = ((reg & (0xf00)) >> 8); + no = ((reg & (0x30000)) >> 16); + rate = ((parent_rate) * m / n) >> no; + return rate; + +} + +static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) + { + unsigned int m = 0, n = 0, no = 1; + u32 reg; + struct fh_clk_divider *div = (struct fh_clk_divider *)hw; + + /* Fetch the register value */ + reg = fh_pmu_get_reg(div->reg); + m = reg & 0xff; + n = ((reg & (0xf00)) >> 8); + no = ((reg & (0x30000)) >> 16); + rate = ((*parent_rate) * m / n) >> no; + return rate; + + } + + +static const struct clk_ops clk_pll_ops = { + .recalc_rate = clk_pll_recalc_rate, + .round_rate = clk_pll_round_rate, +}; + +int fh_pll_clk_register(struct fh_clk *fh_clk) +{ + struct clk *clk; + const char *clk_name = fh_clk->name; + const char *parents[CLOCK_MAX_PARENT]; + struct fh_clk_divider *div = NULL; + int i = 0; + + /* if we have a mux, we will have >1 parents */ + while (i < CLOCK_MAX_PARENT && fh_clk->parent[i] != NULL) { + parents[i] = fh_clk->parent[i]->name; + i++; + } + div = kzalloc(sizeof(struct fh_clk_divider), GFP_KERNEL); + if (!div) + return 0; + div->reg = fh_clk->div_reg_offset; + clk = clk_register_composite(NULL, clk_name, + parents, i, + NULL, NULL, + &div->hw, &clk_pll_ops, + NULL, NULL, CLK_IGNORE_UNUSED); + if (!IS_ERR(clk)) + clk_register_clkdev(clk, clk_name, NULL); + return 1; + +} + +int fh_pll_pr_clk_register(struct fh_clk *fh_clk) +{ + struct clk *clk; + const char *clk_name = fh_clk->name; + const char *parents[CLOCK_MAX_PARENT]; + struct fh_clk_pllpr *pll_ctrl = NULL; + int i = 0; + + /* if we have a mux, we will have >1 parents */ + while (i < CLOCK_MAX_PARENT && fh_clk->parent[i] != NULL) { + parents[i] = fh_clk->parent[i]->name; + i++; + } + pll_ctrl = kzalloc(sizeof(struct fh_clk_pllpr), GFP_KERNEL); + if (!pll_ctrl) + return 0; + pll_ctrl->reg_ctrl0 = fh_clk->div_reg_offset; + pll_ctrl->reg_ctrl1 = fh_clk->en_reg_offset; + pll_ctrl->covpr_mask = fh_clk->en_reg_mask; + pll_ctrl->flag = fh_clk->flag; + clk = clk_register_composite(NULL, clk_name, + parents, i, + NULL, NULL, + &pll_ctrl->hw, &clk_pll_pr_ops, + NULL, NULL, CLK_IGNORE_UNUSED); + if (!IS_ERR(clk)) + clk_register_clkdev(clk, clk_name, NULL); + return 1; + +} + +static int fh_clk_set_phase(struct clk_hw *hw, + int degree) +{ + u32 reg; + struct fh_clk_phase *phase = (struct fh_clk_phase *)hw; + unsigned long flags = 0; + u32 local_degree = 0; + u32 shift = 0; + + /*printk("fh_clk_set_phase:%d\n",degree);*/ + if (phase->lock) + spin_lock_irqsave(phase->lock, flags); + + /* Fetch the register value */ + reg = fh_pmu_get_reg(phase->reg); + + local_degree = degree; + + shift = ffs(phase->mux)-1; + + reg |= (local_degree << shift); + + /* Apply them now */ + fh_pmu_set_reg(phase->reg, reg); + if (phase->lock) + spin_unlock_irqrestore(phase->lock, flags); + + return 1; +} + +static int fh_clk_get_phase(struct clk_hw *hw) +{ + u32 reg; + struct fh_clk_phase *phase = (struct fh_clk_phase *)hw; + unsigned long flags = 0; + u32 local_degree = 0; + u32 shift; + + if (phase->lock) + spin_lock_irqsave(phase->lock, flags); + + /* Fetch the register value */ + reg = fh_pmu_get_reg(phase->reg); + shift = ffs(phase->mux)-1; + + reg = reg&(phase->mux) >> shift; + local_degree = reg; + + /*printk("fh_clk_get_phase:%d\n",local_degree);*/ + + if (phase->lock) + spin_unlock_irqrestore(phase->lock, flags); + + return local_degree; +} + + +static const struct clk_ops fh_clk_phase_ops = { + .set_phase = fh_clk_set_phase, + .get_phase = fh_clk_get_phase, +}; + +int fh_phase_clk_register(struct fh_clk *fh_clk) +{ + struct clk *clk; + const char *clk_name = fh_clk->name; + const char *parents[CLOCK_MAX_PARENT]; + struct fh_clk_phase *clk_phase = NULL; + int i = 0; + struct clk_init_data *init = NULL; + + /* if we have a mux, we will have >1 parents */ + while (i < CLOCK_MAX_PARENT && fh_clk->parent[i] != NULL) { + parents[i] = fh_clk->parent[i]->name; + i++; + } + clk_phase = kzalloc(sizeof(struct fh_clk_phase), GFP_KERNEL); + if (!clk_phase) + return 0; + clk_phase->mux = fh_clk->sel_reg_mask; + init = kzalloc(sizeof(struct clk_init_data), GFP_KERNEL); + + /* set up gate properties */ + clk_phase->reg = fh_clk->sel_reg_offset; + clk_phase->lock = &clocks_lock; + init->ops = &fh_clk_phase_ops; + init->parent_names = parents; + init->num_parents = i; + init->name = clk_name; + clk_phase->hw.init = init; + clk = clk_register(NULL, &clk_phase->hw); + if (!IS_ERR(clk)) { + clk_register_clkdev(clk, clk_name, NULL); + } + return 1; + +} + + +int fh_fix_clk_register(struct fh_clk *fh_clk) +{ + struct clk *clk; + u32 out_values = fh_clk->frequency; + const char *clk_name = fh_clk->name; + + clk = clk_register_fixed_rate(NULL, clk_name, + NULL, + CLK_IS_ROOT, + out_values); + if (!IS_ERR(clk)) {; + clk_register_clkdev(clk, clk_name, NULL); + } + return 0; +} + +static unsigned long fh_clk_divide_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + u32 reg; + u32 divide = 0; + struct fh_clk_divider *factors = (struct fh_clk_divider *)hw; + unsigned long rate; + unsigned long shift; + unsigned long flags = 0; + + if (factors->lock) + spin_lock_irqsave(factors->lock, flags); + if (factors->div_flag) { + /* Fetch the register value */ + reg = fh_pmu_get_reg(factors->reg); + + /* Get each individual factor if applicable */ + shift = ffs(factors->div_reg_mask)-1; + divide = (factors->div_reg_mask & reg)>> shift; + + /* Calculate the rate */ + rate = (parent_rate) / (divide+1) / factors->prediv; + } else + rate = parent_rate / factors->prediv; + if (factors->lock) + spin_unlock_irqrestore(factors->lock, flags); + + return rate; +} + +static long fh_clk_divide_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + u32 reg; + u32 rount_rate = 0, divide; + struct fh_clk_divider *factors = (struct fh_clk_divider *)hw; + unsigned long flags = 0; + + if (factors->lock) + spin_lock_irqsave(factors->lock, flags); + + if (factors->div_flag) { + + /* Fetch the register value */ + reg = fh_pmu_get_reg(factors->reg); + + /* Calculate the rate */ + divide = (*parent_rate) / factors->prediv / rate; + rount_rate = (*parent_rate) / divide / factors->prediv; + } else + pr_err("fh_clk_divide_round_rate not support divide\n"); + + if (factors->lock) + spin_unlock_irqrestore(factors->lock, flags); + + return rount_rate; +} + +static int fh_clk_divide_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + u32 reg; + struct fh_clk_divider *factors = (struct fh_clk_divider *)hw; + u32 divide = 0; + unsigned long flags = 0; + unsigned long shift = 0; + + if (factors->lock) + spin_lock_irqsave(factors->lock, flags); + + + if (factors->div_flag) { + + /* Fetch the register value */ + reg = fh_pmu_get_reg(factors->reg); + + divide = parent_rate/rate/factors->prediv - 1; + /*printk("fh_clk_divide_set_rate:%x\n",divide);*/ + + shift = ffs(factors->div_reg_mask)-1; + + + reg &= ~(factors->div_reg_mask); + reg |= ((divide << shift) & factors->div_reg_mask); + + /* Apply them now */ + fh_pmu_set_reg(factors->reg,reg); + + } + if (factors->lock) + spin_unlock_irqrestore(factors->lock, flags); + + return 0; +} + + +static const struct clk_ops fh_clk_divider_ops = { + .recalc_rate = fh_clk_divide_recalc_rate, + .round_rate = fh_clk_divide_round_rate, + .set_rate = fh_clk_divide_set_rate, +}; + +int fh_complex_clk_register(struct fh_clk *fh_clk) +{ + struct clk *clk; + struct clk_gate *gate = NULL; + struct clk_hw *clk_mux_hw = NULL; + struct clk_mux *mux = NULL; + struct clk_hw *clk_gate_hw = NULL; + struct fh_clk_divider *div = NULL; + struct clk_hw *clk_divider_hw = NULL; + const char *clk_name; + const char *parents[CLOCK_MAX_PARENT]; + int i = 0; + + /* if we have a mux, we will have >1 parents */ + while (i < CLOCK_MAX_PARENT && fh_clk->parent[i] != NULL) { + parents[i] = fh_clk->parent[i]->name; + i++; + } + + clk_name = fh_clk->name; + /* Leaves can be fixed or configurable divisors */ + if ((!(fh_clk->flag & CLOCK_NODIV)) || (fh_clk->prediv > 1)) { + div = kzalloc(sizeof(struct fh_clk_divider), GFP_KERNEL); + if (!div) + return 0; + clk_divider_hw = &div->hw; + div->reg = fh_clk->div_reg_offset; + if(!(fh_clk->flag & CLOCK_NODIV)) + div->div_flag = 1; + div->div_reg_mask = fh_clk->div_reg_mask; + div->prediv = fh_clk->prediv; + div->lock = &clocks_lock; + } + + /* Add a gate if this factor clock can be gated */ + if (!(fh_clk->flag & CLOCK_NOGATE)) { + gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); + if (!gate) { + kfree(div); + return 0; + } + /* set up gate properties */ + gate->reg = (void __iomem *)(fh_clk->en_reg_offset + VA_PMU_REG_BASE); + gate->bit_idx =ffs(fh_clk->en_reg_mask)-1; + gate->lock = &clocks_lock; + gate->flags = CLK_GATE_SET_TO_DISABLE; + clk_gate_hw = &gate->hw; + } + + if (fh_clk->flag & CLOCK_MULTI_PARENT) { + mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL); + + + /* set up gate properties */ + mux->reg = (void __iomem *)(fh_clk->sel_reg_offset + VA_PMU_REG_BASE); + mux->shift = ffs(fh_clk->sel_reg_mask)-1; + mux->mask = fh_clk->sel_reg_mask>>mux->shift; + mux->lock = &clocks_lock; + clk_mux_hw = &mux->hw; + } + clk = clk_register_composite(NULL, clk_name, + parents, i, + clk_mux_hw, &clk_mux_ops, + clk_divider_hw, &fh_clk_divider_ops, + clk_gate_hw, &clk_gate_ops, CLK_IGNORE_UNUSED); + if (!IS_ERR(clk)) { + clk_register_clkdev(clk, clk_name, NULL); + } + return 1; +} + + +int fh_clk_register(struct fh_clk *clk) +{ + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + + if(clk->flag & CLOCK_PLL) { + fh_pll_clk_register(clk); + return 0; + } + if(clk->flag & (CLOCK_PLL_P|CLOCK_PLL_R)) { + fh_pll_pr_clk_register(clk); + return 0; + } + if(clk->flag & CLOCK_FIXED) { + fh_fix_clk_register(clk); + return 0; + } + if(clk->flag & CLOCK_PHASE) { + fh_phase_clk_register(clk); + return 0; + } + fh_complex_clk_register(clk); + return 0; +} +EXPORT_SYMBOL(fh_clk_register); + + +static void del_char(char* str, char ch) +{ + char *p = str; + char *q = str; + while (*q) { + if (*q != ch) { + *p++ = *q; + } + q++; + } + *p = '\0'; +} +static ssize_t fh_clk_proc_write(struct file *filp, const char *buf, size_t len, loff_t *off) +{ + int i, ret; + char message[64] = {0}; + char * const delim = ","; + char *cur = message; + char *param_str[4]; + unsigned int param[4]; + struct clk *clk; + + len = (len > 64) ? 64 : len; + + if (copy_from_user(message, buf, len)) + return -EFAULT; + + for (i = 0; i < 3; i++) { + param_str[i] = strsep(&cur, delim); + if (!param_str[i]) { + pr_err("%s: ERROR: parameter[%d] is empty\n", __func__, i); + pr_err("[clk name], [enable/disable], [clk rate]\n"); + return -EINVAL; + } else { + del_char(param_str[i], ' '); + del_char(param_str[i], '\n'); + } + } + + clk = clk_get(NULL, param_str[0]); + if (!clk || IS_ERR(clk)) { + pr_err("%s: ERROR: clk %s is not found\n", __func__, param_str[0]); + pr_err("[clk name], [enable/disable], [clk rate]\n"); + return -EINVAL; + } + + param[2] = (u32)simple_strtoul(param_str[2], NULL, 10); + if (param[2] < 0) { + pr_err("ERROR: parameter[2] is incorrect\n"); + return -EINVAL; + } + + if (!strcmp(param_str[1], "enable")) { + clk_prepare_enable(clk); + printk("clk %s enabled\n", param_str[0]); + } + else if (!strcmp(param_str[1], "disable")) { + clk_disable_unprepare(clk); + printk(KERN_ERR "clk %s disabled\n", param_str[0]); + return len; + } else { + pr_err("%s: ERROR: parameter[1]:%s is incorrect\n", + __func__, param_str[1]); + pr_err("[clk name], [enable/disable], [clk rate]\n"); + return -EINVAL; + } + + ret = clk_set_rate(clk, param[2]); + if (ret) + pr_err("set clk rate failed\n, ret=%d\n", ret); + + return len; +} + + +static void *v_seq_start(struct seq_file *s, loff_t *pos) +{ + static unsigned long counter = 0; + if (*pos == 0) + return &counter; + else { + *pos = 0; + return NULL; + } +} + +static void *v_seq_next(struct seq_file *s, void *v, loff_t *pos) +{ + (*pos)++; + return NULL; +} + +static void v_seq_stop(struct seq_file *s, void *v) +{ + +} + +static int v_seq_show(struct seq_file *sfile, void *v) +{ + + struct fh_clk *fh_clk; + struct clk *clk; + unsigned long rate; + unsigned int reg; + char gate[10] = {0}; + int i = 0; + seq_printf(sfile, "\nPLL Information: \n"); + for (; fh_clks[i]; i++) { + fh_clk = fh_clks[i]; + if (fh_clk->flag & CLOCK_HIDE) + continue; + clk = clk_get(NULL, fh_clk->name); + if (clk == NULL || IS_ERR(clk)) + continue; + rate = clk_get_rate(clk); + if (!(fh_clk->flag & CLOCK_NOGATE)) { + reg = fh_pmu_get_reg(fh_clk->en_reg_offset); + reg &= fh_clk->en_reg_mask; + if (reg) { + if (fh_clk->flag & (CLOCK_PLL_P|CLOCK_PLL_R)) + strncpy(gate, "enable", sizeof(gate)); + else + strncpy(gate, "disable", sizeof(gate)); + } else { + if (fh_clk->flag & (CLOCK_PLL_P|CLOCK_PLL_R)) + strncpy(gate, "disable", sizeof(gate)); + else + strncpy(gate, "enable", sizeof(gate)); + } + } else { + strncpy(gate, "nogate", sizeof(gate)); + } + seq_printf(sfile, "\t%-20s \t%9luHZ \t%-10s\n", + fh_clk->name, rate, gate); + clk_put(clk); +} + return 0; +} + +static const struct seq_operations fh_clk_seq_ops = { + .start = v_seq_start, + .next = v_seq_next, + .stop = v_seq_stop, + .show = v_seq_show +}; + +static int fh_clk_proc_open(struct inode *inode, struct file *file) +{ + return seq_open(file, &fh_clk_seq_ops); +} + + +static struct file_operations fh_clk_proc_ops = { + .owner = THIS_MODULE, + .open = fh_clk_proc_open, + .read = seq_read, + .write = fh_clk_proc_write, + .release = seq_release, +}; + +int __init fh_clk_procfs_init(void) +{ + proc_file = proc_create(PROC_FILE, 0644, NULL, &fh_clk_proc_ops); + if (!proc_file) + pr_err("clock, create proc fs failed\n"); + + return 0; +} +module_init(fh_clk_procfs_init); + +int __init fh_clk_init(void) +{ + struct fh_clk *fh_clk; + struct clk *clk; + int i = 0; + for (; fh_clks[i]; i++) { + fh_clk = fh_clks[i]; + fh_clk_register(fh_clk); + if (fh_clk->def_rate) { + clk = clk_get(NULL, fh_clk->name); + if(clk && !IS_ERR(clk)) { + clk_set_rate(clk, fh_clk->def_rate); + clk_put(clk); + } + } + } + return 0; +} diff --git a/arch/arm/mach-fh/core.h b/arch/arm/mach-fh/core.h new file mode 100644 index 00000000..1ac9a11d --- /dev/null +++ b/arch/arm/mach-fh/core.h @@ -0,0 +1,24 @@ +#ifndef __HISILICON_CORE_H +#define __HISILICON_CORE_H + +#include + +#define MPCORE_COH_MAGIC 0x434f484d +#define COH_MAGIC (0x0500) +#define COH_FUN_BASE (0x0504) +#define COH_FUN_PARAM (0x0508) + +#define OFFSET_LOWPOWER_CTRL (0x109c) + +extern void fhca7_set_cpu_jump(int cpu, void *jump_addr); +extern int fhca7_get_cpu_jump(int cpu); +extern void secondary_startup(void); + +extern void fhca7_cpu_die(unsigned int cpu); +extern int fhca7_cpu_kill(unsigned int cpu); +extern void fhca7_set_cpu(int cpu, bool enable); + +extern void fhca7_wakeup_cpu(unsigned int cpu); +extern void fhca7_shutdown_cpu(unsigned int cpu); + +#endif diff --git a/arch/arm/mach-fh/cpuidle.c b/arch/arm/mach-fh/cpuidle.c new file mode 100644 index 00000000..45668ba3 --- /dev/null +++ b/arch/arm/mach-fh/cpuidle.c @@ -0,0 +1,215 @@ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "core.h" + +enum { + CPU_OP_NONE = 0, + CPU_OP_DOWN = 1, + CPU_OP_UP = 2, +}; + +static int wait_for_cpu_up(unsigned int cpu); +static void cpu_op_task(struct work_struct *work); + +static void __iomem *pmu_base; +static void __iomem *intc_base; +static DECLARE_WORK(cpu_op_wq, cpu_op_task); +static atomic_t fh_cpu_op = ATOMIC_INIT(CPU_OP_NONE); + +void fhca7_wakeup_cpu(unsigned int cpu) +{ + if (!pmu_base) + return; + + if (atomic_read(&fh_cpu_op) == CPU_OP_NONE && cpu_is_offline(cpu)) { + pr_debug("cpu%u up\n", cpu); + atomic_set(&fh_cpu_op, CPU_OP_UP); + schedule_work_on(0, &cpu_op_wq); + } +} + +void fhca7_shutdown_cpu(unsigned int cpu) +{ + if (!pmu_base) + return; + + if (atomic_read(&fh_cpu_op) == CPU_OP_NONE && cpu_active(cpu)) { + pr_debug("cpu%u down\n", cpu); + atomic_set(&fh_cpu_op, CPU_OP_DOWN); + schedule_work_on(0, &cpu_op_wq); + } +} + +int fhca7_force_cpu_poweron(unsigned int cpu) +{ + int ret = 0; + + if (fhca7_get_cpu_jump(cpu) == 0) + return -EBUSY; + + /* force up */ + writel(0x00079444, pmu_base + OFFSET_LOWPOWER_CTRL); + + /* wait for cpu poweron and init done */ + ret = wait_for_cpu_up(cpu); + + if (ret) + pr_err("cpu%u poweron fail, timeout %d\n", cpu, ret); + + writel(0, pmu_base + OFFSET_LOWPOWER_CTRL); + return ret; +} + +void fhca7_wakeup_cpu_force(unsigned int cpu) +{ + if (pmu_base && cpu_is_offline(cpu)) { + if (!fhca7_force_cpu_poweron(cpu)) + fhca7_wakeup_cpu(cpu); + } +} + +static inline void fhca7_sencondary_cpu_do_idle(unsigned int cpu) +{ + fhca7_shutdown_cpu(cpu); + cpu_do_idle(); +} + +static inline void fhca7_cpu0_do_idle(unsigned int cpu) +{ + cpu_do_idle(); +} + +static void fhca7_cpu_idle(void) +{ + unsigned int cpu = smp_processor_id(); + if (cpu == 0) + fhca7_cpu0_do_idle(cpu); + else + fhca7_sencondary_cpu_do_idle(cpu); +} + +static int wait_for_cpu_up(unsigned int cpu) +{ + unsigned long timeout = jiffies + msecs_to_jiffies(50); + + while (fhca7_get_cpu_jump(cpu)) { + if (time_after(jiffies, timeout)) + return -1; + msleep(1); + } + + return 0; +} + +static void cpu_op_task(struct work_struct *work) +{ + int cpu = 1; + int ret = 0; + int cpu_op = atomic_read(&fh_cpu_op); + + if (cpu_op == CPU_OP_DOWN && cpu_active(cpu)) { + ret = cpu_down(cpu); + if (!ret) { + atomic_set(&fh_cpu_op, CPU_OP_NONE); + /* enable core 1 int wakeup */ + writel(0x00078444, pmu_base + OFFSET_LOWPOWER_CTRL); + } else { + pr_err("cpu%d down error %d\n", cpu, ret); + return; + } + } + else if (cpu_op == CPU_OP_UP && cpu_is_offline(cpu)) { + if (wait_for_cpu_up(cpu)) { + pr_err("wait for cpu%u up timeout\n", cpu); + return; + } + /* disable core 1 int wakeup */ + writel(0, pmu_base + OFFSET_LOWPOWER_CTRL); + ret = cpu_up(cpu); + if (!ret) { + atomic_set(&fh_cpu_op, CPU_OP_NONE); + } + else { + pr_err("cpu%d up error %d\n", cpu, ret); + writel(0x00078444, pmu_base + OFFSET_LOWPOWER_CTRL); + return; + } + } +} + +static int fhca7_cpuidle_enter(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index) +{ + fhca7_cpu_idle(); + return index; +} + +static struct cpuidle_driver fhca7_cpuidle_driver = { + .name = "fhca7_cpuidle", + .owner = THIS_MODULE, + .states[0] = { + .enter = fhca7_cpuidle_enter, + .exit_latency = 2, + .target_residency = 1, + .name = "fhca7 SRPG", + .desc = "CPU powered off", + }, + .state_count = 1, +}; + +static int __init fhca7_cpuidle_init(void) +{ + struct device_node *node, *idle_node; + struct clk *clk; + + node = of_find_compatible_node(NULL, NULL, "fh,fh-pmu"); + if (!node) { + return -ENOENT; + } + + pmu_base = of_iomap(node, 0); + of_node_put(node); + if (!pmu_base) { + return -ENOMEM; + } + + idle_node = of_find_compatible_node(NULL, NULL, "fh,fh-cpuidle"); + if (!idle_node) { + return -ENOENT; + } + + clk = of_clk_get_by_name(idle_node, "intc"); + if (IS_ERR(clk)) { + pr_err("failed to get intc clk\n"); + return PTR_ERR(clk); + } + else + clk_prepare_enable(clk); + + intc_base = of_iomap(idle_node, 0); + of_node_put(idle_node); + if (!intc_base) { + return -ENOMEM; + } + + /* enable timer, wdt int */ + writel_relaxed(0xc, intc_base); + + arm_pm_idle = fhca7_cpu_idle; + + return cpuidle_register(&fhca7_cpuidle_driver, NULL); +} + +late_initcall(fhca7_cpuidle_init); diff --git a/arch/arm/mach-fh/fh8852v200/Makefile b/arch/arm/mach-fh/fh8852v200/Makefile new file mode 100644 index 00000000..1443fdae --- /dev/null +++ b/arch/arm/mach-fh/fh8852v200/Makefile @@ -0,0 +1 @@ +obj-y += board.o chip.o \ No newline at end of file diff --git a/arch/arm/mach-fh/fh8852v200/board.c b/arch/arm/mach-fh/fh8852v200/board.c new file mode 100644 index 00000000..4d96fee2 --- /dev/null +++ b/arch/arm/mach-fh/fh8852v200/board.c @@ -0,0 +1,1166 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +struct uart_port fh_serial_ports[FH_UART_NUMBER]; + +static struct map_desc fh8852v200_io_desc[] = { + { + .virtual = VA_RAM_REG_BASE, + .pfn = __phys_to_pfn(RAM_BASE), + .length = SZ_16K, + .type = MT_MEMORY_RWX, + }, + { + .virtual = VA_DDRC_REG_BASE, + .pfn = __phys_to_pfn(DDRC_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_INTC_REG_BASE, + .pfn = __phys_to_pfn(INTC_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_TIMER_REG_BASE, + .pfn = __phys_to_pfn(TIMER_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_PMU_REG_BASE, + .pfn = __phys_to_pfn(PMU_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_UART0_REG_BASE, + .pfn = __phys_to_pfn(UART0_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_UART1_REG_BASE, + .pfn = __phys_to_pfn(UART1_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_UART2_REG_BASE, + .pfn = __phys_to_pfn(UART2_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + +}; + +static struct resource fh_gpio0_resources[] = { + { + .start = GPIO0_REG_BASE, + .end = GPIO0_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = GPIO0_IRQ, + .end = GPIO0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_gpio1_resources[] = { + { + .start = GPIO1_REG_BASE, + .end = GPIO1_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = GPIO1_IRQ, + .end = GPIO1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_uart0_resources[] = { + { + .start = (UART0_REG_BASE), + .end = (UART0_REG_BASE) + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = UART0_IRQ, + .end = UART0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_uart1_resources[] = { + { + .start = (UART1_REG_BASE), + .end = (UART1_REG_BASE) + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = UART1_IRQ, + .end = UART1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_uart2_resources[] = { + { + .start = (UART2_REG_BASE), + .end = (UART2_REG_BASE) + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = UART2_IRQ, + .end = UART2_IRQ, + .flags = IORESOURCE_IRQ, + } +}; +static struct resource fh_sdc0_resources[] = { + { + .start = SDC0_REG_BASE, + .end = SDC0_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SDC0_IRQ, + .end = SDC0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_sdc1_resources[] = { + { + .start = SDC1_REG_BASE, + .end = SDC1_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SDC1_IRQ, + .end = SDC1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_gmac_resources[] = { + { + .start = GMAC_REG_BASE, + .end = GMAC_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = GMAC_IRQ, + .end = GMAC_IRQ, + .flags = IORESOURCE_IRQ, + } +}; + +static struct resource fh_wdt_resources[] = { + { + .start = WDT_REG_BASE, + .end = WDT_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = WDT_IRQ, + .end = WDT_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +#ifdef CONFIG_FH_PERF_MON +static struct resource fh_perf_resources[] = { + { + .start = PMU_REG_BASE, + .end = PMU_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = PERF_IRQ, + .end = PERF_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +#endif + + +static struct fh_gmac_platform_data fh_gmac_data = { + .phy_reset_pin = 29, +}; + +static struct fh_uart_dma uart1_dma_info = { +#ifdef CONFIG_UART_TX_DMA + .tx_hs_no = UART1_TX_HW_HANDSHAKE, + .tx_dma_channel = UART1_DMA_TX_CHAN, +#endif + .rx_hs_no = UART1_RX_HW_HANDSHAKE, + .rx_dma_channel = UART1_DMA_RX_CHAN, + .rx_xmit_len = 16, +}; + +static struct fh_uart_dma uart2_dma_info = { +#ifdef CONFIG_UART_TX_DMA + .tx_hs_no = UART2_TX_HW_HANDSHAKE, + .tx_dma_channel = UART2_DMA_TX_CHAN, +#endif + .rx_hs_no = UART2_RX_HW_HANDSHAKE, + .rx_dma_channel = UART2_DMA_RX_CHAN, + .rx_xmit_len = 16, +}; + + +static struct fh_platform_uart fh_uart_platform_data[] = { + { + .mapbase = UART0_REG_BASE, + .fifo_size = 16, + .irq = UART0_IRQ, + .uartclk = 16666667, + .use_dma = 0, + .dma_info = NULL, + }, + { + .mapbase = UART1_REG_BASE, + .fifo_size = 32, + .irq = UART1_IRQ, + .uartclk = 16666667, + .use_dma = 0, + .dma_info = &uart1_dma_info, + }, + { + .mapbase = UART2_REG_BASE, + .fifo_size = 32, + .irq = UART2_IRQ, + .uartclk = 16666667, + .use_dma = 0, + .dma_info = &uart2_dma_info, + }, +}; + +static struct resource fh_pwm_resources[] = { + { + .start = PWM_REG_BASE, + .end = PWM_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = PWM_IRQ, + .end = PWM_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_i2c_resources_0[] = { + { + .start = I2C0_REG_BASE, + .end = I2C0_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = I2C0_IRQ, + .end = I2C0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_i2c_resources_1[] = { + { + .start = I2C1_REG_BASE, + .end = I2C1_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = I2C1_IRQ, + .end = I2C1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_i2c_resources_2[] = { + { + .start = I2C2_REG_BASE, + .end = I2C2_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = I2C2_IRQ, + .end = I2C2_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_rtc_resources[] = { + { + .start = RTC_REG_BASE, + .end = RTC_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = RTC_IRQ, + .end = RTC_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct fh_gpio_chip fh_gpio0_chip = { + .chip = { + .owner = THIS_MODULE, + .label = "FH_GPIO0", + .base = 0, + .ngpio = 32, + }, +}; + +static struct fh_gpio_chip fh_gpio1_chip = { + .chip = { + .owner = THIS_MODULE, + .label = "FH_GPIO1", + .base = 32, + .ngpio = 32, + }, +}; + +static struct fh_pwm_data pwm_data = { + .npwm = 12, +}; + +static struct resource fh_sadc_resources[] = { + { + .start = SADC_REG_BASE, + .end = SADC_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SADC_IRQ, + .end = SADC_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_aes_resources[] = { + { + .start = AES_REG_BASE, + .end = AES_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = AES_IRQ, + .end = AES_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_efuse_resources[] = { + { + .start = EFUSE_REG_BASE, + .end = EFUSE_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +#ifdef CONFIG_FH_DMAC +static struct resource fh_dma_resources[] = { + { + .start = (DMAC_REG_BASE), + .end = (DMAC_REG_BASE) + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = DMAC0_IRQ, + .end = DMAC0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +#endif + +#ifdef CONFIG_FH_AXI_DMAC +static struct resource fh_axi_dma_resources[] = { + { + .start = (DMAC_REG_BASE), + .end = (DMAC_REG_BASE) + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = DMAC0_IRQ, + .end = DMAC0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +#endif + +static struct resource fh_spi0_resources[] = { + { + .start = SPI0_REG_BASE, + .end = SPI0_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SPI0_IRQ, + .end = SPI0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_spi1_resources[] = { + { + .start = SPI1_REG_BASE, + .end = SPI1_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SPI1_IRQ, + .end = SPI1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_spi2_resources[] = { + { + .start = SPI2_REG_BASE, + .end = SPI2_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + .name = "fh spi2 mem", + }, + { + .start = SPI2_IRQ, + .end = SPI2_IRQ, + .flags = IORESOURCE_IRQ, + .name = "fh spi2 irq", + }, +}; + +static struct resource fh_usb_resources[] = { + { + .start = USBC_REG_BASE, + .end = USBC_REG_BASE + SZ_1M - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = USBC_IRQ, + .end = USBC_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static unsigned int fh_mci_sys_card_detect_fixed(struct fhmci_host *host) +{ + return 0; +} + +struct fh_mci_board fh_mci = { + .num_slots = 1, + .get_cd = fh_mci_sys_card_detect_fixed, + .bus_hz = 50000000, + .detect_delay_ms = 200, + .caps = MMC_CAP_4_BIT_DATA, + /*8:180 degree*/ + .drv_degree = 8, + .sam_degree = 0, + .rescan_max_num = 2, +}; + +struct fh_mci_board fh_mci_sd = { + .num_slots = 1, + .bus_hz = 50000000, + .detect_delay_ms = 200, + .caps = MMC_CAP_4_BIT_DATA, + /*8:180 degree*/ + .drv_degree = 8, + .sam_degree = 0, +}; + +static struct platform_device fh_gmac_device = { + .name = "fh_gmac", + .id = 0, + .num_resources = ARRAY_SIZE(fh_gmac_resources), + .resource = fh_gmac_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &fh_gmac_data, + }, +}; + +struct platform_device fh_sd0_device = { + .name = "fh_mci", + .id = 0, + .num_resources = ARRAY_SIZE(fh_sdc0_resources), + .resource = fh_sdc0_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &fh_mci_sd, + } +}; + +struct platform_device fh_sd1_device = { + .name = "fh_mci", + .id = 1, + .num_resources = ARRAY_SIZE(fh_sdc1_resources), + .resource = fh_sdc1_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &fh_mci, + } +}; + +struct fh_sadc_platform_data fh_sadc_data = { + .ref_vol = 1800, + .active_bit = 0xfff, +}; + +static struct platform_device fh_sadc_device = { + .name = "fh_sadc", + .id = 0, + .num_resources = ARRAY_SIZE(fh_sadc_resources), + .resource = fh_sadc_resources, + .dev = { + .platform_data = &fh_sadc_data, + }, +}; + +static struct platform_device fh_uart0_device = { + .name = "ttyS", + .id = 0, + .num_resources = ARRAY_SIZE(fh_uart0_resources), + .resource = fh_uart0_resources, + .dev.platform_data = &fh_uart_platform_data[0], +}; + +static struct platform_device fh_uart1_device = { + .name = "ttyS", + .id = 1, + .num_resources = ARRAY_SIZE(fh_uart1_resources), + .resource = fh_uart1_resources, + .dev.platform_data = &fh_uart_platform_data[1], +}; + +static struct platform_device fh_uart2_device = { + .name = "ttyS", + .id = 2, + .num_resources = ARRAY_SIZE(fh_uart2_resources), + .resource = fh_uart2_resources, + .dev.platform_data = &fh_uart_platform_data[2], +}; + +static struct platform_device fh_pinctrl_device = { + .name = "fh_pinctrl", + .id = 0, +}; + +static struct platform_device fh_i2c0_device = { + .name = "fh_i2c", + .id = 0, + .num_resources = ARRAY_SIZE(fh_i2c_resources_0), + .resource = fh_i2c_resources_0, +}; + +static struct platform_device fh_i2c1_device = { + .name = "fh_i2c", + .id = 1, + .num_resources = ARRAY_SIZE(fh_i2c_resources_1), + .resource = fh_i2c_resources_1, +}; + +static struct platform_device fh_i2c2_device = { + .name = "fh_i2c", + .id = 2, + .num_resources = ARRAY_SIZE(fh_i2c_resources_2), + .resource = fh_i2c_resources_2, +}; + +static struct fh_rtc_plat_data rtc_plat_data[] = { + { + .lut_cof = 58, + .lut_offset = 0xff, + .tsensor_cp_default_out = 0x993, + .clk_name = "rtc_hclk_gate", + }, + { + .lut_cof = 71, + .lut_offset = 0xf6, + .tsensor_cp_default_out = 0x9cc, + .clk_name = "rtc_hclk_gate", + } +}; + +static struct platform_device fh_rtc_device = { + .name = "fh_rtc", + .id = 0, + .num_resources = ARRAY_SIZE(fh_rtc_resources), + .resource = fh_rtc_resources, + .dev.platform_data = &rtc_plat_data[0], +}; + +static struct resource fh_i2s_resources[] = { + { + .start = I2S_REG_BASE, + .end = I2S_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = ACW_REG_BASE, + .end = ACW_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = I2S0_IRQ, + .end = I2S0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct fh_i2s_platform_data fh_i2s_data = { + .dma_capture_channel = 4, + .dma_playback_channel = 5, + .dma_master = 0, + .dma_rx_hs_num = 10, + .dma_tx_hs_num = 11, + .clk = "i2s_clk", + .acodec_mclk = "ac_clk", +}; + +static struct platform_device fh_i2s_device = { + .name = "fh_audio", + .id = 0, + .num_resources = ARRAY_SIZE(fh_i2s_resources), + .resource = fh_i2s_resources, + .dev = { + .platform_data = &fh_i2s_data, + }, +}; + +static struct platform_device fh_gpio0_device = { + .name = GPIO_NAME, + .id = 0, + .num_resources = ARRAY_SIZE(fh_gpio0_resources), + .resource = fh_gpio0_resources, + .dev = { + .platform_data = &fh_gpio0_chip, + }, +}; + +static struct platform_device fh_gpio1_device = { + .name = GPIO_NAME, + .id = 1, + .num_resources = ARRAY_SIZE(fh_gpio1_resources), + .resource = fh_gpio1_resources, + .dev = { + .platform_data = &fh_gpio1_chip, + }, +}; + +static struct platform_device fh_aes_device = { + .name = "fh_aes", + .id = 0, + .num_resources = ARRAY_SIZE(fh_aes_resources), + .resource = fh_aes_resources, + .dev = { + .platform_data = NULL, + }, +}; + +struct fh_efuse_platform_data fh_efuse_plat_data = { + .efuse_support_flag = CRYPTO_CPU_SET_KEY | + CRYPTO_EX_MEM_SET_KEY | + CRYPTO_EX_MEM_SWITCH_KEY | + CRYPTO_EX_MEM_4_ENTRY_1_KEY | + CRYPTO_EX_MEM_INDEP_POWER, +}; + + + +#define FH_SPI0_CS0 (6) +#define FH_SPI0_CS1 (55) + +#define FH_SPI1_CS0 (14) +#define FH_SPI1_CS1 (57) + +#define SPI0_FIFO_DEPTH (128) +#define SPI0_CLK_IN (200000000) +#define SPI0_MAX_SLAVE_NO (2) +#define SPI0_DMA_RX_CHANNEL (0) +#define SPI0_DMA_TX_CHANNEL (1) + +#define SPI1_FIFO_DEPTH (64) +#define SPI1_CLK_IN (100000000) +#define SPI1_MAX_SLAVE_NO (2) +#define SPI1_DMA_RX_CHANNEL (2) +#define SPI1_DMA_TX_CHANNEL (3) + +#define SPI2_CLK_IN (100000000) + +/* SPI_TRANSFER_USE_DMA */ +static struct fh_spi_platform_data fh_spi0_data = { + .bus_no = 0, + .apb_clock_in = SPI0_CLK_IN, + .clock_source = {100000000, 150000000, 200000000}, + .clock_source_num = 3, + .slave_max_num = SPI0_MAX_SLAVE_NO, + .cs_data[0].GPIO_Pin = FH_SPI0_CS0, + .cs_data[0].name = "spi0_cs0", + .cs_data[1].GPIO_Pin = FH_SPI0_CS1, + .cs_data[1].name = "spi0_cs1", + .clk_name = "spi0_clk", + .dma_transfer_enable = SPI_TRANSFER_USE_DMA, + .rx_dma_channel = SPI0_DMA_RX_CHANNEL, + .rx_handshake_num = 4, + /*dma use inc mode could move data by burst mode...*/ + /*or move data use single mode with low efficient*/ + .ctl_wire_support = ONE_WIRE_SUPPORT | DUAL_WIRE_SUPPORT | + MULTI_WIRE_SUPPORT, +}; + +static struct fh_spi_platform_data fh_spi1_data = { + .bus_no = 1, + .apb_clock_in = SPI1_CLK_IN, + .clock_source = {SPI1_CLK_IN}, + .clock_source_num = 1, + .slave_max_num = SPI1_MAX_SLAVE_NO, + .cs_data[0].GPIO_Pin = FH_SPI1_CS0, + .cs_data[0].name = "spi1_cs0", + .cs_data[1].GPIO_Pin = FH_SPI1_CS1, + .cs_data[1].name = "spi1_cs1", + .clk_name = "spi1_clk", + .ctl_wire_support = 0, +}; + +static struct fh_spi_platform_data fh_spi2_data = { + .apb_clock_in = SPI2_CLK_IN, + .dma_transfer_enable = 0, + .rx_handshake_num = 12, + .clk_name = "spi2_clk", + .ctl_wire_support = 0, +}; + +static struct platform_device fh_efuse_device = { + .name = "fh_efuse", + .id = 0, + .num_resources = ARRAY_SIZE(fh_efuse_resources), + .resource = fh_efuse_resources, + .dev = { + .platform_data = &fh_efuse_plat_data, + }, +}; + +#ifdef CONFIG_FH_DMAC +static struct fh_dma_platform_data fh_dma_data = { + .chan_priority = CHAN_PRIORITY_ASCENDING, + .nr_channels = 6, + .clk_name = "ahb_clk", +}; + +static struct platform_device fh_dma_device = { + .name = "fh_dmac", + .id = 0, + .num_resources = ARRAY_SIZE(fh_dma_resources), + .resource = fh_dma_resources, + .dev = { + .platform_data = &fh_dma_data, + }, +}; +#endif + +#ifdef CONFIG_FH_AXI_DMAC +struct fh_axi_dma_platform_data axi_dma_plat_data = { + .chan_priority = CHAN_PRIORITY_ASCENDING, + .clk_name = "ahb_clk", +}; + +static struct platform_device fh_axi_dma_device = { + .name = "fh_axi_dmac", + .id = 0, + .num_resources = ARRAY_SIZE(fh_axi_dma_resources), + .resource = fh_axi_dma_resources, + .dev = { + .platform_data = &axi_dma_plat_data, + }, +}; +#endif + + + +static struct platform_device fh_spi0_device = { + .name = "fh_spi", + .id = 0, + .num_resources = ARRAY_SIZE(fh_spi0_resources), + .resource = fh_spi0_resources, + .dev = { + .platform_data = &fh_spi0_data, + }, +}; + +static struct platform_device fh_spi1_device = { + .name = "fh_spi", + .id = 1, + .num_resources = ARRAY_SIZE(fh_spi1_resources), + .resource = fh_spi1_resources, + .dev = { + .platform_data = &fh_spi1_data, + }, +}; + +static struct platform_device fh_spi2_device = { + .name = "fh_spi_slave", + .id = 0, + .num_resources = ARRAY_SIZE(fh_spi2_resources), + .resource = fh_spi2_resources, + .dev = { + .platform_data = &fh_spi2_data, + }, +}; + +#ifdef CONFIG_FH_PERF_MON +static struct platform_device fh_perf_device = { + .name = "fh_perf_mon", + .id = 0, + .num_resources = ARRAY_SIZE(fh_perf_resources), + .resource = fh_perf_resources, + .dev = { + .platform_data = NULL, + }, +}; +#endif + +static struct fh_wdt_platform_data fh_wdt_data = { + .mode = MODE_DISCRETE, +}; + +struct platform_device fh_wdt_device = { + .name = "fh_wdt", + .id = 0, + .num_resources = ARRAY_SIZE(fh_wdt_resources), + .resource = fh_wdt_resources, + .dev = { + .platform_data = &fh_wdt_data, + } +}; + +static struct platform_device fh_pwm_device = { + .name = "fh_pwm", + .id = 0, + .num_resources = ARRAY_SIZE(fh_pwm_resources), + .resource = fh_pwm_resources, + .dev = { + .platform_data = &pwm_data, + }, +}; + +static struct fh_usb_platform_data fh_usb_data = { + .dr_mode = "host", + .vbus_pwren = 47, +}; + +struct platform_device fh_usb_device = { + .name = "fh_usb", + .id = 0, + .num_resources = ARRAY_SIZE(fh_usb_resources), + .resource = fh_usb_resources, + .dev = { + .platform_data = &fh_usb_data, + } +}; + +#ifdef CONFIG_FH_TSENSOR +struct platform_device fh_tsensor_device = { + .name = "fh_tsensor", + .id = 0, +}; +#endif + +static struct platform_device *fh8852v200_devices[] __initdata = { + &fh_uart0_device, + &fh_uart1_device, + &fh_uart2_device, + &fh_pinctrl_device, + &fh_i2c0_device, + &fh_i2c1_device, + &fh_i2c2_device, + &fh_rtc_device, + &fh_sd0_device, + &fh_sd1_device, + &fh_sadc_device, + &fh_gmac_device, + &fh_gpio0_device, + &fh_gpio1_device, + &fh_aes_device, + &fh_efuse_device, +#ifdef CONFIG_FH_DMAC + &fh_dma_device, +#endif +#ifdef CONFIG_FH_AXI_DMAC + &fh_axi_dma_device, +#endif + &fh_spi0_device, + &fh_spi1_device, + &fh_spi2_device, + &fh_i2s_device, + &fh_pwm_device, + &fh_wdt_device, + &fh_usb_device, +#ifdef CONFIG_FH_PERF_MON + &fh_perf_device, +#endif +#ifdef CONFIG_FH_TSENSOR + &fh_tsensor_device, +#endif +}; + +static struct mtd_partition fh_sf_parts[] = { + { + /* head & Ramboot */ + .name = "bootstrap", + .offset = 0, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + /* Ramboot & U-Boot environment */ + .name = "uboot-env", + .offset = MTDPART_OFS_APPEND, + .size = SZ_64K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + /* U-Boot */ + .name = "uboot", + .offset = MTDPART_OFS_APPEND, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_4M, + .mask_flags = 0, + }, { + .name = "rootfs", + .offset = MTDPART_OFS_APPEND, + .size = SZ_8M, + .mask_flags = 0, + }, { + .name = "app", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + } + /* mtdparts= + * spi_flash:256k(bootstrap), + * 64k(u-boot-env), + * 192k(u-boot),4M(kernel), + * 8M(rootfs), + * -(app) */ + /* two blocks with bad block table (and mirror) at the end */ +}; +#ifdef CONFIG_MTD_SPI_NAND +static struct mtd_partition fh_sf_nand_parts[] = { + { + /* head & Ramboot */ + .name = "bootstrap", + .offset = 0, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + .name = "uboot-env", + .offset = MTDPART_OFS_APPEND, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "uboot", + .offset = MTDPART_OFS_APPEND, + .size = SZ_512K, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_4M, + .mask_flags = 0, + }, { + .name = "rootfs", + .offset = MTDPART_OFS_APPEND, + .size = SZ_8M, + .mask_flags = 0, + }, { + .name = "app", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + } + /* mtdparts= + * spi0.0:64k(bootstrap), + * 64k(u-boot-env), + * 192k(u-boot), + * 4M(kernel), + * 8M(rootfs), + * -(app) + * two blocks with bad block table (and mirror) at the end + */ +}; +#endif + +static struct flash_platform_data fh_flash_platform_data = { + .name = "spi_flash", + .parts = fh_sf_parts, + .nr_parts = ARRAY_SIZE(fh_sf_parts), +}; +#ifdef CONFIG_MTD_SPI_NAND +static struct flash_platform_data fh_nandflash_platform_data = { + .name = "spi_nandflash", + .parts = fh_sf_nand_parts, + .nr_parts = ARRAY_SIZE(fh_sf_nand_parts), +}; +#endif + +static struct spi_board_info fh_spi_devices[] = { +#ifdef CONFIG_MTD_SPI_NAND + { + .modalias = "spi-nand", + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 50000000, + .mode = SPI_MODE_3, + .platform_data = &fh_nandflash_platform_data, + }, +#endif + { + .modalias = "m25p80", + .bus_num = 0, + .chip_select = 0, + /* multi wire should adapt spi para 'ctl_wire_support'*/ + .mode = SPI_MODE_3 | SPI_RX_DUAL, + .max_speed_hz = 50000000, + .platform_data = &fh_flash_platform_data, + }, + +}; + +extern void early_print(const char *str, ...); + +static void __init fh_console_pre_init(struct fh_platform_uart *plat, int num) +{ + int idx = 0; + + for (; idx < num; idx++) { + struct uart_port *port; + + port = &fh_serial_ports[idx]; + port->mapbase = plat[idx].mapbase; + port->fifosize = plat[idx].fifo_size; + port->uartclk = plat[idx].uartclk; + + switch (idx) { + case 0: + port->membase = (unsigned char *)VA_UART0_REG_BASE; + break; + case 1: + port->membase = (unsigned char *)VA_UART1_REG_BASE; + break; + case 2: + port->membase = (unsigned char *)VA_UART2_REG_BASE; + break; + default: + break; + } + } +} + +static void __init fh8852v200_map_io(void) +{ + iotable_init(fh8852v200_io_desc, ARRAY_SIZE(fh8852v200_io_desc)); + fh_console_pre_init(fh_uart_platform_data, + ARRAY_SIZE(fh_uart_platform_data)); +} + + +static __init void fh8852v200_board_init(void) +{ + if (fh_is_8852v210()) + fh_rtc_device.dev.platform_data = &rtc_plat_data[1]; + platform_add_devices(fh8852v200_devices, + ARRAY_SIZE(fh8852v200_devices)); + spi_register_board_info(fh_spi_devices, ARRAY_SIZE(fh_spi_devices)); +} +void __init fh_timer_init_no_of(unsigned int iovbase, + unsigned int irqno); + +static void __init fh8852v200_init_early(void) +{ + fh_pmu_init(); + fh_pinctrl_init(VA_PMU_REG_BASE + 0x80); +} + +static void __init fh_time_init(void) +{ + unsigned int vtimerbase = (unsigned int)ioremap(TIMER_REG_BASE, SZ_4K); + + fh_clk_init(); + fh_timer_init_no_of(vtimerbase, TMR0_IRQ); + +} + +void __init fh_intc_init_no_of(unsigned int iovbase); +static void __init fh_intc_init(void) +{ + unsigned int vintcbase = (unsigned int)ioremap(INTC_REG_BASE, SZ_4K); + + fh_intc_init_no_of(vintcbase); + +} + +static void fh8852v200_restart + (enum reboot_mode mode, const char *cmd) +{ + fh_pmu_restart(); +} + + +MACHINE_START(FH8852V200, "FH8852V200") + .atag_offset = 0x100, + .map_io = fh8852v200_map_io, + .init_irq = fh_intc_init, + .init_time = fh_time_init, + .init_machine = fh8852v200_board_init, + .init_early = fh8852v200_init_early, + .restart = fh8852v200_restart, +MACHINE_END + diff --git a/arch/arm/mach-fh/fh8852v200/board_config.fh8852v200.appboard b/arch/arm/mach-fh/fh8852v200/board_config.fh8852v200.appboard new file mode 100644 index 00000000..02dae328 --- /dev/null +++ b/arch/arm/mach-fh/fh8852v200/board_config.fh8852v200.appboard @@ -0,0 +1,44 @@ +#ifndef BOARD_CONFIG_H_ +#define BOARD_CONFIG_H_ + +/* + * GPIO0 -> IRCUT_ON + * GPIO1 -> IRCUT_OFF + * GPIO2 -> USB_PWREN + * GPIO11 -> EMAC PHY Reset + * GPIO12 -> CIS_CLK + * GPIO13 -> CIS_RSTN + * GPIO14 -> CIS_PDN + * GPIO19 -> SD1_PWREN/WIFI_REG_ON + * GPIO20 -> AK7755 Reset + * GPIO24 -> LED0 + * GPIO25 -> LED1 + * GPIO26 -> Reset Configs + * GPIO27 -> AK7755 PowerDown + * GPIO28 -> IR + * GPIO53 -> USB_PWREN/SD0_PWREN + * GPIO55 -> SD1 WIFI Interrupt + */ + +#define CONFIG_SD_CD_FIXED + +#define CONFIG_ISP_CLK_RATE 171000000 +#define CONFIG_JPEG_CLK_RATE 171000000 +#define CONFIG_VEU_CLK_RATE 240000000 + +#define USB_VBUS_PWR_GPIO (47) + +#define CONFIG_PINCTRL_SELECT \ + "ETH", "I2C0", "PWM2", "PWM3", "PWM4", "PWM5", "PWM6", \ + "PWM7", "PWM8", "PWM9", "SADC_XAIN0", "SADC_XAIN1", \ + "SD0_NO_WP", "SENSOR_CLK", "SSI0_4BIT", "UART0", \ + "UART1", "GPIO4", "GPIO13", "GPIO30", "GPIO31", \ + "GPIO32", "GPIO43", "GPIO44", "GPIO47", \ +\ + "GPIO11", "GPIO14", "GPIO15", "GPIO16", "GPIO24", \ + "GPIO25", "GPIO45", "GPIO46", "GPIO48", "GPIO49", \ + "GPIO50", "GPIO51", "GPIO52", "GPIO53", "GPIO54", \ + "GPIO55", "GPIO56", "GPIO57", "GPIO58", "GPIO59", \ + "GPIO60", "GPIO61", "GPIO62", "GPIO63" + +#endif /* BOARD_CONFIG_H_ */ diff --git a/arch/arm/mach-fh/fh8852v200/chip.c b/arch/arm/mach-fh/fh8852v200/chip.c new file mode 100644 index 00000000..9bbb3c49 --- /dev/null +++ b/arch/arm/mach-fh/fh8852v200/chip.c @@ -0,0 +1,747 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * external oscillator + * fixed to 24M + */ +static struct fh_clk osc_clk = { + .name = "osc_clk", + .frequency = OSC_FREQUENCY, + .flag = CLOCK_FIXED, +}; + +/* + * phase-locked-loop device, + * generates a higher frequency clock + * from the external oscillator reference + *PLL_DDR + */ + +static struct fh_clk pll_ddr_rclk = { + .name = "pll_ddr_rclk", + .flag = CLOCK_PLL_R|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL0, + .en_reg_offset = REG_PMU_PLL0_CTRL, + .en_reg_mask = 0xf000, +}; + +/*PLL_CPU*/ +static struct fh_clk pll_cpu_pclk = { + .name = "pll_cpu_pclk", + .flag = CLOCK_PLL_P|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL1, + .en_reg_offset = REG_PMU_PLL1_CTRL, + .en_reg_mask = 0xf00, +}; + +static struct fh_clk pll_cpu_rclk = { + .name = "pll_cpu_rclk", + .flag = CLOCK_PLL_R|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL1, + .en_reg_offset = REG_PMU_PLL1_CTRL, + .en_reg_mask = 0xf000, +}; + +/*PLL_SYS*/ +static struct fh_clk pll_sys_pclk = { + .name = "pll_sys_pclk", + .flag = CLOCK_PLL_P|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL2, + .en_reg_offset = REG_PMU_PLL2_CTRL, + .en_reg_mask = 0xf00, +}; + + +static struct fh_clk pll_sys_rclk = { + .name = "pll_sys_rclk", + .flag = CLOCK_PLL_R|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL2, + .en_reg_offset = REG_PMU_PLL2_CTRL, + .en_reg_mask = 0xf000, +}; + +static struct fh_clk pllsysp_div12_clk = { + .name = "pllsysp_div12_clk", + .flag = CLOCK_NORESET|CLOCK_NOGATE, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV5, + .div_reg_mask = 0xf000000, +}; + +static struct fh_clk ddr_clk = { + .name = "ddr_clk", + .flag = CLOCK_NODIV, + .parent = {&pll_ddr_rclk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x4000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x8, +}; +static struct fh_clk arm_clk = { + .name = "arm_clk", + .flag = CLOCK_MULTI_PARENT|CLOCK_NOGATE|CLOCK_NODIV, + .parent = {&osc_clk, &pll_cpu_pclk}, + .prediv = 1, + .sel_reg_offset = REG_PMU_SYS_CTRL, + .sel_reg_mask = 0x1, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x1, +}; +static struct fh_clk arc_clk = { + .name = "arc_clk", + .flag = CLOCK_MULTI_PARENT|CLOCK_NODIV, + .parent = {&osc_clk, &pll_cpu_rclk}, + .prediv = 1, + .sel_reg_offset = REG_PMU_SYS_CTRL, + .sel_reg_mask = 0x1, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x400000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x400000, +}; +static struct fh_clk ahb_clk = { + .name = "ahb_clk", + .flag = CLOCK_MULTI_PARENT|CLOCK_NORESET|CLOCK_NOGATE, + .parent = {&osc_clk, &pll_sys_pclk}, + .prediv = 1, + .sel_reg_offset = REG_PMU_SYS_CTRL, + .sel_reg_mask = 0x1, + .div_reg_offset = REG_PMU_CLK_DIV0, + .div_reg_mask = 0xf0000, +}; + +static struct fh_clk isp_aclk = { + .name = "isp_aclk", + .flag = CLOCK_NORESET, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV0, + .div_reg_mask = 0xf00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x1, + .def_rate = CONFIG_ISP_CLK_RATE, +}; +static struct fh_clk ispb_aclk = { + .name = "ispb_aclk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&isp_aclk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x4, +}; + +static struct fh_clk vpu_clk = { + .name = "vpu_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&isp_aclk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x80000000, +}; + +static struct fh_clk pix_clk = { + .name = "pix_clk", + .flag = CLOCK_NORESET|CLOCK_NOGATE, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV2, + .div_reg_mask = 0xf000000, +}; + +static struct fh_clk jpeg_clk = { + .name = "jpeg_clk", + .flag = CLOCK_NORESET, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV7, + .div_reg_mask = 0xf00000, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x40000000, + .def_rate = CONFIG_JPEG_CLK_RATE, +}; + +static struct fh_clk bgm_clk = { + .name = "bgm_clk", + .flag = CLOCK_NORESET, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV7, + .div_reg_mask = 0xf00000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x40000, +}; + +static struct fh_clk jpeg_adapt_clk = { + .name = "jpeg_adapt_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&jpeg_clk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x2, +}; +static struct fh_clk spi0_clk = { + .name = "spi0_clk", + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xff, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x80, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x100, +}; +static struct fh_clk sdc0_clk = { + .name = "sdc0_clk", + .parent = {&pll_sys_pclk}, + .prediv = 8, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xf00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x200, + .rst_reg_offset = REG_PMU_SWRST_AHB_CTRL, + .rst_reg_mask = 0x4, +}; +static struct fh_clk spi2_clk = { + .name = "spi2_clk", + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xf000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x2, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x100000, +}; +static struct fh_clk spi1_clk = { + .name = "spi1_clk", + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xff0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x100, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x200, +}; +static struct fh_clk sdc1_clk = { + .name = "sdc1_clk", + .parent = {&pll_sys_pclk}, + .prediv = 8, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xf000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x400, + .rst_reg_offset = REG_PMU_SWRST_AHB_CTRL, + .rst_reg_mask = 0x2, +}; + +static struct fh_clk veu_clk = { + .name = "veu_clk", + .flag = CLOCK_MULTI_PARENT, + .parent = {&pll_sys_pclk, &pll_sys_rclk}, + .prediv = 1, + .sel_reg_offset = REG_PMU_SYS_CTRL, + .sel_reg_mask = 0x4, + .div_reg_offset = REG_PMU_CLK_DIV0, + .div_reg_mask = 0x7000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x10, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x2000000, + .def_rate = CONFIG_VEU_CLK_RATE, + +}; + +static struct fh_clk veu_adapt_clk = { + .name = "veu_adapt_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&veu_clk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x20000000, + +}; + +static struct fh_clk cis_clk_out = { + .name = "cis_clk_out", + .flag = CLOCK_NORESET, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV1, + .div_reg_mask = 0xff0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x800000, +}; + +static struct fh_clk eth_clk = { + .name = "eth_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV6, + .div_reg_mask = 0xf000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x12000000, + .rst_reg_offset = REG_PMU_SWRST_AHB_CTRL, + .rst_reg_mask = 0x20000, +}; +static struct fh_clk i2c0_clk = { + .name = "i2c0_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV4, + .div_reg_mask = 0x3f0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x1000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x400, +}; + +static struct fh_clk i2c1_clk = { + .name = "i2c1_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV4, + .div_reg_mask = 0x3f000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x8000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x800, +}; + +static struct fh_clk i2c2_clk = { + .name = "i2c2_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV7, + .div_reg_mask = 0x00003f00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x00000008, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x20000000, +}; + +static struct fh_clk pwm_clk = { + .name = "pwm_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV5, + .div_reg_mask = 0xff, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x10000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x80, + .def_rate = 50000000, +}; + +static struct fh_clk uart0_clk = { + .name = "uart0_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV4, + .div_reg_mask = 0x1f, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x2000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x4000, + .def_rate = 16666666, +}; + +static struct fh_clk uart1_clk = { + .name = "uart1_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV4, + .div_reg_mask = 0x1f00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x4000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x8000, + .def_rate = 16666666, +}; +static struct fh_clk uart2_clk = { + .name = "uart2_clk", + .parent = {&pllsysp_div12_clk}, + .flag = 0, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV7, + .div_reg_mask = 0x7f, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x8000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x8000000, + .def_rate = 16666666, +}; + +static struct fh_clk efuse_clk = { + .name = "efuse_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV1, + .div_reg_mask = 0x3f000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x200000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x800000, +}; + +static struct fh_clk pts_clk = { + .name = "pts_clk", + .parent = {&pllsysp_div12_clk}, + .flag = CLOCK_NORESET, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV2, + .div_reg_mask = 0x1ff, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x80000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL2, + .rst_reg_mask = 0x1, + .def_rate = 1000000, +}; + +static struct fh_clk tmr0_clk = { + .name = "tmr0_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV5, + .div_reg_mask = 0xff0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x20000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x40000, +}; + +static struct fh_clk sadc_clk = { + .name = "sadc_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV6, + .div_reg_mask = 0x7f0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x4000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x10000, +}; + +static struct fh_clk ac_clk = { + .name = "ac_clk", + .parent = {&osc_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV6, + .div_reg_mask = 0x3f, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x800, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x1000, +}; + +static struct fh_clk i2s_clk = { + .name = "i2s_clk", + .parent = {&ac_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV6, + .div_reg_mask = 0x3f00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x1000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x2000, +}; + +static struct fh_clk wdt_clk = { + .name = "wdt_clk", + .flag = 0, + .parent = {&ahb_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV5, + .div_reg_mask = 0xff00, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x8000000, + .rst_reg_offset = REG_PMU_SWRST_APB_CTRL, + .rst_reg_mask = 0x100000, + .def_rate = 1000000, +}; + +static struct fh_clk gpio0_db_clk = { + .name = "gpio0_db_clk", + .flag = 0, + .parent = {&pllsysp_div12_clk}, + .prediv = 100, + .div_reg_offset = REG_PMU_CLK_DIV8, + .div_reg_mask = 0x7fff, + .en_reg_offset = REG_PMU_CLK_DIV8, + .en_reg_mask = 0x8000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x10, +}; + +static struct fh_clk gpio1_db_clk = { + .name = "gpio1_db_clk", + .flag = 0, + .parent = {&pllsysp_div12_clk}, + .prediv = 100, + .div_reg_offset = REG_PMU_CLK_DIV8, + .div_reg_mask = 0x7fff0000, + .en_reg_offset = REG_PMU_CLK_DIV8, + .en_reg_mask = 0x80000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x20, +}; + + +static struct fh_clk mipi_dphy_clk = { + .name = "mipi_dphy_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&osc_clk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x100000, +}; +static struct fh_clk mipi_wrap_gate = { + .name = "mipi_wrap_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x20000000, +}; +static struct fh_clk rtc_hclk_gate = { + .name = "rtc_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x10000000, +}; +static struct fh_clk emac_hclk_gate = { + .name = "emac_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x2000000, +}; +static struct fh_clk usb_clk = { + .name = "usb_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x1000000, +}; +static struct fh_clk aes_hclk_gate = { + .name = "aes_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x80, +}; +static struct fh_clk ephy_clk_gate = { + .name = "ephy_clk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x1, +}; +static struct fh_clk sdc0_clk8x_gate = { + .name = "sdc0_clk8x_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x4, +}; +static struct fh_clk sdc1_clk8x_gate = { + .name = "sdc1_clk8x_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x8, +}; +static struct fh_clk mipic_pclk_gate = { + .name = "mipic_pclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x10, +}; + +static struct fh_clk gpio0_pclk_gate = { + .name = "gpio0_pclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV8, + .en_reg_mask = 0x4000, +}; +static struct fh_clk gpio1_pclk_gate = { + .name = "gpio1_pclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV8, + .en_reg_mask = 0x40000000, +}; +static struct fh_clk isp_hclk_gate = { + .name = "isp_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x1000000, +}; +static struct fh_clk veu_hclk_gate = { + .name = "veu_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x2000000, +}; +static struct fh_clk bgm_hclk_gate = { + .name = "bgm_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x4000000, +}; +static struct fh_clk adapt_hclk_gate = { + .name = "adapt_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x8000000, +}; +static struct fh_clk jpg_hclk_gate = { + .name = "jpg_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x10000000, +}; +static struct fh_clk jpg_adapt_gate = { + .name = "jpg_adapt_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x20000000, +}; +static struct fh_clk vpu_hclk_gate = { + .name = "vpu_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x40000000, +}; + +static struct fh_clk sdc0_clk_sample = { + .name = "sdc0_clk_sample", + .parent = {&sdc0_clk}, + .flag = CLOCK_NOGATE | CLOCK_PHASE, + .prediv = 1, + .sel_reg_offset = REG_PMU_CLK_GATE1, + .sel_reg_mask = 0xf0000, +}; + +static struct fh_clk sdc0_clk_drv = { + .name = "sdc0_clk_drv", + .parent = {&sdc0_clk}, + .flag = CLOCK_NOGATE | CLOCK_PHASE, + .prediv = 1, + .sel_reg_offset = REG_PMU_CLK_GATE1, + .sel_reg_mask = 0xf00000, +}; + +static struct fh_clk sdc1_clk_sample = { + .name = "sdc1_clk_sample", + .parent = {&sdc0_clk}, + .flag = CLOCK_NOGATE | CLOCK_PHASE, + .prediv = 1, + .sel_reg_offset = REG_PMU_CLK_GATE1, + .sel_reg_mask = 0xf00, +}; + +static struct fh_clk sdc1_clk_drv = { + .name = "sdc1_clk_drv", + .parent = {&sdc0_clk}, + .flag = CLOCK_NOGATE | CLOCK_PHASE, + .prediv = 1, + .sel_reg_offset = REG_PMU_CLK_GATE1, + .sel_reg_mask = 0xf000, +}; + +struct fh_clk *fh_clks[] = { + &osc_clk, + &pll_ddr_rclk, + &pll_cpu_pclk, + &pll_cpu_rclk, + &pll_sys_pclk, + &pll_sys_rclk, + &arm_clk, + &arc_clk, + &ahb_clk, + &ddr_clk, + &isp_aclk, + &ispb_aclk, + &jpeg_clk, + &jpeg_adapt_clk, + &vpu_clk, + &veu_clk, + &veu_adapt_clk, + &bgm_clk, + &mipi_dphy_clk, + &pllsysp_div12_clk, + &cis_clk_out, + &pix_clk, + &pts_clk, + &spi0_clk, + &spi1_clk, + &spi2_clk, + &sdc0_clk, + &sdc1_clk, + &uart0_clk, + &uart1_clk, + &uart2_clk, + &i2c0_clk, + &i2c1_clk, + &i2c2_clk, + &pwm_clk, + &wdt_clk, + &tmr0_clk, + &ac_clk, + &i2s_clk, + &sadc_clk, + ð_clk, + &efuse_clk, + &gpio0_db_clk, + &gpio1_db_clk, + &mipi_wrap_gate, + &rtc_hclk_gate, + &emac_hclk_gate, + &usb_clk, + &aes_hclk_gate, + &ephy_clk_gate, + &sdc0_clk8x_gate, + &sdc1_clk8x_gate, + &gpio0_pclk_gate, + &gpio1_pclk_gate, + &mipic_pclk_gate, + &sdc0_clk_sample, + &sdc0_clk_drv, + &sdc1_clk_sample, + &sdc1_clk_drv, + &isp_hclk_gate, + &veu_hclk_gate, + &bgm_hclk_gate, + &adapt_hclk_gate, + &jpg_hclk_gate, + &jpg_adapt_gate, + &vpu_hclk_gate, + NULL, +}; +EXPORT_SYMBOL(fh_clks); diff --git a/arch/arm/mach-fh/fh8852v200/chip.h b/arch/arm/mach-fh/fh8852v200/chip.h new file mode 100644 index 00000000..18ff2d65 --- /dev/null +++ b/arch/arm/mach-fh/fh8852v200/chip.h @@ -0,0 +1,421 @@ +#ifndef __ASM_ARCH_HL_H +#define __ASM_ARCH_HL_H + +#include + +#define SRAM_GRANULARITY 32 +#define SRAM_SIZE (SZ_128K+SZ_8K) + + +#define RAM_BASE (0x10000000) +#define DDR_BASE (0xA0000000) + + +#define PMU_REG_BASE (0xF0000000) +#define TIMER_REG_BASE (0xF0C00000) +#define GPIO0_REG_BASE (0xF0300000) +#define GPIO1_REG_BASE (0xF4000000) +#define UART0_REG_BASE (0xF0700000) +#define UART1_REG_BASE (0xF0800000) +#define SPI0_REG_BASE (0xF0500000) +#define SPI1_REG_BASE (0xF0600000) +#define SPI2_REG_BASE (0xF0640000) +#define INTC_REG_BASE (0xE0200000) +#define GMAC_REG_BASE (0xE0600000) +#define USBC_REG_BASE (0xE0700000) +#define DMAC_REG_BASE (0xE0300000) +#define I2C1_REG_BASE (0xF0B00000) +#define I2C0_REG_BASE (0xF0200000) +#define I2C2_REG_BASE (0xF0100000) +#define SDC0_REG_BASE (0xE2000000) +#define SDC1_REG_BASE (0xE2200000) +#define WDT_REG_BASE (0xF0D00000) +#define PWM_REG_BASE (0xF0400000) +#define I2S_REG_BASE (0xF0900000) +#define ACW_REG_BASE (0xF0A00000) +#define UART2_REG_BASE (0xF1300000) +#define SADC_REG_BASE (0xF1200000) +#define EFUSE_REG_BASE (0xF1600000) +#define AES_REG_BASE (0xE8200000) +#define RTC_REG_BASE (0xF1500000) +#define DDRC_REG_BASE (0xED000000) +#define CONSOLE_REG_BASE UART0_REG_BASE +#define FH_UART_NUMBER 3 + +#define FH_PMU_REG_SIZE 0x2110 +#define REG_PMU_CHIP_ID (0x0000) +#define REG_PMU_IP_VER (0x0004) +#define REG_PMU_FW_VER (0x0008) +#define REG_PMU_CLK_SEL (0x000c) +/*for HL REG_PMU_SYS_CTRL and CLK_SEL use one register */ +#define REG_PMU_SYS_CTRL (0x000c) +#define REG_PMU_PLL0 (0x0010) +#define REG_PMU_PLL1 (0x0014) +#define REG_PMU_PLL0_CTRL (0x0018) +#define REG_PMU_CLK_GATE (0x001c) +#define REG_PMU_CLK_GATE1 (0x0020) +#define REG_PMU_CLK_DIV0 (0x0024) +#define REG_PMU_CLK_DIV1 (0x0028) +#define REG_PMU_CLK_DIV2 (0x002c) +#define REG_PMU_CLK_DIV3 (0x0030) +#define REG_PMU_CLK_DIV4 (0x0034) +#define REG_PMU_CLK_DIV5 (0x0038) +#define REG_PMU_CLK_DIV6 (0x003c) +#define REG_PMU_SWRST_MAIN_CTRL (0x0040) +#define REG_PMU_SWRST_MAIN_CTRL2 (0x0044) +#define REG_PMU_SWRST_AHB_CTRL (0x0048) +#define REG_PMU_SWRST_APB_CTRL (0x004c) +#define REG_PMU_SPC_IO_STATUS (0x0054) +#define REG_PMU_SPC_FUN (0x0058) +#define REG_PMU_CLK_DIV7 (0x005c) +#define REG_PMU_CLK_DIV8 (0x0060) +#define REG_PMU_PLL2 (0x0064) +#define REG_PMU_PLL2_CTRL (0x0068) +#define REG_PMU_PLL1_CTRL (0x006c) +#define REG_PAD_PWR_SEL (0x0074) +#define REG_PMU_SWRSTN_NSR (0x0078) +#define REG_PMU_SWRSTN_NSR1 (0x007c) +#define REG_PMU_ETHPHY_REG0 (0x2108) + + +#define REG_PMU_PAD_BOOT_MODE_CFG (0x0080) +#define REG_PMU_PAD_BOOT_SEL1_CFG (0x0084) +#define REG_PMU_PAD_BOOT_SEL0_CFG (0x0088) +#define REG_PMU_PAD_UART0_TX_CFG (0x008c) +#define REG_PMU_PAD_UART0_RX_CFG (0x0090) +#define REG_PMU_PAD_I2C0_SCL_CFG (0x0094) +#define REG_PMU_PAD_I2C0_SDA_CFG (0x0098) +#define REG_PMU_PAD_SENSOR_CLK_CFG (0x009c) +#define REG_PMU_PAD_SENSOR_RSTN_CFG (0x00a0) +#define REG_PMU_PAD_UART1_TX_CFG (0x00a4) +#define REG_PMU_PAD_UART1_RX_CFG (0x00a8) +#define REG_PMU_PAD_I2C1_SCL_CFG (0x00ac) +#define REG_PMU_PAD_I2C1_SDA_CFG (0x00b0) +#define REG_PMU_PAD_UART2_TX_CFG (0x00b4) +#define REG_PMU_PAD_UART2_RX_CFG (0x00b8) +#define REG_PMU_PAD_USB_PWREN_CFG (0x00bc) +#define REG_PMU_PAD_PWM0_CFG (0x00c0) +#define REG_PMU_PAD_PWM1_CFG (0x00c4) +#define REG_PMU_PAD_PWM2_CFG (0x00c8) +#define REG_PMU_PAD_PWM3_CFG (0x00cc) +#define REG_PMU_PAD_MAC_RMII_CLK_CFG (0x00d0) +#define REG_PMU_PAD_MAC_REF_CLK_CFG (0x00d4) +#define REG_PMU_PAD_MAC_TXD0_CFG (0x00d8) +#define REG_PMU_PAD_MAC_TXD1_CFG (0x00dc) +#define REG_PMU_PAD_MAC_TXEN_CFG (0x00e0) +#define REG_PMU_PAD_MAC_RXD0_CFG (0x00e4) +#define REG_PMU_PAD_MAC_RXD1_CFG (0x00e8) +#define REG_PMU_PAD_MAC_RXDV_CFG (0x00ec) +#define REG_PMU_PAD_MAC_MDC_CFG (0x00f0) +#define REG_PMU_PAD_MAC_MDIO_CFG (0x00f4) +#define REG_PMU_PAD_SD1_CLK_CFG (0x00f8) +#define REG_PMU_PAD_SD1_CD_CFG (0x00fc) +#define REG_PMU_PAD_SD1_CMD_RSP_CFG (0x0100) +#define REG_PMU_PAD_SD1_DATA_0_CFG (0x0104) +#define REG_PMU_PAD_SD1_DATA_1_CFG (0x0108) +#define REG_PMU_PAD_SD1_DATA_2_CFG (0x010c) +#define REG_PMU_PAD_SD1_DATA_3_CFG (0x0110) +#define REG_PMU_PAD_GPIO_0_CFG (0x0114) +#define REG_PMU_PAD_GPIO_1_CFG (0x0118) +#define REG_PMU_PAD_GPIO_2_CFG (0x011c) +#define REG_PMU_PAD_GPIO_3_CFG (0x0120) +#define REG_PMU_PAD_GPIO_4_CFG (0x0124) +#define REG_PMU_PAD_SSI0_CLK_CFG (0x0128) +#define REG_PMU_PAD_SSI0_CSN_0_CFG (0x012c) +#define REG_PMU_PAD_SSI0_TXD_CFG (0x0130) +#define REG_PMU_PAD_SSI0_RXD_CFG (0x0134) +#define REG_PMU_PAD_SSI0_D2_CFG (0x0138) +#define REG_PMU_PAD_SSI0_D3_CFG (0x013c) +#define REG_PMU_PAD_SSI1_CLK_CFG (0x0140) +#define REG_PMU_PAD_SSI1_CSN_0_CFG (0x0144) +#define REG_PMU_PAD_SSI1_TXD_CFG (0x0148) +#define REG_PMU_PAD_SSI1_RXD_CFG (0x014c) +#define REG_PMU_PAD_SD0_CD_CFG (0x0150) +#define REG_PMU_PAD_SD0_CLK_CFG (0x0154) +#define REG_PMU_PAD_SD0_CMD_RSP_CFG (0x0158) +#define REG_PMU_PAD_SD0_DATA_0_CFG (0x015c) +#define REG_PMU_PAD_SD0_DATA_1_CFG (0x0160) +#define REG_PMU_PAD_SD0_DATA_2_CFG (0x0164) +#define REG_PMU_PAD_SD0_DATA_3_CFG (0x0168) +#define REG_PMU_PAD_SADC_XAIN0_CFG (0x016c) +#define REG_PMU_PAD_SADC_XAIN1_CFG (0x0170) +#define REG_PMU_PAD_SADC_XAIN2_CFG (0x0174) +#define REG_PMU_PAD_SADC_XAIN3_CFG (0x0178) +#define REG_PMU_PAD_GPIO_28_CFG (0x017c) +#define REG_PMU_PAD_GPIO_29_CFG (0x0180) + +#define REG_PMU_ARM_INT_0 (0x01e0) +#define REG_PMU_ARM_INT_1 (0x01e4) +#define REG_PMU_ARM_INT_2 (0x01e8) +#define REG_PMU_A625_INT_0 (0x01ec) +#define REG_PMU_A625_INT_1 (0x01f0) +#define REG_PMU_A625_INT_2 (0x01f4) +#define REG_PMU_DMA (0x01f8) +#define REG_PMU_WDT_CTRL (0x01fc) +#define REG_PMU_DBG_STAT0 (0x0200) +#define REG_PMU_DBG_STAT1 (0x0204) +#define REG_PMU_DBG_STAT2 (0x0208) +#define REG_PMU_DBG_STAT3 (0x020c) +#define REG_PMU_USB_SYS (0x0210) +#define REG_PMU_USB_CFG (0x0214) +#define REG_PMU_USB_TUNE (0x0218) +#define REG_PMU_USB_SYS1 (0x0228) +#define REG_PMU_PTSLO (0x022c) +#define REG_PMU_PTSHI (0x0230) +#define REG_PMU_USER0 (0x0234) +#define REG_PMU_BOOT_MODE (0x0330) +#define REG_PMU_DDR_SIZE (0x0334) +#define REG_PMU_RESERVED2 (0x0338) +#define REG_PMU_CHIP_INFO (0x033c) +#define REG_PMU_EPHY_PARAM (0x0340) +#define REG_PMU_RTC_PARAM (0x0344) +#define REG_PMU_SD1_FUNC_SEL (0x03a0) +#define REG_PMU_PRDCID_CTRL0 (0x0500) +#define REG_PMU_A625BOOT0 (0x2000) +#define REG_PMU_A625BOOT1 (0x2004) +#define REG_PMU_A625BOOT2 (0x2008) +#define REG_PMU_A625BOOT3 (0x200c) +#define REG_PMU_A625_START_CTRL (0x2010) +#define REG_PMU_ARC_INTC_MASK (0x2014) + +#define FH_GMAC_AHB_RESET (1<<17) +#define FH_GMAC_SPEED_100M (1<<24) +#define PMU_RMII_SPEED_MODE (REG_PMU_CLK_SEL) +#define PMU_RXDV_GPIO_SWITCH (REG_PMU_PAD_MAC_RXDV_CFG) +#define PMU_RXDV_GPIO_MASK (0x0f000000) +#define PMU_RXDV_GPIO_VAL (0x01000000) + +#define PMU_DWI2S_CLK_SEL_REG (REG_PMU_CLK_SEL) +#define PMU_DWI2S_CLK_SEL_SHIFT (1) +#define PMU_DWI2S_CLK_DIV_REG (REG_PMU_CLK_DIV6) +#define PMU_DWI2S_CLK_DIV_SHIFT (0) + +/*ATTENTION: written by ARC */ +#define PMU_ARM_INT_MASK (0x01ec) +#define PMU_ARM_INT_RAWSTAT (0x01f0) +#define PMU_ARM_INT_STAT (0x01f4) + +#define PMU_A625_INT_MASK (0x01e0) +#define PMU_A625_INT_RAWSTAT (0x01e4) +#define PMU_A625_INT_STAT (0x01e8) + +#define PMU_IRQ 0 +#define DDRC_IRQ 1 +#define WDT_IRQ 2 +#define TMR0_IRQ 3 +#define VEU_IRQ 4 +#define PERF_IRQ 5 +#define VPU_IRQ 9 +#define I2C0_IRQ 11 +#define I2C1_IRQ 12 +#define JPEG_IRQ 13 +#define BGM_IRQ 14 +#define VEU_LOOP_IRQ 15 +#define AES_IRQ 16 +#define MIPIC_IRQ 17 +#define MIPI_WRAP_IRQ 18 +#define ACW_IRQ 19 +#define SADC_IRQ 20 +#define SPI1_IRQ 21 +#define JPEG_LOOP_IRQ 22 +#define DMAC0_IRQ 23 +#define DMAC1_IRQ 24 +#define I2S0_IRQ 25 +#define GPIO0_IRQ 26 +#define SPI0_IRQ 28 +#define ARC_SW_IRQ 29 +#define UART0_IRQ 30 +#define UART1_IRQ 31 +#define ARM_SW_IRQ 32 +#define RTC_IRQ 33 +#define PWM_IRQ 36 +#define SPI2_IRQ 38 +#define USBC_IRQ 39 +#define GPIO1_IRQ 40 +#define UART2_IRQ 41 +#define SDC0_IRQ 42 +#define SDC1_IRQ 43 +#define GMAC_IRQ 44 +#define EPHY_IRQ 45 +#define I2C2_IRQ 46 +#define RTC_ALM_IRQ 47 +#define RTC_CORE_IRQ 48 +/* because chips with some same function in different */ +/* pmu register, use wrap marco to make code to be same */ +#define PMU_RMII_SPEED_MODE (REG_PMU_CLK_SEL) + +#define MEM_START_PHY_ADDR DDR_BASE +#define MEM_SIZE 0x4000000 + + +#define NR_INTERNAL_IRQS (64) +#define NR_EXTERNAL_IRQS (64) +/*#define NR_IRQS (NR_INTERNAL_IRQS + NR_EXTERNAL_IRQS)*/ + +/* SWRST_MAIN_CTRL */ +#define CPU_RSTN_BIT (0) +#define UTMI_RSTN_BIT (1) +#define DDRPHY_RSTN_BIT (2) +#define DDRC_RSTN_BIT (3) +#define GPIO0_DB_RSTN_BIT (4) +#define GPIO1_DB_RSTN_BIT (5) +#define PIXEL_RSTN_BIT (6) +#define PWM_RSTN_BIT (7) +#define SPI0_RSTN_BIT (8) +#define SPI1_RSTN_BIT (9) +#define I2C0_RSTN_BIT (10) +#define I2C1_RSTN_BIT (11) +#define ACODEC_RSTN_BIT (12) +#define I2S_RSTN_BIT (13) +#define UART0_RSTN_BIT (14) +#define UART1_RSTN_BIT (15) +#define SADC_RSTN_BIT (16) +#define ADAPT_RSTN_BIT (17) +#define TMR_RSTN_BIT (18) +#define UART2_RSTN_BIT (19) +#define SPI2_RSTN_BIT (20) +#define JPG_ADAPT_RSTN_BIT (21) +#define ARC_RSTN_BIT (22) +#define EFUSE_RSTN_BIT (23) +#define JPG_RSTN_BIT (24) +#define VEU_RSTN_BIT (25) +#define VPU_RSTN_BIT (26) +#define ISP_RSTN_BIT (27) +#define BGM_RSTN_BIT (28) +#define I2C2_RSTN_BIT (29) +#define EPHY_RSTN_BIT (30) +#define SYS_RSTN_BIT (31) + +/* SWRST_AHB_CTRL */ +#define EMC_HRSTN_BIT (0) +#define SDC1_HRSTN_BIT (1) +#define SDC0_HRSTN_BIT (2) +#define AES_HRSTN_BIT (3) +#define DMAC0_HRSTN_BIT (4) +#define INTC_HRSTN_BIT (5) +#define JPEG_ADAPT_HRSTN_BIT (7) +#define JPEG_HRSTN_BIT (8) +#define VCU_HRSTN_BIT (9) +#define VPU_HRSTN_BIT (10) +#define ISP_HRSTN_BIT (11) +#define USB_HRSTN_BIT (12) +#define HRSTN_BIT (13) +#define EMAC_HRSTN_BIT (17) +#define DDRC_HRSTN_BIT (19) +#define DMAC1_HRSTN_BIT (20) +#define BGM_HRSTN_BIT (22) +#define ADAPT_HRSTN_BIT (23) + +/* SWRST_APB_CTRL */ +#define ACODEC_PRSTN_BIT (0) +#define I2S_PRSTN_BIT (1) +#define UART1_PRSTN_BIT (2) +#define UART0_PRSTN_BIT (3) +#define SPI0_PRSTN_BIT (4) +#define SPI1_PRSTN_BIT (5) +#define GPIO0_PRSTN_BIT (6) +#define UART2_PRSTN_BIT (7) +#define I2C2_PRSTN_BIT (8) +#define I2C0_PRSTN_BIT (9) +#define I2C1_PRSTN_BIT (10) +#define TMR_PRSTN_BIT (11) +#define PWM_PRSTN_BIT (12) +#define MIPIW_PRSTN_BIT (13) +#define MIPIC_PRSTN_BIT (14) +#define RTC_PRSTN_BIT (15) +#define SADC_PRSTN_BIT (16) +#define EFUSE_PRSTN_BIT (17) +#define SPI2_PRSTN_BIT (18) +#define WDT_PRSTN_BIT (19) +#define GPIO1_PRSTN_BIT (20) + +/* timer clk fpga 1M,soc 50M*/ +#ifdef CONFIG_FPGA +#define TIMER_CLK (1000000) +#else +#define TIMER_CLK (50000000) +#endif + +#define UART1_TX_HW_HANDSHAKE (9) +#define UART1_RX_HW_HANDSHAKE (8) +#define UART2_TX_HW_HANDSHAKE (13) +#define UART2_RX_HW_HANDSHAKE (12) +#define UART1_DMA_TX_CHAN (4) +#define UART1_DMA_RX_CHAN (5) +#define UART2_DMA_TX_CHAN (4) +#define UART2_DMA_RX_CHAN (5) + +/*sdio*/ +#define SIMPLE_0 (0) +#define SIMPLE_22 (1) +#define SIMPLE_45 (2) +#define SIMPLE_67 (3) +#define SIMPLE_90 (4) +#define SIMPLE_112 (5) +#define SIMPLE_135 (6) +#define SIMPLE_157 (7) +#define SIMPLE_180 (8) +#define SIMPLE_202 (9) +#define SIMPLE_225 (10) +#define SIMPLE_247 (11) +#define SIMPLE_270 (12) +#define SIMPLE_292 (13) +#define SIMPLE_315 (14) +#define SIMPLE_337 (15) + + + +#define SDIO0_RST_BIT (~UL(1<<2)) +#define SDIO0_CLK_RATE (50000000) +#define SDIO0_CLK_DRV_SHIFT (20) +#define SDIO0_CLK_DRV_DEGREE (SIMPLE_180) +#define SDIO0_CLK_SAM_SHIFT (16) +#define SDIO0_CLK_SAM_DEGREE (SIMPLE_0) + + +#define SDIO1_RST_BIT (~UL(1<<1)) +#define SDIO1_CLK_RATE (50000000) +#define SDIO1_CLK_DRV_SHIFT (12) +#define SDIO1_CLK_DRV_DEGREE (SIMPLE_180) +#define SDIO1_CLK_SAM_SHIFT (8) +#define SDIO1_CLK_SAM_DEGREE (SIMPLE_0) + +#define SDC0_HRSTN (0x1<<2) +#define SDC1_HRSTN (0x1<<1) +#define SDC2_HRSTN (0) + + +/*usb*/ +#define IRQ_UHOST USBC_IRQ +#define FH_PA_OTG USBC_REG_BASE +#define IRQ_OTG IRQ_UHOST +#define FH_SZ_USBHOST SZ_1M +#define FH_SZ_OTG SZ_1M + +#define USB_UTMI_RST_BIT (0x1<<1) +#define USB_PHY_RST_BIT (0x11) +#define USB_SLEEP_MODE_BIT (0x1<<24) +#define USB_IDDQ_PWR_BIT (0x1<<10) + + +/* Specific Uart Number */ +#define FH_UART_NUMBER 3 +#define CLK_SCAN_BIT_POS (28) +#define INSIDE_PHY_ENABLE_BIT_POS (24) +#define MAC_REF_CLK_DIV_MASK (0x0f) +#define MAC_REF_CLK_DIV_BIT_POS (24) +#define MAC_PAD_RMII_CLK_MASK (0x0f) +#define MAC_PAD_RMII_CLK_BIT_POS (24) +#define MAC_PAD_MAC_REF_CLK_BIT_POS (28) +#define ETH_REF_CLK_OUT_GATE_BIT_POS (25) +#define ETH_RMII_CLK_OUT_GATE_BIT_POS (28) +#define IN_OR_OUT_PHY_SEL_BIT_POS (26) +#define INSIDE_CLK_GATE_BIT_POS (0) +#define INSIDE_PHY_SHUTDOWN_BIT_POS (31) +#define INSIDE_PHY_RST_BIT_POS (30) +#define INSIDE_PHY_TRAINING_BIT_POS (27) +#define INSIDE_PHY_TRAINING_MASK (0x0f) + +#define TRAINING_EFUSE_ACTIVE_BIT_POS 4 + +#endif /* __ASM_ARCH_HL_H */ diff --git a/arch/arm/mach-fh/fh8852v200/iopad.h b/arch/arm/mach-fh/fh8852v200/iopad.h new file mode 100644 index 00000000..ebc24024 --- /dev/null +++ b/arch/arm/mach-fh/fh8852v200/iopad.h @@ -0,0 +1,729 @@ +#include +#include +#include + +/* PINCTRL_FUNC */ +PINCTRL_FUNC(GPIO30, 0, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(GPIO31, 1, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(ETH_LINK_ACT, 1, FUNC1, PUPD_UP, 0); +PINCTRL_FUNC(GPIO32, 2, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(ETH_LINK_STA, 2, FUNC1, PUPD_UP, 0); +PINCTRL_FUNC(ETH_LINK_SPD, 2, FUNC2, PUPD_UP, 0); +PINCTRL_FUNC(UART0_TX, 3, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO33, 3, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART0_RX, 4, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO34, 4, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C0_SCL, 5, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(GPIO35, 5, FUNC1, PUPD_UP, 0); +PINCTRL_FUNC(I2C0_SDA, 6, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(GPIO36, 6, FUNC1, PUPD_UP, 0); +PINCTRL_FUNC(SENSOR_CLK, 7, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO12, 7, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO13, 8, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(UART1_TX, 9, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO39, 9, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CLK, 9, FUNC3, PUPD_NONE, 3); +PINCTRL_FUNC(TEST_O_INT_RMII_CLK, 9, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(UART1_RX, 10, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO40, 10, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 10, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_INT_RMII_TXD_0, 10, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(I2C1_SCL, 11, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO37, 11, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM2, 11, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CMD_RSP, 11, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CLK, 11, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_INT_RMII_TXD_1, 11, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(I2C1_SDA, 12, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO38, 12, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM3, 12, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_0, 12, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CSN_0, 12, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_INT_RMII_TXEN, 12, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_TX, 13, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO41, 13, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM4, 13, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_1, 13, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_TXD, 13, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_O_INT_RMII_RXD_0, 13, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_RX, 14, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO42, 14, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM5, 14, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_2, 14, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_RXD, 14, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_O_INT_RMII_RXD_1, 14, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(USB_PWREN, 15, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO47, 15, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_3, 15, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_O_INT_RMII_CRSDV, 15, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM0, 16, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO43, 16, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C2_SCL, 16, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_TX, 16, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_RMII_TXD_0, 16, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM1, 17, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO44, 17, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C2_SDA, 17, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_RX, 17, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_RMII_TXD_1, 17, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM2, 18, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO45, 18, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM3, 19, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO46, 19, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_RMII_CLK, 20, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO48, 20, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CLK, 20, FUNC2, PUPD_NONE, 3); +PINCTRL_FUNC(PWM2, 20, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_REF_CLK, 21, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(MAC_TXD_0, 22, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO49, 22, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 22, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM3, 22, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_TXD_1, 23, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO50, 23, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CMD_RSP, 23, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM4, 23, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_TXEN, 24, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO51, 24, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_0, 24, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM5, 24, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_RXD_0, 25, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO52, 25, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_1, 25, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM6, 25, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_RXD_1, 26, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO53, 26, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_2, 26, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM7, 26, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_RXDV, 27, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO54, 27, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_3, 27, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM8, 27, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_MDC, 28, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO55, 28, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM9, 28, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_MDIO, 29, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO56, 29, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CLK, 30, FUNC0, PUPD_NONE, 3); +PINCTRL_FUNC(GPIO57, 30, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C1_SCL, 30, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 31, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO58, 31, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C1_SDA, 31, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CMD_RSP, 32, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO59, 32, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART1_TX, 32, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_0, 33, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO60, 33, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART1_RX, 33, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_1, 34, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO61, 34, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_TX, 34, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_2, 35, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO62, 35, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_RX, 35, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_3, 36, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO63, 36, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TRSTN, 37, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO0, 37, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_I2S_DO, 37, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(DW_I2S_DO, 37, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SSI1_CLK, 37, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI2_CLK, 37, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_ADDAT, 37, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM6, 37, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_SMI_MDC, 37, FUNC8, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TDO, 38, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO1, 38, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_I2S_DI, 38, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(DW_I2S_DI, 38, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SSI1_CSN_0, 38, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI2_CSN_0, 38, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_DADAT, 38, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM7, 38, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_SMI_MDIO_I, 38, FUNC8, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TDI, 39, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO2, 39, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_I2S_CLK, 39, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(DW_I2S_CLK, 39, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SSI1_TXD, 39, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI2_TXD, 39, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_ADBCLK, 39, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM8, 39, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_SMI_MDIO_O, 39, FUNC8, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TCK, 40, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO3, 40, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_I2S_WS, 40, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(DW_I2S_WS, 40, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SSI1_RXD, 40, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI2_RXD, 40, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_ADLRC, 40, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM9, 40, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_I_INT_SMI_MDIO_I, 40, FUNC8, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TMS, 41, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO4, 41, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_MCLK, 41, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(USB_PWREN, 41, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 41, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_I_INT_SMI_MDC, 41, FUNC5, PUPD_NONE, 0); +PINCTRL_FUNC(SSI0_CLK, 42, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO5, 42, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_CLK, 42, FUNC4, PUPD_NONE, 3); +PINCTRL_FUNC(SSI0_CSN_0, 43, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO6, 43, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_CMD_RSP, 43, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI0_TXD, 44, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO7, 44, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_DATA_0, 44, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI0_RXD, 45, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO8, 45, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_DATA_1, 45, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI0_D2, 46, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO9, 46, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(UART1_TX, 46, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(I2C1_SCL, 46, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_DATA_2, 46, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI0_D3, 47, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO10, 47, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(UART1_RX, 47, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(I2C1_SDA, 47, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_DATA_3, 47, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CLK, 48, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO11, 48, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SSI2_CLK, 48, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CSN_0, 49, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO14, 49, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SSI2_CSN_0, 49, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_TXD, 50, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO15, 50, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SSI2_TXD, 50, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_RXD, 51, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO16, 51, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SSI2_RXD, 51, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_CD, 52, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO17, 52, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(ARC_JTAG_TRSTN, 52, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(PAE_JTAG_TRSTN, 52, FUNC4, PUPD_NONE, 0); +PINCTRL_FUNC(SD0_CLK, 53, FUNC0, PUPD_NONE, 3); +PINCTRL_FUNC(GPIO18, 53, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CLK, 53, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(ARC_JTAG_TDO, 53, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(PAE_JTAG_TDO, 53, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_CMD_RSP, 54, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO19, 54, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_TXD, 54, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(ARC_JTAG_TDI, 54, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(PAE_JTAG_TDI, 54, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_DATA_0, 55, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO20, 55, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_RXD, 55, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(ARC_JTAG_TCK, 55, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(PAE_JTAG_TCK, 55, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_DATA_1, 56, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO21, 56, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CSN_0, 56, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(ARC_JTAG_TMS, 56, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(PAE_JTAG_TMS, 56, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_DATA_2, 57, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO22, 57, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(UART2_TX, 57, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(I2C2_SCL, 57, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_DABCLK, 57, FUNC6, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_DATA_3, 58, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO23, 58, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CSN_0, 58, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(UART2_RX, 58, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(I2C2_SDA, 58, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_DALRC, 58, FUNC6, PUPD_NONE, 2); +PINCTRL_FUNC(SADC_XAIN0, 59, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO26, 59, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SADC_XAIN1, 60, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO27, 60, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SADC_XAIN2, 61, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO24, 61, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SADC_XAIN3, 62, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO25, 62, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO28, 63, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(ETH_LINK_ACT, 63, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(PWM10, 63, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(USB_DBG_CLK, 63, FUNC4, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 63, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_O_INT_RMII_TXEN, 63, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_MDC, 63, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO29, 64, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(ETH_LINK_STA, 64, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(PWM11, 64, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(RTC_CLK, 64, FUNC4, PUPD_NONE, 0); +PINCTRL_FUNC(ETH_LINK_SPD, 64, FUNC5, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_SMI_MDIO_OE, 64, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_MDIO, 64, FUNC7, PUPD_NONE, 0); + + +/* PINCTRL_MUX */ + +PINCTRL_MUX(AC_I2S_CLK, 0, &PAD39_AC_I2S_CLK); +PINCTRL_MUX(AC_I2S_DI, 0, &PAD38_AC_I2S_DI); +PINCTRL_MUX(AC_I2S_DO, 0, &PAD37_AC_I2S_DO); +PINCTRL_MUX(AC_I2S_WS, 0, &PAD40_AC_I2S_WS); +PINCTRL_MUX(AC_MCLK, 0, &PAD41_AC_MCLK); + +PINCTRL_MUX(ARC_JTAG_TCK, 0, &PAD55_ARC_JTAG_TCK); +PINCTRL_MUX(ARC_JTAG_TDI, 0, &PAD54_ARC_JTAG_TDI); +PINCTRL_MUX(ARC_JTAG_TDO, 0, &PAD53_ARC_JTAG_TDO); +PINCTRL_MUX(ARC_JTAG_TMS, 0, &PAD56_ARC_JTAG_TMS); +PINCTRL_MUX(ARC_JTAG_TRSTN, 0, &PAD52_ARC_JTAG_TRSTN); + +PINCTRL_MUX(ARM_JTAG_TCK, 0, &PAD40_ARM_JTAG_TCK); +PINCTRL_MUX(ARM_JTAG_TDI, 0, &PAD39_ARM_JTAG_TDI); +PINCTRL_MUX(ARM_JTAG_TDO, 0, &PAD38_ARM_JTAG_TDO); +PINCTRL_MUX(ARM_JTAG_TMS, 0, &PAD41_ARM_JTAG_TMS); +PINCTRL_MUX(ARM_JTAG_TRSTN, 0, &PAD37_ARM_JTAG_TRSTN); + +PINCTRL_MUX(DW_I2S_CLK, 0, &PAD39_DW_I2S_CLK); +PINCTRL_MUX(DW_I2S_DI, 0, &PAD38_DW_I2S_DI); +PINCTRL_MUX(DW_I2S_DO, 0, &PAD37_DW_I2S_DO); +PINCTRL_MUX(DW_I2S_WS, 0, &PAD40_DW_I2S_WS); + +PINCTRL_MUX(ETH_LINK_ACT, 1, &PAD1_ETH_LINK_ACT, + &PAD63_ETH_LINK_ACT); +PINCTRL_MUX(ETH_LINK_SPD, 1, &PAD2_ETH_LINK_SPD, + &PAD64_ETH_LINK_SPD); +PINCTRL_MUX(ETH_LINK_STA, 1, &PAD2_ETH_LINK_STA, + &PAD64_ETH_LINK_STA); + +PINCTRL_MUX(I2C0_SCL, 0, &PAD5_I2C0_SCL); +PINCTRL_MUX(I2C0_SDA, 0, &PAD6_I2C0_SDA); + +PINCTRL_MUX(I2C1_SCL, 2, &PAD11_I2C1_SCL, &PAD30_I2C1_SCL, &PAD46_I2C1_SCL); +PINCTRL_MUX(I2C1_SDA, 2, &PAD12_I2C1_SDA, &PAD31_I2C1_SDA, &PAD47_I2C1_SDA); + +PINCTRL_MUX(I2C2_SCL, 1, &PAD16_I2C2_SCL, &PAD57_I2C2_SCL); +PINCTRL_MUX(I2C2_SDA, 1, &PAD17_I2C2_SDA, &PAD58_I2C2_SDA); + +PINCTRL_MUX(MAC_MDC, 0, &PAD28_MAC_MDC, &PAD63_MAC_MDC); +PINCTRL_MUX(MAC_MDIO, 0, &PAD29_MAC_MDIO, &PAD64_MAC_MDIO); +PINCTRL_MUX(MAC_REF_CLK, 0, &PAD21_MAC_REF_CLK); +PINCTRL_MUX(MAC_RMII_CLK, 0, &PAD20_MAC_RMII_CLK); +PINCTRL_MUX(MAC_RXDV, 0, &PAD27_MAC_RXDV); +PINCTRL_MUX(MAC_RXD_0, 0, &PAD25_MAC_RXD_0); +PINCTRL_MUX(MAC_RXD_1, 0, &PAD26_MAC_RXD_1); +PINCTRL_MUX(MAC_TXD_0, 0, &PAD22_MAC_TXD_0); +PINCTRL_MUX(MAC_TXD_1, 0, &PAD23_MAC_TXD_1); +PINCTRL_MUX(MAC_TXEN, 0, &PAD24_MAC_TXEN); + +PINCTRL_MUX(PAE_JTAG_TCK, 0, &PAD55_PAE_JTAG_TCK); +PINCTRL_MUX(PAE_JTAG_TDI, 0, &PAD54_PAE_JTAG_TDI); +PINCTRL_MUX(PAE_JTAG_TDO, 0, &PAD53_PAE_JTAG_TDO); +PINCTRL_MUX(PAE_JTAG_TMS, 0, &PAD56_PAE_JTAG_TMS); +PINCTRL_MUX(PAE_JTAG_TRSTN, 0, &PAD52_PAE_JTAG_TRSTN); + +PINCTRL_MUX(PWM0, 0, &PAD16_PWM0); +PINCTRL_MUX(PWM1, 0, &PAD17_PWM1); +PINCTRL_MUX(PWM10, 0, &PAD63_PWM10); +PINCTRL_MUX(PWM11, 0, &PAD64_PWM11); +PINCTRL_MUX(PWM2, 0, &PAD11_PWM2, &PAD18_PWM2, &PAD20_PWM2); +PINCTRL_MUX(PWM3, 0, &PAD12_PWM3, &PAD19_PWM3, &PAD22_PWM3); +PINCTRL_MUX(PWM4, 0, &PAD13_PWM4, &PAD23_PWM4); +PINCTRL_MUX(PWM5, 0, &PAD14_PWM5, &PAD24_PWM5); +PINCTRL_MUX(PWM6, 1, &PAD25_PWM6, &PAD37_PWM6); +PINCTRL_MUX(PWM7, 1, &PAD26_PWM7, &PAD38_PWM7); +PINCTRL_MUX(PWM8, 1, &PAD27_PWM8, &PAD39_PWM8); +PINCTRL_MUX(PWM9, 1, &PAD28_PWM9, &PAD40_PWM9); + +PINCTRL_MUX(RTC_CLK, 0, &PAD64_RTC_CLK); + +PINCTRL_MUX(SADC_XAIN0, 0, &PAD59_SADC_XAIN0); +PINCTRL_MUX(SADC_XAIN1, 0, &PAD60_SADC_XAIN1); +PINCTRL_MUX(SADC_XAIN2, 0, &PAD61_SADC_XAIN2); +PINCTRL_MUX(SADC_XAIN3, 0, &PAD62_SADC_XAIN3); + +PINCTRL_MUX(SD0_CD, 0, &PAD52_SD0_CD); +PINCTRL_MUX(SD0_CLK, 0, &PAD53_SD0_CLK); +PINCTRL_MUX(SD0_CMD_RSP, 0, &PAD54_SD0_CMD_RSP); +PINCTRL_MUX(SD0_DATA_0, 0, &PAD55_SD0_DATA_0); +PINCTRL_MUX(SD0_DATA_1, 0, &PAD56_SD0_DATA_1); +PINCTRL_MUX(SD0_DATA_2, 0, &PAD57_SD0_DATA_2); +PINCTRL_MUX(SD0_DATA_3, 0, &PAD58_SD0_DATA_3); + +PINCTRL_MUX(SD1_CD, 0, &PAD10_SD1_CD, &PAD22_SD1_CD, &PAD31_SD1_CD, + &PAD41_SD1_CD, &PAD63_SD1_CD); +PINCTRL_MUX(SD1_CLK, 0, &PAD9_SD1_CLK, &PAD20_SD1_CLK, &PAD30_SD1_CLK, + &PAD42_SD1_CLK); +PINCTRL_MUX(SD1_CMD_RSP, 0, &PAD11_SD1_CMD_RSP, &PAD23_SD1_CMD_RSP, + &PAD32_SD1_CMD_RSP, &PAD43_SD1_CMD_RSP); +PINCTRL_MUX(SD1_DATA_0, 0, &PAD12_SD1_DATA_0, &PAD24_SD1_DATA_0, + &PAD33_SD1_DATA_0, &PAD44_SD1_DATA_0); +PINCTRL_MUX(SD1_DATA_1, 0, &PAD13_SD1_DATA_1, &PAD25_SD1_DATA_1, + &PAD34_SD1_DATA_1, &PAD45_SD1_DATA_1); +PINCTRL_MUX(SD1_DATA_2, 0, &PAD14_SD1_DATA_2, &PAD26_SD1_DATA_2, + &PAD35_SD1_DATA_2, &PAD46_SD1_DATA_2); +PINCTRL_MUX(SD1_DATA_3, 0, &PAD15_SD1_DATA_3, &PAD27_SD1_DATA_3, + &PAD36_SD1_DATA_3, &PAD47_SD1_DATA_3); + +PINCTRL_MUX(SENSOR_CLK, 0, &PAD7_SENSOR_CLK); + +PINCTRL_MUX(SSI0_CLK, 0, &PAD42_SSI0_CLK); +PINCTRL_MUX(SSI0_D2, 0, &PAD46_SSI0_D2); +PINCTRL_MUX(SSI0_D3, 0, &PAD47_SSI0_D3); +PINCTRL_MUX(SSI0_RXD, 0, &PAD45_SSI0_RXD); +PINCTRL_MUX(SSI0_TXD, 0, &PAD44_SSI0_TXD); + +PINCTRL_MUX(SSI1_CLK, 2, &PAD11_SSI1_CLK, &PAD37_SSI1_CLK, &PAD48_SSI1_CLK, + &PAD53_SSI1_CLK); +PINCTRL_MUX(SSI1_RXD, 2, &PAD14_SSI1_RXD, &PAD40_SSI1_RXD, &PAD51_SSI1_RXD, + &PAD55_SSI1_RXD); +PINCTRL_MUX(SSI1_TXD, 2, &PAD13_SSI1_TXD, &PAD39_SSI1_TXD, &PAD50_SSI1_TXD, + &PAD54_SSI1_TXD); + +PINCTRL_MUX(SSI2_CLK, 1, &PAD37_SSI2_CLK, &PAD48_SSI2_CLK); +PINCTRL_MUX(SSI2_CSN_0, 1, &PAD38_SSI2_CSN_0, &PAD49_SSI2_CSN_0); +PINCTRL_MUX(SSI2_RXD, 1, &PAD40_SSI2_RXD, &PAD51_SSI2_RXD); +PINCTRL_MUX(SSI2_TXD, 1, &PAD39_SSI2_TXD, &PAD50_SSI2_TXD); + +PINCTRL_MUX(UART0_RX, 0, &PAD4_UART0_RX); +PINCTRL_MUX(UART0_TX, 0, &PAD3_UART0_TX); + +PINCTRL_MUX(UART1_RX, 0, &PAD10_UART1_RX, &PAD33_UART1_RX, &PAD47_UART1_RX); +PINCTRL_MUX(UART1_TX, 0, &PAD9_UART1_TX, &PAD32_UART1_TX, &PAD46_UART1_TX); + +PINCTRL_MUX(UART2_RX, 0, &PAD14_UART2_RX, &PAD17_UART2_RX, &PAD35_UART2_RX, + &PAD58_UART2_RX); +PINCTRL_MUX(UART2_TX, 0, &PAD13_UART2_TX, &PAD16_UART2_TX, &PAD34_UART2_TX, + &PAD57_UART2_TX); + +PINCTRL_MUX(USB_PWREN, 0, &PAD15_USB_PWREN, &PAD41_USB_PWREN); + +PINCTRL_MUX(GPIO0, 0, &PAD37_GPIO0); +PINCTRL_MUX(GPIO1, 0, &PAD38_GPIO1); +PINCTRL_MUX(GPIO2, 0, &PAD39_GPIO2); +PINCTRL_MUX(GPIO3, 0, &PAD40_GPIO3); +PINCTRL_MUX(GPIO4, 0, &PAD41_GPIO4); +PINCTRL_MUX(GPIO5, 0, &PAD42_GPIO5); +PINCTRL_MUX(GPIO6, 0, &PAD43_GPIO6); +PINCTRL_MUX(GPIO7, 0, &PAD44_GPIO7); +PINCTRL_MUX(GPIO8, 0, &PAD45_GPIO8); +PINCTRL_MUX(GPIO9, 0, &PAD46_GPIO9); +PINCTRL_MUX(GPIO10, 0, &PAD47_GPIO10); +PINCTRL_MUX(GPIO11, 0, &PAD48_GPIO11); +PINCTRL_MUX(GPIO12, 0, &PAD7_GPIO12); +PINCTRL_MUX(GPIO13, 0, &PAD8_GPIO13); +PINCTRL_MUX(GPIO14, 0, &PAD49_GPIO14); +PINCTRL_MUX(GPIO15, 0, &PAD50_GPIO15); +PINCTRL_MUX(GPIO16, 0, &PAD51_GPIO16); +PINCTRL_MUX(GPIO17, 0, &PAD52_GPIO17); +PINCTRL_MUX(GPIO18, 0, &PAD53_GPIO18); +PINCTRL_MUX(GPIO19, 0, &PAD54_GPIO19); +PINCTRL_MUX(GPIO20, 0, &PAD55_GPIO20); +PINCTRL_MUX(GPIO21, 0, &PAD56_GPIO21); +PINCTRL_MUX(GPIO22, 0, &PAD57_GPIO22); +PINCTRL_MUX(GPIO23, 0, &PAD58_GPIO23); +PINCTRL_MUX(GPIO24, 0, &PAD61_GPIO24); +PINCTRL_MUX(GPIO25, 0, &PAD62_GPIO25); +PINCTRL_MUX(GPIO26, 0, &PAD59_GPIO26); +PINCTRL_MUX(GPIO27, 0, &PAD60_GPIO27); +PINCTRL_MUX(GPIO28, 0, &PAD63_GPIO28); +PINCTRL_MUX(GPIO29, 0, &PAD64_GPIO29); +PINCTRL_MUX(GPIO30, 0, &PAD0_GPIO30); +PINCTRL_MUX(GPIO31, 0, &PAD1_GPIO31); +PINCTRL_MUX(GPIO32, 0, &PAD2_GPIO32); +PINCTRL_MUX(GPIO33, 0, &PAD3_GPIO33); +PINCTRL_MUX(GPIO34, 0, &PAD4_GPIO34); +PINCTRL_MUX(GPIO35, 0, &PAD5_GPIO35); +PINCTRL_MUX(GPIO36, 0, &PAD6_GPIO36); +PINCTRL_MUX(GPIO37, 0, &PAD11_GPIO37); +PINCTRL_MUX(GPIO38, 0, &PAD12_GPIO38); +PINCTRL_MUX(GPIO39, 0, &PAD9_GPIO39); +PINCTRL_MUX(GPIO40, 0, &PAD10_GPIO40); +PINCTRL_MUX(GPIO41, 0, &PAD13_GPIO41); +PINCTRL_MUX(GPIO42, 0, &PAD14_GPIO42); +PINCTRL_MUX(GPIO43, 0, &PAD16_GPIO43); +PINCTRL_MUX(GPIO44, 0, &PAD17_GPIO44); +PINCTRL_MUX(GPIO45, 0, &PAD18_GPIO45); +PINCTRL_MUX(GPIO46, 0, &PAD19_GPIO46); +PINCTRL_MUX(GPIO47, 0, &PAD15_GPIO47); +PINCTRL_MUX(GPIO48, 0, &PAD20_GPIO48); +PINCTRL_MUX(GPIO49, 0, &PAD22_GPIO49); +PINCTRL_MUX(GPIO50, 0, &PAD23_GPIO50); +PINCTRL_MUX(GPIO51, 0, &PAD24_GPIO51); +PINCTRL_MUX(GPIO52, 0, &PAD25_GPIO52); +PINCTRL_MUX(GPIO53, 0, &PAD26_GPIO53); +PINCTRL_MUX(GPIO54, 0, &PAD27_GPIO54); +PINCTRL_MUX(GPIO55, 0, &PAD28_GPIO55); +PINCTRL_MUX(GPIO56, 0, &PAD29_GPIO56); +PINCTRL_MUX(GPIO57, 0, &PAD30_GPIO57); +PINCTRL_MUX(GPIO58, 0, &PAD31_GPIO58); +PINCTRL_MUX(GPIO59, 0, &PAD32_GPIO59); +PINCTRL_MUX(GPIO60, 0, &PAD33_GPIO60); +PINCTRL_MUX(GPIO61, 0, &PAD34_GPIO61); +PINCTRL_MUX(GPIO62, 0, &PAD35_GPIO62); +PINCTRL_MUX(GPIO63, 0, &PAD36_GPIO63); + +PINCTRL_MUX(SD1_CLK_EMMC, 3, &PAD9_SD1_CLK, &PAD20_SD1_CLK, &PAD30_SD1_CLK, + &PAD42_SD1_CLK); +PINCTRL_MUX(SD1_CMD_RSP_EMMC, 3, &PAD11_SD1_CMD_RSP, &PAD23_SD1_CMD_RSP, + &PAD32_SD1_CMD_RSP, &PAD43_SD1_CMD_RSP); +PINCTRL_MUX(SD1_DATA_0_EMMC, 3, &PAD12_SD1_DATA_0, &PAD24_SD1_DATA_0, + &PAD33_SD1_DATA_0, &PAD44_SD1_DATA_0); +PINCTRL_MUX(SD1_DATA_1_EMMC, 3, &PAD13_SD1_DATA_1, &PAD25_SD1_DATA_1, + &PAD34_SD1_DATA_1, &PAD45_SD1_DATA_1); +PINCTRL_MUX(SD1_DATA_2_EMMC, 3, &PAD14_SD1_DATA_2, &PAD26_SD1_DATA_2, + &PAD35_SD1_DATA_2, &PAD46_SD1_DATA_2); +PINCTRL_MUX(SD1_DATA_3_EMMC, 3, &PAD15_SD1_DATA_3, &PAD27_SD1_DATA_3, + &PAD36_SD1_DATA_3, &PAD47_SD1_DATA_3); + +/* PINCTRL_DEVICE */ +PINCTRL_DEVICE(ACI2S, 5, &MUX_AC_I2S_CLK, &MUX_AC_I2S_DI, &MUX_AC_I2S_DO, + &MUX_AC_I2S_WS, &MUX_AC_MCLK); +PINCTRL_DEVICE(AC_MCLK, 1, &MUX_AC_MCLK); +PINCTRL_DEVICE(ARCJTAG, 5, &MUX_ARC_JTAG_TCK, &MUX_ARC_JTAG_TDI, + &MUX_ARC_JTAG_TDO, &MUX_ARC_JTAG_TMS, &MUX_ARC_JTAG_TRSTN); +PINCTRL_DEVICE(ARMJTAG, 5, &MUX_ARM_JTAG_TCK, &MUX_ARM_JTAG_TDI, + &MUX_ARM_JTAG_TDO, &MUX_ARM_JTAG_TMS, &MUX_ARM_JTAG_TRSTN); +PINCTRL_DEVICE(DWI2S, 4, &MUX_DW_I2S_CLK, &MUX_DW_I2S_DI, &MUX_DW_I2S_DO, + &MUX_DW_I2S_WS); +PINCTRL_DEVICE(ETH, 2, &MUX_ETH_LINK_ACT, &MUX_ETH_LINK_STA); +PINCTRL_DEVICE(I2C0, 2, &MUX_I2C0_SCL, &MUX_I2C0_SDA); +PINCTRL_DEVICE(I2C1, 2, &MUX_I2C1_SCL, &MUX_I2C1_SDA); +PINCTRL_DEVICE(I2C2, 2, &MUX_I2C2_SCL, &MUX_I2C2_SDA); +PINCTRL_DEVICE(PAEJTAG, 5, &MUX_PAE_JTAG_TCK, &MUX_PAE_JTAG_TDI, + &MUX_PAE_JTAG_TDO, &MUX_PAE_JTAG_TMS, &MUX_PAE_JTAG_TRSTN); +PINCTRL_DEVICE(PWM0, 1, &MUX_PWM0); +PINCTRL_DEVICE(PWM1, 1, &MUX_PWM1); +PINCTRL_DEVICE(PWM10, 1, &MUX_PWM10); +PINCTRL_DEVICE(PWM11, 1, &MUX_PWM11); +PINCTRL_DEVICE(PWM2, 1, &MUX_PWM2); +PINCTRL_DEVICE(PWM3, 1, &MUX_PWM3); +PINCTRL_DEVICE(PWM4, 1, &MUX_PWM4); +PINCTRL_DEVICE(PWM5, 1, &MUX_PWM5); +PINCTRL_DEVICE(PWM6, 1, &MUX_PWM6); +PINCTRL_DEVICE(PWM7, 1, &MUX_PWM7); +PINCTRL_DEVICE(PWM8, 1, &MUX_PWM8); +PINCTRL_DEVICE(PWM9, 1, &MUX_PWM9); +PINCTRL_DEVICE(RMII, 10, &MUX_MAC_MDC, &MUX_MAC_MDIO, &MUX_MAC_REF_CLK, + &MUX_MAC_RMII_CLK, &MUX_MAC_RXDV, &MUX_MAC_RXD_0, &MUX_MAC_RXD_1, + &MUX_MAC_TXD_0, &MUX_MAC_TXD_1, &MUX_MAC_TXEN); +PINCTRL_DEVICE(RTC, 1, &MUX_RTC_CLK); +PINCTRL_DEVICE(SADC_XAIN0, 1, &MUX_SADC_XAIN0); +PINCTRL_DEVICE(SADC_XAIN1, 1, &MUX_SADC_XAIN1); +PINCTRL_DEVICE(SADC_XAIN2, 1, &MUX_SADC_XAIN2); +PINCTRL_DEVICE(SADC_XAIN3, 1, &MUX_SADC_XAIN3); +PINCTRL_DEVICE(SD0, 7, &MUX_SD0_CD, &MUX_SD0_CLK, &MUX_SD0_CMD_RSP, + &MUX_SD0_DATA_0, &MUX_SD0_DATA_1, &MUX_SD0_DATA_2, &MUX_SD0_DATA_3); +PINCTRL_DEVICE(SD0_1BIT_NO_WP, 4, &MUX_SD0_CD, &MUX_SD0_CLK, &MUX_SD0_CMD_RSP, + &MUX_SD0_DATA_0); +PINCTRL_DEVICE(SD0_NO_WP, 7, &MUX_SD0_CD, &MUX_SD0_CLK, &MUX_SD0_CMD_RSP, + &MUX_SD0_DATA_0, &MUX_SD0_DATA_1, &MUX_SD0_DATA_2, &MUX_SD0_DATA_3); +PINCTRL_DEVICE(SD0_WIFI, 6, &MUX_SD0_CLK, &MUX_SD0_CMD_RSP, &MUX_SD0_DATA_0, + &MUX_SD0_DATA_1, &MUX_SD0_DATA_2, &MUX_SD0_DATA_3); +PINCTRL_DEVICE(SD1, 7, &MUX_SD1_CD, &MUX_SD1_CLK, &MUX_SD1_CMD_RSP, + &MUX_SD1_DATA_0, &MUX_SD1_DATA_1, &MUX_SD1_DATA_2, &MUX_SD1_DATA_3); +PINCTRL_DEVICE(SD1_1BIT_NO_WP, 4, &MUX_SD1_CD, &MUX_SD1_CLK, &MUX_SD1_CMD_RSP, + &MUX_SD1_DATA_0); +PINCTRL_DEVICE(SD1_NO_WP, 7, &MUX_SD1_CD, &MUX_SD1_CLK, &MUX_SD1_CMD_RSP, + &MUX_SD1_DATA_0, &MUX_SD1_DATA_1, &MUX_SD1_DATA_2, &MUX_SD1_DATA_3); +PINCTRL_DEVICE(SD1_WIFI, 6, &MUX_SD1_CLK, &MUX_SD1_CMD_RSP, &MUX_SD1_DATA_0, + &MUX_SD1_DATA_1, &MUX_SD1_DATA_2, &MUX_SD1_DATA_3); +PINCTRL_DEVICE(SENSOR_CLK, 1, &MUX_SENSOR_CLK); +PINCTRL_DEVICE(SSI0, 4, &MUX_GPIO6, &MUX_SSI0_CLK, &MUX_SSI0_RXD, + &MUX_SSI0_TXD); +PINCTRL_DEVICE(SSI0_4BIT, 6, &MUX_GPIO6, &MUX_SSI0_CLK, &MUX_SSI0_D2, + &MUX_SSI0_D3, &MUX_SSI0_RXD, &MUX_SSI0_TXD); +PINCTRL_DEVICE(SSI1, 4, &MUX_GPIO14, &MUX_SSI1_CLK, &MUX_SSI1_RXD, + &MUX_SSI1_TXD); +PINCTRL_DEVICE(SSI2, 4, &MUX_SSI2_CLK, &MUX_SSI2_CSN_0, &MUX_SSI2_RXD, + &MUX_SSI2_TXD); +PINCTRL_DEVICE(UART0, 2, &MUX_UART0_RX, &MUX_UART0_TX); +PINCTRL_DEVICE(UART1, 2, &MUX_UART1_RX, &MUX_UART1_TX); +PINCTRL_DEVICE(UART2, 2, &MUX_UART2_RX, &MUX_UART2_TX); +PINCTRL_DEVICE(USB, 1, &MUX_USB_PWREN); +PINCTRL_DEVICE(GPIO0, 1, &MUX_GPIO0); +PINCTRL_DEVICE(GPIO1, 1, &MUX_GPIO1); +PINCTRL_DEVICE(GPIO2, 1, &MUX_GPIO2); +PINCTRL_DEVICE(GPIO3, 1, &MUX_GPIO3); +PINCTRL_DEVICE(GPIO4, 1, &MUX_GPIO4); +PINCTRL_DEVICE(GPIO5, 1, &MUX_GPIO5); +PINCTRL_DEVICE(GPIO6, 1, &MUX_GPIO6); +PINCTRL_DEVICE(GPIO7, 1, &MUX_GPIO7); +PINCTRL_DEVICE(GPIO8, 1, &MUX_GPIO8); +PINCTRL_DEVICE(GPIO9, 1, &MUX_GPIO9); +PINCTRL_DEVICE(GPIO10, 1, &MUX_GPIO10); +PINCTRL_DEVICE(GPIO11, 1, &MUX_GPIO11); +PINCTRL_DEVICE(GPIO12, 1, &MUX_GPIO12); +PINCTRL_DEVICE(GPIO13, 1, &MUX_GPIO13); +PINCTRL_DEVICE(GPIO14, 1, &MUX_GPIO14); +PINCTRL_DEVICE(GPIO15, 1, &MUX_GPIO15); +PINCTRL_DEVICE(GPIO16, 1, &MUX_GPIO16); +PINCTRL_DEVICE(GPIO17, 1, &MUX_GPIO17); +PINCTRL_DEVICE(GPIO18, 1, &MUX_GPIO18); +PINCTRL_DEVICE(GPIO19, 1, &MUX_GPIO19); +PINCTRL_DEVICE(GPIO20, 1, &MUX_GPIO20); +PINCTRL_DEVICE(GPIO21, 1, &MUX_GPIO21); +PINCTRL_DEVICE(GPIO22, 1, &MUX_GPIO22); +PINCTRL_DEVICE(GPIO23, 1, &MUX_GPIO23); +PINCTRL_DEVICE(GPIO24, 1, &MUX_GPIO24); +PINCTRL_DEVICE(GPIO25, 1, &MUX_GPIO25); +PINCTRL_DEVICE(GPIO26, 1, &MUX_GPIO26); +PINCTRL_DEVICE(GPIO27, 1, &MUX_GPIO27); +PINCTRL_DEVICE(GPIO28, 1, &MUX_GPIO28); +PINCTRL_DEVICE(GPIO29, 1, &MUX_GPIO29); +PINCTRL_DEVICE(GPIO30, 1, &MUX_GPIO30); +PINCTRL_DEVICE(GPIO31, 1, &MUX_GPIO31); +PINCTRL_DEVICE(GPIO32, 1, &MUX_GPIO32); +PINCTRL_DEVICE(GPIO33, 1, &MUX_GPIO33); +PINCTRL_DEVICE(GPIO34, 1, &MUX_GPIO34); +PINCTRL_DEVICE(GPIO35, 1, &MUX_GPIO35); +PINCTRL_DEVICE(GPIO36, 1, &MUX_GPIO36); +PINCTRL_DEVICE(GPIO37, 1, &MUX_GPIO37); +PINCTRL_DEVICE(GPIO38, 1, &MUX_GPIO38); +PINCTRL_DEVICE(GPIO39, 1, &MUX_GPIO39); +PINCTRL_DEVICE(GPIO40, 1, &MUX_GPIO40); +PINCTRL_DEVICE(GPIO41, 1, &MUX_GPIO41); +PINCTRL_DEVICE(GPIO42, 1, &MUX_GPIO42); +PINCTRL_DEVICE(GPIO43, 1, &MUX_GPIO43); +PINCTRL_DEVICE(GPIO44, 1, &MUX_GPIO44); +PINCTRL_DEVICE(GPIO45, 1, &MUX_GPIO45); +PINCTRL_DEVICE(GPIO46, 1, &MUX_GPIO46); +PINCTRL_DEVICE(GPIO47, 1, &MUX_GPIO47); +PINCTRL_DEVICE(GPIO48, 1, &MUX_GPIO48); +PINCTRL_DEVICE(GPIO49, 1, &MUX_GPIO49); +PINCTRL_DEVICE(GPIO50, 1, &MUX_GPIO50); +PINCTRL_DEVICE(GPIO51, 1, &MUX_GPIO51); +PINCTRL_DEVICE(GPIO52, 1, &MUX_GPIO52); +PINCTRL_DEVICE(GPIO53, 1, &MUX_GPIO53); +PINCTRL_DEVICE(GPIO54, 1, &MUX_GPIO54); +PINCTRL_DEVICE(GPIO55, 1, &MUX_GPIO55); +PINCTRL_DEVICE(GPIO56, 1, &MUX_GPIO56); +PINCTRL_DEVICE(GPIO57, 1, &MUX_GPIO57); +PINCTRL_DEVICE(GPIO58, 1, &MUX_GPIO58); +PINCTRL_DEVICE(GPIO59, 1, &MUX_GPIO59); +PINCTRL_DEVICE(GPIO60, 1, &MUX_GPIO60); +PINCTRL_DEVICE(GPIO61, 1, &MUX_GPIO61); +PINCTRL_DEVICE(GPIO62, 1, &MUX_GPIO62); +PINCTRL_DEVICE(GPIO63, 1, &MUX_GPIO63); + +PINCTRL_DEVICE(SD1_EMMC, 6, &MUX_SD1_CLK_EMMC, &MUX_SD1_CMD_RSP_EMMC, + &MUX_SD1_DATA_0_EMMC, &MUX_SD1_DATA_1_EMMC, &MUX_SD1_DATA_2_EMMC, + &MUX_SD1_DATA_3_EMMC); + +void fh_pinctrl_init_devicelist(OS_LIST *list) +{ + OS_LIST_EMPTY(list); + + /*PINCTRL_ADD_DEVICE*/ + PINCTRL_ADD_DEVICE(ACI2S); + PINCTRL_ADD_DEVICE(AC_MCLK); + PINCTRL_ADD_DEVICE(ARCJTAG); + PINCTRL_ADD_DEVICE(ARMJTAG); + PINCTRL_ADD_DEVICE(DWI2S); + PINCTRL_ADD_DEVICE(ETH); + PINCTRL_ADD_DEVICE(I2C0); + PINCTRL_ADD_DEVICE(I2C1); + PINCTRL_ADD_DEVICE(I2C2); + PINCTRL_ADD_DEVICE(PAEJTAG); + PINCTRL_ADD_DEVICE(PWM0); + PINCTRL_ADD_DEVICE(PWM1); + PINCTRL_ADD_DEVICE(PWM10); + PINCTRL_ADD_DEVICE(PWM11); + PINCTRL_ADD_DEVICE(PWM2); + PINCTRL_ADD_DEVICE(PWM3); + PINCTRL_ADD_DEVICE(PWM4); + PINCTRL_ADD_DEVICE(PWM5); + PINCTRL_ADD_DEVICE(PWM6); + PINCTRL_ADD_DEVICE(PWM7); + PINCTRL_ADD_DEVICE(PWM8); + PINCTRL_ADD_DEVICE(PWM9); + PINCTRL_ADD_DEVICE(RMII); + PINCTRL_ADD_DEVICE(RTC); + PINCTRL_ADD_DEVICE(SADC_XAIN0); + PINCTRL_ADD_DEVICE(SADC_XAIN1); + PINCTRL_ADD_DEVICE(SADC_XAIN2); + PINCTRL_ADD_DEVICE(SADC_XAIN3); + PINCTRL_ADD_DEVICE(SD0); + PINCTRL_ADD_DEVICE(SD0_1BIT_NO_WP); + PINCTRL_ADD_DEVICE(SD0_NO_WP); + PINCTRL_ADD_DEVICE(SD0_WIFI); + PINCTRL_ADD_DEVICE(SD1); + PINCTRL_ADD_DEVICE(SD1_1BIT_NO_WP); + PINCTRL_ADD_DEVICE(SD1_NO_WP); + PINCTRL_ADD_DEVICE(SD1_WIFI); + PINCTRL_ADD_DEVICE(SENSOR_CLK); + PINCTRL_ADD_DEVICE(SSI0); + PINCTRL_ADD_DEVICE(SSI0_4BIT); + PINCTRL_ADD_DEVICE(SSI1); + PINCTRL_ADD_DEVICE(SSI2); + PINCTRL_ADD_DEVICE(UART0); + PINCTRL_ADD_DEVICE(UART1); + PINCTRL_ADD_DEVICE(UART2); + PINCTRL_ADD_DEVICE(USB); + PINCTRL_ADD_DEVICE(GPIO0); + PINCTRL_ADD_DEVICE(GPIO1); + PINCTRL_ADD_DEVICE(GPIO2); + PINCTRL_ADD_DEVICE(GPIO3); + PINCTRL_ADD_DEVICE(GPIO4); + PINCTRL_ADD_DEVICE(GPIO5); + PINCTRL_ADD_DEVICE(GPIO6); + PINCTRL_ADD_DEVICE(GPIO7); + PINCTRL_ADD_DEVICE(GPIO8); + PINCTRL_ADD_DEVICE(GPIO9); + PINCTRL_ADD_DEVICE(GPIO10); + PINCTRL_ADD_DEVICE(GPIO11); + PINCTRL_ADD_DEVICE(GPIO12); + PINCTRL_ADD_DEVICE(GPIO13); + PINCTRL_ADD_DEVICE(GPIO14); + PINCTRL_ADD_DEVICE(GPIO15); + PINCTRL_ADD_DEVICE(GPIO16); + PINCTRL_ADD_DEVICE(GPIO17); + PINCTRL_ADD_DEVICE(GPIO18); + PINCTRL_ADD_DEVICE(GPIO19); + PINCTRL_ADD_DEVICE(GPIO20); + PINCTRL_ADD_DEVICE(GPIO21); + PINCTRL_ADD_DEVICE(GPIO22); + PINCTRL_ADD_DEVICE(GPIO23); + PINCTRL_ADD_DEVICE(GPIO24); + PINCTRL_ADD_DEVICE(GPIO25); + PINCTRL_ADD_DEVICE(GPIO26); + PINCTRL_ADD_DEVICE(GPIO27); + PINCTRL_ADD_DEVICE(GPIO28); + PINCTRL_ADD_DEVICE(GPIO29); + PINCTRL_ADD_DEVICE(GPIO30); + PINCTRL_ADD_DEVICE(GPIO31); + PINCTRL_ADD_DEVICE(GPIO32); + PINCTRL_ADD_DEVICE(GPIO33); + PINCTRL_ADD_DEVICE(GPIO34); + PINCTRL_ADD_DEVICE(GPIO35); + PINCTRL_ADD_DEVICE(GPIO36); + PINCTRL_ADD_DEVICE(GPIO37); + PINCTRL_ADD_DEVICE(GPIO38); + PINCTRL_ADD_DEVICE(GPIO39); + PINCTRL_ADD_DEVICE(GPIO40); + PINCTRL_ADD_DEVICE(GPIO41); + PINCTRL_ADD_DEVICE(GPIO42); + PINCTRL_ADD_DEVICE(GPIO43); + PINCTRL_ADD_DEVICE(GPIO44); + PINCTRL_ADD_DEVICE(GPIO45); + PINCTRL_ADD_DEVICE(GPIO46); + PINCTRL_ADD_DEVICE(GPIO47); + PINCTRL_ADD_DEVICE(GPIO48); + PINCTRL_ADD_DEVICE(GPIO49); + PINCTRL_ADD_DEVICE(GPIO50); + PINCTRL_ADD_DEVICE(GPIO51); + PINCTRL_ADD_DEVICE(GPIO52); + PINCTRL_ADD_DEVICE(GPIO53); + PINCTRL_ADD_DEVICE(GPIO54); + PINCTRL_ADD_DEVICE(GPIO55); + PINCTRL_ADD_DEVICE(GPIO56); + PINCTRL_ADD_DEVICE(GPIO57); + PINCTRL_ADD_DEVICE(GPIO58); + PINCTRL_ADD_DEVICE(GPIO59); + PINCTRL_ADD_DEVICE(GPIO60); + PINCTRL_ADD_DEVICE(GPIO61); + PINCTRL_ADD_DEVICE(GPIO62); + PINCTRL_ADD_DEVICE(GPIO63); + + PINCTRL_ADD_DEVICE(SD1_EMMC); +} + +char *fh_pinctrl_selected_devices[] = +{ + CONFIG_PINCTRL_SELECT +}; diff --git a/arch/arm/mach-fh/fh8852v210/Makefile b/arch/arm/mach-fh/fh8852v210/Makefile new file mode 100644 index 00000000..1443fdae --- /dev/null +++ b/arch/arm/mach-fh/fh8852v210/Makefile @@ -0,0 +1 @@ +obj-y += board.o chip.o \ No newline at end of file diff --git a/arch/arm/mach-fh/fh8852v210/board.c b/arch/arm/mach-fh/fh8852v210/board.c new file mode 100644 index 00000000..21655fca --- /dev/null +++ b/arch/arm/mach-fh/fh8852v210/board.c @@ -0,0 +1,1166 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +struct uart_port fh_serial_ports[FH_UART_NUMBER]; + +static struct map_desc fh8852v210_io_desc[] = { + { + .virtual = VA_RAM_REG_BASE, + .pfn = __phys_to_pfn(RAM_BASE), + .length = SZ_16K, + .type = MT_MEMORY_RWX, + }, + { + .virtual = VA_DDRC_REG_BASE, + .pfn = __phys_to_pfn(DDRC_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_INTC_REG_BASE, + .pfn = __phys_to_pfn(INTC_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_TIMER_REG_BASE, + .pfn = __phys_to_pfn(TIMER_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_PMU_REG_BASE, + .pfn = __phys_to_pfn(PMU_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_UART0_REG_BASE, + .pfn = __phys_to_pfn(UART0_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_UART1_REG_BASE, + .pfn = __phys_to_pfn(UART1_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_UART2_REG_BASE, + .pfn = __phys_to_pfn(UART2_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + +}; + +static struct resource fh_gpio0_resources[] = { + { + .start = GPIO0_REG_BASE, + .end = GPIO0_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = GPIO0_IRQ, + .end = GPIO0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_gpio1_resources[] = { + { + .start = GPIO1_REG_BASE, + .end = GPIO1_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = GPIO1_IRQ, + .end = GPIO1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_uart0_resources[] = { + { + .start = (UART0_REG_BASE), + .end = (UART0_REG_BASE) + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = UART0_IRQ, + .end = UART0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_uart1_resources[] = { + { + .start = (UART1_REG_BASE), + .end = (UART1_REG_BASE) + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = UART1_IRQ, + .end = UART1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_uart2_resources[] = { + { + .start = (UART2_REG_BASE), + .end = (UART2_REG_BASE) + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = UART2_IRQ, + .end = UART2_IRQ, + .flags = IORESOURCE_IRQ, + } +}; +static struct resource fh_sdc0_resources[] = { + { + .start = SDC0_REG_BASE, + .end = SDC0_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SDC0_IRQ, + .end = SDC0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_sdc1_resources[] = { + { + .start = SDC1_REG_BASE, + .end = SDC1_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SDC1_IRQ, + .end = SDC1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_gmac_resources[] = { + { + .start = GMAC_REG_BASE, + .end = GMAC_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = GMAC_IRQ, + .end = GMAC_IRQ, + .flags = IORESOURCE_IRQ, + } +}; + +static struct resource fh_wdt_resources[] = { + { + .start = WDT_REG_BASE, + .end = WDT_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = WDT_IRQ, + .end = WDT_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +#ifdef CONFIG_FH_PERF_MON +static struct resource fh_perf_resources[] = { + { + .start = PMU_REG_BASE, + .end = PMU_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = PERF_IRQ, + .end = PERF_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +#endif + + +static struct fh_gmac_platform_data fh_gmac_data = { + .phy_reset_pin = 29, +}; + +static struct fh_uart_dma uart1_dma_info = { +#ifdef CONFIG_UART_TX_DMA + .tx_hs_no = UART1_TX_HW_HANDSHAKE, + .tx_dma_channel = UART1_DMA_TX_CHAN, +#endif + .rx_hs_no = UART1_RX_HW_HANDSHAKE, + .rx_dma_channel = UART1_DMA_RX_CHAN, + .rx_xmit_len = 16, +}; + +static struct fh_uart_dma uart2_dma_info = { +#ifdef CONFIG_UART_TX_DMA + .tx_hs_no = UART2_TX_HW_HANDSHAKE, + .tx_dma_channel = UART2_DMA_TX_CHAN, +#endif + .rx_hs_no = UART2_RX_HW_HANDSHAKE, + .rx_dma_channel = UART2_DMA_RX_CHAN, + .rx_xmit_len = 16, +}; + + +static struct fh_platform_uart fh_uart_platform_data[] = { + { + .mapbase = UART0_REG_BASE, + .fifo_size = 16, + .irq = UART0_IRQ, + .uartclk = 16666667, + .use_dma = 0, + .dma_info = NULL, + }, + { + .mapbase = UART1_REG_BASE, + .fifo_size = 32, + .irq = UART1_IRQ, + .uartclk = 16666667, + .use_dma = 0, + .dma_info = &uart1_dma_info, + }, + { + .mapbase = UART2_REG_BASE, + .fifo_size = 32, + .irq = UART2_IRQ, + .uartclk = 16666667, + .use_dma = 0, + .dma_info = &uart2_dma_info, + }, +}; + +static struct resource fh_pwm_resources[] = { + { + .start = PWM_REG_BASE, + .end = PWM_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = PWM_IRQ, + .end = PWM_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_i2c_resources_0[] = { + { + .start = I2C0_REG_BASE, + .end = I2C0_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = I2C0_IRQ, + .end = I2C0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_i2c_resources_1[] = { + { + .start = I2C1_REG_BASE, + .end = I2C1_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = I2C1_IRQ, + .end = I2C1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_i2c_resources_2[] = { + { + .start = I2C2_REG_BASE, + .end = I2C2_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = I2C2_IRQ, + .end = I2C2_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_rtc_resources[] = { + { + .start = RTC_REG_BASE, + .end = RTC_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = RTC_IRQ, + .end = RTC_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct fh_gpio_chip fh_gpio0_chip = { + .chip = { + .owner = THIS_MODULE, + .label = "FH_GPIO0", + .base = 0, + .ngpio = 32, + }, +}; + +static struct fh_gpio_chip fh_gpio1_chip = { + .chip = { + .owner = THIS_MODULE, + .label = "FH_GPIO1", + .base = 32, + .ngpio = 32, + }, +}; + +static struct fh_pwm_data pwm_data = { + .npwm = 12, +}; + +static struct resource fh_sadc_resources[] = { + { + .start = SADC_REG_BASE, + .end = SADC_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SADC_IRQ, + .end = SADC_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_aes_resources[] = { + { + .start = AES_REG_BASE, + .end = AES_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = AES_IRQ, + .end = AES_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_efuse_resources[] = { + { + .start = EFUSE_REG_BASE, + .end = EFUSE_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +#ifdef CONFIG_FH_DMAC +static struct resource fh_dma_resources[] = { + { + .start = (DMAC_REG_BASE), + .end = (DMAC_REG_BASE) + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = DMAC0_IRQ, + .end = DMAC0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +#endif + +#ifdef CONFIG_FH_AXI_DMAC +static struct resource fh_axi_dma_resources[] = { + { + .start = (DMAC_REG_BASE), + .end = (DMAC_REG_BASE) + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = DMAC0_IRQ, + .end = DMAC0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +#endif + +static struct resource fh_spi0_resources[] = { + { + .start = SPI0_REG_BASE, + .end = SPI0_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SPI0_IRQ, + .end = SPI0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_spi1_resources[] = { + { + .start = SPI1_REG_BASE, + .end = SPI1_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SPI1_IRQ, + .end = SPI1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_spi2_resources[] = { + { + .start = SPI2_REG_BASE, + .end = SPI2_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + .name = "fh spi2 mem", + }, + { + .start = SPI2_IRQ, + .end = SPI2_IRQ, + .flags = IORESOURCE_IRQ, + .name = "fh spi2 irq", + }, +}; + +static struct resource fh_usb_resources[] = { + { + .start = USBC_REG_BASE, + .end = USBC_REG_BASE + SZ_1M - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = USBC_IRQ, + .end = USBC_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static unsigned int fh_mci_sys_card_detect_fixed(struct fhmci_host *host) +{ + return 0; +} + +struct fh_mci_board fh_mci = { + .num_slots = 1, + .get_cd = fh_mci_sys_card_detect_fixed, + .bus_hz = 50000000, + .detect_delay_ms = 200, + .caps = MMC_CAP_4_BIT_DATA, + /*8:180 degree*/ + .drv_degree = 8, + .sam_degree = 0, + .rescan_max_num = 2, +}; + +struct fh_mci_board fh_mci_sd = { + .num_slots = 1, + .bus_hz = 50000000, + .detect_delay_ms = 200, + .caps = MMC_CAP_4_BIT_DATA, + /*8:180 degree*/ + .drv_degree = 8, + .sam_degree = 0, +}; + +static struct platform_device fh_gmac_device = { + .name = "fh_gmac", + .id = 0, + .num_resources = ARRAY_SIZE(fh_gmac_resources), + .resource = fh_gmac_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &fh_gmac_data, + }, +}; + +struct platform_device fh_sd0_device = { + .name = "fh_mci", + .id = 0, + .num_resources = ARRAY_SIZE(fh_sdc0_resources), + .resource = fh_sdc0_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &fh_mci_sd, + } +}; + +struct platform_device fh_sd1_device = { + .name = "fh_mci", + .id = 1, + .num_resources = ARRAY_SIZE(fh_sdc1_resources), + .resource = fh_sdc1_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &fh_mci, + } +}; + +struct fh_sadc_platform_data fh_sadc_data = { + .ref_vol = 1800, + .active_bit = 0xfff, +}; + +static struct platform_device fh_sadc_device = { + .name = "fh_sadc", + .id = 0, + .num_resources = ARRAY_SIZE(fh_sadc_resources), + .resource = fh_sadc_resources, + .dev = { + .platform_data = &fh_sadc_data, + }, +}; + +static struct platform_device fh_uart0_device = { + .name = "ttyS", + .id = 0, + .num_resources = ARRAY_SIZE(fh_uart0_resources), + .resource = fh_uart0_resources, + .dev.platform_data = &fh_uart_platform_data[0], +}; + +static struct platform_device fh_uart1_device = { + .name = "ttyS", + .id = 1, + .num_resources = ARRAY_SIZE(fh_uart1_resources), + .resource = fh_uart1_resources, + .dev.platform_data = &fh_uart_platform_data[1], +}; + +static struct platform_device fh_uart2_device = { + .name = "ttyS", + .id = 2, + .num_resources = ARRAY_SIZE(fh_uart2_resources), + .resource = fh_uart2_resources, + .dev.platform_data = &fh_uart_platform_data[2], +}; + +static struct platform_device fh_pinctrl_device = { + .name = "fh_pinctrl", + .id = 0, +}; + +static struct platform_device fh_i2c0_device = { + .name = "fh_i2c", + .id = 0, + .num_resources = ARRAY_SIZE(fh_i2c_resources_0), + .resource = fh_i2c_resources_0, +}; + +static struct platform_device fh_i2c1_device = { + .name = "fh_i2c", + .id = 1, + .num_resources = ARRAY_SIZE(fh_i2c_resources_1), + .resource = fh_i2c_resources_1, +}; + +static struct platform_device fh_i2c2_device = { + .name = "fh_i2c", + .id = 2, + .num_resources = ARRAY_SIZE(fh_i2c_resources_2), + .resource = fh_i2c_resources_2, +}; + +static struct fh_rtc_plat_data rtc_plat_data[] = { + { + .lut_cof = 58, + .lut_offset = 0xff, + .tsensor_cp_default_out = 0x993, + .clk_name = "rtc_hclk_gate", + }, + { + .lut_cof = 71, + .lut_offset = 0xf6, + .tsensor_cp_default_out = 0x9cc, + .clk_name = "rtc_hclk_gate", + } +}; + +static struct platform_device fh_rtc_device = { + .name = "fh_rtc", + .id = 0, + .num_resources = ARRAY_SIZE(fh_rtc_resources), + .resource = fh_rtc_resources, + .dev.platform_data = &rtc_plat_data[0], +}; + +static struct resource fh_i2s_resources[] = { + { + .start = I2S_REG_BASE, + .end = I2S_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = ACW_REG_BASE, + .end = ACW_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = I2S0_IRQ, + .end = I2S0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct fh_i2s_platform_data fh_i2s_data = { + .dma_capture_channel = 4, + .dma_playback_channel = 5, + .dma_master = 0, + .dma_rx_hs_num = 10, + .dma_tx_hs_num = 11, + .clk = "i2s_clk", + .acodec_mclk = "ac_clk", +}; + +static struct platform_device fh_i2s_device = { + .name = "fh_audio", + .id = 0, + .num_resources = ARRAY_SIZE(fh_i2s_resources), + .resource = fh_i2s_resources, + .dev = { + .platform_data = &fh_i2s_data, + }, +}; + +static struct platform_device fh_gpio0_device = { + .name = GPIO_NAME, + .id = 0, + .num_resources = ARRAY_SIZE(fh_gpio0_resources), + .resource = fh_gpio0_resources, + .dev = { + .platform_data = &fh_gpio0_chip, + }, +}; + +static struct platform_device fh_gpio1_device = { + .name = GPIO_NAME, + .id = 1, + .num_resources = ARRAY_SIZE(fh_gpio1_resources), + .resource = fh_gpio1_resources, + .dev = { + .platform_data = &fh_gpio1_chip, + }, +}; + +static struct platform_device fh_aes_device = { + .name = "fh_aes", + .id = 0, + .num_resources = ARRAY_SIZE(fh_aes_resources), + .resource = fh_aes_resources, + .dev = { + .platform_data = NULL, + }, +}; + +struct fh_efuse_platform_data fh_efuse_plat_data = { + .efuse_support_flag = CRYPTO_CPU_SET_KEY | + CRYPTO_EX_MEM_SET_KEY | + CRYPTO_EX_MEM_SWITCH_KEY | + CRYPTO_EX_MEM_4_ENTRY_1_KEY | + CRYPTO_EX_MEM_INDEP_POWER, +}; + + + +#define FH_SPI0_CS0 (6) +#define FH_SPI0_CS1 (55) + +#define FH_SPI1_CS0 (14) +#define FH_SPI1_CS1 (57) + +#define SPI0_FIFO_DEPTH (128) +#define SPI0_CLK_IN (200000000) +#define SPI0_MAX_SLAVE_NO (2) +#define SPI0_DMA_RX_CHANNEL (0) +#define SPI0_DMA_TX_CHANNEL (1) + +#define SPI1_FIFO_DEPTH (64) +#define SPI1_CLK_IN (100000000) +#define SPI1_MAX_SLAVE_NO (2) +#define SPI1_DMA_RX_CHANNEL (2) +#define SPI1_DMA_TX_CHANNEL (3) + +#define SPI2_CLK_IN (100000000) + +/* SPI_TRANSFER_USE_DMA */ +static struct fh_spi_platform_data fh_spi0_data = { + .bus_no = 0, + .apb_clock_in = SPI0_CLK_IN, + .clock_source = {100000000, 150000000, 200000000}, + .clock_source_num = 3, + .slave_max_num = SPI0_MAX_SLAVE_NO, + .cs_data[0].GPIO_Pin = FH_SPI0_CS0, + .cs_data[0].name = "spi0_cs0", + .cs_data[1].GPIO_Pin = FH_SPI0_CS1, + .cs_data[1].name = "spi0_cs1", + .clk_name = "spi0_clk", + .dma_transfer_enable = SPI_TRANSFER_USE_DMA, + .rx_dma_channel = SPI0_DMA_RX_CHANNEL, + .rx_handshake_num = 4, + /*dma use inc mode could move data by burst mode...*/ + /*or move data use single mode with low efficient*/ + .ctl_wire_support = ONE_WIRE_SUPPORT | DUAL_WIRE_SUPPORT | + MULTI_WIRE_SUPPORT, +}; + +static struct fh_spi_platform_data fh_spi1_data = { + .bus_no = 1, + .apb_clock_in = SPI1_CLK_IN, + .clock_source = {SPI1_CLK_IN}, + .clock_source_num = 1, + .slave_max_num = SPI1_MAX_SLAVE_NO, + .cs_data[0].GPIO_Pin = FH_SPI1_CS0, + .cs_data[0].name = "spi1_cs0", + .cs_data[1].GPIO_Pin = FH_SPI1_CS1, + .cs_data[1].name = "spi1_cs1", + .clk_name = "spi1_clk", + .ctl_wire_support = 0, +}; + +static struct fh_spi_platform_data fh_spi2_data = { + .apb_clock_in = SPI2_CLK_IN, + .dma_transfer_enable = 0, + .rx_handshake_num = 12, + .clk_name = "spi2_clk", + .ctl_wire_support = 0, +}; + +static struct platform_device fh_efuse_device = { + .name = "fh_efuse", + .id = 0, + .num_resources = ARRAY_SIZE(fh_efuse_resources), + .resource = fh_efuse_resources, + .dev = { + .platform_data = &fh_efuse_plat_data, + }, +}; + +#ifdef CONFIG_FH_DMAC +static struct fh_dma_platform_data fh_dma_data = { + .chan_priority = CHAN_PRIORITY_ASCENDING, + .nr_channels = 6, + .clk_name = "ahb_clk", +}; + +static struct platform_device fh_dma_device = { + .name = "fh_dmac", + .id = 0, + .num_resources = ARRAY_SIZE(fh_dma_resources), + .resource = fh_dma_resources, + .dev = { + .platform_data = &fh_dma_data, + }, +}; +#endif + +#ifdef CONFIG_FH_AXI_DMAC +struct fh_axi_dma_platform_data axi_dma_plat_data = { + .chan_priority = CHAN_PRIORITY_ASCENDING, + .clk_name = "ahb_clk", +}; + +static struct platform_device fh_axi_dma_device = { + .name = "fh_axi_dmac", + .id = 0, + .num_resources = ARRAY_SIZE(fh_axi_dma_resources), + .resource = fh_axi_dma_resources, + .dev = { + .platform_data = &axi_dma_plat_data, + }, +}; +#endif + + + +static struct platform_device fh_spi0_device = { + .name = "fh_spi", + .id = 0, + .num_resources = ARRAY_SIZE(fh_spi0_resources), + .resource = fh_spi0_resources, + .dev = { + .platform_data = &fh_spi0_data, + }, +}; + +static struct platform_device fh_spi1_device = { + .name = "fh_spi", + .id = 1, + .num_resources = ARRAY_SIZE(fh_spi1_resources), + .resource = fh_spi1_resources, + .dev = { + .platform_data = &fh_spi1_data, + }, +}; + +static struct platform_device fh_spi2_device = { + .name = "fh_spi_slave", + .id = 0, + .num_resources = ARRAY_SIZE(fh_spi2_resources), + .resource = fh_spi2_resources, + .dev = { + .platform_data = &fh_spi2_data, + }, +}; + +#ifdef CONFIG_FH_PERF_MON +static struct platform_device fh_perf_device = { + .name = "fh_perf_mon", + .id = 0, + .num_resources = ARRAY_SIZE(fh_perf_resources), + .resource = fh_perf_resources, + .dev = { + .platform_data = NULL, + }, +}; +#endif + +static struct fh_wdt_platform_data fh_wdt_data = { + .mode = MODE_DISCRETE, +}; + +struct platform_device fh_wdt_device = { + .name = "fh_wdt", + .id = 0, + .num_resources = ARRAY_SIZE(fh_wdt_resources), + .resource = fh_wdt_resources, + .dev = { + .platform_data = &fh_wdt_data, + } +}; + +static struct platform_device fh_pwm_device = { + .name = "fh_pwm", + .id = 0, + .num_resources = ARRAY_SIZE(fh_pwm_resources), + .resource = fh_pwm_resources, + .dev = { + .platform_data = &pwm_data, + }, +}; + +static struct fh_usb_platform_data fh_usb_data = { + .dr_mode = "host", + .vbus_pwren = 47, +}; + +struct platform_device fh_usb_device = { + .name = "fh_usb", + .id = 0, + .num_resources = ARRAY_SIZE(fh_usb_resources), + .resource = fh_usb_resources, + .dev = { + .platform_data = &fh_usb_data, + } +}; + +#ifdef CONFIG_FH_TSENSOR +struct platform_device fh_tsensor_device = { + .name = "fh_tsensor", + .id = 0, +}; +#endif + +static struct platform_device *fh8852v210_devices[] __initdata = { + &fh_uart0_device, + &fh_uart1_device, + &fh_uart2_device, + &fh_pinctrl_device, + &fh_i2c0_device, + &fh_i2c1_device, + &fh_i2c2_device, + &fh_rtc_device, + &fh_sd0_device, + &fh_sd1_device, + &fh_sadc_device, + &fh_gmac_device, + &fh_gpio0_device, + &fh_gpio1_device, + &fh_aes_device, + &fh_efuse_device, +#ifdef CONFIG_FH_DMAC + &fh_dma_device, +#endif +#ifdef CONFIG_FH_AXI_DMAC + &fh_axi_dma_device, +#endif + &fh_spi0_device, + &fh_spi1_device, + &fh_spi2_device, + &fh_i2s_device, + &fh_pwm_device, + &fh_wdt_device, + &fh_usb_device, +#ifdef CONFIG_FH_PERF_MON + &fh_perf_device, +#endif +#ifdef CONFIG_FH_TSENSOR + &fh_tsensor_device, +#endif +}; + +static struct mtd_partition fh_sf_parts[] = { + { + /* head & Ramboot */ + .name = "bootstrap", + .offset = 0, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + /* Ramboot & U-Boot environment */ + .name = "uboot-env", + .offset = MTDPART_OFS_APPEND, + .size = SZ_64K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + /* U-Boot */ + .name = "uboot", + .offset = MTDPART_OFS_APPEND, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_4M, + .mask_flags = 0, + }, { + .name = "rootfs", + .offset = MTDPART_OFS_APPEND, + .size = SZ_8M, + .mask_flags = 0, + }, { + .name = "app", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + } + /* mtdparts= + * spi_flash:256k(bootstrap), + * 64k(u-boot-env), + * 192k(u-boot),4M(kernel), + * 8M(rootfs), + * -(app) */ + /* two blocks with bad block table (and mirror) at the end */ +}; +#ifdef CONFIG_MTD_SPI_NAND +static struct mtd_partition fh_sf_nand_parts[] = { + { + /* head & Ramboot */ + .name = "bootstrap", + .offset = 0, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + .name = "uboot-env", + .offset = MTDPART_OFS_APPEND, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "uboot", + .offset = MTDPART_OFS_APPEND, + .size = SZ_512K, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_4M, + .mask_flags = 0, + }, { + .name = "rootfs", + .offset = MTDPART_OFS_APPEND, + .size = SZ_8M, + .mask_flags = 0, + }, { + .name = "app", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + } + /* mtdparts= + * spi0.0:64k(bootstrap), + * 64k(u-boot-env), + * 192k(u-boot), + * 4M(kernel), + * 8M(rootfs), + * -(app) + * two blocks with bad block table (and mirror) at the end + */ +}; +#endif + +static struct flash_platform_data fh_flash_platform_data = { + .name = "spi_flash", + .parts = fh_sf_parts, + .nr_parts = ARRAY_SIZE(fh_sf_parts), +}; +#ifdef CONFIG_MTD_SPI_NAND +static struct flash_platform_data fh_nandflash_platform_data = { + .name = "spi_nandflash", + .parts = fh_sf_nand_parts, + .nr_parts = ARRAY_SIZE(fh_sf_nand_parts), +}; +#endif + +static struct spi_board_info fh_spi_devices[] = { +#ifdef CONFIG_MTD_SPI_NAND + { + .modalias = "spi-nand", + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 50000000, + .mode = SPI_MODE_3, + .platform_data = &fh_nandflash_platform_data, + }, +#endif + { + .modalias = "m25p80", + .bus_num = 0, + .chip_select = 0, + /* multi wire should adapt spi para 'ctl_wire_support'*/ + .mode = SPI_MODE_3 | SPI_RX_DUAL, + .max_speed_hz = 50000000, + .platform_data = &fh_flash_platform_data, + }, + +}; + +extern void early_print(const char *str, ...); + +static void __init fh_console_pre_init(struct fh_platform_uart *plat, int num) +{ + int idx = 0; + + for (; idx < num; idx++) { + struct uart_port *port; + + port = &fh_serial_ports[idx]; + port->mapbase = plat[idx].mapbase; + port->fifosize = plat[idx].fifo_size; + port->uartclk = plat[idx].uartclk; + + switch (idx) { + case 0: + port->membase = (unsigned char *)VA_UART0_REG_BASE; + break; + case 1: + port->membase = (unsigned char *)VA_UART1_REG_BASE; + break; + case 2: + port->membase = (unsigned char *)VA_UART2_REG_BASE; + break; + default: + break; + } + } +} + +static void __init fh8852v210_map_io(void) +{ + iotable_init(fh8852v210_io_desc, ARRAY_SIZE(fh8852v210_io_desc)); + fh_console_pre_init(fh_uart_platform_data, + ARRAY_SIZE(fh_uart_platform_data)); +} + + +static __init void fh8852v210_board_init(void) +{ + if (fh_is_8852v210()) + fh_rtc_device.dev.platform_data = &rtc_plat_data[1]; + platform_add_devices(fh8852v210_devices, + ARRAY_SIZE(fh8852v210_devices)); + spi_register_board_info(fh_spi_devices, ARRAY_SIZE(fh_spi_devices)); +} +void __init fh_timer_init_no_of(unsigned int iovbase, + unsigned int irqno); + +static void __init fh8852v210_init_early(void) +{ + fh_pmu_init(); + fh_pinctrl_init(VA_PMU_REG_BASE + 0x80); +} + +static void __init fh_time_init(void) +{ + unsigned int vtimerbase = (unsigned int)ioremap(TIMER_REG_BASE, SZ_4K); + + fh_clk_init(); + fh_timer_init_no_of(vtimerbase, TMR0_IRQ); + +} + +void __init fh_intc_init_no_of(unsigned int iovbase); +static void __init fh_intc_init(void) +{ + unsigned int vintcbase = (unsigned int)ioremap(INTC_REG_BASE, SZ_4K); + + fh_intc_init_no_of(vintcbase); + +} + +static void fh8852v210_restart + (enum reboot_mode mode, const char *cmd) +{ + fh_pmu_restart(); +} + + +MACHINE_START(FH8852V210, "FH8852V210") + .atag_offset = 0x100, + .map_io = fh8852v210_map_io, + .init_irq = fh_intc_init, + .init_time = fh_time_init, + .init_machine = fh8852v210_board_init, + .init_early = fh8852v210_init_early, + .restart = fh8852v210_restart, +MACHINE_END + diff --git a/arch/arm/mach-fh/fh8852v210/board_config.fh8852v210.appboard b/arch/arm/mach-fh/fh8852v210/board_config.fh8852v210.appboard new file mode 100644 index 00000000..02dae328 --- /dev/null +++ b/arch/arm/mach-fh/fh8852v210/board_config.fh8852v210.appboard @@ -0,0 +1,44 @@ +#ifndef BOARD_CONFIG_H_ +#define BOARD_CONFIG_H_ + +/* + * GPIO0 -> IRCUT_ON + * GPIO1 -> IRCUT_OFF + * GPIO2 -> USB_PWREN + * GPIO11 -> EMAC PHY Reset + * GPIO12 -> CIS_CLK + * GPIO13 -> CIS_RSTN + * GPIO14 -> CIS_PDN + * GPIO19 -> SD1_PWREN/WIFI_REG_ON + * GPIO20 -> AK7755 Reset + * GPIO24 -> LED0 + * GPIO25 -> LED1 + * GPIO26 -> Reset Configs + * GPIO27 -> AK7755 PowerDown + * GPIO28 -> IR + * GPIO53 -> USB_PWREN/SD0_PWREN + * GPIO55 -> SD1 WIFI Interrupt + */ + +#define CONFIG_SD_CD_FIXED + +#define CONFIG_ISP_CLK_RATE 171000000 +#define CONFIG_JPEG_CLK_RATE 171000000 +#define CONFIG_VEU_CLK_RATE 240000000 + +#define USB_VBUS_PWR_GPIO (47) + +#define CONFIG_PINCTRL_SELECT \ + "ETH", "I2C0", "PWM2", "PWM3", "PWM4", "PWM5", "PWM6", \ + "PWM7", "PWM8", "PWM9", "SADC_XAIN0", "SADC_XAIN1", \ + "SD0_NO_WP", "SENSOR_CLK", "SSI0_4BIT", "UART0", \ + "UART1", "GPIO4", "GPIO13", "GPIO30", "GPIO31", \ + "GPIO32", "GPIO43", "GPIO44", "GPIO47", \ +\ + "GPIO11", "GPIO14", "GPIO15", "GPIO16", "GPIO24", \ + "GPIO25", "GPIO45", "GPIO46", "GPIO48", "GPIO49", \ + "GPIO50", "GPIO51", "GPIO52", "GPIO53", "GPIO54", \ + "GPIO55", "GPIO56", "GPIO57", "GPIO58", "GPIO59", \ + "GPIO60", "GPIO61", "GPIO62", "GPIO63" + +#endif /* BOARD_CONFIG_H_ */ diff --git a/arch/arm/mach-fh/fh8852v210/chip.c b/arch/arm/mach-fh/fh8852v210/chip.c new file mode 100644 index 00000000..9bbb3c49 --- /dev/null +++ b/arch/arm/mach-fh/fh8852v210/chip.c @@ -0,0 +1,747 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * external oscillator + * fixed to 24M + */ +static struct fh_clk osc_clk = { + .name = "osc_clk", + .frequency = OSC_FREQUENCY, + .flag = CLOCK_FIXED, +}; + +/* + * phase-locked-loop device, + * generates a higher frequency clock + * from the external oscillator reference + *PLL_DDR + */ + +static struct fh_clk pll_ddr_rclk = { + .name = "pll_ddr_rclk", + .flag = CLOCK_PLL_R|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL0, + .en_reg_offset = REG_PMU_PLL0_CTRL, + .en_reg_mask = 0xf000, +}; + +/*PLL_CPU*/ +static struct fh_clk pll_cpu_pclk = { + .name = "pll_cpu_pclk", + .flag = CLOCK_PLL_P|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL1, + .en_reg_offset = REG_PMU_PLL1_CTRL, + .en_reg_mask = 0xf00, +}; + +static struct fh_clk pll_cpu_rclk = { + .name = "pll_cpu_rclk", + .flag = CLOCK_PLL_R|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL1, + .en_reg_offset = REG_PMU_PLL1_CTRL, + .en_reg_mask = 0xf000, +}; + +/*PLL_SYS*/ +static struct fh_clk pll_sys_pclk = { + .name = "pll_sys_pclk", + .flag = CLOCK_PLL_P|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL2, + .en_reg_offset = REG_PMU_PLL2_CTRL, + .en_reg_mask = 0xf00, +}; + + +static struct fh_clk pll_sys_rclk = { + .name = "pll_sys_rclk", + .flag = CLOCK_PLL_R|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL2, + .en_reg_offset = REG_PMU_PLL2_CTRL, + .en_reg_mask = 0xf000, +}; + +static struct fh_clk pllsysp_div12_clk = { + .name = "pllsysp_div12_clk", + .flag = CLOCK_NORESET|CLOCK_NOGATE, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV5, + .div_reg_mask = 0xf000000, +}; + +static struct fh_clk ddr_clk = { + .name = "ddr_clk", + .flag = CLOCK_NODIV, + .parent = {&pll_ddr_rclk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x4000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x8, +}; +static struct fh_clk arm_clk = { + .name = "arm_clk", + .flag = CLOCK_MULTI_PARENT|CLOCK_NOGATE|CLOCK_NODIV, + .parent = {&osc_clk, &pll_cpu_pclk}, + .prediv = 1, + .sel_reg_offset = REG_PMU_SYS_CTRL, + .sel_reg_mask = 0x1, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x1, +}; +static struct fh_clk arc_clk = { + .name = "arc_clk", + .flag = CLOCK_MULTI_PARENT|CLOCK_NODIV, + .parent = {&osc_clk, &pll_cpu_rclk}, + .prediv = 1, + .sel_reg_offset = REG_PMU_SYS_CTRL, + .sel_reg_mask = 0x1, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x400000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x400000, +}; +static struct fh_clk ahb_clk = { + .name = "ahb_clk", + .flag = CLOCK_MULTI_PARENT|CLOCK_NORESET|CLOCK_NOGATE, + .parent = {&osc_clk, &pll_sys_pclk}, + .prediv = 1, + .sel_reg_offset = REG_PMU_SYS_CTRL, + .sel_reg_mask = 0x1, + .div_reg_offset = REG_PMU_CLK_DIV0, + .div_reg_mask = 0xf0000, +}; + +static struct fh_clk isp_aclk = { + .name = "isp_aclk", + .flag = CLOCK_NORESET, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV0, + .div_reg_mask = 0xf00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x1, + .def_rate = CONFIG_ISP_CLK_RATE, +}; +static struct fh_clk ispb_aclk = { + .name = "ispb_aclk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&isp_aclk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x4, +}; + +static struct fh_clk vpu_clk = { + .name = "vpu_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&isp_aclk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x80000000, +}; + +static struct fh_clk pix_clk = { + .name = "pix_clk", + .flag = CLOCK_NORESET|CLOCK_NOGATE, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV2, + .div_reg_mask = 0xf000000, +}; + +static struct fh_clk jpeg_clk = { + .name = "jpeg_clk", + .flag = CLOCK_NORESET, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV7, + .div_reg_mask = 0xf00000, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x40000000, + .def_rate = CONFIG_JPEG_CLK_RATE, +}; + +static struct fh_clk bgm_clk = { + .name = "bgm_clk", + .flag = CLOCK_NORESET, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV7, + .div_reg_mask = 0xf00000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x40000, +}; + +static struct fh_clk jpeg_adapt_clk = { + .name = "jpeg_adapt_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&jpeg_clk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x2, +}; +static struct fh_clk spi0_clk = { + .name = "spi0_clk", + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xff, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x80, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x100, +}; +static struct fh_clk sdc0_clk = { + .name = "sdc0_clk", + .parent = {&pll_sys_pclk}, + .prediv = 8, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xf00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x200, + .rst_reg_offset = REG_PMU_SWRST_AHB_CTRL, + .rst_reg_mask = 0x4, +}; +static struct fh_clk spi2_clk = { + .name = "spi2_clk", + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xf000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x2, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x100000, +}; +static struct fh_clk spi1_clk = { + .name = "spi1_clk", + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xff0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x100, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x200, +}; +static struct fh_clk sdc1_clk = { + .name = "sdc1_clk", + .parent = {&pll_sys_pclk}, + .prediv = 8, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xf000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x400, + .rst_reg_offset = REG_PMU_SWRST_AHB_CTRL, + .rst_reg_mask = 0x2, +}; + +static struct fh_clk veu_clk = { + .name = "veu_clk", + .flag = CLOCK_MULTI_PARENT, + .parent = {&pll_sys_pclk, &pll_sys_rclk}, + .prediv = 1, + .sel_reg_offset = REG_PMU_SYS_CTRL, + .sel_reg_mask = 0x4, + .div_reg_offset = REG_PMU_CLK_DIV0, + .div_reg_mask = 0x7000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x10, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x2000000, + .def_rate = CONFIG_VEU_CLK_RATE, + +}; + +static struct fh_clk veu_adapt_clk = { + .name = "veu_adapt_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&veu_clk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x20000000, + +}; + +static struct fh_clk cis_clk_out = { + .name = "cis_clk_out", + .flag = CLOCK_NORESET, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV1, + .div_reg_mask = 0xff0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x800000, +}; + +static struct fh_clk eth_clk = { + .name = "eth_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV6, + .div_reg_mask = 0xf000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x12000000, + .rst_reg_offset = REG_PMU_SWRST_AHB_CTRL, + .rst_reg_mask = 0x20000, +}; +static struct fh_clk i2c0_clk = { + .name = "i2c0_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV4, + .div_reg_mask = 0x3f0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x1000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x400, +}; + +static struct fh_clk i2c1_clk = { + .name = "i2c1_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV4, + .div_reg_mask = 0x3f000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x8000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x800, +}; + +static struct fh_clk i2c2_clk = { + .name = "i2c2_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV7, + .div_reg_mask = 0x00003f00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x00000008, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x20000000, +}; + +static struct fh_clk pwm_clk = { + .name = "pwm_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV5, + .div_reg_mask = 0xff, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x10000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x80, + .def_rate = 50000000, +}; + +static struct fh_clk uart0_clk = { + .name = "uart0_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV4, + .div_reg_mask = 0x1f, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x2000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x4000, + .def_rate = 16666666, +}; + +static struct fh_clk uart1_clk = { + .name = "uart1_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV4, + .div_reg_mask = 0x1f00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x4000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x8000, + .def_rate = 16666666, +}; +static struct fh_clk uart2_clk = { + .name = "uart2_clk", + .parent = {&pllsysp_div12_clk}, + .flag = 0, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV7, + .div_reg_mask = 0x7f, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x8000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x8000000, + .def_rate = 16666666, +}; + +static struct fh_clk efuse_clk = { + .name = "efuse_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV1, + .div_reg_mask = 0x3f000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x200000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x800000, +}; + +static struct fh_clk pts_clk = { + .name = "pts_clk", + .parent = {&pllsysp_div12_clk}, + .flag = CLOCK_NORESET, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV2, + .div_reg_mask = 0x1ff, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x80000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL2, + .rst_reg_mask = 0x1, + .def_rate = 1000000, +}; + +static struct fh_clk tmr0_clk = { + .name = "tmr0_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV5, + .div_reg_mask = 0xff0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x20000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x40000, +}; + +static struct fh_clk sadc_clk = { + .name = "sadc_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV6, + .div_reg_mask = 0x7f0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x4000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x10000, +}; + +static struct fh_clk ac_clk = { + .name = "ac_clk", + .parent = {&osc_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV6, + .div_reg_mask = 0x3f, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x800, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x1000, +}; + +static struct fh_clk i2s_clk = { + .name = "i2s_clk", + .parent = {&ac_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV6, + .div_reg_mask = 0x3f00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x1000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x2000, +}; + +static struct fh_clk wdt_clk = { + .name = "wdt_clk", + .flag = 0, + .parent = {&ahb_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV5, + .div_reg_mask = 0xff00, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x8000000, + .rst_reg_offset = REG_PMU_SWRST_APB_CTRL, + .rst_reg_mask = 0x100000, + .def_rate = 1000000, +}; + +static struct fh_clk gpio0_db_clk = { + .name = "gpio0_db_clk", + .flag = 0, + .parent = {&pllsysp_div12_clk}, + .prediv = 100, + .div_reg_offset = REG_PMU_CLK_DIV8, + .div_reg_mask = 0x7fff, + .en_reg_offset = REG_PMU_CLK_DIV8, + .en_reg_mask = 0x8000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x10, +}; + +static struct fh_clk gpio1_db_clk = { + .name = "gpio1_db_clk", + .flag = 0, + .parent = {&pllsysp_div12_clk}, + .prediv = 100, + .div_reg_offset = REG_PMU_CLK_DIV8, + .div_reg_mask = 0x7fff0000, + .en_reg_offset = REG_PMU_CLK_DIV8, + .en_reg_mask = 0x80000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x20, +}; + + +static struct fh_clk mipi_dphy_clk = { + .name = "mipi_dphy_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&osc_clk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x100000, +}; +static struct fh_clk mipi_wrap_gate = { + .name = "mipi_wrap_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x20000000, +}; +static struct fh_clk rtc_hclk_gate = { + .name = "rtc_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x10000000, +}; +static struct fh_clk emac_hclk_gate = { + .name = "emac_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x2000000, +}; +static struct fh_clk usb_clk = { + .name = "usb_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x1000000, +}; +static struct fh_clk aes_hclk_gate = { + .name = "aes_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x80, +}; +static struct fh_clk ephy_clk_gate = { + .name = "ephy_clk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x1, +}; +static struct fh_clk sdc0_clk8x_gate = { + .name = "sdc0_clk8x_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x4, +}; +static struct fh_clk sdc1_clk8x_gate = { + .name = "sdc1_clk8x_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x8, +}; +static struct fh_clk mipic_pclk_gate = { + .name = "mipic_pclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x10, +}; + +static struct fh_clk gpio0_pclk_gate = { + .name = "gpio0_pclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV8, + .en_reg_mask = 0x4000, +}; +static struct fh_clk gpio1_pclk_gate = { + .name = "gpio1_pclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV8, + .en_reg_mask = 0x40000000, +}; +static struct fh_clk isp_hclk_gate = { + .name = "isp_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x1000000, +}; +static struct fh_clk veu_hclk_gate = { + .name = "veu_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x2000000, +}; +static struct fh_clk bgm_hclk_gate = { + .name = "bgm_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x4000000, +}; +static struct fh_clk adapt_hclk_gate = { + .name = "adapt_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x8000000, +}; +static struct fh_clk jpg_hclk_gate = { + .name = "jpg_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x10000000, +}; +static struct fh_clk jpg_adapt_gate = { + .name = "jpg_adapt_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x20000000, +}; +static struct fh_clk vpu_hclk_gate = { + .name = "vpu_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x40000000, +}; + +static struct fh_clk sdc0_clk_sample = { + .name = "sdc0_clk_sample", + .parent = {&sdc0_clk}, + .flag = CLOCK_NOGATE | CLOCK_PHASE, + .prediv = 1, + .sel_reg_offset = REG_PMU_CLK_GATE1, + .sel_reg_mask = 0xf0000, +}; + +static struct fh_clk sdc0_clk_drv = { + .name = "sdc0_clk_drv", + .parent = {&sdc0_clk}, + .flag = CLOCK_NOGATE | CLOCK_PHASE, + .prediv = 1, + .sel_reg_offset = REG_PMU_CLK_GATE1, + .sel_reg_mask = 0xf00000, +}; + +static struct fh_clk sdc1_clk_sample = { + .name = "sdc1_clk_sample", + .parent = {&sdc0_clk}, + .flag = CLOCK_NOGATE | CLOCK_PHASE, + .prediv = 1, + .sel_reg_offset = REG_PMU_CLK_GATE1, + .sel_reg_mask = 0xf00, +}; + +static struct fh_clk sdc1_clk_drv = { + .name = "sdc1_clk_drv", + .parent = {&sdc0_clk}, + .flag = CLOCK_NOGATE | CLOCK_PHASE, + .prediv = 1, + .sel_reg_offset = REG_PMU_CLK_GATE1, + .sel_reg_mask = 0xf000, +}; + +struct fh_clk *fh_clks[] = { + &osc_clk, + &pll_ddr_rclk, + &pll_cpu_pclk, + &pll_cpu_rclk, + &pll_sys_pclk, + &pll_sys_rclk, + &arm_clk, + &arc_clk, + &ahb_clk, + &ddr_clk, + &isp_aclk, + &ispb_aclk, + &jpeg_clk, + &jpeg_adapt_clk, + &vpu_clk, + &veu_clk, + &veu_adapt_clk, + &bgm_clk, + &mipi_dphy_clk, + &pllsysp_div12_clk, + &cis_clk_out, + &pix_clk, + &pts_clk, + &spi0_clk, + &spi1_clk, + &spi2_clk, + &sdc0_clk, + &sdc1_clk, + &uart0_clk, + &uart1_clk, + &uart2_clk, + &i2c0_clk, + &i2c1_clk, + &i2c2_clk, + &pwm_clk, + &wdt_clk, + &tmr0_clk, + &ac_clk, + &i2s_clk, + &sadc_clk, + ð_clk, + &efuse_clk, + &gpio0_db_clk, + &gpio1_db_clk, + &mipi_wrap_gate, + &rtc_hclk_gate, + &emac_hclk_gate, + &usb_clk, + &aes_hclk_gate, + &ephy_clk_gate, + &sdc0_clk8x_gate, + &sdc1_clk8x_gate, + &gpio0_pclk_gate, + &gpio1_pclk_gate, + &mipic_pclk_gate, + &sdc0_clk_sample, + &sdc0_clk_drv, + &sdc1_clk_sample, + &sdc1_clk_drv, + &isp_hclk_gate, + &veu_hclk_gate, + &bgm_hclk_gate, + &adapt_hclk_gate, + &jpg_hclk_gate, + &jpg_adapt_gate, + &vpu_hclk_gate, + NULL, +}; +EXPORT_SYMBOL(fh_clks); diff --git a/arch/arm/mach-fh/fh8852v210/chip.h b/arch/arm/mach-fh/fh8852v210/chip.h new file mode 100644 index 00000000..f2b2fcae --- /dev/null +++ b/arch/arm/mach-fh/fh8852v210/chip.h @@ -0,0 +1,420 @@ +#ifndef __ASM_ARCH_HL_H +#define __ASM_ARCH_HL_H + +#include + +#define SRAM_GRANULARITY 32 +#define SRAM_SIZE (SZ_128K+SZ_8K) + + +#define RAM_BASE (0x10000000) +#define DDR_BASE (0xA0000000) + + +#define PMU_REG_BASE (0xF0000000) +#define TIMER_REG_BASE (0xF0C00000) +#define GPIO0_REG_BASE (0xF0300000) +#define GPIO1_REG_BASE (0xF4000000) +#define UART0_REG_BASE (0xF0700000) +#define UART1_REG_BASE (0xF0800000) +#define SPI0_REG_BASE (0xF0500000) +#define SPI1_REG_BASE (0xF0600000) +#define SPI2_REG_BASE (0xF0640000) +#define INTC_REG_BASE (0xE0200000) +#define GMAC_REG_BASE (0xE0600000) +#define USBC_REG_BASE (0xE0700000) +#define DMAC_REG_BASE (0xE0300000) +#define I2C1_REG_BASE (0xF0B00000) +#define I2C0_REG_BASE (0xF0200000) +#define I2C2_REG_BASE (0xF0100000) +#define SDC0_REG_BASE (0xE2000000) +#define SDC1_REG_BASE (0xE2200000) +#define WDT_REG_BASE (0xF0D00000) +#define PWM_REG_BASE (0xF0400000) +#define I2S_REG_BASE (0xF0900000) +#define ACW_REG_BASE (0xF0A00000) +#define UART2_REG_BASE (0xF1300000) +#define SADC_REG_BASE (0xF1200000) +#define EFUSE_REG_BASE (0xF1600000) +#define AES_REG_BASE (0xE8200000) +#define RTC_REG_BASE (0xF1500000) +#define DDRC_REG_BASE (0xED000000) +#define CONSOLE_REG_BASE UART0_REG_BASE +#define FH_UART_NUMBER 3 + +#define FH_PMU_REG_SIZE 0x2110 +#define REG_PMU_CHIP_ID (0x0000) +#define REG_PMU_IP_VER (0x0004) +#define REG_PMU_FW_VER (0x0008) +#define REG_PMU_CLK_SEL (0x000c) +/*for HL REG_PMU_SYS_CTRL and CLK_SEL use one register */ +#define REG_PMU_SYS_CTRL (0x000c) +#define REG_PMU_PLL0 (0x0010) +#define REG_PMU_PLL1 (0x0014) +#define REG_PMU_PLL0_CTRL (0x0018) +#define REG_PMU_CLK_GATE (0x001c) +#define REG_PMU_CLK_GATE1 (0x0020) +#define REG_PMU_CLK_DIV0 (0x0024) +#define REG_PMU_CLK_DIV1 (0x0028) +#define REG_PMU_CLK_DIV2 (0x002c) +#define REG_PMU_CLK_DIV3 (0x0030) +#define REG_PMU_CLK_DIV4 (0x0034) +#define REG_PMU_CLK_DIV5 (0x0038) +#define REG_PMU_CLK_DIV6 (0x003c) +#define REG_PMU_SWRST_MAIN_CTRL (0x0040) +#define REG_PMU_SWRST_MAIN_CTRL2 (0x0044) +#define REG_PMU_SWRST_AHB_CTRL (0x0048) +#define REG_PMU_SWRST_APB_CTRL (0x004c) +#define REG_PMU_SPC_IO_STATUS (0x0054) +#define REG_PMU_SPC_FUN (0x0058) +#define REG_PMU_CLK_DIV7 (0x005c) +#define REG_PMU_CLK_DIV8 (0x0060) +#define REG_PMU_PLL2 (0x0064) +#define REG_PMU_PLL2_CTRL (0x0068) +#define REG_PMU_PLL1_CTRL (0x006c) +#define REG_PAD_PWR_SEL (0x0074) +#define REG_PMU_SWRSTN_NSR (0x0078) +#define REG_PMU_SWRSTN_NSR1 (0x007c) +#define REG_PMU_ETHPHY_REG0 (0x2108) + + +#define REG_PMU_PAD_BOOT_MODE_CFG (0x0080) +#define REG_PMU_PAD_BOOT_SEL1_CFG (0x0084) +#define REG_PMU_PAD_BOOT_SEL0_CFG (0x0088) +#define REG_PMU_PAD_UART0_TX_CFG (0x008c) +#define REG_PMU_PAD_UART0_RX_CFG (0x0090) +#define REG_PMU_PAD_I2C0_SCL_CFG (0x0094) +#define REG_PMU_PAD_I2C0_SDA_CFG (0x0098) +#define REG_PMU_PAD_SENSOR_CLK_CFG (0x009c) +#define REG_PMU_PAD_SENSOR_RSTN_CFG (0x00a0) +#define REG_PMU_PAD_UART1_TX_CFG (0x00a4) +#define REG_PMU_PAD_UART1_RX_CFG (0x00a8) +#define REG_PMU_PAD_I2C1_SCL_CFG (0x00ac) +#define REG_PMU_PAD_I2C1_SDA_CFG (0x00b0) +#define REG_PMU_PAD_UART2_TX_CFG (0x00b4) +#define REG_PMU_PAD_UART2_RX_CFG (0x00b8) +#define REG_PMU_PAD_USB_PWREN_CFG (0x00bc) +#define REG_PMU_PAD_PWM0_CFG (0x00c0) +#define REG_PMU_PAD_PWM1_CFG (0x00c4) +#define REG_PMU_PAD_PWM2_CFG (0x00c8) +#define REG_PMU_PAD_PWM3_CFG (0x00cc) +#define REG_PMU_PAD_MAC_RMII_CLK_CFG (0x00d0) +#define REG_PMU_PAD_MAC_REF_CLK_CFG (0x00d4) +#define REG_PMU_PAD_MAC_TXD0_CFG (0x00d8) +#define REG_PMU_PAD_MAC_TXD1_CFG (0x00dc) +#define REG_PMU_PAD_MAC_TXEN_CFG (0x00e0) +#define REG_PMU_PAD_MAC_RXD0_CFG (0x00e4) +#define REG_PMU_PAD_MAC_RXD1_CFG (0x00e8) +#define REG_PMU_PAD_MAC_RXDV_CFG (0x00ec) +#define REG_PMU_PAD_MAC_MDC_CFG (0x00f0) +#define REG_PMU_PAD_MAC_MDIO_CFG (0x00f4) +#define REG_PMU_PAD_SD1_CLK_CFG (0x00f8) +#define REG_PMU_PAD_SD1_CD_CFG (0x00fc) +#define REG_PMU_PAD_SD1_CMD_RSP_CFG (0x0100) +#define REG_PMU_PAD_SD1_DATA_0_CFG (0x0104) +#define REG_PMU_PAD_SD1_DATA_1_CFG (0x0108) +#define REG_PMU_PAD_SD1_DATA_2_CFG (0x010c) +#define REG_PMU_PAD_SD1_DATA_3_CFG (0x0110) +#define REG_PMU_PAD_GPIO_0_CFG (0x0114) +#define REG_PMU_PAD_GPIO_1_CFG (0x0118) +#define REG_PMU_PAD_GPIO_2_CFG (0x011c) +#define REG_PMU_PAD_GPIO_3_CFG (0x0120) +#define REG_PMU_PAD_GPIO_4_CFG (0x0124) +#define REG_PMU_PAD_SSI0_CLK_CFG (0x0128) +#define REG_PMU_PAD_SSI0_CSN_0_CFG (0x012c) +#define REG_PMU_PAD_SSI0_TXD_CFG (0x0130) +#define REG_PMU_PAD_SSI0_RXD_CFG (0x0134) +#define REG_PMU_PAD_SSI0_D2_CFG (0x0138) +#define REG_PMU_PAD_SSI0_D3_CFG (0x013c) +#define REG_PMU_PAD_SSI1_CLK_CFG (0x0140) +#define REG_PMU_PAD_SSI1_CSN_0_CFG (0x0144) +#define REG_PMU_PAD_SSI1_TXD_CFG (0x0148) +#define REG_PMU_PAD_SSI1_RXD_CFG (0x014c) +#define REG_PMU_PAD_SD0_CD_CFG (0x0150) +#define REG_PMU_PAD_SD0_CLK_CFG (0x0154) +#define REG_PMU_PAD_SD0_CMD_RSP_CFG (0x0158) +#define REG_PMU_PAD_SD0_DATA_0_CFG (0x015c) +#define REG_PMU_PAD_SD0_DATA_1_CFG (0x0160) +#define REG_PMU_PAD_SD0_DATA_2_CFG (0x0164) +#define REG_PMU_PAD_SD0_DATA_3_CFG (0x0168) +#define REG_PMU_PAD_SADC_XAIN0_CFG (0x016c) +#define REG_PMU_PAD_SADC_XAIN1_CFG (0x0170) +#define REG_PMU_PAD_SADC_XAIN2_CFG (0x0174) +#define REG_PMU_PAD_SADC_XAIN3_CFG (0x0178) +#define REG_PMU_PAD_GPIO_28_CFG (0x017c) +#define REG_PMU_PAD_GPIO_29_CFG (0x0180) + +#define REG_PMU_ARM_INT_0 (0x01e0) +#define REG_PMU_ARM_INT_1 (0x01e4) +#define REG_PMU_ARM_INT_2 (0x01e8) +#define REG_PMU_A625_INT_0 (0x01ec) +#define REG_PMU_A625_INT_1 (0x01f0) +#define REG_PMU_A625_INT_2 (0x01f4) +#define REG_PMU_DMA (0x01f8) +#define REG_PMU_WDT_CTRL (0x01fc) +#define REG_PMU_DBG_STAT0 (0x0200) +#define REG_PMU_DBG_STAT1 (0x0204) +#define REG_PMU_DBG_STAT2 (0x0208) +#define REG_PMU_DBG_STAT3 (0x020c) +#define REG_PMU_USB_SYS (0x0210) +#define REG_PMU_USB_CFG (0x0214) +#define REG_PMU_USB_TUNE (0x0218) +#define REG_PMU_USB_SYS1 (0x0228) +#define REG_PMU_PTSLO (0x022c) +#define REG_PMU_PTSHI (0x0230) +#define REG_PMU_USER0 (0x0234) +#define REG_PMU_BOOT_MODE (0x0330) +#define REG_PMU_DDR_SIZE (0x0334) +#define REG_PMU_CHIP_INFO (0x033C) +#define REG_PMU_EPHY_PARAM (0x0340) +#define REG_PMU_RTC_PARAM (0x0344) +#define REG_PMU_SD1_FUNC_SEL (0x03a0) +#define REG_PMU_PRDCID_CTRL0 (0x0500) +#define REG_PMU_A625BOOT0 (0x2000) +#define REG_PMU_A625BOOT1 (0x2004) +#define REG_PMU_A625BOOT2 (0x2008) +#define REG_PMU_A625BOOT3 (0x200c) +#define REG_PMU_A625_START_CTRL (0x2010) +#define REG_PMU_ARC_INTC_MASK (0x2014) + +#define FH_GMAC_AHB_RESET (1<<17) +#define FH_GMAC_SPEED_100M (1<<24) +#define PMU_RMII_SPEED_MODE (REG_PMU_CLK_SEL) +#define PMU_RXDV_GPIO_SWITCH (REG_PMU_PAD_MAC_RXDV_CFG) +#define PMU_RXDV_GPIO_MASK (0x0f000000) +#define PMU_RXDV_GPIO_VAL (0x01000000) + +#define PMU_DWI2S_CLK_SEL_REG (REG_PMU_CLK_SEL) +#define PMU_DWI2S_CLK_SEL_SHIFT (1) +#define PMU_DWI2S_CLK_DIV_REG (REG_PMU_CLK_DIV6) +#define PMU_DWI2S_CLK_DIV_SHIFT (0) + +/*ATTENTION: written by ARC */ +#define PMU_ARM_INT_MASK (0x01ec) +#define PMU_ARM_INT_RAWSTAT (0x01f0) +#define PMU_ARM_INT_STAT (0x01f4) + +#define PMU_A625_INT_MASK (0x01e0) +#define PMU_A625_INT_RAWSTAT (0x01e4) +#define PMU_A625_INT_STAT (0x01e8) + +#define PMU_IRQ 0 +#define DDRC_IRQ 1 +#define WDT_IRQ 2 +#define TMR0_IRQ 3 +#define VEU_IRQ 4 +#define PERF_IRQ 5 +#define VPU_IRQ 9 +#define I2C0_IRQ 11 +#define I2C1_IRQ 12 +#define JPEG_IRQ 13 +#define BGM_IRQ 14 +#define VEU_LOOP_IRQ 15 +#define AES_IRQ 16 +#define MIPIC_IRQ 17 +#define MIPI_WRAP_IRQ 18 +#define ACW_IRQ 19 +#define SADC_IRQ 20 +#define SPI1_IRQ 21 +#define JPEG_LOOP_IRQ 22 +#define DMAC0_IRQ 23 +#define DMAC1_IRQ 24 +#define I2S0_IRQ 25 +#define GPIO0_IRQ 26 +#define SPI0_IRQ 28 +#define ARC_SW_IRQ 29 +#define UART0_IRQ 30 +#define UART1_IRQ 31 +#define ARM_SW_IRQ 32 +#define RTC_IRQ 33 +#define PWM_IRQ 36 +#define SPI2_IRQ 38 +#define USBC_IRQ 39 +#define GPIO1_IRQ 40 +#define UART2_IRQ 41 +#define SDC0_IRQ 42 +#define SDC1_IRQ 43 +#define GMAC_IRQ 44 +#define EPHY_IRQ 45 +#define I2C2_IRQ 46 +#define RTC_ALM_IRQ 47 +#define RTC_CORE_IRQ 48 +/* because chips with some same function in different */ +/* pmu register, use wrap marco to make code to be same */ +#define PMU_RMII_SPEED_MODE (REG_PMU_CLK_SEL) + +#define MEM_START_PHY_ADDR DDR_BASE +#define MEM_SIZE 0x4000000 + + +#define NR_INTERNAL_IRQS (64) +#define NR_EXTERNAL_IRQS (64) +/*#define NR_IRQS (NR_INTERNAL_IRQS + NR_EXTERNAL_IRQS)*/ + +/* SWRST_MAIN_CTRL */ +#define CPU_RSTN_BIT (0) +#define UTMI_RSTN_BIT (1) +#define DDRPHY_RSTN_BIT (2) +#define DDRC_RSTN_BIT (3) +#define GPIO0_DB_RSTN_BIT (4) +#define GPIO1_DB_RSTN_BIT (5) +#define PIXEL_RSTN_BIT (6) +#define PWM_RSTN_BIT (7) +#define SPI0_RSTN_BIT (8) +#define SPI1_RSTN_BIT (9) +#define I2C0_RSTN_BIT (10) +#define I2C1_RSTN_BIT (11) +#define ACODEC_RSTN_BIT (12) +#define I2S_RSTN_BIT (13) +#define UART0_RSTN_BIT (14) +#define UART1_RSTN_BIT (15) +#define SADC_RSTN_BIT (16) +#define ADAPT_RSTN_BIT (17) +#define TMR_RSTN_BIT (18) +#define UART2_RSTN_BIT (19) +#define SPI2_RSTN_BIT (20) +#define JPG_ADAPT_RSTN_BIT (21) +#define ARC_RSTN_BIT (22) +#define EFUSE_RSTN_BIT (23) +#define JPG_RSTN_BIT (24) +#define VEU_RSTN_BIT (25) +#define VPU_RSTN_BIT (26) +#define ISP_RSTN_BIT (27) +#define BGM_RSTN_BIT (28) +#define I2C2_RSTN_BIT (29) +#define EPHY_RSTN_BIT (30) +#define SYS_RSTN_BIT (31) + +/* SWRST_AHB_CTRL */ +#define EMC_HRSTN_BIT (0) +#define SDC1_HRSTN_BIT (1) +#define SDC0_HRSTN_BIT (2) +#define AES_HRSTN_BIT (3) +#define DMAC0_HRSTN_BIT (4) +#define INTC_HRSTN_BIT (5) +#define JPEG_ADAPT_HRSTN_BIT (7) +#define JPEG_HRSTN_BIT (8) +#define VCU_HRSTN_BIT (9) +#define VPU_HRSTN_BIT (10) +#define ISP_HRSTN_BIT (11) +#define USB_HRSTN_BIT (12) +#define HRSTN_BIT (13) +#define EMAC_HRSTN_BIT (17) +#define DDRC_HRSTN_BIT (19) +#define DMAC1_HRSTN_BIT (20) +#define BGM_HRSTN_BIT (22) +#define ADAPT_HRSTN_BIT (23) + +/* SWRST_APB_CTRL */ +#define ACODEC_PRSTN_BIT (0) +#define I2S_PRSTN_BIT (1) +#define UART1_PRSTN_BIT (2) +#define UART0_PRSTN_BIT (3) +#define SPI0_PRSTN_BIT (4) +#define SPI1_PRSTN_BIT (5) +#define GPIO0_PRSTN_BIT (6) +#define UART2_PRSTN_BIT (7) +#define I2C2_PRSTN_BIT (8) +#define I2C0_PRSTN_BIT (9) +#define I2C1_PRSTN_BIT (10) +#define TMR_PRSTN_BIT (11) +#define PWM_PRSTN_BIT (12) +#define MIPIW_PRSTN_BIT (13) +#define MIPIC_PRSTN_BIT (14) +#define RTC_PRSTN_BIT (15) +#define SADC_PRSTN_BIT (16) +#define EFUSE_PRSTN_BIT (17) +#define SPI2_PRSTN_BIT (18) +#define WDT_PRSTN_BIT (19) +#define GPIO1_PRSTN_BIT (20) + +/* timer clk fpga 1M,soc 50M*/ +#ifdef CONFIG_FPGA +#define TIMER_CLK (1000000) +#else +#define TIMER_CLK (50000000) +#endif + +#define UART1_TX_HW_HANDSHAKE (9) +#define UART1_RX_HW_HANDSHAKE (8) +#define UART2_TX_HW_HANDSHAKE (13) +#define UART2_RX_HW_HANDSHAKE (12) +#define UART1_DMA_TX_CHAN (4) +#define UART1_DMA_RX_CHAN (5) +#define UART2_DMA_TX_CHAN (4) +#define UART2_DMA_RX_CHAN (5) + +/*sdio*/ +#define SIMPLE_0 (0) +#define SIMPLE_22 (1) +#define SIMPLE_45 (2) +#define SIMPLE_67 (3) +#define SIMPLE_90 (4) +#define SIMPLE_112 (5) +#define SIMPLE_135 (6) +#define SIMPLE_157 (7) +#define SIMPLE_180 (8) +#define SIMPLE_202 (9) +#define SIMPLE_225 (10) +#define SIMPLE_247 (11) +#define SIMPLE_270 (12) +#define SIMPLE_292 (13) +#define SIMPLE_315 (14) +#define SIMPLE_337 (15) + + + +#define SDIO0_RST_BIT (~UL(1<<2)) +#define SDIO0_CLK_RATE (50000000) +#define SDIO0_CLK_DRV_SHIFT (20) +#define SDIO0_CLK_DRV_DEGREE (SIMPLE_180) +#define SDIO0_CLK_SAM_SHIFT (16) +#define SDIO0_CLK_SAM_DEGREE (SIMPLE_0) + + +#define SDIO1_RST_BIT (~UL(1<<1)) +#define SDIO1_CLK_RATE (50000000) +#define SDIO1_CLK_DRV_SHIFT (12) +#define SDIO1_CLK_DRV_DEGREE (SIMPLE_180) +#define SDIO1_CLK_SAM_SHIFT (8) +#define SDIO1_CLK_SAM_DEGREE (SIMPLE_0) + +#define SDC0_HRSTN (0x1<<2) +#define SDC1_HRSTN (0x1<<1) +#define SDC2_HRSTN (0) + + +/*usb*/ +#define IRQ_UHOST USBC_IRQ +#define FH_PA_OTG USBC_REG_BASE +#define IRQ_OTG IRQ_UHOST +#define FH_SZ_USBHOST SZ_1M +#define FH_SZ_OTG SZ_1M + +#define USB_UTMI_RST_BIT (0x1<<1) +#define USB_PHY_RST_BIT (0x11) +#define USB_SLEEP_MODE_BIT (0x1<<24) +#define USB_IDDQ_PWR_BIT (0x1<<10) + + +/* Specific Uart Number */ +#define FH_UART_NUMBER 3 +#define CLK_SCAN_BIT_POS (28) +#define INSIDE_PHY_ENABLE_BIT_POS (24) +#define MAC_REF_CLK_DIV_MASK (0x0f) +#define MAC_REF_CLK_DIV_BIT_POS (24) +#define MAC_PAD_RMII_CLK_MASK (0x0f) +#define MAC_PAD_RMII_CLK_BIT_POS (24) +#define MAC_PAD_MAC_REF_CLK_BIT_POS (28) +#define ETH_REF_CLK_OUT_GATE_BIT_POS (25) +#define ETH_RMII_CLK_OUT_GATE_BIT_POS (28) +#define IN_OR_OUT_PHY_SEL_BIT_POS (26) +#define INSIDE_CLK_GATE_BIT_POS (0) +#define INSIDE_PHY_SHUTDOWN_BIT_POS (31) +#define INSIDE_PHY_RST_BIT_POS (30) +#define INSIDE_PHY_TRAINING_BIT_POS (27) +#define INSIDE_PHY_TRAINING_MASK (0x0f) + +#define TRAINING_EFUSE_ACTIVE_BIT_POS 4 + +#endif /* __ASM_ARCH_HL_H */ diff --git a/arch/arm/mach-fh/fh8852v210/iopad.h b/arch/arm/mach-fh/fh8852v210/iopad.h new file mode 100644 index 00000000..ebc24024 --- /dev/null +++ b/arch/arm/mach-fh/fh8852v210/iopad.h @@ -0,0 +1,729 @@ +#include +#include +#include + +/* PINCTRL_FUNC */ +PINCTRL_FUNC(GPIO30, 0, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(GPIO31, 1, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(ETH_LINK_ACT, 1, FUNC1, PUPD_UP, 0); +PINCTRL_FUNC(GPIO32, 2, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(ETH_LINK_STA, 2, FUNC1, PUPD_UP, 0); +PINCTRL_FUNC(ETH_LINK_SPD, 2, FUNC2, PUPD_UP, 0); +PINCTRL_FUNC(UART0_TX, 3, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO33, 3, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART0_RX, 4, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO34, 4, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C0_SCL, 5, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(GPIO35, 5, FUNC1, PUPD_UP, 0); +PINCTRL_FUNC(I2C0_SDA, 6, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(GPIO36, 6, FUNC1, PUPD_UP, 0); +PINCTRL_FUNC(SENSOR_CLK, 7, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO12, 7, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO13, 8, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(UART1_TX, 9, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO39, 9, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CLK, 9, FUNC3, PUPD_NONE, 3); +PINCTRL_FUNC(TEST_O_INT_RMII_CLK, 9, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(UART1_RX, 10, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO40, 10, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 10, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_INT_RMII_TXD_0, 10, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(I2C1_SCL, 11, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO37, 11, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM2, 11, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CMD_RSP, 11, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CLK, 11, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_INT_RMII_TXD_1, 11, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(I2C1_SDA, 12, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO38, 12, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM3, 12, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_0, 12, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CSN_0, 12, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_INT_RMII_TXEN, 12, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_TX, 13, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO41, 13, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM4, 13, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_1, 13, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_TXD, 13, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_O_INT_RMII_RXD_0, 13, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_RX, 14, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO42, 14, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM5, 14, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_2, 14, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_RXD, 14, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_O_INT_RMII_RXD_1, 14, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(USB_PWREN, 15, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO47, 15, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_3, 15, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_O_INT_RMII_CRSDV, 15, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM0, 16, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO43, 16, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C2_SCL, 16, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_TX, 16, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_RMII_TXD_0, 16, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM1, 17, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO44, 17, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C2_SDA, 17, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_RX, 17, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_RMII_TXD_1, 17, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM2, 18, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO45, 18, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM3, 19, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO46, 19, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_RMII_CLK, 20, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO48, 20, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CLK, 20, FUNC2, PUPD_NONE, 3); +PINCTRL_FUNC(PWM2, 20, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_REF_CLK, 21, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(MAC_TXD_0, 22, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO49, 22, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 22, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM3, 22, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_TXD_1, 23, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO50, 23, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CMD_RSP, 23, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM4, 23, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_TXEN, 24, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO51, 24, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_0, 24, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM5, 24, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_RXD_0, 25, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO52, 25, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_1, 25, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM6, 25, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_RXD_1, 26, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO53, 26, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_2, 26, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM7, 26, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_RXDV, 27, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO54, 27, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_3, 27, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM8, 27, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_MDC, 28, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO55, 28, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM9, 28, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_MDIO, 29, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO56, 29, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CLK, 30, FUNC0, PUPD_NONE, 3); +PINCTRL_FUNC(GPIO57, 30, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C1_SCL, 30, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 31, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO58, 31, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C1_SDA, 31, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CMD_RSP, 32, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO59, 32, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART1_TX, 32, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_0, 33, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO60, 33, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART1_RX, 33, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_1, 34, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO61, 34, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_TX, 34, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_2, 35, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO62, 35, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_RX, 35, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_3, 36, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO63, 36, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TRSTN, 37, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO0, 37, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_I2S_DO, 37, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(DW_I2S_DO, 37, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SSI1_CLK, 37, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI2_CLK, 37, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_ADDAT, 37, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM6, 37, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_SMI_MDC, 37, FUNC8, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TDO, 38, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO1, 38, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_I2S_DI, 38, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(DW_I2S_DI, 38, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SSI1_CSN_0, 38, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI2_CSN_0, 38, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_DADAT, 38, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM7, 38, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_SMI_MDIO_I, 38, FUNC8, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TDI, 39, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO2, 39, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_I2S_CLK, 39, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(DW_I2S_CLK, 39, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SSI1_TXD, 39, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI2_TXD, 39, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_ADBCLK, 39, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM8, 39, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_SMI_MDIO_O, 39, FUNC8, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TCK, 40, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO3, 40, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_I2S_WS, 40, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(DW_I2S_WS, 40, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SSI1_RXD, 40, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI2_RXD, 40, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_ADLRC, 40, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM9, 40, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_I_INT_SMI_MDIO_I, 40, FUNC8, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TMS, 41, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO4, 41, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_MCLK, 41, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(USB_PWREN, 41, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 41, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_I_INT_SMI_MDC, 41, FUNC5, PUPD_NONE, 0); +PINCTRL_FUNC(SSI0_CLK, 42, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO5, 42, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_CLK, 42, FUNC4, PUPD_NONE, 3); +PINCTRL_FUNC(SSI0_CSN_0, 43, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO6, 43, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_CMD_RSP, 43, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI0_TXD, 44, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO7, 44, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_DATA_0, 44, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI0_RXD, 45, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO8, 45, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_DATA_1, 45, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI0_D2, 46, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO9, 46, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(UART1_TX, 46, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(I2C1_SCL, 46, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_DATA_2, 46, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI0_D3, 47, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO10, 47, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(UART1_RX, 47, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(I2C1_SDA, 47, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_DATA_3, 47, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CLK, 48, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO11, 48, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SSI2_CLK, 48, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CSN_0, 49, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO14, 49, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SSI2_CSN_0, 49, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_TXD, 50, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO15, 50, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SSI2_TXD, 50, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_RXD, 51, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO16, 51, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SSI2_RXD, 51, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_CD, 52, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO17, 52, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(ARC_JTAG_TRSTN, 52, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(PAE_JTAG_TRSTN, 52, FUNC4, PUPD_NONE, 0); +PINCTRL_FUNC(SD0_CLK, 53, FUNC0, PUPD_NONE, 3); +PINCTRL_FUNC(GPIO18, 53, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CLK, 53, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(ARC_JTAG_TDO, 53, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(PAE_JTAG_TDO, 53, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_CMD_RSP, 54, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO19, 54, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_TXD, 54, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(ARC_JTAG_TDI, 54, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(PAE_JTAG_TDI, 54, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_DATA_0, 55, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO20, 55, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_RXD, 55, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(ARC_JTAG_TCK, 55, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(PAE_JTAG_TCK, 55, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_DATA_1, 56, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO21, 56, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CSN_0, 56, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(ARC_JTAG_TMS, 56, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(PAE_JTAG_TMS, 56, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_DATA_2, 57, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO22, 57, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(UART2_TX, 57, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(I2C2_SCL, 57, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_DABCLK, 57, FUNC6, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_DATA_3, 58, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO23, 58, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CSN_0, 58, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(UART2_RX, 58, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(I2C2_SDA, 58, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_DALRC, 58, FUNC6, PUPD_NONE, 2); +PINCTRL_FUNC(SADC_XAIN0, 59, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO26, 59, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SADC_XAIN1, 60, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO27, 60, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SADC_XAIN2, 61, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO24, 61, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SADC_XAIN3, 62, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO25, 62, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO28, 63, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(ETH_LINK_ACT, 63, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(PWM10, 63, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(USB_DBG_CLK, 63, FUNC4, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 63, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_O_INT_RMII_TXEN, 63, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_MDC, 63, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO29, 64, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(ETH_LINK_STA, 64, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(PWM11, 64, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(RTC_CLK, 64, FUNC4, PUPD_NONE, 0); +PINCTRL_FUNC(ETH_LINK_SPD, 64, FUNC5, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_SMI_MDIO_OE, 64, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_MDIO, 64, FUNC7, PUPD_NONE, 0); + + +/* PINCTRL_MUX */ + +PINCTRL_MUX(AC_I2S_CLK, 0, &PAD39_AC_I2S_CLK); +PINCTRL_MUX(AC_I2S_DI, 0, &PAD38_AC_I2S_DI); +PINCTRL_MUX(AC_I2S_DO, 0, &PAD37_AC_I2S_DO); +PINCTRL_MUX(AC_I2S_WS, 0, &PAD40_AC_I2S_WS); +PINCTRL_MUX(AC_MCLK, 0, &PAD41_AC_MCLK); + +PINCTRL_MUX(ARC_JTAG_TCK, 0, &PAD55_ARC_JTAG_TCK); +PINCTRL_MUX(ARC_JTAG_TDI, 0, &PAD54_ARC_JTAG_TDI); +PINCTRL_MUX(ARC_JTAG_TDO, 0, &PAD53_ARC_JTAG_TDO); +PINCTRL_MUX(ARC_JTAG_TMS, 0, &PAD56_ARC_JTAG_TMS); +PINCTRL_MUX(ARC_JTAG_TRSTN, 0, &PAD52_ARC_JTAG_TRSTN); + +PINCTRL_MUX(ARM_JTAG_TCK, 0, &PAD40_ARM_JTAG_TCK); +PINCTRL_MUX(ARM_JTAG_TDI, 0, &PAD39_ARM_JTAG_TDI); +PINCTRL_MUX(ARM_JTAG_TDO, 0, &PAD38_ARM_JTAG_TDO); +PINCTRL_MUX(ARM_JTAG_TMS, 0, &PAD41_ARM_JTAG_TMS); +PINCTRL_MUX(ARM_JTAG_TRSTN, 0, &PAD37_ARM_JTAG_TRSTN); + +PINCTRL_MUX(DW_I2S_CLK, 0, &PAD39_DW_I2S_CLK); +PINCTRL_MUX(DW_I2S_DI, 0, &PAD38_DW_I2S_DI); +PINCTRL_MUX(DW_I2S_DO, 0, &PAD37_DW_I2S_DO); +PINCTRL_MUX(DW_I2S_WS, 0, &PAD40_DW_I2S_WS); + +PINCTRL_MUX(ETH_LINK_ACT, 1, &PAD1_ETH_LINK_ACT, + &PAD63_ETH_LINK_ACT); +PINCTRL_MUX(ETH_LINK_SPD, 1, &PAD2_ETH_LINK_SPD, + &PAD64_ETH_LINK_SPD); +PINCTRL_MUX(ETH_LINK_STA, 1, &PAD2_ETH_LINK_STA, + &PAD64_ETH_LINK_STA); + +PINCTRL_MUX(I2C0_SCL, 0, &PAD5_I2C0_SCL); +PINCTRL_MUX(I2C0_SDA, 0, &PAD6_I2C0_SDA); + +PINCTRL_MUX(I2C1_SCL, 2, &PAD11_I2C1_SCL, &PAD30_I2C1_SCL, &PAD46_I2C1_SCL); +PINCTRL_MUX(I2C1_SDA, 2, &PAD12_I2C1_SDA, &PAD31_I2C1_SDA, &PAD47_I2C1_SDA); + +PINCTRL_MUX(I2C2_SCL, 1, &PAD16_I2C2_SCL, &PAD57_I2C2_SCL); +PINCTRL_MUX(I2C2_SDA, 1, &PAD17_I2C2_SDA, &PAD58_I2C2_SDA); + +PINCTRL_MUX(MAC_MDC, 0, &PAD28_MAC_MDC, &PAD63_MAC_MDC); +PINCTRL_MUX(MAC_MDIO, 0, &PAD29_MAC_MDIO, &PAD64_MAC_MDIO); +PINCTRL_MUX(MAC_REF_CLK, 0, &PAD21_MAC_REF_CLK); +PINCTRL_MUX(MAC_RMII_CLK, 0, &PAD20_MAC_RMII_CLK); +PINCTRL_MUX(MAC_RXDV, 0, &PAD27_MAC_RXDV); +PINCTRL_MUX(MAC_RXD_0, 0, &PAD25_MAC_RXD_0); +PINCTRL_MUX(MAC_RXD_1, 0, &PAD26_MAC_RXD_1); +PINCTRL_MUX(MAC_TXD_0, 0, &PAD22_MAC_TXD_0); +PINCTRL_MUX(MAC_TXD_1, 0, &PAD23_MAC_TXD_1); +PINCTRL_MUX(MAC_TXEN, 0, &PAD24_MAC_TXEN); + +PINCTRL_MUX(PAE_JTAG_TCK, 0, &PAD55_PAE_JTAG_TCK); +PINCTRL_MUX(PAE_JTAG_TDI, 0, &PAD54_PAE_JTAG_TDI); +PINCTRL_MUX(PAE_JTAG_TDO, 0, &PAD53_PAE_JTAG_TDO); +PINCTRL_MUX(PAE_JTAG_TMS, 0, &PAD56_PAE_JTAG_TMS); +PINCTRL_MUX(PAE_JTAG_TRSTN, 0, &PAD52_PAE_JTAG_TRSTN); + +PINCTRL_MUX(PWM0, 0, &PAD16_PWM0); +PINCTRL_MUX(PWM1, 0, &PAD17_PWM1); +PINCTRL_MUX(PWM10, 0, &PAD63_PWM10); +PINCTRL_MUX(PWM11, 0, &PAD64_PWM11); +PINCTRL_MUX(PWM2, 0, &PAD11_PWM2, &PAD18_PWM2, &PAD20_PWM2); +PINCTRL_MUX(PWM3, 0, &PAD12_PWM3, &PAD19_PWM3, &PAD22_PWM3); +PINCTRL_MUX(PWM4, 0, &PAD13_PWM4, &PAD23_PWM4); +PINCTRL_MUX(PWM5, 0, &PAD14_PWM5, &PAD24_PWM5); +PINCTRL_MUX(PWM6, 1, &PAD25_PWM6, &PAD37_PWM6); +PINCTRL_MUX(PWM7, 1, &PAD26_PWM7, &PAD38_PWM7); +PINCTRL_MUX(PWM8, 1, &PAD27_PWM8, &PAD39_PWM8); +PINCTRL_MUX(PWM9, 1, &PAD28_PWM9, &PAD40_PWM9); + +PINCTRL_MUX(RTC_CLK, 0, &PAD64_RTC_CLK); + +PINCTRL_MUX(SADC_XAIN0, 0, &PAD59_SADC_XAIN0); +PINCTRL_MUX(SADC_XAIN1, 0, &PAD60_SADC_XAIN1); +PINCTRL_MUX(SADC_XAIN2, 0, &PAD61_SADC_XAIN2); +PINCTRL_MUX(SADC_XAIN3, 0, &PAD62_SADC_XAIN3); + +PINCTRL_MUX(SD0_CD, 0, &PAD52_SD0_CD); +PINCTRL_MUX(SD0_CLK, 0, &PAD53_SD0_CLK); +PINCTRL_MUX(SD0_CMD_RSP, 0, &PAD54_SD0_CMD_RSP); +PINCTRL_MUX(SD0_DATA_0, 0, &PAD55_SD0_DATA_0); +PINCTRL_MUX(SD0_DATA_1, 0, &PAD56_SD0_DATA_1); +PINCTRL_MUX(SD0_DATA_2, 0, &PAD57_SD0_DATA_2); +PINCTRL_MUX(SD0_DATA_3, 0, &PAD58_SD0_DATA_3); + +PINCTRL_MUX(SD1_CD, 0, &PAD10_SD1_CD, &PAD22_SD1_CD, &PAD31_SD1_CD, + &PAD41_SD1_CD, &PAD63_SD1_CD); +PINCTRL_MUX(SD1_CLK, 0, &PAD9_SD1_CLK, &PAD20_SD1_CLK, &PAD30_SD1_CLK, + &PAD42_SD1_CLK); +PINCTRL_MUX(SD1_CMD_RSP, 0, &PAD11_SD1_CMD_RSP, &PAD23_SD1_CMD_RSP, + &PAD32_SD1_CMD_RSP, &PAD43_SD1_CMD_RSP); +PINCTRL_MUX(SD1_DATA_0, 0, &PAD12_SD1_DATA_0, &PAD24_SD1_DATA_0, + &PAD33_SD1_DATA_0, &PAD44_SD1_DATA_0); +PINCTRL_MUX(SD1_DATA_1, 0, &PAD13_SD1_DATA_1, &PAD25_SD1_DATA_1, + &PAD34_SD1_DATA_1, &PAD45_SD1_DATA_1); +PINCTRL_MUX(SD1_DATA_2, 0, &PAD14_SD1_DATA_2, &PAD26_SD1_DATA_2, + &PAD35_SD1_DATA_2, &PAD46_SD1_DATA_2); +PINCTRL_MUX(SD1_DATA_3, 0, &PAD15_SD1_DATA_3, &PAD27_SD1_DATA_3, + &PAD36_SD1_DATA_3, &PAD47_SD1_DATA_3); + +PINCTRL_MUX(SENSOR_CLK, 0, &PAD7_SENSOR_CLK); + +PINCTRL_MUX(SSI0_CLK, 0, &PAD42_SSI0_CLK); +PINCTRL_MUX(SSI0_D2, 0, &PAD46_SSI0_D2); +PINCTRL_MUX(SSI0_D3, 0, &PAD47_SSI0_D3); +PINCTRL_MUX(SSI0_RXD, 0, &PAD45_SSI0_RXD); +PINCTRL_MUX(SSI0_TXD, 0, &PAD44_SSI0_TXD); + +PINCTRL_MUX(SSI1_CLK, 2, &PAD11_SSI1_CLK, &PAD37_SSI1_CLK, &PAD48_SSI1_CLK, + &PAD53_SSI1_CLK); +PINCTRL_MUX(SSI1_RXD, 2, &PAD14_SSI1_RXD, &PAD40_SSI1_RXD, &PAD51_SSI1_RXD, + &PAD55_SSI1_RXD); +PINCTRL_MUX(SSI1_TXD, 2, &PAD13_SSI1_TXD, &PAD39_SSI1_TXD, &PAD50_SSI1_TXD, + &PAD54_SSI1_TXD); + +PINCTRL_MUX(SSI2_CLK, 1, &PAD37_SSI2_CLK, &PAD48_SSI2_CLK); +PINCTRL_MUX(SSI2_CSN_0, 1, &PAD38_SSI2_CSN_0, &PAD49_SSI2_CSN_0); +PINCTRL_MUX(SSI2_RXD, 1, &PAD40_SSI2_RXD, &PAD51_SSI2_RXD); +PINCTRL_MUX(SSI2_TXD, 1, &PAD39_SSI2_TXD, &PAD50_SSI2_TXD); + +PINCTRL_MUX(UART0_RX, 0, &PAD4_UART0_RX); +PINCTRL_MUX(UART0_TX, 0, &PAD3_UART0_TX); + +PINCTRL_MUX(UART1_RX, 0, &PAD10_UART1_RX, &PAD33_UART1_RX, &PAD47_UART1_RX); +PINCTRL_MUX(UART1_TX, 0, &PAD9_UART1_TX, &PAD32_UART1_TX, &PAD46_UART1_TX); + +PINCTRL_MUX(UART2_RX, 0, &PAD14_UART2_RX, &PAD17_UART2_RX, &PAD35_UART2_RX, + &PAD58_UART2_RX); +PINCTRL_MUX(UART2_TX, 0, &PAD13_UART2_TX, &PAD16_UART2_TX, &PAD34_UART2_TX, + &PAD57_UART2_TX); + +PINCTRL_MUX(USB_PWREN, 0, &PAD15_USB_PWREN, &PAD41_USB_PWREN); + +PINCTRL_MUX(GPIO0, 0, &PAD37_GPIO0); +PINCTRL_MUX(GPIO1, 0, &PAD38_GPIO1); +PINCTRL_MUX(GPIO2, 0, &PAD39_GPIO2); +PINCTRL_MUX(GPIO3, 0, &PAD40_GPIO3); +PINCTRL_MUX(GPIO4, 0, &PAD41_GPIO4); +PINCTRL_MUX(GPIO5, 0, &PAD42_GPIO5); +PINCTRL_MUX(GPIO6, 0, &PAD43_GPIO6); +PINCTRL_MUX(GPIO7, 0, &PAD44_GPIO7); +PINCTRL_MUX(GPIO8, 0, &PAD45_GPIO8); +PINCTRL_MUX(GPIO9, 0, &PAD46_GPIO9); +PINCTRL_MUX(GPIO10, 0, &PAD47_GPIO10); +PINCTRL_MUX(GPIO11, 0, &PAD48_GPIO11); +PINCTRL_MUX(GPIO12, 0, &PAD7_GPIO12); +PINCTRL_MUX(GPIO13, 0, &PAD8_GPIO13); +PINCTRL_MUX(GPIO14, 0, &PAD49_GPIO14); +PINCTRL_MUX(GPIO15, 0, &PAD50_GPIO15); +PINCTRL_MUX(GPIO16, 0, &PAD51_GPIO16); +PINCTRL_MUX(GPIO17, 0, &PAD52_GPIO17); +PINCTRL_MUX(GPIO18, 0, &PAD53_GPIO18); +PINCTRL_MUX(GPIO19, 0, &PAD54_GPIO19); +PINCTRL_MUX(GPIO20, 0, &PAD55_GPIO20); +PINCTRL_MUX(GPIO21, 0, &PAD56_GPIO21); +PINCTRL_MUX(GPIO22, 0, &PAD57_GPIO22); +PINCTRL_MUX(GPIO23, 0, &PAD58_GPIO23); +PINCTRL_MUX(GPIO24, 0, &PAD61_GPIO24); +PINCTRL_MUX(GPIO25, 0, &PAD62_GPIO25); +PINCTRL_MUX(GPIO26, 0, &PAD59_GPIO26); +PINCTRL_MUX(GPIO27, 0, &PAD60_GPIO27); +PINCTRL_MUX(GPIO28, 0, &PAD63_GPIO28); +PINCTRL_MUX(GPIO29, 0, &PAD64_GPIO29); +PINCTRL_MUX(GPIO30, 0, &PAD0_GPIO30); +PINCTRL_MUX(GPIO31, 0, &PAD1_GPIO31); +PINCTRL_MUX(GPIO32, 0, &PAD2_GPIO32); +PINCTRL_MUX(GPIO33, 0, &PAD3_GPIO33); +PINCTRL_MUX(GPIO34, 0, &PAD4_GPIO34); +PINCTRL_MUX(GPIO35, 0, &PAD5_GPIO35); +PINCTRL_MUX(GPIO36, 0, &PAD6_GPIO36); +PINCTRL_MUX(GPIO37, 0, &PAD11_GPIO37); +PINCTRL_MUX(GPIO38, 0, &PAD12_GPIO38); +PINCTRL_MUX(GPIO39, 0, &PAD9_GPIO39); +PINCTRL_MUX(GPIO40, 0, &PAD10_GPIO40); +PINCTRL_MUX(GPIO41, 0, &PAD13_GPIO41); +PINCTRL_MUX(GPIO42, 0, &PAD14_GPIO42); +PINCTRL_MUX(GPIO43, 0, &PAD16_GPIO43); +PINCTRL_MUX(GPIO44, 0, &PAD17_GPIO44); +PINCTRL_MUX(GPIO45, 0, &PAD18_GPIO45); +PINCTRL_MUX(GPIO46, 0, &PAD19_GPIO46); +PINCTRL_MUX(GPIO47, 0, &PAD15_GPIO47); +PINCTRL_MUX(GPIO48, 0, &PAD20_GPIO48); +PINCTRL_MUX(GPIO49, 0, &PAD22_GPIO49); +PINCTRL_MUX(GPIO50, 0, &PAD23_GPIO50); +PINCTRL_MUX(GPIO51, 0, &PAD24_GPIO51); +PINCTRL_MUX(GPIO52, 0, &PAD25_GPIO52); +PINCTRL_MUX(GPIO53, 0, &PAD26_GPIO53); +PINCTRL_MUX(GPIO54, 0, &PAD27_GPIO54); +PINCTRL_MUX(GPIO55, 0, &PAD28_GPIO55); +PINCTRL_MUX(GPIO56, 0, &PAD29_GPIO56); +PINCTRL_MUX(GPIO57, 0, &PAD30_GPIO57); +PINCTRL_MUX(GPIO58, 0, &PAD31_GPIO58); +PINCTRL_MUX(GPIO59, 0, &PAD32_GPIO59); +PINCTRL_MUX(GPIO60, 0, &PAD33_GPIO60); +PINCTRL_MUX(GPIO61, 0, &PAD34_GPIO61); +PINCTRL_MUX(GPIO62, 0, &PAD35_GPIO62); +PINCTRL_MUX(GPIO63, 0, &PAD36_GPIO63); + +PINCTRL_MUX(SD1_CLK_EMMC, 3, &PAD9_SD1_CLK, &PAD20_SD1_CLK, &PAD30_SD1_CLK, + &PAD42_SD1_CLK); +PINCTRL_MUX(SD1_CMD_RSP_EMMC, 3, &PAD11_SD1_CMD_RSP, &PAD23_SD1_CMD_RSP, + &PAD32_SD1_CMD_RSP, &PAD43_SD1_CMD_RSP); +PINCTRL_MUX(SD1_DATA_0_EMMC, 3, &PAD12_SD1_DATA_0, &PAD24_SD1_DATA_0, + &PAD33_SD1_DATA_0, &PAD44_SD1_DATA_0); +PINCTRL_MUX(SD1_DATA_1_EMMC, 3, &PAD13_SD1_DATA_1, &PAD25_SD1_DATA_1, + &PAD34_SD1_DATA_1, &PAD45_SD1_DATA_1); +PINCTRL_MUX(SD1_DATA_2_EMMC, 3, &PAD14_SD1_DATA_2, &PAD26_SD1_DATA_2, + &PAD35_SD1_DATA_2, &PAD46_SD1_DATA_2); +PINCTRL_MUX(SD1_DATA_3_EMMC, 3, &PAD15_SD1_DATA_3, &PAD27_SD1_DATA_3, + &PAD36_SD1_DATA_3, &PAD47_SD1_DATA_3); + +/* PINCTRL_DEVICE */ +PINCTRL_DEVICE(ACI2S, 5, &MUX_AC_I2S_CLK, &MUX_AC_I2S_DI, &MUX_AC_I2S_DO, + &MUX_AC_I2S_WS, &MUX_AC_MCLK); +PINCTRL_DEVICE(AC_MCLK, 1, &MUX_AC_MCLK); +PINCTRL_DEVICE(ARCJTAG, 5, &MUX_ARC_JTAG_TCK, &MUX_ARC_JTAG_TDI, + &MUX_ARC_JTAG_TDO, &MUX_ARC_JTAG_TMS, &MUX_ARC_JTAG_TRSTN); +PINCTRL_DEVICE(ARMJTAG, 5, &MUX_ARM_JTAG_TCK, &MUX_ARM_JTAG_TDI, + &MUX_ARM_JTAG_TDO, &MUX_ARM_JTAG_TMS, &MUX_ARM_JTAG_TRSTN); +PINCTRL_DEVICE(DWI2S, 4, &MUX_DW_I2S_CLK, &MUX_DW_I2S_DI, &MUX_DW_I2S_DO, + &MUX_DW_I2S_WS); +PINCTRL_DEVICE(ETH, 2, &MUX_ETH_LINK_ACT, &MUX_ETH_LINK_STA); +PINCTRL_DEVICE(I2C0, 2, &MUX_I2C0_SCL, &MUX_I2C0_SDA); +PINCTRL_DEVICE(I2C1, 2, &MUX_I2C1_SCL, &MUX_I2C1_SDA); +PINCTRL_DEVICE(I2C2, 2, &MUX_I2C2_SCL, &MUX_I2C2_SDA); +PINCTRL_DEVICE(PAEJTAG, 5, &MUX_PAE_JTAG_TCK, &MUX_PAE_JTAG_TDI, + &MUX_PAE_JTAG_TDO, &MUX_PAE_JTAG_TMS, &MUX_PAE_JTAG_TRSTN); +PINCTRL_DEVICE(PWM0, 1, &MUX_PWM0); +PINCTRL_DEVICE(PWM1, 1, &MUX_PWM1); +PINCTRL_DEVICE(PWM10, 1, &MUX_PWM10); +PINCTRL_DEVICE(PWM11, 1, &MUX_PWM11); +PINCTRL_DEVICE(PWM2, 1, &MUX_PWM2); +PINCTRL_DEVICE(PWM3, 1, &MUX_PWM3); +PINCTRL_DEVICE(PWM4, 1, &MUX_PWM4); +PINCTRL_DEVICE(PWM5, 1, &MUX_PWM5); +PINCTRL_DEVICE(PWM6, 1, &MUX_PWM6); +PINCTRL_DEVICE(PWM7, 1, &MUX_PWM7); +PINCTRL_DEVICE(PWM8, 1, &MUX_PWM8); +PINCTRL_DEVICE(PWM9, 1, &MUX_PWM9); +PINCTRL_DEVICE(RMII, 10, &MUX_MAC_MDC, &MUX_MAC_MDIO, &MUX_MAC_REF_CLK, + &MUX_MAC_RMII_CLK, &MUX_MAC_RXDV, &MUX_MAC_RXD_0, &MUX_MAC_RXD_1, + &MUX_MAC_TXD_0, &MUX_MAC_TXD_1, &MUX_MAC_TXEN); +PINCTRL_DEVICE(RTC, 1, &MUX_RTC_CLK); +PINCTRL_DEVICE(SADC_XAIN0, 1, &MUX_SADC_XAIN0); +PINCTRL_DEVICE(SADC_XAIN1, 1, &MUX_SADC_XAIN1); +PINCTRL_DEVICE(SADC_XAIN2, 1, &MUX_SADC_XAIN2); +PINCTRL_DEVICE(SADC_XAIN3, 1, &MUX_SADC_XAIN3); +PINCTRL_DEVICE(SD0, 7, &MUX_SD0_CD, &MUX_SD0_CLK, &MUX_SD0_CMD_RSP, + &MUX_SD0_DATA_0, &MUX_SD0_DATA_1, &MUX_SD0_DATA_2, &MUX_SD0_DATA_3); +PINCTRL_DEVICE(SD0_1BIT_NO_WP, 4, &MUX_SD0_CD, &MUX_SD0_CLK, &MUX_SD0_CMD_RSP, + &MUX_SD0_DATA_0); +PINCTRL_DEVICE(SD0_NO_WP, 7, &MUX_SD0_CD, &MUX_SD0_CLK, &MUX_SD0_CMD_RSP, + &MUX_SD0_DATA_0, &MUX_SD0_DATA_1, &MUX_SD0_DATA_2, &MUX_SD0_DATA_3); +PINCTRL_DEVICE(SD0_WIFI, 6, &MUX_SD0_CLK, &MUX_SD0_CMD_RSP, &MUX_SD0_DATA_0, + &MUX_SD0_DATA_1, &MUX_SD0_DATA_2, &MUX_SD0_DATA_3); +PINCTRL_DEVICE(SD1, 7, &MUX_SD1_CD, &MUX_SD1_CLK, &MUX_SD1_CMD_RSP, + &MUX_SD1_DATA_0, &MUX_SD1_DATA_1, &MUX_SD1_DATA_2, &MUX_SD1_DATA_3); +PINCTRL_DEVICE(SD1_1BIT_NO_WP, 4, &MUX_SD1_CD, &MUX_SD1_CLK, &MUX_SD1_CMD_RSP, + &MUX_SD1_DATA_0); +PINCTRL_DEVICE(SD1_NO_WP, 7, &MUX_SD1_CD, &MUX_SD1_CLK, &MUX_SD1_CMD_RSP, + &MUX_SD1_DATA_0, &MUX_SD1_DATA_1, &MUX_SD1_DATA_2, &MUX_SD1_DATA_3); +PINCTRL_DEVICE(SD1_WIFI, 6, &MUX_SD1_CLK, &MUX_SD1_CMD_RSP, &MUX_SD1_DATA_0, + &MUX_SD1_DATA_1, &MUX_SD1_DATA_2, &MUX_SD1_DATA_3); +PINCTRL_DEVICE(SENSOR_CLK, 1, &MUX_SENSOR_CLK); +PINCTRL_DEVICE(SSI0, 4, &MUX_GPIO6, &MUX_SSI0_CLK, &MUX_SSI0_RXD, + &MUX_SSI0_TXD); +PINCTRL_DEVICE(SSI0_4BIT, 6, &MUX_GPIO6, &MUX_SSI0_CLK, &MUX_SSI0_D2, + &MUX_SSI0_D3, &MUX_SSI0_RXD, &MUX_SSI0_TXD); +PINCTRL_DEVICE(SSI1, 4, &MUX_GPIO14, &MUX_SSI1_CLK, &MUX_SSI1_RXD, + &MUX_SSI1_TXD); +PINCTRL_DEVICE(SSI2, 4, &MUX_SSI2_CLK, &MUX_SSI2_CSN_0, &MUX_SSI2_RXD, + &MUX_SSI2_TXD); +PINCTRL_DEVICE(UART0, 2, &MUX_UART0_RX, &MUX_UART0_TX); +PINCTRL_DEVICE(UART1, 2, &MUX_UART1_RX, &MUX_UART1_TX); +PINCTRL_DEVICE(UART2, 2, &MUX_UART2_RX, &MUX_UART2_TX); +PINCTRL_DEVICE(USB, 1, &MUX_USB_PWREN); +PINCTRL_DEVICE(GPIO0, 1, &MUX_GPIO0); +PINCTRL_DEVICE(GPIO1, 1, &MUX_GPIO1); +PINCTRL_DEVICE(GPIO2, 1, &MUX_GPIO2); +PINCTRL_DEVICE(GPIO3, 1, &MUX_GPIO3); +PINCTRL_DEVICE(GPIO4, 1, &MUX_GPIO4); +PINCTRL_DEVICE(GPIO5, 1, &MUX_GPIO5); +PINCTRL_DEVICE(GPIO6, 1, &MUX_GPIO6); +PINCTRL_DEVICE(GPIO7, 1, &MUX_GPIO7); +PINCTRL_DEVICE(GPIO8, 1, &MUX_GPIO8); +PINCTRL_DEVICE(GPIO9, 1, &MUX_GPIO9); +PINCTRL_DEVICE(GPIO10, 1, &MUX_GPIO10); +PINCTRL_DEVICE(GPIO11, 1, &MUX_GPIO11); +PINCTRL_DEVICE(GPIO12, 1, &MUX_GPIO12); +PINCTRL_DEVICE(GPIO13, 1, &MUX_GPIO13); +PINCTRL_DEVICE(GPIO14, 1, &MUX_GPIO14); +PINCTRL_DEVICE(GPIO15, 1, &MUX_GPIO15); +PINCTRL_DEVICE(GPIO16, 1, &MUX_GPIO16); +PINCTRL_DEVICE(GPIO17, 1, &MUX_GPIO17); +PINCTRL_DEVICE(GPIO18, 1, &MUX_GPIO18); +PINCTRL_DEVICE(GPIO19, 1, &MUX_GPIO19); +PINCTRL_DEVICE(GPIO20, 1, &MUX_GPIO20); +PINCTRL_DEVICE(GPIO21, 1, &MUX_GPIO21); +PINCTRL_DEVICE(GPIO22, 1, &MUX_GPIO22); +PINCTRL_DEVICE(GPIO23, 1, &MUX_GPIO23); +PINCTRL_DEVICE(GPIO24, 1, &MUX_GPIO24); +PINCTRL_DEVICE(GPIO25, 1, &MUX_GPIO25); +PINCTRL_DEVICE(GPIO26, 1, &MUX_GPIO26); +PINCTRL_DEVICE(GPIO27, 1, &MUX_GPIO27); +PINCTRL_DEVICE(GPIO28, 1, &MUX_GPIO28); +PINCTRL_DEVICE(GPIO29, 1, &MUX_GPIO29); +PINCTRL_DEVICE(GPIO30, 1, &MUX_GPIO30); +PINCTRL_DEVICE(GPIO31, 1, &MUX_GPIO31); +PINCTRL_DEVICE(GPIO32, 1, &MUX_GPIO32); +PINCTRL_DEVICE(GPIO33, 1, &MUX_GPIO33); +PINCTRL_DEVICE(GPIO34, 1, &MUX_GPIO34); +PINCTRL_DEVICE(GPIO35, 1, &MUX_GPIO35); +PINCTRL_DEVICE(GPIO36, 1, &MUX_GPIO36); +PINCTRL_DEVICE(GPIO37, 1, &MUX_GPIO37); +PINCTRL_DEVICE(GPIO38, 1, &MUX_GPIO38); +PINCTRL_DEVICE(GPIO39, 1, &MUX_GPIO39); +PINCTRL_DEVICE(GPIO40, 1, &MUX_GPIO40); +PINCTRL_DEVICE(GPIO41, 1, &MUX_GPIO41); +PINCTRL_DEVICE(GPIO42, 1, &MUX_GPIO42); +PINCTRL_DEVICE(GPIO43, 1, &MUX_GPIO43); +PINCTRL_DEVICE(GPIO44, 1, &MUX_GPIO44); +PINCTRL_DEVICE(GPIO45, 1, &MUX_GPIO45); +PINCTRL_DEVICE(GPIO46, 1, &MUX_GPIO46); +PINCTRL_DEVICE(GPIO47, 1, &MUX_GPIO47); +PINCTRL_DEVICE(GPIO48, 1, &MUX_GPIO48); +PINCTRL_DEVICE(GPIO49, 1, &MUX_GPIO49); +PINCTRL_DEVICE(GPIO50, 1, &MUX_GPIO50); +PINCTRL_DEVICE(GPIO51, 1, &MUX_GPIO51); +PINCTRL_DEVICE(GPIO52, 1, &MUX_GPIO52); +PINCTRL_DEVICE(GPIO53, 1, &MUX_GPIO53); +PINCTRL_DEVICE(GPIO54, 1, &MUX_GPIO54); +PINCTRL_DEVICE(GPIO55, 1, &MUX_GPIO55); +PINCTRL_DEVICE(GPIO56, 1, &MUX_GPIO56); +PINCTRL_DEVICE(GPIO57, 1, &MUX_GPIO57); +PINCTRL_DEVICE(GPIO58, 1, &MUX_GPIO58); +PINCTRL_DEVICE(GPIO59, 1, &MUX_GPIO59); +PINCTRL_DEVICE(GPIO60, 1, &MUX_GPIO60); +PINCTRL_DEVICE(GPIO61, 1, &MUX_GPIO61); +PINCTRL_DEVICE(GPIO62, 1, &MUX_GPIO62); +PINCTRL_DEVICE(GPIO63, 1, &MUX_GPIO63); + +PINCTRL_DEVICE(SD1_EMMC, 6, &MUX_SD1_CLK_EMMC, &MUX_SD1_CMD_RSP_EMMC, + &MUX_SD1_DATA_0_EMMC, &MUX_SD1_DATA_1_EMMC, &MUX_SD1_DATA_2_EMMC, + &MUX_SD1_DATA_3_EMMC); + +void fh_pinctrl_init_devicelist(OS_LIST *list) +{ + OS_LIST_EMPTY(list); + + /*PINCTRL_ADD_DEVICE*/ + PINCTRL_ADD_DEVICE(ACI2S); + PINCTRL_ADD_DEVICE(AC_MCLK); + PINCTRL_ADD_DEVICE(ARCJTAG); + PINCTRL_ADD_DEVICE(ARMJTAG); + PINCTRL_ADD_DEVICE(DWI2S); + PINCTRL_ADD_DEVICE(ETH); + PINCTRL_ADD_DEVICE(I2C0); + PINCTRL_ADD_DEVICE(I2C1); + PINCTRL_ADD_DEVICE(I2C2); + PINCTRL_ADD_DEVICE(PAEJTAG); + PINCTRL_ADD_DEVICE(PWM0); + PINCTRL_ADD_DEVICE(PWM1); + PINCTRL_ADD_DEVICE(PWM10); + PINCTRL_ADD_DEVICE(PWM11); + PINCTRL_ADD_DEVICE(PWM2); + PINCTRL_ADD_DEVICE(PWM3); + PINCTRL_ADD_DEVICE(PWM4); + PINCTRL_ADD_DEVICE(PWM5); + PINCTRL_ADD_DEVICE(PWM6); + PINCTRL_ADD_DEVICE(PWM7); + PINCTRL_ADD_DEVICE(PWM8); + PINCTRL_ADD_DEVICE(PWM9); + PINCTRL_ADD_DEVICE(RMII); + PINCTRL_ADD_DEVICE(RTC); + PINCTRL_ADD_DEVICE(SADC_XAIN0); + PINCTRL_ADD_DEVICE(SADC_XAIN1); + PINCTRL_ADD_DEVICE(SADC_XAIN2); + PINCTRL_ADD_DEVICE(SADC_XAIN3); + PINCTRL_ADD_DEVICE(SD0); + PINCTRL_ADD_DEVICE(SD0_1BIT_NO_WP); + PINCTRL_ADD_DEVICE(SD0_NO_WP); + PINCTRL_ADD_DEVICE(SD0_WIFI); + PINCTRL_ADD_DEVICE(SD1); + PINCTRL_ADD_DEVICE(SD1_1BIT_NO_WP); + PINCTRL_ADD_DEVICE(SD1_NO_WP); + PINCTRL_ADD_DEVICE(SD1_WIFI); + PINCTRL_ADD_DEVICE(SENSOR_CLK); + PINCTRL_ADD_DEVICE(SSI0); + PINCTRL_ADD_DEVICE(SSI0_4BIT); + PINCTRL_ADD_DEVICE(SSI1); + PINCTRL_ADD_DEVICE(SSI2); + PINCTRL_ADD_DEVICE(UART0); + PINCTRL_ADD_DEVICE(UART1); + PINCTRL_ADD_DEVICE(UART2); + PINCTRL_ADD_DEVICE(USB); + PINCTRL_ADD_DEVICE(GPIO0); + PINCTRL_ADD_DEVICE(GPIO1); + PINCTRL_ADD_DEVICE(GPIO2); + PINCTRL_ADD_DEVICE(GPIO3); + PINCTRL_ADD_DEVICE(GPIO4); + PINCTRL_ADD_DEVICE(GPIO5); + PINCTRL_ADD_DEVICE(GPIO6); + PINCTRL_ADD_DEVICE(GPIO7); + PINCTRL_ADD_DEVICE(GPIO8); + PINCTRL_ADD_DEVICE(GPIO9); + PINCTRL_ADD_DEVICE(GPIO10); + PINCTRL_ADD_DEVICE(GPIO11); + PINCTRL_ADD_DEVICE(GPIO12); + PINCTRL_ADD_DEVICE(GPIO13); + PINCTRL_ADD_DEVICE(GPIO14); + PINCTRL_ADD_DEVICE(GPIO15); + PINCTRL_ADD_DEVICE(GPIO16); + PINCTRL_ADD_DEVICE(GPIO17); + PINCTRL_ADD_DEVICE(GPIO18); + PINCTRL_ADD_DEVICE(GPIO19); + PINCTRL_ADD_DEVICE(GPIO20); + PINCTRL_ADD_DEVICE(GPIO21); + PINCTRL_ADD_DEVICE(GPIO22); + PINCTRL_ADD_DEVICE(GPIO23); + PINCTRL_ADD_DEVICE(GPIO24); + PINCTRL_ADD_DEVICE(GPIO25); + PINCTRL_ADD_DEVICE(GPIO26); + PINCTRL_ADD_DEVICE(GPIO27); + PINCTRL_ADD_DEVICE(GPIO28); + PINCTRL_ADD_DEVICE(GPIO29); + PINCTRL_ADD_DEVICE(GPIO30); + PINCTRL_ADD_DEVICE(GPIO31); + PINCTRL_ADD_DEVICE(GPIO32); + PINCTRL_ADD_DEVICE(GPIO33); + PINCTRL_ADD_DEVICE(GPIO34); + PINCTRL_ADD_DEVICE(GPIO35); + PINCTRL_ADD_DEVICE(GPIO36); + PINCTRL_ADD_DEVICE(GPIO37); + PINCTRL_ADD_DEVICE(GPIO38); + PINCTRL_ADD_DEVICE(GPIO39); + PINCTRL_ADD_DEVICE(GPIO40); + PINCTRL_ADD_DEVICE(GPIO41); + PINCTRL_ADD_DEVICE(GPIO42); + PINCTRL_ADD_DEVICE(GPIO43); + PINCTRL_ADD_DEVICE(GPIO44); + PINCTRL_ADD_DEVICE(GPIO45); + PINCTRL_ADD_DEVICE(GPIO46); + PINCTRL_ADD_DEVICE(GPIO47); + PINCTRL_ADD_DEVICE(GPIO48); + PINCTRL_ADD_DEVICE(GPIO49); + PINCTRL_ADD_DEVICE(GPIO50); + PINCTRL_ADD_DEVICE(GPIO51); + PINCTRL_ADD_DEVICE(GPIO52); + PINCTRL_ADD_DEVICE(GPIO53); + PINCTRL_ADD_DEVICE(GPIO54); + PINCTRL_ADD_DEVICE(GPIO55); + PINCTRL_ADD_DEVICE(GPIO56); + PINCTRL_ADD_DEVICE(GPIO57); + PINCTRL_ADD_DEVICE(GPIO58); + PINCTRL_ADD_DEVICE(GPIO59); + PINCTRL_ADD_DEVICE(GPIO60); + PINCTRL_ADD_DEVICE(GPIO61); + PINCTRL_ADD_DEVICE(GPIO62); + PINCTRL_ADD_DEVICE(GPIO63); + + PINCTRL_ADD_DEVICE(SD1_EMMC); +} + +char *fh_pinctrl_selected_devices[] = +{ + CONFIG_PINCTRL_SELECT +}; diff --git a/arch/arm/mach-fh/fh8856v200/Makefile b/arch/arm/mach-fh/fh8856v200/Makefile new file mode 100644 index 00000000..1443fdae --- /dev/null +++ b/arch/arm/mach-fh/fh8856v200/Makefile @@ -0,0 +1 @@ +obj-y += board.o chip.o \ No newline at end of file diff --git a/arch/arm/mach-fh/fh8856v200/board.c b/arch/arm/mach-fh/fh8856v200/board.c new file mode 100644 index 00000000..2b9fa6de --- /dev/null +++ b/arch/arm/mach-fh/fh8856v200/board.c @@ -0,0 +1,1165 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +struct uart_port fh_serial_ports[FH_UART_NUMBER]; + +static struct map_desc fh8856v200_io_desc[] = { + { + .virtual = VA_RAM_REG_BASE, + .pfn = __phys_to_pfn(RAM_BASE), + .length = SZ_16K, + .type = MT_MEMORY_RWX, + }, + { + .virtual = VA_DDRC_REG_BASE, + .pfn = __phys_to_pfn(DDRC_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_INTC_REG_BASE, + .pfn = __phys_to_pfn(INTC_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_TIMER_REG_BASE, + .pfn = __phys_to_pfn(TIMER_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_PMU_REG_BASE, + .pfn = __phys_to_pfn(PMU_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_UART0_REG_BASE, + .pfn = __phys_to_pfn(UART0_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_UART1_REG_BASE, + .pfn = __phys_to_pfn(UART1_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_UART2_REG_BASE, + .pfn = __phys_to_pfn(UART2_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + +}; + +static struct resource fh_gpio0_resources[] = { + { + .start = GPIO0_REG_BASE, + .end = GPIO0_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = GPIO0_IRQ, + .end = GPIO0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_gpio1_resources[] = { + { + .start = GPIO1_REG_BASE, + .end = GPIO1_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = GPIO1_IRQ, + .end = GPIO1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_uart0_resources[] = { + { + .start = (UART0_REG_BASE), + .end = (UART0_REG_BASE) + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = UART0_IRQ, + .end = UART0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_uart1_resources[] = { + { + .start = (UART1_REG_BASE), + .end = (UART1_REG_BASE) + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = UART1_IRQ, + .end = UART1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_uart2_resources[] = { + { + .start = (UART2_REG_BASE), + .end = (UART2_REG_BASE) + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = UART2_IRQ, + .end = UART2_IRQ, + .flags = IORESOURCE_IRQ, + } +}; +static struct resource fh_sdc0_resources[] = { + { + .start = SDC0_REG_BASE, + .end = SDC0_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SDC0_IRQ, + .end = SDC0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_sdc1_resources[] = { + { + .start = SDC1_REG_BASE, + .end = SDC1_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SDC1_IRQ, + .end = SDC1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_gmac_resources[] = { + { + .start = GMAC_REG_BASE, + .end = GMAC_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = GMAC_IRQ, + .end = GMAC_IRQ, + .flags = IORESOURCE_IRQ, + } +}; + +static struct resource fh_wdt_resources[] = { + { + .start = WDT_REG_BASE, + .end = WDT_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = WDT_IRQ, + .end = WDT_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +#ifdef CONFIG_FH_PERF_MON +static struct resource fh_perf_resources[] = { + { + .start = PMU_REG_BASE, + .end = PMU_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = PERF_IRQ, + .end = PERF_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +#endif + + +static struct fh_gmac_platform_data fh_gmac_data = { + .phy_reset_pin = 29, +}; + +static struct fh_uart_dma uart1_dma_info = { +#ifdef CONFIG_UART_TX_DMA + .tx_hs_no = UART1_TX_HW_HANDSHAKE, + .tx_dma_channel = UART1_DMA_TX_CHAN, +#endif + .rx_hs_no = UART1_RX_HW_HANDSHAKE, + .rx_dma_channel = UART1_DMA_RX_CHAN, + .rx_xmit_len = 16, +}; + +static struct fh_uart_dma uart2_dma_info = { +#ifdef CONFIG_UART_TX_DMA + .tx_hs_no = UART2_TX_HW_HANDSHAKE, + .tx_dma_channel = UART2_DMA_TX_CHAN, +#endif + .rx_hs_no = UART2_RX_HW_HANDSHAKE, + .rx_dma_channel = UART2_DMA_RX_CHAN, + .rx_xmit_len = 16, +}; + + +static struct fh_platform_uart fh_uart_platform_data[] = { + { + .mapbase = UART0_REG_BASE, + .fifo_size = 16, + .irq = UART0_IRQ, + .uartclk = 16666667, + .use_dma = 0, + .dma_info = NULL, + }, + { + .mapbase = UART1_REG_BASE, + .fifo_size = 32, + .irq = UART1_IRQ, + .uartclk = 16666667, + .use_dma = 0, + .dma_info = &uart1_dma_info, + }, + { + .mapbase = UART2_REG_BASE, + .fifo_size = 32, + .irq = UART2_IRQ, + .uartclk = 16666667, + .use_dma = 0, + .dma_info = &uart2_dma_info, + }, +}; + +static struct resource fh_pwm_resources[] = { + { + .start = PWM_REG_BASE, + .end = PWM_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = PWM_IRQ, + .end = PWM_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_i2c_resources_0[] = { + { + .start = I2C0_REG_BASE, + .end = I2C0_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = I2C0_IRQ, + .end = I2C0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_i2c_resources_1[] = { + { + .start = I2C1_REG_BASE, + .end = I2C1_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = I2C1_IRQ, + .end = I2C1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_i2c_resources_2[] = { + { + .start = I2C2_REG_BASE, + .end = I2C2_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = I2C2_IRQ, + .end = I2C2_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_rtc_resources[] = { + { + .start = RTC_REG_BASE, + .end = RTC_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = RTC_IRQ, + .end = RTC_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct fh_gpio_chip fh_gpio0_chip = { + .chip = { + .owner = THIS_MODULE, + .label = "FH_GPIO0", + .base = 0, + .ngpio = 32, + }, +}; + +static struct fh_gpio_chip fh_gpio1_chip = { + .chip = { + .owner = THIS_MODULE, + .label = "FH_GPIO1", + .base = 32, + .ngpio = 32, + }, +}; + +static struct fh_pwm_data pwm_data = { + .npwm = 12, +}; + +static struct resource fh_sadc_resources[] = { + { + .start = SADC_REG_BASE, + .end = SADC_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SADC_IRQ, + .end = SADC_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_aes_resources[] = { + { + .start = AES_REG_BASE, + .end = AES_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = AES_IRQ, + .end = AES_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_efuse_resources[] = { + { + .start = EFUSE_REG_BASE, + .end = EFUSE_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +#ifdef CONFIG_FH_DMAC +static struct resource fh_dma_resources[] = { + { + .start = (DMAC_REG_BASE), + .end = (DMAC_REG_BASE) + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = DMAC0_IRQ, + .end = DMAC0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +#endif + +#ifdef CONFIG_FH_AXI_DMAC +static struct resource fh_axi_dma_resources[] = { + { + .start = (DMAC_REG_BASE), + .end = (DMAC_REG_BASE) + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = DMAC0_IRQ, + .end = DMAC0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +#endif + +static struct resource fh_spi0_resources[] = { + { + .start = SPI0_REG_BASE, + .end = SPI0_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SPI0_IRQ, + .end = SPI0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_spi1_resources[] = { + { + .start = SPI1_REG_BASE, + .end = SPI1_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SPI1_IRQ, + .end = SPI1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_spi2_resources[] = { + { + .start = SPI2_REG_BASE, + .end = SPI2_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + .name = "fh spi2 mem", + }, + { + .start = SPI2_IRQ, + .end = SPI2_IRQ, + .flags = IORESOURCE_IRQ, + .name = "fh spi2 irq", + }, +}; + +static struct resource fh_usb_resources[] = { + { + .start = USBC_REG_BASE, + .end = USBC_REG_BASE + SZ_1M - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = USBC_IRQ, + .end = USBC_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static unsigned int fh_mci_sys_card_detect_fixed(struct fhmci_host *host) +{ + return 0; +} + +struct fh_mci_board fh_mci = { + .num_slots = 1, + .get_cd = fh_mci_sys_card_detect_fixed, + .bus_hz = 50000000, + .detect_delay_ms = 200, + .caps = MMC_CAP_4_BIT_DATA, + /*8:180 degree*/ + .drv_degree = 8, + .sam_degree = 0, + .rescan_max_num = 2, +}; + +struct fh_mci_board fh_mci_sd = { + .num_slots = 1, + .bus_hz = 50000000, + .detect_delay_ms = 200, + .caps = MMC_CAP_4_BIT_DATA, + /*8:180 degree*/ + .drv_degree = 8, + .sam_degree = 0, +}; + +static struct platform_device fh_gmac_device = { + .name = "fh_gmac", + .id = 0, + .num_resources = ARRAY_SIZE(fh_gmac_resources), + .resource = fh_gmac_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &fh_gmac_data, + }, +}; + +struct platform_device fh_sd0_device = { + .name = "fh_mci", + .id = 0, + .num_resources = ARRAY_SIZE(fh_sdc0_resources), + .resource = fh_sdc0_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &fh_mci_sd, + } +}; + +struct platform_device fh_sd1_device = { + .name = "fh_mci", + .id = 1, + .num_resources = ARRAY_SIZE(fh_sdc1_resources), + .resource = fh_sdc1_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &fh_mci, + } +}; + +struct fh_sadc_platform_data fh_sadc_data = { + .ref_vol = 1800, + .active_bit = 0xfff, +}; + +static struct platform_device fh_sadc_device = { + .name = "fh_sadc", + .id = 0, + .num_resources = ARRAY_SIZE(fh_sadc_resources), + .resource = fh_sadc_resources, + .dev = { + .platform_data = &fh_sadc_data, + }, +}; + +static struct platform_device fh_uart0_device = { + .name = "ttyS", + .id = 0, + .num_resources = ARRAY_SIZE(fh_uart0_resources), + .resource = fh_uart0_resources, + .dev.platform_data = &fh_uart_platform_data[0], +}; + +static struct platform_device fh_uart1_device = { + .name = "ttyS", + .id = 1, + .num_resources = ARRAY_SIZE(fh_uart1_resources), + .resource = fh_uart1_resources, + .dev.platform_data = &fh_uart_platform_data[1], +}; + +static struct platform_device fh_uart2_device = { + .name = "ttyS", + .id = 2, + .num_resources = ARRAY_SIZE(fh_uart2_resources), + .resource = fh_uart2_resources, + .dev.platform_data = &fh_uart_platform_data[2], +}; + +static struct platform_device fh_pinctrl_device = { + .name = "fh_pinctrl", + .id = 0, +}; + +static struct platform_device fh_i2c0_device = { + .name = "fh_i2c", + .id = 0, + .num_resources = ARRAY_SIZE(fh_i2c_resources_0), + .resource = fh_i2c_resources_0, +}; + +static struct platform_device fh_i2c1_device = { + .name = "fh_i2c", + .id = 1, + .num_resources = ARRAY_SIZE(fh_i2c_resources_1), + .resource = fh_i2c_resources_1, +}; + +static struct platform_device fh_i2c2_device = { + .name = "fh_i2c", + .id = 2, + .num_resources = ARRAY_SIZE(fh_i2c_resources_2), + .resource = fh_i2c_resources_2, +}; + +static struct fh_rtc_plat_data rtc_plat_data[] = { + { + .lut_cof = 58, + .lut_offset = 0xff, + .tsensor_cp_default_out = 0x993, + .clk_name = "rtc_hclk_gate", + }, + { + .lut_cof = 71, + .lut_offset = 0xf6, + .tsensor_cp_default_out = 0x9cc, + .clk_name = "rtc_hclk_gate", + } +}; + +static struct platform_device fh_rtc_device = { + .name = "fh_rtc", + .id = 0, + .num_resources = ARRAY_SIZE(fh_rtc_resources), + .resource = fh_rtc_resources, + .dev.platform_data = &rtc_plat_data[0], +}; + +static struct resource fh_i2s_resources[] = { + { + .start = I2S_REG_BASE, + .end = I2S_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = ACW_REG_BASE, + .end = ACW_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = I2S0_IRQ, + .end = I2S0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct fh_i2s_platform_data fh_i2s_data = { + .dma_capture_channel = 4, + .dma_playback_channel = 5, + .dma_master = 0, + .dma_rx_hs_num = 10, + .dma_tx_hs_num = 11, + .clk = "i2s_clk", + .acodec_mclk = "ac_clk", +}; + +static struct platform_device fh_i2s_device = { + .name = "fh_audio", + .id = 0, + .num_resources = ARRAY_SIZE(fh_i2s_resources), + .resource = fh_i2s_resources, + .dev = { + .platform_data = &fh_i2s_data, + }, +}; + +static struct platform_device fh_gpio0_device = { + .name = GPIO_NAME, + .id = 0, + .num_resources = ARRAY_SIZE(fh_gpio0_resources), + .resource = fh_gpio0_resources, + .dev = { + .platform_data = &fh_gpio0_chip, + }, +}; + +static struct platform_device fh_gpio1_device = { + .name = GPIO_NAME, + .id = 1, + .num_resources = ARRAY_SIZE(fh_gpio1_resources), + .resource = fh_gpio1_resources, + .dev = { + .platform_data = &fh_gpio1_chip, + }, +}; + +static struct platform_device fh_aes_device = { + .name = "fh_aes", + .id = 0, + .num_resources = ARRAY_SIZE(fh_aes_resources), + .resource = fh_aes_resources, + .dev = { + .platform_data = NULL, + }, +}; + +struct fh_efuse_platform_data fh_efuse_plat_data = { + .efuse_support_flag = CRYPTO_CPU_SET_KEY | + CRYPTO_EX_MEM_SET_KEY | + CRYPTO_EX_MEM_SWITCH_KEY | + CRYPTO_EX_MEM_4_ENTRY_1_KEY | + CRYPTO_EX_MEM_INDEP_POWER, +}; + + + +#define FH_SPI0_CS0 (6) +#define FH_SPI0_CS1 (55) + +#define FH_SPI1_CS0 (14) +#define FH_SPI1_CS1 (57) + +#define SPI0_FIFO_DEPTH (128) +#define SPI0_CLK_IN (200000000) +#define SPI0_MAX_SLAVE_NO (2) +#define SPI0_DMA_RX_CHANNEL (0) +#define SPI0_DMA_TX_CHANNEL (1) + +#define SPI1_FIFO_DEPTH (64) +#define SPI1_CLK_IN (100000000) +#define SPI1_MAX_SLAVE_NO (2) +#define SPI1_DMA_RX_CHANNEL (2) +#define SPI1_DMA_TX_CHANNEL (3) + +#define SPI2_CLK_IN (100000000) + +/* SPI_TRANSFER_USE_DMA */ +static struct fh_spi_platform_data fh_spi0_data = { + .bus_no = 0, + .apb_clock_in = SPI0_CLK_IN, + .clock_source = {100000000, 150000000, 200000000}, + .clock_source_num = 3, + .slave_max_num = SPI0_MAX_SLAVE_NO, + .cs_data[0].GPIO_Pin = FH_SPI0_CS0, + .cs_data[0].name = "spi0_cs0", + .cs_data[1].GPIO_Pin = FH_SPI0_CS1, + .cs_data[1].name = "spi0_cs1", + .clk_name = "spi0_clk", + .dma_transfer_enable = SPI_TRANSFER_USE_DMA, + .rx_dma_channel = SPI0_DMA_RX_CHANNEL, + .rx_handshake_num = 4, + /*dma use inc mode could move data by burst mode...*/ + /*or move data use single mode with low efficient*/ + .ctl_wire_support = ONE_WIRE_SUPPORT | DUAL_WIRE_SUPPORT | + MULTI_WIRE_SUPPORT, +}; + +static struct fh_spi_platform_data fh_spi1_data = { + .bus_no = 1, + .apb_clock_in = SPI1_CLK_IN, + .clock_source = {SPI1_CLK_IN}, + .clock_source_num = 1, + .slave_max_num = SPI1_MAX_SLAVE_NO, + .cs_data[0].GPIO_Pin = FH_SPI1_CS0, + .cs_data[0].name = "spi1_cs0", + .cs_data[1].GPIO_Pin = FH_SPI1_CS1, + .cs_data[1].name = "spi1_cs1", + .clk_name = "spi1_clk", + .ctl_wire_support = 0, +}; + +static struct fh_spi_platform_data fh_spi2_data = { + .apb_clock_in = SPI2_CLK_IN, + .dma_transfer_enable = 0, + .rx_handshake_num = 12, + .clk_name = "spi2_clk", + .ctl_wire_support = 0, +}; + +static struct platform_device fh_efuse_device = { + .name = "fh_efuse", + .id = 0, + .num_resources = ARRAY_SIZE(fh_efuse_resources), + .resource = fh_efuse_resources, + .dev = { + .platform_data = &fh_efuse_plat_data, + }, +}; + +#ifdef CONFIG_FH_DMAC +static struct fh_dma_platform_data fh_dma_data = { + .chan_priority = CHAN_PRIORITY_ASCENDING, + .nr_channels = 6, + .clk_name = "ahb_clk", +}; + +static struct platform_device fh_dma_device = { + .name = "fh_dmac", + .id = 0, + .num_resources = ARRAY_SIZE(fh_dma_resources), + .resource = fh_dma_resources, + .dev = { + .platform_data = &fh_dma_data, + }, +}; +#endif + +#ifdef CONFIG_FH_AXI_DMAC +struct fh_axi_dma_platform_data axi_dma_plat_data = { + .chan_priority = CHAN_PRIORITY_ASCENDING, + .clk_name = "ahb_clk", +}; + +static struct platform_device fh_axi_dma_device = { + .name = "fh_axi_dmac", + .id = 0, + .num_resources = ARRAY_SIZE(fh_axi_dma_resources), + .resource = fh_axi_dma_resources, + .dev = { + .platform_data = &axi_dma_plat_data, + }, +}; +#endif + + + +static struct platform_device fh_spi0_device = { + .name = "fh_spi", + .id = 0, + .num_resources = ARRAY_SIZE(fh_spi0_resources), + .resource = fh_spi0_resources, + .dev = { + .platform_data = &fh_spi0_data, + }, +}; + +static struct platform_device fh_spi1_device = { + .name = "fh_spi", + .id = 1, + .num_resources = ARRAY_SIZE(fh_spi1_resources), + .resource = fh_spi1_resources, + .dev = { + .platform_data = &fh_spi1_data, + }, +}; + +static struct platform_device fh_spi2_device = { + .name = "fh_spi_slave", + .id = 0, + .num_resources = ARRAY_SIZE(fh_spi2_resources), + .resource = fh_spi2_resources, + .dev = { + .platform_data = &fh_spi2_data, + }, +}; + +#ifdef CONFIG_FH_PERF_MON +static struct platform_device fh_perf_device = { + .name = "fh_perf_mon", + .id = 0, + .num_resources = ARRAY_SIZE(fh_perf_resources), + .resource = fh_perf_resources, + .dev = { + .platform_data = NULL, + }, +}; +#endif + +static struct fh_wdt_platform_data fh_wdt_data = { + .mode = MODE_DISCRETE, +}; + +struct platform_device fh_wdt_device = { + .name = "fh_wdt", + .id = 0, + .num_resources = ARRAY_SIZE(fh_wdt_resources), + .resource = fh_wdt_resources, + .dev = { + .platform_data = &fh_wdt_data, + } +}; + +static struct platform_device fh_pwm_device = { + .name = "fh_pwm", + .id = 0, + .num_resources = ARRAY_SIZE(fh_pwm_resources), + .resource = fh_pwm_resources, + .dev = { + .platform_data = &pwm_data, + }, +}; + +static struct fh_usb_platform_data fh_usb_data = { + .dr_mode = "host", + .vbus_pwren = 47, +}; + +struct platform_device fh_usb_device = { + .name = "fh_usb", + .id = 0, + .num_resources = ARRAY_SIZE(fh_usb_resources), + .resource = fh_usb_resources, + .dev = { + .platform_data = &fh_usb_data, + } +}; + +#ifdef CONFIG_FH_TSENSOR +struct platform_device fh_tsensor_device = { + .name = "fh_tsensor", + .id = 0, +}; +#endif + +static struct platform_device *fh8856v200_devices[] __initdata = { + &fh_uart0_device, + &fh_uart1_device, + &fh_uart2_device, + &fh_pinctrl_device, + &fh_i2c0_device, + &fh_i2c1_device, + &fh_i2c2_device, + &fh_rtc_device, + &fh_sd0_device, + &fh_sd1_device, + &fh_sadc_device, + &fh_gmac_device, + &fh_gpio0_device, + &fh_gpio1_device, + &fh_aes_device, + &fh_efuse_device, +#ifdef CONFIG_FH_DMAC + &fh_dma_device, +#endif +#ifdef CONFIG_FH_AXI_DMAC + &fh_axi_dma_device, +#endif + &fh_spi0_device, + &fh_spi1_device, + &fh_spi2_device, + &fh_i2s_device, + &fh_pwm_device, + &fh_wdt_device, + &fh_usb_device, +#ifdef CONFIG_FH_PERF_MON + &fh_perf_device, +#endif +#ifdef CONFIG_FH_TSENSOR + &fh_tsensor_device, +#endif +}; + +static struct mtd_partition fh_sf_parts[] = { + { + /* head & Ramboot */ + .name = "bootstrap", + .offset = 0, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + /* Ramboot & U-Boot environment */ + .name = "uboot-env", + .offset = MTDPART_OFS_APPEND, + .size = SZ_64K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + /* U-Boot */ + .name = "uboot", + .offset = MTDPART_OFS_APPEND, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_4M, + .mask_flags = 0, + }, { + .name = "rootfs", + .offset = MTDPART_OFS_APPEND, + .size = SZ_8M, + .mask_flags = 0, + }, { + .name = "app", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + } + /* mtdparts= + * spi_flash:256k(bootstrap), + * 64k(u-boot-env), + * 192k(u-boot),4M(kernel), + * 8M(rootfs), + * -(app) */ + /* two blocks with bad block table (and mirror) at the end */ +}; +#ifdef CONFIG_MTD_SPI_NAND +static struct mtd_partition fh_sf_nand_parts[] = { + { + /* head & Ramboot */ + .name = "bootstrap", + .offset = 0, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + .name = "uboot-env", + .offset = MTDPART_OFS_APPEND, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "uboot", + .offset = MTDPART_OFS_APPEND, + .size = SZ_512K, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_4M, + .mask_flags = 0, + }, { + .name = "rootfs", + .offset = MTDPART_OFS_APPEND, + .size = SZ_8M, + .mask_flags = 0, + }, { + .name = "app", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + } + /* mtdparts= + * spi0.0:64k(bootstrap), + * 64k(u-boot-env), + * 192k(u-boot), + * 4M(kernel), + * 8M(rootfs), + * -(app) + * two blocks with bad block table (and mirror) at the end + */ +}; +#endif + +static struct flash_platform_data fh_flash_platform_data = { + .name = "spi_flash", + .parts = fh_sf_parts, + .nr_parts = ARRAY_SIZE(fh_sf_parts), +}; +#ifdef CONFIG_MTD_SPI_NAND +static struct flash_platform_data fh_nandflash_platform_data = { + .name = "spi_nandflash", + .parts = fh_sf_nand_parts, + .nr_parts = ARRAY_SIZE(fh_sf_nand_parts), +}; +#endif + +static struct spi_board_info fh_spi_devices[] = { +#ifdef CONFIG_MTD_SPI_NAND + { + .modalias = "spi-nand", + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 50000000, + .mode = SPI_MODE_3, + .platform_data = &fh_nandflash_platform_data, + }, +#endif + { + .modalias = "m25p80", + .bus_num = 0, + .chip_select = 0, + /* multi wire should adapt spi para 'ctl_wire_support'*/ + .mode = SPI_MODE_3 | SPI_RX_DUAL, + .max_speed_hz = 50000000, + .platform_data = &fh_flash_platform_data, + }, + +}; + +extern void early_print(const char *str, ...); + +static void __init fh_console_pre_init(struct fh_platform_uart *plat, int num) +{ + int idx = 0; + + for (; idx < num; idx++) { + struct uart_port *port; + + port = &fh_serial_ports[idx]; + port->mapbase = plat[idx].mapbase; + port->fifosize = plat[idx].fifo_size; + port->uartclk = plat[idx].uartclk; + + switch (idx) { + case 0: + port->membase = (unsigned char *)VA_UART0_REG_BASE; + break; + case 1: + port->membase = (unsigned char *)VA_UART1_REG_BASE; + break; + case 2: + port->membase = (unsigned char *)VA_UART2_REG_BASE; + break; + default: + break; + } + } +} + +static void __init fh8856v200_map_io(void) +{ + iotable_init(fh8856v200_io_desc, ARRAY_SIZE(fh8856v200_io_desc)); + fh_console_pre_init(fh_uart_platform_data, + ARRAY_SIZE(fh_uart_platform_data)); +} + + +static __init void fh8856v200_board_init(void) +{ + if (fh_is_8856v210()) + fh_rtc_device.dev.platform_data = &rtc_plat_data[1]; + platform_add_devices(fh8856v200_devices, + ARRAY_SIZE(fh8856v200_devices)); + spi_register_board_info(fh_spi_devices, ARRAY_SIZE(fh_spi_devices)); +} +void __init fh_timer_init_no_of(unsigned int iovbase, + unsigned int irqno); + +static void __init fh8856v200_init_early(void) +{ + fh_pmu_init(); + fh_pinctrl_init(VA_PMU_REG_BASE + 0x80); +} + +static void __init fh_time_init(void) +{ + unsigned int vtimerbase = (unsigned int)ioremap(TIMER_REG_BASE, SZ_4K); + + fh_clk_init(); + fh_timer_init_no_of(vtimerbase, TMR0_IRQ); + +} + +void __init fh_intc_init_no_of(unsigned int iovbase); +static void __init fh_intc_init(void) +{ + unsigned int vintcbase = (unsigned int)ioremap(INTC_REG_BASE, SZ_4K); + + fh_intc_init_no_of(vintcbase); + +} +static void fh8856v200_restart + (enum reboot_mode mode, const char *cmd) +{ + fh_pmu_restart(); +} + + +MACHINE_START(FH8856V200, "FH8856V200") + .atag_offset = 0x100, + .map_io = fh8856v200_map_io, + .init_irq = fh_intc_init, + .init_time = fh_time_init, + .init_machine = fh8856v200_board_init, + .init_early = fh8856v200_init_early, + .restart = fh8856v200_restart, +MACHINE_END + diff --git a/arch/arm/mach-fh/fh8856v200/board_config.fh8856v200.appboard b/arch/arm/mach-fh/fh8856v200/board_config.fh8856v200.appboard new file mode 100644 index 00000000..1c1a9153 --- /dev/null +++ b/arch/arm/mach-fh/fh8856v200/board_config.fh8856v200.appboard @@ -0,0 +1,45 @@ +#ifndef BOARD_CONFIG_H_ +#define BOARD_CONFIG_H_ + +/* + * GPIO0 -> IRCUT_ON + * GPIO1 -> IRCUT_OFF + * GPIO2 -> USB_PWREN + * GPIO11 -> EMAC PHY Reset + * GPIO12 -> CIS_CLK + * GPIO13 -> CIS_RSTN + * GPIO14 -> CIS_PDN + * GPIO19 -> SD1_PWREN/WIFI_REG_ON + * GPIO20 -> AK7755 Reset + * GPIO24 -> LED0 + * GPIO25 -> LED1 + * GPIO26 -> Reset Configs + * GPIO27 -> AK7755 PowerDown + * GPIO28 -> IR + * GPIO53 -> USB_PWREN/SD0_PWREN + * GPIO55 -> SD1 WIFI Interrupt + */ + +#define CONFIG_SD_CD_FIXED + +#define CONFIG_ISP_CLK_RATE 171000000 +#define CONFIG_JPEG_CLK_RATE 171000000 +#define CONFIG_VEU_CLK_RATE 240000000 + +#define USB_VBUS_PWR_GPIO (47) + +#define ETH_GPIO "ETH", "GPIO48", "GPIO49", "GPIO50", "GPIO51", "GPIO52",\ + "GPIO53", "GPIO54", "GPIO55", "GPIO56" + +#define CONFIG_PINCTRL_SELECT \ + ETH_GPIO, "I2C0", "PWM2", "PWM3", "PWM4", "PWM5", "PWM6", \ + "PWM7", "PWM8", "PWM9", "SADC_XAIN0", "SADC_XAIN1", \ + "SD0_NO_WP", "SENSOR_CLK", "SSI0_4BIT", "UART0", \ + "UART1", "GPIO4", "GPIO13", "GPIO30", "GPIO31", \ + "GPIO32", "GPIO43", "GPIO44", "GPIO47", \ +\ + "GPIO11", "GPIO14", "GPIO15", "GPIO16", "GPIO24", \ + "GPIO25", "GPIO45", "GPIO46", "GPIO57", "GPIO58", "GPIO59", \ + "GPIO60", "GPIO61", "GPIO62", "GPIO63" + +#endif /* BOARD_CONFIG_H_ */ diff --git a/arch/arm/mach-fh/fh8856v200/chip.c b/arch/arm/mach-fh/fh8856v200/chip.c new file mode 100644 index 00000000..9bbb3c49 --- /dev/null +++ b/arch/arm/mach-fh/fh8856v200/chip.c @@ -0,0 +1,747 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * external oscillator + * fixed to 24M + */ +static struct fh_clk osc_clk = { + .name = "osc_clk", + .frequency = OSC_FREQUENCY, + .flag = CLOCK_FIXED, +}; + +/* + * phase-locked-loop device, + * generates a higher frequency clock + * from the external oscillator reference + *PLL_DDR + */ + +static struct fh_clk pll_ddr_rclk = { + .name = "pll_ddr_rclk", + .flag = CLOCK_PLL_R|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL0, + .en_reg_offset = REG_PMU_PLL0_CTRL, + .en_reg_mask = 0xf000, +}; + +/*PLL_CPU*/ +static struct fh_clk pll_cpu_pclk = { + .name = "pll_cpu_pclk", + .flag = CLOCK_PLL_P|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL1, + .en_reg_offset = REG_PMU_PLL1_CTRL, + .en_reg_mask = 0xf00, +}; + +static struct fh_clk pll_cpu_rclk = { + .name = "pll_cpu_rclk", + .flag = CLOCK_PLL_R|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL1, + .en_reg_offset = REG_PMU_PLL1_CTRL, + .en_reg_mask = 0xf000, +}; + +/*PLL_SYS*/ +static struct fh_clk pll_sys_pclk = { + .name = "pll_sys_pclk", + .flag = CLOCK_PLL_P|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL2, + .en_reg_offset = REG_PMU_PLL2_CTRL, + .en_reg_mask = 0xf00, +}; + + +static struct fh_clk pll_sys_rclk = { + .name = "pll_sys_rclk", + .flag = CLOCK_PLL_R|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL2, + .en_reg_offset = REG_PMU_PLL2_CTRL, + .en_reg_mask = 0xf000, +}; + +static struct fh_clk pllsysp_div12_clk = { + .name = "pllsysp_div12_clk", + .flag = CLOCK_NORESET|CLOCK_NOGATE, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV5, + .div_reg_mask = 0xf000000, +}; + +static struct fh_clk ddr_clk = { + .name = "ddr_clk", + .flag = CLOCK_NODIV, + .parent = {&pll_ddr_rclk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x4000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x8, +}; +static struct fh_clk arm_clk = { + .name = "arm_clk", + .flag = CLOCK_MULTI_PARENT|CLOCK_NOGATE|CLOCK_NODIV, + .parent = {&osc_clk, &pll_cpu_pclk}, + .prediv = 1, + .sel_reg_offset = REG_PMU_SYS_CTRL, + .sel_reg_mask = 0x1, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x1, +}; +static struct fh_clk arc_clk = { + .name = "arc_clk", + .flag = CLOCK_MULTI_PARENT|CLOCK_NODIV, + .parent = {&osc_clk, &pll_cpu_rclk}, + .prediv = 1, + .sel_reg_offset = REG_PMU_SYS_CTRL, + .sel_reg_mask = 0x1, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x400000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x400000, +}; +static struct fh_clk ahb_clk = { + .name = "ahb_clk", + .flag = CLOCK_MULTI_PARENT|CLOCK_NORESET|CLOCK_NOGATE, + .parent = {&osc_clk, &pll_sys_pclk}, + .prediv = 1, + .sel_reg_offset = REG_PMU_SYS_CTRL, + .sel_reg_mask = 0x1, + .div_reg_offset = REG_PMU_CLK_DIV0, + .div_reg_mask = 0xf0000, +}; + +static struct fh_clk isp_aclk = { + .name = "isp_aclk", + .flag = CLOCK_NORESET, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV0, + .div_reg_mask = 0xf00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x1, + .def_rate = CONFIG_ISP_CLK_RATE, +}; +static struct fh_clk ispb_aclk = { + .name = "ispb_aclk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&isp_aclk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x4, +}; + +static struct fh_clk vpu_clk = { + .name = "vpu_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&isp_aclk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x80000000, +}; + +static struct fh_clk pix_clk = { + .name = "pix_clk", + .flag = CLOCK_NORESET|CLOCK_NOGATE, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV2, + .div_reg_mask = 0xf000000, +}; + +static struct fh_clk jpeg_clk = { + .name = "jpeg_clk", + .flag = CLOCK_NORESET, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV7, + .div_reg_mask = 0xf00000, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x40000000, + .def_rate = CONFIG_JPEG_CLK_RATE, +}; + +static struct fh_clk bgm_clk = { + .name = "bgm_clk", + .flag = CLOCK_NORESET, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV7, + .div_reg_mask = 0xf00000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x40000, +}; + +static struct fh_clk jpeg_adapt_clk = { + .name = "jpeg_adapt_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&jpeg_clk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x2, +}; +static struct fh_clk spi0_clk = { + .name = "spi0_clk", + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xff, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x80, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x100, +}; +static struct fh_clk sdc0_clk = { + .name = "sdc0_clk", + .parent = {&pll_sys_pclk}, + .prediv = 8, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xf00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x200, + .rst_reg_offset = REG_PMU_SWRST_AHB_CTRL, + .rst_reg_mask = 0x4, +}; +static struct fh_clk spi2_clk = { + .name = "spi2_clk", + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xf000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x2, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x100000, +}; +static struct fh_clk spi1_clk = { + .name = "spi1_clk", + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xff0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x100, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x200, +}; +static struct fh_clk sdc1_clk = { + .name = "sdc1_clk", + .parent = {&pll_sys_pclk}, + .prediv = 8, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xf000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x400, + .rst_reg_offset = REG_PMU_SWRST_AHB_CTRL, + .rst_reg_mask = 0x2, +}; + +static struct fh_clk veu_clk = { + .name = "veu_clk", + .flag = CLOCK_MULTI_PARENT, + .parent = {&pll_sys_pclk, &pll_sys_rclk}, + .prediv = 1, + .sel_reg_offset = REG_PMU_SYS_CTRL, + .sel_reg_mask = 0x4, + .div_reg_offset = REG_PMU_CLK_DIV0, + .div_reg_mask = 0x7000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x10, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x2000000, + .def_rate = CONFIG_VEU_CLK_RATE, + +}; + +static struct fh_clk veu_adapt_clk = { + .name = "veu_adapt_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&veu_clk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x20000000, + +}; + +static struct fh_clk cis_clk_out = { + .name = "cis_clk_out", + .flag = CLOCK_NORESET, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV1, + .div_reg_mask = 0xff0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x800000, +}; + +static struct fh_clk eth_clk = { + .name = "eth_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV6, + .div_reg_mask = 0xf000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x12000000, + .rst_reg_offset = REG_PMU_SWRST_AHB_CTRL, + .rst_reg_mask = 0x20000, +}; +static struct fh_clk i2c0_clk = { + .name = "i2c0_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV4, + .div_reg_mask = 0x3f0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x1000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x400, +}; + +static struct fh_clk i2c1_clk = { + .name = "i2c1_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV4, + .div_reg_mask = 0x3f000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x8000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x800, +}; + +static struct fh_clk i2c2_clk = { + .name = "i2c2_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV7, + .div_reg_mask = 0x00003f00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x00000008, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x20000000, +}; + +static struct fh_clk pwm_clk = { + .name = "pwm_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV5, + .div_reg_mask = 0xff, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x10000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x80, + .def_rate = 50000000, +}; + +static struct fh_clk uart0_clk = { + .name = "uart0_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV4, + .div_reg_mask = 0x1f, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x2000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x4000, + .def_rate = 16666666, +}; + +static struct fh_clk uart1_clk = { + .name = "uart1_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV4, + .div_reg_mask = 0x1f00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x4000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x8000, + .def_rate = 16666666, +}; +static struct fh_clk uart2_clk = { + .name = "uart2_clk", + .parent = {&pllsysp_div12_clk}, + .flag = 0, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV7, + .div_reg_mask = 0x7f, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x8000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x8000000, + .def_rate = 16666666, +}; + +static struct fh_clk efuse_clk = { + .name = "efuse_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV1, + .div_reg_mask = 0x3f000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x200000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x800000, +}; + +static struct fh_clk pts_clk = { + .name = "pts_clk", + .parent = {&pllsysp_div12_clk}, + .flag = CLOCK_NORESET, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV2, + .div_reg_mask = 0x1ff, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x80000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL2, + .rst_reg_mask = 0x1, + .def_rate = 1000000, +}; + +static struct fh_clk tmr0_clk = { + .name = "tmr0_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV5, + .div_reg_mask = 0xff0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x20000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x40000, +}; + +static struct fh_clk sadc_clk = { + .name = "sadc_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV6, + .div_reg_mask = 0x7f0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x4000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x10000, +}; + +static struct fh_clk ac_clk = { + .name = "ac_clk", + .parent = {&osc_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV6, + .div_reg_mask = 0x3f, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x800, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x1000, +}; + +static struct fh_clk i2s_clk = { + .name = "i2s_clk", + .parent = {&ac_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV6, + .div_reg_mask = 0x3f00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x1000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x2000, +}; + +static struct fh_clk wdt_clk = { + .name = "wdt_clk", + .flag = 0, + .parent = {&ahb_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV5, + .div_reg_mask = 0xff00, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x8000000, + .rst_reg_offset = REG_PMU_SWRST_APB_CTRL, + .rst_reg_mask = 0x100000, + .def_rate = 1000000, +}; + +static struct fh_clk gpio0_db_clk = { + .name = "gpio0_db_clk", + .flag = 0, + .parent = {&pllsysp_div12_clk}, + .prediv = 100, + .div_reg_offset = REG_PMU_CLK_DIV8, + .div_reg_mask = 0x7fff, + .en_reg_offset = REG_PMU_CLK_DIV8, + .en_reg_mask = 0x8000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x10, +}; + +static struct fh_clk gpio1_db_clk = { + .name = "gpio1_db_clk", + .flag = 0, + .parent = {&pllsysp_div12_clk}, + .prediv = 100, + .div_reg_offset = REG_PMU_CLK_DIV8, + .div_reg_mask = 0x7fff0000, + .en_reg_offset = REG_PMU_CLK_DIV8, + .en_reg_mask = 0x80000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x20, +}; + + +static struct fh_clk mipi_dphy_clk = { + .name = "mipi_dphy_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&osc_clk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x100000, +}; +static struct fh_clk mipi_wrap_gate = { + .name = "mipi_wrap_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x20000000, +}; +static struct fh_clk rtc_hclk_gate = { + .name = "rtc_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x10000000, +}; +static struct fh_clk emac_hclk_gate = { + .name = "emac_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x2000000, +}; +static struct fh_clk usb_clk = { + .name = "usb_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x1000000, +}; +static struct fh_clk aes_hclk_gate = { + .name = "aes_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x80, +}; +static struct fh_clk ephy_clk_gate = { + .name = "ephy_clk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x1, +}; +static struct fh_clk sdc0_clk8x_gate = { + .name = "sdc0_clk8x_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x4, +}; +static struct fh_clk sdc1_clk8x_gate = { + .name = "sdc1_clk8x_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x8, +}; +static struct fh_clk mipic_pclk_gate = { + .name = "mipic_pclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x10, +}; + +static struct fh_clk gpio0_pclk_gate = { + .name = "gpio0_pclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV8, + .en_reg_mask = 0x4000, +}; +static struct fh_clk gpio1_pclk_gate = { + .name = "gpio1_pclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV8, + .en_reg_mask = 0x40000000, +}; +static struct fh_clk isp_hclk_gate = { + .name = "isp_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x1000000, +}; +static struct fh_clk veu_hclk_gate = { + .name = "veu_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x2000000, +}; +static struct fh_clk bgm_hclk_gate = { + .name = "bgm_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x4000000, +}; +static struct fh_clk adapt_hclk_gate = { + .name = "adapt_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x8000000, +}; +static struct fh_clk jpg_hclk_gate = { + .name = "jpg_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x10000000, +}; +static struct fh_clk jpg_adapt_gate = { + .name = "jpg_adapt_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x20000000, +}; +static struct fh_clk vpu_hclk_gate = { + .name = "vpu_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x40000000, +}; + +static struct fh_clk sdc0_clk_sample = { + .name = "sdc0_clk_sample", + .parent = {&sdc0_clk}, + .flag = CLOCK_NOGATE | CLOCK_PHASE, + .prediv = 1, + .sel_reg_offset = REG_PMU_CLK_GATE1, + .sel_reg_mask = 0xf0000, +}; + +static struct fh_clk sdc0_clk_drv = { + .name = "sdc0_clk_drv", + .parent = {&sdc0_clk}, + .flag = CLOCK_NOGATE | CLOCK_PHASE, + .prediv = 1, + .sel_reg_offset = REG_PMU_CLK_GATE1, + .sel_reg_mask = 0xf00000, +}; + +static struct fh_clk sdc1_clk_sample = { + .name = "sdc1_clk_sample", + .parent = {&sdc0_clk}, + .flag = CLOCK_NOGATE | CLOCK_PHASE, + .prediv = 1, + .sel_reg_offset = REG_PMU_CLK_GATE1, + .sel_reg_mask = 0xf00, +}; + +static struct fh_clk sdc1_clk_drv = { + .name = "sdc1_clk_drv", + .parent = {&sdc0_clk}, + .flag = CLOCK_NOGATE | CLOCK_PHASE, + .prediv = 1, + .sel_reg_offset = REG_PMU_CLK_GATE1, + .sel_reg_mask = 0xf000, +}; + +struct fh_clk *fh_clks[] = { + &osc_clk, + &pll_ddr_rclk, + &pll_cpu_pclk, + &pll_cpu_rclk, + &pll_sys_pclk, + &pll_sys_rclk, + &arm_clk, + &arc_clk, + &ahb_clk, + &ddr_clk, + &isp_aclk, + &ispb_aclk, + &jpeg_clk, + &jpeg_adapt_clk, + &vpu_clk, + &veu_clk, + &veu_adapt_clk, + &bgm_clk, + &mipi_dphy_clk, + &pllsysp_div12_clk, + &cis_clk_out, + &pix_clk, + &pts_clk, + &spi0_clk, + &spi1_clk, + &spi2_clk, + &sdc0_clk, + &sdc1_clk, + &uart0_clk, + &uart1_clk, + &uart2_clk, + &i2c0_clk, + &i2c1_clk, + &i2c2_clk, + &pwm_clk, + &wdt_clk, + &tmr0_clk, + &ac_clk, + &i2s_clk, + &sadc_clk, + ð_clk, + &efuse_clk, + &gpio0_db_clk, + &gpio1_db_clk, + &mipi_wrap_gate, + &rtc_hclk_gate, + &emac_hclk_gate, + &usb_clk, + &aes_hclk_gate, + &ephy_clk_gate, + &sdc0_clk8x_gate, + &sdc1_clk8x_gate, + &gpio0_pclk_gate, + &gpio1_pclk_gate, + &mipic_pclk_gate, + &sdc0_clk_sample, + &sdc0_clk_drv, + &sdc1_clk_sample, + &sdc1_clk_drv, + &isp_hclk_gate, + &veu_hclk_gate, + &bgm_hclk_gate, + &adapt_hclk_gate, + &jpg_hclk_gate, + &jpg_adapt_gate, + &vpu_hclk_gate, + NULL, +}; +EXPORT_SYMBOL(fh_clks); diff --git a/arch/arm/mach-fh/fh8856v200/chip.h b/arch/arm/mach-fh/fh8856v200/chip.h new file mode 100644 index 00000000..18ff2d65 --- /dev/null +++ b/arch/arm/mach-fh/fh8856v200/chip.h @@ -0,0 +1,421 @@ +#ifndef __ASM_ARCH_HL_H +#define __ASM_ARCH_HL_H + +#include + +#define SRAM_GRANULARITY 32 +#define SRAM_SIZE (SZ_128K+SZ_8K) + + +#define RAM_BASE (0x10000000) +#define DDR_BASE (0xA0000000) + + +#define PMU_REG_BASE (0xF0000000) +#define TIMER_REG_BASE (0xF0C00000) +#define GPIO0_REG_BASE (0xF0300000) +#define GPIO1_REG_BASE (0xF4000000) +#define UART0_REG_BASE (0xF0700000) +#define UART1_REG_BASE (0xF0800000) +#define SPI0_REG_BASE (0xF0500000) +#define SPI1_REG_BASE (0xF0600000) +#define SPI2_REG_BASE (0xF0640000) +#define INTC_REG_BASE (0xE0200000) +#define GMAC_REG_BASE (0xE0600000) +#define USBC_REG_BASE (0xE0700000) +#define DMAC_REG_BASE (0xE0300000) +#define I2C1_REG_BASE (0xF0B00000) +#define I2C0_REG_BASE (0xF0200000) +#define I2C2_REG_BASE (0xF0100000) +#define SDC0_REG_BASE (0xE2000000) +#define SDC1_REG_BASE (0xE2200000) +#define WDT_REG_BASE (0xF0D00000) +#define PWM_REG_BASE (0xF0400000) +#define I2S_REG_BASE (0xF0900000) +#define ACW_REG_BASE (0xF0A00000) +#define UART2_REG_BASE (0xF1300000) +#define SADC_REG_BASE (0xF1200000) +#define EFUSE_REG_BASE (0xF1600000) +#define AES_REG_BASE (0xE8200000) +#define RTC_REG_BASE (0xF1500000) +#define DDRC_REG_BASE (0xED000000) +#define CONSOLE_REG_BASE UART0_REG_BASE +#define FH_UART_NUMBER 3 + +#define FH_PMU_REG_SIZE 0x2110 +#define REG_PMU_CHIP_ID (0x0000) +#define REG_PMU_IP_VER (0x0004) +#define REG_PMU_FW_VER (0x0008) +#define REG_PMU_CLK_SEL (0x000c) +/*for HL REG_PMU_SYS_CTRL and CLK_SEL use one register */ +#define REG_PMU_SYS_CTRL (0x000c) +#define REG_PMU_PLL0 (0x0010) +#define REG_PMU_PLL1 (0x0014) +#define REG_PMU_PLL0_CTRL (0x0018) +#define REG_PMU_CLK_GATE (0x001c) +#define REG_PMU_CLK_GATE1 (0x0020) +#define REG_PMU_CLK_DIV0 (0x0024) +#define REG_PMU_CLK_DIV1 (0x0028) +#define REG_PMU_CLK_DIV2 (0x002c) +#define REG_PMU_CLK_DIV3 (0x0030) +#define REG_PMU_CLK_DIV4 (0x0034) +#define REG_PMU_CLK_DIV5 (0x0038) +#define REG_PMU_CLK_DIV6 (0x003c) +#define REG_PMU_SWRST_MAIN_CTRL (0x0040) +#define REG_PMU_SWRST_MAIN_CTRL2 (0x0044) +#define REG_PMU_SWRST_AHB_CTRL (0x0048) +#define REG_PMU_SWRST_APB_CTRL (0x004c) +#define REG_PMU_SPC_IO_STATUS (0x0054) +#define REG_PMU_SPC_FUN (0x0058) +#define REG_PMU_CLK_DIV7 (0x005c) +#define REG_PMU_CLK_DIV8 (0x0060) +#define REG_PMU_PLL2 (0x0064) +#define REG_PMU_PLL2_CTRL (0x0068) +#define REG_PMU_PLL1_CTRL (0x006c) +#define REG_PAD_PWR_SEL (0x0074) +#define REG_PMU_SWRSTN_NSR (0x0078) +#define REG_PMU_SWRSTN_NSR1 (0x007c) +#define REG_PMU_ETHPHY_REG0 (0x2108) + + +#define REG_PMU_PAD_BOOT_MODE_CFG (0x0080) +#define REG_PMU_PAD_BOOT_SEL1_CFG (0x0084) +#define REG_PMU_PAD_BOOT_SEL0_CFG (0x0088) +#define REG_PMU_PAD_UART0_TX_CFG (0x008c) +#define REG_PMU_PAD_UART0_RX_CFG (0x0090) +#define REG_PMU_PAD_I2C0_SCL_CFG (0x0094) +#define REG_PMU_PAD_I2C0_SDA_CFG (0x0098) +#define REG_PMU_PAD_SENSOR_CLK_CFG (0x009c) +#define REG_PMU_PAD_SENSOR_RSTN_CFG (0x00a0) +#define REG_PMU_PAD_UART1_TX_CFG (0x00a4) +#define REG_PMU_PAD_UART1_RX_CFG (0x00a8) +#define REG_PMU_PAD_I2C1_SCL_CFG (0x00ac) +#define REG_PMU_PAD_I2C1_SDA_CFG (0x00b0) +#define REG_PMU_PAD_UART2_TX_CFG (0x00b4) +#define REG_PMU_PAD_UART2_RX_CFG (0x00b8) +#define REG_PMU_PAD_USB_PWREN_CFG (0x00bc) +#define REG_PMU_PAD_PWM0_CFG (0x00c0) +#define REG_PMU_PAD_PWM1_CFG (0x00c4) +#define REG_PMU_PAD_PWM2_CFG (0x00c8) +#define REG_PMU_PAD_PWM3_CFG (0x00cc) +#define REG_PMU_PAD_MAC_RMII_CLK_CFG (0x00d0) +#define REG_PMU_PAD_MAC_REF_CLK_CFG (0x00d4) +#define REG_PMU_PAD_MAC_TXD0_CFG (0x00d8) +#define REG_PMU_PAD_MAC_TXD1_CFG (0x00dc) +#define REG_PMU_PAD_MAC_TXEN_CFG (0x00e0) +#define REG_PMU_PAD_MAC_RXD0_CFG (0x00e4) +#define REG_PMU_PAD_MAC_RXD1_CFG (0x00e8) +#define REG_PMU_PAD_MAC_RXDV_CFG (0x00ec) +#define REG_PMU_PAD_MAC_MDC_CFG (0x00f0) +#define REG_PMU_PAD_MAC_MDIO_CFG (0x00f4) +#define REG_PMU_PAD_SD1_CLK_CFG (0x00f8) +#define REG_PMU_PAD_SD1_CD_CFG (0x00fc) +#define REG_PMU_PAD_SD1_CMD_RSP_CFG (0x0100) +#define REG_PMU_PAD_SD1_DATA_0_CFG (0x0104) +#define REG_PMU_PAD_SD1_DATA_1_CFG (0x0108) +#define REG_PMU_PAD_SD1_DATA_2_CFG (0x010c) +#define REG_PMU_PAD_SD1_DATA_3_CFG (0x0110) +#define REG_PMU_PAD_GPIO_0_CFG (0x0114) +#define REG_PMU_PAD_GPIO_1_CFG (0x0118) +#define REG_PMU_PAD_GPIO_2_CFG (0x011c) +#define REG_PMU_PAD_GPIO_3_CFG (0x0120) +#define REG_PMU_PAD_GPIO_4_CFG (0x0124) +#define REG_PMU_PAD_SSI0_CLK_CFG (0x0128) +#define REG_PMU_PAD_SSI0_CSN_0_CFG (0x012c) +#define REG_PMU_PAD_SSI0_TXD_CFG (0x0130) +#define REG_PMU_PAD_SSI0_RXD_CFG (0x0134) +#define REG_PMU_PAD_SSI0_D2_CFG (0x0138) +#define REG_PMU_PAD_SSI0_D3_CFG (0x013c) +#define REG_PMU_PAD_SSI1_CLK_CFG (0x0140) +#define REG_PMU_PAD_SSI1_CSN_0_CFG (0x0144) +#define REG_PMU_PAD_SSI1_TXD_CFG (0x0148) +#define REG_PMU_PAD_SSI1_RXD_CFG (0x014c) +#define REG_PMU_PAD_SD0_CD_CFG (0x0150) +#define REG_PMU_PAD_SD0_CLK_CFG (0x0154) +#define REG_PMU_PAD_SD0_CMD_RSP_CFG (0x0158) +#define REG_PMU_PAD_SD0_DATA_0_CFG (0x015c) +#define REG_PMU_PAD_SD0_DATA_1_CFG (0x0160) +#define REG_PMU_PAD_SD0_DATA_2_CFG (0x0164) +#define REG_PMU_PAD_SD0_DATA_3_CFG (0x0168) +#define REG_PMU_PAD_SADC_XAIN0_CFG (0x016c) +#define REG_PMU_PAD_SADC_XAIN1_CFG (0x0170) +#define REG_PMU_PAD_SADC_XAIN2_CFG (0x0174) +#define REG_PMU_PAD_SADC_XAIN3_CFG (0x0178) +#define REG_PMU_PAD_GPIO_28_CFG (0x017c) +#define REG_PMU_PAD_GPIO_29_CFG (0x0180) + +#define REG_PMU_ARM_INT_0 (0x01e0) +#define REG_PMU_ARM_INT_1 (0x01e4) +#define REG_PMU_ARM_INT_2 (0x01e8) +#define REG_PMU_A625_INT_0 (0x01ec) +#define REG_PMU_A625_INT_1 (0x01f0) +#define REG_PMU_A625_INT_2 (0x01f4) +#define REG_PMU_DMA (0x01f8) +#define REG_PMU_WDT_CTRL (0x01fc) +#define REG_PMU_DBG_STAT0 (0x0200) +#define REG_PMU_DBG_STAT1 (0x0204) +#define REG_PMU_DBG_STAT2 (0x0208) +#define REG_PMU_DBG_STAT3 (0x020c) +#define REG_PMU_USB_SYS (0x0210) +#define REG_PMU_USB_CFG (0x0214) +#define REG_PMU_USB_TUNE (0x0218) +#define REG_PMU_USB_SYS1 (0x0228) +#define REG_PMU_PTSLO (0x022c) +#define REG_PMU_PTSHI (0x0230) +#define REG_PMU_USER0 (0x0234) +#define REG_PMU_BOOT_MODE (0x0330) +#define REG_PMU_DDR_SIZE (0x0334) +#define REG_PMU_RESERVED2 (0x0338) +#define REG_PMU_CHIP_INFO (0x033c) +#define REG_PMU_EPHY_PARAM (0x0340) +#define REG_PMU_RTC_PARAM (0x0344) +#define REG_PMU_SD1_FUNC_SEL (0x03a0) +#define REG_PMU_PRDCID_CTRL0 (0x0500) +#define REG_PMU_A625BOOT0 (0x2000) +#define REG_PMU_A625BOOT1 (0x2004) +#define REG_PMU_A625BOOT2 (0x2008) +#define REG_PMU_A625BOOT3 (0x200c) +#define REG_PMU_A625_START_CTRL (0x2010) +#define REG_PMU_ARC_INTC_MASK (0x2014) + +#define FH_GMAC_AHB_RESET (1<<17) +#define FH_GMAC_SPEED_100M (1<<24) +#define PMU_RMII_SPEED_MODE (REG_PMU_CLK_SEL) +#define PMU_RXDV_GPIO_SWITCH (REG_PMU_PAD_MAC_RXDV_CFG) +#define PMU_RXDV_GPIO_MASK (0x0f000000) +#define PMU_RXDV_GPIO_VAL (0x01000000) + +#define PMU_DWI2S_CLK_SEL_REG (REG_PMU_CLK_SEL) +#define PMU_DWI2S_CLK_SEL_SHIFT (1) +#define PMU_DWI2S_CLK_DIV_REG (REG_PMU_CLK_DIV6) +#define PMU_DWI2S_CLK_DIV_SHIFT (0) + +/*ATTENTION: written by ARC */ +#define PMU_ARM_INT_MASK (0x01ec) +#define PMU_ARM_INT_RAWSTAT (0x01f0) +#define PMU_ARM_INT_STAT (0x01f4) + +#define PMU_A625_INT_MASK (0x01e0) +#define PMU_A625_INT_RAWSTAT (0x01e4) +#define PMU_A625_INT_STAT (0x01e8) + +#define PMU_IRQ 0 +#define DDRC_IRQ 1 +#define WDT_IRQ 2 +#define TMR0_IRQ 3 +#define VEU_IRQ 4 +#define PERF_IRQ 5 +#define VPU_IRQ 9 +#define I2C0_IRQ 11 +#define I2C1_IRQ 12 +#define JPEG_IRQ 13 +#define BGM_IRQ 14 +#define VEU_LOOP_IRQ 15 +#define AES_IRQ 16 +#define MIPIC_IRQ 17 +#define MIPI_WRAP_IRQ 18 +#define ACW_IRQ 19 +#define SADC_IRQ 20 +#define SPI1_IRQ 21 +#define JPEG_LOOP_IRQ 22 +#define DMAC0_IRQ 23 +#define DMAC1_IRQ 24 +#define I2S0_IRQ 25 +#define GPIO0_IRQ 26 +#define SPI0_IRQ 28 +#define ARC_SW_IRQ 29 +#define UART0_IRQ 30 +#define UART1_IRQ 31 +#define ARM_SW_IRQ 32 +#define RTC_IRQ 33 +#define PWM_IRQ 36 +#define SPI2_IRQ 38 +#define USBC_IRQ 39 +#define GPIO1_IRQ 40 +#define UART2_IRQ 41 +#define SDC0_IRQ 42 +#define SDC1_IRQ 43 +#define GMAC_IRQ 44 +#define EPHY_IRQ 45 +#define I2C2_IRQ 46 +#define RTC_ALM_IRQ 47 +#define RTC_CORE_IRQ 48 +/* because chips with some same function in different */ +/* pmu register, use wrap marco to make code to be same */ +#define PMU_RMII_SPEED_MODE (REG_PMU_CLK_SEL) + +#define MEM_START_PHY_ADDR DDR_BASE +#define MEM_SIZE 0x4000000 + + +#define NR_INTERNAL_IRQS (64) +#define NR_EXTERNAL_IRQS (64) +/*#define NR_IRQS (NR_INTERNAL_IRQS + NR_EXTERNAL_IRQS)*/ + +/* SWRST_MAIN_CTRL */ +#define CPU_RSTN_BIT (0) +#define UTMI_RSTN_BIT (1) +#define DDRPHY_RSTN_BIT (2) +#define DDRC_RSTN_BIT (3) +#define GPIO0_DB_RSTN_BIT (4) +#define GPIO1_DB_RSTN_BIT (5) +#define PIXEL_RSTN_BIT (6) +#define PWM_RSTN_BIT (7) +#define SPI0_RSTN_BIT (8) +#define SPI1_RSTN_BIT (9) +#define I2C0_RSTN_BIT (10) +#define I2C1_RSTN_BIT (11) +#define ACODEC_RSTN_BIT (12) +#define I2S_RSTN_BIT (13) +#define UART0_RSTN_BIT (14) +#define UART1_RSTN_BIT (15) +#define SADC_RSTN_BIT (16) +#define ADAPT_RSTN_BIT (17) +#define TMR_RSTN_BIT (18) +#define UART2_RSTN_BIT (19) +#define SPI2_RSTN_BIT (20) +#define JPG_ADAPT_RSTN_BIT (21) +#define ARC_RSTN_BIT (22) +#define EFUSE_RSTN_BIT (23) +#define JPG_RSTN_BIT (24) +#define VEU_RSTN_BIT (25) +#define VPU_RSTN_BIT (26) +#define ISP_RSTN_BIT (27) +#define BGM_RSTN_BIT (28) +#define I2C2_RSTN_BIT (29) +#define EPHY_RSTN_BIT (30) +#define SYS_RSTN_BIT (31) + +/* SWRST_AHB_CTRL */ +#define EMC_HRSTN_BIT (0) +#define SDC1_HRSTN_BIT (1) +#define SDC0_HRSTN_BIT (2) +#define AES_HRSTN_BIT (3) +#define DMAC0_HRSTN_BIT (4) +#define INTC_HRSTN_BIT (5) +#define JPEG_ADAPT_HRSTN_BIT (7) +#define JPEG_HRSTN_BIT (8) +#define VCU_HRSTN_BIT (9) +#define VPU_HRSTN_BIT (10) +#define ISP_HRSTN_BIT (11) +#define USB_HRSTN_BIT (12) +#define HRSTN_BIT (13) +#define EMAC_HRSTN_BIT (17) +#define DDRC_HRSTN_BIT (19) +#define DMAC1_HRSTN_BIT (20) +#define BGM_HRSTN_BIT (22) +#define ADAPT_HRSTN_BIT (23) + +/* SWRST_APB_CTRL */ +#define ACODEC_PRSTN_BIT (0) +#define I2S_PRSTN_BIT (1) +#define UART1_PRSTN_BIT (2) +#define UART0_PRSTN_BIT (3) +#define SPI0_PRSTN_BIT (4) +#define SPI1_PRSTN_BIT (5) +#define GPIO0_PRSTN_BIT (6) +#define UART2_PRSTN_BIT (7) +#define I2C2_PRSTN_BIT (8) +#define I2C0_PRSTN_BIT (9) +#define I2C1_PRSTN_BIT (10) +#define TMR_PRSTN_BIT (11) +#define PWM_PRSTN_BIT (12) +#define MIPIW_PRSTN_BIT (13) +#define MIPIC_PRSTN_BIT (14) +#define RTC_PRSTN_BIT (15) +#define SADC_PRSTN_BIT (16) +#define EFUSE_PRSTN_BIT (17) +#define SPI2_PRSTN_BIT (18) +#define WDT_PRSTN_BIT (19) +#define GPIO1_PRSTN_BIT (20) + +/* timer clk fpga 1M,soc 50M*/ +#ifdef CONFIG_FPGA +#define TIMER_CLK (1000000) +#else +#define TIMER_CLK (50000000) +#endif + +#define UART1_TX_HW_HANDSHAKE (9) +#define UART1_RX_HW_HANDSHAKE (8) +#define UART2_TX_HW_HANDSHAKE (13) +#define UART2_RX_HW_HANDSHAKE (12) +#define UART1_DMA_TX_CHAN (4) +#define UART1_DMA_RX_CHAN (5) +#define UART2_DMA_TX_CHAN (4) +#define UART2_DMA_RX_CHAN (5) + +/*sdio*/ +#define SIMPLE_0 (0) +#define SIMPLE_22 (1) +#define SIMPLE_45 (2) +#define SIMPLE_67 (3) +#define SIMPLE_90 (4) +#define SIMPLE_112 (5) +#define SIMPLE_135 (6) +#define SIMPLE_157 (7) +#define SIMPLE_180 (8) +#define SIMPLE_202 (9) +#define SIMPLE_225 (10) +#define SIMPLE_247 (11) +#define SIMPLE_270 (12) +#define SIMPLE_292 (13) +#define SIMPLE_315 (14) +#define SIMPLE_337 (15) + + + +#define SDIO0_RST_BIT (~UL(1<<2)) +#define SDIO0_CLK_RATE (50000000) +#define SDIO0_CLK_DRV_SHIFT (20) +#define SDIO0_CLK_DRV_DEGREE (SIMPLE_180) +#define SDIO0_CLK_SAM_SHIFT (16) +#define SDIO0_CLK_SAM_DEGREE (SIMPLE_0) + + +#define SDIO1_RST_BIT (~UL(1<<1)) +#define SDIO1_CLK_RATE (50000000) +#define SDIO1_CLK_DRV_SHIFT (12) +#define SDIO1_CLK_DRV_DEGREE (SIMPLE_180) +#define SDIO1_CLK_SAM_SHIFT (8) +#define SDIO1_CLK_SAM_DEGREE (SIMPLE_0) + +#define SDC0_HRSTN (0x1<<2) +#define SDC1_HRSTN (0x1<<1) +#define SDC2_HRSTN (0) + + +/*usb*/ +#define IRQ_UHOST USBC_IRQ +#define FH_PA_OTG USBC_REG_BASE +#define IRQ_OTG IRQ_UHOST +#define FH_SZ_USBHOST SZ_1M +#define FH_SZ_OTG SZ_1M + +#define USB_UTMI_RST_BIT (0x1<<1) +#define USB_PHY_RST_BIT (0x11) +#define USB_SLEEP_MODE_BIT (0x1<<24) +#define USB_IDDQ_PWR_BIT (0x1<<10) + + +/* Specific Uart Number */ +#define FH_UART_NUMBER 3 +#define CLK_SCAN_BIT_POS (28) +#define INSIDE_PHY_ENABLE_BIT_POS (24) +#define MAC_REF_CLK_DIV_MASK (0x0f) +#define MAC_REF_CLK_DIV_BIT_POS (24) +#define MAC_PAD_RMII_CLK_MASK (0x0f) +#define MAC_PAD_RMII_CLK_BIT_POS (24) +#define MAC_PAD_MAC_REF_CLK_BIT_POS (28) +#define ETH_REF_CLK_OUT_GATE_BIT_POS (25) +#define ETH_RMII_CLK_OUT_GATE_BIT_POS (28) +#define IN_OR_OUT_PHY_SEL_BIT_POS (26) +#define INSIDE_CLK_GATE_BIT_POS (0) +#define INSIDE_PHY_SHUTDOWN_BIT_POS (31) +#define INSIDE_PHY_RST_BIT_POS (30) +#define INSIDE_PHY_TRAINING_BIT_POS (27) +#define INSIDE_PHY_TRAINING_MASK (0x0f) + +#define TRAINING_EFUSE_ACTIVE_BIT_POS 4 + +#endif /* __ASM_ARCH_HL_H */ diff --git a/arch/arm/mach-fh/fh8856v200/iopad.h b/arch/arm/mach-fh/fh8856v200/iopad.h new file mode 100644 index 00000000..ebc24024 --- /dev/null +++ b/arch/arm/mach-fh/fh8856v200/iopad.h @@ -0,0 +1,729 @@ +#include +#include +#include + +/* PINCTRL_FUNC */ +PINCTRL_FUNC(GPIO30, 0, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(GPIO31, 1, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(ETH_LINK_ACT, 1, FUNC1, PUPD_UP, 0); +PINCTRL_FUNC(GPIO32, 2, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(ETH_LINK_STA, 2, FUNC1, PUPD_UP, 0); +PINCTRL_FUNC(ETH_LINK_SPD, 2, FUNC2, PUPD_UP, 0); +PINCTRL_FUNC(UART0_TX, 3, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO33, 3, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART0_RX, 4, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO34, 4, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C0_SCL, 5, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(GPIO35, 5, FUNC1, PUPD_UP, 0); +PINCTRL_FUNC(I2C0_SDA, 6, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(GPIO36, 6, FUNC1, PUPD_UP, 0); +PINCTRL_FUNC(SENSOR_CLK, 7, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO12, 7, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO13, 8, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(UART1_TX, 9, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO39, 9, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CLK, 9, FUNC3, PUPD_NONE, 3); +PINCTRL_FUNC(TEST_O_INT_RMII_CLK, 9, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(UART1_RX, 10, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO40, 10, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 10, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_INT_RMII_TXD_0, 10, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(I2C1_SCL, 11, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO37, 11, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM2, 11, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CMD_RSP, 11, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CLK, 11, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_INT_RMII_TXD_1, 11, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(I2C1_SDA, 12, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO38, 12, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM3, 12, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_0, 12, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CSN_0, 12, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_INT_RMII_TXEN, 12, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_TX, 13, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO41, 13, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM4, 13, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_1, 13, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_TXD, 13, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_O_INT_RMII_RXD_0, 13, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_RX, 14, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO42, 14, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM5, 14, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_2, 14, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_RXD, 14, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_O_INT_RMII_RXD_1, 14, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(USB_PWREN, 15, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO47, 15, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_3, 15, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_O_INT_RMII_CRSDV, 15, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM0, 16, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO43, 16, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C2_SCL, 16, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_TX, 16, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_RMII_TXD_0, 16, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM1, 17, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO44, 17, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C2_SDA, 17, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_RX, 17, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_RMII_TXD_1, 17, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM2, 18, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO45, 18, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM3, 19, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO46, 19, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_RMII_CLK, 20, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO48, 20, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CLK, 20, FUNC2, PUPD_NONE, 3); +PINCTRL_FUNC(PWM2, 20, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_REF_CLK, 21, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(MAC_TXD_0, 22, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO49, 22, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 22, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM3, 22, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_TXD_1, 23, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO50, 23, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CMD_RSP, 23, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM4, 23, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_TXEN, 24, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO51, 24, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_0, 24, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM5, 24, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_RXD_0, 25, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO52, 25, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_1, 25, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM6, 25, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_RXD_1, 26, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO53, 26, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_2, 26, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM7, 26, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_RXDV, 27, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO54, 27, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_3, 27, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM8, 27, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_MDC, 28, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO55, 28, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM9, 28, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_MDIO, 29, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO56, 29, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CLK, 30, FUNC0, PUPD_NONE, 3); +PINCTRL_FUNC(GPIO57, 30, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C1_SCL, 30, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 31, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO58, 31, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C1_SDA, 31, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CMD_RSP, 32, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO59, 32, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART1_TX, 32, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_0, 33, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO60, 33, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART1_RX, 33, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_1, 34, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO61, 34, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_TX, 34, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_2, 35, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO62, 35, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_RX, 35, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_3, 36, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO63, 36, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TRSTN, 37, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO0, 37, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_I2S_DO, 37, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(DW_I2S_DO, 37, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SSI1_CLK, 37, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI2_CLK, 37, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_ADDAT, 37, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM6, 37, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_SMI_MDC, 37, FUNC8, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TDO, 38, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO1, 38, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_I2S_DI, 38, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(DW_I2S_DI, 38, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SSI1_CSN_0, 38, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI2_CSN_0, 38, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_DADAT, 38, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM7, 38, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_SMI_MDIO_I, 38, FUNC8, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TDI, 39, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO2, 39, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_I2S_CLK, 39, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(DW_I2S_CLK, 39, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SSI1_TXD, 39, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI2_TXD, 39, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_ADBCLK, 39, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM8, 39, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_SMI_MDIO_O, 39, FUNC8, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TCK, 40, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO3, 40, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_I2S_WS, 40, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(DW_I2S_WS, 40, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SSI1_RXD, 40, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI2_RXD, 40, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_ADLRC, 40, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM9, 40, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_I_INT_SMI_MDIO_I, 40, FUNC8, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TMS, 41, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO4, 41, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_MCLK, 41, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(USB_PWREN, 41, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 41, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_I_INT_SMI_MDC, 41, FUNC5, PUPD_NONE, 0); +PINCTRL_FUNC(SSI0_CLK, 42, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO5, 42, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_CLK, 42, FUNC4, PUPD_NONE, 3); +PINCTRL_FUNC(SSI0_CSN_0, 43, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO6, 43, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_CMD_RSP, 43, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI0_TXD, 44, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO7, 44, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_DATA_0, 44, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI0_RXD, 45, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO8, 45, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_DATA_1, 45, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI0_D2, 46, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO9, 46, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(UART1_TX, 46, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(I2C1_SCL, 46, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_DATA_2, 46, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI0_D3, 47, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO10, 47, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(UART1_RX, 47, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(I2C1_SDA, 47, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_DATA_3, 47, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CLK, 48, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO11, 48, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SSI2_CLK, 48, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CSN_0, 49, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO14, 49, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SSI2_CSN_0, 49, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_TXD, 50, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO15, 50, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SSI2_TXD, 50, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_RXD, 51, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO16, 51, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SSI2_RXD, 51, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_CD, 52, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO17, 52, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(ARC_JTAG_TRSTN, 52, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(PAE_JTAG_TRSTN, 52, FUNC4, PUPD_NONE, 0); +PINCTRL_FUNC(SD0_CLK, 53, FUNC0, PUPD_NONE, 3); +PINCTRL_FUNC(GPIO18, 53, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CLK, 53, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(ARC_JTAG_TDO, 53, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(PAE_JTAG_TDO, 53, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_CMD_RSP, 54, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO19, 54, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_TXD, 54, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(ARC_JTAG_TDI, 54, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(PAE_JTAG_TDI, 54, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_DATA_0, 55, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO20, 55, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_RXD, 55, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(ARC_JTAG_TCK, 55, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(PAE_JTAG_TCK, 55, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_DATA_1, 56, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO21, 56, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CSN_0, 56, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(ARC_JTAG_TMS, 56, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(PAE_JTAG_TMS, 56, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_DATA_2, 57, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO22, 57, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(UART2_TX, 57, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(I2C2_SCL, 57, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_DABCLK, 57, FUNC6, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_DATA_3, 58, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO23, 58, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CSN_0, 58, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(UART2_RX, 58, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(I2C2_SDA, 58, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_DALRC, 58, FUNC6, PUPD_NONE, 2); +PINCTRL_FUNC(SADC_XAIN0, 59, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO26, 59, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SADC_XAIN1, 60, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO27, 60, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SADC_XAIN2, 61, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO24, 61, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SADC_XAIN3, 62, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO25, 62, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO28, 63, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(ETH_LINK_ACT, 63, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(PWM10, 63, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(USB_DBG_CLK, 63, FUNC4, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 63, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_O_INT_RMII_TXEN, 63, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_MDC, 63, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO29, 64, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(ETH_LINK_STA, 64, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(PWM11, 64, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(RTC_CLK, 64, FUNC4, PUPD_NONE, 0); +PINCTRL_FUNC(ETH_LINK_SPD, 64, FUNC5, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_SMI_MDIO_OE, 64, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_MDIO, 64, FUNC7, PUPD_NONE, 0); + + +/* PINCTRL_MUX */ + +PINCTRL_MUX(AC_I2S_CLK, 0, &PAD39_AC_I2S_CLK); +PINCTRL_MUX(AC_I2S_DI, 0, &PAD38_AC_I2S_DI); +PINCTRL_MUX(AC_I2S_DO, 0, &PAD37_AC_I2S_DO); +PINCTRL_MUX(AC_I2S_WS, 0, &PAD40_AC_I2S_WS); +PINCTRL_MUX(AC_MCLK, 0, &PAD41_AC_MCLK); + +PINCTRL_MUX(ARC_JTAG_TCK, 0, &PAD55_ARC_JTAG_TCK); +PINCTRL_MUX(ARC_JTAG_TDI, 0, &PAD54_ARC_JTAG_TDI); +PINCTRL_MUX(ARC_JTAG_TDO, 0, &PAD53_ARC_JTAG_TDO); +PINCTRL_MUX(ARC_JTAG_TMS, 0, &PAD56_ARC_JTAG_TMS); +PINCTRL_MUX(ARC_JTAG_TRSTN, 0, &PAD52_ARC_JTAG_TRSTN); + +PINCTRL_MUX(ARM_JTAG_TCK, 0, &PAD40_ARM_JTAG_TCK); +PINCTRL_MUX(ARM_JTAG_TDI, 0, &PAD39_ARM_JTAG_TDI); +PINCTRL_MUX(ARM_JTAG_TDO, 0, &PAD38_ARM_JTAG_TDO); +PINCTRL_MUX(ARM_JTAG_TMS, 0, &PAD41_ARM_JTAG_TMS); +PINCTRL_MUX(ARM_JTAG_TRSTN, 0, &PAD37_ARM_JTAG_TRSTN); + +PINCTRL_MUX(DW_I2S_CLK, 0, &PAD39_DW_I2S_CLK); +PINCTRL_MUX(DW_I2S_DI, 0, &PAD38_DW_I2S_DI); +PINCTRL_MUX(DW_I2S_DO, 0, &PAD37_DW_I2S_DO); +PINCTRL_MUX(DW_I2S_WS, 0, &PAD40_DW_I2S_WS); + +PINCTRL_MUX(ETH_LINK_ACT, 1, &PAD1_ETH_LINK_ACT, + &PAD63_ETH_LINK_ACT); +PINCTRL_MUX(ETH_LINK_SPD, 1, &PAD2_ETH_LINK_SPD, + &PAD64_ETH_LINK_SPD); +PINCTRL_MUX(ETH_LINK_STA, 1, &PAD2_ETH_LINK_STA, + &PAD64_ETH_LINK_STA); + +PINCTRL_MUX(I2C0_SCL, 0, &PAD5_I2C0_SCL); +PINCTRL_MUX(I2C0_SDA, 0, &PAD6_I2C0_SDA); + +PINCTRL_MUX(I2C1_SCL, 2, &PAD11_I2C1_SCL, &PAD30_I2C1_SCL, &PAD46_I2C1_SCL); +PINCTRL_MUX(I2C1_SDA, 2, &PAD12_I2C1_SDA, &PAD31_I2C1_SDA, &PAD47_I2C1_SDA); + +PINCTRL_MUX(I2C2_SCL, 1, &PAD16_I2C2_SCL, &PAD57_I2C2_SCL); +PINCTRL_MUX(I2C2_SDA, 1, &PAD17_I2C2_SDA, &PAD58_I2C2_SDA); + +PINCTRL_MUX(MAC_MDC, 0, &PAD28_MAC_MDC, &PAD63_MAC_MDC); +PINCTRL_MUX(MAC_MDIO, 0, &PAD29_MAC_MDIO, &PAD64_MAC_MDIO); +PINCTRL_MUX(MAC_REF_CLK, 0, &PAD21_MAC_REF_CLK); +PINCTRL_MUX(MAC_RMII_CLK, 0, &PAD20_MAC_RMII_CLK); +PINCTRL_MUX(MAC_RXDV, 0, &PAD27_MAC_RXDV); +PINCTRL_MUX(MAC_RXD_0, 0, &PAD25_MAC_RXD_0); +PINCTRL_MUX(MAC_RXD_1, 0, &PAD26_MAC_RXD_1); +PINCTRL_MUX(MAC_TXD_0, 0, &PAD22_MAC_TXD_0); +PINCTRL_MUX(MAC_TXD_1, 0, &PAD23_MAC_TXD_1); +PINCTRL_MUX(MAC_TXEN, 0, &PAD24_MAC_TXEN); + +PINCTRL_MUX(PAE_JTAG_TCK, 0, &PAD55_PAE_JTAG_TCK); +PINCTRL_MUX(PAE_JTAG_TDI, 0, &PAD54_PAE_JTAG_TDI); +PINCTRL_MUX(PAE_JTAG_TDO, 0, &PAD53_PAE_JTAG_TDO); +PINCTRL_MUX(PAE_JTAG_TMS, 0, &PAD56_PAE_JTAG_TMS); +PINCTRL_MUX(PAE_JTAG_TRSTN, 0, &PAD52_PAE_JTAG_TRSTN); + +PINCTRL_MUX(PWM0, 0, &PAD16_PWM0); +PINCTRL_MUX(PWM1, 0, &PAD17_PWM1); +PINCTRL_MUX(PWM10, 0, &PAD63_PWM10); +PINCTRL_MUX(PWM11, 0, &PAD64_PWM11); +PINCTRL_MUX(PWM2, 0, &PAD11_PWM2, &PAD18_PWM2, &PAD20_PWM2); +PINCTRL_MUX(PWM3, 0, &PAD12_PWM3, &PAD19_PWM3, &PAD22_PWM3); +PINCTRL_MUX(PWM4, 0, &PAD13_PWM4, &PAD23_PWM4); +PINCTRL_MUX(PWM5, 0, &PAD14_PWM5, &PAD24_PWM5); +PINCTRL_MUX(PWM6, 1, &PAD25_PWM6, &PAD37_PWM6); +PINCTRL_MUX(PWM7, 1, &PAD26_PWM7, &PAD38_PWM7); +PINCTRL_MUX(PWM8, 1, &PAD27_PWM8, &PAD39_PWM8); +PINCTRL_MUX(PWM9, 1, &PAD28_PWM9, &PAD40_PWM9); + +PINCTRL_MUX(RTC_CLK, 0, &PAD64_RTC_CLK); + +PINCTRL_MUX(SADC_XAIN0, 0, &PAD59_SADC_XAIN0); +PINCTRL_MUX(SADC_XAIN1, 0, &PAD60_SADC_XAIN1); +PINCTRL_MUX(SADC_XAIN2, 0, &PAD61_SADC_XAIN2); +PINCTRL_MUX(SADC_XAIN3, 0, &PAD62_SADC_XAIN3); + +PINCTRL_MUX(SD0_CD, 0, &PAD52_SD0_CD); +PINCTRL_MUX(SD0_CLK, 0, &PAD53_SD0_CLK); +PINCTRL_MUX(SD0_CMD_RSP, 0, &PAD54_SD0_CMD_RSP); +PINCTRL_MUX(SD0_DATA_0, 0, &PAD55_SD0_DATA_0); +PINCTRL_MUX(SD0_DATA_1, 0, &PAD56_SD0_DATA_1); +PINCTRL_MUX(SD0_DATA_2, 0, &PAD57_SD0_DATA_2); +PINCTRL_MUX(SD0_DATA_3, 0, &PAD58_SD0_DATA_3); + +PINCTRL_MUX(SD1_CD, 0, &PAD10_SD1_CD, &PAD22_SD1_CD, &PAD31_SD1_CD, + &PAD41_SD1_CD, &PAD63_SD1_CD); +PINCTRL_MUX(SD1_CLK, 0, &PAD9_SD1_CLK, &PAD20_SD1_CLK, &PAD30_SD1_CLK, + &PAD42_SD1_CLK); +PINCTRL_MUX(SD1_CMD_RSP, 0, &PAD11_SD1_CMD_RSP, &PAD23_SD1_CMD_RSP, + &PAD32_SD1_CMD_RSP, &PAD43_SD1_CMD_RSP); +PINCTRL_MUX(SD1_DATA_0, 0, &PAD12_SD1_DATA_0, &PAD24_SD1_DATA_0, + &PAD33_SD1_DATA_0, &PAD44_SD1_DATA_0); +PINCTRL_MUX(SD1_DATA_1, 0, &PAD13_SD1_DATA_1, &PAD25_SD1_DATA_1, + &PAD34_SD1_DATA_1, &PAD45_SD1_DATA_1); +PINCTRL_MUX(SD1_DATA_2, 0, &PAD14_SD1_DATA_2, &PAD26_SD1_DATA_2, + &PAD35_SD1_DATA_2, &PAD46_SD1_DATA_2); +PINCTRL_MUX(SD1_DATA_3, 0, &PAD15_SD1_DATA_3, &PAD27_SD1_DATA_3, + &PAD36_SD1_DATA_3, &PAD47_SD1_DATA_3); + +PINCTRL_MUX(SENSOR_CLK, 0, &PAD7_SENSOR_CLK); + +PINCTRL_MUX(SSI0_CLK, 0, &PAD42_SSI0_CLK); +PINCTRL_MUX(SSI0_D2, 0, &PAD46_SSI0_D2); +PINCTRL_MUX(SSI0_D3, 0, &PAD47_SSI0_D3); +PINCTRL_MUX(SSI0_RXD, 0, &PAD45_SSI0_RXD); +PINCTRL_MUX(SSI0_TXD, 0, &PAD44_SSI0_TXD); + +PINCTRL_MUX(SSI1_CLK, 2, &PAD11_SSI1_CLK, &PAD37_SSI1_CLK, &PAD48_SSI1_CLK, + &PAD53_SSI1_CLK); +PINCTRL_MUX(SSI1_RXD, 2, &PAD14_SSI1_RXD, &PAD40_SSI1_RXD, &PAD51_SSI1_RXD, + &PAD55_SSI1_RXD); +PINCTRL_MUX(SSI1_TXD, 2, &PAD13_SSI1_TXD, &PAD39_SSI1_TXD, &PAD50_SSI1_TXD, + &PAD54_SSI1_TXD); + +PINCTRL_MUX(SSI2_CLK, 1, &PAD37_SSI2_CLK, &PAD48_SSI2_CLK); +PINCTRL_MUX(SSI2_CSN_0, 1, &PAD38_SSI2_CSN_0, &PAD49_SSI2_CSN_0); +PINCTRL_MUX(SSI2_RXD, 1, &PAD40_SSI2_RXD, &PAD51_SSI2_RXD); +PINCTRL_MUX(SSI2_TXD, 1, &PAD39_SSI2_TXD, &PAD50_SSI2_TXD); + +PINCTRL_MUX(UART0_RX, 0, &PAD4_UART0_RX); +PINCTRL_MUX(UART0_TX, 0, &PAD3_UART0_TX); + +PINCTRL_MUX(UART1_RX, 0, &PAD10_UART1_RX, &PAD33_UART1_RX, &PAD47_UART1_RX); +PINCTRL_MUX(UART1_TX, 0, &PAD9_UART1_TX, &PAD32_UART1_TX, &PAD46_UART1_TX); + +PINCTRL_MUX(UART2_RX, 0, &PAD14_UART2_RX, &PAD17_UART2_RX, &PAD35_UART2_RX, + &PAD58_UART2_RX); +PINCTRL_MUX(UART2_TX, 0, &PAD13_UART2_TX, &PAD16_UART2_TX, &PAD34_UART2_TX, + &PAD57_UART2_TX); + +PINCTRL_MUX(USB_PWREN, 0, &PAD15_USB_PWREN, &PAD41_USB_PWREN); + +PINCTRL_MUX(GPIO0, 0, &PAD37_GPIO0); +PINCTRL_MUX(GPIO1, 0, &PAD38_GPIO1); +PINCTRL_MUX(GPIO2, 0, &PAD39_GPIO2); +PINCTRL_MUX(GPIO3, 0, &PAD40_GPIO3); +PINCTRL_MUX(GPIO4, 0, &PAD41_GPIO4); +PINCTRL_MUX(GPIO5, 0, &PAD42_GPIO5); +PINCTRL_MUX(GPIO6, 0, &PAD43_GPIO6); +PINCTRL_MUX(GPIO7, 0, &PAD44_GPIO7); +PINCTRL_MUX(GPIO8, 0, &PAD45_GPIO8); +PINCTRL_MUX(GPIO9, 0, &PAD46_GPIO9); +PINCTRL_MUX(GPIO10, 0, &PAD47_GPIO10); +PINCTRL_MUX(GPIO11, 0, &PAD48_GPIO11); +PINCTRL_MUX(GPIO12, 0, &PAD7_GPIO12); +PINCTRL_MUX(GPIO13, 0, &PAD8_GPIO13); +PINCTRL_MUX(GPIO14, 0, &PAD49_GPIO14); +PINCTRL_MUX(GPIO15, 0, &PAD50_GPIO15); +PINCTRL_MUX(GPIO16, 0, &PAD51_GPIO16); +PINCTRL_MUX(GPIO17, 0, &PAD52_GPIO17); +PINCTRL_MUX(GPIO18, 0, &PAD53_GPIO18); +PINCTRL_MUX(GPIO19, 0, &PAD54_GPIO19); +PINCTRL_MUX(GPIO20, 0, &PAD55_GPIO20); +PINCTRL_MUX(GPIO21, 0, &PAD56_GPIO21); +PINCTRL_MUX(GPIO22, 0, &PAD57_GPIO22); +PINCTRL_MUX(GPIO23, 0, &PAD58_GPIO23); +PINCTRL_MUX(GPIO24, 0, &PAD61_GPIO24); +PINCTRL_MUX(GPIO25, 0, &PAD62_GPIO25); +PINCTRL_MUX(GPIO26, 0, &PAD59_GPIO26); +PINCTRL_MUX(GPIO27, 0, &PAD60_GPIO27); +PINCTRL_MUX(GPIO28, 0, &PAD63_GPIO28); +PINCTRL_MUX(GPIO29, 0, &PAD64_GPIO29); +PINCTRL_MUX(GPIO30, 0, &PAD0_GPIO30); +PINCTRL_MUX(GPIO31, 0, &PAD1_GPIO31); +PINCTRL_MUX(GPIO32, 0, &PAD2_GPIO32); +PINCTRL_MUX(GPIO33, 0, &PAD3_GPIO33); +PINCTRL_MUX(GPIO34, 0, &PAD4_GPIO34); +PINCTRL_MUX(GPIO35, 0, &PAD5_GPIO35); +PINCTRL_MUX(GPIO36, 0, &PAD6_GPIO36); +PINCTRL_MUX(GPIO37, 0, &PAD11_GPIO37); +PINCTRL_MUX(GPIO38, 0, &PAD12_GPIO38); +PINCTRL_MUX(GPIO39, 0, &PAD9_GPIO39); +PINCTRL_MUX(GPIO40, 0, &PAD10_GPIO40); +PINCTRL_MUX(GPIO41, 0, &PAD13_GPIO41); +PINCTRL_MUX(GPIO42, 0, &PAD14_GPIO42); +PINCTRL_MUX(GPIO43, 0, &PAD16_GPIO43); +PINCTRL_MUX(GPIO44, 0, &PAD17_GPIO44); +PINCTRL_MUX(GPIO45, 0, &PAD18_GPIO45); +PINCTRL_MUX(GPIO46, 0, &PAD19_GPIO46); +PINCTRL_MUX(GPIO47, 0, &PAD15_GPIO47); +PINCTRL_MUX(GPIO48, 0, &PAD20_GPIO48); +PINCTRL_MUX(GPIO49, 0, &PAD22_GPIO49); +PINCTRL_MUX(GPIO50, 0, &PAD23_GPIO50); +PINCTRL_MUX(GPIO51, 0, &PAD24_GPIO51); +PINCTRL_MUX(GPIO52, 0, &PAD25_GPIO52); +PINCTRL_MUX(GPIO53, 0, &PAD26_GPIO53); +PINCTRL_MUX(GPIO54, 0, &PAD27_GPIO54); +PINCTRL_MUX(GPIO55, 0, &PAD28_GPIO55); +PINCTRL_MUX(GPIO56, 0, &PAD29_GPIO56); +PINCTRL_MUX(GPIO57, 0, &PAD30_GPIO57); +PINCTRL_MUX(GPIO58, 0, &PAD31_GPIO58); +PINCTRL_MUX(GPIO59, 0, &PAD32_GPIO59); +PINCTRL_MUX(GPIO60, 0, &PAD33_GPIO60); +PINCTRL_MUX(GPIO61, 0, &PAD34_GPIO61); +PINCTRL_MUX(GPIO62, 0, &PAD35_GPIO62); +PINCTRL_MUX(GPIO63, 0, &PAD36_GPIO63); + +PINCTRL_MUX(SD1_CLK_EMMC, 3, &PAD9_SD1_CLK, &PAD20_SD1_CLK, &PAD30_SD1_CLK, + &PAD42_SD1_CLK); +PINCTRL_MUX(SD1_CMD_RSP_EMMC, 3, &PAD11_SD1_CMD_RSP, &PAD23_SD1_CMD_RSP, + &PAD32_SD1_CMD_RSP, &PAD43_SD1_CMD_RSP); +PINCTRL_MUX(SD1_DATA_0_EMMC, 3, &PAD12_SD1_DATA_0, &PAD24_SD1_DATA_0, + &PAD33_SD1_DATA_0, &PAD44_SD1_DATA_0); +PINCTRL_MUX(SD1_DATA_1_EMMC, 3, &PAD13_SD1_DATA_1, &PAD25_SD1_DATA_1, + &PAD34_SD1_DATA_1, &PAD45_SD1_DATA_1); +PINCTRL_MUX(SD1_DATA_2_EMMC, 3, &PAD14_SD1_DATA_2, &PAD26_SD1_DATA_2, + &PAD35_SD1_DATA_2, &PAD46_SD1_DATA_2); +PINCTRL_MUX(SD1_DATA_3_EMMC, 3, &PAD15_SD1_DATA_3, &PAD27_SD1_DATA_3, + &PAD36_SD1_DATA_3, &PAD47_SD1_DATA_3); + +/* PINCTRL_DEVICE */ +PINCTRL_DEVICE(ACI2S, 5, &MUX_AC_I2S_CLK, &MUX_AC_I2S_DI, &MUX_AC_I2S_DO, + &MUX_AC_I2S_WS, &MUX_AC_MCLK); +PINCTRL_DEVICE(AC_MCLK, 1, &MUX_AC_MCLK); +PINCTRL_DEVICE(ARCJTAG, 5, &MUX_ARC_JTAG_TCK, &MUX_ARC_JTAG_TDI, + &MUX_ARC_JTAG_TDO, &MUX_ARC_JTAG_TMS, &MUX_ARC_JTAG_TRSTN); +PINCTRL_DEVICE(ARMJTAG, 5, &MUX_ARM_JTAG_TCK, &MUX_ARM_JTAG_TDI, + &MUX_ARM_JTAG_TDO, &MUX_ARM_JTAG_TMS, &MUX_ARM_JTAG_TRSTN); +PINCTRL_DEVICE(DWI2S, 4, &MUX_DW_I2S_CLK, &MUX_DW_I2S_DI, &MUX_DW_I2S_DO, + &MUX_DW_I2S_WS); +PINCTRL_DEVICE(ETH, 2, &MUX_ETH_LINK_ACT, &MUX_ETH_LINK_STA); +PINCTRL_DEVICE(I2C0, 2, &MUX_I2C0_SCL, &MUX_I2C0_SDA); +PINCTRL_DEVICE(I2C1, 2, &MUX_I2C1_SCL, &MUX_I2C1_SDA); +PINCTRL_DEVICE(I2C2, 2, &MUX_I2C2_SCL, &MUX_I2C2_SDA); +PINCTRL_DEVICE(PAEJTAG, 5, &MUX_PAE_JTAG_TCK, &MUX_PAE_JTAG_TDI, + &MUX_PAE_JTAG_TDO, &MUX_PAE_JTAG_TMS, &MUX_PAE_JTAG_TRSTN); +PINCTRL_DEVICE(PWM0, 1, &MUX_PWM0); +PINCTRL_DEVICE(PWM1, 1, &MUX_PWM1); +PINCTRL_DEVICE(PWM10, 1, &MUX_PWM10); +PINCTRL_DEVICE(PWM11, 1, &MUX_PWM11); +PINCTRL_DEVICE(PWM2, 1, &MUX_PWM2); +PINCTRL_DEVICE(PWM3, 1, &MUX_PWM3); +PINCTRL_DEVICE(PWM4, 1, &MUX_PWM4); +PINCTRL_DEVICE(PWM5, 1, &MUX_PWM5); +PINCTRL_DEVICE(PWM6, 1, &MUX_PWM6); +PINCTRL_DEVICE(PWM7, 1, &MUX_PWM7); +PINCTRL_DEVICE(PWM8, 1, &MUX_PWM8); +PINCTRL_DEVICE(PWM9, 1, &MUX_PWM9); +PINCTRL_DEVICE(RMII, 10, &MUX_MAC_MDC, &MUX_MAC_MDIO, &MUX_MAC_REF_CLK, + &MUX_MAC_RMII_CLK, &MUX_MAC_RXDV, &MUX_MAC_RXD_0, &MUX_MAC_RXD_1, + &MUX_MAC_TXD_0, &MUX_MAC_TXD_1, &MUX_MAC_TXEN); +PINCTRL_DEVICE(RTC, 1, &MUX_RTC_CLK); +PINCTRL_DEVICE(SADC_XAIN0, 1, &MUX_SADC_XAIN0); +PINCTRL_DEVICE(SADC_XAIN1, 1, &MUX_SADC_XAIN1); +PINCTRL_DEVICE(SADC_XAIN2, 1, &MUX_SADC_XAIN2); +PINCTRL_DEVICE(SADC_XAIN3, 1, &MUX_SADC_XAIN3); +PINCTRL_DEVICE(SD0, 7, &MUX_SD0_CD, &MUX_SD0_CLK, &MUX_SD0_CMD_RSP, + &MUX_SD0_DATA_0, &MUX_SD0_DATA_1, &MUX_SD0_DATA_2, &MUX_SD0_DATA_3); +PINCTRL_DEVICE(SD0_1BIT_NO_WP, 4, &MUX_SD0_CD, &MUX_SD0_CLK, &MUX_SD0_CMD_RSP, + &MUX_SD0_DATA_0); +PINCTRL_DEVICE(SD0_NO_WP, 7, &MUX_SD0_CD, &MUX_SD0_CLK, &MUX_SD0_CMD_RSP, + &MUX_SD0_DATA_0, &MUX_SD0_DATA_1, &MUX_SD0_DATA_2, &MUX_SD0_DATA_3); +PINCTRL_DEVICE(SD0_WIFI, 6, &MUX_SD0_CLK, &MUX_SD0_CMD_RSP, &MUX_SD0_DATA_0, + &MUX_SD0_DATA_1, &MUX_SD0_DATA_2, &MUX_SD0_DATA_3); +PINCTRL_DEVICE(SD1, 7, &MUX_SD1_CD, &MUX_SD1_CLK, &MUX_SD1_CMD_RSP, + &MUX_SD1_DATA_0, &MUX_SD1_DATA_1, &MUX_SD1_DATA_2, &MUX_SD1_DATA_3); +PINCTRL_DEVICE(SD1_1BIT_NO_WP, 4, &MUX_SD1_CD, &MUX_SD1_CLK, &MUX_SD1_CMD_RSP, + &MUX_SD1_DATA_0); +PINCTRL_DEVICE(SD1_NO_WP, 7, &MUX_SD1_CD, &MUX_SD1_CLK, &MUX_SD1_CMD_RSP, + &MUX_SD1_DATA_0, &MUX_SD1_DATA_1, &MUX_SD1_DATA_2, &MUX_SD1_DATA_3); +PINCTRL_DEVICE(SD1_WIFI, 6, &MUX_SD1_CLK, &MUX_SD1_CMD_RSP, &MUX_SD1_DATA_0, + &MUX_SD1_DATA_1, &MUX_SD1_DATA_2, &MUX_SD1_DATA_3); +PINCTRL_DEVICE(SENSOR_CLK, 1, &MUX_SENSOR_CLK); +PINCTRL_DEVICE(SSI0, 4, &MUX_GPIO6, &MUX_SSI0_CLK, &MUX_SSI0_RXD, + &MUX_SSI0_TXD); +PINCTRL_DEVICE(SSI0_4BIT, 6, &MUX_GPIO6, &MUX_SSI0_CLK, &MUX_SSI0_D2, + &MUX_SSI0_D3, &MUX_SSI0_RXD, &MUX_SSI0_TXD); +PINCTRL_DEVICE(SSI1, 4, &MUX_GPIO14, &MUX_SSI1_CLK, &MUX_SSI1_RXD, + &MUX_SSI1_TXD); +PINCTRL_DEVICE(SSI2, 4, &MUX_SSI2_CLK, &MUX_SSI2_CSN_0, &MUX_SSI2_RXD, + &MUX_SSI2_TXD); +PINCTRL_DEVICE(UART0, 2, &MUX_UART0_RX, &MUX_UART0_TX); +PINCTRL_DEVICE(UART1, 2, &MUX_UART1_RX, &MUX_UART1_TX); +PINCTRL_DEVICE(UART2, 2, &MUX_UART2_RX, &MUX_UART2_TX); +PINCTRL_DEVICE(USB, 1, &MUX_USB_PWREN); +PINCTRL_DEVICE(GPIO0, 1, &MUX_GPIO0); +PINCTRL_DEVICE(GPIO1, 1, &MUX_GPIO1); +PINCTRL_DEVICE(GPIO2, 1, &MUX_GPIO2); +PINCTRL_DEVICE(GPIO3, 1, &MUX_GPIO3); +PINCTRL_DEVICE(GPIO4, 1, &MUX_GPIO4); +PINCTRL_DEVICE(GPIO5, 1, &MUX_GPIO5); +PINCTRL_DEVICE(GPIO6, 1, &MUX_GPIO6); +PINCTRL_DEVICE(GPIO7, 1, &MUX_GPIO7); +PINCTRL_DEVICE(GPIO8, 1, &MUX_GPIO8); +PINCTRL_DEVICE(GPIO9, 1, &MUX_GPIO9); +PINCTRL_DEVICE(GPIO10, 1, &MUX_GPIO10); +PINCTRL_DEVICE(GPIO11, 1, &MUX_GPIO11); +PINCTRL_DEVICE(GPIO12, 1, &MUX_GPIO12); +PINCTRL_DEVICE(GPIO13, 1, &MUX_GPIO13); +PINCTRL_DEVICE(GPIO14, 1, &MUX_GPIO14); +PINCTRL_DEVICE(GPIO15, 1, &MUX_GPIO15); +PINCTRL_DEVICE(GPIO16, 1, &MUX_GPIO16); +PINCTRL_DEVICE(GPIO17, 1, &MUX_GPIO17); +PINCTRL_DEVICE(GPIO18, 1, &MUX_GPIO18); +PINCTRL_DEVICE(GPIO19, 1, &MUX_GPIO19); +PINCTRL_DEVICE(GPIO20, 1, &MUX_GPIO20); +PINCTRL_DEVICE(GPIO21, 1, &MUX_GPIO21); +PINCTRL_DEVICE(GPIO22, 1, &MUX_GPIO22); +PINCTRL_DEVICE(GPIO23, 1, &MUX_GPIO23); +PINCTRL_DEVICE(GPIO24, 1, &MUX_GPIO24); +PINCTRL_DEVICE(GPIO25, 1, &MUX_GPIO25); +PINCTRL_DEVICE(GPIO26, 1, &MUX_GPIO26); +PINCTRL_DEVICE(GPIO27, 1, &MUX_GPIO27); +PINCTRL_DEVICE(GPIO28, 1, &MUX_GPIO28); +PINCTRL_DEVICE(GPIO29, 1, &MUX_GPIO29); +PINCTRL_DEVICE(GPIO30, 1, &MUX_GPIO30); +PINCTRL_DEVICE(GPIO31, 1, &MUX_GPIO31); +PINCTRL_DEVICE(GPIO32, 1, &MUX_GPIO32); +PINCTRL_DEVICE(GPIO33, 1, &MUX_GPIO33); +PINCTRL_DEVICE(GPIO34, 1, &MUX_GPIO34); +PINCTRL_DEVICE(GPIO35, 1, &MUX_GPIO35); +PINCTRL_DEVICE(GPIO36, 1, &MUX_GPIO36); +PINCTRL_DEVICE(GPIO37, 1, &MUX_GPIO37); +PINCTRL_DEVICE(GPIO38, 1, &MUX_GPIO38); +PINCTRL_DEVICE(GPIO39, 1, &MUX_GPIO39); +PINCTRL_DEVICE(GPIO40, 1, &MUX_GPIO40); +PINCTRL_DEVICE(GPIO41, 1, &MUX_GPIO41); +PINCTRL_DEVICE(GPIO42, 1, &MUX_GPIO42); +PINCTRL_DEVICE(GPIO43, 1, &MUX_GPIO43); +PINCTRL_DEVICE(GPIO44, 1, &MUX_GPIO44); +PINCTRL_DEVICE(GPIO45, 1, &MUX_GPIO45); +PINCTRL_DEVICE(GPIO46, 1, &MUX_GPIO46); +PINCTRL_DEVICE(GPIO47, 1, &MUX_GPIO47); +PINCTRL_DEVICE(GPIO48, 1, &MUX_GPIO48); +PINCTRL_DEVICE(GPIO49, 1, &MUX_GPIO49); +PINCTRL_DEVICE(GPIO50, 1, &MUX_GPIO50); +PINCTRL_DEVICE(GPIO51, 1, &MUX_GPIO51); +PINCTRL_DEVICE(GPIO52, 1, &MUX_GPIO52); +PINCTRL_DEVICE(GPIO53, 1, &MUX_GPIO53); +PINCTRL_DEVICE(GPIO54, 1, &MUX_GPIO54); +PINCTRL_DEVICE(GPIO55, 1, &MUX_GPIO55); +PINCTRL_DEVICE(GPIO56, 1, &MUX_GPIO56); +PINCTRL_DEVICE(GPIO57, 1, &MUX_GPIO57); +PINCTRL_DEVICE(GPIO58, 1, &MUX_GPIO58); +PINCTRL_DEVICE(GPIO59, 1, &MUX_GPIO59); +PINCTRL_DEVICE(GPIO60, 1, &MUX_GPIO60); +PINCTRL_DEVICE(GPIO61, 1, &MUX_GPIO61); +PINCTRL_DEVICE(GPIO62, 1, &MUX_GPIO62); +PINCTRL_DEVICE(GPIO63, 1, &MUX_GPIO63); + +PINCTRL_DEVICE(SD1_EMMC, 6, &MUX_SD1_CLK_EMMC, &MUX_SD1_CMD_RSP_EMMC, + &MUX_SD1_DATA_0_EMMC, &MUX_SD1_DATA_1_EMMC, &MUX_SD1_DATA_2_EMMC, + &MUX_SD1_DATA_3_EMMC); + +void fh_pinctrl_init_devicelist(OS_LIST *list) +{ + OS_LIST_EMPTY(list); + + /*PINCTRL_ADD_DEVICE*/ + PINCTRL_ADD_DEVICE(ACI2S); + PINCTRL_ADD_DEVICE(AC_MCLK); + PINCTRL_ADD_DEVICE(ARCJTAG); + PINCTRL_ADD_DEVICE(ARMJTAG); + PINCTRL_ADD_DEVICE(DWI2S); + PINCTRL_ADD_DEVICE(ETH); + PINCTRL_ADD_DEVICE(I2C0); + PINCTRL_ADD_DEVICE(I2C1); + PINCTRL_ADD_DEVICE(I2C2); + PINCTRL_ADD_DEVICE(PAEJTAG); + PINCTRL_ADD_DEVICE(PWM0); + PINCTRL_ADD_DEVICE(PWM1); + PINCTRL_ADD_DEVICE(PWM10); + PINCTRL_ADD_DEVICE(PWM11); + PINCTRL_ADD_DEVICE(PWM2); + PINCTRL_ADD_DEVICE(PWM3); + PINCTRL_ADD_DEVICE(PWM4); + PINCTRL_ADD_DEVICE(PWM5); + PINCTRL_ADD_DEVICE(PWM6); + PINCTRL_ADD_DEVICE(PWM7); + PINCTRL_ADD_DEVICE(PWM8); + PINCTRL_ADD_DEVICE(PWM9); + PINCTRL_ADD_DEVICE(RMII); + PINCTRL_ADD_DEVICE(RTC); + PINCTRL_ADD_DEVICE(SADC_XAIN0); + PINCTRL_ADD_DEVICE(SADC_XAIN1); + PINCTRL_ADD_DEVICE(SADC_XAIN2); + PINCTRL_ADD_DEVICE(SADC_XAIN3); + PINCTRL_ADD_DEVICE(SD0); + PINCTRL_ADD_DEVICE(SD0_1BIT_NO_WP); + PINCTRL_ADD_DEVICE(SD0_NO_WP); + PINCTRL_ADD_DEVICE(SD0_WIFI); + PINCTRL_ADD_DEVICE(SD1); + PINCTRL_ADD_DEVICE(SD1_1BIT_NO_WP); + PINCTRL_ADD_DEVICE(SD1_NO_WP); + PINCTRL_ADD_DEVICE(SD1_WIFI); + PINCTRL_ADD_DEVICE(SENSOR_CLK); + PINCTRL_ADD_DEVICE(SSI0); + PINCTRL_ADD_DEVICE(SSI0_4BIT); + PINCTRL_ADD_DEVICE(SSI1); + PINCTRL_ADD_DEVICE(SSI2); + PINCTRL_ADD_DEVICE(UART0); + PINCTRL_ADD_DEVICE(UART1); + PINCTRL_ADD_DEVICE(UART2); + PINCTRL_ADD_DEVICE(USB); + PINCTRL_ADD_DEVICE(GPIO0); + PINCTRL_ADD_DEVICE(GPIO1); + PINCTRL_ADD_DEVICE(GPIO2); + PINCTRL_ADD_DEVICE(GPIO3); + PINCTRL_ADD_DEVICE(GPIO4); + PINCTRL_ADD_DEVICE(GPIO5); + PINCTRL_ADD_DEVICE(GPIO6); + PINCTRL_ADD_DEVICE(GPIO7); + PINCTRL_ADD_DEVICE(GPIO8); + PINCTRL_ADD_DEVICE(GPIO9); + PINCTRL_ADD_DEVICE(GPIO10); + PINCTRL_ADD_DEVICE(GPIO11); + PINCTRL_ADD_DEVICE(GPIO12); + PINCTRL_ADD_DEVICE(GPIO13); + PINCTRL_ADD_DEVICE(GPIO14); + PINCTRL_ADD_DEVICE(GPIO15); + PINCTRL_ADD_DEVICE(GPIO16); + PINCTRL_ADD_DEVICE(GPIO17); + PINCTRL_ADD_DEVICE(GPIO18); + PINCTRL_ADD_DEVICE(GPIO19); + PINCTRL_ADD_DEVICE(GPIO20); + PINCTRL_ADD_DEVICE(GPIO21); + PINCTRL_ADD_DEVICE(GPIO22); + PINCTRL_ADD_DEVICE(GPIO23); + PINCTRL_ADD_DEVICE(GPIO24); + PINCTRL_ADD_DEVICE(GPIO25); + PINCTRL_ADD_DEVICE(GPIO26); + PINCTRL_ADD_DEVICE(GPIO27); + PINCTRL_ADD_DEVICE(GPIO28); + PINCTRL_ADD_DEVICE(GPIO29); + PINCTRL_ADD_DEVICE(GPIO30); + PINCTRL_ADD_DEVICE(GPIO31); + PINCTRL_ADD_DEVICE(GPIO32); + PINCTRL_ADD_DEVICE(GPIO33); + PINCTRL_ADD_DEVICE(GPIO34); + PINCTRL_ADD_DEVICE(GPIO35); + PINCTRL_ADD_DEVICE(GPIO36); + PINCTRL_ADD_DEVICE(GPIO37); + PINCTRL_ADD_DEVICE(GPIO38); + PINCTRL_ADD_DEVICE(GPIO39); + PINCTRL_ADD_DEVICE(GPIO40); + PINCTRL_ADD_DEVICE(GPIO41); + PINCTRL_ADD_DEVICE(GPIO42); + PINCTRL_ADD_DEVICE(GPIO43); + PINCTRL_ADD_DEVICE(GPIO44); + PINCTRL_ADD_DEVICE(GPIO45); + PINCTRL_ADD_DEVICE(GPIO46); + PINCTRL_ADD_DEVICE(GPIO47); + PINCTRL_ADD_DEVICE(GPIO48); + PINCTRL_ADD_DEVICE(GPIO49); + PINCTRL_ADD_DEVICE(GPIO50); + PINCTRL_ADD_DEVICE(GPIO51); + PINCTRL_ADD_DEVICE(GPIO52); + PINCTRL_ADD_DEVICE(GPIO53); + PINCTRL_ADD_DEVICE(GPIO54); + PINCTRL_ADD_DEVICE(GPIO55); + PINCTRL_ADD_DEVICE(GPIO56); + PINCTRL_ADD_DEVICE(GPIO57); + PINCTRL_ADD_DEVICE(GPIO58); + PINCTRL_ADD_DEVICE(GPIO59); + PINCTRL_ADD_DEVICE(GPIO60); + PINCTRL_ADD_DEVICE(GPIO61); + PINCTRL_ADD_DEVICE(GPIO62); + PINCTRL_ADD_DEVICE(GPIO63); + + PINCTRL_ADD_DEVICE(SD1_EMMC); +} + +char *fh_pinctrl_selected_devices[] = +{ + CONFIG_PINCTRL_SELECT +}; diff --git a/arch/arm/mach-fh/fh8856v210/Makefile b/arch/arm/mach-fh/fh8856v210/Makefile new file mode 100644 index 00000000..1443fdae --- /dev/null +++ b/arch/arm/mach-fh/fh8856v210/Makefile @@ -0,0 +1 @@ +obj-y += board.o chip.o \ No newline at end of file diff --git a/arch/arm/mach-fh/fh8856v210/board.c b/arch/arm/mach-fh/fh8856v210/board.c new file mode 100644 index 00000000..9fc938c1 --- /dev/null +++ b/arch/arm/mach-fh/fh8856v210/board.c @@ -0,0 +1,1165 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +struct uart_port fh_serial_ports[FH_UART_NUMBER]; + +static struct map_desc fh8856v210_io_desc[] = { + { + .virtual = VA_RAM_REG_BASE, + .pfn = __phys_to_pfn(RAM_BASE), + .length = SZ_16K, + .type = MT_MEMORY_RWX, + }, + { + .virtual = VA_DDRC_REG_BASE, + .pfn = __phys_to_pfn(DDRC_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_INTC_REG_BASE, + .pfn = __phys_to_pfn(INTC_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_TIMER_REG_BASE, + .pfn = __phys_to_pfn(TIMER_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_PMU_REG_BASE, + .pfn = __phys_to_pfn(PMU_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_UART0_REG_BASE, + .pfn = __phys_to_pfn(UART0_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_UART1_REG_BASE, + .pfn = __phys_to_pfn(UART1_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_UART2_REG_BASE, + .pfn = __phys_to_pfn(UART2_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + +}; + +static struct resource fh_gpio0_resources[] = { + { + .start = GPIO0_REG_BASE, + .end = GPIO0_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = GPIO0_IRQ, + .end = GPIO0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_gpio1_resources[] = { + { + .start = GPIO1_REG_BASE, + .end = GPIO1_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = GPIO1_IRQ, + .end = GPIO1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_uart0_resources[] = { + { + .start = (UART0_REG_BASE), + .end = (UART0_REG_BASE) + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = UART0_IRQ, + .end = UART0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_uart1_resources[] = { + { + .start = (UART1_REG_BASE), + .end = (UART1_REG_BASE) + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = UART1_IRQ, + .end = UART1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_uart2_resources[] = { + { + .start = (UART2_REG_BASE), + .end = (UART2_REG_BASE) + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = UART2_IRQ, + .end = UART2_IRQ, + .flags = IORESOURCE_IRQ, + } +}; +static struct resource fh_sdc0_resources[] = { + { + .start = SDC0_REG_BASE, + .end = SDC0_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SDC0_IRQ, + .end = SDC0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_sdc1_resources[] = { + { + .start = SDC1_REG_BASE, + .end = SDC1_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SDC1_IRQ, + .end = SDC1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_gmac_resources[] = { + { + .start = GMAC_REG_BASE, + .end = GMAC_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = GMAC_IRQ, + .end = GMAC_IRQ, + .flags = IORESOURCE_IRQ, + } +}; + +static struct resource fh_wdt_resources[] = { + { + .start = WDT_REG_BASE, + .end = WDT_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = WDT_IRQ, + .end = WDT_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +#ifdef CONFIG_FH_PERF_MON +static struct resource fh_perf_resources[] = { + { + .start = PMU_REG_BASE, + .end = PMU_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = PERF_IRQ, + .end = PERF_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +#endif + + +static struct fh_gmac_platform_data fh_gmac_data = { + .phy_reset_pin = 29, +}; + +static struct fh_uart_dma uart1_dma_info = { +#ifdef CONFIG_UART_TX_DMA + .tx_hs_no = UART1_TX_HW_HANDSHAKE, + .tx_dma_channel = UART1_DMA_TX_CHAN, +#endif + .rx_hs_no = UART1_RX_HW_HANDSHAKE, + .rx_dma_channel = UART1_DMA_RX_CHAN, + .rx_xmit_len = 16, +}; + +static struct fh_uart_dma uart2_dma_info = { +#ifdef CONFIG_UART_TX_DMA + .tx_hs_no = UART2_TX_HW_HANDSHAKE, + .tx_dma_channel = UART2_DMA_TX_CHAN, +#endif + .rx_hs_no = UART2_RX_HW_HANDSHAKE, + .rx_dma_channel = UART2_DMA_RX_CHAN, + .rx_xmit_len = 16, +}; + + +static struct fh_platform_uart fh_uart_platform_data[] = { + { + .mapbase = UART0_REG_BASE, + .fifo_size = 16, + .irq = UART0_IRQ, + .uartclk = 16666667, + .use_dma = 0, + .dma_info = NULL, + }, + { + .mapbase = UART1_REG_BASE, + .fifo_size = 32, + .irq = UART1_IRQ, + .uartclk = 16666667, + .use_dma = 0, + .dma_info = &uart1_dma_info, + }, + { + .mapbase = UART2_REG_BASE, + .fifo_size = 32, + .irq = UART2_IRQ, + .uartclk = 16666667, + .use_dma = 0, + .dma_info = &uart2_dma_info, + }, +}; + +static struct resource fh_pwm_resources[] = { + { + .start = PWM_REG_BASE, + .end = PWM_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = PWM_IRQ, + .end = PWM_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_i2c_resources_0[] = { + { + .start = I2C0_REG_BASE, + .end = I2C0_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = I2C0_IRQ, + .end = I2C0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_i2c_resources_1[] = { + { + .start = I2C1_REG_BASE, + .end = I2C1_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = I2C1_IRQ, + .end = I2C1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_i2c_resources_2[] = { + { + .start = I2C2_REG_BASE, + .end = I2C2_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = I2C2_IRQ, + .end = I2C2_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_rtc_resources[] = { + { + .start = RTC_REG_BASE, + .end = RTC_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = RTC_IRQ, + .end = RTC_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct fh_gpio_chip fh_gpio0_chip = { + .chip = { + .owner = THIS_MODULE, + .label = "FH_GPIO0", + .base = 0, + .ngpio = 32, + }, +}; + +static struct fh_gpio_chip fh_gpio1_chip = { + .chip = { + .owner = THIS_MODULE, + .label = "FH_GPIO1", + .base = 32, + .ngpio = 32, + }, +}; + +static struct fh_pwm_data pwm_data = { + .npwm = 12, +}; + +static struct resource fh_sadc_resources[] = { + { + .start = SADC_REG_BASE, + .end = SADC_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SADC_IRQ, + .end = SADC_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_aes_resources[] = { + { + .start = AES_REG_BASE, + .end = AES_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = AES_IRQ, + .end = AES_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_efuse_resources[] = { + { + .start = EFUSE_REG_BASE, + .end = EFUSE_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +#ifdef CONFIG_FH_DMAC +static struct resource fh_dma_resources[] = { + { + .start = (DMAC_REG_BASE), + .end = (DMAC_REG_BASE) + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = DMAC0_IRQ, + .end = DMAC0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +#endif + +#ifdef CONFIG_FH_AXI_DMAC +static struct resource fh_axi_dma_resources[] = { + { + .start = (DMAC_REG_BASE), + .end = (DMAC_REG_BASE) + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = DMAC0_IRQ, + .end = DMAC0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +#endif + +static struct resource fh_spi0_resources[] = { + { + .start = SPI0_REG_BASE, + .end = SPI0_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SPI0_IRQ, + .end = SPI0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_spi1_resources[] = { + { + .start = SPI1_REG_BASE, + .end = SPI1_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SPI1_IRQ, + .end = SPI1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_spi2_resources[] = { + { + .start = SPI2_REG_BASE, + .end = SPI2_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + .name = "fh spi2 mem", + }, + { + .start = SPI2_IRQ, + .end = SPI2_IRQ, + .flags = IORESOURCE_IRQ, + .name = "fh spi2 irq", + }, +}; + +static struct resource fh_usb_resources[] = { + { + .start = USBC_REG_BASE, + .end = USBC_REG_BASE + SZ_1M - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = USBC_IRQ, + .end = USBC_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static unsigned int fh_mci_sys_card_detect_fixed(struct fhmci_host *host) +{ + return 0; +} + +struct fh_mci_board fh_mci = { + .num_slots = 1, + .get_cd = fh_mci_sys_card_detect_fixed, + .bus_hz = 50000000, + .detect_delay_ms = 200, + .caps = MMC_CAP_4_BIT_DATA, + /*8:180 degree*/ + .drv_degree = 8, + .sam_degree = 0, + .rescan_max_num = 2, +}; + +struct fh_mci_board fh_mci_sd = { + .num_slots = 1, + .bus_hz = 50000000, + .detect_delay_ms = 200, + .caps = MMC_CAP_4_BIT_DATA, + /*8:180 degree*/ + .drv_degree = 8, + .sam_degree = 0, +}; + +static struct platform_device fh_gmac_device = { + .name = "fh_gmac", + .id = 0, + .num_resources = ARRAY_SIZE(fh_gmac_resources), + .resource = fh_gmac_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &fh_gmac_data, + }, +}; + +struct platform_device fh_sd0_device = { + .name = "fh_mci", + .id = 0, + .num_resources = ARRAY_SIZE(fh_sdc0_resources), + .resource = fh_sdc0_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &fh_mci_sd, + } +}; + +struct platform_device fh_sd1_device = { + .name = "fh_mci", + .id = 1, + .num_resources = ARRAY_SIZE(fh_sdc1_resources), + .resource = fh_sdc1_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &fh_mci, + } +}; + +struct fh_sadc_platform_data fh_sadc_data = { + .ref_vol = 1800, + .active_bit = 0xfff, +}; + +static struct platform_device fh_sadc_device = { + .name = "fh_sadc", + .id = 0, + .num_resources = ARRAY_SIZE(fh_sadc_resources), + .resource = fh_sadc_resources, + .dev = { + .platform_data = &fh_sadc_data, + }, +}; + +static struct platform_device fh_uart0_device = { + .name = "ttyS", + .id = 0, + .num_resources = ARRAY_SIZE(fh_uart0_resources), + .resource = fh_uart0_resources, + .dev.platform_data = &fh_uart_platform_data[0], +}; + +static struct platform_device fh_uart1_device = { + .name = "ttyS", + .id = 1, + .num_resources = ARRAY_SIZE(fh_uart1_resources), + .resource = fh_uart1_resources, + .dev.platform_data = &fh_uart_platform_data[1], +}; + +static struct platform_device fh_uart2_device = { + .name = "ttyS", + .id = 2, + .num_resources = ARRAY_SIZE(fh_uart2_resources), + .resource = fh_uart2_resources, + .dev.platform_data = &fh_uart_platform_data[2], +}; + +static struct platform_device fh_pinctrl_device = { + .name = "fh_pinctrl", + .id = 0, +}; + +static struct platform_device fh_i2c0_device = { + .name = "fh_i2c", + .id = 0, + .num_resources = ARRAY_SIZE(fh_i2c_resources_0), + .resource = fh_i2c_resources_0, +}; + +static struct platform_device fh_i2c1_device = { + .name = "fh_i2c", + .id = 1, + .num_resources = ARRAY_SIZE(fh_i2c_resources_1), + .resource = fh_i2c_resources_1, +}; + +static struct platform_device fh_i2c2_device = { + .name = "fh_i2c", + .id = 2, + .num_resources = ARRAY_SIZE(fh_i2c_resources_2), + .resource = fh_i2c_resources_2, +}; + +static struct fh_rtc_plat_data rtc_plat_data[] = { + { + .lut_cof = 58, + .lut_offset = 0xff, + .tsensor_cp_default_out = 0x993, + .clk_name = "rtc_hclk_gate", + }, + { + .lut_cof = 71, + .lut_offset = 0xf6, + .tsensor_cp_default_out = 0x9cc, + .clk_name = "rtc_hclk_gate", + } +}; + +static struct platform_device fh_rtc_device = { + .name = "fh_rtc", + .id = 0, + .num_resources = ARRAY_SIZE(fh_rtc_resources), + .resource = fh_rtc_resources, + .dev.platform_data = &rtc_plat_data[0], +}; + +static struct resource fh_i2s_resources[] = { + { + .start = I2S_REG_BASE, + .end = I2S_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = ACW_REG_BASE, + .end = ACW_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = I2S0_IRQ, + .end = I2S0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct fh_i2s_platform_data fh_i2s_data = { + .dma_capture_channel = 4, + .dma_playback_channel = 5, + .dma_master = 0, + .dma_rx_hs_num = 10, + .dma_tx_hs_num = 11, + .clk = "i2s_clk", + .acodec_mclk = "ac_clk", +}; + +static struct platform_device fh_i2s_device = { + .name = "fh_audio", + .id = 0, + .num_resources = ARRAY_SIZE(fh_i2s_resources), + .resource = fh_i2s_resources, + .dev = { + .platform_data = &fh_i2s_data, + }, +}; + +static struct platform_device fh_gpio0_device = { + .name = GPIO_NAME, + .id = 0, + .num_resources = ARRAY_SIZE(fh_gpio0_resources), + .resource = fh_gpio0_resources, + .dev = { + .platform_data = &fh_gpio0_chip, + }, +}; + +static struct platform_device fh_gpio1_device = { + .name = GPIO_NAME, + .id = 1, + .num_resources = ARRAY_SIZE(fh_gpio1_resources), + .resource = fh_gpio1_resources, + .dev = { + .platform_data = &fh_gpio1_chip, + }, +}; + +static struct platform_device fh_aes_device = { + .name = "fh_aes", + .id = 0, + .num_resources = ARRAY_SIZE(fh_aes_resources), + .resource = fh_aes_resources, + .dev = { + .platform_data = NULL, + }, +}; + +struct fh_efuse_platform_data fh_efuse_plat_data = { + .efuse_support_flag = CRYPTO_CPU_SET_KEY | + CRYPTO_EX_MEM_SET_KEY | + CRYPTO_EX_MEM_SWITCH_KEY | + CRYPTO_EX_MEM_4_ENTRY_1_KEY | + CRYPTO_EX_MEM_INDEP_POWER, +}; + + + +#define FH_SPI0_CS0 (6) +#define FH_SPI0_CS1 (55) + +#define FH_SPI1_CS0 (14) +#define FH_SPI1_CS1 (57) + +#define SPI0_FIFO_DEPTH (128) +#define SPI0_CLK_IN (200000000) +#define SPI0_MAX_SLAVE_NO (2) +#define SPI0_DMA_RX_CHANNEL (0) +#define SPI0_DMA_TX_CHANNEL (1) + +#define SPI1_FIFO_DEPTH (64) +#define SPI1_CLK_IN (100000000) +#define SPI1_MAX_SLAVE_NO (2) +#define SPI1_DMA_RX_CHANNEL (2) +#define SPI1_DMA_TX_CHANNEL (3) + +#define SPI2_CLK_IN (100000000) + +/* SPI_TRANSFER_USE_DMA */ +static struct fh_spi_platform_data fh_spi0_data = { + .bus_no = 0, + .apb_clock_in = SPI0_CLK_IN, + .clock_source = {100000000, 150000000, 200000000}, + .clock_source_num = 3, + .slave_max_num = SPI0_MAX_SLAVE_NO, + .cs_data[0].GPIO_Pin = FH_SPI0_CS0, + .cs_data[0].name = "spi0_cs0", + .cs_data[1].GPIO_Pin = FH_SPI0_CS1, + .cs_data[1].name = "spi0_cs1", + .clk_name = "spi0_clk", + .dma_transfer_enable = SPI_TRANSFER_USE_DMA, + .rx_dma_channel = SPI0_DMA_RX_CHANNEL, + .rx_handshake_num = 4, + /*dma use inc mode could move data by burst mode...*/ + /*or move data use single mode with low efficient*/ + .ctl_wire_support = ONE_WIRE_SUPPORT | DUAL_WIRE_SUPPORT | + MULTI_WIRE_SUPPORT, +}; + +static struct fh_spi_platform_data fh_spi1_data = { + .bus_no = 1, + .apb_clock_in = SPI1_CLK_IN, + .clock_source = {SPI1_CLK_IN}, + .clock_source_num = 1, + .slave_max_num = SPI1_MAX_SLAVE_NO, + .cs_data[0].GPIO_Pin = FH_SPI1_CS0, + .cs_data[0].name = "spi1_cs0", + .cs_data[1].GPIO_Pin = FH_SPI1_CS1, + .cs_data[1].name = "spi1_cs1", + .clk_name = "spi1_clk", + .ctl_wire_support = 0, +}; + +static struct fh_spi_platform_data fh_spi2_data = { + .apb_clock_in = SPI2_CLK_IN, + .dma_transfer_enable = 0, + .rx_handshake_num = 12, + .clk_name = "spi2_clk", + .ctl_wire_support = 0, +}; + +static struct platform_device fh_efuse_device = { + .name = "fh_efuse", + .id = 0, + .num_resources = ARRAY_SIZE(fh_efuse_resources), + .resource = fh_efuse_resources, + .dev = { + .platform_data = &fh_efuse_plat_data, + }, +}; + +#ifdef CONFIG_FH_DMAC +static struct fh_dma_platform_data fh_dma_data = { + .chan_priority = CHAN_PRIORITY_ASCENDING, + .nr_channels = 6, + .clk_name = "ahb_clk", +}; + +static struct platform_device fh_dma_device = { + .name = "fh_dmac", + .id = 0, + .num_resources = ARRAY_SIZE(fh_dma_resources), + .resource = fh_dma_resources, + .dev = { + .platform_data = &fh_dma_data, + }, +}; +#endif + +#ifdef CONFIG_FH_AXI_DMAC +struct fh_axi_dma_platform_data axi_dma_plat_data = { + .chan_priority = CHAN_PRIORITY_ASCENDING, + .clk_name = "ahb_clk", +}; + +static struct platform_device fh_axi_dma_device = { + .name = "fh_axi_dmac", + .id = 0, + .num_resources = ARRAY_SIZE(fh_axi_dma_resources), + .resource = fh_axi_dma_resources, + .dev = { + .platform_data = &axi_dma_plat_data, + }, +}; +#endif + + + +static struct platform_device fh_spi0_device = { + .name = "fh_spi", + .id = 0, + .num_resources = ARRAY_SIZE(fh_spi0_resources), + .resource = fh_spi0_resources, + .dev = { + .platform_data = &fh_spi0_data, + }, +}; + +static struct platform_device fh_spi1_device = { + .name = "fh_spi", + .id = 1, + .num_resources = ARRAY_SIZE(fh_spi1_resources), + .resource = fh_spi1_resources, + .dev = { + .platform_data = &fh_spi1_data, + }, +}; + +static struct platform_device fh_spi2_device = { + .name = "fh_spi_slave", + .id = 0, + .num_resources = ARRAY_SIZE(fh_spi2_resources), + .resource = fh_spi2_resources, + .dev = { + .platform_data = &fh_spi2_data, + }, +}; + +#ifdef CONFIG_FH_PERF_MON +static struct platform_device fh_perf_device = { + .name = "fh_perf_mon", + .id = 0, + .num_resources = ARRAY_SIZE(fh_perf_resources), + .resource = fh_perf_resources, + .dev = { + .platform_data = NULL, + }, +}; +#endif + +static struct fh_wdt_platform_data fh_wdt_data = { + .mode = MODE_DISCRETE, +}; + +struct platform_device fh_wdt_device = { + .name = "fh_wdt", + .id = 0, + .num_resources = ARRAY_SIZE(fh_wdt_resources), + .resource = fh_wdt_resources, + .dev = { + .platform_data = &fh_wdt_data, + } +}; + +static struct platform_device fh_pwm_device = { + .name = "fh_pwm", + .id = 0, + .num_resources = ARRAY_SIZE(fh_pwm_resources), + .resource = fh_pwm_resources, + .dev = { + .platform_data = &pwm_data, + }, +}; + +static struct fh_usb_platform_data fh_usb_data = { + .dr_mode = "host", + .vbus_pwren = 47, +}; + +struct platform_device fh_usb_device = { + .name = "fh_usb", + .id = 0, + .num_resources = ARRAY_SIZE(fh_usb_resources), + .resource = fh_usb_resources, + .dev = { + .platform_data = &fh_usb_data, + } +}; + +#ifdef CONFIG_FH_TSENSOR +struct platform_device fh_tsensor_device = { + .name = "fh_tsensor", + .id = 0, +}; +#endif + +static struct platform_device *fh8856v210_devices[] __initdata = { + &fh_uart0_device, + &fh_uart1_device, + &fh_uart2_device, + &fh_pinctrl_device, + &fh_i2c0_device, + &fh_i2c1_device, + &fh_i2c2_device, + &fh_rtc_device, + &fh_sd0_device, + &fh_sd1_device, + &fh_sadc_device, + &fh_gmac_device, + &fh_gpio0_device, + &fh_gpio1_device, + &fh_aes_device, + &fh_efuse_device, +#ifdef CONFIG_FH_DMAC + &fh_dma_device, +#endif +#ifdef CONFIG_FH_AXI_DMAC + &fh_axi_dma_device, +#endif + &fh_spi0_device, + &fh_spi1_device, + &fh_spi2_device, + &fh_i2s_device, + &fh_pwm_device, + &fh_wdt_device, + &fh_usb_device, +#ifdef CONFIG_FH_PERF_MON + &fh_perf_device, +#endif +#ifdef CONFIG_FH_TSENSOR + &fh_tsensor_device, +#endif +}; + +static struct mtd_partition fh_sf_parts[] = { + { + /* head & Ramboot */ + .name = "bootstrap", + .offset = 0, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + /* Ramboot & U-Boot environment */ + .name = "uboot-env", + .offset = MTDPART_OFS_APPEND, + .size = SZ_64K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + /* U-Boot */ + .name = "uboot", + .offset = MTDPART_OFS_APPEND, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_4M, + .mask_flags = 0, + }, { + .name = "rootfs", + .offset = MTDPART_OFS_APPEND, + .size = SZ_8M, + .mask_flags = 0, + }, { + .name = "app", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + } + /* mtdparts= + * spi_flash:256k(bootstrap), + * 64k(u-boot-env), + * 192k(u-boot),4M(kernel), + * 8M(rootfs), + * -(app) */ + /* two blocks with bad block table (and mirror) at the end */ +}; +#ifdef CONFIG_MTD_SPI_NAND +static struct mtd_partition fh_sf_nand_parts[] = { + { + /* head & Ramboot */ + .name = "bootstrap", + .offset = 0, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + .name = "uboot-env", + .offset = MTDPART_OFS_APPEND, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "uboot", + .offset = MTDPART_OFS_APPEND, + .size = SZ_512K, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_4M, + .mask_flags = 0, + }, { + .name = "rootfs", + .offset = MTDPART_OFS_APPEND, + .size = SZ_8M, + .mask_flags = 0, + }, { + .name = "app", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + } + /* mtdparts= + * spi0.0:64k(bootstrap), + * 64k(u-boot-env), + * 192k(u-boot), + * 4M(kernel), + * 8M(rootfs), + * -(app) + * two blocks with bad block table (and mirror) at the end + */ +}; +#endif + +static struct flash_platform_data fh_flash_platform_data = { + .name = "spi_flash", + .parts = fh_sf_parts, + .nr_parts = ARRAY_SIZE(fh_sf_parts), +}; +#ifdef CONFIG_MTD_SPI_NAND +static struct flash_platform_data fh_nandflash_platform_data = { + .name = "spi_nandflash", + .parts = fh_sf_nand_parts, + .nr_parts = ARRAY_SIZE(fh_sf_nand_parts), +}; +#endif + +static struct spi_board_info fh_spi_devices[] = { +#ifdef CONFIG_MTD_SPI_NAND + { + .modalias = "spi-nand", + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 50000000, + .mode = SPI_MODE_3, + .platform_data = &fh_nandflash_platform_data, + }, +#endif + { + .modalias = "m25p80", + .bus_num = 0, + .chip_select = 0, + /* multi wire should adapt spi para 'ctl_wire_support'*/ + .mode = SPI_MODE_3 | SPI_RX_DUAL, + .max_speed_hz = 50000000, + .platform_data = &fh_flash_platform_data, + }, + +}; + +extern void early_print(const char *str, ...); + +static void __init fh_console_pre_init(struct fh_platform_uart *plat, int num) +{ + int idx = 0; + + for (; idx < num; idx++) { + struct uart_port *port; + + port = &fh_serial_ports[idx]; + port->mapbase = plat[idx].mapbase; + port->fifosize = plat[idx].fifo_size; + port->uartclk = plat[idx].uartclk; + + switch (idx) { + case 0: + port->membase = (unsigned char *)VA_UART0_REG_BASE; + break; + case 1: + port->membase = (unsigned char *)VA_UART1_REG_BASE; + break; + case 2: + port->membase = (unsigned char *)VA_UART2_REG_BASE; + break; + default: + break; + } + } +} + +static void __init fh8856v210_map_io(void) +{ + iotable_init(fh8856v210_io_desc, ARRAY_SIZE(fh8856v210_io_desc)); + fh_console_pre_init(fh_uart_platform_data, + ARRAY_SIZE(fh_uart_platform_data)); +} + + +static __init void fh8856v210_board_init(void) +{ + if (fh_is_8856v210()) + fh_rtc_device.dev.platform_data = &rtc_plat_data[1]; + platform_add_devices(fh8856v210_devices, + ARRAY_SIZE(fh8856v210_devices)); + spi_register_board_info(fh_spi_devices, ARRAY_SIZE(fh_spi_devices)); +} +void __init fh_timer_init_no_of(unsigned int iovbase, + unsigned int irqno); + +static void __init fh8856v210_init_early(void) +{ + fh_pmu_init(); + fh_pinctrl_init(VA_PMU_REG_BASE + 0x80); +} + +static void __init fh_time_init(void) +{ + unsigned int vtimerbase = (unsigned int)ioremap(TIMER_REG_BASE, SZ_4K); + + fh_clk_init(); + fh_timer_init_no_of(vtimerbase, TMR0_IRQ); + +} + +void __init fh_intc_init_no_of(unsigned int iovbase); +static void __init fh_intc_init(void) +{ + unsigned int vintcbase = (unsigned int)ioremap(INTC_REG_BASE, SZ_4K); + + fh_intc_init_no_of(vintcbase); + +} +static void fh8856v210_restart + (enum reboot_mode mode, const char *cmd) +{ + fh_pmu_restart(); +} + + +MACHINE_START(FH8856V210, "FH8856V210") + .atag_offset = 0x100, + .map_io = fh8856v210_map_io, + .init_irq = fh_intc_init, + .init_time = fh_time_init, + .init_machine = fh8856v210_board_init, + .init_early = fh8856v210_init_early, + .restart = fh8856v210_restart, +MACHINE_END + diff --git a/arch/arm/mach-fh/fh8856v210/board_config.fh8856v210.appboard b/arch/arm/mach-fh/fh8856v210/board_config.fh8856v210.appboard new file mode 100644 index 00000000..1c1a9153 --- /dev/null +++ b/arch/arm/mach-fh/fh8856v210/board_config.fh8856v210.appboard @@ -0,0 +1,45 @@ +#ifndef BOARD_CONFIG_H_ +#define BOARD_CONFIG_H_ + +/* + * GPIO0 -> IRCUT_ON + * GPIO1 -> IRCUT_OFF + * GPIO2 -> USB_PWREN + * GPIO11 -> EMAC PHY Reset + * GPIO12 -> CIS_CLK + * GPIO13 -> CIS_RSTN + * GPIO14 -> CIS_PDN + * GPIO19 -> SD1_PWREN/WIFI_REG_ON + * GPIO20 -> AK7755 Reset + * GPIO24 -> LED0 + * GPIO25 -> LED1 + * GPIO26 -> Reset Configs + * GPIO27 -> AK7755 PowerDown + * GPIO28 -> IR + * GPIO53 -> USB_PWREN/SD0_PWREN + * GPIO55 -> SD1 WIFI Interrupt + */ + +#define CONFIG_SD_CD_FIXED + +#define CONFIG_ISP_CLK_RATE 171000000 +#define CONFIG_JPEG_CLK_RATE 171000000 +#define CONFIG_VEU_CLK_RATE 240000000 + +#define USB_VBUS_PWR_GPIO (47) + +#define ETH_GPIO "ETH", "GPIO48", "GPIO49", "GPIO50", "GPIO51", "GPIO52",\ + "GPIO53", "GPIO54", "GPIO55", "GPIO56" + +#define CONFIG_PINCTRL_SELECT \ + ETH_GPIO, "I2C0", "PWM2", "PWM3", "PWM4", "PWM5", "PWM6", \ + "PWM7", "PWM8", "PWM9", "SADC_XAIN0", "SADC_XAIN1", \ + "SD0_NO_WP", "SENSOR_CLK", "SSI0_4BIT", "UART0", \ + "UART1", "GPIO4", "GPIO13", "GPIO30", "GPIO31", \ + "GPIO32", "GPIO43", "GPIO44", "GPIO47", \ +\ + "GPIO11", "GPIO14", "GPIO15", "GPIO16", "GPIO24", \ + "GPIO25", "GPIO45", "GPIO46", "GPIO57", "GPIO58", "GPIO59", \ + "GPIO60", "GPIO61", "GPIO62", "GPIO63" + +#endif /* BOARD_CONFIG_H_ */ diff --git a/arch/arm/mach-fh/fh8856v210/chip.c b/arch/arm/mach-fh/fh8856v210/chip.c new file mode 100644 index 00000000..9bbb3c49 --- /dev/null +++ b/arch/arm/mach-fh/fh8856v210/chip.c @@ -0,0 +1,747 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * external oscillator + * fixed to 24M + */ +static struct fh_clk osc_clk = { + .name = "osc_clk", + .frequency = OSC_FREQUENCY, + .flag = CLOCK_FIXED, +}; + +/* + * phase-locked-loop device, + * generates a higher frequency clock + * from the external oscillator reference + *PLL_DDR + */ + +static struct fh_clk pll_ddr_rclk = { + .name = "pll_ddr_rclk", + .flag = CLOCK_PLL_R|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL0, + .en_reg_offset = REG_PMU_PLL0_CTRL, + .en_reg_mask = 0xf000, +}; + +/*PLL_CPU*/ +static struct fh_clk pll_cpu_pclk = { + .name = "pll_cpu_pclk", + .flag = CLOCK_PLL_P|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL1, + .en_reg_offset = REG_PMU_PLL1_CTRL, + .en_reg_mask = 0xf00, +}; + +static struct fh_clk pll_cpu_rclk = { + .name = "pll_cpu_rclk", + .flag = CLOCK_PLL_R|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL1, + .en_reg_offset = REG_PMU_PLL1_CTRL, + .en_reg_mask = 0xf000, +}; + +/*PLL_SYS*/ +static struct fh_clk pll_sys_pclk = { + .name = "pll_sys_pclk", + .flag = CLOCK_PLL_P|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL2, + .en_reg_offset = REG_PMU_PLL2_CTRL, + .en_reg_mask = 0xf00, +}; + + +static struct fh_clk pll_sys_rclk = { + .name = "pll_sys_rclk", + .flag = CLOCK_PLL_R|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL2, + .en_reg_offset = REG_PMU_PLL2_CTRL, + .en_reg_mask = 0xf000, +}; + +static struct fh_clk pllsysp_div12_clk = { + .name = "pllsysp_div12_clk", + .flag = CLOCK_NORESET|CLOCK_NOGATE, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV5, + .div_reg_mask = 0xf000000, +}; + +static struct fh_clk ddr_clk = { + .name = "ddr_clk", + .flag = CLOCK_NODIV, + .parent = {&pll_ddr_rclk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x4000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x8, +}; +static struct fh_clk arm_clk = { + .name = "arm_clk", + .flag = CLOCK_MULTI_PARENT|CLOCK_NOGATE|CLOCK_NODIV, + .parent = {&osc_clk, &pll_cpu_pclk}, + .prediv = 1, + .sel_reg_offset = REG_PMU_SYS_CTRL, + .sel_reg_mask = 0x1, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x1, +}; +static struct fh_clk arc_clk = { + .name = "arc_clk", + .flag = CLOCK_MULTI_PARENT|CLOCK_NODIV, + .parent = {&osc_clk, &pll_cpu_rclk}, + .prediv = 1, + .sel_reg_offset = REG_PMU_SYS_CTRL, + .sel_reg_mask = 0x1, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x400000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x400000, +}; +static struct fh_clk ahb_clk = { + .name = "ahb_clk", + .flag = CLOCK_MULTI_PARENT|CLOCK_NORESET|CLOCK_NOGATE, + .parent = {&osc_clk, &pll_sys_pclk}, + .prediv = 1, + .sel_reg_offset = REG_PMU_SYS_CTRL, + .sel_reg_mask = 0x1, + .div_reg_offset = REG_PMU_CLK_DIV0, + .div_reg_mask = 0xf0000, +}; + +static struct fh_clk isp_aclk = { + .name = "isp_aclk", + .flag = CLOCK_NORESET, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV0, + .div_reg_mask = 0xf00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x1, + .def_rate = CONFIG_ISP_CLK_RATE, +}; +static struct fh_clk ispb_aclk = { + .name = "ispb_aclk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&isp_aclk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x4, +}; + +static struct fh_clk vpu_clk = { + .name = "vpu_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&isp_aclk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x80000000, +}; + +static struct fh_clk pix_clk = { + .name = "pix_clk", + .flag = CLOCK_NORESET|CLOCK_NOGATE, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV2, + .div_reg_mask = 0xf000000, +}; + +static struct fh_clk jpeg_clk = { + .name = "jpeg_clk", + .flag = CLOCK_NORESET, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV7, + .div_reg_mask = 0xf00000, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x40000000, + .def_rate = CONFIG_JPEG_CLK_RATE, +}; + +static struct fh_clk bgm_clk = { + .name = "bgm_clk", + .flag = CLOCK_NORESET, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV7, + .div_reg_mask = 0xf00000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x40000, +}; + +static struct fh_clk jpeg_adapt_clk = { + .name = "jpeg_adapt_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&jpeg_clk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x2, +}; +static struct fh_clk spi0_clk = { + .name = "spi0_clk", + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xff, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x80, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x100, +}; +static struct fh_clk sdc0_clk = { + .name = "sdc0_clk", + .parent = {&pll_sys_pclk}, + .prediv = 8, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xf00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x200, + .rst_reg_offset = REG_PMU_SWRST_AHB_CTRL, + .rst_reg_mask = 0x4, +}; +static struct fh_clk spi2_clk = { + .name = "spi2_clk", + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xf000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x2, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x100000, +}; +static struct fh_clk spi1_clk = { + .name = "spi1_clk", + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xff0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x100, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x200, +}; +static struct fh_clk sdc1_clk = { + .name = "sdc1_clk", + .parent = {&pll_sys_pclk}, + .prediv = 8, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xf000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x400, + .rst_reg_offset = REG_PMU_SWRST_AHB_CTRL, + .rst_reg_mask = 0x2, +}; + +static struct fh_clk veu_clk = { + .name = "veu_clk", + .flag = CLOCK_MULTI_PARENT, + .parent = {&pll_sys_pclk, &pll_sys_rclk}, + .prediv = 1, + .sel_reg_offset = REG_PMU_SYS_CTRL, + .sel_reg_mask = 0x4, + .div_reg_offset = REG_PMU_CLK_DIV0, + .div_reg_mask = 0x7000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x10, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x2000000, + .def_rate = CONFIG_VEU_CLK_RATE, + +}; + +static struct fh_clk veu_adapt_clk = { + .name = "veu_adapt_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&veu_clk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x20000000, + +}; + +static struct fh_clk cis_clk_out = { + .name = "cis_clk_out", + .flag = CLOCK_NORESET, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV1, + .div_reg_mask = 0xff0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x800000, +}; + +static struct fh_clk eth_clk = { + .name = "eth_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV6, + .div_reg_mask = 0xf000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x12000000, + .rst_reg_offset = REG_PMU_SWRST_AHB_CTRL, + .rst_reg_mask = 0x20000, +}; +static struct fh_clk i2c0_clk = { + .name = "i2c0_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV4, + .div_reg_mask = 0x3f0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x1000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x400, +}; + +static struct fh_clk i2c1_clk = { + .name = "i2c1_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV4, + .div_reg_mask = 0x3f000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x8000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x800, +}; + +static struct fh_clk i2c2_clk = { + .name = "i2c2_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV7, + .div_reg_mask = 0x00003f00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x00000008, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x20000000, +}; + +static struct fh_clk pwm_clk = { + .name = "pwm_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV5, + .div_reg_mask = 0xff, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x10000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x80, + .def_rate = 50000000, +}; + +static struct fh_clk uart0_clk = { + .name = "uart0_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV4, + .div_reg_mask = 0x1f, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x2000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x4000, + .def_rate = 16666666, +}; + +static struct fh_clk uart1_clk = { + .name = "uart1_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV4, + .div_reg_mask = 0x1f00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x4000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x8000, + .def_rate = 16666666, +}; +static struct fh_clk uart2_clk = { + .name = "uart2_clk", + .parent = {&pllsysp_div12_clk}, + .flag = 0, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV7, + .div_reg_mask = 0x7f, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x8000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x8000000, + .def_rate = 16666666, +}; + +static struct fh_clk efuse_clk = { + .name = "efuse_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV1, + .div_reg_mask = 0x3f000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x200000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x800000, +}; + +static struct fh_clk pts_clk = { + .name = "pts_clk", + .parent = {&pllsysp_div12_clk}, + .flag = CLOCK_NORESET, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV2, + .div_reg_mask = 0x1ff, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x80000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL2, + .rst_reg_mask = 0x1, + .def_rate = 1000000, +}; + +static struct fh_clk tmr0_clk = { + .name = "tmr0_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV5, + .div_reg_mask = 0xff0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x20000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x40000, +}; + +static struct fh_clk sadc_clk = { + .name = "sadc_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV6, + .div_reg_mask = 0x7f0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x4000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x10000, +}; + +static struct fh_clk ac_clk = { + .name = "ac_clk", + .parent = {&osc_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV6, + .div_reg_mask = 0x3f, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x800, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x1000, +}; + +static struct fh_clk i2s_clk = { + .name = "i2s_clk", + .parent = {&ac_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV6, + .div_reg_mask = 0x3f00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x1000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x2000, +}; + +static struct fh_clk wdt_clk = { + .name = "wdt_clk", + .flag = 0, + .parent = {&ahb_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV5, + .div_reg_mask = 0xff00, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x8000000, + .rst_reg_offset = REG_PMU_SWRST_APB_CTRL, + .rst_reg_mask = 0x100000, + .def_rate = 1000000, +}; + +static struct fh_clk gpio0_db_clk = { + .name = "gpio0_db_clk", + .flag = 0, + .parent = {&pllsysp_div12_clk}, + .prediv = 100, + .div_reg_offset = REG_PMU_CLK_DIV8, + .div_reg_mask = 0x7fff, + .en_reg_offset = REG_PMU_CLK_DIV8, + .en_reg_mask = 0x8000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x10, +}; + +static struct fh_clk gpio1_db_clk = { + .name = "gpio1_db_clk", + .flag = 0, + .parent = {&pllsysp_div12_clk}, + .prediv = 100, + .div_reg_offset = REG_PMU_CLK_DIV8, + .div_reg_mask = 0x7fff0000, + .en_reg_offset = REG_PMU_CLK_DIV8, + .en_reg_mask = 0x80000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x20, +}; + + +static struct fh_clk mipi_dphy_clk = { + .name = "mipi_dphy_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&osc_clk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x100000, +}; +static struct fh_clk mipi_wrap_gate = { + .name = "mipi_wrap_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x20000000, +}; +static struct fh_clk rtc_hclk_gate = { + .name = "rtc_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x10000000, +}; +static struct fh_clk emac_hclk_gate = { + .name = "emac_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x2000000, +}; +static struct fh_clk usb_clk = { + .name = "usb_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x1000000, +}; +static struct fh_clk aes_hclk_gate = { + .name = "aes_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x80, +}; +static struct fh_clk ephy_clk_gate = { + .name = "ephy_clk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x1, +}; +static struct fh_clk sdc0_clk8x_gate = { + .name = "sdc0_clk8x_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x4, +}; +static struct fh_clk sdc1_clk8x_gate = { + .name = "sdc1_clk8x_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x8, +}; +static struct fh_clk mipic_pclk_gate = { + .name = "mipic_pclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x10, +}; + +static struct fh_clk gpio0_pclk_gate = { + .name = "gpio0_pclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV8, + .en_reg_mask = 0x4000, +}; +static struct fh_clk gpio1_pclk_gate = { + .name = "gpio1_pclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV8, + .en_reg_mask = 0x40000000, +}; +static struct fh_clk isp_hclk_gate = { + .name = "isp_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x1000000, +}; +static struct fh_clk veu_hclk_gate = { + .name = "veu_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x2000000, +}; +static struct fh_clk bgm_hclk_gate = { + .name = "bgm_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x4000000, +}; +static struct fh_clk adapt_hclk_gate = { + .name = "adapt_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x8000000, +}; +static struct fh_clk jpg_hclk_gate = { + .name = "jpg_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x10000000, +}; +static struct fh_clk jpg_adapt_gate = { + .name = "jpg_adapt_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x20000000, +}; +static struct fh_clk vpu_hclk_gate = { + .name = "vpu_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x40000000, +}; + +static struct fh_clk sdc0_clk_sample = { + .name = "sdc0_clk_sample", + .parent = {&sdc0_clk}, + .flag = CLOCK_NOGATE | CLOCK_PHASE, + .prediv = 1, + .sel_reg_offset = REG_PMU_CLK_GATE1, + .sel_reg_mask = 0xf0000, +}; + +static struct fh_clk sdc0_clk_drv = { + .name = "sdc0_clk_drv", + .parent = {&sdc0_clk}, + .flag = CLOCK_NOGATE | CLOCK_PHASE, + .prediv = 1, + .sel_reg_offset = REG_PMU_CLK_GATE1, + .sel_reg_mask = 0xf00000, +}; + +static struct fh_clk sdc1_clk_sample = { + .name = "sdc1_clk_sample", + .parent = {&sdc0_clk}, + .flag = CLOCK_NOGATE | CLOCK_PHASE, + .prediv = 1, + .sel_reg_offset = REG_PMU_CLK_GATE1, + .sel_reg_mask = 0xf00, +}; + +static struct fh_clk sdc1_clk_drv = { + .name = "sdc1_clk_drv", + .parent = {&sdc0_clk}, + .flag = CLOCK_NOGATE | CLOCK_PHASE, + .prediv = 1, + .sel_reg_offset = REG_PMU_CLK_GATE1, + .sel_reg_mask = 0xf000, +}; + +struct fh_clk *fh_clks[] = { + &osc_clk, + &pll_ddr_rclk, + &pll_cpu_pclk, + &pll_cpu_rclk, + &pll_sys_pclk, + &pll_sys_rclk, + &arm_clk, + &arc_clk, + &ahb_clk, + &ddr_clk, + &isp_aclk, + &ispb_aclk, + &jpeg_clk, + &jpeg_adapt_clk, + &vpu_clk, + &veu_clk, + &veu_adapt_clk, + &bgm_clk, + &mipi_dphy_clk, + &pllsysp_div12_clk, + &cis_clk_out, + &pix_clk, + &pts_clk, + &spi0_clk, + &spi1_clk, + &spi2_clk, + &sdc0_clk, + &sdc1_clk, + &uart0_clk, + &uart1_clk, + &uart2_clk, + &i2c0_clk, + &i2c1_clk, + &i2c2_clk, + &pwm_clk, + &wdt_clk, + &tmr0_clk, + &ac_clk, + &i2s_clk, + &sadc_clk, + ð_clk, + &efuse_clk, + &gpio0_db_clk, + &gpio1_db_clk, + &mipi_wrap_gate, + &rtc_hclk_gate, + &emac_hclk_gate, + &usb_clk, + &aes_hclk_gate, + &ephy_clk_gate, + &sdc0_clk8x_gate, + &sdc1_clk8x_gate, + &gpio0_pclk_gate, + &gpio1_pclk_gate, + &mipic_pclk_gate, + &sdc0_clk_sample, + &sdc0_clk_drv, + &sdc1_clk_sample, + &sdc1_clk_drv, + &isp_hclk_gate, + &veu_hclk_gate, + &bgm_hclk_gate, + &adapt_hclk_gate, + &jpg_hclk_gate, + &jpg_adapt_gate, + &vpu_hclk_gate, + NULL, +}; +EXPORT_SYMBOL(fh_clks); diff --git a/arch/arm/mach-fh/fh8856v210/chip.h b/arch/arm/mach-fh/fh8856v210/chip.h new file mode 100644 index 00000000..f2b2fcae --- /dev/null +++ b/arch/arm/mach-fh/fh8856v210/chip.h @@ -0,0 +1,420 @@ +#ifndef __ASM_ARCH_HL_H +#define __ASM_ARCH_HL_H + +#include + +#define SRAM_GRANULARITY 32 +#define SRAM_SIZE (SZ_128K+SZ_8K) + + +#define RAM_BASE (0x10000000) +#define DDR_BASE (0xA0000000) + + +#define PMU_REG_BASE (0xF0000000) +#define TIMER_REG_BASE (0xF0C00000) +#define GPIO0_REG_BASE (0xF0300000) +#define GPIO1_REG_BASE (0xF4000000) +#define UART0_REG_BASE (0xF0700000) +#define UART1_REG_BASE (0xF0800000) +#define SPI0_REG_BASE (0xF0500000) +#define SPI1_REG_BASE (0xF0600000) +#define SPI2_REG_BASE (0xF0640000) +#define INTC_REG_BASE (0xE0200000) +#define GMAC_REG_BASE (0xE0600000) +#define USBC_REG_BASE (0xE0700000) +#define DMAC_REG_BASE (0xE0300000) +#define I2C1_REG_BASE (0xF0B00000) +#define I2C0_REG_BASE (0xF0200000) +#define I2C2_REG_BASE (0xF0100000) +#define SDC0_REG_BASE (0xE2000000) +#define SDC1_REG_BASE (0xE2200000) +#define WDT_REG_BASE (0xF0D00000) +#define PWM_REG_BASE (0xF0400000) +#define I2S_REG_BASE (0xF0900000) +#define ACW_REG_BASE (0xF0A00000) +#define UART2_REG_BASE (0xF1300000) +#define SADC_REG_BASE (0xF1200000) +#define EFUSE_REG_BASE (0xF1600000) +#define AES_REG_BASE (0xE8200000) +#define RTC_REG_BASE (0xF1500000) +#define DDRC_REG_BASE (0xED000000) +#define CONSOLE_REG_BASE UART0_REG_BASE +#define FH_UART_NUMBER 3 + +#define FH_PMU_REG_SIZE 0x2110 +#define REG_PMU_CHIP_ID (0x0000) +#define REG_PMU_IP_VER (0x0004) +#define REG_PMU_FW_VER (0x0008) +#define REG_PMU_CLK_SEL (0x000c) +/*for HL REG_PMU_SYS_CTRL and CLK_SEL use one register */ +#define REG_PMU_SYS_CTRL (0x000c) +#define REG_PMU_PLL0 (0x0010) +#define REG_PMU_PLL1 (0x0014) +#define REG_PMU_PLL0_CTRL (0x0018) +#define REG_PMU_CLK_GATE (0x001c) +#define REG_PMU_CLK_GATE1 (0x0020) +#define REG_PMU_CLK_DIV0 (0x0024) +#define REG_PMU_CLK_DIV1 (0x0028) +#define REG_PMU_CLK_DIV2 (0x002c) +#define REG_PMU_CLK_DIV3 (0x0030) +#define REG_PMU_CLK_DIV4 (0x0034) +#define REG_PMU_CLK_DIV5 (0x0038) +#define REG_PMU_CLK_DIV6 (0x003c) +#define REG_PMU_SWRST_MAIN_CTRL (0x0040) +#define REG_PMU_SWRST_MAIN_CTRL2 (0x0044) +#define REG_PMU_SWRST_AHB_CTRL (0x0048) +#define REG_PMU_SWRST_APB_CTRL (0x004c) +#define REG_PMU_SPC_IO_STATUS (0x0054) +#define REG_PMU_SPC_FUN (0x0058) +#define REG_PMU_CLK_DIV7 (0x005c) +#define REG_PMU_CLK_DIV8 (0x0060) +#define REG_PMU_PLL2 (0x0064) +#define REG_PMU_PLL2_CTRL (0x0068) +#define REG_PMU_PLL1_CTRL (0x006c) +#define REG_PAD_PWR_SEL (0x0074) +#define REG_PMU_SWRSTN_NSR (0x0078) +#define REG_PMU_SWRSTN_NSR1 (0x007c) +#define REG_PMU_ETHPHY_REG0 (0x2108) + + +#define REG_PMU_PAD_BOOT_MODE_CFG (0x0080) +#define REG_PMU_PAD_BOOT_SEL1_CFG (0x0084) +#define REG_PMU_PAD_BOOT_SEL0_CFG (0x0088) +#define REG_PMU_PAD_UART0_TX_CFG (0x008c) +#define REG_PMU_PAD_UART0_RX_CFG (0x0090) +#define REG_PMU_PAD_I2C0_SCL_CFG (0x0094) +#define REG_PMU_PAD_I2C0_SDA_CFG (0x0098) +#define REG_PMU_PAD_SENSOR_CLK_CFG (0x009c) +#define REG_PMU_PAD_SENSOR_RSTN_CFG (0x00a0) +#define REG_PMU_PAD_UART1_TX_CFG (0x00a4) +#define REG_PMU_PAD_UART1_RX_CFG (0x00a8) +#define REG_PMU_PAD_I2C1_SCL_CFG (0x00ac) +#define REG_PMU_PAD_I2C1_SDA_CFG (0x00b0) +#define REG_PMU_PAD_UART2_TX_CFG (0x00b4) +#define REG_PMU_PAD_UART2_RX_CFG (0x00b8) +#define REG_PMU_PAD_USB_PWREN_CFG (0x00bc) +#define REG_PMU_PAD_PWM0_CFG (0x00c0) +#define REG_PMU_PAD_PWM1_CFG (0x00c4) +#define REG_PMU_PAD_PWM2_CFG (0x00c8) +#define REG_PMU_PAD_PWM3_CFG (0x00cc) +#define REG_PMU_PAD_MAC_RMII_CLK_CFG (0x00d0) +#define REG_PMU_PAD_MAC_REF_CLK_CFG (0x00d4) +#define REG_PMU_PAD_MAC_TXD0_CFG (0x00d8) +#define REG_PMU_PAD_MAC_TXD1_CFG (0x00dc) +#define REG_PMU_PAD_MAC_TXEN_CFG (0x00e0) +#define REG_PMU_PAD_MAC_RXD0_CFG (0x00e4) +#define REG_PMU_PAD_MAC_RXD1_CFG (0x00e8) +#define REG_PMU_PAD_MAC_RXDV_CFG (0x00ec) +#define REG_PMU_PAD_MAC_MDC_CFG (0x00f0) +#define REG_PMU_PAD_MAC_MDIO_CFG (0x00f4) +#define REG_PMU_PAD_SD1_CLK_CFG (0x00f8) +#define REG_PMU_PAD_SD1_CD_CFG (0x00fc) +#define REG_PMU_PAD_SD1_CMD_RSP_CFG (0x0100) +#define REG_PMU_PAD_SD1_DATA_0_CFG (0x0104) +#define REG_PMU_PAD_SD1_DATA_1_CFG (0x0108) +#define REG_PMU_PAD_SD1_DATA_2_CFG (0x010c) +#define REG_PMU_PAD_SD1_DATA_3_CFG (0x0110) +#define REG_PMU_PAD_GPIO_0_CFG (0x0114) +#define REG_PMU_PAD_GPIO_1_CFG (0x0118) +#define REG_PMU_PAD_GPIO_2_CFG (0x011c) +#define REG_PMU_PAD_GPIO_3_CFG (0x0120) +#define REG_PMU_PAD_GPIO_4_CFG (0x0124) +#define REG_PMU_PAD_SSI0_CLK_CFG (0x0128) +#define REG_PMU_PAD_SSI0_CSN_0_CFG (0x012c) +#define REG_PMU_PAD_SSI0_TXD_CFG (0x0130) +#define REG_PMU_PAD_SSI0_RXD_CFG (0x0134) +#define REG_PMU_PAD_SSI0_D2_CFG (0x0138) +#define REG_PMU_PAD_SSI0_D3_CFG (0x013c) +#define REG_PMU_PAD_SSI1_CLK_CFG (0x0140) +#define REG_PMU_PAD_SSI1_CSN_0_CFG (0x0144) +#define REG_PMU_PAD_SSI1_TXD_CFG (0x0148) +#define REG_PMU_PAD_SSI1_RXD_CFG (0x014c) +#define REG_PMU_PAD_SD0_CD_CFG (0x0150) +#define REG_PMU_PAD_SD0_CLK_CFG (0x0154) +#define REG_PMU_PAD_SD0_CMD_RSP_CFG (0x0158) +#define REG_PMU_PAD_SD0_DATA_0_CFG (0x015c) +#define REG_PMU_PAD_SD0_DATA_1_CFG (0x0160) +#define REG_PMU_PAD_SD0_DATA_2_CFG (0x0164) +#define REG_PMU_PAD_SD0_DATA_3_CFG (0x0168) +#define REG_PMU_PAD_SADC_XAIN0_CFG (0x016c) +#define REG_PMU_PAD_SADC_XAIN1_CFG (0x0170) +#define REG_PMU_PAD_SADC_XAIN2_CFG (0x0174) +#define REG_PMU_PAD_SADC_XAIN3_CFG (0x0178) +#define REG_PMU_PAD_GPIO_28_CFG (0x017c) +#define REG_PMU_PAD_GPIO_29_CFG (0x0180) + +#define REG_PMU_ARM_INT_0 (0x01e0) +#define REG_PMU_ARM_INT_1 (0x01e4) +#define REG_PMU_ARM_INT_2 (0x01e8) +#define REG_PMU_A625_INT_0 (0x01ec) +#define REG_PMU_A625_INT_1 (0x01f0) +#define REG_PMU_A625_INT_2 (0x01f4) +#define REG_PMU_DMA (0x01f8) +#define REG_PMU_WDT_CTRL (0x01fc) +#define REG_PMU_DBG_STAT0 (0x0200) +#define REG_PMU_DBG_STAT1 (0x0204) +#define REG_PMU_DBG_STAT2 (0x0208) +#define REG_PMU_DBG_STAT3 (0x020c) +#define REG_PMU_USB_SYS (0x0210) +#define REG_PMU_USB_CFG (0x0214) +#define REG_PMU_USB_TUNE (0x0218) +#define REG_PMU_USB_SYS1 (0x0228) +#define REG_PMU_PTSLO (0x022c) +#define REG_PMU_PTSHI (0x0230) +#define REG_PMU_USER0 (0x0234) +#define REG_PMU_BOOT_MODE (0x0330) +#define REG_PMU_DDR_SIZE (0x0334) +#define REG_PMU_CHIP_INFO (0x033C) +#define REG_PMU_EPHY_PARAM (0x0340) +#define REG_PMU_RTC_PARAM (0x0344) +#define REG_PMU_SD1_FUNC_SEL (0x03a0) +#define REG_PMU_PRDCID_CTRL0 (0x0500) +#define REG_PMU_A625BOOT0 (0x2000) +#define REG_PMU_A625BOOT1 (0x2004) +#define REG_PMU_A625BOOT2 (0x2008) +#define REG_PMU_A625BOOT3 (0x200c) +#define REG_PMU_A625_START_CTRL (0x2010) +#define REG_PMU_ARC_INTC_MASK (0x2014) + +#define FH_GMAC_AHB_RESET (1<<17) +#define FH_GMAC_SPEED_100M (1<<24) +#define PMU_RMII_SPEED_MODE (REG_PMU_CLK_SEL) +#define PMU_RXDV_GPIO_SWITCH (REG_PMU_PAD_MAC_RXDV_CFG) +#define PMU_RXDV_GPIO_MASK (0x0f000000) +#define PMU_RXDV_GPIO_VAL (0x01000000) + +#define PMU_DWI2S_CLK_SEL_REG (REG_PMU_CLK_SEL) +#define PMU_DWI2S_CLK_SEL_SHIFT (1) +#define PMU_DWI2S_CLK_DIV_REG (REG_PMU_CLK_DIV6) +#define PMU_DWI2S_CLK_DIV_SHIFT (0) + +/*ATTENTION: written by ARC */ +#define PMU_ARM_INT_MASK (0x01ec) +#define PMU_ARM_INT_RAWSTAT (0x01f0) +#define PMU_ARM_INT_STAT (0x01f4) + +#define PMU_A625_INT_MASK (0x01e0) +#define PMU_A625_INT_RAWSTAT (0x01e4) +#define PMU_A625_INT_STAT (0x01e8) + +#define PMU_IRQ 0 +#define DDRC_IRQ 1 +#define WDT_IRQ 2 +#define TMR0_IRQ 3 +#define VEU_IRQ 4 +#define PERF_IRQ 5 +#define VPU_IRQ 9 +#define I2C0_IRQ 11 +#define I2C1_IRQ 12 +#define JPEG_IRQ 13 +#define BGM_IRQ 14 +#define VEU_LOOP_IRQ 15 +#define AES_IRQ 16 +#define MIPIC_IRQ 17 +#define MIPI_WRAP_IRQ 18 +#define ACW_IRQ 19 +#define SADC_IRQ 20 +#define SPI1_IRQ 21 +#define JPEG_LOOP_IRQ 22 +#define DMAC0_IRQ 23 +#define DMAC1_IRQ 24 +#define I2S0_IRQ 25 +#define GPIO0_IRQ 26 +#define SPI0_IRQ 28 +#define ARC_SW_IRQ 29 +#define UART0_IRQ 30 +#define UART1_IRQ 31 +#define ARM_SW_IRQ 32 +#define RTC_IRQ 33 +#define PWM_IRQ 36 +#define SPI2_IRQ 38 +#define USBC_IRQ 39 +#define GPIO1_IRQ 40 +#define UART2_IRQ 41 +#define SDC0_IRQ 42 +#define SDC1_IRQ 43 +#define GMAC_IRQ 44 +#define EPHY_IRQ 45 +#define I2C2_IRQ 46 +#define RTC_ALM_IRQ 47 +#define RTC_CORE_IRQ 48 +/* because chips with some same function in different */ +/* pmu register, use wrap marco to make code to be same */ +#define PMU_RMII_SPEED_MODE (REG_PMU_CLK_SEL) + +#define MEM_START_PHY_ADDR DDR_BASE +#define MEM_SIZE 0x4000000 + + +#define NR_INTERNAL_IRQS (64) +#define NR_EXTERNAL_IRQS (64) +/*#define NR_IRQS (NR_INTERNAL_IRQS + NR_EXTERNAL_IRQS)*/ + +/* SWRST_MAIN_CTRL */ +#define CPU_RSTN_BIT (0) +#define UTMI_RSTN_BIT (1) +#define DDRPHY_RSTN_BIT (2) +#define DDRC_RSTN_BIT (3) +#define GPIO0_DB_RSTN_BIT (4) +#define GPIO1_DB_RSTN_BIT (5) +#define PIXEL_RSTN_BIT (6) +#define PWM_RSTN_BIT (7) +#define SPI0_RSTN_BIT (8) +#define SPI1_RSTN_BIT (9) +#define I2C0_RSTN_BIT (10) +#define I2C1_RSTN_BIT (11) +#define ACODEC_RSTN_BIT (12) +#define I2S_RSTN_BIT (13) +#define UART0_RSTN_BIT (14) +#define UART1_RSTN_BIT (15) +#define SADC_RSTN_BIT (16) +#define ADAPT_RSTN_BIT (17) +#define TMR_RSTN_BIT (18) +#define UART2_RSTN_BIT (19) +#define SPI2_RSTN_BIT (20) +#define JPG_ADAPT_RSTN_BIT (21) +#define ARC_RSTN_BIT (22) +#define EFUSE_RSTN_BIT (23) +#define JPG_RSTN_BIT (24) +#define VEU_RSTN_BIT (25) +#define VPU_RSTN_BIT (26) +#define ISP_RSTN_BIT (27) +#define BGM_RSTN_BIT (28) +#define I2C2_RSTN_BIT (29) +#define EPHY_RSTN_BIT (30) +#define SYS_RSTN_BIT (31) + +/* SWRST_AHB_CTRL */ +#define EMC_HRSTN_BIT (0) +#define SDC1_HRSTN_BIT (1) +#define SDC0_HRSTN_BIT (2) +#define AES_HRSTN_BIT (3) +#define DMAC0_HRSTN_BIT (4) +#define INTC_HRSTN_BIT (5) +#define JPEG_ADAPT_HRSTN_BIT (7) +#define JPEG_HRSTN_BIT (8) +#define VCU_HRSTN_BIT (9) +#define VPU_HRSTN_BIT (10) +#define ISP_HRSTN_BIT (11) +#define USB_HRSTN_BIT (12) +#define HRSTN_BIT (13) +#define EMAC_HRSTN_BIT (17) +#define DDRC_HRSTN_BIT (19) +#define DMAC1_HRSTN_BIT (20) +#define BGM_HRSTN_BIT (22) +#define ADAPT_HRSTN_BIT (23) + +/* SWRST_APB_CTRL */ +#define ACODEC_PRSTN_BIT (0) +#define I2S_PRSTN_BIT (1) +#define UART1_PRSTN_BIT (2) +#define UART0_PRSTN_BIT (3) +#define SPI0_PRSTN_BIT (4) +#define SPI1_PRSTN_BIT (5) +#define GPIO0_PRSTN_BIT (6) +#define UART2_PRSTN_BIT (7) +#define I2C2_PRSTN_BIT (8) +#define I2C0_PRSTN_BIT (9) +#define I2C1_PRSTN_BIT (10) +#define TMR_PRSTN_BIT (11) +#define PWM_PRSTN_BIT (12) +#define MIPIW_PRSTN_BIT (13) +#define MIPIC_PRSTN_BIT (14) +#define RTC_PRSTN_BIT (15) +#define SADC_PRSTN_BIT (16) +#define EFUSE_PRSTN_BIT (17) +#define SPI2_PRSTN_BIT (18) +#define WDT_PRSTN_BIT (19) +#define GPIO1_PRSTN_BIT (20) + +/* timer clk fpga 1M,soc 50M*/ +#ifdef CONFIG_FPGA +#define TIMER_CLK (1000000) +#else +#define TIMER_CLK (50000000) +#endif + +#define UART1_TX_HW_HANDSHAKE (9) +#define UART1_RX_HW_HANDSHAKE (8) +#define UART2_TX_HW_HANDSHAKE (13) +#define UART2_RX_HW_HANDSHAKE (12) +#define UART1_DMA_TX_CHAN (4) +#define UART1_DMA_RX_CHAN (5) +#define UART2_DMA_TX_CHAN (4) +#define UART2_DMA_RX_CHAN (5) + +/*sdio*/ +#define SIMPLE_0 (0) +#define SIMPLE_22 (1) +#define SIMPLE_45 (2) +#define SIMPLE_67 (3) +#define SIMPLE_90 (4) +#define SIMPLE_112 (5) +#define SIMPLE_135 (6) +#define SIMPLE_157 (7) +#define SIMPLE_180 (8) +#define SIMPLE_202 (9) +#define SIMPLE_225 (10) +#define SIMPLE_247 (11) +#define SIMPLE_270 (12) +#define SIMPLE_292 (13) +#define SIMPLE_315 (14) +#define SIMPLE_337 (15) + + + +#define SDIO0_RST_BIT (~UL(1<<2)) +#define SDIO0_CLK_RATE (50000000) +#define SDIO0_CLK_DRV_SHIFT (20) +#define SDIO0_CLK_DRV_DEGREE (SIMPLE_180) +#define SDIO0_CLK_SAM_SHIFT (16) +#define SDIO0_CLK_SAM_DEGREE (SIMPLE_0) + + +#define SDIO1_RST_BIT (~UL(1<<1)) +#define SDIO1_CLK_RATE (50000000) +#define SDIO1_CLK_DRV_SHIFT (12) +#define SDIO1_CLK_DRV_DEGREE (SIMPLE_180) +#define SDIO1_CLK_SAM_SHIFT (8) +#define SDIO1_CLK_SAM_DEGREE (SIMPLE_0) + +#define SDC0_HRSTN (0x1<<2) +#define SDC1_HRSTN (0x1<<1) +#define SDC2_HRSTN (0) + + +/*usb*/ +#define IRQ_UHOST USBC_IRQ +#define FH_PA_OTG USBC_REG_BASE +#define IRQ_OTG IRQ_UHOST +#define FH_SZ_USBHOST SZ_1M +#define FH_SZ_OTG SZ_1M + +#define USB_UTMI_RST_BIT (0x1<<1) +#define USB_PHY_RST_BIT (0x11) +#define USB_SLEEP_MODE_BIT (0x1<<24) +#define USB_IDDQ_PWR_BIT (0x1<<10) + + +/* Specific Uart Number */ +#define FH_UART_NUMBER 3 +#define CLK_SCAN_BIT_POS (28) +#define INSIDE_PHY_ENABLE_BIT_POS (24) +#define MAC_REF_CLK_DIV_MASK (0x0f) +#define MAC_REF_CLK_DIV_BIT_POS (24) +#define MAC_PAD_RMII_CLK_MASK (0x0f) +#define MAC_PAD_RMII_CLK_BIT_POS (24) +#define MAC_PAD_MAC_REF_CLK_BIT_POS (28) +#define ETH_REF_CLK_OUT_GATE_BIT_POS (25) +#define ETH_RMII_CLK_OUT_GATE_BIT_POS (28) +#define IN_OR_OUT_PHY_SEL_BIT_POS (26) +#define INSIDE_CLK_GATE_BIT_POS (0) +#define INSIDE_PHY_SHUTDOWN_BIT_POS (31) +#define INSIDE_PHY_RST_BIT_POS (30) +#define INSIDE_PHY_TRAINING_BIT_POS (27) +#define INSIDE_PHY_TRAINING_MASK (0x0f) + +#define TRAINING_EFUSE_ACTIVE_BIT_POS 4 + +#endif /* __ASM_ARCH_HL_H */ diff --git a/arch/arm/mach-fh/fh8856v210/iopad.h b/arch/arm/mach-fh/fh8856v210/iopad.h new file mode 100644 index 00000000..ebc24024 --- /dev/null +++ b/arch/arm/mach-fh/fh8856v210/iopad.h @@ -0,0 +1,729 @@ +#include +#include +#include + +/* PINCTRL_FUNC */ +PINCTRL_FUNC(GPIO30, 0, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(GPIO31, 1, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(ETH_LINK_ACT, 1, FUNC1, PUPD_UP, 0); +PINCTRL_FUNC(GPIO32, 2, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(ETH_LINK_STA, 2, FUNC1, PUPD_UP, 0); +PINCTRL_FUNC(ETH_LINK_SPD, 2, FUNC2, PUPD_UP, 0); +PINCTRL_FUNC(UART0_TX, 3, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO33, 3, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART0_RX, 4, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO34, 4, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C0_SCL, 5, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(GPIO35, 5, FUNC1, PUPD_UP, 0); +PINCTRL_FUNC(I2C0_SDA, 6, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(GPIO36, 6, FUNC1, PUPD_UP, 0); +PINCTRL_FUNC(SENSOR_CLK, 7, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO12, 7, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO13, 8, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(UART1_TX, 9, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO39, 9, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CLK, 9, FUNC3, PUPD_NONE, 3); +PINCTRL_FUNC(TEST_O_INT_RMII_CLK, 9, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(UART1_RX, 10, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO40, 10, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 10, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_INT_RMII_TXD_0, 10, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(I2C1_SCL, 11, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO37, 11, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM2, 11, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CMD_RSP, 11, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CLK, 11, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_INT_RMII_TXD_1, 11, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(I2C1_SDA, 12, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO38, 12, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM3, 12, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_0, 12, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CSN_0, 12, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_INT_RMII_TXEN, 12, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_TX, 13, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO41, 13, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM4, 13, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_1, 13, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_TXD, 13, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_O_INT_RMII_RXD_0, 13, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_RX, 14, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO42, 14, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM5, 14, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_2, 14, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_RXD, 14, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_O_INT_RMII_RXD_1, 14, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(USB_PWREN, 15, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO47, 15, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_3, 15, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_O_INT_RMII_CRSDV, 15, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM0, 16, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO43, 16, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C2_SCL, 16, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_TX, 16, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_RMII_TXD_0, 16, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM1, 17, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO44, 17, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C2_SDA, 17, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_RX, 17, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_RMII_TXD_1, 17, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM2, 18, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO45, 18, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM3, 19, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO46, 19, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_RMII_CLK, 20, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO48, 20, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CLK, 20, FUNC2, PUPD_NONE, 3); +PINCTRL_FUNC(PWM2, 20, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_REF_CLK, 21, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(MAC_TXD_0, 22, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO49, 22, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 22, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM3, 22, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_TXD_1, 23, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO50, 23, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CMD_RSP, 23, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM4, 23, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_TXEN, 24, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO51, 24, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_0, 24, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM5, 24, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_RXD_0, 25, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO52, 25, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_1, 25, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM6, 25, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_RXD_1, 26, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO53, 26, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_2, 26, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM7, 26, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_RXDV, 27, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO54, 27, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_3, 27, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM8, 27, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_MDC, 28, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO55, 28, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM9, 28, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_MDIO, 29, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO56, 29, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CLK, 30, FUNC0, PUPD_NONE, 3); +PINCTRL_FUNC(GPIO57, 30, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C1_SCL, 30, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 31, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO58, 31, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C1_SDA, 31, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CMD_RSP, 32, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO59, 32, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART1_TX, 32, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_0, 33, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO60, 33, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART1_RX, 33, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_1, 34, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO61, 34, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_TX, 34, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_2, 35, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO62, 35, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_RX, 35, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_3, 36, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO63, 36, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TRSTN, 37, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO0, 37, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_I2S_DO, 37, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(DW_I2S_DO, 37, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SSI1_CLK, 37, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI2_CLK, 37, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_ADDAT, 37, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM6, 37, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_SMI_MDC, 37, FUNC8, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TDO, 38, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO1, 38, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_I2S_DI, 38, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(DW_I2S_DI, 38, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SSI1_CSN_0, 38, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI2_CSN_0, 38, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_DADAT, 38, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM7, 38, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_SMI_MDIO_I, 38, FUNC8, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TDI, 39, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO2, 39, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_I2S_CLK, 39, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(DW_I2S_CLK, 39, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SSI1_TXD, 39, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI2_TXD, 39, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_ADBCLK, 39, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM8, 39, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_SMI_MDIO_O, 39, FUNC8, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TCK, 40, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO3, 40, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_I2S_WS, 40, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(DW_I2S_WS, 40, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SSI1_RXD, 40, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI2_RXD, 40, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_ADLRC, 40, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM9, 40, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_I_INT_SMI_MDIO_I, 40, FUNC8, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TMS, 41, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO4, 41, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_MCLK, 41, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(USB_PWREN, 41, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 41, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_I_INT_SMI_MDC, 41, FUNC5, PUPD_NONE, 0); +PINCTRL_FUNC(SSI0_CLK, 42, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO5, 42, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_CLK, 42, FUNC4, PUPD_NONE, 3); +PINCTRL_FUNC(SSI0_CSN_0, 43, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO6, 43, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_CMD_RSP, 43, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI0_TXD, 44, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO7, 44, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_DATA_0, 44, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI0_RXD, 45, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO8, 45, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_DATA_1, 45, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI0_D2, 46, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO9, 46, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(UART1_TX, 46, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(I2C1_SCL, 46, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_DATA_2, 46, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI0_D3, 47, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO10, 47, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(UART1_RX, 47, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(I2C1_SDA, 47, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_DATA_3, 47, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CLK, 48, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO11, 48, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SSI2_CLK, 48, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CSN_0, 49, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO14, 49, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SSI2_CSN_0, 49, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_TXD, 50, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO15, 50, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SSI2_TXD, 50, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_RXD, 51, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO16, 51, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SSI2_RXD, 51, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_CD, 52, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO17, 52, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(ARC_JTAG_TRSTN, 52, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(PAE_JTAG_TRSTN, 52, FUNC4, PUPD_NONE, 0); +PINCTRL_FUNC(SD0_CLK, 53, FUNC0, PUPD_NONE, 3); +PINCTRL_FUNC(GPIO18, 53, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CLK, 53, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(ARC_JTAG_TDO, 53, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(PAE_JTAG_TDO, 53, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_CMD_RSP, 54, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO19, 54, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_TXD, 54, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(ARC_JTAG_TDI, 54, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(PAE_JTAG_TDI, 54, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_DATA_0, 55, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO20, 55, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_RXD, 55, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(ARC_JTAG_TCK, 55, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(PAE_JTAG_TCK, 55, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_DATA_1, 56, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO21, 56, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CSN_0, 56, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(ARC_JTAG_TMS, 56, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(PAE_JTAG_TMS, 56, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_DATA_2, 57, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO22, 57, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(UART2_TX, 57, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(I2C2_SCL, 57, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_DABCLK, 57, FUNC6, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_DATA_3, 58, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO23, 58, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CSN_0, 58, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(UART2_RX, 58, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(I2C2_SDA, 58, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_DALRC, 58, FUNC6, PUPD_NONE, 2); +PINCTRL_FUNC(SADC_XAIN0, 59, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO26, 59, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SADC_XAIN1, 60, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO27, 60, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SADC_XAIN2, 61, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO24, 61, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SADC_XAIN3, 62, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO25, 62, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO28, 63, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(ETH_LINK_ACT, 63, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(PWM10, 63, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(USB_DBG_CLK, 63, FUNC4, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 63, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_O_INT_RMII_TXEN, 63, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_MDC, 63, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO29, 64, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(ETH_LINK_STA, 64, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(PWM11, 64, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(RTC_CLK, 64, FUNC4, PUPD_NONE, 0); +PINCTRL_FUNC(ETH_LINK_SPD, 64, FUNC5, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_SMI_MDIO_OE, 64, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_MDIO, 64, FUNC7, PUPD_NONE, 0); + + +/* PINCTRL_MUX */ + +PINCTRL_MUX(AC_I2S_CLK, 0, &PAD39_AC_I2S_CLK); +PINCTRL_MUX(AC_I2S_DI, 0, &PAD38_AC_I2S_DI); +PINCTRL_MUX(AC_I2S_DO, 0, &PAD37_AC_I2S_DO); +PINCTRL_MUX(AC_I2S_WS, 0, &PAD40_AC_I2S_WS); +PINCTRL_MUX(AC_MCLK, 0, &PAD41_AC_MCLK); + +PINCTRL_MUX(ARC_JTAG_TCK, 0, &PAD55_ARC_JTAG_TCK); +PINCTRL_MUX(ARC_JTAG_TDI, 0, &PAD54_ARC_JTAG_TDI); +PINCTRL_MUX(ARC_JTAG_TDO, 0, &PAD53_ARC_JTAG_TDO); +PINCTRL_MUX(ARC_JTAG_TMS, 0, &PAD56_ARC_JTAG_TMS); +PINCTRL_MUX(ARC_JTAG_TRSTN, 0, &PAD52_ARC_JTAG_TRSTN); + +PINCTRL_MUX(ARM_JTAG_TCK, 0, &PAD40_ARM_JTAG_TCK); +PINCTRL_MUX(ARM_JTAG_TDI, 0, &PAD39_ARM_JTAG_TDI); +PINCTRL_MUX(ARM_JTAG_TDO, 0, &PAD38_ARM_JTAG_TDO); +PINCTRL_MUX(ARM_JTAG_TMS, 0, &PAD41_ARM_JTAG_TMS); +PINCTRL_MUX(ARM_JTAG_TRSTN, 0, &PAD37_ARM_JTAG_TRSTN); + +PINCTRL_MUX(DW_I2S_CLK, 0, &PAD39_DW_I2S_CLK); +PINCTRL_MUX(DW_I2S_DI, 0, &PAD38_DW_I2S_DI); +PINCTRL_MUX(DW_I2S_DO, 0, &PAD37_DW_I2S_DO); +PINCTRL_MUX(DW_I2S_WS, 0, &PAD40_DW_I2S_WS); + +PINCTRL_MUX(ETH_LINK_ACT, 1, &PAD1_ETH_LINK_ACT, + &PAD63_ETH_LINK_ACT); +PINCTRL_MUX(ETH_LINK_SPD, 1, &PAD2_ETH_LINK_SPD, + &PAD64_ETH_LINK_SPD); +PINCTRL_MUX(ETH_LINK_STA, 1, &PAD2_ETH_LINK_STA, + &PAD64_ETH_LINK_STA); + +PINCTRL_MUX(I2C0_SCL, 0, &PAD5_I2C0_SCL); +PINCTRL_MUX(I2C0_SDA, 0, &PAD6_I2C0_SDA); + +PINCTRL_MUX(I2C1_SCL, 2, &PAD11_I2C1_SCL, &PAD30_I2C1_SCL, &PAD46_I2C1_SCL); +PINCTRL_MUX(I2C1_SDA, 2, &PAD12_I2C1_SDA, &PAD31_I2C1_SDA, &PAD47_I2C1_SDA); + +PINCTRL_MUX(I2C2_SCL, 1, &PAD16_I2C2_SCL, &PAD57_I2C2_SCL); +PINCTRL_MUX(I2C2_SDA, 1, &PAD17_I2C2_SDA, &PAD58_I2C2_SDA); + +PINCTRL_MUX(MAC_MDC, 0, &PAD28_MAC_MDC, &PAD63_MAC_MDC); +PINCTRL_MUX(MAC_MDIO, 0, &PAD29_MAC_MDIO, &PAD64_MAC_MDIO); +PINCTRL_MUX(MAC_REF_CLK, 0, &PAD21_MAC_REF_CLK); +PINCTRL_MUX(MAC_RMII_CLK, 0, &PAD20_MAC_RMII_CLK); +PINCTRL_MUX(MAC_RXDV, 0, &PAD27_MAC_RXDV); +PINCTRL_MUX(MAC_RXD_0, 0, &PAD25_MAC_RXD_0); +PINCTRL_MUX(MAC_RXD_1, 0, &PAD26_MAC_RXD_1); +PINCTRL_MUX(MAC_TXD_0, 0, &PAD22_MAC_TXD_0); +PINCTRL_MUX(MAC_TXD_1, 0, &PAD23_MAC_TXD_1); +PINCTRL_MUX(MAC_TXEN, 0, &PAD24_MAC_TXEN); + +PINCTRL_MUX(PAE_JTAG_TCK, 0, &PAD55_PAE_JTAG_TCK); +PINCTRL_MUX(PAE_JTAG_TDI, 0, &PAD54_PAE_JTAG_TDI); +PINCTRL_MUX(PAE_JTAG_TDO, 0, &PAD53_PAE_JTAG_TDO); +PINCTRL_MUX(PAE_JTAG_TMS, 0, &PAD56_PAE_JTAG_TMS); +PINCTRL_MUX(PAE_JTAG_TRSTN, 0, &PAD52_PAE_JTAG_TRSTN); + +PINCTRL_MUX(PWM0, 0, &PAD16_PWM0); +PINCTRL_MUX(PWM1, 0, &PAD17_PWM1); +PINCTRL_MUX(PWM10, 0, &PAD63_PWM10); +PINCTRL_MUX(PWM11, 0, &PAD64_PWM11); +PINCTRL_MUX(PWM2, 0, &PAD11_PWM2, &PAD18_PWM2, &PAD20_PWM2); +PINCTRL_MUX(PWM3, 0, &PAD12_PWM3, &PAD19_PWM3, &PAD22_PWM3); +PINCTRL_MUX(PWM4, 0, &PAD13_PWM4, &PAD23_PWM4); +PINCTRL_MUX(PWM5, 0, &PAD14_PWM5, &PAD24_PWM5); +PINCTRL_MUX(PWM6, 1, &PAD25_PWM6, &PAD37_PWM6); +PINCTRL_MUX(PWM7, 1, &PAD26_PWM7, &PAD38_PWM7); +PINCTRL_MUX(PWM8, 1, &PAD27_PWM8, &PAD39_PWM8); +PINCTRL_MUX(PWM9, 1, &PAD28_PWM9, &PAD40_PWM9); + +PINCTRL_MUX(RTC_CLK, 0, &PAD64_RTC_CLK); + +PINCTRL_MUX(SADC_XAIN0, 0, &PAD59_SADC_XAIN0); +PINCTRL_MUX(SADC_XAIN1, 0, &PAD60_SADC_XAIN1); +PINCTRL_MUX(SADC_XAIN2, 0, &PAD61_SADC_XAIN2); +PINCTRL_MUX(SADC_XAIN3, 0, &PAD62_SADC_XAIN3); + +PINCTRL_MUX(SD0_CD, 0, &PAD52_SD0_CD); +PINCTRL_MUX(SD0_CLK, 0, &PAD53_SD0_CLK); +PINCTRL_MUX(SD0_CMD_RSP, 0, &PAD54_SD0_CMD_RSP); +PINCTRL_MUX(SD0_DATA_0, 0, &PAD55_SD0_DATA_0); +PINCTRL_MUX(SD0_DATA_1, 0, &PAD56_SD0_DATA_1); +PINCTRL_MUX(SD0_DATA_2, 0, &PAD57_SD0_DATA_2); +PINCTRL_MUX(SD0_DATA_3, 0, &PAD58_SD0_DATA_3); + +PINCTRL_MUX(SD1_CD, 0, &PAD10_SD1_CD, &PAD22_SD1_CD, &PAD31_SD1_CD, + &PAD41_SD1_CD, &PAD63_SD1_CD); +PINCTRL_MUX(SD1_CLK, 0, &PAD9_SD1_CLK, &PAD20_SD1_CLK, &PAD30_SD1_CLK, + &PAD42_SD1_CLK); +PINCTRL_MUX(SD1_CMD_RSP, 0, &PAD11_SD1_CMD_RSP, &PAD23_SD1_CMD_RSP, + &PAD32_SD1_CMD_RSP, &PAD43_SD1_CMD_RSP); +PINCTRL_MUX(SD1_DATA_0, 0, &PAD12_SD1_DATA_0, &PAD24_SD1_DATA_0, + &PAD33_SD1_DATA_0, &PAD44_SD1_DATA_0); +PINCTRL_MUX(SD1_DATA_1, 0, &PAD13_SD1_DATA_1, &PAD25_SD1_DATA_1, + &PAD34_SD1_DATA_1, &PAD45_SD1_DATA_1); +PINCTRL_MUX(SD1_DATA_2, 0, &PAD14_SD1_DATA_2, &PAD26_SD1_DATA_2, + &PAD35_SD1_DATA_2, &PAD46_SD1_DATA_2); +PINCTRL_MUX(SD1_DATA_3, 0, &PAD15_SD1_DATA_3, &PAD27_SD1_DATA_3, + &PAD36_SD1_DATA_3, &PAD47_SD1_DATA_3); + +PINCTRL_MUX(SENSOR_CLK, 0, &PAD7_SENSOR_CLK); + +PINCTRL_MUX(SSI0_CLK, 0, &PAD42_SSI0_CLK); +PINCTRL_MUX(SSI0_D2, 0, &PAD46_SSI0_D2); +PINCTRL_MUX(SSI0_D3, 0, &PAD47_SSI0_D3); +PINCTRL_MUX(SSI0_RXD, 0, &PAD45_SSI0_RXD); +PINCTRL_MUX(SSI0_TXD, 0, &PAD44_SSI0_TXD); + +PINCTRL_MUX(SSI1_CLK, 2, &PAD11_SSI1_CLK, &PAD37_SSI1_CLK, &PAD48_SSI1_CLK, + &PAD53_SSI1_CLK); +PINCTRL_MUX(SSI1_RXD, 2, &PAD14_SSI1_RXD, &PAD40_SSI1_RXD, &PAD51_SSI1_RXD, + &PAD55_SSI1_RXD); +PINCTRL_MUX(SSI1_TXD, 2, &PAD13_SSI1_TXD, &PAD39_SSI1_TXD, &PAD50_SSI1_TXD, + &PAD54_SSI1_TXD); + +PINCTRL_MUX(SSI2_CLK, 1, &PAD37_SSI2_CLK, &PAD48_SSI2_CLK); +PINCTRL_MUX(SSI2_CSN_0, 1, &PAD38_SSI2_CSN_0, &PAD49_SSI2_CSN_0); +PINCTRL_MUX(SSI2_RXD, 1, &PAD40_SSI2_RXD, &PAD51_SSI2_RXD); +PINCTRL_MUX(SSI2_TXD, 1, &PAD39_SSI2_TXD, &PAD50_SSI2_TXD); + +PINCTRL_MUX(UART0_RX, 0, &PAD4_UART0_RX); +PINCTRL_MUX(UART0_TX, 0, &PAD3_UART0_TX); + +PINCTRL_MUX(UART1_RX, 0, &PAD10_UART1_RX, &PAD33_UART1_RX, &PAD47_UART1_RX); +PINCTRL_MUX(UART1_TX, 0, &PAD9_UART1_TX, &PAD32_UART1_TX, &PAD46_UART1_TX); + +PINCTRL_MUX(UART2_RX, 0, &PAD14_UART2_RX, &PAD17_UART2_RX, &PAD35_UART2_RX, + &PAD58_UART2_RX); +PINCTRL_MUX(UART2_TX, 0, &PAD13_UART2_TX, &PAD16_UART2_TX, &PAD34_UART2_TX, + &PAD57_UART2_TX); + +PINCTRL_MUX(USB_PWREN, 0, &PAD15_USB_PWREN, &PAD41_USB_PWREN); + +PINCTRL_MUX(GPIO0, 0, &PAD37_GPIO0); +PINCTRL_MUX(GPIO1, 0, &PAD38_GPIO1); +PINCTRL_MUX(GPIO2, 0, &PAD39_GPIO2); +PINCTRL_MUX(GPIO3, 0, &PAD40_GPIO3); +PINCTRL_MUX(GPIO4, 0, &PAD41_GPIO4); +PINCTRL_MUX(GPIO5, 0, &PAD42_GPIO5); +PINCTRL_MUX(GPIO6, 0, &PAD43_GPIO6); +PINCTRL_MUX(GPIO7, 0, &PAD44_GPIO7); +PINCTRL_MUX(GPIO8, 0, &PAD45_GPIO8); +PINCTRL_MUX(GPIO9, 0, &PAD46_GPIO9); +PINCTRL_MUX(GPIO10, 0, &PAD47_GPIO10); +PINCTRL_MUX(GPIO11, 0, &PAD48_GPIO11); +PINCTRL_MUX(GPIO12, 0, &PAD7_GPIO12); +PINCTRL_MUX(GPIO13, 0, &PAD8_GPIO13); +PINCTRL_MUX(GPIO14, 0, &PAD49_GPIO14); +PINCTRL_MUX(GPIO15, 0, &PAD50_GPIO15); +PINCTRL_MUX(GPIO16, 0, &PAD51_GPIO16); +PINCTRL_MUX(GPIO17, 0, &PAD52_GPIO17); +PINCTRL_MUX(GPIO18, 0, &PAD53_GPIO18); +PINCTRL_MUX(GPIO19, 0, &PAD54_GPIO19); +PINCTRL_MUX(GPIO20, 0, &PAD55_GPIO20); +PINCTRL_MUX(GPIO21, 0, &PAD56_GPIO21); +PINCTRL_MUX(GPIO22, 0, &PAD57_GPIO22); +PINCTRL_MUX(GPIO23, 0, &PAD58_GPIO23); +PINCTRL_MUX(GPIO24, 0, &PAD61_GPIO24); +PINCTRL_MUX(GPIO25, 0, &PAD62_GPIO25); +PINCTRL_MUX(GPIO26, 0, &PAD59_GPIO26); +PINCTRL_MUX(GPIO27, 0, &PAD60_GPIO27); +PINCTRL_MUX(GPIO28, 0, &PAD63_GPIO28); +PINCTRL_MUX(GPIO29, 0, &PAD64_GPIO29); +PINCTRL_MUX(GPIO30, 0, &PAD0_GPIO30); +PINCTRL_MUX(GPIO31, 0, &PAD1_GPIO31); +PINCTRL_MUX(GPIO32, 0, &PAD2_GPIO32); +PINCTRL_MUX(GPIO33, 0, &PAD3_GPIO33); +PINCTRL_MUX(GPIO34, 0, &PAD4_GPIO34); +PINCTRL_MUX(GPIO35, 0, &PAD5_GPIO35); +PINCTRL_MUX(GPIO36, 0, &PAD6_GPIO36); +PINCTRL_MUX(GPIO37, 0, &PAD11_GPIO37); +PINCTRL_MUX(GPIO38, 0, &PAD12_GPIO38); +PINCTRL_MUX(GPIO39, 0, &PAD9_GPIO39); +PINCTRL_MUX(GPIO40, 0, &PAD10_GPIO40); +PINCTRL_MUX(GPIO41, 0, &PAD13_GPIO41); +PINCTRL_MUX(GPIO42, 0, &PAD14_GPIO42); +PINCTRL_MUX(GPIO43, 0, &PAD16_GPIO43); +PINCTRL_MUX(GPIO44, 0, &PAD17_GPIO44); +PINCTRL_MUX(GPIO45, 0, &PAD18_GPIO45); +PINCTRL_MUX(GPIO46, 0, &PAD19_GPIO46); +PINCTRL_MUX(GPIO47, 0, &PAD15_GPIO47); +PINCTRL_MUX(GPIO48, 0, &PAD20_GPIO48); +PINCTRL_MUX(GPIO49, 0, &PAD22_GPIO49); +PINCTRL_MUX(GPIO50, 0, &PAD23_GPIO50); +PINCTRL_MUX(GPIO51, 0, &PAD24_GPIO51); +PINCTRL_MUX(GPIO52, 0, &PAD25_GPIO52); +PINCTRL_MUX(GPIO53, 0, &PAD26_GPIO53); +PINCTRL_MUX(GPIO54, 0, &PAD27_GPIO54); +PINCTRL_MUX(GPIO55, 0, &PAD28_GPIO55); +PINCTRL_MUX(GPIO56, 0, &PAD29_GPIO56); +PINCTRL_MUX(GPIO57, 0, &PAD30_GPIO57); +PINCTRL_MUX(GPIO58, 0, &PAD31_GPIO58); +PINCTRL_MUX(GPIO59, 0, &PAD32_GPIO59); +PINCTRL_MUX(GPIO60, 0, &PAD33_GPIO60); +PINCTRL_MUX(GPIO61, 0, &PAD34_GPIO61); +PINCTRL_MUX(GPIO62, 0, &PAD35_GPIO62); +PINCTRL_MUX(GPIO63, 0, &PAD36_GPIO63); + +PINCTRL_MUX(SD1_CLK_EMMC, 3, &PAD9_SD1_CLK, &PAD20_SD1_CLK, &PAD30_SD1_CLK, + &PAD42_SD1_CLK); +PINCTRL_MUX(SD1_CMD_RSP_EMMC, 3, &PAD11_SD1_CMD_RSP, &PAD23_SD1_CMD_RSP, + &PAD32_SD1_CMD_RSP, &PAD43_SD1_CMD_RSP); +PINCTRL_MUX(SD1_DATA_0_EMMC, 3, &PAD12_SD1_DATA_0, &PAD24_SD1_DATA_0, + &PAD33_SD1_DATA_0, &PAD44_SD1_DATA_0); +PINCTRL_MUX(SD1_DATA_1_EMMC, 3, &PAD13_SD1_DATA_1, &PAD25_SD1_DATA_1, + &PAD34_SD1_DATA_1, &PAD45_SD1_DATA_1); +PINCTRL_MUX(SD1_DATA_2_EMMC, 3, &PAD14_SD1_DATA_2, &PAD26_SD1_DATA_2, + &PAD35_SD1_DATA_2, &PAD46_SD1_DATA_2); +PINCTRL_MUX(SD1_DATA_3_EMMC, 3, &PAD15_SD1_DATA_3, &PAD27_SD1_DATA_3, + &PAD36_SD1_DATA_3, &PAD47_SD1_DATA_3); + +/* PINCTRL_DEVICE */ +PINCTRL_DEVICE(ACI2S, 5, &MUX_AC_I2S_CLK, &MUX_AC_I2S_DI, &MUX_AC_I2S_DO, + &MUX_AC_I2S_WS, &MUX_AC_MCLK); +PINCTRL_DEVICE(AC_MCLK, 1, &MUX_AC_MCLK); +PINCTRL_DEVICE(ARCJTAG, 5, &MUX_ARC_JTAG_TCK, &MUX_ARC_JTAG_TDI, + &MUX_ARC_JTAG_TDO, &MUX_ARC_JTAG_TMS, &MUX_ARC_JTAG_TRSTN); +PINCTRL_DEVICE(ARMJTAG, 5, &MUX_ARM_JTAG_TCK, &MUX_ARM_JTAG_TDI, + &MUX_ARM_JTAG_TDO, &MUX_ARM_JTAG_TMS, &MUX_ARM_JTAG_TRSTN); +PINCTRL_DEVICE(DWI2S, 4, &MUX_DW_I2S_CLK, &MUX_DW_I2S_DI, &MUX_DW_I2S_DO, + &MUX_DW_I2S_WS); +PINCTRL_DEVICE(ETH, 2, &MUX_ETH_LINK_ACT, &MUX_ETH_LINK_STA); +PINCTRL_DEVICE(I2C0, 2, &MUX_I2C0_SCL, &MUX_I2C0_SDA); +PINCTRL_DEVICE(I2C1, 2, &MUX_I2C1_SCL, &MUX_I2C1_SDA); +PINCTRL_DEVICE(I2C2, 2, &MUX_I2C2_SCL, &MUX_I2C2_SDA); +PINCTRL_DEVICE(PAEJTAG, 5, &MUX_PAE_JTAG_TCK, &MUX_PAE_JTAG_TDI, + &MUX_PAE_JTAG_TDO, &MUX_PAE_JTAG_TMS, &MUX_PAE_JTAG_TRSTN); +PINCTRL_DEVICE(PWM0, 1, &MUX_PWM0); +PINCTRL_DEVICE(PWM1, 1, &MUX_PWM1); +PINCTRL_DEVICE(PWM10, 1, &MUX_PWM10); +PINCTRL_DEVICE(PWM11, 1, &MUX_PWM11); +PINCTRL_DEVICE(PWM2, 1, &MUX_PWM2); +PINCTRL_DEVICE(PWM3, 1, &MUX_PWM3); +PINCTRL_DEVICE(PWM4, 1, &MUX_PWM4); +PINCTRL_DEVICE(PWM5, 1, &MUX_PWM5); +PINCTRL_DEVICE(PWM6, 1, &MUX_PWM6); +PINCTRL_DEVICE(PWM7, 1, &MUX_PWM7); +PINCTRL_DEVICE(PWM8, 1, &MUX_PWM8); +PINCTRL_DEVICE(PWM9, 1, &MUX_PWM9); +PINCTRL_DEVICE(RMII, 10, &MUX_MAC_MDC, &MUX_MAC_MDIO, &MUX_MAC_REF_CLK, + &MUX_MAC_RMII_CLK, &MUX_MAC_RXDV, &MUX_MAC_RXD_0, &MUX_MAC_RXD_1, + &MUX_MAC_TXD_0, &MUX_MAC_TXD_1, &MUX_MAC_TXEN); +PINCTRL_DEVICE(RTC, 1, &MUX_RTC_CLK); +PINCTRL_DEVICE(SADC_XAIN0, 1, &MUX_SADC_XAIN0); +PINCTRL_DEVICE(SADC_XAIN1, 1, &MUX_SADC_XAIN1); +PINCTRL_DEVICE(SADC_XAIN2, 1, &MUX_SADC_XAIN2); +PINCTRL_DEVICE(SADC_XAIN3, 1, &MUX_SADC_XAIN3); +PINCTRL_DEVICE(SD0, 7, &MUX_SD0_CD, &MUX_SD0_CLK, &MUX_SD0_CMD_RSP, + &MUX_SD0_DATA_0, &MUX_SD0_DATA_1, &MUX_SD0_DATA_2, &MUX_SD0_DATA_3); +PINCTRL_DEVICE(SD0_1BIT_NO_WP, 4, &MUX_SD0_CD, &MUX_SD0_CLK, &MUX_SD0_CMD_RSP, + &MUX_SD0_DATA_0); +PINCTRL_DEVICE(SD0_NO_WP, 7, &MUX_SD0_CD, &MUX_SD0_CLK, &MUX_SD0_CMD_RSP, + &MUX_SD0_DATA_0, &MUX_SD0_DATA_1, &MUX_SD0_DATA_2, &MUX_SD0_DATA_3); +PINCTRL_DEVICE(SD0_WIFI, 6, &MUX_SD0_CLK, &MUX_SD0_CMD_RSP, &MUX_SD0_DATA_0, + &MUX_SD0_DATA_1, &MUX_SD0_DATA_2, &MUX_SD0_DATA_3); +PINCTRL_DEVICE(SD1, 7, &MUX_SD1_CD, &MUX_SD1_CLK, &MUX_SD1_CMD_RSP, + &MUX_SD1_DATA_0, &MUX_SD1_DATA_1, &MUX_SD1_DATA_2, &MUX_SD1_DATA_3); +PINCTRL_DEVICE(SD1_1BIT_NO_WP, 4, &MUX_SD1_CD, &MUX_SD1_CLK, &MUX_SD1_CMD_RSP, + &MUX_SD1_DATA_0); +PINCTRL_DEVICE(SD1_NO_WP, 7, &MUX_SD1_CD, &MUX_SD1_CLK, &MUX_SD1_CMD_RSP, + &MUX_SD1_DATA_0, &MUX_SD1_DATA_1, &MUX_SD1_DATA_2, &MUX_SD1_DATA_3); +PINCTRL_DEVICE(SD1_WIFI, 6, &MUX_SD1_CLK, &MUX_SD1_CMD_RSP, &MUX_SD1_DATA_0, + &MUX_SD1_DATA_1, &MUX_SD1_DATA_2, &MUX_SD1_DATA_3); +PINCTRL_DEVICE(SENSOR_CLK, 1, &MUX_SENSOR_CLK); +PINCTRL_DEVICE(SSI0, 4, &MUX_GPIO6, &MUX_SSI0_CLK, &MUX_SSI0_RXD, + &MUX_SSI0_TXD); +PINCTRL_DEVICE(SSI0_4BIT, 6, &MUX_GPIO6, &MUX_SSI0_CLK, &MUX_SSI0_D2, + &MUX_SSI0_D3, &MUX_SSI0_RXD, &MUX_SSI0_TXD); +PINCTRL_DEVICE(SSI1, 4, &MUX_GPIO14, &MUX_SSI1_CLK, &MUX_SSI1_RXD, + &MUX_SSI1_TXD); +PINCTRL_DEVICE(SSI2, 4, &MUX_SSI2_CLK, &MUX_SSI2_CSN_0, &MUX_SSI2_RXD, + &MUX_SSI2_TXD); +PINCTRL_DEVICE(UART0, 2, &MUX_UART0_RX, &MUX_UART0_TX); +PINCTRL_DEVICE(UART1, 2, &MUX_UART1_RX, &MUX_UART1_TX); +PINCTRL_DEVICE(UART2, 2, &MUX_UART2_RX, &MUX_UART2_TX); +PINCTRL_DEVICE(USB, 1, &MUX_USB_PWREN); +PINCTRL_DEVICE(GPIO0, 1, &MUX_GPIO0); +PINCTRL_DEVICE(GPIO1, 1, &MUX_GPIO1); +PINCTRL_DEVICE(GPIO2, 1, &MUX_GPIO2); +PINCTRL_DEVICE(GPIO3, 1, &MUX_GPIO3); +PINCTRL_DEVICE(GPIO4, 1, &MUX_GPIO4); +PINCTRL_DEVICE(GPIO5, 1, &MUX_GPIO5); +PINCTRL_DEVICE(GPIO6, 1, &MUX_GPIO6); +PINCTRL_DEVICE(GPIO7, 1, &MUX_GPIO7); +PINCTRL_DEVICE(GPIO8, 1, &MUX_GPIO8); +PINCTRL_DEVICE(GPIO9, 1, &MUX_GPIO9); +PINCTRL_DEVICE(GPIO10, 1, &MUX_GPIO10); +PINCTRL_DEVICE(GPIO11, 1, &MUX_GPIO11); +PINCTRL_DEVICE(GPIO12, 1, &MUX_GPIO12); +PINCTRL_DEVICE(GPIO13, 1, &MUX_GPIO13); +PINCTRL_DEVICE(GPIO14, 1, &MUX_GPIO14); +PINCTRL_DEVICE(GPIO15, 1, &MUX_GPIO15); +PINCTRL_DEVICE(GPIO16, 1, &MUX_GPIO16); +PINCTRL_DEVICE(GPIO17, 1, &MUX_GPIO17); +PINCTRL_DEVICE(GPIO18, 1, &MUX_GPIO18); +PINCTRL_DEVICE(GPIO19, 1, &MUX_GPIO19); +PINCTRL_DEVICE(GPIO20, 1, &MUX_GPIO20); +PINCTRL_DEVICE(GPIO21, 1, &MUX_GPIO21); +PINCTRL_DEVICE(GPIO22, 1, &MUX_GPIO22); +PINCTRL_DEVICE(GPIO23, 1, &MUX_GPIO23); +PINCTRL_DEVICE(GPIO24, 1, &MUX_GPIO24); +PINCTRL_DEVICE(GPIO25, 1, &MUX_GPIO25); +PINCTRL_DEVICE(GPIO26, 1, &MUX_GPIO26); +PINCTRL_DEVICE(GPIO27, 1, &MUX_GPIO27); +PINCTRL_DEVICE(GPIO28, 1, &MUX_GPIO28); +PINCTRL_DEVICE(GPIO29, 1, &MUX_GPIO29); +PINCTRL_DEVICE(GPIO30, 1, &MUX_GPIO30); +PINCTRL_DEVICE(GPIO31, 1, &MUX_GPIO31); +PINCTRL_DEVICE(GPIO32, 1, &MUX_GPIO32); +PINCTRL_DEVICE(GPIO33, 1, &MUX_GPIO33); +PINCTRL_DEVICE(GPIO34, 1, &MUX_GPIO34); +PINCTRL_DEVICE(GPIO35, 1, &MUX_GPIO35); +PINCTRL_DEVICE(GPIO36, 1, &MUX_GPIO36); +PINCTRL_DEVICE(GPIO37, 1, &MUX_GPIO37); +PINCTRL_DEVICE(GPIO38, 1, &MUX_GPIO38); +PINCTRL_DEVICE(GPIO39, 1, &MUX_GPIO39); +PINCTRL_DEVICE(GPIO40, 1, &MUX_GPIO40); +PINCTRL_DEVICE(GPIO41, 1, &MUX_GPIO41); +PINCTRL_DEVICE(GPIO42, 1, &MUX_GPIO42); +PINCTRL_DEVICE(GPIO43, 1, &MUX_GPIO43); +PINCTRL_DEVICE(GPIO44, 1, &MUX_GPIO44); +PINCTRL_DEVICE(GPIO45, 1, &MUX_GPIO45); +PINCTRL_DEVICE(GPIO46, 1, &MUX_GPIO46); +PINCTRL_DEVICE(GPIO47, 1, &MUX_GPIO47); +PINCTRL_DEVICE(GPIO48, 1, &MUX_GPIO48); +PINCTRL_DEVICE(GPIO49, 1, &MUX_GPIO49); +PINCTRL_DEVICE(GPIO50, 1, &MUX_GPIO50); +PINCTRL_DEVICE(GPIO51, 1, &MUX_GPIO51); +PINCTRL_DEVICE(GPIO52, 1, &MUX_GPIO52); +PINCTRL_DEVICE(GPIO53, 1, &MUX_GPIO53); +PINCTRL_DEVICE(GPIO54, 1, &MUX_GPIO54); +PINCTRL_DEVICE(GPIO55, 1, &MUX_GPIO55); +PINCTRL_DEVICE(GPIO56, 1, &MUX_GPIO56); +PINCTRL_DEVICE(GPIO57, 1, &MUX_GPIO57); +PINCTRL_DEVICE(GPIO58, 1, &MUX_GPIO58); +PINCTRL_DEVICE(GPIO59, 1, &MUX_GPIO59); +PINCTRL_DEVICE(GPIO60, 1, &MUX_GPIO60); +PINCTRL_DEVICE(GPIO61, 1, &MUX_GPIO61); +PINCTRL_DEVICE(GPIO62, 1, &MUX_GPIO62); +PINCTRL_DEVICE(GPIO63, 1, &MUX_GPIO63); + +PINCTRL_DEVICE(SD1_EMMC, 6, &MUX_SD1_CLK_EMMC, &MUX_SD1_CMD_RSP_EMMC, + &MUX_SD1_DATA_0_EMMC, &MUX_SD1_DATA_1_EMMC, &MUX_SD1_DATA_2_EMMC, + &MUX_SD1_DATA_3_EMMC); + +void fh_pinctrl_init_devicelist(OS_LIST *list) +{ + OS_LIST_EMPTY(list); + + /*PINCTRL_ADD_DEVICE*/ + PINCTRL_ADD_DEVICE(ACI2S); + PINCTRL_ADD_DEVICE(AC_MCLK); + PINCTRL_ADD_DEVICE(ARCJTAG); + PINCTRL_ADD_DEVICE(ARMJTAG); + PINCTRL_ADD_DEVICE(DWI2S); + PINCTRL_ADD_DEVICE(ETH); + PINCTRL_ADD_DEVICE(I2C0); + PINCTRL_ADD_DEVICE(I2C1); + PINCTRL_ADD_DEVICE(I2C2); + PINCTRL_ADD_DEVICE(PAEJTAG); + PINCTRL_ADD_DEVICE(PWM0); + PINCTRL_ADD_DEVICE(PWM1); + PINCTRL_ADD_DEVICE(PWM10); + PINCTRL_ADD_DEVICE(PWM11); + PINCTRL_ADD_DEVICE(PWM2); + PINCTRL_ADD_DEVICE(PWM3); + PINCTRL_ADD_DEVICE(PWM4); + PINCTRL_ADD_DEVICE(PWM5); + PINCTRL_ADD_DEVICE(PWM6); + PINCTRL_ADD_DEVICE(PWM7); + PINCTRL_ADD_DEVICE(PWM8); + PINCTRL_ADD_DEVICE(PWM9); + PINCTRL_ADD_DEVICE(RMII); + PINCTRL_ADD_DEVICE(RTC); + PINCTRL_ADD_DEVICE(SADC_XAIN0); + PINCTRL_ADD_DEVICE(SADC_XAIN1); + PINCTRL_ADD_DEVICE(SADC_XAIN2); + PINCTRL_ADD_DEVICE(SADC_XAIN3); + PINCTRL_ADD_DEVICE(SD0); + PINCTRL_ADD_DEVICE(SD0_1BIT_NO_WP); + PINCTRL_ADD_DEVICE(SD0_NO_WP); + PINCTRL_ADD_DEVICE(SD0_WIFI); + PINCTRL_ADD_DEVICE(SD1); + PINCTRL_ADD_DEVICE(SD1_1BIT_NO_WP); + PINCTRL_ADD_DEVICE(SD1_NO_WP); + PINCTRL_ADD_DEVICE(SD1_WIFI); + PINCTRL_ADD_DEVICE(SENSOR_CLK); + PINCTRL_ADD_DEVICE(SSI0); + PINCTRL_ADD_DEVICE(SSI0_4BIT); + PINCTRL_ADD_DEVICE(SSI1); + PINCTRL_ADD_DEVICE(SSI2); + PINCTRL_ADD_DEVICE(UART0); + PINCTRL_ADD_DEVICE(UART1); + PINCTRL_ADD_DEVICE(UART2); + PINCTRL_ADD_DEVICE(USB); + PINCTRL_ADD_DEVICE(GPIO0); + PINCTRL_ADD_DEVICE(GPIO1); + PINCTRL_ADD_DEVICE(GPIO2); + PINCTRL_ADD_DEVICE(GPIO3); + PINCTRL_ADD_DEVICE(GPIO4); + PINCTRL_ADD_DEVICE(GPIO5); + PINCTRL_ADD_DEVICE(GPIO6); + PINCTRL_ADD_DEVICE(GPIO7); + PINCTRL_ADD_DEVICE(GPIO8); + PINCTRL_ADD_DEVICE(GPIO9); + PINCTRL_ADD_DEVICE(GPIO10); + PINCTRL_ADD_DEVICE(GPIO11); + PINCTRL_ADD_DEVICE(GPIO12); + PINCTRL_ADD_DEVICE(GPIO13); + PINCTRL_ADD_DEVICE(GPIO14); + PINCTRL_ADD_DEVICE(GPIO15); + PINCTRL_ADD_DEVICE(GPIO16); + PINCTRL_ADD_DEVICE(GPIO17); + PINCTRL_ADD_DEVICE(GPIO18); + PINCTRL_ADD_DEVICE(GPIO19); + PINCTRL_ADD_DEVICE(GPIO20); + PINCTRL_ADD_DEVICE(GPIO21); + PINCTRL_ADD_DEVICE(GPIO22); + PINCTRL_ADD_DEVICE(GPIO23); + PINCTRL_ADD_DEVICE(GPIO24); + PINCTRL_ADD_DEVICE(GPIO25); + PINCTRL_ADD_DEVICE(GPIO26); + PINCTRL_ADD_DEVICE(GPIO27); + PINCTRL_ADD_DEVICE(GPIO28); + PINCTRL_ADD_DEVICE(GPIO29); + PINCTRL_ADD_DEVICE(GPIO30); + PINCTRL_ADD_DEVICE(GPIO31); + PINCTRL_ADD_DEVICE(GPIO32); + PINCTRL_ADD_DEVICE(GPIO33); + PINCTRL_ADD_DEVICE(GPIO34); + PINCTRL_ADD_DEVICE(GPIO35); + PINCTRL_ADD_DEVICE(GPIO36); + PINCTRL_ADD_DEVICE(GPIO37); + PINCTRL_ADD_DEVICE(GPIO38); + PINCTRL_ADD_DEVICE(GPIO39); + PINCTRL_ADD_DEVICE(GPIO40); + PINCTRL_ADD_DEVICE(GPIO41); + PINCTRL_ADD_DEVICE(GPIO42); + PINCTRL_ADD_DEVICE(GPIO43); + PINCTRL_ADD_DEVICE(GPIO44); + PINCTRL_ADD_DEVICE(GPIO45); + PINCTRL_ADD_DEVICE(GPIO46); + PINCTRL_ADD_DEVICE(GPIO47); + PINCTRL_ADD_DEVICE(GPIO48); + PINCTRL_ADD_DEVICE(GPIO49); + PINCTRL_ADD_DEVICE(GPIO50); + PINCTRL_ADD_DEVICE(GPIO51); + PINCTRL_ADD_DEVICE(GPIO52); + PINCTRL_ADD_DEVICE(GPIO53); + PINCTRL_ADD_DEVICE(GPIO54); + PINCTRL_ADD_DEVICE(GPIO55); + PINCTRL_ADD_DEVICE(GPIO56); + PINCTRL_ADD_DEVICE(GPIO57); + PINCTRL_ADD_DEVICE(GPIO58); + PINCTRL_ADD_DEVICE(GPIO59); + PINCTRL_ADD_DEVICE(GPIO60); + PINCTRL_ADD_DEVICE(GPIO61); + PINCTRL_ADD_DEVICE(GPIO62); + PINCTRL_ADD_DEVICE(GPIO63); + + PINCTRL_ADD_DEVICE(SD1_EMMC); +} + +char *fh_pinctrl_selected_devices[] = +{ + CONFIG_PINCTRL_SELECT +}; diff --git a/arch/arm/mach-fh/fh8858v200/Makefile b/arch/arm/mach-fh/fh8858v200/Makefile new file mode 100644 index 00000000..1443fdae --- /dev/null +++ b/arch/arm/mach-fh/fh8858v200/Makefile @@ -0,0 +1 @@ +obj-y += board.o chip.o \ No newline at end of file diff --git a/arch/arm/mach-fh/fh8858v200/board.c b/arch/arm/mach-fh/fh8858v200/board.c new file mode 100644 index 00000000..f6be0a53 --- /dev/null +++ b/arch/arm/mach-fh/fh8858v200/board.c @@ -0,0 +1,1123 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +struct uart_port fh_serial_ports[FH_UART_NUMBER]; + +static struct map_desc fh8858v200_io_desc[] = { + { + .virtual = VA_RAM_REG_BASE, + .pfn = __phys_to_pfn(RAM_BASE), + .length = SZ_16K, + .type = MT_MEMORY_RWX, + }, + { + .virtual = VA_DDRC_REG_BASE, + .pfn = __phys_to_pfn(DDRC_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_INTC_REG_BASE, + .pfn = __phys_to_pfn(INTC_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_TIMER_REG_BASE, + .pfn = __phys_to_pfn(TIMER_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_PMU_REG_BASE, + .pfn = __phys_to_pfn(PMU_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_UART0_REG_BASE, + .pfn = __phys_to_pfn(UART0_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_UART1_REG_BASE, + .pfn = __phys_to_pfn(UART1_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_UART2_REG_BASE, + .pfn = __phys_to_pfn(UART2_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + +}; + +static struct resource fh_gpio0_resources[] = { + { + .start = GPIO0_REG_BASE, + .end = GPIO0_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = GPIO0_IRQ, + .end = GPIO0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_gpio1_resources[] = { + { + .start = GPIO1_REG_BASE, + .end = GPIO1_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = GPIO1_IRQ, + .end = GPIO1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_uart0_resources[] = { + { + .start = (UART0_REG_BASE), + .end = (UART0_REG_BASE) + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = UART0_IRQ, + .end = UART0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_uart1_resources[] = { + { + .start = (UART1_REG_BASE), + .end = (UART1_REG_BASE) + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = UART1_IRQ, + .end = UART1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_uart2_resources[] = { + { + .start = (UART2_REG_BASE), + .end = (UART2_REG_BASE) + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = UART2_IRQ, + .end = UART2_IRQ, + .flags = IORESOURCE_IRQ, + } +}; +static struct resource fh_sdc0_resources[] = { + { + .start = SDC0_REG_BASE, + .end = SDC0_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SDC0_IRQ, + .end = SDC0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_sdc1_resources[] = { + { + .start = SDC1_REG_BASE, + .end = SDC1_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SDC1_IRQ, + .end = SDC1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_gmac_resources[] = { + { + .start = GMAC_REG_BASE, + .end = GMAC_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = GMAC_IRQ, + .end = GMAC_IRQ, + .flags = IORESOURCE_IRQ, + } +}; + +static struct resource fh_wdt_resources[] = { + { + .start = WDT_REG_BASE, + .end = WDT_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = WDT_IRQ, + .end = WDT_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +#ifdef CONFIG_FH_PERF_MON +static struct resource fh_perf_resources[] = { + { + .start = PMU_REG_BASE, + .end = PMU_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = PERF_IRQ, + .end = PERF_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +#endif + + +static struct fh_gmac_platform_data fh_gmac_data = { + .phy_reset_pin = 29, +}; + +static struct fh_uart_dma uart1_dma_info = { +#ifdef CONFIG_UART_TX_DMA + .tx_hs_no = UART1_TX_HW_HANDSHAKE, + .tx_dma_channel = UART1_DMA_TX_CHAN, +#endif + .rx_hs_no = UART1_RX_HW_HANDSHAKE, + .rx_dma_channel = UART1_DMA_RX_CHAN, + .rx_xmit_len = 16, +}; + +static struct fh_uart_dma uart2_dma_info = { +#ifdef CONFIG_UART_TX_DMA + .tx_hs_no = UART2_TX_HW_HANDSHAKE, + .tx_dma_channel = UART2_DMA_TX_CHAN, +#endif + .rx_hs_no = UART2_RX_HW_HANDSHAKE, + .rx_dma_channel = UART2_DMA_RX_CHAN, + .rx_xmit_len = 16, +}; + + +static struct fh_platform_uart fh_uart_platform_data[] = { + { + .mapbase = UART0_REG_BASE, + .fifo_size = 16, + .irq = UART0_IRQ, + .uartclk = 16666667, + .use_dma = 0, + .dma_info = NULL, + }, + { + .mapbase = UART1_REG_BASE, + .fifo_size = 32, + .irq = UART1_IRQ, + .uartclk = 16666667, + .use_dma = 0, + .dma_info = &uart1_dma_info, + }, + { + .mapbase = UART2_REG_BASE, + .fifo_size = 32, + .irq = UART2_IRQ, + .uartclk = 16666667, + .use_dma = 0, + .dma_info = &uart2_dma_info, + }, +}; + +static struct resource fh_pwm_resources[] = { + { + .start = PWM_REG_BASE, + .end = PWM_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = PWM_IRQ, + .end = PWM_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_i2c_resources_0[] = { + { + .start = I2C0_REG_BASE, + .end = I2C0_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = I2C0_IRQ, + .end = I2C0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_i2c_resources_1[] = { + { + .start = I2C1_REG_BASE, + .end = I2C1_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = I2C1_IRQ, + .end = I2C1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_i2c_resources_2[] = { + { + .start = I2C2_REG_BASE, + .end = I2C2_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = I2C2_IRQ, + .end = I2C2_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_rtc_resources[] = { + { + .start = RTC_REG_BASE, + .end = RTC_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = RTC_IRQ, + .end = RTC_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct fh_gpio_chip fh_gpio0_chip = { + .chip = { + .owner = THIS_MODULE, + .label = "FH_GPIO0", + .base = 0, + .ngpio = 32, + }, +}; + +static struct fh_gpio_chip fh_gpio1_chip = { + .chip = { + .owner = THIS_MODULE, + .label = "FH_GPIO1", + .base = 32, + .ngpio = 32, + }, +}; + +static struct fh_pwm_data pwm_data = { + .npwm = 12, +}; + +static struct resource fh_sadc_resources[] = { + { + .start = SADC_REG_BASE, + .end = SADC_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SADC_IRQ, + .end = SADC_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_aes_resources[] = { + { + .start = AES_REG_BASE, + .end = AES_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = AES_IRQ, + .end = AES_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_efuse_resources[] = { + { + .start = EFUSE_REG_BASE, + .end = EFUSE_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, +}; + + +static struct resource fh_axi_dma_resources[] = { + { + .start = (DMAC_REG_BASE), + .end = (DMAC_REG_BASE) + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = DMAC0_IRQ, + .end = DMAC0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + + +static struct resource fh_spi0_resources[] = { + { + .start = SPI0_REG_BASE, + .end = SPI0_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SPI0_IRQ, + .end = SPI0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_spi1_resources[] = { + { + .start = SPI1_REG_BASE, + .end = SPI1_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SPI1_IRQ, + .end = SPI1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_spi2_resources[] = { + { + .start = SPI2_REG_BASE, + .end = SPI2_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + .name = "fh spi2 mem", + }, + { + .start = SPI2_IRQ, + .end = SPI2_IRQ, + .flags = IORESOURCE_IRQ, + .name = "fh spi2 irq", + }, +}; + +static struct resource fh_usb_resources[] = { + { + .start = USBC_REG_BASE, + .end = USBC_REG_BASE + SZ_1M - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = USBC_IRQ, + .end = USBC_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static unsigned int fh_mci_sys_card_detect_fixed(struct fhmci_host *host) +{ + return 0; +} + +struct fh_mci_board fh_mci = { + .num_slots = 1, + .get_cd = fh_mci_sys_card_detect_fixed, + .bus_hz = 50000000, + .detect_delay_ms = 200, + .caps = MMC_CAP_4_BIT_DATA, + /*8:180 degree*/ + .drv_degree = 8, + .sam_degree = 0, + .rescan_max_num = 2, +}; + +struct fh_mci_board fh_mci_sd = { + .num_slots = 1, + .bus_hz = 50000000, + .detect_delay_ms = 200, + .caps = MMC_CAP_4_BIT_DATA, + /*8:180 degree*/ + .drv_degree = 8, + .sam_degree = 0, +}; + +static struct platform_device fh_gmac_device = { + .name = "fh_gmac", + .id = 0, + .num_resources = ARRAY_SIZE(fh_gmac_resources), + .resource = fh_gmac_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &fh_gmac_data, + }, +}; + +struct platform_device fh_sd0_device = { + .name = "fh_mci", + .id = 0, + .num_resources = ARRAY_SIZE(fh_sdc0_resources), + .resource = fh_sdc0_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &fh_mci_sd, + } +}; + +struct platform_device fh_sd1_device = { + .name = "fh_mci", + .id = 1, + .num_resources = ARRAY_SIZE(fh_sdc1_resources), + .resource = fh_sdc1_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &fh_mci, + } +}; + +struct fh_sadc_platform_data fh_sadc_data = { + .ref_vol = 1800, + .active_bit = 0xfff, +}; + +static struct platform_device fh_sadc_device = { + .name = "fh_sadc", + .id = 0, + .num_resources = ARRAY_SIZE(fh_sadc_resources), + .resource = fh_sadc_resources, + .dev = { + .platform_data = &fh_sadc_data, + }, +}; + +static struct platform_device fh_uart0_device = { + .name = "ttyS", + .id = 0, + .num_resources = ARRAY_SIZE(fh_uart0_resources), + .resource = fh_uart0_resources, + .dev.platform_data = &fh_uart_platform_data[0], +}; + +static struct platform_device fh_uart1_device = { + .name = "ttyS", + .id = 1, + .num_resources = ARRAY_SIZE(fh_uart1_resources), + .resource = fh_uart1_resources, + .dev.platform_data = &fh_uart_platform_data[1], +}; + +static struct platform_device fh_uart2_device = { + .name = "ttyS", + .id = 2, + .num_resources = ARRAY_SIZE(fh_uart2_resources), + .resource = fh_uart2_resources, + .dev.platform_data = &fh_uart_platform_data[2], +}; + +static struct platform_device fh_pinctrl_device = { + .name = "fh_pinctrl", + .id = 0, +}; + +static struct platform_device fh_i2c0_device = { + .name = "fh_i2c", + .id = 0, + .num_resources = ARRAY_SIZE(fh_i2c_resources_0), + .resource = fh_i2c_resources_0, +}; + +static struct platform_device fh_i2c1_device = { + .name = "fh_i2c", + .id = 1, + .num_resources = ARRAY_SIZE(fh_i2c_resources_1), + .resource = fh_i2c_resources_1, +}; + +static struct platform_device fh_i2c2_device = { + .name = "fh_i2c", + .id = 2, + .num_resources = ARRAY_SIZE(fh_i2c_resources_2), + .resource = fh_i2c_resources_2, +}; + +static struct fh_rtc_plat_data rtc_plat_data[] = { + { + .lut_cof = 58, + .lut_offset = 0xff, + .tsensor_cp_default_out = 0x993, + .clk_name = "rtc_hclk_gate", + }, + { + .lut_cof = 71, + .lut_offset = 0xf6, + .tsensor_cp_default_out = 0x9cc, + .clk_name = "rtc_hclk_gate", + } +}; + +static struct platform_device fh_rtc_device = { + .name = "fh_rtc", + .id = 0, + .num_resources = ARRAY_SIZE(fh_rtc_resources), + .resource = fh_rtc_resources, + .dev.platform_data = &rtc_plat_data[0], +}; + +static struct resource fh_i2s_resources[] = { + { + .start = I2S_REG_BASE, + .end = I2S_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = ACW_REG_BASE, + .end = ACW_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = I2S0_IRQ, + .end = I2S0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct fh_i2s_platform_data fh_i2s_data = { + .dma_capture_channel = 4, + .dma_playback_channel = 5, + .dma_master = 0, + .dma_rx_hs_num = 10, + .dma_tx_hs_num = 11, + .clk = "i2s_clk", + .acodec_mclk = "ac_clk", +}; + +static struct platform_device fh_i2s_device = { + .name = "fh_audio", + .id = 0, + .num_resources = ARRAY_SIZE(fh_i2s_resources), + .resource = fh_i2s_resources, + .dev = { + .platform_data = &fh_i2s_data, + }, +}; + +static struct platform_device fh_gpio0_device = { + .name = GPIO_NAME, + .id = 0, + .num_resources = ARRAY_SIZE(fh_gpio0_resources), + .resource = fh_gpio0_resources, + .dev = { + .platform_data = &fh_gpio0_chip, + }, +}; + +static struct platform_device fh_gpio1_device = { + .name = GPIO_NAME, + .id = 1, + .num_resources = ARRAY_SIZE(fh_gpio1_resources), + .resource = fh_gpio1_resources, + .dev = { + .platform_data = &fh_gpio1_chip, + }, +}; + +static struct platform_device fh_aes_device = { + .name = "fh_aes", + .id = 0, + .num_resources = ARRAY_SIZE(fh_aes_resources), + .resource = fh_aes_resources, + .dev = { + .platform_data = NULL, + }, +}; + +struct fh_efuse_platform_data fh_efuse_plat_data = { + .efuse_support_flag = CRYPTO_CPU_SET_KEY | + CRYPTO_EX_MEM_SET_KEY | + CRYPTO_EX_MEM_SWITCH_KEY | + CRYPTO_EX_MEM_4_ENTRY_1_KEY | + CRYPTO_EX_MEM_INDEP_POWER, +}; + + + +#define FH_SPI0_CS0 (6) +#define FH_SPI0_CS1 (55) + +#define FH_SPI1_CS0 (14) +#define FH_SPI1_CS1 (57) + +#define SPI0_FIFO_DEPTH (128) +#define SPI0_CLK_IN (200000000) +#define SPI0_MAX_SLAVE_NO (2) +#define SPI0_DMA_RX_CHANNEL (0) +#define SPI0_DMA_TX_CHANNEL (1) + +#define SPI1_FIFO_DEPTH (64) +#define SPI1_CLK_IN (100000000) +#define SPI1_MAX_SLAVE_NO (2) +#define SPI1_DMA_RX_CHANNEL (2) +#define SPI1_DMA_TX_CHANNEL (3) + +#define SPI2_CLK_IN (100000000) + +/* SPI_TRANSFER_USE_DMA */ +static struct fh_spi_platform_data fh_spi0_data = { + .bus_no = 0, + .apb_clock_in = SPI0_CLK_IN, + .clock_source = {100000000, 150000000, 200000000}, + .clock_source_num = 3, + .slave_max_num = SPI0_MAX_SLAVE_NO, + .cs_data[0].GPIO_Pin = FH_SPI0_CS0, + .cs_data[0].name = "spi0_cs0", + .cs_data[1].GPIO_Pin = FH_SPI0_CS1, + .cs_data[1].name = "spi0_cs1", + .clk_name = "spi0_clk", + .dma_transfer_enable = SPI_TRANSFER_USE_DMA, + .rx_dma_channel = SPI0_DMA_RX_CHANNEL, + .rx_handshake_num = 4, + /*dma use inc mode could move data by burst mode...*/ + /*or move data use single mode with low efficient*/ + .ctl_wire_support = ONE_WIRE_SUPPORT | DUAL_WIRE_SUPPORT | + MULTI_WIRE_SUPPORT, +}; + +static struct fh_spi_platform_data fh_spi1_data = { + .bus_no = 1, + .apb_clock_in = SPI1_CLK_IN, + .clock_source = {SPI1_CLK_IN}, + .clock_source_num = 1, + .slave_max_num = SPI1_MAX_SLAVE_NO, + .cs_data[0].GPIO_Pin = FH_SPI1_CS0, + .cs_data[0].name = "spi1_cs0", + .cs_data[1].GPIO_Pin = FH_SPI1_CS1, + .cs_data[1].name = "spi1_cs1", + .clk_name = "spi1_clk", + .ctl_wire_support = 0, +}; + +static struct fh_spi_platform_data fh_spi2_data = { + .apb_clock_in = SPI2_CLK_IN, + .dma_transfer_enable = 0, + .rx_handshake_num = 12, + .clk_name = "spi2_clk", + .ctl_wire_support = 0, +}; + +static struct platform_device fh_efuse_device = { + .name = "fh_efuse", + .id = 0, + .num_resources = ARRAY_SIZE(fh_efuse_resources), + .resource = fh_efuse_resources, + .dev = { + .platform_data = &fh_efuse_plat_data, + }, +}; + +struct fh_axi_dma_platform_data axi_dma_plat_data = { + .chan_priority = CHAN_PRIORITY_ASCENDING, + .clk_name = "ahb_clk", +}; + +static struct platform_device fh_axi_dma_device = { + .name = "fh_axi_dmac", + .id = 0, + .num_resources = ARRAY_SIZE(fh_axi_dma_resources), + .resource = fh_axi_dma_resources, + .dev = { + .platform_data = &axi_dma_plat_data, + }, +}; + +static struct platform_device fh_spi0_device = { + .name = "fh_spi", + .id = 0, + .num_resources = ARRAY_SIZE(fh_spi0_resources), + .resource = fh_spi0_resources, + .dev = { + .platform_data = &fh_spi0_data, + }, +}; + +static struct platform_device fh_spi1_device = { + .name = "fh_spi", + .id = 1, + .num_resources = ARRAY_SIZE(fh_spi1_resources), + .resource = fh_spi1_resources, + .dev = { + .platform_data = &fh_spi1_data, + }, +}; + +static struct platform_device fh_spi2_device = { + .name = "fh_spi_slave", + .id = 0, + .num_resources = ARRAY_SIZE(fh_spi2_resources), + .resource = fh_spi2_resources, + .dev = { + .platform_data = &fh_spi2_data, + }, +}; + +#ifdef CONFIG_FH_PERF_MON +static struct platform_device fh_perf_device = { + .name = "fh_perf_mon", + .id = 0, + .num_resources = ARRAY_SIZE(fh_perf_resources), + .resource = fh_perf_resources, + .dev = { + .platform_data = NULL, + }, +}; +#endif + + +static struct fh_wdt_platform_data fh_wdt_data = { + .mode = MODE_DISCRETE, +}; + +struct platform_device fh_wdt_device = { + .name = "fh_wdt", + .id = 0, + .num_resources = ARRAY_SIZE(fh_wdt_resources), + .resource = fh_wdt_resources, + .dev = { + .platform_data = &fh_wdt_data, + } +}; + +static struct platform_device fh_pwm_device = { + .name = "fh_pwm", + .id = 0, + .num_resources = ARRAY_SIZE(fh_pwm_resources), + .resource = fh_pwm_resources, + .dev = { + .platform_data = &pwm_data, + }, +}; + +static struct fh_usb_platform_data fh_usb_data = { + .dr_mode = "host", + .vbus_pwren = 47, +}; + +struct platform_device fh_usb_device = { + .name = "fh_usb", + .id = 0, + .num_resources = ARRAY_SIZE(fh_usb_resources), + .resource = fh_usb_resources, + .dev = { + .platform_data = &fh_usb_data, + } +}; + +#ifdef CONFIG_FH_TSENSOR +struct platform_device fh_tsensor_device = { + .name = "fh_tsensor", + .id = 0, +}; +#endif + +static struct platform_device *fh8858v200_devices[] __initdata = { + &fh_uart0_device, + &fh_uart1_device, + &fh_uart2_device, + &fh_pinctrl_device, + &fh_i2c0_device, + &fh_i2c1_device, + &fh_i2c2_device, + &fh_rtc_device, + &fh_sd0_device, + &fh_sd1_device, + &fh_sadc_device, + &fh_gmac_device, + &fh_gpio0_device, + &fh_gpio1_device, + &fh_aes_device, + &fh_efuse_device, + &fh_axi_dma_device, + &fh_spi0_device, + &fh_spi1_device, + &fh_spi2_device, + &fh_i2s_device, + &fh_pwm_device, + &fh_wdt_device, + &fh_usb_device, +#ifdef CONFIG_FH_PERF_MON + &fh_perf_device, +#endif +#ifdef CONFIG_FH_TSENSOR + &fh_tsensor_device, +#endif +}; + +static struct mtd_partition fh_sf_parts[] = { + { + /* head & Ramboot */ + .name = "bootstrap", + .offset = 0, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + /* Ramboot & U-Boot environment */ + .name = "uboot-env", + .offset = MTDPART_OFS_APPEND, + .size = SZ_64K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + /* U-Boot */ + .name = "uboot", + .offset = MTDPART_OFS_APPEND, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_4M, + .mask_flags = 0, + }, { + .name = "rootfs", + .offset = MTDPART_OFS_APPEND, + .size = SZ_8M, + .mask_flags = 0, + }, { + .name = "app", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + } + /* mtdparts= + * spi_flash:256k(bootstrap), + * 64k(u-boot-env), + * 192k(u-boot),4M(kernel), + * 8M(rootfs), + * -(app) */ + /* two blocks with bad block table (and mirror) at the end */ +}; +#ifdef CONFIG_MTD_SPI_NAND +static struct mtd_partition fh_sf_nand_parts[] = { + { + /* head & Ramboot */ + .name = "bootstrap", + .offset = 0, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + .name = "uboot-env", + .offset = MTDPART_OFS_APPEND, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "uboot", + .offset = MTDPART_OFS_APPEND, + .size = SZ_512K, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_4M, + .mask_flags = 0, + }, { + .name = "rootfs", + .offset = MTDPART_OFS_APPEND, + .size = SZ_8M, + .mask_flags = 0, + }, { + .name = "app", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + } + /* mtdparts= + * spi0.0:64k(bootstrap), + * 64k(u-boot-env), + * 192k(u-boot), + * 4M(kernel), + * 8M(rootfs), + * -(app) + * two blocks with bad block table (and mirror) at the end + */ +}; +#endif + +static struct flash_platform_data fh_flash_platform_data = { + .name = "spi_flash", + .parts = fh_sf_parts, + .nr_parts = ARRAY_SIZE(fh_sf_parts), +}; +#ifdef CONFIG_MTD_SPI_NAND +static struct flash_platform_data fh_nandflash_platform_data = { + .name = "spi_nandflash", + .parts = fh_sf_nand_parts, + .nr_parts = ARRAY_SIZE(fh_sf_nand_parts), +}; +#endif + +static struct spi_board_info fh_spi_devices[] = { +#ifdef CONFIG_MTD_SPI_NAND + { + .modalias = "spi-nand", + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 50000000, + .mode = SPI_MODE_3, + .platform_data = &fh_nandflash_platform_data, + }, +#endif + { + .modalias = "m25p80", + .bus_num = 0, + .chip_select = 0, + /* multi wire should adapt spi para 'ctl_wire_support'*/ + .mode = SPI_MODE_3 | SPI_RX_DUAL, + .max_speed_hz = 50000000, + .platform_data = &fh_flash_platform_data, + }, + +}; + +extern void early_print(const char *str, ...); + +static void __init fh_console_pre_init(struct fh_platform_uart *plat, int num) +{ + int idx = 0; + + for (; idx < num; idx++) { + struct uart_port *port; + + port = &fh_serial_ports[idx]; + port->mapbase = plat[idx].mapbase; + port->fifosize = plat[idx].fifo_size; + port->uartclk = plat[idx].uartclk; + + switch (idx) { + case 0: + port->membase = (unsigned char *)VA_UART0_REG_BASE; + break; + case 1: + port->membase = (unsigned char *)VA_UART1_REG_BASE; + break; + case 2: + port->membase = (unsigned char *)VA_UART2_REG_BASE; + break; + default: + break; + } + } +} + +static void __init fh8858v200_map_io(void) +{ + iotable_init(fh8858v200_io_desc, ARRAY_SIZE(fh8858v200_io_desc)); + fh_console_pre_init(fh_uart_platform_data, + ARRAY_SIZE(fh_uart_platform_data)); +} + + +static __init void fh8858v200_board_init(void) +{ + if (fh_is_8858v210()) + fh_rtc_device.dev.platform_data = &rtc_plat_data[1]; + platform_add_devices(fh8858v200_devices, + ARRAY_SIZE(fh8858v200_devices)); + spi_register_board_info(fh_spi_devices, ARRAY_SIZE(fh_spi_devices)); +} +void __init fh_timer_init_no_of(unsigned int iovbase, + unsigned int irqno); + +static void __init fh8858v200_init_early(void) +{ + fh_pmu_init(); + fh_pinctrl_init(VA_PMU_REG_BASE + 0x80); +} + +static void __init fh_time_init(void) +{ + unsigned int vtimerbase = (unsigned int)ioremap(TIMER_REG_BASE, SZ_4K); + + fh_clk_init(); + fh_timer_init_no_of(vtimerbase, TMR0_IRQ); + +} + +void __init fh_intc_init_no_of(unsigned int iovbase); +static void __init fh_intc_init(void) +{ + unsigned int vintcbase = (unsigned int)ioremap(INTC_REG_BASE, SZ_4K); + + fh_intc_init_no_of(vintcbase); + +} +static void fh8858v200_restart + (enum reboot_mode mode, const char *cmd) +{ + fh_pmu_restart(); +} + + +MACHINE_START(FH8858V200, "FH8858V200") + .atag_offset = 0x100, + .map_io = fh8858v200_map_io, + .init_irq = fh_intc_init, + .init_time = fh_time_init, + .init_machine = fh8858v200_board_init, + .init_early = fh8858v200_init_early, + .restart = fh8858v200_restart, +MACHINE_END + diff --git a/arch/arm/mach-fh/fh8858v200/board_config.fh8858v200.appboard b/arch/arm/mach-fh/fh8858v200/board_config.fh8858v200.appboard new file mode 100644 index 00000000..335a1304 --- /dev/null +++ b/arch/arm/mach-fh/fh8858v200/board_config.fh8858v200.appboard @@ -0,0 +1,45 @@ +#ifndef BOARD_CONFIG_H_ +#define BOARD_CONFIG_H_ + +/* + * GPIO0 -> IRCUT_ON + * GPIO1 -> IRCUT_OFF + * GPIO2 -> USB_PWREN + * GPIO11 -> EMAC PHY Reset + * GPIO12 -> CIS_CLK + * GPIO13 -> CIS_RSTN + * GPIO14 -> CIS_PDN + * GPIO19 -> SD1_PWREN/WIFI_REG_ON + * GPIO20 -> AK7755 Reset + * GPIO24 -> LED0 + * GPIO25 -> LED1 + * GPIO26 -> Reset Configs + * GPIO27 -> AK7755 PowerDown + * GPIO28 -> IR + * GPIO53 -> USB_PWREN/SD0_PWREN + * GPIO55 -> SD1 WIFI Interrupt + */ + +#define CONFIG_SD_CD_FIXED + +#define CONFIG_ISP_CLK_RATE 200000000 +#define CONFIG_JPEG_CLK_RATE 200000000 +#define CONFIG_VEU_CLK_RATE 300000000 + +#define USB_VBUS_PWR_GPIO (47) + +#define ETH_GPIO "ETH", "GPIO48", "GPIO49", "GPIO50", "GPIO51", "GPIO52",\ + "GPIO53", "GPIO54", "GPIO55", "GPIO56" + +#define CONFIG_PINCTRL_SELECT \ + "I2C0", "PWM2", "PWM3", "PWM4", "PWM5", "PWM6", "PWM7", \ + "PWM8", "PWM9", "SADC_XAIN0", "SADC_XAIN1", \ + "SADC_XAIN2", "SADC_XAIN3", "SD0_NO_WP", "SD1_NO_WP", \ + "SENSOR_CLK", "SSI0_4BIT", "UART0", "UART1", "GPIO4", \ + "GPIO13", "GPIO14", "GPIO15", ETH_GPIO, \ + "GPIO30", "GPIO31", "GPIO32", "GPIO43", "GPIO44", \ + "GPIO47", \ +\ + "GPIO11", "GPIO16", "GPIO45", "GPIO46" + +#endif /* BOARD_CONFIG_H_ */ diff --git a/arch/arm/mach-fh/fh8858v200/chip.c b/arch/arm/mach-fh/fh8858v200/chip.c new file mode 100644 index 00000000..9bbb3c49 --- /dev/null +++ b/arch/arm/mach-fh/fh8858v200/chip.c @@ -0,0 +1,747 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * external oscillator + * fixed to 24M + */ +static struct fh_clk osc_clk = { + .name = "osc_clk", + .frequency = OSC_FREQUENCY, + .flag = CLOCK_FIXED, +}; + +/* + * phase-locked-loop device, + * generates a higher frequency clock + * from the external oscillator reference + *PLL_DDR + */ + +static struct fh_clk pll_ddr_rclk = { + .name = "pll_ddr_rclk", + .flag = CLOCK_PLL_R|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL0, + .en_reg_offset = REG_PMU_PLL0_CTRL, + .en_reg_mask = 0xf000, +}; + +/*PLL_CPU*/ +static struct fh_clk pll_cpu_pclk = { + .name = "pll_cpu_pclk", + .flag = CLOCK_PLL_P|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL1, + .en_reg_offset = REG_PMU_PLL1_CTRL, + .en_reg_mask = 0xf00, +}; + +static struct fh_clk pll_cpu_rclk = { + .name = "pll_cpu_rclk", + .flag = CLOCK_PLL_R|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL1, + .en_reg_offset = REG_PMU_PLL1_CTRL, + .en_reg_mask = 0xf000, +}; + +/*PLL_SYS*/ +static struct fh_clk pll_sys_pclk = { + .name = "pll_sys_pclk", + .flag = CLOCK_PLL_P|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL2, + .en_reg_offset = REG_PMU_PLL2_CTRL, + .en_reg_mask = 0xf00, +}; + + +static struct fh_clk pll_sys_rclk = { + .name = "pll_sys_rclk", + .flag = CLOCK_PLL_R|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL2, + .en_reg_offset = REG_PMU_PLL2_CTRL, + .en_reg_mask = 0xf000, +}; + +static struct fh_clk pllsysp_div12_clk = { + .name = "pllsysp_div12_clk", + .flag = CLOCK_NORESET|CLOCK_NOGATE, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV5, + .div_reg_mask = 0xf000000, +}; + +static struct fh_clk ddr_clk = { + .name = "ddr_clk", + .flag = CLOCK_NODIV, + .parent = {&pll_ddr_rclk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x4000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x8, +}; +static struct fh_clk arm_clk = { + .name = "arm_clk", + .flag = CLOCK_MULTI_PARENT|CLOCK_NOGATE|CLOCK_NODIV, + .parent = {&osc_clk, &pll_cpu_pclk}, + .prediv = 1, + .sel_reg_offset = REG_PMU_SYS_CTRL, + .sel_reg_mask = 0x1, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x1, +}; +static struct fh_clk arc_clk = { + .name = "arc_clk", + .flag = CLOCK_MULTI_PARENT|CLOCK_NODIV, + .parent = {&osc_clk, &pll_cpu_rclk}, + .prediv = 1, + .sel_reg_offset = REG_PMU_SYS_CTRL, + .sel_reg_mask = 0x1, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x400000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x400000, +}; +static struct fh_clk ahb_clk = { + .name = "ahb_clk", + .flag = CLOCK_MULTI_PARENT|CLOCK_NORESET|CLOCK_NOGATE, + .parent = {&osc_clk, &pll_sys_pclk}, + .prediv = 1, + .sel_reg_offset = REG_PMU_SYS_CTRL, + .sel_reg_mask = 0x1, + .div_reg_offset = REG_PMU_CLK_DIV0, + .div_reg_mask = 0xf0000, +}; + +static struct fh_clk isp_aclk = { + .name = "isp_aclk", + .flag = CLOCK_NORESET, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV0, + .div_reg_mask = 0xf00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x1, + .def_rate = CONFIG_ISP_CLK_RATE, +}; +static struct fh_clk ispb_aclk = { + .name = "ispb_aclk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&isp_aclk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x4, +}; + +static struct fh_clk vpu_clk = { + .name = "vpu_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&isp_aclk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x80000000, +}; + +static struct fh_clk pix_clk = { + .name = "pix_clk", + .flag = CLOCK_NORESET|CLOCK_NOGATE, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV2, + .div_reg_mask = 0xf000000, +}; + +static struct fh_clk jpeg_clk = { + .name = "jpeg_clk", + .flag = CLOCK_NORESET, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV7, + .div_reg_mask = 0xf00000, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x40000000, + .def_rate = CONFIG_JPEG_CLK_RATE, +}; + +static struct fh_clk bgm_clk = { + .name = "bgm_clk", + .flag = CLOCK_NORESET, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV7, + .div_reg_mask = 0xf00000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x40000, +}; + +static struct fh_clk jpeg_adapt_clk = { + .name = "jpeg_adapt_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&jpeg_clk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x2, +}; +static struct fh_clk spi0_clk = { + .name = "spi0_clk", + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xff, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x80, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x100, +}; +static struct fh_clk sdc0_clk = { + .name = "sdc0_clk", + .parent = {&pll_sys_pclk}, + .prediv = 8, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xf00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x200, + .rst_reg_offset = REG_PMU_SWRST_AHB_CTRL, + .rst_reg_mask = 0x4, +}; +static struct fh_clk spi2_clk = { + .name = "spi2_clk", + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xf000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x2, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x100000, +}; +static struct fh_clk spi1_clk = { + .name = "spi1_clk", + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xff0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x100, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x200, +}; +static struct fh_clk sdc1_clk = { + .name = "sdc1_clk", + .parent = {&pll_sys_pclk}, + .prediv = 8, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xf000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x400, + .rst_reg_offset = REG_PMU_SWRST_AHB_CTRL, + .rst_reg_mask = 0x2, +}; + +static struct fh_clk veu_clk = { + .name = "veu_clk", + .flag = CLOCK_MULTI_PARENT, + .parent = {&pll_sys_pclk, &pll_sys_rclk}, + .prediv = 1, + .sel_reg_offset = REG_PMU_SYS_CTRL, + .sel_reg_mask = 0x4, + .div_reg_offset = REG_PMU_CLK_DIV0, + .div_reg_mask = 0x7000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x10, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x2000000, + .def_rate = CONFIG_VEU_CLK_RATE, + +}; + +static struct fh_clk veu_adapt_clk = { + .name = "veu_adapt_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&veu_clk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x20000000, + +}; + +static struct fh_clk cis_clk_out = { + .name = "cis_clk_out", + .flag = CLOCK_NORESET, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV1, + .div_reg_mask = 0xff0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x800000, +}; + +static struct fh_clk eth_clk = { + .name = "eth_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV6, + .div_reg_mask = 0xf000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x12000000, + .rst_reg_offset = REG_PMU_SWRST_AHB_CTRL, + .rst_reg_mask = 0x20000, +}; +static struct fh_clk i2c0_clk = { + .name = "i2c0_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV4, + .div_reg_mask = 0x3f0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x1000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x400, +}; + +static struct fh_clk i2c1_clk = { + .name = "i2c1_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV4, + .div_reg_mask = 0x3f000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x8000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x800, +}; + +static struct fh_clk i2c2_clk = { + .name = "i2c2_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV7, + .div_reg_mask = 0x00003f00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x00000008, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x20000000, +}; + +static struct fh_clk pwm_clk = { + .name = "pwm_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV5, + .div_reg_mask = 0xff, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x10000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x80, + .def_rate = 50000000, +}; + +static struct fh_clk uart0_clk = { + .name = "uart0_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV4, + .div_reg_mask = 0x1f, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x2000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x4000, + .def_rate = 16666666, +}; + +static struct fh_clk uart1_clk = { + .name = "uart1_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV4, + .div_reg_mask = 0x1f00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x4000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x8000, + .def_rate = 16666666, +}; +static struct fh_clk uart2_clk = { + .name = "uart2_clk", + .parent = {&pllsysp_div12_clk}, + .flag = 0, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV7, + .div_reg_mask = 0x7f, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x8000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x8000000, + .def_rate = 16666666, +}; + +static struct fh_clk efuse_clk = { + .name = "efuse_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV1, + .div_reg_mask = 0x3f000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x200000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x800000, +}; + +static struct fh_clk pts_clk = { + .name = "pts_clk", + .parent = {&pllsysp_div12_clk}, + .flag = CLOCK_NORESET, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV2, + .div_reg_mask = 0x1ff, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x80000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL2, + .rst_reg_mask = 0x1, + .def_rate = 1000000, +}; + +static struct fh_clk tmr0_clk = { + .name = "tmr0_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV5, + .div_reg_mask = 0xff0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x20000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x40000, +}; + +static struct fh_clk sadc_clk = { + .name = "sadc_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV6, + .div_reg_mask = 0x7f0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x4000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x10000, +}; + +static struct fh_clk ac_clk = { + .name = "ac_clk", + .parent = {&osc_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV6, + .div_reg_mask = 0x3f, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x800, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x1000, +}; + +static struct fh_clk i2s_clk = { + .name = "i2s_clk", + .parent = {&ac_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV6, + .div_reg_mask = 0x3f00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x1000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x2000, +}; + +static struct fh_clk wdt_clk = { + .name = "wdt_clk", + .flag = 0, + .parent = {&ahb_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV5, + .div_reg_mask = 0xff00, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x8000000, + .rst_reg_offset = REG_PMU_SWRST_APB_CTRL, + .rst_reg_mask = 0x100000, + .def_rate = 1000000, +}; + +static struct fh_clk gpio0_db_clk = { + .name = "gpio0_db_clk", + .flag = 0, + .parent = {&pllsysp_div12_clk}, + .prediv = 100, + .div_reg_offset = REG_PMU_CLK_DIV8, + .div_reg_mask = 0x7fff, + .en_reg_offset = REG_PMU_CLK_DIV8, + .en_reg_mask = 0x8000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x10, +}; + +static struct fh_clk gpio1_db_clk = { + .name = "gpio1_db_clk", + .flag = 0, + .parent = {&pllsysp_div12_clk}, + .prediv = 100, + .div_reg_offset = REG_PMU_CLK_DIV8, + .div_reg_mask = 0x7fff0000, + .en_reg_offset = REG_PMU_CLK_DIV8, + .en_reg_mask = 0x80000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x20, +}; + + +static struct fh_clk mipi_dphy_clk = { + .name = "mipi_dphy_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&osc_clk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x100000, +}; +static struct fh_clk mipi_wrap_gate = { + .name = "mipi_wrap_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x20000000, +}; +static struct fh_clk rtc_hclk_gate = { + .name = "rtc_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x10000000, +}; +static struct fh_clk emac_hclk_gate = { + .name = "emac_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x2000000, +}; +static struct fh_clk usb_clk = { + .name = "usb_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x1000000, +}; +static struct fh_clk aes_hclk_gate = { + .name = "aes_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x80, +}; +static struct fh_clk ephy_clk_gate = { + .name = "ephy_clk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x1, +}; +static struct fh_clk sdc0_clk8x_gate = { + .name = "sdc0_clk8x_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x4, +}; +static struct fh_clk sdc1_clk8x_gate = { + .name = "sdc1_clk8x_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x8, +}; +static struct fh_clk mipic_pclk_gate = { + .name = "mipic_pclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x10, +}; + +static struct fh_clk gpio0_pclk_gate = { + .name = "gpio0_pclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV8, + .en_reg_mask = 0x4000, +}; +static struct fh_clk gpio1_pclk_gate = { + .name = "gpio1_pclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV8, + .en_reg_mask = 0x40000000, +}; +static struct fh_clk isp_hclk_gate = { + .name = "isp_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x1000000, +}; +static struct fh_clk veu_hclk_gate = { + .name = "veu_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x2000000, +}; +static struct fh_clk bgm_hclk_gate = { + .name = "bgm_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x4000000, +}; +static struct fh_clk adapt_hclk_gate = { + .name = "adapt_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x8000000, +}; +static struct fh_clk jpg_hclk_gate = { + .name = "jpg_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x10000000, +}; +static struct fh_clk jpg_adapt_gate = { + .name = "jpg_adapt_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x20000000, +}; +static struct fh_clk vpu_hclk_gate = { + .name = "vpu_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x40000000, +}; + +static struct fh_clk sdc0_clk_sample = { + .name = "sdc0_clk_sample", + .parent = {&sdc0_clk}, + .flag = CLOCK_NOGATE | CLOCK_PHASE, + .prediv = 1, + .sel_reg_offset = REG_PMU_CLK_GATE1, + .sel_reg_mask = 0xf0000, +}; + +static struct fh_clk sdc0_clk_drv = { + .name = "sdc0_clk_drv", + .parent = {&sdc0_clk}, + .flag = CLOCK_NOGATE | CLOCK_PHASE, + .prediv = 1, + .sel_reg_offset = REG_PMU_CLK_GATE1, + .sel_reg_mask = 0xf00000, +}; + +static struct fh_clk sdc1_clk_sample = { + .name = "sdc1_clk_sample", + .parent = {&sdc0_clk}, + .flag = CLOCK_NOGATE | CLOCK_PHASE, + .prediv = 1, + .sel_reg_offset = REG_PMU_CLK_GATE1, + .sel_reg_mask = 0xf00, +}; + +static struct fh_clk sdc1_clk_drv = { + .name = "sdc1_clk_drv", + .parent = {&sdc0_clk}, + .flag = CLOCK_NOGATE | CLOCK_PHASE, + .prediv = 1, + .sel_reg_offset = REG_PMU_CLK_GATE1, + .sel_reg_mask = 0xf000, +}; + +struct fh_clk *fh_clks[] = { + &osc_clk, + &pll_ddr_rclk, + &pll_cpu_pclk, + &pll_cpu_rclk, + &pll_sys_pclk, + &pll_sys_rclk, + &arm_clk, + &arc_clk, + &ahb_clk, + &ddr_clk, + &isp_aclk, + &ispb_aclk, + &jpeg_clk, + &jpeg_adapt_clk, + &vpu_clk, + &veu_clk, + &veu_adapt_clk, + &bgm_clk, + &mipi_dphy_clk, + &pllsysp_div12_clk, + &cis_clk_out, + &pix_clk, + &pts_clk, + &spi0_clk, + &spi1_clk, + &spi2_clk, + &sdc0_clk, + &sdc1_clk, + &uart0_clk, + &uart1_clk, + &uart2_clk, + &i2c0_clk, + &i2c1_clk, + &i2c2_clk, + &pwm_clk, + &wdt_clk, + &tmr0_clk, + &ac_clk, + &i2s_clk, + &sadc_clk, + ð_clk, + &efuse_clk, + &gpio0_db_clk, + &gpio1_db_clk, + &mipi_wrap_gate, + &rtc_hclk_gate, + &emac_hclk_gate, + &usb_clk, + &aes_hclk_gate, + &ephy_clk_gate, + &sdc0_clk8x_gate, + &sdc1_clk8x_gate, + &gpio0_pclk_gate, + &gpio1_pclk_gate, + &mipic_pclk_gate, + &sdc0_clk_sample, + &sdc0_clk_drv, + &sdc1_clk_sample, + &sdc1_clk_drv, + &isp_hclk_gate, + &veu_hclk_gate, + &bgm_hclk_gate, + &adapt_hclk_gate, + &jpg_hclk_gate, + &jpg_adapt_gate, + &vpu_hclk_gate, + NULL, +}; +EXPORT_SYMBOL(fh_clks); diff --git a/arch/arm/mach-fh/fh8858v200/chip.h b/arch/arm/mach-fh/fh8858v200/chip.h new file mode 100644 index 00000000..e552f718 --- /dev/null +++ b/arch/arm/mach-fh/fh8858v200/chip.h @@ -0,0 +1,422 @@ +#ifndef __ASM_ARCH_HL_H +#define __ASM_ARCH_HL_H + +#include + +#define SRAM_GRANULARITY 32 +#define SRAM_SIZE (SZ_128K+SZ_8K) + + +#define RAM_BASE (0x10000000) +#define DDR_BASE (0xA0000000) + + +#define PMU_REG_BASE (0xF0000000) +#define TIMER_REG_BASE (0xF0C00000) +#define GPIO0_REG_BASE (0xF0300000) +#define GPIO1_REG_BASE (0xF4000000) +#define UART0_REG_BASE (0xF0700000) +#define UART1_REG_BASE (0xF0800000) +#define SPI0_REG_BASE (0xF0500000) +#define SPI1_REG_BASE (0xF0600000) +#define SPI2_REG_BASE (0xF0640000) +#define INTC_REG_BASE (0xE0200000) +#define GMAC_REG_BASE (0xE0600000) +#define USBC_REG_BASE (0xE0700000) +#define DMAC_REG_BASE (0xE0300000) +#define I2C1_REG_BASE (0xF0B00000) +#define I2C0_REG_BASE (0xF0200000) +#define I2C2_REG_BASE (0xF0100000) +#define SDC0_REG_BASE (0xE2000000) +#define SDC1_REG_BASE (0xE2200000) +#define WDT_REG_BASE (0xF0D00000) +#define PWM_REG_BASE (0xF0400000) +#define I2S_REG_BASE (0xF0900000) +#define ACW_REG_BASE (0xF0A00000) +#define UART2_REG_BASE (0xF1300000) +#define SADC_REG_BASE (0xF1200000) +#define EFUSE_REG_BASE (0xF1600000) +#define AES_REG_BASE (0xE8200000) +#define RTC_REG_BASE (0xF1500000) +#define DDRC_REG_BASE (0xED000000) +#define CONSOLE_REG_BASE UART0_REG_BASE +#define FH_UART_NUMBER 3 + +#define FH_PMU_REG_SIZE 0x2110 +#define REG_PMU_CHIP_ID (0x0000) +#define REG_PMU_IP_VER (0x0004) +#define REG_PMU_FW_VER (0x0008) +#define REG_PMU_CLK_SEL (0x000c) +/*for HL REG_PMU_SYS_CTRL and CLK_SEL use one register */ +#define REG_PMU_SYS_CTRL (0x000c) +#define REG_PMU_PLL0 (0x0010) +#define REG_PMU_PLL1 (0x0014) +#define REG_PMU_PLL0_CTRL (0x0018) +#define REG_PMU_CLK_GATE (0x001c) +#define REG_PMU_CLK_GATE1 (0x0020) +#define REG_PMU_CLK_DIV0 (0x0024) +#define REG_PMU_CLK_DIV1 (0x0028) +#define REG_PMU_CLK_DIV2 (0x002c) +#define REG_PMU_CLK_DIV3 (0x0030) +#define REG_PMU_CLK_DIV4 (0x0034) +#define REG_PMU_CLK_DIV5 (0x0038) +#define REG_PMU_CLK_DIV6 (0x003c) +#define REG_PMU_SWRST_MAIN_CTRL (0x0040) +#define REG_PMU_SWRST_MAIN_CTRL2 (0x0044) +#define REG_PMU_SWRST_AHB_CTRL (0x0048) +#define REG_PMU_SWRST_APB_CTRL (0x004c) +#define REG_PMU_SPC_IO_STATUS (0x0054) +#define REG_PMU_SPC_FUN (0x0058) +#define REG_PMU_CLK_DIV7 (0x005c) +#define REG_PMU_CLK_DIV8 (0x0060) +#define REG_PMU_PLL2 (0x0064) +#define REG_PMU_PLL2_CTRL (0x0068) +#define REG_PMU_PLL1_CTRL (0x006c) +#define REG_PAD_PWR_SEL (0x0074) +#define REG_PMU_SWRSTN_NSR (0x0078) +#define REG_PMU_SWRSTN_NSR1 (0x007c) +#define REG_PMU_ETHPHY_REG0 (0x2108) + + +#define REG_PMU_PAD_BOOT_MODE_CFG (0x0080) +#define REG_PMU_PAD_BOOT_SEL1_CFG (0x0084) +#define REG_PMU_PAD_BOOT_SEL0_CFG (0x0088) +#define REG_PMU_PAD_UART0_TX_CFG (0x008c) +#define REG_PMU_PAD_UART0_RX_CFG (0x0090) +#define REG_PMU_PAD_I2C0_SCL_CFG (0x0094) +#define REG_PMU_PAD_I2C0_SDA_CFG (0x0098) +#define REG_PMU_PAD_SENSOR_CLK_CFG (0x009c) +#define REG_PMU_PAD_SENSOR_RSTN_CFG (0x00a0) +#define REG_PMU_PAD_UART1_TX_CFG (0x00a4) +#define REG_PMU_PAD_UART1_RX_CFG (0x00a8) +#define REG_PMU_PAD_I2C1_SCL_CFG (0x00ac) +#define REG_PMU_PAD_I2C1_SDA_CFG (0x00b0) +#define REG_PMU_PAD_UART2_TX_CFG (0x00b4) +#define REG_PMU_PAD_UART2_RX_CFG (0x00b8) +#define REG_PMU_PAD_USB_PWREN_CFG (0x00bc) +#define REG_PMU_PAD_PWM0_CFG (0x00c0) +#define REG_PMU_PAD_PWM1_CFG (0x00c4) +#define REG_PMU_PAD_PWM2_CFG (0x00c8) +#define REG_PMU_PAD_PWM3_CFG (0x00cc) +#define REG_PMU_PAD_MAC_RMII_CLK_CFG (0x00d0) +#define REG_PMU_PAD_MAC_REF_CLK_CFG (0x00d4) +#define REG_PMU_PAD_MAC_TXD0_CFG (0x00d8) +#define REG_PMU_PAD_MAC_TXD1_CFG (0x00dc) +#define REG_PMU_PAD_MAC_TXEN_CFG (0x00e0) +#define REG_PMU_PAD_MAC_RXD0_CFG (0x00e4) +#define REG_PMU_PAD_MAC_RXD1_CFG (0x00e8) +#define REG_PMU_PAD_MAC_RXDV_CFG (0x00ec) +#define REG_PMU_PAD_MAC_MDC_CFG (0x00f0) +#define REG_PMU_PAD_MAC_MDIO_CFG (0x00f4) +#define REG_PMU_PAD_SD1_CLK_CFG (0x00f8) +#define REG_PMU_PAD_SD1_CD_CFG (0x00fc) +#define REG_PMU_PAD_SD1_CMD_RSP_CFG (0x0100) +#define REG_PMU_PAD_SD1_DATA_0_CFG (0x0104) +#define REG_PMU_PAD_SD1_DATA_1_CFG (0x0108) +#define REG_PMU_PAD_SD1_DATA_2_CFG (0x010c) +#define REG_PMU_PAD_SD1_DATA_3_CFG (0x0110) +#define REG_PMU_PAD_GPIO_0_CFG (0x0114) +#define REG_PMU_PAD_GPIO_1_CFG (0x0118) +#define REG_PMU_PAD_GPIO_2_CFG (0x011c) +#define REG_PMU_PAD_GPIO_3_CFG (0x0120) +#define REG_PMU_PAD_GPIO_4_CFG (0x0124) +#define REG_PMU_PAD_SSI0_CLK_CFG (0x0128) +#define REG_PMU_PAD_SSI0_CSN_0_CFG (0x012c) +#define REG_PMU_PAD_SSI0_TXD_CFG (0x0130) +#define REG_PMU_PAD_SSI0_RXD_CFG (0x0134) +#define REG_PMU_PAD_SSI0_D2_CFG (0x0138) +#define REG_PMU_PAD_SSI0_D3_CFG (0x013c) +#define REG_PMU_PAD_SSI1_CLK_CFG (0x0140) +#define REG_PMU_PAD_SSI1_CSN_0_CFG (0x0144) +#define REG_PMU_PAD_SSI1_TXD_CFG (0x0148) +#define REG_PMU_PAD_SSI1_RXD_CFG (0x014c) +#define REG_PMU_PAD_SD0_CD_CFG (0x0150) +#define REG_PMU_PAD_SD0_CLK_CFG (0x0154) +#define REG_PMU_PAD_SD0_CMD_RSP_CFG (0x0158) +#define REG_PMU_PAD_SD0_DATA_0_CFG (0x015c) +#define REG_PMU_PAD_SD0_DATA_1_CFG (0x0160) +#define REG_PMU_PAD_SD0_DATA_2_CFG (0x0164) +#define REG_PMU_PAD_SD0_DATA_3_CFG (0x0168) +#define REG_PMU_PAD_SADC_XAIN0_CFG (0x016c) +#define REG_PMU_PAD_SADC_XAIN1_CFG (0x0170) +#define REG_PMU_PAD_SADC_XAIN2_CFG (0x0174) +#define REG_PMU_PAD_SADC_XAIN3_CFG (0x0178) +#define REG_PMU_PAD_GPIO_28_CFG (0x017c) +#define REG_PMU_PAD_GPIO_29_CFG (0x0180) + +#define REG_PMU_ARM_INT_0 (0x01e0) +#define REG_PMU_ARM_INT_1 (0x01e4) +#define REG_PMU_ARM_INT_2 (0x01e8) +#define REG_PMU_A625_INT_0 (0x01ec) +#define REG_PMU_A625_INT_1 (0x01f0) +#define REG_PMU_A625_INT_2 (0x01f4) +#define REG_PMU_DMA (0x01f8) +#define REG_PMU_WDT_CTRL (0x01fc) +#define REG_PMU_DBG_STAT0 (0x0200) +#define REG_PMU_DBG_STAT1 (0x0204) +#define REG_PMU_DBG_STAT2 (0x0208) +#define REG_PMU_DBG_STAT3 (0x020c) +#define REG_PMU_USB_SYS (0x0210) +#define REG_PMU_USB_CFG (0x0214) +#define REG_PMU_USB_TUNE (0x0218) +#define REG_PMU_USB_SYS1 (0x0228) +#define REG_PMU_PTSLO (0x022c) +#define REG_PMU_PTSHI (0x0230) +#define REG_PMU_USER0 (0x0234) +#define REG_PMU_BOOT_MODE (0x0330) +#define REG_PMU_DDR_SIZE (0x0334) +#define REG_PMU_RESERVED2 (0x0338) +#define REG_PMU_CHIP_INFO (0x033c) +#define REG_PMU_EPHY_PARAM (0x0340) +#define REG_PMU_RTC_PARAM (0x0344) +#define REG_PMU_SD1_FUNC_SEL (0x03a0) +#define REG_PMU_PRDCID_CTRL0 (0x0500) +#define REG_PMU_A625BOOT0 (0x2000) +#define REG_PMU_A625BOOT1 (0x2004) +#define REG_PMU_A625BOOT2 (0x2008) +#define REG_PMU_A625BOOT3 (0x200c) +#define REG_PMU_A625_START_CTRL (0x2010) +#define REG_PMU_ARC_INTC_MASK (0x2014) + +#define FH_GMAC_AHB_RESET (1<<17) +#define FH_GMAC_SPEED_100M (1<<24) +#define PMU_RMII_SPEED_MODE (REG_PMU_CLK_SEL) +#define PMU_RXDV_GPIO_SWITCH (REG_PMU_PAD_MAC_RXDV_CFG) +#define PMU_RXDV_GPIO_MASK (0x0f000000) +#define PMU_RXDV_GPIO_VAL (0x01000000) + +#define PMU_DWI2S_CLK_SEL_REG (REG_PMU_CLK_SEL) +#define PMU_DWI2S_CLK_SEL_SHIFT (1) +#define PMU_DWI2S_CLK_DIV_REG (REG_PMU_CLK_DIV6) +#define PMU_DWI2S_CLK_DIV_SHIFT (0) + +/*ATTENTION: written by ARC */ +#define PMU_ARM_INT_MASK (0x01ec) +#define PMU_ARM_INT_RAWSTAT (0x01f0) +#define PMU_ARM_INT_STAT (0x01f4) + +#define PMU_A625_INT_MASK (0x01e0) +#define PMU_A625_INT_RAWSTAT (0x01e4) +#define PMU_A625_INT_STAT (0x01e8) + +#define PMU_IRQ 0 +#define DDRC_IRQ 1 +#define WDT_IRQ 2 +#define TMR0_IRQ 3 +#define VEU_IRQ 4 +#define PERF_IRQ 5 +#define VPU_IRQ 9 +#define I2C0_IRQ 11 +#define I2C1_IRQ 12 +#define JPEG_IRQ 13 +#define BGM_IRQ 14 +#define VEU_LOOP_IRQ 15 +#define AES_IRQ 16 +#define MIPIC_IRQ 17 +#define MIPI_WRAP_IRQ 18 +#define ACW_IRQ 19 +#define SADC_IRQ 20 +#define SPI1_IRQ 21 +#define JPEG_LOOP_IRQ 22 +#define DMAC0_IRQ 23 +#define DMAC1_IRQ 24 +#define I2S0_IRQ 25 +#define GPIO0_IRQ 26 +#define SPI0_IRQ 28 +#define ARC_SW_IRQ 29 +#define UART0_IRQ 30 +#define UART1_IRQ 31 +#define ARM_SW_IRQ 32 +#define RTC_IRQ 33 +#define PWM_IRQ 36 +#define SPI2_IRQ 38 +#define USBC_IRQ 39 +#define GPIO1_IRQ 40 +#define UART2_IRQ 41 +#define SDC0_IRQ 42 +#define SDC1_IRQ 43 +#define GMAC_IRQ 44 +#define EPHY_IRQ 45 +#define I2C2_IRQ 46 +#define RTC_ALM_IRQ 47 +#define RTC_CORE_IRQ 48 +/* because chips with some same function in different */ +/* pmu register, use wrap marco to make code to be same */ +#define PMU_RMII_SPEED_MODE (REG_PMU_CLK_SEL) + +#define MEM_START_PHY_ADDR DDR_BASE +#define MEM_SIZE 0x8000000 + + +#define NR_INTERNAL_IRQS (64) +#define NR_EXTERNAL_IRQS (64) +/*#define NR_IRQS (NR_INTERNAL_IRQS + NR_EXTERNAL_IRQS)*/ + +/* SWRST_MAIN_CTRL */ +#define CPU_RSTN_BIT (0) +#define UTMI_RSTN_BIT (1) +#define DDRPHY_RSTN_BIT (2) +#define DDRC_RSTN_BIT (3) +#define GPIO0_DB_RSTN_BIT (4) +#define GPIO1_DB_RSTN_BIT (5) +#define PIXEL_RSTN_BIT (6) +#define PWM_RSTN_BIT (7) +#define SPI0_RSTN_BIT (8) +#define SPI1_RSTN_BIT (9) +#define I2C0_RSTN_BIT (10) +#define I2C1_RSTN_BIT (11) +#define ACODEC_RSTN_BIT (12) +#define I2S_RSTN_BIT (13) +#define UART0_RSTN_BIT (14) +#define UART1_RSTN_BIT (15) +#define SADC_RSTN_BIT (16) +#define ADAPT_RSTN_BIT (17) +#define TMR_RSTN_BIT (18) +#define UART2_RSTN_BIT (19) +#define SPI2_RSTN_BIT (20) +#define JPG_ADAPT_RSTN_BIT (21) +#define ARC_RSTN_BIT (22) +#define EFUSE_RSTN_BIT (23) +#define JPG_RSTN_BIT (24) +#define VEU_RSTN_BIT (25) +#define VPU_RSTN_BIT (26) +#define ISP_RSTN_BIT (27) +#define BGM_RSTN_BIT (28) +#define I2C2_RSTN_BIT (29) +#define EPHY_RSTN_BIT (30) +#define SYS_RSTN_BIT (31) + +/* SWRST_AHB_CTRL */ +#define EMC_HRSTN_BIT (0) +#define SDC1_HRSTN_BIT (1) +#define SDC0_HRSTN_BIT (2) +#define AES_HRSTN_BIT (3) +#define DMAC0_HRSTN_BIT (4) +#define INTC_HRSTN_BIT (5) +#define JPEG_ADAPT_HRSTN_BIT (7) +#define JPEG_HRSTN_BIT (8) +#define VCU_HRSTN_BIT (9) +#define VPU_HRSTN_BIT (10) +#define ISP_HRSTN_BIT (11) +#define USB_HRSTN_BIT (12) +#define HRSTN_BIT (13) +#define EMAC_HRSTN_BIT (17) +#define DDRC_HRSTN_BIT (19) +#define DMAC1_HRSTN_BIT (20) +#define BGM_HRSTN_BIT (22) +#define ADAPT_HRSTN_BIT (23) + + +/* SWRST_APB_CTRL */ +#define ACODEC_PRSTN_BIT (0) +#define I2S_PRSTN_BIT (1) +#define UART1_PRSTN_BIT (2) +#define UART0_PRSTN_BIT (3) +#define SPI0_PRSTN_BIT (4) +#define SPI1_PRSTN_BIT (5) +#define GPIO0_PRSTN_BIT (6) +#define UART2_PRSTN_BIT (7) +#define I2C2_PRSTN_BIT (8) +#define I2C0_PRSTN_BIT (9) +#define I2C1_PRSTN_BIT (10) +#define TMR_PRSTN_BIT (11) +#define PWM_PRSTN_BIT (12) +#define MIPIW_PRSTN_BIT (13) +#define MIPIC_PRSTN_BIT (14) +#define RTC_PRSTN_BIT (15) +#define SADC_PRSTN_BIT (16) +#define EFUSE_PRSTN_BIT (17) +#define SPI2_PRSTN_BIT (18) +#define WDT_PRSTN_BIT (19) +#define GPIO1_PRSTN_BIT (20) + +/* timer clk fpga 1M,soc 50M*/ +#ifdef CONFIG_FPGA +#define TIMER_CLK (1000000) +#else +#define TIMER_CLK (50000000) +#endif + +#define UART1_TX_HW_HANDSHAKE (9) +#define UART1_RX_HW_HANDSHAKE (8) +#define UART2_TX_HW_HANDSHAKE (13) +#define UART2_RX_HW_HANDSHAKE (12) +#define UART1_DMA_TX_CHAN (4) +#define UART1_DMA_RX_CHAN (5) +#define UART2_DMA_TX_CHAN (4) +#define UART2_DMA_RX_CHAN (5) + +/*sdio*/ +#define SIMPLE_0 (0) +#define SIMPLE_22 (1) +#define SIMPLE_45 (2) +#define SIMPLE_67 (3) +#define SIMPLE_90 (4) +#define SIMPLE_112 (5) +#define SIMPLE_135 (6) +#define SIMPLE_157 (7) +#define SIMPLE_180 (8) +#define SIMPLE_202 (9) +#define SIMPLE_225 (10) +#define SIMPLE_247 (11) +#define SIMPLE_270 (12) +#define SIMPLE_292 (13) +#define SIMPLE_315 (14) +#define SIMPLE_337 (15) + + + +#define SDIO0_RST_BIT (~UL(1<<2)) +#define SDIO0_CLK_RATE (50000000) +#define SDIO0_CLK_DRV_SHIFT (20) +#define SDIO0_CLK_DRV_DEGREE (SIMPLE_180) +#define SDIO0_CLK_SAM_SHIFT (16) +#define SDIO0_CLK_SAM_DEGREE (SIMPLE_0) + + +#define SDIO1_RST_BIT (~UL(1<<1)) +#define SDIO1_CLK_RATE (50000000) +#define SDIO1_CLK_DRV_SHIFT (12) +#define SDIO1_CLK_DRV_DEGREE (SIMPLE_180) +#define SDIO1_CLK_SAM_SHIFT (8) +#define SDIO1_CLK_SAM_DEGREE (SIMPLE_0) + +#define SDC0_HRSTN (0x1<<2) +#define SDC1_HRSTN (0x1<<1) +#define SDC2_HRSTN (0) + + +/*usb*/ +#define IRQ_UHOST USBC_IRQ +#define FH_PA_OTG USBC_REG_BASE +#define IRQ_OTG IRQ_UHOST +#define FH_SZ_USBHOST SZ_1M +#define FH_SZ_OTG SZ_1M + +#define USB_UTMI_RST_BIT (0x1<<1) +#define USB_PHY_RST_BIT (0x11) +#define USB_SLEEP_MODE_BIT (0x1<<24) +#define USB_IDDQ_PWR_BIT (0x1<<10) + + +/* Specific Uart Number */ +#define FH_UART_NUMBER 3 +#define CLK_SCAN_BIT_POS (28) +#define INSIDE_PHY_ENABLE_BIT_POS (24) +#define MAC_REF_CLK_DIV_MASK (0x0f) +#define MAC_REF_CLK_DIV_BIT_POS (24) +#define MAC_PAD_RMII_CLK_MASK (0x0f) +#define MAC_PAD_RMII_CLK_BIT_POS (24) +#define MAC_PAD_MAC_REF_CLK_BIT_POS (28) +#define ETH_REF_CLK_OUT_GATE_BIT_POS (25) +#define ETH_RMII_CLK_OUT_GATE_BIT_POS (28) +#define IN_OR_OUT_PHY_SEL_BIT_POS (26) +#define INSIDE_CLK_GATE_BIT_POS (0) +#define INSIDE_PHY_SHUTDOWN_BIT_POS (31) +#define INSIDE_PHY_RST_BIT_POS (30) +#define INSIDE_PHY_TRAINING_BIT_POS (27) +#define INSIDE_PHY_TRAINING_MASK (0x0f) + +#define TRAINING_EFUSE_ACTIVE_BIT_POS 4 + +#endif /* __ASM_ARCH_HL_H */ diff --git a/arch/arm/mach-fh/fh8858v200/iopad.h b/arch/arm/mach-fh/fh8858v200/iopad.h new file mode 100644 index 00000000..be10c032 --- /dev/null +++ b/arch/arm/mach-fh/fh8858v200/iopad.h @@ -0,0 +1,729 @@ +#include +#include +#include + +/* PINCTRL_FUNC */ +PINCTRL_FUNC(GPIO30, 0, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(GPIO31, 1, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(ETH_LINK_ACT, 1, FUNC1, PUPD_UP, 0); +PINCTRL_FUNC(GPIO32, 2, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(ETH_LINK_STA, 2, FUNC1, PUPD_UP, 0); +PINCTRL_FUNC(ETH_LINK_SPD, 2, FUNC2, PUPD_UP, 0); +PINCTRL_FUNC(UART0_TX, 3, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO33, 3, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART0_RX, 4, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO34, 4, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C0_SCL, 5, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(GPIO35, 5, FUNC1, PUPD_UP, 0); +PINCTRL_FUNC(I2C0_SDA, 6, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(GPIO36, 6, FUNC1, PUPD_UP, 0); +PINCTRL_FUNC(SENSOR_CLK, 7, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO12, 7, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO13, 8, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(UART1_TX, 9, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO39, 9, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CLK, 9, FUNC3, PUPD_NONE, 3); +PINCTRL_FUNC(TEST_O_INT_RMII_CLK, 9, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(UART1_RX, 10, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO40, 10, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 10, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_INT_RMII_TXD_0, 10, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(I2C1_SCL, 11, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO37, 11, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM2, 11, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CMD_RSP, 11, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CLK, 11, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_INT_RMII_TXD_1, 11, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(I2C1_SDA, 12, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO38, 12, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM3, 12, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_0, 12, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CSN_0, 12, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_INT_RMII_TXEN, 12, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_TX, 13, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO41, 13, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM4, 13, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_1, 13, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_TXD, 13, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_O_INT_RMII_RXD_0, 13, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_RX, 14, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO42, 14, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM5, 14, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_2, 14, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_RXD, 14, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_O_INT_RMII_RXD_1, 14, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(USB_PWREN, 15, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO47, 15, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_3, 15, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_O_INT_RMII_CRSDV, 15, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM0, 16, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO43, 16, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C2_SCL, 16, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_TX, 16, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_RMII_TXD_0, 16, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM1, 17, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO44, 17, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C2_SDA, 17, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_RX, 17, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_RMII_TXD_1, 17, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM2, 18, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO45, 18, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM3, 19, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO46, 19, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_RMII_CLK, 20, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO48, 20, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CLK, 20, FUNC2, PUPD_NONE, 3); +PINCTRL_FUNC(PWM2, 20, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_REF_CLK, 21, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(MAC_TXD_0, 22, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO49, 22, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 22, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM3, 22, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_TXD_1, 23, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO50, 23, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CMD_RSP, 23, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM4, 23, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_TXEN, 24, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO51, 24, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_0, 24, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM5, 24, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_RXD_0, 25, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO52, 25, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_1, 25, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM6, 25, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_RXD_1, 26, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO53, 26, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_2, 26, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM7, 26, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_RXDV, 27, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO54, 27, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_3, 27, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM8, 27, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_MDC, 28, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO55, 28, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM9, 28, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_MDIO, 29, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO56, 29, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CLK, 30, FUNC0, PUPD_NONE, 3); +PINCTRL_FUNC(GPIO57, 30, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C1_SCL, 30, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 31, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO58, 31, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C1_SDA, 31, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CMD_RSP, 32, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO59, 32, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART1_TX, 32, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_0, 33, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO60, 33, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART1_RX, 33, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_1, 34, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO61, 34, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_TX, 34, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_2, 35, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO62, 35, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_RX, 35, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_3, 36, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO63, 36, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TRSTN, 37, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO0, 37, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_I2S_DO, 37, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(DW_I2S_DO, 37, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SSI1_CLK, 37, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI2_CLK, 37, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_ADDAT, 37, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM6, 37, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_SMI_MDC, 37, FUNC8, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TDO, 38, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO1, 38, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_I2S_DI, 38, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(DW_I2S_DI, 38, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SSI1_CSN_0, 38, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI2_CSN_0, 38, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_DADAT, 38, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM7, 38, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_SMI_MDIO_I, 38, FUNC8, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TDI, 39, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO2, 39, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_I2S_CLK, 39, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(DW_I2S_CLK, 39, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SSI1_TXD, 39, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI2_TXD, 39, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_ADBCLK, 39, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM8, 39, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_SMI_MDIO_O, 39, FUNC8, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TCK, 40, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO3, 40, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_I2S_WS, 40, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(DW_I2S_WS, 40, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SSI1_RXD, 40, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI2_RXD, 40, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_ADLRC, 40, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM9, 40, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_I_INT_SMI_MDIO_I, 40, FUNC8, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TMS, 41, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO4, 41, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_MCLK, 41, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(USB_PWREN, 41, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 41, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_I_INT_SMI_MDC, 41, FUNC5, PUPD_NONE, 0); +PINCTRL_FUNC(SSI0_CLK, 42, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO5, 42, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_CLK, 42, FUNC4, PUPD_NONE, 3); +PINCTRL_FUNC(SSI0_CSN_0, 43, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO6, 43, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_CMD_RSP, 43, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI0_TXD, 44, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO7, 44, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_DATA_0, 44, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI0_RXD, 45, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO8, 45, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_DATA_1, 45, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI0_D2, 46, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO9, 46, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(UART1_TX, 46, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(I2C1_SCL, 46, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_DATA_2, 46, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI0_D3, 47, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO10, 47, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(UART1_RX, 47, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(I2C1_SDA, 47, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_DATA_3, 47, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CLK, 48, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO11, 48, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SSI2_CLK, 48, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CSN_0, 49, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO14, 49, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SSI2_CSN_0, 49, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_TXD, 50, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO15, 50, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SSI2_TXD, 50, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_RXD, 51, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO16, 51, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SSI2_RXD, 51, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_CD, 52, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO17, 52, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(ARC_JTAG_TRSTN, 52, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(PAE_JTAG_TRSTN, 52, FUNC4, PUPD_NONE, 0); +PINCTRL_FUNC(SD0_CLK, 53, FUNC0, PUPD_NONE, 3); +PINCTRL_FUNC(GPIO18, 53, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CLK, 53, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(ARC_JTAG_TDO, 53, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(PAE_JTAG_TDO, 53, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_CMD_RSP, 54, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO19, 54, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_TXD, 54, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(ARC_JTAG_TDI, 54, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(PAE_JTAG_TDI, 54, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_DATA_0, 55, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO20, 55, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_RXD, 55, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(ARC_JTAG_TCK, 55, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(PAE_JTAG_TCK, 55, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_DATA_1, 56, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO21, 56, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CSN_0, 56, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(ARC_JTAG_TMS, 56, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(PAE_JTAG_TMS, 56, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_DATA_2, 57, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO22, 57, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(UART2_TX, 57, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(I2C2_SCL, 57, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_DABCLK, 57, FUNC6, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_DATA_3, 58, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO23, 58, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CSN_0, 58, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(UART2_RX, 58, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(I2C2_SDA, 58, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_DALRC, 58, FUNC6, PUPD_NONE, 2); +PINCTRL_FUNC(SADC_XAIN0, 59, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO26, 59, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SADC_XAIN1, 60, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO27, 60, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SADC_XAIN2, 61, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO24, 61, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SADC_XAIN3, 62, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO25, 62, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO28, 63, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(ETH_LINK_ACT, 63, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(PWM10, 63, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(USB_DBG_CLK, 63, FUNC4, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 63, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_O_INT_RMII_TXEN, 63, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_MDC, 63, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO29, 64, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(ETH_LINK_STA, 64, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(PWM11, 64, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(RTC_CLK, 64, FUNC4, PUPD_NONE, 0); +PINCTRL_FUNC(ETH_LINK_SPD, 64, FUNC5, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_SMI_MDIO_OE, 64, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_MDIO, 64, FUNC7, PUPD_NONE, 0); + + +/* PINCTRL_MUX */ + +PINCTRL_MUX(AC_I2S_CLK, 0, &PAD39_AC_I2S_CLK); +PINCTRL_MUX(AC_I2S_DI, 0, &PAD38_AC_I2S_DI); +PINCTRL_MUX(AC_I2S_DO, 0, &PAD37_AC_I2S_DO); +PINCTRL_MUX(AC_I2S_WS, 0, &PAD40_AC_I2S_WS); +PINCTRL_MUX(AC_MCLK, 0, &PAD41_AC_MCLK); + +PINCTRL_MUX(ARC_JTAG_TCK, 0, &PAD55_ARC_JTAG_TCK); +PINCTRL_MUX(ARC_JTAG_TDI, 0, &PAD54_ARC_JTAG_TDI); +PINCTRL_MUX(ARC_JTAG_TDO, 0, &PAD53_ARC_JTAG_TDO); +PINCTRL_MUX(ARC_JTAG_TMS, 0, &PAD56_ARC_JTAG_TMS); +PINCTRL_MUX(ARC_JTAG_TRSTN, 0, &PAD52_ARC_JTAG_TRSTN); + +PINCTRL_MUX(ARM_JTAG_TCK, 0, &PAD40_ARM_JTAG_TCK); +PINCTRL_MUX(ARM_JTAG_TDI, 0, &PAD39_ARM_JTAG_TDI); +PINCTRL_MUX(ARM_JTAG_TDO, 0, &PAD38_ARM_JTAG_TDO); +PINCTRL_MUX(ARM_JTAG_TMS, 0, &PAD41_ARM_JTAG_TMS); +PINCTRL_MUX(ARM_JTAG_TRSTN, 0, &PAD37_ARM_JTAG_TRSTN); + +PINCTRL_MUX(DW_I2S_CLK, 0, &PAD39_DW_I2S_CLK); +PINCTRL_MUX(DW_I2S_DI, 0, &PAD38_DW_I2S_DI); +PINCTRL_MUX(DW_I2S_DO, 0, &PAD37_DW_I2S_DO); +PINCTRL_MUX(DW_I2S_WS, 0, &PAD40_DW_I2S_WS); + +PINCTRL_MUX(ETH_LINK_ACT, 1, &PAD1_ETH_LINK_ACT, + &PAD63_ETH_LINK_ACT); +PINCTRL_MUX(ETH_LINK_SPD, 1, &PAD2_ETH_LINK_SPD, + &PAD64_ETH_LINK_SPD); +PINCTRL_MUX(ETH_LINK_STA, 1, &PAD2_ETH_LINK_STA, + &PAD64_ETH_LINK_STA); + +PINCTRL_MUX(I2C0_SCL, 0, &PAD5_I2C0_SCL); +PINCTRL_MUX(I2C0_SDA, 0, &PAD6_I2C0_SDA); + +PINCTRL_MUX(I2C1_SCL, 2, &PAD11_I2C1_SCL, &PAD30_I2C1_SCL, &PAD46_I2C1_SCL); +PINCTRL_MUX(I2C1_SDA, 2, &PAD12_I2C1_SDA, &PAD31_I2C1_SDA, &PAD47_I2C1_SDA); + +PINCTRL_MUX(I2C2_SCL, 1, &PAD16_I2C2_SCL, &PAD57_I2C2_SCL); +PINCTRL_MUX(I2C2_SDA, 1, &PAD17_I2C2_SDA, &PAD58_I2C2_SDA); + +PINCTRL_MUX(MAC_MDC, 0, &PAD28_MAC_MDC, &PAD63_MAC_MDC); +PINCTRL_MUX(MAC_MDIO, 0, &PAD29_MAC_MDIO, &PAD64_MAC_MDIO); +PINCTRL_MUX(MAC_REF_CLK, 0, &PAD21_MAC_REF_CLK); +PINCTRL_MUX(MAC_RMII_CLK, 0, &PAD20_MAC_RMII_CLK); +PINCTRL_MUX(MAC_RXDV, 0, &PAD27_MAC_RXDV); +PINCTRL_MUX(MAC_RXD_0, 0, &PAD25_MAC_RXD_0); +PINCTRL_MUX(MAC_RXD_1, 0, &PAD26_MAC_RXD_1); +PINCTRL_MUX(MAC_TXD_0, 0, &PAD22_MAC_TXD_0); +PINCTRL_MUX(MAC_TXD_1, 0, &PAD23_MAC_TXD_1); +PINCTRL_MUX(MAC_TXEN, 0, &PAD24_MAC_TXEN); + +PINCTRL_MUX(PAE_JTAG_TCK, 0, &PAD55_PAE_JTAG_TCK); +PINCTRL_MUX(PAE_JTAG_TDI, 0, &PAD54_PAE_JTAG_TDI); +PINCTRL_MUX(PAE_JTAG_TDO, 0, &PAD53_PAE_JTAG_TDO); +PINCTRL_MUX(PAE_JTAG_TMS, 0, &PAD56_PAE_JTAG_TMS); +PINCTRL_MUX(PAE_JTAG_TRSTN, 0, &PAD52_PAE_JTAG_TRSTN); + +PINCTRL_MUX(PWM0, 0, &PAD16_PWM0); +PINCTRL_MUX(PWM1, 0, &PAD17_PWM1); +PINCTRL_MUX(PWM10, 0, &PAD63_PWM10); +PINCTRL_MUX(PWM11, 0, &PAD64_PWM11); +PINCTRL_MUX(PWM2, 0, &PAD11_PWM2, &PAD18_PWM2, &PAD20_PWM2); +PINCTRL_MUX(PWM3, 0, &PAD12_PWM3, &PAD19_PWM3, &PAD22_PWM3); +PINCTRL_MUX(PWM4, 0, &PAD13_PWM4, &PAD23_PWM4); +PINCTRL_MUX(PWM5, 0, &PAD14_PWM5, &PAD24_PWM5); +PINCTRL_MUX(PWM6, 1, &PAD25_PWM6, &PAD37_PWM6); +PINCTRL_MUX(PWM7, 1, &PAD26_PWM7, &PAD38_PWM7); +PINCTRL_MUX(PWM8, 1, &PAD27_PWM8, &PAD39_PWM8); +PINCTRL_MUX(PWM9, 1, &PAD28_PWM9, &PAD40_PWM9); + +PINCTRL_MUX(RTC_CLK, 0, &PAD64_RTC_CLK); + +PINCTRL_MUX(SADC_XAIN0, 0, &PAD59_SADC_XAIN0); +PINCTRL_MUX(SADC_XAIN1, 0, &PAD60_SADC_XAIN1); +PINCTRL_MUX(SADC_XAIN2, 0, &PAD61_SADC_XAIN2); +PINCTRL_MUX(SADC_XAIN3, 0, &PAD62_SADC_XAIN3); + +PINCTRL_MUX(SD0_CD, 0, &PAD52_SD0_CD); +PINCTRL_MUX(SD0_CLK, 0, &PAD53_SD0_CLK); +PINCTRL_MUX(SD0_CMD_RSP, 0, &PAD54_SD0_CMD_RSP); +PINCTRL_MUX(SD0_DATA_0, 0, &PAD55_SD0_DATA_0); +PINCTRL_MUX(SD0_DATA_1, 0, &PAD56_SD0_DATA_1); +PINCTRL_MUX(SD0_DATA_2, 0, &PAD57_SD0_DATA_2); +PINCTRL_MUX(SD0_DATA_3, 0, &PAD58_SD0_DATA_3); + +PINCTRL_MUX(SD1_CD, 2, &PAD10_SD1_CD, &PAD22_SD1_CD, &PAD31_SD1_CD, + &PAD41_SD1_CD, &PAD63_SD1_CD); +PINCTRL_MUX(SD1_CLK, 2, &PAD9_SD1_CLK, &PAD20_SD1_CLK, &PAD30_SD1_CLK, + &PAD42_SD1_CLK); +PINCTRL_MUX(SD1_CMD_RSP, 2, &PAD11_SD1_CMD_RSP, &PAD23_SD1_CMD_RSP, + &PAD32_SD1_CMD_RSP, &PAD43_SD1_CMD_RSP); +PINCTRL_MUX(SD1_DATA_0, 2, &PAD12_SD1_DATA_0, &PAD24_SD1_DATA_0, + &PAD33_SD1_DATA_0, &PAD44_SD1_DATA_0); +PINCTRL_MUX(SD1_DATA_1, 2, &PAD13_SD1_DATA_1, &PAD25_SD1_DATA_1, + &PAD34_SD1_DATA_1, &PAD45_SD1_DATA_1); +PINCTRL_MUX(SD1_DATA_2, 2, &PAD14_SD1_DATA_2, &PAD26_SD1_DATA_2, + &PAD35_SD1_DATA_2, &PAD46_SD1_DATA_2); +PINCTRL_MUX(SD1_DATA_3, 2, &PAD15_SD1_DATA_3, &PAD27_SD1_DATA_3, + &PAD36_SD1_DATA_3, &PAD47_SD1_DATA_3); + +PINCTRL_MUX(SENSOR_CLK, 0, &PAD7_SENSOR_CLK); + +PINCTRL_MUX(SSI0_CLK, 0, &PAD42_SSI0_CLK); +PINCTRL_MUX(SSI0_D2, 0, &PAD46_SSI0_D2); +PINCTRL_MUX(SSI0_D3, 0, &PAD47_SSI0_D3); +PINCTRL_MUX(SSI0_RXD, 0, &PAD45_SSI0_RXD); +PINCTRL_MUX(SSI0_TXD, 0, &PAD44_SSI0_TXD); + +PINCTRL_MUX(SSI1_CLK, 2, &PAD11_SSI1_CLK, &PAD37_SSI1_CLK, &PAD48_SSI1_CLK, + &PAD53_SSI1_CLK); +PINCTRL_MUX(SSI1_RXD, 2, &PAD14_SSI1_RXD, &PAD40_SSI1_RXD, &PAD51_SSI1_RXD, + &PAD55_SSI1_RXD); +PINCTRL_MUX(SSI1_TXD, 2, &PAD13_SSI1_TXD, &PAD39_SSI1_TXD, &PAD50_SSI1_TXD, + &PAD54_SSI1_TXD); + +PINCTRL_MUX(SSI2_CLK, 1, &PAD37_SSI2_CLK, &PAD48_SSI2_CLK); +PINCTRL_MUX(SSI2_CSN_0, 1, &PAD38_SSI2_CSN_0, &PAD49_SSI2_CSN_0); +PINCTRL_MUX(SSI2_RXD, 1, &PAD40_SSI2_RXD, &PAD51_SSI2_RXD); +PINCTRL_MUX(SSI2_TXD, 1, &PAD39_SSI2_TXD, &PAD50_SSI2_TXD); + +PINCTRL_MUX(UART0_RX, 0, &PAD4_UART0_RX); +PINCTRL_MUX(UART0_TX, 0, &PAD3_UART0_TX); + +PINCTRL_MUX(UART1_RX, 0, &PAD10_UART1_RX, &PAD33_UART1_RX, &PAD47_UART1_RX); +PINCTRL_MUX(UART1_TX, 0, &PAD9_UART1_TX, &PAD32_UART1_TX, &PAD46_UART1_TX); + +PINCTRL_MUX(UART2_RX, 0, &PAD14_UART2_RX, &PAD17_UART2_RX, &PAD35_UART2_RX, + &PAD58_UART2_RX); +PINCTRL_MUX(UART2_TX, 0, &PAD13_UART2_TX, &PAD16_UART2_TX, &PAD34_UART2_TX, + &PAD57_UART2_TX); + +PINCTRL_MUX(USB_PWREN, 0, &PAD15_USB_PWREN, &PAD41_USB_PWREN); + +PINCTRL_MUX(GPIO0, 0, &PAD37_GPIO0); +PINCTRL_MUX(GPIO1, 0, &PAD38_GPIO1); +PINCTRL_MUX(GPIO2, 0, &PAD39_GPIO2); +PINCTRL_MUX(GPIO3, 0, &PAD40_GPIO3); +PINCTRL_MUX(GPIO4, 0, &PAD41_GPIO4); +PINCTRL_MUX(GPIO5, 0, &PAD42_GPIO5); +PINCTRL_MUX(GPIO6, 0, &PAD43_GPIO6); +PINCTRL_MUX(GPIO7, 0, &PAD44_GPIO7); +PINCTRL_MUX(GPIO8, 0, &PAD45_GPIO8); +PINCTRL_MUX(GPIO9, 0, &PAD46_GPIO9); +PINCTRL_MUX(GPIO10, 0, &PAD47_GPIO10); +PINCTRL_MUX(GPIO11, 0, &PAD48_GPIO11); +PINCTRL_MUX(GPIO12, 0, &PAD7_GPIO12); +PINCTRL_MUX(GPIO13, 0, &PAD8_GPIO13); +PINCTRL_MUX(GPIO14, 0, &PAD49_GPIO14); +PINCTRL_MUX(GPIO15, 0, &PAD50_GPIO15); +PINCTRL_MUX(GPIO16, 0, &PAD51_GPIO16); +PINCTRL_MUX(GPIO17, 0, &PAD52_GPIO17); +PINCTRL_MUX(GPIO18, 0, &PAD53_GPIO18); +PINCTRL_MUX(GPIO19, 0, &PAD54_GPIO19); +PINCTRL_MUX(GPIO20, 0, &PAD55_GPIO20); +PINCTRL_MUX(GPIO21, 0, &PAD56_GPIO21); +PINCTRL_MUX(GPIO22, 0, &PAD57_GPIO22); +PINCTRL_MUX(GPIO23, 0, &PAD58_GPIO23); +PINCTRL_MUX(GPIO24, 0, &PAD61_GPIO24); +PINCTRL_MUX(GPIO25, 0, &PAD62_GPIO25); +PINCTRL_MUX(GPIO26, 0, &PAD59_GPIO26); +PINCTRL_MUX(GPIO27, 0, &PAD60_GPIO27); +PINCTRL_MUX(GPIO28, 0, &PAD63_GPIO28); +PINCTRL_MUX(GPIO29, 0, &PAD64_GPIO29); +PINCTRL_MUX(GPIO30, 0, &PAD0_GPIO30); +PINCTRL_MUX(GPIO31, 0, &PAD1_GPIO31); +PINCTRL_MUX(GPIO32, 0, &PAD2_GPIO32); +PINCTRL_MUX(GPIO33, 0, &PAD3_GPIO33); +PINCTRL_MUX(GPIO34, 0, &PAD4_GPIO34); +PINCTRL_MUX(GPIO35, 0, &PAD5_GPIO35); +PINCTRL_MUX(GPIO36, 0, &PAD6_GPIO36); +PINCTRL_MUX(GPIO37, 0, &PAD11_GPIO37); +PINCTRL_MUX(GPIO38, 0, &PAD12_GPIO38); +PINCTRL_MUX(GPIO39, 0, &PAD9_GPIO39); +PINCTRL_MUX(GPIO40, 0, &PAD10_GPIO40); +PINCTRL_MUX(GPIO41, 0, &PAD13_GPIO41); +PINCTRL_MUX(GPIO42, 0, &PAD14_GPIO42); +PINCTRL_MUX(GPIO43, 0, &PAD16_GPIO43); +PINCTRL_MUX(GPIO44, 0, &PAD17_GPIO44); +PINCTRL_MUX(GPIO45, 0, &PAD18_GPIO45); +PINCTRL_MUX(GPIO46, 0, &PAD19_GPIO46); +PINCTRL_MUX(GPIO47, 0, &PAD15_GPIO47); +PINCTRL_MUX(GPIO48, 0, &PAD20_GPIO48); +PINCTRL_MUX(GPIO49, 0, &PAD22_GPIO49); +PINCTRL_MUX(GPIO50, 0, &PAD23_GPIO50); +PINCTRL_MUX(GPIO51, 0, &PAD24_GPIO51); +PINCTRL_MUX(GPIO52, 0, &PAD25_GPIO52); +PINCTRL_MUX(GPIO53, 0, &PAD26_GPIO53); +PINCTRL_MUX(GPIO54, 0, &PAD27_GPIO54); +PINCTRL_MUX(GPIO55, 0, &PAD28_GPIO55); +PINCTRL_MUX(GPIO56, 0, &PAD29_GPIO56); +PINCTRL_MUX(GPIO57, 0, &PAD30_GPIO57); +PINCTRL_MUX(GPIO58, 0, &PAD31_GPIO58); +PINCTRL_MUX(GPIO59, 0, &PAD32_GPIO59); +PINCTRL_MUX(GPIO60, 0, &PAD33_GPIO60); +PINCTRL_MUX(GPIO61, 0, &PAD34_GPIO61); +PINCTRL_MUX(GPIO62, 0, &PAD35_GPIO62); +PINCTRL_MUX(GPIO63, 0, &PAD36_GPIO63); + +PINCTRL_MUX(SD1_CLK_EMMC, 3, &PAD9_SD1_CLK, &PAD20_SD1_CLK, &PAD30_SD1_CLK, + &PAD42_SD1_CLK); +PINCTRL_MUX(SD1_CMD_RSP_EMMC, 3, &PAD11_SD1_CMD_RSP, &PAD23_SD1_CMD_RSP, + &PAD32_SD1_CMD_RSP, &PAD43_SD1_CMD_RSP); +PINCTRL_MUX(SD1_DATA_0_EMMC, 3, &PAD12_SD1_DATA_0, &PAD24_SD1_DATA_0, + &PAD33_SD1_DATA_0, &PAD44_SD1_DATA_0); +PINCTRL_MUX(SD1_DATA_1_EMMC, 3, &PAD13_SD1_DATA_1, &PAD25_SD1_DATA_1, + &PAD34_SD1_DATA_1, &PAD45_SD1_DATA_1); +PINCTRL_MUX(SD1_DATA_2_EMMC, 3, &PAD14_SD1_DATA_2, &PAD26_SD1_DATA_2, + &PAD35_SD1_DATA_2, &PAD46_SD1_DATA_2); +PINCTRL_MUX(SD1_DATA_3_EMMC, 3, &PAD15_SD1_DATA_3, &PAD27_SD1_DATA_3, + &PAD36_SD1_DATA_3, &PAD47_SD1_DATA_3); + +/* PINCTRL_DEVICE */ +PINCTRL_DEVICE(ACI2S, 5, &MUX_AC_I2S_CLK, &MUX_AC_I2S_DI, &MUX_AC_I2S_DO, + &MUX_AC_I2S_WS, &MUX_AC_MCLK); +PINCTRL_DEVICE(AC_MCLK, 1, &MUX_AC_MCLK); +PINCTRL_DEVICE(ARCJTAG, 5, &MUX_ARC_JTAG_TCK, &MUX_ARC_JTAG_TDI, + &MUX_ARC_JTAG_TDO, &MUX_ARC_JTAG_TMS, &MUX_ARC_JTAG_TRSTN); +PINCTRL_DEVICE(ARMJTAG, 5, &MUX_ARM_JTAG_TCK, &MUX_ARM_JTAG_TDI, + &MUX_ARM_JTAG_TDO, &MUX_ARM_JTAG_TMS, &MUX_ARM_JTAG_TRSTN); +PINCTRL_DEVICE(DWI2S, 4, &MUX_DW_I2S_CLK, &MUX_DW_I2S_DI, &MUX_DW_I2S_DO, + &MUX_DW_I2S_WS); +PINCTRL_DEVICE(ETH, 2, &MUX_ETH_LINK_ACT, &MUX_ETH_LINK_STA); +PINCTRL_DEVICE(I2C0, 2, &MUX_I2C0_SCL, &MUX_I2C0_SDA); +PINCTRL_DEVICE(I2C1, 2, &MUX_I2C1_SCL, &MUX_I2C1_SDA); +PINCTRL_DEVICE(I2C2, 2, &MUX_I2C2_SCL, &MUX_I2C2_SDA); +PINCTRL_DEVICE(PAEJTAG, 5, &MUX_PAE_JTAG_TCK, &MUX_PAE_JTAG_TDI, + &MUX_PAE_JTAG_TDO, &MUX_PAE_JTAG_TMS, &MUX_PAE_JTAG_TRSTN); +PINCTRL_DEVICE(PWM0, 1, &MUX_PWM0); +PINCTRL_DEVICE(PWM1, 1, &MUX_PWM1); +PINCTRL_DEVICE(PWM10, 1, &MUX_PWM10); +PINCTRL_DEVICE(PWM11, 1, &MUX_PWM11); +PINCTRL_DEVICE(PWM2, 1, &MUX_PWM2); +PINCTRL_DEVICE(PWM3, 1, &MUX_PWM3); +PINCTRL_DEVICE(PWM4, 1, &MUX_PWM4); +PINCTRL_DEVICE(PWM5, 1, &MUX_PWM5); +PINCTRL_DEVICE(PWM6, 1, &MUX_PWM6); +PINCTRL_DEVICE(PWM7, 1, &MUX_PWM7); +PINCTRL_DEVICE(PWM8, 1, &MUX_PWM8); +PINCTRL_DEVICE(PWM9, 1, &MUX_PWM9); +PINCTRL_DEVICE(RMII, 10, &MUX_MAC_MDC, &MUX_MAC_MDIO, &MUX_MAC_REF_CLK, + &MUX_MAC_RMII_CLK, &MUX_MAC_RXDV, &MUX_MAC_RXD_0, &MUX_MAC_RXD_1, + &MUX_MAC_TXD_0, &MUX_MAC_TXD_1, &MUX_MAC_TXEN); +PINCTRL_DEVICE(RTC, 1, &MUX_RTC_CLK); +PINCTRL_DEVICE(SADC_XAIN0, 1, &MUX_SADC_XAIN0); +PINCTRL_DEVICE(SADC_XAIN1, 1, &MUX_SADC_XAIN1); +PINCTRL_DEVICE(SADC_XAIN2, 1, &MUX_SADC_XAIN2); +PINCTRL_DEVICE(SADC_XAIN3, 1, &MUX_SADC_XAIN3); +PINCTRL_DEVICE(SD0, 7, &MUX_SD0_CD, &MUX_SD0_CLK, &MUX_SD0_CMD_RSP, + &MUX_SD0_DATA_0, &MUX_SD0_DATA_1, &MUX_SD0_DATA_2, &MUX_SD0_DATA_3); +PINCTRL_DEVICE(SD0_1BIT_NO_WP, 4, &MUX_SD0_CD, &MUX_SD0_CLK, &MUX_SD0_CMD_RSP, + &MUX_SD0_DATA_0); +PINCTRL_DEVICE(SD0_NO_WP, 7, &MUX_SD0_CD, &MUX_SD0_CLK, &MUX_SD0_CMD_RSP, + &MUX_SD0_DATA_0, &MUX_SD0_DATA_1, &MUX_SD0_DATA_2, &MUX_SD0_DATA_3); +PINCTRL_DEVICE(SD0_WIFI, 6, &MUX_SD0_CLK, &MUX_SD0_CMD_RSP, &MUX_SD0_DATA_0, + &MUX_SD0_DATA_1, &MUX_SD0_DATA_2, &MUX_SD0_DATA_3); +PINCTRL_DEVICE(SD1, 7, &MUX_SD1_CD, &MUX_SD1_CLK, &MUX_SD1_CMD_RSP, + &MUX_SD1_DATA_0, &MUX_SD1_DATA_1, &MUX_SD1_DATA_2, &MUX_SD1_DATA_3); +PINCTRL_DEVICE(SD1_1BIT_NO_WP, 4, &MUX_SD1_CD, &MUX_SD1_CLK, &MUX_SD1_CMD_RSP, + &MUX_SD1_DATA_0); +PINCTRL_DEVICE(SD1_NO_WP, 7, &MUX_SD1_CD, &MUX_SD1_CLK, &MUX_SD1_CMD_RSP, + &MUX_SD1_DATA_0, &MUX_SD1_DATA_1, &MUX_SD1_DATA_2, &MUX_SD1_DATA_3); +PINCTRL_DEVICE(SD1_WIFI, 6, &MUX_SD1_CLK, &MUX_SD1_CMD_RSP, &MUX_SD1_DATA_0, + &MUX_SD1_DATA_1, &MUX_SD1_DATA_2, &MUX_SD1_DATA_3); +PINCTRL_DEVICE(SENSOR_CLK, 1, &MUX_SENSOR_CLK); +PINCTRL_DEVICE(SSI0, 4, &MUX_GPIO6, &MUX_SSI0_CLK, &MUX_SSI0_RXD, + &MUX_SSI0_TXD); +PINCTRL_DEVICE(SSI0_4BIT, 6, &MUX_GPIO6, &MUX_SSI0_CLK, &MUX_SSI0_D2, + &MUX_SSI0_D3, &MUX_SSI0_RXD, &MUX_SSI0_TXD); +PINCTRL_DEVICE(SSI1, 4, &MUX_GPIO14, &MUX_SSI1_CLK, &MUX_SSI1_RXD, + &MUX_SSI1_TXD); +PINCTRL_DEVICE(SSI2, 4, &MUX_SSI2_CLK, &MUX_SSI2_CSN_0, &MUX_SSI2_RXD, + &MUX_SSI2_TXD); +PINCTRL_DEVICE(UART0, 2, &MUX_UART0_RX, &MUX_UART0_TX); +PINCTRL_DEVICE(UART1, 2, &MUX_UART1_RX, &MUX_UART1_TX); +PINCTRL_DEVICE(UART2, 2, &MUX_UART2_RX, &MUX_UART2_TX); +PINCTRL_DEVICE(USB, 1, &MUX_USB_PWREN); +PINCTRL_DEVICE(GPIO0, 1, &MUX_GPIO0); +PINCTRL_DEVICE(GPIO1, 1, &MUX_GPIO1); +PINCTRL_DEVICE(GPIO2, 1, &MUX_GPIO2); +PINCTRL_DEVICE(GPIO3, 1, &MUX_GPIO3); +PINCTRL_DEVICE(GPIO4, 1, &MUX_GPIO4); +PINCTRL_DEVICE(GPIO5, 1, &MUX_GPIO5); +PINCTRL_DEVICE(GPIO6, 1, &MUX_GPIO6); +PINCTRL_DEVICE(GPIO7, 1, &MUX_GPIO7); +PINCTRL_DEVICE(GPIO8, 1, &MUX_GPIO8); +PINCTRL_DEVICE(GPIO9, 1, &MUX_GPIO9); +PINCTRL_DEVICE(GPIO10, 1, &MUX_GPIO10); +PINCTRL_DEVICE(GPIO11, 1, &MUX_GPIO11); +PINCTRL_DEVICE(GPIO12, 1, &MUX_GPIO12); +PINCTRL_DEVICE(GPIO13, 1, &MUX_GPIO13); +PINCTRL_DEVICE(GPIO14, 1, &MUX_GPIO14); +PINCTRL_DEVICE(GPIO15, 1, &MUX_GPIO15); +PINCTRL_DEVICE(GPIO16, 1, &MUX_GPIO16); +PINCTRL_DEVICE(GPIO17, 1, &MUX_GPIO17); +PINCTRL_DEVICE(GPIO18, 1, &MUX_GPIO18); +PINCTRL_DEVICE(GPIO19, 1, &MUX_GPIO19); +PINCTRL_DEVICE(GPIO20, 1, &MUX_GPIO20); +PINCTRL_DEVICE(GPIO21, 1, &MUX_GPIO21); +PINCTRL_DEVICE(GPIO22, 1, &MUX_GPIO22); +PINCTRL_DEVICE(GPIO23, 1, &MUX_GPIO23); +PINCTRL_DEVICE(GPIO24, 1, &MUX_GPIO24); +PINCTRL_DEVICE(GPIO25, 1, &MUX_GPIO25); +PINCTRL_DEVICE(GPIO26, 1, &MUX_GPIO26); +PINCTRL_DEVICE(GPIO27, 1, &MUX_GPIO27); +PINCTRL_DEVICE(GPIO28, 1, &MUX_GPIO28); +PINCTRL_DEVICE(GPIO29, 1, &MUX_GPIO29); +PINCTRL_DEVICE(GPIO30, 1, &MUX_GPIO30); +PINCTRL_DEVICE(GPIO31, 1, &MUX_GPIO31); +PINCTRL_DEVICE(GPIO32, 1, &MUX_GPIO32); +PINCTRL_DEVICE(GPIO33, 1, &MUX_GPIO33); +PINCTRL_DEVICE(GPIO34, 1, &MUX_GPIO34); +PINCTRL_DEVICE(GPIO35, 1, &MUX_GPIO35); +PINCTRL_DEVICE(GPIO36, 1, &MUX_GPIO36); +PINCTRL_DEVICE(GPIO37, 1, &MUX_GPIO37); +PINCTRL_DEVICE(GPIO38, 1, &MUX_GPIO38); +PINCTRL_DEVICE(GPIO39, 1, &MUX_GPIO39); +PINCTRL_DEVICE(GPIO40, 1, &MUX_GPIO40); +PINCTRL_DEVICE(GPIO41, 1, &MUX_GPIO41); +PINCTRL_DEVICE(GPIO42, 1, &MUX_GPIO42); +PINCTRL_DEVICE(GPIO43, 1, &MUX_GPIO43); +PINCTRL_DEVICE(GPIO44, 1, &MUX_GPIO44); +PINCTRL_DEVICE(GPIO45, 1, &MUX_GPIO45); +PINCTRL_DEVICE(GPIO46, 1, &MUX_GPIO46); +PINCTRL_DEVICE(GPIO47, 1, &MUX_GPIO47); +PINCTRL_DEVICE(GPIO48, 1, &MUX_GPIO48); +PINCTRL_DEVICE(GPIO49, 1, &MUX_GPIO49); +PINCTRL_DEVICE(GPIO50, 1, &MUX_GPIO50); +PINCTRL_DEVICE(GPIO51, 1, &MUX_GPIO51); +PINCTRL_DEVICE(GPIO52, 1, &MUX_GPIO52); +PINCTRL_DEVICE(GPIO53, 1, &MUX_GPIO53); +PINCTRL_DEVICE(GPIO54, 1, &MUX_GPIO54); +PINCTRL_DEVICE(GPIO55, 1, &MUX_GPIO55); +PINCTRL_DEVICE(GPIO56, 1, &MUX_GPIO56); +PINCTRL_DEVICE(GPIO57, 1, &MUX_GPIO57); +PINCTRL_DEVICE(GPIO58, 1, &MUX_GPIO58); +PINCTRL_DEVICE(GPIO59, 1, &MUX_GPIO59); +PINCTRL_DEVICE(GPIO60, 1, &MUX_GPIO60); +PINCTRL_DEVICE(GPIO61, 1, &MUX_GPIO61); +PINCTRL_DEVICE(GPIO62, 1, &MUX_GPIO62); +PINCTRL_DEVICE(GPIO63, 1, &MUX_GPIO63); + +PINCTRL_DEVICE(SD1_EMMC, 6, &MUX_SD1_CLK_EMMC, &MUX_SD1_CMD_RSP_EMMC, + &MUX_SD1_DATA_0_EMMC, &MUX_SD1_DATA_1_EMMC, &MUX_SD1_DATA_2_EMMC, + &MUX_SD1_DATA_3_EMMC); + +void fh_pinctrl_init_devicelist(OS_LIST *list) +{ + OS_LIST_EMPTY(list); + + /*PINCTRL_ADD_DEVICE*/ + PINCTRL_ADD_DEVICE(ACI2S); + PINCTRL_ADD_DEVICE(AC_MCLK); + PINCTRL_ADD_DEVICE(ARCJTAG); + PINCTRL_ADD_DEVICE(ARMJTAG); + PINCTRL_ADD_DEVICE(DWI2S); + PINCTRL_ADD_DEVICE(ETH); + PINCTRL_ADD_DEVICE(I2C0); + PINCTRL_ADD_DEVICE(I2C1); + PINCTRL_ADD_DEVICE(I2C2); + PINCTRL_ADD_DEVICE(PAEJTAG); + PINCTRL_ADD_DEVICE(PWM0); + PINCTRL_ADD_DEVICE(PWM1); + PINCTRL_ADD_DEVICE(PWM10); + PINCTRL_ADD_DEVICE(PWM11); + PINCTRL_ADD_DEVICE(PWM2); + PINCTRL_ADD_DEVICE(PWM3); + PINCTRL_ADD_DEVICE(PWM4); + PINCTRL_ADD_DEVICE(PWM5); + PINCTRL_ADD_DEVICE(PWM6); + PINCTRL_ADD_DEVICE(PWM7); + PINCTRL_ADD_DEVICE(PWM8); + PINCTRL_ADD_DEVICE(PWM9); + PINCTRL_ADD_DEVICE(RMII); + PINCTRL_ADD_DEVICE(RTC); + PINCTRL_ADD_DEVICE(SADC_XAIN0); + PINCTRL_ADD_DEVICE(SADC_XAIN1); + PINCTRL_ADD_DEVICE(SADC_XAIN2); + PINCTRL_ADD_DEVICE(SADC_XAIN3); + PINCTRL_ADD_DEVICE(SD0); + PINCTRL_ADD_DEVICE(SD0_1BIT_NO_WP); + PINCTRL_ADD_DEVICE(SD0_NO_WP); + PINCTRL_ADD_DEVICE(SD0_WIFI); + PINCTRL_ADD_DEVICE(SD1); + PINCTRL_ADD_DEVICE(SD1_1BIT_NO_WP); + PINCTRL_ADD_DEVICE(SD1_NO_WP); + PINCTRL_ADD_DEVICE(SD1_WIFI); + PINCTRL_ADD_DEVICE(SENSOR_CLK); + PINCTRL_ADD_DEVICE(SSI0); + PINCTRL_ADD_DEVICE(SSI0_4BIT); + PINCTRL_ADD_DEVICE(SSI1); + PINCTRL_ADD_DEVICE(SSI2); + PINCTRL_ADD_DEVICE(UART0); + PINCTRL_ADD_DEVICE(UART1); + PINCTRL_ADD_DEVICE(UART2); + PINCTRL_ADD_DEVICE(USB); + PINCTRL_ADD_DEVICE(GPIO0); + PINCTRL_ADD_DEVICE(GPIO1); + PINCTRL_ADD_DEVICE(GPIO2); + PINCTRL_ADD_DEVICE(GPIO3); + PINCTRL_ADD_DEVICE(GPIO4); + PINCTRL_ADD_DEVICE(GPIO5); + PINCTRL_ADD_DEVICE(GPIO6); + PINCTRL_ADD_DEVICE(GPIO7); + PINCTRL_ADD_DEVICE(GPIO8); + PINCTRL_ADD_DEVICE(GPIO9); + PINCTRL_ADD_DEVICE(GPIO10); + PINCTRL_ADD_DEVICE(GPIO11); + PINCTRL_ADD_DEVICE(GPIO12); + PINCTRL_ADD_DEVICE(GPIO13); + PINCTRL_ADD_DEVICE(GPIO14); + PINCTRL_ADD_DEVICE(GPIO15); + PINCTRL_ADD_DEVICE(GPIO16); + PINCTRL_ADD_DEVICE(GPIO17); + PINCTRL_ADD_DEVICE(GPIO18); + PINCTRL_ADD_DEVICE(GPIO19); + PINCTRL_ADD_DEVICE(GPIO20); + PINCTRL_ADD_DEVICE(GPIO21); + PINCTRL_ADD_DEVICE(GPIO22); + PINCTRL_ADD_DEVICE(GPIO23); + PINCTRL_ADD_DEVICE(GPIO24); + PINCTRL_ADD_DEVICE(GPIO25); + PINCTRL_ADD_DEVICE(GPIO26); + PINCTRL_ADD_DEVICE(GPIO27); + PINCTRL_ADD_DEVICE(GPIO28); + PINCTRL_ADD_DEVICE(GPIO29); + PINCTRL_ADD_DEVICE(GPIO30); + PINCTRL_ADD_DEVICE(GPIO31); + PINCTRL_ADD_DEVICE(GPIO32); + PINCTRL_ADD_DEVICE(GPIO33); + PINCTRL_ADD_DEVICE(GPIO34); + PINCTRL_ADD_DEVICE(GPIO35); + PINCTRL_ADD_DEVICE(GPIO36); + PINCTRL_ADD_DEVICE(GPIO37); + PINCTRL_ADD_DEVICE(GPIO38); + PINCTRL_ADD_DEVICE(GPIO39); + PINCTRL_ADD_DEVICE(GPIO40); + PINCTRL_ADD_DEVICE(GPIO41); + PINCTRL_ADD_DEVICE(GPIO42); + PINCTRL_ADD_DEVICE(GPIO43); + PINCTRL_ADD_DEVICE(GPIO44); + PINCTRL_ADD_DEVICE(GPIO45); + PINCTRL_ADD_DEVICE(GPIO46); + PINCTRL_ADD_DEVICE(GPIO47); + PINCTRL_ADD_DEVICE(GPIO48); + PINCTRL_ADD_DEVICE(GPIO49); + PINCTRL_ADD_DEVICE(GPIO50); + PINCTRL_ADD_DEVICE(GPIO51); + PINCTRL_ADD_DEVICE(GPIO52); + PINCTRL_ADD_DEVICE(GPIO53); + PINCTRL_ADD_DEVICE(GPIO54); + PINCTRL_ADD_DEVICE(GPIO55); + PINCTRL_ADD_DEVICE(GPIO56); + PINCTRL_ADD_DEVICE(GPIO57); + PINCTRL_ADD_DEVICE(GPIO58); + PINCTRL_ADD_DEVICE(GPIO59); + PINCTRL_ADD_DEVICE(GPIO60); + PINCTRL_ADD_DEVICE(GPIO61); + PINCTRL_ADD_DEVICE(GPIO62); + PINCTRL_ADD_DEVICE(GPIO63); + + PINCTRL_ADD_DEVICE(SD1_EMMC); +} + +char *fh_pinctrl_selected_devices[] = +{ + CONFIG_PINCTRL_SELECT +}; diff --git a/arch/arm/mach-fh/fh8858v210/Makefile b/arch/arm/mach-fh/fh8858v210/Makefile new file mode 100644 index 00000000..1443fdae --- /dev/null +++ b/arch/arm/mach-fh/fh8858v210/Makefile @@ -0,0 +1 @@ +obj-y += board.o chip.o \ No newline at end of file diff --git a/arch/arm/mach-fh/fh8858v210/board.c b/arch/arm/mach-fh/fh8858v210/board.c new file mode 100644 index 00000000..bc3e265a --- /dev/null +++ b/arch/arm/mach-fh/fh8858v210/board.c @@ -0,0 +1,1123 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +struct uart_port fh_serial_ports[FH_UART_NUMBER]; + +static struct map_desc fh8858v210_io_desc[] = { + { + .virtual = VA_RAM_REG_BASE, + .pfn = __phys_to_pfn(RAM_BASE), + .length = SZ_16K, + .type = MT_MEMORY_RWX, + }, + { + .virtual = VA_DDRC_REG_BASE, + .pfn = __phys_to_pfn(DDRC_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_INTC_REG_BASE, + .pfn = __phys_to_pfn(INTC_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_TIMER_REG_BASE, + .pfn = __phys_to_pfn(TIMER_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_PMU_REG_BASE, + .pfn = __phys_to_pfn(PMU_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_UART0_REG_BASE, + .pfn = __phys_to_pfn(UART0_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_UART1_REG_BASE, + .pfn = __phys_to_pfn(UART1_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + { + .virtual = VA_UART2_REG_BASE, + .pfn = __phys_to_pfn(UART2_REG_BASE), + .length = SZ_16K, + .type = MT_DEVICE, + }, + +}; + +static struct resource fh_gpio0_resources[] = { + { + .start = GPIO0_REG_BASE, + .end = GPIO0_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = GPIO0_IRQ, + .end = GPIO0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_gpio1_resources[] = { + { + .start = GPIO1_REG_BASE, + .end = GPIO1_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = GPIO1_IRQ, + .end = GPIO1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_uart0_resources[] = { + { + .start = (UART0_REG_BASE), + .end = (UART0_REG_BASE) + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = UART0_IRQ, + .end = UART0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_uart1_resources[] = { + { + .start = (UART1_REG_BASE), + .end = (UART1_REG_BASE) + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = UART1_IRQ, + .end = UART1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_uart2_resources[] = { + { + .start = (UART2_REG_BASE), + .end = (UART2_REG_BASE) + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = UART2_IRQ, + .end = UART2_IRQ, + .flags = IORESOURCE_IRQ, + } +}; +static struct resource fh_sdc0_resources[] = { + { + .start = SDC0_REG_BASE, + .end = SDC0_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SDC0_IRQ, + .end = SDC0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_sdc1_resources[] = { + { + .start = SDC1_REG_BASE, + .end = SDC1_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SDC1_IRQ, + .end = SDC1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_gmac_resources[] = { + { + .start = GMAC_REG_BASE, + .end = GMAC_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = GMAC_IRQ, + .end = GMAC_IRQ, + .flags = IORESOURCE_IRQ, + } +}; + +static struct resource fh_wdt_resources[] = { + { + .start = WDT_REG_BASE, + .end = WDT_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = WDT_IRQ, + .end = WDT_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +#ifdef CONFIG_FH_PERF_MON +static struct resource fh_perf_resources[] = { + { + .start = PMU_REG_BASE, + .end = PMU_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = PERF_IRQ, + .end = PERF_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +#endif + + +static struct fh_gmac_platform_data fh_gmac_data = { + .phy_reset_pin = 29, +}; + +static struct fh_uart_dma uart1_dma_info = { +#ifdef CONFIG_UART_TX_DMA + .tx_hs_no = UART1_TX_HW_HANDSHAKE, + .tx_dma_channel = UART1_DMA_TX_CHAN, +#endif + .rx_hs_no = UART1_RX_HW_HANDSHAKE, + .rx_dma_channel = UART1_DMA_RX_CHAN, + .rx_xmit_len = 16, +}; + +static struct fh_uart_dma uart2_dma_info = { +#ifdef CONFIG_UART_TX_DMA + .tx_hs_no = UART2_TX_HW_HANDSHAKE, + .tx_dma_channel = UART2_DMA_TX_CHAN, +#endif + .rx_hs_no = UART2_RX_HW_HANDSHAKE, + .rx_dma_channel = UART2_DMA_RX_CHAN, + .rx_xmit_len = 16, +}; + + +static struct fh_platform_uart fh_uart_platform_data[] = { + { + .mapbase = UART0_REG_BASE, + .fifo_size = 16, + .irq = UART0_IRQ, + .uartclk = 16666667, + .use_dma = 0, + .dma_info = NULL, + }, + { + .mapbase = UART1_REG_BASE, + .fifo_size = 32, + .irq = UART1_IRQ, + .uartclk = 16666667, + .use_dma = 0, + .dma_info = &uart1_dma_info, + }, + { + .mapbase = UART2_REG_BASE, + .fifo_size = 32, + .irq = UART2_IRQ, + .uartclk = 16666667, + .use_dma = 0, + .dma_info = &uart2_dma_info, + }, +}; + +static struct resource fh_pwm_resources[] = { + { + .start = PWM_REG_BASE, + .end = PWM_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = PWM_IRQ, + .end = PWM_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_i2c_resources_0[] = { + { + .start = I2C0_REG_BASE, + .end = I2C0_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = I2C0_IRQ, + .end = I2C0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_i2c_resources_1[] = { + { + .start = I2C1_REG_BASE, + .end = I2C1_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = I2C1_IRQ, + .end = I2C1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_i2c_resources_2[] = { + { + .start = I2C2_REG_BASE, + .end = I2C2_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = I2C2_IRQ, + .end = I2C2_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static struct resource fh_rtc_resources[] = { + { + .start = RTC_REG_BASE, + .end = RTC_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + + { + .start = RTC_IRQ, + .end = RTC_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct fh_gpio_chip fh_gpio0_chip = { + .chip = { + .owner = THIS_MODULE, + .label = "FH_GPIO0", + .base = 0, + .ngpio = 32, + }, +}; + +static struct fh_gpio_chip fh_gpio1_chip = { + .chip = { + .owner = THIS_MODULE, + .label = "FH_GPIO1", + .base = 32, + .ngpio = 32, + }, +}; + +static struct fh_pwm_data pwm_data = { + .npwm = 12, +}; + +static struct resource fh_sadc_resources[] = { + { + .start = SADC_REG_BASE, + .end = SADC_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SADC_IRQ, + .end = SADC_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_aes_resources[] = { + { + .start = AES_REG_BASE, + .end = AES_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = AES_IRQ, + .end = AES_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_efuse_resources[] = { + { + .start = EFUSE_REG_BASE, + .end = EFUSE_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, +}; + + +static struct resource fh_axi_dma_resources[] = { + { + .start = (DMAC_REG_BASE), + .end = (DMAC_REG_BASE) + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = DMAC0_IRQ, + .end = DMAC0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + + +static struct resource fh_spi0_resources[] = { + { + .start = SPI0_REG_BASE, + .end = SPI0_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SPI0_IRQ, + .end = SPI0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_spi1_resources[] = { + { + .start = SPI1_REG_BASE, + .end = SPI1_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = SPI1_IRQ, + .end = SPI1_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource fh_spi2_resources[] = { + { + .start = SPI2_REG_BASE, + .end = SPI2_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + .name = "fh spi2 mem", + }, + { + .start = SPI2_IRQ, + .end = SPI2_IRQ, + .flags = IORESOURCE_IRQ, + .name = "fh spi2 irq", + }, +}; + +static struct resource fh_usb_resources[] = { + { + .start = USBC_REG_BASE, + .end = USBC_REG_BASE + SZ_1M - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = USBC_IRQ, + .end = USBC_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; +static unsigned int fh_mci_sys_card_detect_fixed(struct fhmci_host *host) +{ + return 0; +} + +struct fh_mci_board fh_mci = { + .num_slots = 1, + .get_cd = fh_mci_sys_card_detect_fixed, + .bus_hz = 50000000, + .detect_delay_ms = 200, + .caps = MMC_CAP_4_BIT_DATA, + /*8:180 degree*/ + .drv_degree = 8, + .sam_degree = 0, + .rescan_max_num = 2, +}; + +struct fh_mci_board fh_mci_sd = { + .num_slots = 1, + .bus_hz = 50000000, + .detect_delay_ms = 200, + .caps = MMC_CAP_4_BIT_DATA, + /*8:180 degree*/ + .drv_degree = 8, + .sam_degree = 0, +}; + +static struct platform_device fh_gmac_device = { + .name = "fh_gmac", + .id = 0, + .num_resources = ARRAY_SIZE(fh_gmac_resources), + .resource = fh_gmac_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &fh_gmac_data, + }, +}; + +struct platform_device fh_sd0_device = { + .name = "fh_mci", + .id = 0, + .num_resources = ARRAY_SIZE(fh_sdc0_resources), + .resource = fh_sdc0_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &fh_mci_sd, + } +}; + +struct platform_device fh_sd1_device = { + .name = "fh_mci", + .id = 1, + .num_resources = ARRAY_SIZE(fh_sdc1_resources), + .resource = fh_sdc1_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &fh_mci, + } +}; + +struct fh_sadc_platform_data fh_sadc_data = { + .ref_vol = 1800, + .active_bit = 0xfff, +}; + +static struct platform_device fh_sadc_device = { + .name = "fh_sadc", + .id = 0, + .num_resources = ARRAY_SIZE(fh_sadc_resources), + .resource = fh_sadc_resources, + .dev = { + .platform_data = &fh_sadc_data, + }, +}; + +static struct platform_device fh_uart0_device = { + .name = "ttyS", + .id = 0, + .num_resources = ARRAY_SIZE(fh_uart0_resources), + .resource = fh_uart0_resources, + .dev.platform_data = &fh_uart_platform_data[0], +}; + +static struct platform_device fh_uart1_device = { + .name = "ttyS", + .id = 1, + .num_resources = ARRAY_SIZE(fh_uart1_resources), + .resource = fh_uart1_resources, + .dev.platform_data = &fh_uart_platform_data[1], +}; + +static struct platform_device fh_uart2_device = { + .name = "ttyS", + .id = 2, + .num_resources = ARRAY_SIZE(fh_uart2_resources), + .resource = fh_uart2_resources, + .dev.platform_data = &fh_uart_platform_data[2], +}; + +static struct platform_device fh_pinctrl_device = { + .name = "fh_pinctrl", + .id = 0, +}; + +static struct platform_device fh_i2c0_device = { + .name = "fh_i2c", + .id = 0, + .num_resources = ARRAY_SIZE(fh_i2c_resources_0), + .resource = fh_i2c_resources_0, +}; + +static struct platform_device fh_i2c1_device = { + .name = "fh_i2c", + .id = 1, + .num_resources = ARRAY_SIZE(fh_i2c_resources_1), + .resource = fh_i2c_resources_1, +}; + +static struct platform_device fh_i2c2_device = { + .name = "fh_i2c", + .id = 2, + .num_resources = ARRAY_SIZE(fh_i2c_resources_2), + .resource = fh_i2c_resources_2, +}; + +static struct fh_rtc_plat_data rtc_plat_data[] = { + { + .lut_cof = 58, + .lut_offset = 0xff, + .tsensor_cp_default_out = 0x993, + .clk_name = "rtc_hclk_gate", + }, + { + .lut_cof = 71, + .lut_offset = 0xf6, + .tsensor_cp_default_out = 0x9cc, + .clk_name = "rtc_hclk_gate", + } +}; + +static struct platform_device fh_rtc_device = { + .name = "fh_rtc", + .id = 0, + .num_resources = ARRAY_SIZE(fh_rtc_resources), + .resource = fh_rtc_resources, + .dev.platform_data = &rtc_plat_data[0], +}; + +static struct resource fh_i2s_resources[] = { + { + .start = I2S_REG_BASE, + .end = I2S_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = ACW_REG_BASE, + .end = ACW_REG_BASE + SZ_16K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = I2S0_IRQ, + .end = I2S0_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct fh_i2s_platform_data fh_i2s_data = { + .dma_capture_channel = 4, + .dma_playback_channel = 5, + .dma_master = 0, + .dma_rx_hs_num = 10, + .dma_tx_hs_num = 11, + .clk = "i2s_clk", + .acodec_mclk = "ac_clk", +}; + +static struct platform_device fh_i2s_device = { + .name = "fh_audio", + .id = 0, + .num_resources = ARRAY_SIZE(fh_i2s_resources), + .resource = fh_i2s_resources, + .dev = { + .platform_data = &fh_i2s_data, + }, +}; + +static struct platform_device fh_gpio0_device = { + .name = GPIO_NAME, + .id = 0, + .num_resources = ARRAY_SIZE(fh_gpio0_resources), + .resource = fh_gpio0_resources, + .dev = { + .platform_data = &fh_gpio0_chip, + }, +}; + +static struct platform_device fh_gpio1_device = { + .name = GPIO_NAME, + .id = 1, + .num_resources = ARRAY_SIZE(fh_gpio1_resources), + .resource = fh_gpio1_resources, + .dev = { + .platform_data = &fh_gpio1_chip, + }, +}; + +static struct platform_device fh_aes_device = { + .name = "fh_aes", + .id = 0, + .num_resources = ARRAY_SIZE(fh_aes_resources), + .resource = fh_aes_resources, + .dev = { + .platform_data = NULL, + }, +}; + +struct fh_efuse_platform_data fh_efuse_plat_data = { + .efuse_support_flag = CRYPTO_CPU_SET_KEY | + CRYPTO_EX_MEM_SET_KEY | + CRYPTO_EX_MEM_SWITCH_KEY | + CRYPTO_EX_MEM_4_ENTRY_1_KEY | + CRYPTO_EX_MEM_INDEP_POWER, +}; + + + +#define FH_SPI0_CS0 (6) +#define FH_SPI0_CS1 (55) + +#define FH_SPI1_CS0 (14) +#define FH_SPI1_CS1 (57) + +#define SPI0_FIFO_DEPTH (128) +#define SPI0_CLK_IN (200000000) +#define SPI0_MAX_SLAVE_NO (2) +#define SPI0_DMA_RX_CHANNEL (0) +#define SPI0_DMA_TX_CHANNEL (1) + +#define SPI1_FIFO_DEPTH (64) +#define SPI1_CLK_IN (100000000) +#define SPI1_MAX_SLAVE_NO (2) +#define SPI1_DMA_RX_CHANNEL (2) +#define SPI1_DMA_TX_CHANNEL (3) + +#define SPI2_CLK_IN (100000000) + +/* SPI_TRANSFER_USE_DMA */ +static struct fh_spi_platform_data fh_spi0_data = { + .bus_no = 0, + .apb_clock_in = SPI0_CLK_IN, + .clock_source = {100000000, 150000000, 200000000}, + .clock_source_num = 3, + .slave_max_num = SPI0_MAX_SLAVE_NO, + .cs_data[0].GPIO_Pin = FH_SPI0_CS0, + .cs_data[0].name = "spi0_cs0", + .cs_data[1].GPIO_Pin = FH_SPI0_CS1, + .cs_data[1].name = "spi0_cs1", + .clk_name = "spi0_clk", + .dma_transfer_enable = SPI_TRANSFER_USE_DMA, + .rx_dma_channel = SPI0_DMA_RX_CHANNEL, + .rx_handshake_num = 4, + /*dma use inc mode could move data by burst mode...*/ + /*or move data use single mode with low efficient*/ + .ctl_wire_support = ONE_WIRE_SUPPORT | DUAL_WIRE_SUPPORT | + MULTI_WIRE_SUPPORT, +}; + +static struct fh_spi_platform_data fh_spi1_data = { + .bus_no = 1, + .apb_clock_in = SPI1_CLK_IN, + .clock_source = {SPI1_CLK_IN}, + .clock_source_num = 1, + .slave_max_num = SPI1_MAX_SLAVE_NO, + .cs_data[0].GPIO_Pin = FH_SPI1_CS0, + .cs_data[0].name = "spi1_cs0", + .cs_data[1].GPIO_Pin = FH_SPI1_CS1, + .cs_data[1].name = "spi1_cs1", + .clk_name = "spi1_clk", + .ctl_wire_support = 0, +}; + +static struct fh_spi_platform_data fh_spi2_data = { + .apb_clock_in = SPI2_CLK_IN, + .dma_transfer_enable = 0, + .rx_handshake_num = 12, + .clk_name = "spi2_clk", + .ctl_wire_support = 0, +}; + +static struct platform_device fh_efuse_device = { + .name = "fh_efuse", + .id = 0, + .num_resources = ARRAY_SIZE(fh_efuse_resources), + .resource = fh_efuse_resources, + .dev = { + .platform_data = &fh_efuse_plat_data, + }, +}; + +struct fh_axi_dma_platform_data axi_dma_plat_data = { + .chan_priority = CHAN_PRIORITY_ASCENDING, + .clk_name = "ahb_clk", +}; + +static struct platform_device fh_axi_dma_device = { + .name = "fh_axi_dmac", + .id = 0, + .num_resources = ARRAY_SIZE(fh_axi_dma_resources), + .resource = fh_axi_dma_resources, + .dev = { + .platform_data = &axi_dma_plat_data, + }, +}; + +static struct platform_device fh_spi0_device = { + .name = "fh_spi", + .id = 0, + .num_resources = ARRAY_SIZE(fh_spi0_resources), + .resource = fh_spi0_resources, + .dev = { + .platform_data = &fh_spi0_data, + }, +}; + +static struct platform_device fh_spi1_device = { + .name = "fh_spi", + .id = 1, + .num_resources = ARRAY_SIZE(fh_spi1_resources), + .resource = fh_spi1_resources, + .dev = { + .platform_data = &fh_spi1_data, + }, +}; + +static struct platform_device fh_spi2_device = { + .name = "fh_spi_slave", + .id = 0, + .num_resources = ARRAY_SIZE(fh_spi2_resources), + .resource = fh_spi2_resources, + .dev = { + .platform_data = &fh_spi2_data, + }, +}; + +#ifdef CONFIG_FH_PERF_MON +static struct platform_device fh_perf_device = { + .name = "fh_perf_mon", + .id = 0, + .num_resources = ARRAY_SIZE(fh_perf_resources), + .resource = fh_perf_resources, + .dev = { + .platform_data = NULL, + }, +}; +#endif + + +static struct fh_wdt_platform_data fh_wdt_data = { + .mode = MODE_DISCRETE, +}; + +struct platform_device fh_wdt_device = { + .name = "fh_wdt", + .id = 0, + .num_resources = ARRAY_SIZE(fh_wdt_resources), + .resource = fh_wdt_resources, + .dev = { + .platform_data = &fh_wdt_data, + } +}; + +static struct platform_device fh_pwm_device = { + .name = "fh_pwm", + .id = 0, + .num_resources = ARRAY_SIZE(fh_pwm_resources), + .resource = fh_pwm_resources, + .dev = { + .platform_data = &pwm_data, + }, +}; + +static struct fh_usb_platform_data fh_usb_data = { + .dr_mode = "host", + .vbus_pwren = 47, +}; + +struct platform_device fh_usb_device = { + .name = "fh_usb", + .id = 0, + .num_resources = ARRAY_SIZE(fh_usb_resources), + .resource = fh_usb_resources, + .dev = { + .platform_data = &fh_usb_data, + } +}; + +#ifdef CONFIG_FH_TSENSOR +struct platform_device fh_tsensor_device = { + .name = "fh_tsensor", + .id = 0, +}; +#endif + +static struct platform_device *fh8858v210_devices[] __initdata = { + &fh_uart0_device, + &fh_uart1_device, + &fh_uart2_device, + &fh_pinctrl_device, + &fh_i2c0_device, + &fh_i2c1_device, + &fh_i2c2_device, + &fh_rtc_device, + &fh_sd0_device, + &fh_sd1_device, + &fh_sadc_device, + &fh_gmac_device, + &fh_gpio0_device, + &fh_gpio1_device, + &fh_aes_device, + &fh_efuse_device, + &fh_axi_dma_device, + &fh_spi0_device, + &fh_spi1_device, + &fh_spi2_device, + &fh_i2s_device, + &fh_pwm_device, + &fh_wdt_device, + &fh_usb_device, +#ifdef CONFIG_FH_PERF_MON + &fh_perf_device, +#endif +#ifdef CONFIG_FH_TSENSOR + &fh_tsensor_device, +#endif +}; + +static struct mtd_partition fh_sf_parts[] = { + { + /* head & Ramboot */ + .name = "bootstrap", + .offset = 0, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + /* Ramboot & U-Boot environment */ + .name = "uboot-env", + .offset = MTDPART_OFS_APPEND, + .size = SZ_64K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + /* U-Boot */ + .name = "uboot", + .offset = MTDPART_OFS_APPEND, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_4M, + .mask_flags = 0, + }, { + .name = "rootfs", + .offset = MTDPART_OFS_APPEND, + .size = SZ_8M, + .mask_flags = 0, + }, { + .name = "app", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + } + /* mtdparts= + * spi_flash:256k(bootstrap), + * 64k(u-boot-env), + * 192k(u-boot),4M(kernel), + * 8M(rootfs), + * -(app) */ + /* two blocks with bad block table (and mirror) at the end */ +}; +#ifdef CONFIG_MTD_SPI_NAND +static struct mtd_partition fh_sf_nand_parts[] = { + { + /* head & Ramboot */ + .name = "bootstrap", + .offset = 0, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, { + .name = "uboot-env", + .offset = MTDPART_OFS_APPEND, + .size = SZ_256K, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "uboot", + .offset = MTDPART_OFS_APPEND, + .size = SZ_512K, + .mask_flags = MTD_WRITEABLE, + }, { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = SZ_4M, + .mask_flags = 0, + }, { + .name = "rootfs", + .offset = MTDPART_OFS_APPEND, + .size = SZ_8M, + .mask_flags = 0, + }, { + .name = "app", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + .mask_flags = 0, + } + /* mtdparts= + * spi0.0:64k(bootstrap), + * 64k(u-boot-env), + * 192k(u-boot), + * 4M(kernel), + * 8M(rootfs), + * -(app) + * two blocks with bad block table (and mirror) at the end + */ +}; +#endif + +static struct flash_platform_data fh_flash_platform_data = { + .name = "spi_flash", + .parts = fh_sf_parts, + .nr_parts = ARRAY_SIZE(fh_sf_parts), +}; +#ifdef CONFIG_MTD_SPI_NAND +static struct flash_platform_data fh_nandflash_platform_data = { + .name = "spi_nandflash", + .parts = fh_sf_nand_parts, + .nr_parts = ARRAY_SIZE(fh_sf_nand_parts), +}; +#endif + +static struct spi_board_info fh_spi_devices[] = { +#ifdef CONFIG_MTD_SPI_NAND + { + .modalias = "spi-nand", + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 50000000, + .mode = SPI_MODE_3, + .platform_data = &fh_nandflash_platform_data, + }, +#endif + { + .modalias = "m25p80", + .bus_num = 0, + .chip_select = 0, + /* multi wire should adapt spi para 'ctl_wire_support'*/ + .mode = SPI_MODE_3 | SPI_RX_DUAL, + .max_speed_hz = 50000000, + .platform_data = &fh_flash_platform_data, + }, + +}; + +extern void early_print(const char *str, ...); + +static void __init fh_console_pre_init(struct fh_platform_uart *plat, int num) +{ + int idx = 0; + + for (; idx < num; idx++) { + struct uart_port *port; + + port = &fh_serial_ports[idx]; + port->mapbase = plat[idx].mapbase; + port->fifosize = plat[idx].fifo_size; + port->uartclk = plat[idx].uartclk; + + switch (idx) { + case 0: + port->membase = (unsigned char *)VA_UART0_REG_BASE; + break; + case 1: + port->membase = (unsigned char *)VA_UART1_REG_BASE; + break; + case 2: + port->membase = (unsigned char *)VA_UART2_REG_BASE; + break; + default: + break; + } + } +} + +static void __init fh8858v210_map_io(void) +{ + iotable_init(fh8858v210_io_desc, ARRAY_SIZE(fh8858v210_io_desc)); + fh_console_pre_init(fh_uart_platform_data, + ARRAY_SIZE(fh_uart_platform_data)); +} + + +static __init void fh8858v210_board_init(void) +{ + if (fh_is_8858v210()) + fh_rtc_device.dev.platform_data = &rtc_plat_data[1]; + platform_add_devices(fh8858v210_devices, + ARRAY_SIZE(fh8858v210_devices)); + spi_register_board_info(fh_spi_devices, ARRAY_SIZE(fh_spi_devices)); +} +void __init fh_timer_init_no_of(unsigned int iovbase, + unsigned int irqno); + +static void __init fh8858v210_init_early(void) +{ + fh_pmu_init(); + fh_pinctrl_init(VA_PMU_REG_BASE + 0x80); +} + +static void __init fh_time_init(void) +{ + unsigned int vtimerbase = (unsigned int)ioremap(TIMER_REG_BASE, SZ_4K); + + fh_clk_init(); + fh_timer_init_no_of(vtimerbase, TMR0_IRQ); + +} + +void __init fh_intc_init_no_of(unsigned int iovbase); +static void __init fh_intc_init(void) +{ + unsigned int vintcbase = (unsigned int)ioremap(INTC_REG_BASE, SZ_4K); + + fh_intc_init_no_of(vintcbase); + +} +static void fh8858v210_restart + (enum reboot_mode mode, const char *cmd) +{ + fh_pmu_restart(); +} + + +MACHINE_START(FH8858V210, "FH8858V210") + .atag_offset = 0x100, + .map_io = fh8858v210_map_io, + .init_irq = fh_intc_init, + .init_time = fh_time_init, + .init_machine = fh8858v210_board_init, + .init_early = fh8858v210_init_early, + .restart = fh8858v210_restart, +MACHINE_END + diff --git a/arch/arm/mach-fh/fh8858v210/board_config.fh8858v210.appboard b/arch/arm/mach-fh/fh8858v210/board_config.fh8858v210.appboard new file mode 100644 index 00000000..335a1304 --- /dev/null +++ b/arch/arm/mach-fh/fh8858v210/board_config.fh8858v210.appboard @@ -0,0 +1,45 @@ +#ifndef BOARD_CONFIG_H_ +#define BOARD_CONFIG_H_ + +/* + * GPIO0 -> IRCUT_ON + * GPIO1 -> IRCUT_OFF + * GPIO2 -> USB_PWREN + * GPIO11 -> EMAC PHY Reset + * GPIO12 -> CIS_CLK + * GPIO13 -> CIS_RSTN + * GPIO14 -> CIS_PDN + * GPIO19 -> SD1_PWREN/WIFI_REG_ON + * GPIO20 -> AK7755 Reset + * GPIO24 -> LED0 + * GPIO25 -> LED1 + * GPIO26 -> Reset Configs + * GPIO27 -> AK7755 PowerDown + * GPIO28 -> IR + * GPIO53 -> USB_PWREN/SD0_PWREN + * GPIO55 -> SD1 WIFI Interrupt + */ + +#define CONFIG_SD_CD_FIXED + +#define CONFIG_ISP_CLK_RATE 200000000 +#define CONFIG_JPEG_CLK_RATE 200000000 +#define CONFIG_VEU_CLK_RATE 300000000 + +#define USB_VBUS_PWR_GPIO (47) + +#define ETH_GPIO "ETH", "GPIO48", "GPIO49", "GPIO50", "GPIO51", "GPIO52",\ + "GPIO53", "GPIO54", "GPIO55", "GPIO56" + +#define CONFIG_PINCTRL_SELECT \ + "I2C0", "PWM2", "PWM3", "PWM4", "PWM5", "PWM6", "PWM7", \ + "PWM8", "PWM9", "SADC_XAIN0", "SADC_XAIN1", \ + "SADC_XAIN2", "SADC_XAIN3", "SD0_NO_WP", "SD1_NO_WP", \ + "SENSOR_CLK", "SSI0_4BIT", "UART0", "UART1", "GPIO4", \ + "GPIO13", "GPIO14", "GPIO15", ETH_GPIO, \ + "GPIO30", "GPIO31", "GPIO32", "GPIO43", "GPIO44", \ + "GPIO47", \ +\ + "GPIO11", "GPIO16", "GPIO45", "GPIO46" + +#endif /* BOARD_CONFIG_H_ */ diff --git a/arch/arm/mach-fh/fh8858v210/chip.c b/arch/arm/mach-fh/fh8858v210/chip.c new file mode 100644 index 00000000..9bbb3c49 --- /dev/null +++ b/arch/arm/mach-fh/fh8858v210/chip.c @@ -0,0 +1,747 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * external oscillator + * fixed to 24M + */ +static struct fh_clk osc_clk = { + .name = "osc_clk", + .frequency = OSC_FREQUENCY, + .flag = CLOCK_FIXED, +}; + +/* + * phase-locked-loop device, + * generates a higher frequency clock + * from the external oscillator reference + *PLL_DDR + */ + +static struct fh_clk pll_ddr_rclk = { + .name = "pll_ddr_rclk", + .flag = CLOCK_PLL_R|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL0, + .en_reg_offset = REG_PMU_PLL0_CTRL, + .en_reg_mask = 0xf000, +}; + +/*PLL_CPU*/ +static struct fh_clk pll_cpu_pclk = { + .name = "pll_cpu_pclk", + .flag = CLOCK_PLL_P|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL1, + .en_reg_offset = REG_PMU_PLL1_CTRL, + .en_reg_mask = 0xf00, +}; + +static struct fh_clk pll_cpu_rclk = { + .name = "pll_cpu_rclk", + .flag = CLOCK_PLL_R|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL1, + .en_reg_offset = REG_PMU_PLL1_CTRL, + .en_reg_mask = 0xf000, +}; + +/*PLL_SYS*/ +static struct fh_clk pll_sys_pclk = { + .name = "pll_sys_pclk", + .flag = CLOCK_PLL_P|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL2, + .en_reg_offset = REG_PMU_PLL2_CTRL, + .en_reg_mask = 0xf00, +}; + + +static struct fh_clk pll_sys_rclk = { + .name = "pll_sys_rclk", + .flag = CLOCK_PLL_R|CLOCK_NOGATE, + .parent = {&osc_clk}, + .div_reg_offset = REG_PMU_PLL2, + .en_reg_offset = REG_PMU_PLL2_CTRL, + .en_reg_mask = 0xf000, +}; + +static struct fh_clk pllsysp_div12_clk = { + .name = "pllsysp_div12_clk", + .flag = CLOCK_NORESET|CLOCK_NOGATE, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV5, + .div_reg_mask = 0xf000000, +}; + +static struct fh_clk ddr_clk = { + .name = "ddr_clk", + .flag = CLOCK_NODIV, + .parent = {&pll_ddr_rclk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x4000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x8, +}; +static struct fh_clk arm_clk = { + .name = "arm_clk", + .flag = CLOCK_MULTI_PARENT|CLOCK_NOGATE|CLOCK_NODIV, + .parent = {&osc_clk, &pll_cpu_pclk}, + .prediv = 1, + .sel_reg_offset = REG_PMU_SYS_CTRL, + .sel_reg_mask = 0x1, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x1, +}; +static struct fh_clk arc_clk = { + .name = "arc_clk", + .flag = CLOCK_MULTI_PARENT|CLOCK_NODIV, + .parent = {&osc_clk, &pll_cpu_rclk}, + .prediv = 1, + .sel_reg_offset = REG_PMU_SYS_CTRL, + .sel_reg_mask = 0x1, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x400000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x400000, +}; +static struct fh_clk ahb_clk = { + .name = "ahb_clk", + .flag = CLOCK_MULTI_PARENT|CLOCK_NORESET|CLOCK_NOGATE, + .parent = {&osc_clk, &pll_sys_pclk}, + .prediv = 1, + .sel_reg_offset = REG_PMU_SYS_CTRL, + .sel_reg_mask = 0x1, + .div_reg_offset = REG_PMU_CLK_DIV0, + .div_reg_mask = 0xf0000, +}; + +static struct fh_clk isp_aclk = { + .name = "isp_aclk", + .flag = CLOCK_NORESET, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV0, + .div_reg_mask = 0xf00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x1, + .def_rate = CONFIG_ISP_CLK_RATE, +}; +static struct fh_clk ispb_aclk = { + .name = "ispb_aclk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&isp_aclk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x4, +}; + +static struct fh_clk vpu_clk = { + .name = "vpu_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&isp_aclk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x80000000, +}; + +static struct fh_clk pix_clk = { + .name = "pix_clk", + .flag = CLOCK_NORESET|CLOCK_NOGATE, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV2, + .div_reg_mask = 0xf000000, +}; + +static struct fh_clk jpeg_clk = { + .name = "jpeg_clk", + .flag = CLOCK_NORESET, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV7, + .div_reg_mask = 0xf00000, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x40000000, + .def_rate = CONFIG_JPEG_CLK_RATE, +}; + +static struct fh_clk bgm_clk = { + .name = "bgm_clk", + .flag = CLOCK_NORESET, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV7, + .div_reg_mask = 0xf00000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x40000, +}; + +static struct fh_clk jpeg_adapt_clk = { + .name = "jpeg_adapt_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&jpeg_clk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x2, +}; +static struct fh_clk spi0_clk = { + .name = "spi0_clk", + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xff, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x80, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x100, +}; +static struct fh_clk sdc0_clk = { + .name = "sdc0_clk", + .parent = {&pll_sys_pclk}, + .prediv = 8, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xf00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x200, + .rst_reg_offset = REG_PMU_SWRST_AHB_CTRL, + .rst_reg_mask = 0x4, +}; +static struct fh_clk spi2_clk = { + .name = "spi2_clk", + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xf000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x2, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x100000, +}; +static struct fh_clk spi1_clk = { + .name = "spi1_clk", + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xff0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x100, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x200, +}; +static struct fh_clk sdc1_clk = { + .name = "sdc1_clk", + .parent = {&pll_sys_pclk}, + .prediv = 8, + .div_reg_offset = REG_PMU_CLK_DIV3, + .div_reg_mask = 0xf000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x400, + .rst_reg_offset = REG_PMU_SWRST_AHB_CTRL, + .rst_reg_mask = 0x2, +}; + +static struct fh_clk veu_clk = { + .name = "veu_clk", + .flag = CLOCK_MULTI_PARENT, + .parent = {&pll_sys_pclk, &pll_sys_rclk}, + .prediv = 1, + .sel_reg_offset = REG_PMU_SYS_CTRL, + .sel_reg_mask = 0x4, + .div_reg_offset = REG_PMU_CLK_DIV0, + .div_reg_mask = 0x7000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x10, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x2000000, + .def_rate = CONFIG_VEU_CLK_RATE, + +}; + +static struct fh_clk veu_adapt_clk = { + .name = "veu_adapt_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&veu_clk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x20000000, + +}; + +static struct fh_clk cis_clk_out = { + .name = "cis_clk_out", + .flag = CLOCK_NORESET, + .parent = {&pll_sys_pclk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV1, + .div_reg_mask = 0xff0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x800000, +}; + +static struct fh_clk eth_clk = { + .name = "eth_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV6, + .div_reg_mask = 0xf000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x12000000, + .rst_reg_offset = REG_PMU_SWRST_AHB_CTRL, + .rst_reg_mask = 0x20000, +}; +static struct fh_clk i2c0_clk = { + .name = "i2c0_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV4, + .div_reg_mask = 0x3f0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x1000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x400, +}; + +static struct fh_clk i2c1_clk = { + .name = "i2c1_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV4, + .div_reg_mask = 0x3f000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x8000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x800, +}; + +static struct fh_clk i2c2_clk = { + .name = "i2c2_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV7, + .div_reg_mask = 0x00003f00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x00000008, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x20000000, +}; + +static struct fh_clk pwm_clk = { + .name = "pwm_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV5, + .div_reg_mask = 0xff, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x10000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x80, + .def_rate = 50000000, +}; + +static struct fh_clk uart0_clk = { + .name = "uart0_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV4, + .div_reg_mask = 0x1f, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x2000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x4000, + .def_rate = 16666666, +}; + +static struct fh_clk uart1_clk = { + .name = "uart1_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV4, + .div_reg_mask = 0x1f00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x4000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x8000, + .def_rate = 16666666, +}; +static struct fh_clk uart2_clk = { + .name = "uart2_clk", + .parent = {&pllsysp_div12_clk}, + .flag = 0, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV7, + .div_reg_mask = 0x7f, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x8000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x8000000, + .def_rate = 16666666, +}; + +static struct fh_clk efuse_clk = { + .name = "efuse_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV1, + .div_reg_mask = 0x3f000000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x200000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x800000, +}; + +static struct fh_clk pts_clk = { + .name = "pts_clk", + .parent = {&pllsysp_div12_clk}, + .flag = CLOCK_NORESET, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV2, + .div_reg_mask = 0x1ff, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x80000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL2, + .rst_reg_mask = 0x1, + .def_rate = 1000000, +}; + +static struct fh_clk tmr0_clk = { + .name = "tmr0_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV5, + .div_reg_mask = 0xff0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x20000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x40000, +}; + +static struct fh_clk sadc_clk = { + .name = "sadc_clk", + .parent = {&pllsysp_div12_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV6, + .div_reg_mask = 0x7f0000, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x4000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x10000, +}; + +static struct fh_clk ac_clk = { + .name = "ac_clk", + .parent = {&osc_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV6, + .div_reg_mask = 0x3f, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x800, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x1000, +}; + +static struct fh_clk i2s_clk = { + .name = "i2s_clk", + .parent = {&ac_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV6, + .div_reg_mask = 0x3f00, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x1000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x2000, +}; + +static struct fh_clk wdt_clk = { + .name = "wdt_clk", + .flag = 0, + .parent = {&ahb_clk}, + .prediv = 1, + .div_reg_offset = REG_PMU_CLK_DIV5, + .div_reg_mask = 0xff00, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x8000000, + .rst_reg_offset = REG_PMU_SWRST_APB_CTRL, + .rst_reg_mask = 0x100000, + .def_rate = 1000000, +}; + +static struct fh_clk gpio0_db_clk = { + .name = "gpio0_db_clk", + .flag = 0, + .parent = {&pllsysp_div12_clk}, + .prediv = 100, + .div_reg_offset = REG_PMU_CLK_DIV8, + .div_reg_mask = 0x7fff, + .en_reg_offset = REG_PMU_CLK_DIV8, + .en_reg_mask = 0x8000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x10, +}; + +static struct fh_clk gpio1_db_clk = { + .name = "gpio1_db_clk", + .flag = 0, + .parent = {&pllsysp_div12_clk}, + .prediv = 100, + .div_reg_offset = REG_PMU_CLK_DIV8, + .div_reg_mask = 0x7fff0000, + .en_reg_offset = REG_PMU_CLK_DIV8, + .en_reg_mask = 0x80000000, + .rst_reg_offset = REG_PMU_SWRST_MAIN_CTRL, + .rst_reg_mask = 0x20, +}; + + +static struct fh_clk mipi_dphy_clk = { + .name = "mipi_dphy_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .parent = {&osc_clk}, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE, + .en_reg_mask = 0x100000, +}; +static struct fh_clk mipi_wrap_gate = { + .name = "mipi_wrap_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x20000000, +}; +static struct fh_clk rtc_hclk_gate = { + .name = "rtc_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x10000000, +}; +static struct fh_clk emac_hclk_gate = { + .name = "emac_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x2000000, +}; +static struct fh_clk usb_clk = { + .name = "usb_clk", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x1000000, +}; +static struct fh_clk aes_hclk_gate = { + .name = "aes_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x80, +}; +static struct fh_clk ephy_clk_gate = { + .name = "ephy_clk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x1, +}; +static struct fh_clk sdc0_clk8x_gate = { + .name = "sdc0_clk8x_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x4, +}; +static struct fh_clk sdc1_clk8x_gate = { + .name = "sdc1_clk8x_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x8, +}; +static struct fh_clk mipic_pclk_gate = { + .name = "mipic_pclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_GATE1, + .en_reg_mask = 0x10, +}; + +static struct fh_clk gpio0_pclk_gate = { + .name = "gpio0_pclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV8, + .en_reg_mask = 0x4000, +}; +static struct fh_clk gpio1_pclk_gate = { + .name = "gpio1_pclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV8, + .en_reg_mask = 0x40000000, +}; +static struct fh_clk isp_hclk_gate = { + .name = "isp_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x1000000, +}; +static struct fh_clk veu_hclk_gate = { + .name = "veu_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x2000000, +}; +static struct fh_clk bgm_hclk_gate = { + .name = "bgm_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x4000000, +}; +static struct fh_clk adapt_hclk_gate = { + .name = "adapt_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x8000000, +}; +static struct fh_clk jpg_hclk_gate = { + .name = "jpg_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x10000000, +}; +static struct fh_clk jpg_adapt_gate = { + .name = "jpg_adapt_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x20000000, +}; +static struct fh_clk vpu_hclk_gate = { + .name = "vpu_hclk_gate", + .flag = CLOCK_NORESET|CLOCK_NODIV, + .prediv = 1, + .en_reg_offset = REG_PMU_CLK_DIV7, + .en_reg_mask = 0x40000000, +}; + +static struct fh_clk sdc0_clk_sample = { + .name = "sdc0_clk_sample", + .parent = {&sdc0_clk}, + .flag = CLOCK_NOGATE | CLOCK_PHASE, + .prediv = 1, + .sel_reg_offset = REG_PMU_CLK_GATE1, + .sel_reg_mask = 0xf0000, +}; + +static struct fh_clk sdc0_clk_drv = { + .name = "sdc0_clk_drv", + .parent = {&sdc0_clk}, + .flag = CLOCK_NOGATE | CLOCK_PHASE, + .prediv = 1, + .sel_reg_offset = REG_PMU_CLK_GATE1, + .sel_reg_mask = 0xf00000, +}; + +static struct fh_clk sdc1_clk_sample = { + .name = "sdc1_clk_sample", + .parent = {&sdc0_clk}, + .flag = CLOCK_NOGATE | CLOCK_PHASE, + .prediv = 1, + .sel_reg_offset = REG_PMU_CLK_GATE1, + .sel_reg_mask = 0xf00, +}; + +static struct fh_clk sdc1_clk_drv = { + .name = "sdc1_clk_drv", + .parent = {&sdc0_clk}, + .flag = CLOCK_NOGATE | CLOCK_PHASE, + .prediv = 1, + .sel_reg_offset = REG_PMU_CLK_GATE1, + .sel_reg_mask = 0xf000, +}; + +struct fh_clk *fh_clks[] = { + &osc_clk, + &pll_ddr_rclk, + &pll_cpu_pclk, + &pll_cpu_rclk, + &pll_sys_pclk, + &pll_sys_rclk, + &arm_clk, + &arc_clk, + &ahb_clk, + &ddr_clk, + &isp_aclk, + &ispb_aclk, + &jpeg_clk, + &jpeg_adapt_clk, + &vpu_clk, + &veu_clk, + &veu_adapt_clk, + &bgm_clk, + &mipi_dphy_clk, + &pllsysp_div12_clk, + &cis_clk_out, + &pix_clk, + &pts_clk, + &spi0_clk, + &spi1_clk, + &spi2_clk, + &sdc0_clk, + &sdc1_clk, + &uart0_clk, + &uart1_clk, + &uart2_clk, + &i2c0_clk, + &i2c1_clk, + &i2c2_clk, + &pwm_clk, + &wdt_clk, + &tmr0_clk, + &ac_clk, + &i2s_clk, + &sadc_clk, + ð_clk, + &efuse_clk, + &gpio0_db_clk, + &gpio1_db_clk, + &mipi_wrap_gate, + &rtc_hclk_gate, + &emac_hclk_gate, + &usb_clk, + &aes_hclk_gate, + &ephy_clk_gate, + &sdc0_clk8x_gate, + &sdc1_clk8x_gate, + &gpio0_pclk_gate, + &gpio1_pclk_gate, + &mipic_pclk_gate, + &sdc0_clk_sample, + &sdc0_clk_drv, + &sdc1_clk_sample, + &sdc1_clk_drv, + &isp_hclk_gate, + &veu_hclk_gate, + &bgm_hclk_gate, + &adapt_hclk_gate, + &jpg_hclk_gate, + &jpg_adapt_gate, + &vpu_hclk_gate, + NULL, +}; +EXPORT_SYMBOL(fh_clks); diff --git a/arch/arm/mach-fh/fh8858v210/chip.h b/arch/arm/mach-fh/fh8858v210/chip.h new file mode 100644 index 00000000..100b92d8 --- /dev/null +++ b/arch/arm/mach-fh/fh8858v210/chip.h @@ -0,0 +1,421 @@ +#ifndef __ASM_ARCH_HL_H +#define __ASM_ARCH_HL_H + +#include + +#define SRAM_GRANULARITY 32 +#define SRAM_SIZE (SZ_128K+SZ_8K) + + +#define RAM_BASE (0x10000000) +#define DDR_BASE (0xA0000000) + + +#define PMU_REG_BASE (0xF0000000) +#define TIMER_REG_BASE (0xF0C00000) +#define GPIO0_REG_BASE (0xF0300000) +#define GPIO1_REG_BASE (0xF4000000) +#define UART0_REG_BASE (0xF0700000) +#define UART1_REG_BASE (0xF0800000) +#define SPI0_REG_BASE (0xF0500000) +#define SPI1_REG_BASE (0xF0600000) +#define SPI2_REG_BASE (0xF0640000) +#define INTC_REG_BASE (0xE0200000) +#define GMAC_REG_BASE (0xE0600000) +#define USBC_REG_BASE (0xE0700000) +#define DMAC_REG_BASE (0xE0300000) +#define I2C1_REG_BASE (0xF0B00000) +#define I2C0_REG_BASE (0xF0200000) +#define I2C2_REG_BASE (0xF0100000) +#define SDC0_REG_BASE (0xE2000000) +#define SDC1_REG_BASE (0xE2200000) +#define WDT_REG_BASE (0xF0D00000) +#define PWM_REG_BASE (0xF0400000) +#define I2S_REG_BASE (0xF0900000) +#define ACW_REG_BASE (0xF0A00000) +#define UART2_REG_BASE (0xF1300000) +#define SADC_REG_BASE (0xF1200000) +#define EFUSE_REG_BASE (0xF1600000) +#define AES_REG_BASE (0xE8200000) +#define RTC_REG_BASE (0xF1500000) +#define DDRC_REG_BASE (0xED000000) +#define CONSOLE_REG_BASE UART0_REG_BASE +#define FH_UART_NUMBER 3 + +#define FH_PMU_REG_SIZE 0x2110 +#define REG_PMU_CHIP_ID (0x0000) +#define REG_PMU_IP_VER (0x0004) +#define REG_PMU_FW_VER (0x0008) +#define REG_PMU_CLK_SEL (0x000c) +/*for HL REG_PMU_SYS_CTRL and CLK_SEL use one register */ +#define REG_PMU_SYS_CTRL (0x000c) +#define REG_PMU_PLL0 (0x0010) +#define REG_PMU_PLL1 (0x0014) +#define REG_PMU_PLL0_CTRL (0x0018) +#define REG_PMU_CLK_GATE (0x001c) +#define REG_PMU_CLK_GATE1 (0x0020) +#define REG_PMU_CLK_DIV0 (0x0024) +#define REG_PMU_CLK_DIV1 (0x0028) +#define REG_PMU_CLK_DIV2 (0x002c) +#define REG_PMU_CLK_DIV3 (0x0030) +#define REG_PMU_CLK_DIV4 (0x0034) +#define REG_PMU_CLK_DIV5 (0x0038) +#define REG_PMU_CLK_DIV6 (0x003c) +#define REG_PMU_SWRST_MAIN_CTRL (0x0040) +#define REG_PMU_SWRST_MAIN_CTRL2 (0x0044) +#define REG_PMU_SWRST_AHB_CTRL (0x0048) +#define REG_PMU_SWRST_APB_CTRL (0x004c) +#define REG_PMU_SPC_IO_STATUS (0x0054) +#define REG_PMU_SPC_FUN (0x0058) +#define REG_PMU_CLK_DIV7 (0x005c) +#define REG_PMU_CLK_DIV8 (0x0060) +#define REG_PMU_PLL2 (0x0064) +#define REG_PMU_PLL2_CTRL (0x0068) +#define REG_PMU_PLL1_CTRL (0x006c) +#define REG_PAD_PWR_SEL (0x0074) +#define REG_PMU_SWRSTN_NSR (0x0078) +#define REG_PMU_SWRSTN_NSR1 (0x007c) +#define REG_PMU_ETHPHY_REG0 (0x2108) + + +#define REG_PMU_PAD_BOOT_MODE_CFG (0x0080) +#define REG_PMU_PAD_BOOT_SEL1_CFG (0x0084) +#define REG_PMU_PAD_BOOT_SEL0_CFG (0x0088) +#define REG_PMU_PAD_UART0_TX_CFG (0x008c) +#define REG_PMU_PAD_UART0_RX_CFG (0x0090) +#define REG_PMU_PAD_I2C0_SCL_CFG (0x0094) +#define REG_PMU_PAD_I2C0_SDA_CFG (0x0098) +#define REG_PMU_PAD_SENSOR_CLK_CFG (0x009c) +#define REG_PMU_PAD_SENSOR_RSTN_CFG (0x00a0) +#define REG_PMU_PAD_UART1_TX_CFG (0x00a4) +#define REG_PMU_PAD_UART1_RX_CFG (0x00a8) +#define REG_PMU_PAD_I2C1_SCL_CFG (0x00ac) +#define REG_PMU_PAD_I2C1_SDA_CFG (0x00b0) +#define REG_PMU_PAD_UART2_TX_CFG (0x00b4) +#define REG_PMU_PAD_UART2_RX_CFG (0x00b8) +#define REG_PMU_PAD_USB_PWREN_CFG (0x00bc) +#define REG_PMU_PAD_PWM0_CFG (0x00c0) +#define REG_PMU_PAD_PWM1_CFG (0x00c4) +#define REG_PMU_PAD_PWM2_CFG (0x00c8) +#define REG_PMU_PAD_PWM3_CFG (0x00cc) +#define REG_PMU_PAD_MAC_RMII_CLK_CFG (0x00d0) +#define REG_PMU_PAD_MAC_REF_CLK_CFG (0x00d4) +#define REG_PMU_PAD_MAC_TXD0_CFG (0x00d8) +#define REG_PMU_PAD_MAC_TXD1_CFG (0x00dc) +#define REG_PMU_PAD_MAC_TXEN_CFG (0x00e0) +#define REG_PMU_PAD_MAC_RXD0_CFG (0x00e4) +#define REG_PMU_PAD_MAC_RXD1_CFG (0x00e8) +#define REG_PMU_PAD_MAC_RXDV_CFG (0x00ec) +#define REG_PMU_PAD_MAC_MDC_CFG (0x00f0) +#define REG_PMU_PAD_MAC_MDIO_CFG (0x00f4) +#define REG_PMU_PAD_SD1_CLK_CFG (0x00f8) +#define REG_PMU_PAD_SD1_CD_CFG (0x00fc) +#define REG_PMU_PAD_SD1_CMD_RSP_CFG (0x0100) +#define REG_PMU_PAD_SD1_DATA_0_CFG (0x0104) +#define REG_PMU_PAD_SD1_DATA_1_CFG (0x0108) +#define REG_PMU_PAD_SD1_DATA_2_CFG (0x010c) +#define REG_PMU_PAD_SD1_DATA_3_CFG (0x0110) +#define REG_PMU_PAD_GPIO_0_CFG (0x0114) +#define REG_PMU_PAD_GPIO_1_CFG (0x0118) +#define REG_PMU_PAD_GPIO_2_CFG (0x011c) +#define REG_PMU_PAD_GPIO_3_CFG (0x0120) +#define REG_PMU_PAD_GPIO_4_CFG (0x0124) +#define REG_PMU_PAD_SSI0_CLK_CFG (0x0128) +#define REG_PMU_PAD_SSI0_CSN_0_CFG (0x012c) +#define REG_PMU_PAD_SSI0_TXD_CFG (0x0130) +#define REG_PMU_PAD_SSI0_RXD_CFG (0x0134) +#define REG_PMU_PAD_SSI0_D2_CFG (0x0138) +#define REG_PMU_PAD_SSI0_D3_CFG (0x013c) +#define REG_PMU_PAD_SSI1_CLK_CFG (0x0140) +#define REG_PMU_PAD_SSI1_CSN_0_CFG (0x0144) +#define REG_PMU_PAD_SSI1_TXD_CFG (0x0148) +#define REG_PMU_PAD_SSI1_RXD_CFG (0x014c) +#define REG_PMU_PAD_SD0_CD_CFG (0x0150) +#define REG_PMU_PAD_SD0_CLK_CFG (0x0154) +#define REG_PMU_PAD_SD0_CMD_RSP_CFG (0x0158) +#define REG_PMU_PAD_SD0_DATA_0_CFG (0x015c) +#define REG_PMU_PAD_SD0_DATA_1_CFG (0x0160) +#define REG_PMU_PAD_SD0_DATA_2_CFG (0x0164) +#define REG_PMU_PAD_SD0_DATA_3_CFG (0x0168) +#define REG_PMU_PAD_SADC_XAIN0_CFG (0x016c) +#define REG_PMU_PAD_SADC_XAIN1_CFG (0x0170) +#define REG_PMU_PAD_SADC_XAIN2_CFG (0x0174) +#define REG_PMU_PAD_SADC_XAIN3_CFG (0x0178) +#define REG_PMU_PAD_GPIO_28_CFG (0x017c) +#define REG_PMU_PAD_GPIO_29_CFG (0x0180) + +#define REG_PMU_ARM_INT_0 (0x01e0) +#define REG_PMU_ARM_INT_1 (0x01e4) +#define REG_PMU_ARM_INT_2 (0x01e8) +#define REG_PMU_A625_INT_0 (0x01ec) +#define REG_PMU_A625_INT_1 (0x01f0) +#define REG_PMU_A625_INT_2 (0x01f4) +#define REG_PMU_DMA (0x01f8) +#define REG_PMU_WDT_CTRL (0x01fc) +#define REG_PMU_DBG_STAT0 (0x0200) +#define REG_PMU_DBG_STAT1 (0x0204) +#define REG_PMU_DBG_STAT2 (0x0208) +#define REG_PMU_DBG_STAT3 (0x020c) +#define REG_PMU_USB_SYS (0x0210) +#define REG_PMU_USB_CFG (0x0214) +#define REG_PMU_USB_TUNE (0x0218) +#define REG_PMU_USB_SYS1 (0x0228) +#define REG_PMU_PTSLO (0x022c) +#define REG_PMU_PTSHI (0x0230) +#define REG_PMU_USER0 (0x0234) +#define REG_PMU_BOOT_MODE (0x0330) +#define REG_PMU_DDR_SIZE (0x0334) +#define REG_PMU_CHIP_INFO (0x033C) +#define REG_PMU_EPHY_PARAM (0x0340) +#define REG_PMU_RTC_PARAM (0x0344) +#define REG_PMU_SD1_FUNC_SEL (0x03a0) +#define REG_PMU_PRDCID_CTRL0 (0x0500) +#define REG_PMU_A625BOOT0 (0x2000) +#define REG_PMU_A625BOOT1 (0x2004) +#define REG_PMU_A625BOOT2 (0x2008) +#define REG_PMU_A625BOOT3 (0x200c) +#define REG_PMU_A625_START_CTRL (0x2010) +#define REG_PMU_ARC_INTC_MASK (0x2014) + +#define FH_GMAC_AHB_RESET (1<<17) +#define FH_GMAC_SPEED_100M (1<<24) +#define PMU_RMII_SPEED_MODE (REG_PMU_CLK_SEL) +#define PMU_RXDV_GPIO_SWITCH (REG_PMU_PAD_MAC_RXDV_CFG) +#define PMU_RXDV_GPIO_MASK (0x0f000000) +#define PMU_RXDV_GPIO_VAL (0x01000000) + +#define PMU_DWI2S_CLK_SEL_REG (REG_PMU_CLK_SEL) +#define PMU_DWI2S_CLK_SEL_SHIFT (1) +#define PMU_DWI2S_CLK_DIV_REG (REG_PMU_CLK_DIV6) +#define PMU_DWI2S_CLK_DIV_SHIFT (0) + +/*ATTENTION: written by ARC */ +#define PMU_ARM_INT_MASK (0x01ec) +#define PMU_ARM_INT_RAWSTAT (0x01f0) +#define PMU_ARM_INT_STAT (0x01f4) + +#define PMU_A625_INT_MASK (0x01e0) +#define PMU_A625_INT_RAWSTAT (0x01e4) +#define PMU_A625_INT_STAT (0x01e8) + +#define PMU_IRQ 0 +#define DDRC_IRQ 1 +#define WDT_IRQ 2 +#define TMR0_IRQ 3 +#define VEU_IRQ 4 +#define PERF_IRQ 5 +#define VPU_IRQ 9 +#define I2C0_IRQ 11 +#define I2C1_IRQ 12 +#define JPEG_IRQ 13 +#define BGM_IRQ 14 +#define VEU_LOOP_IRQ 15 +#define AES_IRQ 16 +#define MIPIC_IRQ 17 +#define MIPI_WRAP_IRQ 18 +#define ACW_IRQ 19 +#define SADC_IRQ 20 +#define SPI1_IRQ 21 +#define JPEG_LOOP_IRQ 22 +#define DMAC0_IRQ 23 +#define DMAC1_IRQ 24 +#define I2S0_IRQ 25 +#define GPIO0_IRQ 26 +#define SPI0_IRQ 28 +#define ARC_SW_IRQ 29 +#define UART0_IRQ 30 +#define UART1_IRQ 31 +#define ARM_SW_IRQ 32 +#define RTC_IRQ 33 +#define PWM_IRQ 36 +#define SPI2_IRQ 38 +#define USBC_IRQ 39 +#define GPIO1_IRQ 40 +#define UART2_IRQ 41 +#define SDC0_IRQ 42 +#define SDC1_IRQ 43 +#define GMAC_IRQ 44 +#define EPHY_IRQ 45 +#define I2C2_IRQ 46 +#define RTC_ALM_IRQ 47 +#define RTC_CORE_IRQ 48 +/* because chips with some same function in different */ +/* pmu register, use wrap marco to make code to be same */ +#define PMU_RMII_SPEED_MODE (REG_PMU_CLK_SEL) + +#define MEM_START_PHY_ADDR DDR_BASE +#define MEM_SIZE 0x8000000 + + +#define NR_INTERNAL_IRQS (64) +#define NR_EXTERNAL_IRQS (64) +/*#define NR_IRQS (NR_INTERNAL_IRQS + NR_EXTERNAL_IRQS)*/ + +/* SWRST_MAIN_CTRL */ +#define CPU_RSTN_BIT (0) +#define UTMI_RSTN_BIT (1) +#define DDRPHY_RSTN_BIT (2) +#define DDRC_RSTN_BIT (3) +#define GPIO0_DB_RSTN_BIT (4) +#define GPIO1_DB_RSTN_BIT (5) +#define PIXEL_RSTN_BIT (6) +#define PWM_RSTN_BIT (7) +#define SPI0_RSTN_BIT (8) +#define SPI1_RSTN_BIT (9) +#define I2C0_RSTN_BIT (10) +#define I2C1_RSTN_BIT (11) +#define ACODEC_RSTN_BIT (12) +#define I2S_RSTN_BIT (13) +#define UART0_RSTN_BIT (14) +#define UART1_RSTN_BIT (15) +#define SADC_RSTN_BIT (16) +#define ADAPT_RSTN_BIT (17) +#define TMR_RSTN_BIT (18) +#define UART2_RSTN_BIT (19) +#define SPI2_RSTN_BIT (20) +#define JPG_ADAPT_RSTN_BIT (21) +#define ARC_RSTN_BIT (22) +#define EFUSE_RSTN_BIT (23) +#define JPG_RSTN_BIT (24) +#define VEU_RSTN_BIT (25) +#define VPU_RSTN_BIT (26) +#define ISP_RSTN_BIT (27) +#define BGM_RSTN_BIT (28) +#define I2C2_RSTN_BIT (29) +#define EPHY_RSTN_BIT (30) +#define SYS_RSTN_BIT (31) + +/* SWRST_AHB_CTRL */ +#define EMC_HRSTN_BIT (0) +#define SDC1_HRSTN_BIT (1) +#define SDC0_HRSTN_BIT (2) +#define AES_HRSTN_BIT (3) +#define DMAC0_HRSTN_BIT (4) +#define INTC_HRSTN_BIT (5) +#define JPEG_ADAPT_HRSTN_BIT (7) +#define JPEG_HRSTN_BIT (8) +#define VCU_HRSTN_BIT (9) +#define VPU_HRSTN_BIT (10) +#define ISP_HRSTN_BIT (11) +#define USB_HRSTN_BIT (12) +#define HRSTN_BIT (13) +#define EMAC_HRSTN_BIT (17) +#define DDRC_HRSTN_BIT (19) +#define DMAC1_HRSTN_BIT (20) +#define BGM_HRSTN_BIT (22) +#define ADAPT_HRSTN_BIT (23) + + +/* SWRST_APB_CTRL */ +#define ACODEC_PRSTN_BIT (0) +#define I2S_PRSTN_BIT (1) +#define UART1_PRSTN_BIT (2) +#define UART0_PRSTN_BIT (3) +#define SPI0_PRSTN_BIT (4) +#define SPI1_PRSTN_BIT (5) +#define GPIO0_PRSTN_BIT (6) +#define UART2_PRSTN_BIT (7) +#define I2C2_PRSTN_BIT (8) +#define I2C0_PRSTN_BIT (9) +#define I2C1_PRSTN_BIT (10) +#define TMR_PRSTN_BIT (11) +#define PWM_PRSTN_BIT (12) +#define MIPIW_PRSTN_BIT (13) +#define MIPIC_PRSTN_BIT (14) +#define RTC_PRSTN_BIT (15) +#define SADC_PRSTN_BIT (16) +#define EFUSE_PRSTN_BIT (17) +#define SPI2_PRSTN_BIT (18) +#define WDT_PRSTN_BIT (19) +#define GPIO1_PRSTN_BIT (20) + +/* timer clk fpga 1M,soc 50M*/ +#ifdef CONFIG_FPGA +#define TIMER_CLK (1000000) +#else +#define TIMER_CLK (50000000) +#endif + +#define UART1_TX_HW_HANDSHAKE (9) +#define UART1_RX_HW_HANDSHAKE (8) +#define UART2_TX_HW_HANDSHAKE (13) +#define UART2_RX_HW_HANDSHAKE (12) +#define UART1_DMA_TX_CHAN (4) +#define UART1_DMA_RX_CHAN (5) +#define UART2_DMA_TX_CHAN (4) +#define UART2_DMA_RX_CHAN (5) + +/*sdio*/ +#define SIMPLE_0 (0) +#define SIMPLE_22 (1) +#define SIMPLE_45 (2) +#define SIMPLE_67 (3) +#define SIMPLE_90 (4) +#define SIMPLE_112 (5) +#define SIMPLE_135 (6) +#define SIMPLE_157 (7) +#define SIMPLE_180 (8) +#define SIMPLE_202 (9) +#define SIMPLE_225 (10) +#define SIMPLE_247 (11) +#define SIMPLE_270 (12) +#define SIMPLE_292 (13) +#define SIMPLE_315 (14) +#define SIMPLE_337 (15) + + + +#define SDIO0_RST_BIT (~UL(1<<2)) +#define SDIO0_CLK_RATE (50000000) +#define SDIO0_CLK_DRV_SHIFT (20) +#define SDIO0_CLK_DRV_DEGREE (SIMPLE_180) +#define SDIO0_CLK_SAM_SHIFT (16) +#define SDIO0_CLK_SAM_DEGREE (SIMPLE_0) + + +#define SDIO1_RST_BIT (~UL(1<<1)) +#define SDIO1_CLK_RATE (50000000) +#define SDIO1_CLK_DRV_SHIFT (12) +#define SDIO1_CLK_DRV_DEGREE (SIMPLE_180) +#define SDIO1_CLK_SAM_SHIFT (8) +#define SDIO1_CLK_SAM_DEGREE (SIMPLE_0) + +#define SDC0_HRSTN (0x1<<2) +#define SDC1_HRSTN (0x1<<1) +#define SDC2_HRSTN (0) + + +/*usb*/ +#define IRQ_UHOST USBC_IRQ +#define FH_PA_OTG USBC_REG_BASE +#define IRQ_OTG IRQ_UHOST +#define FH_SZ_USBHOST SZ_1M +#define FH_SZ_OTG SZ_1M + +#define USB_UTMI_RST_BIT (0x1<<1) +#define USB_PHY_RST_BIT (0x11) +#define USB_SLEEP_MODE_BIT (0x1<<24) +#define USB_IDDQ_PWR_BIT (0x1<<10) + + +/* Specific Uart Number */ +#define FH_UART_NUMBER 3 +#define CLK_SCAN_BIT_POS (28) +#define INSIDE_PHY_ENABLE_BIT_POS (24) +#define MAC_REF_CLK_DIV_MASK (0x0f) +#define MAC_REF_CLK_DIV_BIT_POS (24) +#define MAC_PAD_RMII_CLK_MASK (0x0f) +#define MAC_PAD_RMII_CLK_BIT_POS (24) +#define MAC_PAD_MAC_REF_CLK_BIT_POS (28) +#define ETH_REF_CLK_OUT_GATE_BIT_POS (25) +#define ETH_RMII_CLK_OUT_GATE_BIT_POS (28) +#define IN_OR_OUT_PHY_SEL_BIT_POS (26) +#define INSIDE_CLK_GATE_BIT_POS (0) +#define INSIDE_PHY_SHUTDOWN_BIT_POS (31) +#define INSIDE_PHY_RST_BIT_POS (30) +#define INSIDE_PHY_TRAINING_BIT_POS (27) +#define INSIDE_PHY_TRAINING_MASK (0x0f) + +#define TRAINING_EFUSE_ACTIVE_BIT_POS 4 + +#endif /* __ASM_ARCH_HL_H */ diff --git a/arch/arm/mach-fh/fh8858v210/iopad.h b/arch/arm/mach-fh/fh8858v210/iopad.h new file mode 100644 index 00000000..be10c032 --- /dev/null +++ b/arch/arm/mach-fh/fh8858v210/iopad.h @@ -0,0 +1,729 @@ +#include +#include +#include + +/* PINCTRL_FUNC */ +PINCTRL_FUNC(GPIO30, 0, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(GPIO31, 1, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(ETH_LINK_ACT, 1, FUNC1, PUPD_UP, 0); +PINCTRL_FUNC(GPIO32, 2, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(ETH_LINK_STA, 2, FUNC1, PUPD_UP, 0); +PINCTRL_FUNC(ETH_LINK_SPD, 2, FUNC2, PUPD_UP, 0); +PINCTRL_FUNC(UART0_TX, 3, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO33, 3, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART0_RX, 4, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO34, 4, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C0_SCL, 5, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(GPIO35, 5, FUNC1, PUPD_UP, 0); +PINCTRL_FUNC(I2C0_SDA, 6, FUNC0, PUPD_UP, 0); +PINCTRL_FUNC(GPIO36, 6, FUNC1, PUPD_UP, 0); +PINCTRL_FUNC(SENSOR_CLK, 7, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO12, 7, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO13, 8, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(UART1_TX, 9, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO39, 9, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CLK, 9, FUNC3, PUPD_NONE, 3); +PINCTRL_FUNC(TEST_O_INT_RMII_CLK, 9, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(UART1_RX, 10, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO40, 10, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 10, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_INT_RMII_TXD_0, 10, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(I2C1_SCL, 11, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO37, 11, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM2, 11, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CMD_RSP, 11, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CLK, 11, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_INT_RMII_TXD_1, 11, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(I2C1_SDA, 12, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO38, 12, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM3, 12, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_0, 12, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CSN_0, 12, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_INT_RMII_TXEN, 12, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_TX, 13, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO41, 13, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM4, 13, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_1, 13, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_TXD, 13, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_O_INT_RMII_RXD_0, 13, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_RX, 14, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO42, 14, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM5, 14, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_2, 14, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_RXD, 14, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_O_INT_RMII_RXD_1, 14, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(USB_PWREN, 15, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO47, 15, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_3, 15, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_O_INT_RMII_CRSDV, 15, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM0, 16, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO43, 16, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C2_SCL, 16, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_TX, 16, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_RMII_TXD_0, 16, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM1, 17, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO44, 17, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C2_SDA, 17, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_RX, 17, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_RMII_TXD_1, 17, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM2, 18, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO45, 18, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM3, 19, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO46, 19, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_RMII_CLK, 20, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO48, 20, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CLK, 20, FUNC2, PUPD_NONE, 3); +PINCTRL_FUNC(PWM2, 20, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_REF_CLK, 21, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(MAC_TXD_0, 22, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO49, 22, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 22, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM3, 22, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_TXD_1, 23, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO50, 23, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CMD_RSP, 23, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM4, 23, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_TXEN, 24, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO51, 24, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_0, 24, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM5, 24, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_RXD_0, 25, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO52, 25, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_1, 25, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM6, 25, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_RXD_1, 26, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO53, 26, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_2, 26, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM7, 26, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_RXDV, 27, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO54, 27, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_3, 27, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(PWM8, 27, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_MDC, 28, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO55, 28, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(PWM9, 28, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_MDIO, 29, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO56, 29, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CLK, 30, FUNC0, PUPD_NONE, 3); +PINCTRL_FUNC(GPIO57, 30, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C1_SCL, 30, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 31, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO58, 31, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(I2C1_SDA, 31, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CMD_RSP, 32, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO59, 32, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART1_TX, 32, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_0, 33, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO60, 33, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART1_RX, 33, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_1, 34, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO61, 34, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_TX, 34, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_2, 35, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO62, 35, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(UART2_RX, 35, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_DATA_3, 36, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO63, 36, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TRSTN, 37, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO0, 37, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_I2S_DO, 37, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(DW_I2S_DO, 37, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SSI1_CLK, 37, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI2_CLK, 37, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_ADDAT, 37, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM6, 37, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_SMI_MDC, 37, FUNC8, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TDO, 38, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO1, 38, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_I2S_DI, 38, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(DW_I2S_DI, 38, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SSI1_CSN_0, 38, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI2_CSN_0, 38, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_DADAT, 38, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM7, 38, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_SMI_MDIO_I, 38, FUNC8, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TDI, 39, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO2, 39, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_I2S_CLK, 39, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(DW_I2S_CLK, 39, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SSI1_TXD, 39, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI2_TXD, 39, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_ADBCLK, 39, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM8, 39, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_SMI_MDIO_O, 39, FUNC8, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TCK, 40, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO3, 40, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_I2S_WS, 40, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(DW_I2S_WS, 40, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SSI1_RXD, 40, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI2_RXD, 40, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_ADLRC, 40, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(PWM9, 40, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_I_INT_SMI_MDIO_I, 40, FUNC8, PUPD_NONE, 0); +PINCTRL_FUNC(ARM_JTAG_TMS, 41, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO4, 41, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(AC_MCLK, 41, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(USB_PWREN, 41, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 41, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_I_INT_SMI_MDC, 41, FUNC5, PUPD_NONE, 0); +PINCTRL_FUNC(SSI0_CLK, 42, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO5, 42, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_CLK, 42, FUNC4, PUPD_NONE, 3); +PINCTRL_FUNC(SSI0_CSN_0, 43, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO6, 43, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_CMD_RSP, 43, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI0_TXD, 44, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO7, 44, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_DATA_0, 44, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI0_RXD, 45, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO8, 45, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_DATA_1, 45, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI0_D2, 46, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO9, 46, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(UART1_TX, 46, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(I2C1_SCL, 46, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_DATA_2, 46, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI0_D3, 47, FUNC0, PUPD_NONE, 4); +PINCTRL_FUNC(GPIO10, 47, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(UART1_RX, 47, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(I2C1_SDA, 47, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(SD1_DATA_3, 47, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CLK, 48, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO11, 48, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SSI2_CLK, 48, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CSN_0, 49, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO14, 49, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SSI2_CSN_0, 49, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_TXD, 50, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO15, 50, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SSI2_TXD, 50, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_RXD, 51, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO16, 51, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SSI2_RXD, 51, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_CD, 52, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO17, 52, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(ARC_JTAG_TRSTN, 52, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(PAE_JTAG_TRSTN, 52, FUNC4, PUPD_NONE, 0); +PINCTRL_FUNC(SD0_CLK, 53, FUNC0, PUPD_NONE, 3); +PINCTRL_FUNC(GPIO18, 53, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CLK, 53, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(ARC_JTAG_TDO, 53, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(PAE_JTAG_TDO, 53, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_CMD_RSP, 54, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO19, 54, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_TXD, 54, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(ARC_JTAG_TDI, 54, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(PAE_JTAG_TDI, 54, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_DATA_0, 55, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO20, 55, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_RXD, 55, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(ARC_JTAG_TCK, 55, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(PAE_JTAG_TCK, 55, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_DATA_1, 56, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO21, 56, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CSN_0, 56, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(ARC_JTAG_TMS, 56, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(PAE_JTAG_TMS, 56, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_DATA_2, 57, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO22, 57, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(UART2_TX, 57, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(I2C2_SCL, 57, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_DABCLK, 57, FUNC6, PUPD_NONE, 2); +PINCTRL_FUNC(SD0_DATA_3, 58, FUNC0, PUPD_NONE, 2); +PINCTRL_FUNC(GPIO23, 58, FUNC1, PUPD_NONE, 2); +PINCTRL_FUNC(SSI1_CSN_0, 58, FUNC2, PUPD_NONE, 2); +PINCTRL_FUNC(UART2_RX, 58, FUNC3, PUPD_NONE, 2); +PINCTRL_FUNC(I2C2_SDA, 58, FUNC4, PUPD_NONE, 2); +PINCTRL_FUNC(ACIP_DALRC, 58, FUNC6, PUPD_NONE, 2); +PINCTRL_FUNC(SADC_XAIN0, 59, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO26, 59, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SADC_XAIN1, 60, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO27, 60, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SADC_XAIN2, 61, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO24, 61, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(SADC_XAIN3, 62, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO25, 62, FUNC1, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO28, 63, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(ETH_LINK_ACT, 63, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(PWM10, 63, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(USB_DBG_CLK, 63, FUNC4, PUPD_NONE, 0); +PINCTRL_FUNC(SD1_CD, 63, FUNC5, PUPD_NONE, 2); +PINCTRL_FUNC(TEST_O_INT_RMII_TXEN, 63, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_MDC, 63, FUNC7, PUPD_NONE, 0); +PINCTRL_FUNC(GPIO29, 64, FUNC0, PUPD_NONE, 0); +PINCTRL_FUNC(ETH_LINK_STA, 64, FUNC2, PUPD_NONE, 0); +PINCTRL_FUNC(PWM11, 64, FUNC3, PUPD_NONE, 0); +PINCTRL_FUNC(RTC_CLK, 64, FUNC4, PUPD_NONE, 0); +PINCTRL_FUNC(ETH_LINK_SPD, 64, FUNC5, PUPD_NONE, 0); +PINCTRL_FUNC(TEST_O_INT_SMI_MDIO_OE, 64, FUNC6, PUPD_NONE, 0); +PINCTRL_FUNC(MAC_MDIO, 64, FUNC7, PUPD_NONE, 0); + + +/* PINCTRL_MUX */ + +PINCTRL_MUX(AC_I2S_CLK, 0, &PAD39_AC_I2S_CLK); +PINCTRL_MUX(AC_I2S_DI, 0, &PAD38_AC_I2S_DI); +PINCTRL_MUX(AC_I2S_DO, 0, &PAD37_AC_I2S_DO); +PINCTRL_MUX(AC_I2S_WS, 0, &PAD40_AC_I2S_WS); +PINCTRL_MUX(AC_MCLK, 0, &PAD41_AC_MCLK); + +PINCTRL_MUX(ARC_JTAG_TCK, 0, &PAD55_ARC_JTAG_TCK); +PINCTRL_MUX(ARC_JTAG_TDI, 0, &PAD54_ARC_JTAG_TDI); +PINCTRL_MUX(ARC_JTAG_TDO, 0, &PAD53_ARC_JTAG_TDO); +PINCTRL_MUX(ARC_JTAG_TMS, 0, &PAD56_ARC_JTAG_TMS); +PINCTRL_MUX(ARC_JTAG_TRSTN, 0, &PAD52_ARC_JTAG_TRSTN); + +PINCTRL_MUX(ARM_JTAG_TCK, 0, &PAD40_ARM_JTAG_TCK); +PINCTRL_MUX(ARM_JTAG_TDI, 0, &PAD39_ARM_JTAG_TDI); +PINCTRL_MUX(ARM_JTAG_TDO, 0, &PAD38_ARM_JTAG_TDO); +PINCTRL_MUX(ARM_JTAG_TMS, 0, &PAD41_ARM_JTAG_TMS); +PINCTRL_MUX(ARM_JTAG_TRSTN, 0, &PAD37_ARM_JTAG_TRSTN); + +PINCTRL_MUX(DW_I2S_CLK, 0, &PAD39_DW_I2S_CLK); +PINCTRL_MUX(DW_I2S_DI, 0, &PAD38_DW_I2S_DI); +PINCTRL_MUX(DW_I2S_DO, 0, &PAD37_DW_I2S_DO); +PINCTRL_MUX(DW_I2S_WS, 0, &PAD40_DW_I2S_WS); + +PINCTRL_MUX(ETH_LINK_ACT, 1, &PAD1_ETH_LINK_ACT, + &PAD63_ETH_LINK_ACT); +PINCTRL_MUX(ETH_LINK_SPD, 1, &PAD2_ETH_LINK_SPD, + &PAD64_ETH_LINK_SPD); +PINCTRL_MUX(ETH_LINK_STA, 1, &PAD2_ETH_LINK_STA, + &PAD64_ETH_LINK_STA); + +PINCTRL_MUX(I2C0_SCL, 0, &PAD5_I2C0_SCL); +PINCTRL_MUX(I2C0_SDA, 0, &PAD6_I2C0_SDA); + +PINCTRL_MUX(I2C1_SCL, 2, &PAD11_I2C1_SCL, &PAD30_I2C1_SCL, &PAD46_I2C1_SCL); +PINCTRL_MUX(I2C1_SDA, 2, &PAD12_I2C1_SDA, &PAD31_I2C1_SDA, &PAD47_I2C1_SDA); + +PINCTRL_MUX(I2C2_SCL, 1, &PAD16_I2C2_SCL, &PAD57_I2C2_SCL); +PINCTRL_MUX(I2C2_SDA, 1, &PAD17_I2C2_SDA, &PAD58_I2C2_SDA); + +PINCTRL_MUX(MAC_MDC, 0, &PAD28_MAC_MDC, &PAD63_MAC_MDC); +PINCTRL_MUX(MAC_MDIO, 0, &PAD29_MAC_MDIO, &PAD64_MAC_MDIO); +PINCTRL_MUX(MAC_REF_CLK, 0, &PAD21_MAC_REF_CLK); +PINCTRL_MUX(MAC_RMII_CLK, 0, &PAD20_MAC_RMII_CLK); +PINCTRL_MUX(MAC_RXDV, 0, &PAD27_MAC_RXDV); +PINCTRL_MUX(MAC_RXD_0, 0, &PAD25_MAC_RXD_0); +PINCTRL_MUX(MAC_RXD_1, 0, &PAD26_MAC_RXD_1); +PINCTRL_MUX(MAC_TXD_0, 0, &PAD22_MAC_TXD_0); +PINCTRL_MUX(MAC_TXD_1, 0, &PAD23_MAC_TXD_1); +PINCTRL_MUX(MAC_TXEN, 0, &PAD24_MAC_TXEN); + +PINCTRL_MUX(PAE_JTAG_TCK, 0, &PAD55_PAE_JTAG_TCK); +PINCTRL_MUX(PAE_JTAG_TDI, 0, &PAD54_PAE_JTAG_TDI); +PINCTRL_MUX(PAE_JTAG_TDO, 0, &PAD53_PAE_JTAG_TDO); +PINCTRL_MUX(PAE_JTAG_TMS, 0, &PAD56_PAE_JTAG_TMS); +PINCTRL_MUX(PAE_JTAG_TRSTN, 0, &PAD52_PAE_JTAG_TRSTN); + +PINCTRL_MUX(PWM0, 0, &PAD16_PWM0); +PINCTRL_MUX(PWM1, 0, &PAD17_PWM1); +PINCTRL_MUX(PWM10, 0, &PAD63_PWM10); +PINCTRL_MUX(PWM11, 0, &PAD64_PWM11); +PINCTRL_MUX(PWM2, 0, &PAD11_PWM2, &PAD18_PWM2, &PAD20_PWM2); +PINCTRL_MUX(PWM3, 0, &PAD12_PWM3, &PAD19_PWM3, &PAD22_PWM3); +PINCTRL_MUX(PWM4, 0, &PAD13_PWM4, &PAD23_PWM4); +PINCTRL_MUX(PWM5, 0, &PAD14_PWM5, &PAD24_PWM5); +PINCTRL_MUX(PWM6, 1, &PAD25_PWM6, &PAD37_PWM6); +PINCTRL_MUX(PWM7, 1, &PAD26_PWM7, &PAD38_PWM7); +PINCTRL_MUX(PWM8, 1, &PAD27_PWM8, &PAD39_PWM8); +PINCTRL_MUX(PWM9, 1, &PAD28_PWM9, &PAD40_PWM9); + +PINCTRL_MUX(RTC_CLK, 0, &PAD64_RTC_CLK); + +PINCTRL_MUX(SADC_XAIN0, 0, &PAD59_SADC_XAIN0); +PINCTRL_MUX(SADC_XAIN1, 0, &PAD60_SADC_XAIN1); +PINCTRL_MUX(SADC_XAIN2, 0, &PAD61_SADC_XAIN2); +PINCTRL_MUX(SADC_XAIN3, 0, &PAD62_SADC_XAIN3); + +PINCTRL_MUX(SD0_CD, 0, &PAD52_SD0_CD); +PINCTRL_MUX(SD0_CLK, 0, &PAD53_SD0_CLK); +PINCTRL_MUX(SD0_CMD_RSP, 0, &PAD54_SD0_CMD_RSP); +PINCTRL_MUX(SD0_DATA_0, 0, &PAD55_SD0_DATA_0); +PINCTRL_MUX(SD0_DATA_1, 0, &PAD56_SD0_DATA_1); +PINCTRL_MUX(SD0_DATA_2, 0, &PAD57_SD0_DATA_2); +PINCTRL_MUX(SD0_DATA_3, 0, &PAD58_SD0_DATA_3); + +PINCTRL_MUX(SD1_CD, 2, &PAD10_SD1_CD, &PAD22_SD1_CD, &PAD31_SD1_CD, + &PAD41_SD1_CD, &PAD63_SD1_CD); +PINCTRL_MUX(SD1_CLK, 2, &PAD9_SD1_CLK, &PAD20_SD1_CLK, &PAD30_SD1_CLK, + &PAD42_SD1_CLK); +PINCTRL_MUX(SD1_CMD_RSP, 2, &PAD11_SD1_CMD_RSP, &PAD23_SD1_CMD_RSP, + &PAD32_SD1_CMD_RSP, &PAD43_SD1_CMD_RSP); +PINCTRL_MUX(SD1_DATA_0, 2, &PAD12_SD1_DATA_0, &PAD24_SD1_DATA_0, + &PAD33_SD1_DATA_0, &PAD44_SD1_DATA_0); +PINCTRL_MUX(SD1_DATA_1, 2, &PAD13_SD1_DATA_1, &PAD25_SD1_DATA_1, + &PAD34_SD1_DATA_1, &PAD45_SD1_DATA_1); +PINCTRL_MUX(SD1_DATA_2, 2, &PAD14_SD1_DATA_2, &PAD26_SD1_DATA_2, + &PAD35_SD1_DATA_2, &PAD46_SD1_DATA_2); +PINCTRL_MUX(SD1_DATA_3, 2, &PAD15_SD1_DATA_3, &PAD27_SD1_DATA_3, + &PAD36_SD1_DATA_3, &PAD47_SD1_DATA_3); + +PINCTRL_MUX(SENSOR_CLK, 0, &PAD7_SENSOR_CLK); + +PINCTRL_MUX(SSI0_CLK, 0, &PAD42_SSI0_CLK); +PINCTRL_MUX(SSI0_D2, 0, &PAD46_SSI0_D2); +PINCTRL_MUX(SSI0_D3, 0, &PAD47_SSI0_D3); +PINCTRL_MUX(SSI0_RXD, 0, &PAD45_SSI0_RXD); +PINCTRL_MUX(SSI0_TXD, 0, &PAD44_SSI0_TXD); + +PINCTRL_MUX(SSI1_CLK, 2, &PAD11_SSI1_CLK, &PAD37_SSI1_CLK, &PAD48_SSI1_CLK, + &PAD53_SSI1_CLK); +PINCTRL_MUX(SSI1_RXD, 2, &PAD14_SSI1_RXD, &PAD40_SSI1_RXD, &PAD51_SSI1_RXD, + &PAD55_SSI1_RXD); +PINCTRL_MUX(SSI1_TXD, 2, &PAD13_SSI1_TXD, &PAD39_SSI1_TXD, &PAD50_SSI1_TXD, + &PAD54_SSI1_TXD); + +PINCTRL_MUX(SSI2_CLK, 1, &PAD37_SSI2_CLK, &PAD48_SSI2_CLK); +PINCTRL_MUX(SSI2_CSN_0, 1, &PAD38_SSI2_CSN_0, &PAD49_SSI2_CSN_0); +PINCTRL_MUX(SSI2_RXD, 1, &PAD40_SSI2_RXD, &PAD51_SSI2_RXD); +PINCTRL_MUX(SSI2_TXD, 1, &PAD39_SSI2_TXD, &PAD50_SSI2_TXD); + +PINCTRL_MUX(UART0_RX, 0, &PAD4_UART0_RX); +PINCTRL_MUX(UART0_TX, 0, &PAD3_UART0_TX); + +PINCTRL_MUX(UART1_RX, 0, &PAD10_UART1_RX, &PAD33_UART1_RX, &PAD47_UART1_RX); +PINCTRL_MUX(UART1_TX, 0, &PAD9_UART1_TX, &PAD32_UART1_TX, &PAD46_UART1_TX); + +PINCTRL_MUX(UART2_RX, 0, &PAD14_UART2_RX, &PAD17_UART2_RX, &PAD35_UART2_RX, + &PAD58_UART2_RX); +PINCTRL_MUX(UART2_TX, 0, &PAD13_UART2_TX, &PAD16_UART2_TX, &PAD34_UART2_TX, + &PAD57_UART2_TX); + +PINCTRL_MUX(USB_PWREN, 0, &PAD15_USB_PWREN, &PAD41_USB_PWREN); + +PINCTRL_MUX(GPIO0, 0, &PAD37_GPIO0); +PINCTRL_MUX(GPIO1, 0, &PAD38_GPIO1); +PINCTRL_MUX(GPIO2, 0, &PAD39_GPIO2); +PINCTRL_MUX(GPIO3, 0, &PAD40_GPIO3); +PINCTRL_MUX(GPIO4, 0, &PAD41_GPIO4); +PINCTRL_MUX(GPIO5, 0, &PAD42_GPIO5); +PINCTRL_MUX(GPIO6, 0, &PAD43_GPIO6); +PINCTRL_MUX(GPIO7, 0, &PAD44_GPIO7); +PINCTRL_MUX(GPIO8, 0, &PAD45_GPIO8); +PINCTRL_MUX(GPIO9, 0, &PAD46_GPIO9); +PINCTRL_MUX(GPIO10, 0, &PAD47_GPIO10); +PINCTRL_MUX(GPIO11, 0, &PAD48_GPIO11); +PINCTRL_MUX(GPIO12, 0, &PAD7_GPIO12); +PINCTRL_MUX(GPIO13, 0, &PAD8_GPIO13); +PINCTRL_MUX(GPIO14, 0, &PAD49_GPIO14); +PINCTRL_MUX(GPIO15, 0, &PAD50_GPIO15); +PINCTRL_MUX(GPIO16, 0, &PAD51_GPIO16); +PINCTRL_MUX(GPIO17, 0, &PAD52_GPIO17); +PINCTRL_MUX(GPIO18, 0, &PAD53_GPIO18); +PINCTRL_MUX(GPIO19, 0, &PAD54_GPIO19); +PINCTRL_MUX(GPIO20, 0, &PAD55_GPIO20); +PINCTRL_MUX(GPIO21, 0, &PAD56_GPIO21); +PINCTRL_MUX(GPIO22, 0, &PAD57_GPIO22); +PINCTRL_MUX(GPIO23, 0, &PAD58_GPIO23); +PINCTRL_MUX(GPIO24, 0, &PAD61_GPIO24); +PINCTRL_MUX(GPIO25, 0, &PAD62_GPIO25); +PINCTRL_MUX(GPIO26, 0, &PAD59_GPIO26); +PINCTRL_MUX(GPIO27, 0, &PAD60_GPIO27); +PINCTRL_MUX(GPIO28, 0, &PAD63_GPIO28); +PINCTRL_MUX(GPIO29, 0, &PAD64_GPIO29); +PINCTRL_MUX(GPIO30, 0, &PAD0_GPIO30); +PINCTRL_MUX(GPIO31, 0, &PAD1_GPIO31); +PINCTRL_MUX(GPIO32, 0, &PAD2_GPIO32); +PINCTRL_MUX(GPIO33, 0, &PAD3_GPIO33); +PINCTRL_MUX(GPIO34, 0, &PAD4_GPIO34); +PINCTRL_MUX(GPIO35, 0, &PAD5_GPIO35); +PINCTRL_MUX(GPIO36, 0, &PAD6_GPIO36); +PINCTRL_MUX(GPIO37, 0, &PAD11_GPIO37); +PINCTRL_MUX(GPIO38, 0, &PAD12_GPIO38); +PINCTRL_MUX(GPIO39, 0, &PAD9_GPIO39); +PINCTRL_MUX(GPIO40, 0, &PAD10_GPIO40); +PINCTRL_MUX(GPIO41, 0, &PAD13_GPIO41); +PINCTRL_MUX(GPIO42, 0, &PAD14_GPIO42); +PINCTRL_MUX(GPIO43, 0, &PAD16_GPIO43); +PINCTRL_MUX(GPIO44, 0, &PAD17_GPIO44); +PINCTRL_MUX(GPIO45, 0, &PAD18_GPIO45); +PINCTRL_MUX(GPIO46, 0, &PAD19_GPIO46); +PINCTRL_MUX(GPIO47, 0, &PAD15_GPIO47); +PINCTRL_MUX(GPIO48, 0, &PAD20_GPIO48); +PINCTRL_MUX(GPIO49, 0, &PAD22_GPIO49); +PINCTRL_MUX(GPIO50, 0, &PAD23_GPIO50); +PINCTRL_MUX(GPIO51, 0, &PAD24_GPIO51); +PINCTRL_MUX(GPIO52, 0, &PAD25_GPIO52); +PINCTRL_MUX(GPIO53, 0, &PAD26_GPIO53); +PINCTRL_MUX(GPIO54, 0, &PAD27_GPIO54); +PINCTRL_MUX(GPIO55, 0, &PAD28_GPIO55); +PINCTRL_MUX(GPIO56, 0, &PAD29_GPIO56); +PINCTRL_MUX(GPIO57, 0, &PAD30_GPIO57); +PINCTRL_MUX(GPIO58, 0, &PAD31_GPIO58); +PINCTRL_MUX(GPIO59, 0, &PAD32_GPIO59); +PINCTRL_MUX(GPIO60, 0, &PAD33_GPIO60); +PINCTRL_MUX(GPIO61, 0, &PAD34_GPIO61); +PINCTRL_MUX(GPIO62, 0, &PAD35_GPIO62); +PINCTRL_MUX(GPIO63, 0, &PAD36_GPIO63); + +PINCTRL_MUX(SD1_CLK_EMMC, 3, &PAD9_SD1_CLK, &PAD20_SD1_CLK, &PAD30_SD1_CLK, + &PAD42_SD1_CLK); +PINCTRL_MUX(SD1_CMD_RSP_EMMC, 3, &PAD11_SD1_CMD_RSP, &PAD23_SD1_CMD_RSP, + &PAD32_SD1_CMD_RSP, &PAD43_SD1_CMD_RSP); +PINCTRL_MUX(SD1_DATA_0_EMMC, 3, &PAD12_SD1_DATA_0, &PAD24_SD1_DATA_0, + &PAD33_SD1_DATA_0, &PAD44_SD1_DATA_0); +PINCTRL_MUX(SD1_DATA_1_EMMC, 3, &PAD13_SD1_DATA_1, &PAD25_SD1_DATA_1, + &PAD34_SD1_DATA_1, &PAD45_SD1_DATA_1); +PINCTRL_MUX(SD1_DATA_2_EMMC, 3, &PAD14_SD1_DATA_2, &PAD26_SD1_DATA_2, + &PAD35_SD1_DATA_2, &PAD46_SD1_DATA_2); +PINCTRL_MUX(SD1_DATA_3_EMMC, 3, &PAD15_SD1_DATA_3, &PAD27_SD1_DATA_3, + &PAD36_SD1_DATA_3, &PAD47_SD1_DATA_3); + +/* PINCTRL_DEVICE */ +PINCTRL_DEVICE(ACI2S, 5, &MUX_AC_I2S_CLK, &MUX_AC_I2S_DI, &MUX_AC_I2S_DO, + &MUX_AC_I2S_WS, &MUX_AC_MCLK); +PINCTRL_DEVICE(AC_MCLK, 1, &MUX_AC_MCLK); +PINCTRL_DEVICE(ARCJTAG, 5, &MUX_ARC_JTAG_TCK, &MUX_ARC_JTAG_TDI, + &MUX_ARC_JTAG_TDO, &MUX_ARC_JTAG_TMS, &MUX_ARC_JTAG_TRSTN); +PINCTRL_DEVICE(ARMJTAG, 5, &MUX_ARM_JTAG_TCK, &MUX_ARM_JTAG_TDI, + &MUX_ARM_JTAG_TDO, &MUX_ARM_JTAG_TMS, &MUX_ARM_JTAG_TRSTN); +PINCTRL_DEVICE(DWI2S, 4, &MUX_DW_I2S_CLK, &MUX_DW_I2S_DI, &MUX_DW_I2S_DO, + &MUX_DW_I2S_WS); +PINCTRL_DEVICE(ETH, 2, &MUX_ETH_LINK_ACT, &MUX_ETH_LINK_STA); +PINCTRL_DEVICE(I2C0, 2, &MUX_I2C0_SCL, &MUX_I2C0_SDA); +PINCTRL_DEVICE(I2C1, 2, &MUX_I2C1_SCL, &MUX_I2C1_SDA); +PINCTRL_DEVICE(I2C2, 2, &MUX_I2C2_SCL, &MUX_I2C2_SDA); +PINCTRL_DEVICE(PAEJTAG, 5, &MUX_PAE_JTAG_TCK, &MUX_PAE_JTAG_TDI, + &MUX_PAE_JTAG_TDO, &MUX_PAE_JTAG_TMS, &MUX_PAE_JTAG_TRSTN); +PINCTRL_DEVICE(PWM0, 1, &MUX_PWM0); +PINCTRL_DEVICE(PWM1, 1, &MUX_PWM1); +PINCTRL_DEVICE(PWM10, 1, &MUX_PWM10); +PINCTRL_DEVICE(PWM11, 1, &MUX_PWM11); +PINCTRL_DEVICE(PWM2, 1, &MUX_PWM2); +PINCTRL_DEVICE(PWM3, 1, &MUX_PWM3); +PINCTRL_DEVICE(PWM4, 1, &MUX_PWM4); +PINCTRL_DEVICE(PWM5, 1, &MUX_PWM5); +PINCTRL_DEVICE(PWM6, 1, &MUX_PWM6); +PINCTRL_DEVICE(PWM7, 1, &MUX_PWM7); +PINCTRL_DEVICE(PWM8, 1, &MUX_PWM8); +PINCTRL_DEVICE(PWM9, 1, &MUX_PWM9); +PINCTRL_DEVICE(RMII, 10, &MUX_MAC_MDC, &MUX_MAC_MDIO, &MUX_MAC_REF_CLK, + &MUX_MAC_RMII_CLK, &MUX_MAC_RXDV, &MUX_MAC_RXD_0, &MUX_MAC_RXD_1, + &MUX_MAC_TXD_0, &MUX_MAC_TXD_1, &MUX_MAC_TXEN); +PINCTRL_DEVICE(RTC, 1, &MUX_RTC_CLK); +PINCTRL_DEVICE(SADC_XAIN0, 1, &MUX_SADC_XAIN0); +PINCTRL_DEVICE(SADC_XAIN1, 1, &MUX_SADC_XAIN1); +PINCTRL_DEVICE(SADC_XAIN2, 1, &MUX_SADC_XAIN2); +PINCTRL_DEVICE(SADC_XAIN3, 1, &MUX_SADC_XAIN3); +PINCTRL_DEVICE(SD0, 7, &MUX_SD0_CD, &MUX_SD0_CLK, &MUX_SD0_CMD_RSP, + &MUX_SD0_DATA_0, &MUX_SD0_DATA_1, &MUX_SD0_DATA_2, &MUX_SD0_DATA_3); +PINCTRL_DEVICE(SD0_1BIT_NO_WP, 4, &MUX_SD0_CD, &MUX_SD0_CLK, &MUX_SD0_CMD_RSP, + &MUX_SD0_DATA_0); +PINCTRL_DEVICE(SD0_NO_WP, 7, &MUX_SD0_CD, &MUX_SD0_CLK, &MUX_SD0_CMD_RSP, + &MUX_SD0_DATA_0, &MUX_SD0_DATA_1, &MUX_SD0_DATA_2, &MUX_SD0_DATA_3); +PINCTRL_DEVICE(SD0_WIFI, 6, &MUX_SD0_CLK, &MUX_SD0_CMD_RSP, &MUX_SD0_DATA_0, + &MUX_SD0_DATA_1, &MUX_SD0_DATA_2, &MUX_SD0_DATA_3); +PINCTRL_DEVICE(SD1, 7, &MUX_SD1_CD, &MUX_SD1_CLK, &MUX_SD1_CMD_RSP, + &MUX_SD1_DATA_0, &MUX_SD1_DATA_1, &MUX_SD1_DATA_2, &MUX_SD1_DATA_3); +PINCTRL_DEVICE(SD1_1BIT_NO_WP, 4, &MUX_SD1_CD, &MUX_SD1_CLK, &MUX_SD1_CMD_RSP, + &MUX_SD1_DATA_0); +PINCTRL_DEVICE(SD1_NO_WP, 7, &MUX_SD1_CD, &MUX_SD1_CLK, &MUX_SD1_CMD_RSP, + &MUX_SD1_DATA_0, &MUX_SD1_DATA_1, &MUX_SD1_DATA_2, &MUX_SD1_DATA_3); +PINCTRL_DEVICE(SD1_WIFI, 6, &MUX_SD1_CLK, &MUX_SD1_CMD_RSP, &MUX_SD1_DATA_0, + &MUX_SD1_DATA_1, &MUX_SD1_DATA_2, &MUX_SD1_DATA_3); +PINCTRL_DEVICE(SENSOR_CLK, 1, &MUX_SENSOR_CLK); +PINCTRL_DEVICE(SSI0, 4, &MUX_GPIO6, &MUX_SSI0_CLK, &MUX_SSI0_RXD, + &MUX_SSI0_TXD); +PINCTRL_DEVICE(SSI0_4BIT, 6, &MUX_GPIO6, &MUX_SSI0_CLK, &MUX_SSI0_D2, + &MUX_SSI0_D3, &MUX_SSI0_RXD, &MUX_SSI0_TXD); +PINCTRL_DEVICE(SSI1, 4, &MUX_GPIO14, &MUX_SSI1_CLK, &MUX_SSI1_RXD, + &MUX_SSI1_TXD); +PINCTRL_DEVICE(SSI2, 4, &MUX_SSI2_CLK, &MUX_SSI2_CSN_0, &MUX_SSI2_RXD, + &MUX_SSI2_TXD); +PINCTRL_DEVICE(UART0, 2, &MUX_UART0_RX, &MUX_UART0_TX); +PINCTRL_DEVICE(UART1, 2, &MUX_UART1_RX, &MUX_UART1_TX); +PINCTRL_DEVICE(UART2, 2, &MUX_UART2_RX, &MUX_UART2_TX); +PINCTRL_DEVICE(USB, 1, &MUX_USB_PWREN); +PINCTRL_DEVICE(GPIO0, 1, &MUX_GPIO0); +PINCTRL_DEVICE(GPIO1, 1, &MUX_GPIO1); +PINCTRL_DEVICE(GPIO2, 1, &MUX_GPIO2); +PINCTRL_DEVICE(GPIO3, 1, &MUX_GPIO3); +PINCTRL_DEVICE(GPIO4, 1, &MUX_GPIO4); +PINCTRL_DEVICE(GPIO5, 1, &MUX_GPIO5); +PINCTRL_DEVICE(GPIO6, 1, &MUX_GPIO6); +PINCTRL_DEVICE(GPIO7, 1, &MUX_GPIO7); +PINCTRL_DEVICE(GPIO8, 1, &MUX_GPIO8); +PINCTRL_DEVICE(GPIO9, 1, &MUX_GPIO9); +PINCTRL_DEVICE(GPIO10, 1, &MUX_GPIO10); +PINCTRL_DEVICE(GPIO11, 1, &MUX_GPIO11); +PINCTRL_DEVICE(GPIO12, 1, &MUX_GPIO12); +PINCTRL_DEVICE(GPIO13, 1, &MUX_GPIO13); +PINCTRL_DEVICE(GPIO14, 1, &MUX_GPIO14); +PINCTRL_DEVICE(GPIO15, 1, &MUX_GPIO15); +PINCTRL_DEVICE(GPIO16, 1, &MUX_GPIO16); +PINCTRL_DEVICE(GPIO17, 1, &MUX_GPIO17); +PINCTRL_DEVICE(GPIO18, 1, &MUX_GPIO18); +PINCTRL_DEVICE(GPIO19, 1, &MUX_GPIO19); +PINCTRL_DEVICE(GPIO20, 1, &MUX_GPIO20); +PINCTRL_DEVICE(GPIO21, 1, &MUX_GPIO21); +PINCTRL_DEVICE(GPIO22, 1, &MUX_GPIO22); +PINCTRL_DEVICE(GPIO23, 1, &MUX_GPIO23); +PINCTRL_DEVICE(GPIO24, 1, &MUX_GPIO24); +PINCTRL_DEVICE(GPIO25, 1, &MUX_GPIO25); +PINCTRL_DEVICE(GPIO26, 1, &MUX_GPIO26); +PINCTRL_DEVICE(GPIO27, 1, &MUX_GPIO27); +PINCTRL_DEVICE(GPIO28, 1, &MUX_GPIO28); +PINCTRL_DEVICE(GPIO29, 1, &MUX_GPIO29); +PINCTRL_DEVICE(GPIO30, 1, &MUX_GPIO30); +PINCTRL_DEVICE(GPIO31, 1, &MUX_GPIO31); +PINCTRL_DEVICE(GPIO32, 1, &MUX_GPIO32); +PINCTRL_DEVICE(GPIO33, 1, &MUX_GPIO33); +PINCTRL_DEVICE(GPIO34, 1, &MUX_GPIO34); +PINCTRL_DEVICE(GPIO35, 1, &MUX_GPIO35); +PINCTRL_DEVICE(GPIO36, 1, &MUX_GPIO36); +PINCTRL_DEVICE(GPIO37, 1, &MUX_GPIO37); +PINCTRL_DEVICE(GPIO38, 1, &MUX_GPIO38); +PINCTRL_DEVICE(GPIO39, 1, &MUX_GPIO39); +PINCTRL_DEVICE(GPIO40, 1, &MUX_GPIO40); +PINCTRL_DEVICE(GPIO41, 1, &MUX_GPIO41); +PINCTRL_DEVICE(GPIO42, 1, &MUX_GPIO42); +PINCTRL_DEVICE(GPIO43, 1, &MUX_GPIO43); +PINCTRL_DEVICE(GPIO44, 1, &MUX_GPIO44); +PINCTRL_DEVICE(GPIO45, 1, &MUX_GPIO45); +PINCTRL_DEVICE(GPIO46, 1, &MUX_GPIO46); +PINCTRL_DEVICE(GPIO47, 1, &MUX_GPIO47); +PINCTRL_DEVICE(GPIO48, 1, &MUX_GPIO48); +PINCTRL_DEVICE(GPIO49, 1, &MUX_GPIO49); +PINCTRL_DEVICE(GPIO50, 1, &MUX_GPIO50); +PINCTRL_DEVICE(GPIO51, 1, &MUX_GPIO51); +PINCTRL_DEVICE(GPIO52, 1, &MUX_GPIO52); +PINCTRL_DEVICE(GPIO53, 1, &MUX_GPIO53); +PINCTRL_DEVICE(GPIO54, 1, &MUX_GPIO54); +PINCTRL_DEVICE(GPIO55, 1, &MUX_GPIO55); +PINCTRL_DEVICE(GPIO56, 1, &MUX_GPIO56); +PINCTRL_DEVICE(GPIO57, 1, &MUX_GPIO57); +PINCTRL_DEVICE(GPIO58, 1, &MUX_GPIO58); +PINCTRL_DEVICE(GPIO59, 1, &MUX_GPIO59); +PINCTRL_DEVICE(GPIO60, 1, &MUX_GPIO60); +PINCTRL_DEVICE(GPIO61, 1, &MUX_GPIO61); +PINCTRL_DEVICE(GPIO62, 1, &MUX_GPIO62); +PINCTRL_DEVICE(GPIO63, 1, &MUX_GPIO63); + +PINCTRL_DEVICE(SD1_EMMC, 6, &MUX_SD1_CLK_EMMC, &MUX_SD1_CMD_RSP_EMMC, + &MUX_SD1_DATA_0_EMMC, &MUX_SD1_DATA_1_EMMC, &MUX_SD1_DATA_2_EMMC, + &MUX_SD1_DATA_3_EMMC); + +void fh_pinctrl_init_devicelist(OS_LIST *list) +{ + OS_LIST_EMPTY(list); + + /*PINCTRL_ADD_DEVICE*/ + PINCTRL_ADD_DEVICE(ACI2S); + PINCTRL_ADD_DEVICE(AC_MCLK); + PINCTRL_ADD_DEVICE(ARCJTAG); + PINCTRL_ADD_DEVICE(ARMJTAG); + PINCTRL_ADD_DEVICE(DWI2S); + PINCTRL_ADD_DEVICE(ETH); + PINCTRL_ADD_DEVICE(I2C0); + PINCTRL_ADD_DEVICE(I2C1); + PINCTRL_ADD_DEVICE(I2C2); + PINCTRL_ADD_DEVICE(PAEJTAG); + PINCTRL_ADD_DEVICE(PWM0); + PINCTRL_ADD_DEVICE(PWM1); + PINCTRL_ADD_DEVICE(PWM10); + PINCTRL_ADD_DEVICE(PWM11); + PINCTRL_ADD_DEVICE(PWM2); + PINCTRL_ADD_DEVICE(PWM3); + PINCTRL_ADD_DEVICE(PWM4); + PINCTRL_ADD_DEVICE(PWM5); + PINCTRL_ADD_DEVICE(PWM6); + PINCTRL_ADD_DEVICE(PWM7); + PINCTRL_ADD_DEVICE(PWM8); + PINCTRL_ADD_DEVICE(PWM9); + PINCTRL_ADD_DEVICE(RMII); + PINCTRL_ADD_DEVICE(RTC); + PINCTRL_ADD_DEVICE(SADC_XAIN0); + PINCTRL_ADD_DEVICE(SADC_XAIN1); + PINCTRL_ADD_DEVICE(SADC_XAIN2); + PINCTRL_ADD_DEVICE(SADC_XAIN3); + PINCTRL_ADD_DEVICE(SD0); + PINCTRL_ADD_DEVICE(SD0_1BIT_NO_WP); + PINCTRL_ADD_DEVICE(SD0_NO_WP); + PINCTRL_ADD_DEVICE(SD0_WIFI); + PINCTRL_ADD_DEVICE(SD1); + PINCTRL_ADD_DEVICE(SD1_1BIT_NO_WP); + PINCTRL_ADD_DEVICE(SD1_NO_WP); + PINCTRL_ADD_DEVICE(SD1_WIFI); + PINCTRL_ADD_DEVICE(SENSOR_CLK); + PINCTRL_ADD_DEVICE(SSI0); + PINCTRL_ADD_DEVICE(SSI0_4BIT); + PINCTRL_ADD_DEVICE(SSI1); + PINCTRL_ADD_DEVICE(SSI2); + PINCTRL_ADD_DEVICE(UART0); + PINCTRL_ADD_DEVICE(UART1); + PINCTRL_ADD_DEVICE(UART2); + PINCTRL_ADD_DEVICE(USB); + PINCTRL_ADD_DEVICE(GPIO0); + PINCTRL_ADD_DEVICE(GPIO1); + PINCTRL_ADD_DEVICE(GPIO2); + PINCTRL_ADD_DEVICE(GPIO3); + PINCTRL_ADD_DEVICE(GPIO4); + PINCTRL_ADD_DEVICE(GPIO5); + PINCTRL_ADD_DEVICE(GPIO6); + PINCTRL_ADD_DEVICE(GPIO7); + PINCTRL_ADD_DEVICE(GPIO8); + PINCTRL_ADD_DEVICE(GPIO9); + PINCTRL_ADD_DEVICE(GPIO10); + PINCTRL_ADD_DEVICE(GPIO11); + PINCTRL_ADD_DEVICE(GPIO12); + PINCTRL_ADD_DEVICE(GPIO13); + PINCTRL_ADD_DEVICE(GPIO14); + PINCTRL_ADD_DEVICE(GPIO15); + PINCTRL_ADD_DEVICE(GPIO16); + PINCTRL_ADD_DEVICE(GPIO17); + PINCTRL_ADD_DEVICE(GPIO18); + PINCTRL_ADD_DEVICE(GPIO19); + PINCTRL_ADD_DEVICE(GPIO20); + PINCTRL_ADD_DEVICE(GPIO21); + PINCTRL_ADD_DEVICE(GPIO22); + PINCTRL_ADD_DEVICE(GPIO23); + PINCTRL_ADD_DEVICE(GPIO24); + PINCTRL_ADD_DEVICE(GPIO25); + PINCTRL_ADD_DEVICE(GPIO26); + PINCTRL_ADD_DEVICE(GPIO27); + PINCTRL_ADD_DEVICE(GPIO28); + PINCTRL_ADD_DEVICE(GPIO29); + PINCTRL_ADD_DEVICE(GPIO30); + PINCTRL_ADD_DEVICE(GPIO31); + PINCTRL_ADD_DEVICE(GPIO32); + PINCTRL_ADD_DEVICE(GPIO33); + PINCTRL_ADD_DEVICE(GPIO34); + PINCTRL_ADD_DEVICE(GPIO35); + PINCTRL_ADD_DEVICE(GPIO36); + PINCTRL_ADD_DEVICE(GPIO37); + PINCTRL_ADD_DEVICE(GPIO38); + PINCTRL_ADD_DEVICE(GPIO39); + PINCTRL_ADD_DEVICE(GPIO40); + PINCTRL_ADD_DEVICE(GPIO41); + PINCTRL_ADD_DEVICE(GPIO42); + PINCTRL_ADD_DEVICE(GPIO43); + PINCTRL_ADD_DEVICE(GPIO44); + PINCTRL_ADD_DEVICE(GPIO45); + PINCTRL_ADD_DEVICE(GPIO46); + PINCTRL_ADD_DEVICE(GPIO47); + PINCTRL_ADD_DEVICE(GPIO48); + PINCTRL_ADD_DEVICE(GPIO49); + PINCTRL_ADD_DEVICE(GPIO50); + PINCTRL_ADD_DEVICE(GPIO51); + PINCTRL_ADD_DEVICE(GPIO52); + PINCTRL_ADD_DEVICE(GPIO53); + PINCTRL_ADD_DEVICE(GPIO54); + PINCTRL_ADD_DEVICE(GPIO55); + PINCTRL_ADD_DEVICE(GPIO56); + PINCTRL_ADD_DEVICE(GPIO57); + PINCTRL_ADD_DEVICE(GPIO58); + PINCTRL_ADD_DEVICE(GPIO59); + PINCTRL_ADD_DEVICE(GPIO60); + PINCTRL_ADD_DEVICE(GPIO61); + PINCTRL_ADD_DEVICE(GPIO62); + PINCTRL_ADD_DEVICE(GPIO63); + + PINCTRL_ADD_DEVICE(SD1_EMMC); +} + +char *fh_pinctrl_selected_devices[] = +{ + CONFIG_PINCTRL_SELECT +}; diff --git a/arch/arm/mach-fh/fh_chipid.c b/arch/arm/mach-fh/fh_chipid.c new file mode 100644 index 00000000..6a5b8446 --- /dev/null +++ b/arch/arm/mach-fh/fh_chipid.c @@ -0,0 +1,214 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include "soc.h" + +#define CHIP_INFO(__plat_id, __chip_id, __chip_mask, chip, size) \ + { \ + ._plat_id = __plat_id, \ + ._chip_id = __chip_id, \ + ._chip_mask = __chip_mask, \ + .chip_id = FH_CHIP_##chip, \ + .ddr_size = size, \ + .chip_name = #chip, \ + }, + +#define RD_REG 0xffffffff + +static struct fh_chip_info chip_infos[] = { + CHIP_INFO(0x46488302, 0x37, 0x3F, FH8632, 512) + CHIP_INFO(0x46488302, 0x07, 0x3F, FH8632v2, 512) + CHIP_INFO(0x17092901, 0xC, 0xF, FH8852, 512) + CHIP_INFO(0x17092901, 0xD, 0xF, FH8856, 1024) + CHIP_INFO(0x18112301, 0x0, 0x0, FH8626V100, 512) + CHIP_INFO(0x19112201, 0x00000001, 0x00FFFFFF, FH8852V200, RD_REG) + CHIP_INFO(0x19112201, 0x00100001, 0x00FFFFFF, FH8856V200, RD_REG) + CHIP_INFO(0x19112201, 0x00410001, 0x00FFFFFF, FH8858V200, RD_REG) + CHIP_INFO(0x19112201, 0x00200001, 0x00FFFFFF, FH8856V201, RD_REG) + CHIP_INFO(0x19112201, 0x00300001, 0x00FFFFFF, FH8858V201, RD_REG) + CHIP_INFO(0x19112201, 0x00000002, 0x00FFFFFF, FH8852V210, RD_REG) + CHIP_INFO(0x19112201, 0x00100002, 0x00FFFFFF, FH8856V210, RD_REG) + CHIP_INFO(0x19112201, 0x00410002, 0x00FFFFFF, FH8858V210, RD_REG) + CHIP_INFO(0x20031601, 0xc, 0xc, FH8652, RD_REG) + CHIP_INFO(0x20031601, 0x8, 0xc, FH8656, RD_REG) + CHIP_INFO(0x20031601, 0x4, 0xc, FH8658, RD_REG) +}; + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) +#endif + + +#define FH_GET_CHIP_ID(plat_id, chip_id) \ + int plat_id = 0;\ + int chip_id = 0;\ + fh_get_chipid(&plat_id, &chip_id) + + +struct fh_chip_info *fh_get_chip_info(void) +{ + static struct fh_chip_info *chip_info = NULL; + struct fh_chip_info *info = NULL; + int plat_id = 0; + int chip_id = 0; + int i = 0; + + if (chip_info != NULL) + return chip_info; + + fh_get_chipid(&plat_id, &chip_id); +#ifdef REG_PMU_CHIP_INFO + chip_id = fh_pmu_get_reg(REG_PMU_CHIP_INFO); +#endif + for (i = 0; i < ARRAY_SIZE(chip_infos); i++) + { + info = &chip_infos[i]; + if (plat_id == info->_plat_id && (chip_id & info->_chip_mask) == info->_chip_id) + { + chip_info = info; + if (chip_info->ddr_size == RD_REG) + chip_info->ddr_size = fh_pmu_get_ddrsize(); + return info; + } + } + pr_err("Error: unknown chip\n"); + return NULL; +} +EXPORT_SYMBOL(fh_get_chip_info); + +unsigned int fh_get_ddrsize_mbit(void) +{ + struct fh_chip_info *info = fh_get_chip_info(); + + if (info) + return info->ddr_size; + return 0; +} +EXPORT_SYMBOL(fh_get_ddrsize_mbit); + +char *fh_get_chipname(void) +{ + struct fh_chip_info *info = fh_get_chip_info(); + + if (info) + return info->chip_name; + return "UNKNOWN"; +} +EXPORT_SYMBOL(fh_get_chipname); + +#define DEFINE_FUNC_FH_IS(name, chip) \ +unsigned int fh_is_##name(void) \ +{ \ + struct fh_chip_info *info = fh_get_chip_info(); \ + \ + if (info) \ + return info->chip_id == FH_CHIP_##chip; \ + return 0; \ +} \ +EXPORT_SYMBOL(fh_is_##name) + +unsigned int fh_is_8632(void) +{ + struct fh_chip_info *info = fh_get_chip_info(); + + if (info) + return (info->chip_id == FH_CHIP_FH8632 || \ + info->chip_id == FH_CHIP_FH8632v2); + return 0; +} +EXPORT_SYMBOL(fh_is_8632); + +DEFINE_FUNC_FH_IS(8830, FH8830); +DEFINE_FUNC_FH_IS(8852, FH8852); +DEFINE_FUNC_FH_IS(8856, FH8856); +DEFINE_FUNC_FH_IS(8626v100, FH8626V100); +DEFINE_FUNC_FH_IS(8852v200, FH8852V200); +DEFINE_FUNC_FH_IS(8856v200, FH8856V200); +DEFINE_FUNC_FH_IS(8858v200, FH8858V200); +DEFINE_FUNC_FH_IS(8856v201, FH8856V201); +DEFINE_FUNC_FH_IS(8858v201, FH8858V201); +DEFINE_FUNC_FH_IS(8852v210, FH8852V210); +DEFINE_FUNC_FH_IS(8856v210, FH8856V210); +DEFINE_FUNC_FH_IS(8858v210, FH8858V210); +DEFINE_FUNC_FH_IS(8652, FH8652); +DEFINE_FUNC_FH_IS(8656, FH8656); +DEFINE_FUNC_FH_IS(8658, FH8658); + + +static void *v_seq_start(struct seq_file *s, loff_t *pos) +{ + static unsigned long counter; + if (*pos == 0) + return &counter; + else { + *pos = 0; + return NULL; + } +} + +static void *v_seq_next(struct seq_file *s, void *v, loff_t *pos) +{ + (*pos)++; + return NULL; +} + +static void v_seq_stop(struct seq_file *s, void *v) +{ + +} + +static int v_seq_show(struct seq_file *sfile, void *v) +{ + unsigned int plat_id = 0; + unsigned int chip_id = 0; + fh_get_chipid(&plat_id, &chip_id); + + seq_printf(sfile, "chip_name\t: %s\n", fh_get_chipname()); + seq_printf(sfile, "ddr_size\t: %dMbit\n", fh_get_ddrsize_mbit()); + seq_printf(sfile, "plat_id\t\t: 0x%x\npkg_id\t\t: 0x%x\n", + plat_id, chip_id); + return 0; +} + +static const struct seq_operations chipid_seq_ops = { + .start = v_seq_start, + .next = v_seq_next, + .stop = v_seq_stop, + .show = v_seq_show +}; + +static int fh_chipid_proc_open(struct inode *inode, struct file *file) +{ + return seq_open(file, &chipid_seq_ops); +} + +static const struct file_operations fh_chipid_proc_ops = { + .owner = THIS_MODULE, + .open = fh_chipid_proc_open, + .read = seq_read, +}; + +#define FH_CHIPID_PROC_FILE "driver/chip" +static struct proc_dir_entry *chipid_proc_file; + +int fh_chipid_init(void) +{ + chipid_proc_file = proc_create(FH_CHIPID_PROC_FILE, 0644, NULL, + &fh_chipid_proc_ops); + + if (!chipid_proc_file) { + pr_err("%s: ERROR: %s proc file create failed", + __func__, "CHIP ID"); + return -EINVAL; + } + + pr_info("CHIP: %s\n", fh_get_chipname()); + + return 0; +} + diff --git a/arch/arm/mach-fh/fh_common.c b/arch/arm/mach-fh/fh_common.c new file mode 100644 index 00000000..1037c3a2 --- /dev/null +++ b/arch/arm/mach-fh/fh_common.c @@ -0,0 +1,110 @@ +/* + * fh_common.c + * + * Copyright (C) 2019 Fullhan Microelectronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include + +/** + * fh_setscheduler - change the scheduling policy and/or RT priority of `current` thread. + * @policy: new policy. egz. SCHED_RR + * @priority: new priority. egz MAX_USER_RT_PRIO-12 + * @param: structure containing the new RT priority. + * + * NOTE that the task may be already dead. + */ +void fh_setscheduler(int policy, int priority) +{ + struct sched_param param; + param.sched_priority = priority; + sched_setscheduler(current, policy, ¶m); +} +EXPORT_SYMBOL(fh_setscheduler); + +int fh_clk_enable(struct clk *clk) +{ + return clk_enable(clk); +} +EXPORT_SYMBOL(fh_clk_enable); + +unsigned long fh_clk_get_rate(struct clk *clk) +{ + return clk_get_rate(clk); +} +EXPORT_SYMBOL(fh_clk_get_rate); + +int fh_clk_set_rate(struct clk *clk, unsigned long rate) +{ + return clk_set_rate(clk, rate); +} +EXPORT_SYMBOL(fh_clk_set_rate); + +int fh_clk_prepare(struct clk *clk) +{ + return clk_prepare(clk); +} +EXPORT_SYMBOL(fh_clk_prepare); + +void fh_clk_disable(struct clk *clk) +{ + clk_disable(clk); +} +EXPORT_SYMBOL(fh_clk_disable); + +void fh_clk_unprepare(struct clk *clk) +{ + clk_unprepare(clk); +} +EXPORT_SYMBOL(fh_clk_unprepare); + +int fh_clk_prepare_enable(struct clk *clk) +{ + return clk_prepare_enable(clk); +} +EXPORT_SYMBOL(fh_clk_prepare_enable); + +void fh_clk_disable_unprepare(struct clk *clk) +{ + clk_disable_unprepare(clk); +} +EXPORT_SYMBOL(fh_clk_disable_unprepare); + +bool fh_clk_is_enabled(struct clk *clk) +{ + return __clk_is_enabled(clk); +} +EXPORT_SYMBOL(fh_clk_is_enabled); + + +int fh_clk_set_parent(struct clk *clk, struct clk *parent) +{ + return clk_set_parent(clk, parent); +} +EXPORT_SYMBOL(fh_clk_set_parent); + +struct clk *fh_clk_get_parent(struct clk *clk) +{ + return clk_get_parent(clk); +} +EXPORT_SYMBOL(fh_clk_get_parent); + +bool fh_clk_has_parent(struct clk *clk, struct clk *parent) +{ + return clk_has_parent(clk, parent); +} +EXPORT_SYMBOL(fh_clk_has_parent); + +unsigned int fh_irq_create_mapping(struct irq_domain *domain, + irq_hw_number_t hwirq) +{ + return irq_create_mapping(domain, hwirq); +} +EXPORT_SYMBOL(fh_irq_create_mapping); diff --git a/arch/arm/mach-fh/fullhan.c b/arch/arm/mach-fh/fullhan.c new file mode 100644 index 00000000..4b62405d --- /dev/null +++ b/arch/arm/mach-fh/fullhan.c @@ -0,0 +1,121 @@ +/* + * Fullhan FH8810 board support + * + * Copyright (C) 2014 Fullhan Microelectronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#include +#include +#include +#include + +#ifdef CONFIG_CPU_V6 +#include +static void fh_cpu_do_idle(void) +{ +} + +static int __init fh_cpu_idle_init(void) +{ + arm_pm_idle = fh_cpu_do_idle; + return 0; +} +early_initcall(fh_cpu_idle_init); +#endif + + +static int __init fullhan_init_early(void) +{ + + fh_pmu_init(); + fh_chipid_init(); + +#ifdef CONFIG_EMULATION + pr_info("---Emulation Version---\n"); +#endif + return 0; +} +arch_initcall(fullhan_init_early); + +#ifdef CONFIG_USE_OF + +static const char *fh8856v200_compat[] __initconst = { + "fh,fh8856v200", + NULL, +}; + +static const char *fh8858v200_compat[] __initconst = { + "fh,fh8858v200", + NULL, +}; + +static const char *fh8852v200_compat[] __initconst = { + "fh,fh8852v200", + NULL, +}; + +static const char *fh8856v210_compat[] __initconst = { + "fh,fh8856v210", + NULL, +}; + +static const char *fh8858v210_compat[] __initconst = { + "fh,fh8858v210", + NULL, +}; + +static const char *fh8852v210_compat[] __initconst = { + "fh,fh8852v210", + NULL, +}; + + + + + + + +DT_MACHINE_START(FH8856V200, "Fullhan FH8856V200 (Flattened Device Tree)") + .dt_compat = fh8856v200_compat, +MACHINE_END + +DT_MACHINE_START(FH8858V200, "Fullhan FH8858V200 (Flattened Device Tree)") + .dt_compat = fh8858v200_compat, +MACHINE_END + +DT_MACHINE_START(FH8852V200, "Fullhan FH8852V200 (Flattened Device Tree)") + .dt_compat = fh8852v200_compat, +MACHINE_END + + +DT_MACHINE_START(FH8856V210, "Fullhan FH8856V210 (Flattened Device Tree)") + .dt_compat = fh8856v210_compat, +MACHINE_END + +DT_MACHINE_START(FH8858V210, "Fullhan FH8858V210 (Flattened Device Tree)") + .dt_compat = fh8858v210_compat, +MACHINE_END + +DT_MACHINE_START(FH8852V210, "Fullhan FH8852V210 (Flattened Device Tree)") + .dt_compat = fh8852v210_compat, +MACHINE_END + + + + + + + +#endif diff --git a/arch/arm/mach-fh/hotplug.c b/arch/arm/mach-fh/hotplug.c new file mode 100644 index 00000000..6b25b845 --- /dev/null +++ b/arch/arm/mach-fh/hotplug.c @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2013 Linaro Ltd. + * Copyright (c) 2013 Hisilicon Limited. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "core.h" + +/* Sysctrl registers in Hi3620 SoC */ +#define SCISOEN 0xc0 +#define SCISODIS 0xc4 +#define SCPERPWREN 0xd0 +#define SCPERPWRDIS 0xd4 +#define SCCPUCOREEN 0xf4 +#define SCCPUCOREDIS 0xf8 +#define SCPERCTRL0 0x200 +#define SCCPURSTEN 0x410 +#define SCCPURSTDIS 0x414 + +/* + * bit definition in SCISOEN/SCPERPWREN/... + * + * CPU2_ISO_CTRL (1 << 5) + * CPU3_ISO_CTRL (1 << 6) + * ... + */ +#define CPU2_ISO_CTRL (1 << 5) + +/* + * bit definition in SCPERCTRL0 + * + * CPU0_WFI_MASK_CFG (1 << 28) + * CPU1_WFI_MASK_CFG (1 << 29) + * ... + */ +#define CPU0_WFI_MASK_CFG (1 << 28) + +/* + * bit definition in SCCPURSTEN/... + * + * CPU0_SRST_REQ_EN (1 << 0) + * CPU1_SRST_REQ_EN (1 << 1) + * ... + */ +#define CPU0_HPM_SRST_REQ_EN (1 << 22) +#define CPU0_DBG_SRST_REQ_EN (1 << 12) +#define CPU0_NEON_SRST_REQ_EN (1 << 4) +#define CPU0_SRST_REQ_EN (1 << 0) + +#define HIX5HD2_PERI_CRG20 0x50 +#define CRG20_CPU1_RESET (1 << 17) + +#define HIX5HD2_PERI_PMC0 0x1000 +#define PMC0_CPU1_WAIT_MTCOMS_ACK (1 << 8) +#define PMC0_CPU1_PMC_ENABLE (1 << 7) +#define PMC0_CPU1_POWERDOWN (1 << 3) + +#define HIP01_PERI9 0x50 +#define PERI9_CPU1_RESET (1 << 1) + + +static void __iomem *ctrl_base; + + +static int fhca7_hotplug_init(void) +{ + struct device_node *node; + + node = of_find_compatible_node(NULL, NULL, "fh,fh-pmu"); + if (!node) { + return -ENOENT; + } + + ctrl_base = of_iomap(node, 0); + of_node_put(node); + if (!ctrl_base) { + return -ENOMEM; + } + + return 0; +} + +void fhca7_set_cpu(int cpu, bool enable) +{ + if (!ctrl_base) { + if (fhca7_hotplug_init() < 0) + return; + } + +} + +static inline void cpu_enter_lowpower(void) +{ + unsigned int v; + + flush_cache_all(); + + /* + * Turn off coherency and L1 D-cache + */ + asm volatile( + " mrc p15, 0, %0, c1, c0, 1\n" + " bic %0, %0, #0x40\n" + " mcr p15, 0, %0, c1, c0, 1\n" + " mrc p15, 0, %0, c1, c0, 0\n" + " bic %0, %0, #0x04\n" + " mcr p15, 0, %0, c1, c0, 0\n" + : "=&r" (v) + : "r" (0) + : "cc"); +} + +#ifdef CONFIG_HOTPLUG_CPU +void fhca7_cpu_die(unsigned int cpu) +{ + cpu_enter_lowpower(); + arch_cpu_idle(); + + /* We should have never returned from idle */ + panic("cpu %d unexpectedly exit from shutdown\n", cpu); +} + +int fhca7_cpu_kill(unsigned int cpu) +{ + fhca7_set_cpu(cpu, false); + + return 1; +} +#endif diff --git a/arch/arm/mach-fh/include/mach/board_config.h b/arch/arm/mach-fh/include/mach/board_config.h new file mode 100644 index 00000000..3d1b0551 --- /dev/null +++ b/arch/arm/mach-fh/include/mach/board_config.h @@ -0,0 +1,44 @@ +#ifndef BOARD_CONFIG_H_ +#define BOARD_CONFIG_H_ + +/* + * GPIO0 -> IRCUT_ON + * GPIO1 -> IRCUT_OFF + * GPIO2 -> USB_PWREN + * GPIO11 -> EMAC PHY Reset + * GPIO12 -> CIS_CLK + * GPIO13 -> CIS_RSTN + * GPIO14 -> CIS_PDN + * GPIO19 -> SD1_PWREN/WIFI_REG_ON + * GPIO20 -> AK7755 Reset + * GPIO24 -> LED0 + * GPIO25 -> LED1 + * GPIO26 -> Reset Configs + * GPIO27 -> AK7755 PowerDown + * GPIO28 -> IR + * GPIO53 -> USB_PWREN/SD0_PWREN + * GPIO55 -> SD1 WIFI Interrupt + */ + +#define CONFIG_SD_CD_FIXED + +#define CONFIG_ISP_CLK_RATE 200000000 +#define CONFIG_JPEG_CLK_RATE 200000000 +#define CONFIG_VEU_CLK_RATE 300000000 + +#define USB_VBUS_PWR_GPIO (47) +#define ETH_GPIO "ETH", "GPIO48", "GPIO49", "GPIO50", "GPIO51", "GPIO52",\ + "GPIO53", "GPIO54", "GPIO55", "GPIO56" + +#define CONFIG_PINCTRL_SELECT \ + "I2C0", "PWM2", "PWM3", "PWM4", "PWM5", "PWM6", "PWM7", \ + "PWM8", "PWM9", "SADC_XAIN0", "SADC_XAIN1", \ + "SADC_XAIN2", "SADC_XAIN3", "SD0_NO_WP", "SD1_NO_WP", \ + "SENSOR_CLK", "SSI0_4BIT", "UART0", "UART1", "GPIO4", \ + "GPIO13", "GPIO14", "GPIO15", ETH_GPIO, \ + "GPIO30", "GPIO31", "GPIO32", "GPIO43", "GPIO44", \ + "GPIO47", \ +\ + "GPIO11", "GPIO16", "GPIO45", "GPIO46" + +#endif /* BOARD_CONFIG_H_ */ diff --git a/arch/arm/mach-fh/include/mach/clock.h b/arch/arm/mach-fh/include/mach/clock.h new file mode 100644 index 00000000..b761ab44 --- /dev/null +++ b/arch/arm/mach-fh/include/mach/clock.h @@ -0,0 +1,59 @@ +#ifndef __FH_CLOCK_H__ +#define __FH_CLOCK_H__ + +#include +#include + +#define CLOCK_MAX_PARENT 4 + +#define OSC_FREQUENCY (24000000) + +#define CLOCK_FIXED (1<<0) +#define CLOCK_NOGATE (1<<1) +#define CLOCK_NODIV (1<<2) +#define CLOCK_NORESET (1<<3) +#define CLOCK_MULTI_PARENT (1<<4) +#define CLOCK_PLL (1<<5) +#define CLOCK_PLL_P (1<<6) +#define CLOCK_PLL_R (1<<7) +#define CLOCK_HIDE (1<<8) +#define CLOCK_CIS (1<<9) +#define CLOCK_PHASE (1<<10) + + +#define CLK(dev, con, ck) \ + { \ + .dev_id = dev, \ + .con_id = con, \ + .clk = ck, \ + } + +struct clk_usr { + char *name; + unsigned long frequency; +}; + + +struct fh_clk { + const char *name; + unsigned long frequency; + unsigned int flag; + int select; + struct fh_clk *parent[CLOCK_MAX_PARENT]; + int prediv; + int divide; + unsigned int div_reg_offset; + unsigned int div_reg_mask; + unsigned int en_reg_offset; + unsigned int en_reg_mask; + unsigned int rst_reg_offset; + unsigned int rst_reg_mask; + unsigned int sel_reg_offset; + unsigned int sel_reg_mask; + unsigned int def_rate; +}; + +extern struct fh_clk *fh_clks[]; +extern int __init fh_clk_init(void); + +#endif diff --git a/arch/arm/mach-fh/include/mach/fh_chipid.h b/arch/arm/mach-fh/include/mach/fh_chipid.h new file mode 100644 index 00000000..6c13d9d6 --- /dev/null +++ b/arch/arm/mach-fh/include/mach/fh_chipid.h @@ -0,0 +1,57 @@ +#ifndef __FH_CHIPID_H__ +#define __FH_CHIPID_H__ + +#define FH_CHIP_FH8830 0x883000A1 +#define FH_CHIP_FH8630M 0x883000B1 +#define FH_CHIP_FH8632 0x863200A1 +#define FH_CHIP_FH8632v2 0x863200A2 +#define FH_CHIP_FH8856 0x885600A1 +#define FH_CHIP_FH8852 0x885600B1 +#define FH_CHIP_FH8626V100 0x8626A100 +#define FH_CHIP_FH8852V200 0x8852A200 +#define FH_CHIP_FH8856V200 0x8856A200 +#define FH_CHIP_FH8858V200 0x8858A200 +#define FH_CHIP_FH8856V201 0x8856A201 +#define FH_CHIP_FH8858V201 0x8858A201 +#define FH_CHIP_FH8852V210 0x8852A210 +#define FH_CHIP_FH8856V210 0x8856A210 +#define FH_CHIP_FH8858V210 0x8858A210 +#define FH_CHIP_FH8652 0x8652A100 +#define FH_CHIP_FH8656 0x8656A100 +#define FH_CHIP_FH8658 0x8658A100 + +struct fh_chip_info +{ + int _plat_id; /* 芯片寄存器中的plat_id */ + int _chip_id; /* 芯片寄存器中的chip_id */ + int _chip_mask; /* 芯片寄存器中的chip_id */ + int chip_id; /* 芯片chip_id，详见上述定义 */ + int ddr_size; /* 芯片DDR大小，单位Mbit */ + char chip_name[32]; /* 芯片名称 */ +}; + +void fh_get_chipid(unsigned int *plat_id, unsigned int *chip_id); +unsigned int fh_get_ddrsize_mbit(void); +char *fh_get_chipname(void); +struct fh_chip_info *fh_get_chip_info(void); + +unsigned int fh_is_8830(void); +unsigned int fh_is_8632(void); +unsigned int fh_is_8852(void); +unsigned int fh_is_8856(void); +unsigned int fh_is_8626v100(void); +unsigned int fh_is_8852v200(void); +unsigned int fh_is_8856v200(void); +unsigned int fh_is_8858v200(void); +unsigned int fh_is_8856v201(void); +unsigned int fh_is_8858v201(void); +unsigned int fh_is_8852v210(void); +unsigned int fh_is_8856v210(void); +unsigned int fh_is_8858v210(void); +unsigned int fh_is_8652(void); +unsigned int fh_is_8656(void); +unsigned int fh_is_8658(void); + +int fh_chipid_init(void); + +#endif diff --git a/arch/arm/mach-fh/include/mach/fh_common.h b/arch/arm/mach-fh/include/mach/fh_common.h new file mode 100644 index 00000000..4b5289f9 --- /dev/null +++ b/arch/arm/mach-fh/include/mach/fh_common.h @@ -0,0 +1,27 @@ +#ifndef __FH_COMMON_H__ +#define __FH_COMMON_H__ + +#include +#include +#include + +/*change the scheduling policy and/or RT priority of `current` thread. */ +void fh_setscheduler(int policy, int priority); + +int fh_clk_enable(struct clk *clk); +unsigned long fh_clk_get_rate(struct clk *clk); +int fh_clk_set_rate(struct clk *clk, unsigned long rate); +int fh_clk_prepare(struct clk *clk); +void fh_clk_disable(struct clk *clk); +void fh_clk_unprepare(struct clk *clk); +int fh_clk_prepare_enable(struct clk *clk); +void fh_clk_disable_unprepare(struct clk *clk); +int fh_clk_set_parent(struct clk *clk, struct clk *parent); +struct clk *fh_clk_get_parent(struct clk *clk); +bool fh_clk_has_parent(struct clk *clk, struct clk *parent); + +unsigned int fh_irq_create_mapping(struct irq_domain *domain, + irq_hw_number_t hwirq); +bool fh_clk_is_enabled(struct clk *clk); + +#endif \ No newline at end of file diff --git a/arch/arm/mach-fh/include/mach/fh_dma_plat.h b/arch/arm/mach-fh/include/mach/fh_dma_plat.h new file mode 100644 index 00000000..989a7e7b --- /dev/null +++ b/arch/arm/mach-fh/include/mach/fh_dma_plat.h @@ -0,0 +1,94 @@ +#ifndef __FH_DMAC_PLAT_H__ +#define __FH_DMAC_PLAT_H__ + +/**************************************************************************** + * #include section + * add #include here if any + ***************************************************************************/ +#include +#include +#include +#include +#include +#include +/**************************************************************************** + * #define section + * add constant #define here if any + ***************************************************************************/ + +#define FH_AXI_DMA_PRINT(fmt, ...) printk(KERN_INFO pr_fmt(fmt), ##__VA_ARGS__) + +#define SOC_CACHE_LINE_SIZE 32 +#define AXI_DMA_NULL (0) +#define AXI_DMA_ASSERT(n) BUG_ON(!(n)) + +#define axi_dma_lock_init(p, name) mutex_init(p) +#define _axi_dma_lock(p, t) mutex_lock(p) +#define axi_dma_unlock(p) mutex_unlock(p) +#define axi_dma_trylock(p) mutex_trylock(p) +#define axi_dma_memset(s, c, cnt) memset(s, c, cnt) +#define axi_dma_malloc(s) kzalloc(s, GFP_KERNEL) +#define axi_dma_free(s) kfree(s) +#define axi_dma_min(d0,d1) min(d0, d1) +#define AXI_DMA_TICK_PER_SEC 100 + + +/**************************************************************************** + * ADT section + * add Abstract Data Type definition here + ***************************************************************************/ +typedef signed char FH_SINT8; +typedef signed short FH_SINT16; +typedef signed int FH_SINT32; +typedef unsigned char FH_UINT8; +typedef unsigned short FH_UINT16; +typedef unsigned int FH_UINT32; +typedef signed int FH_ERR; + +typedef struct mutex axi_dma_lock_t; +typedef struct list_head axi_dma_list; + +#define axi_dma_list_init(n) INIT_LIST_HEAD(n) +#define axi_dma_list_insert_before(to, new) list_add_tail(new, to) +#define axi_dma_list_remove(n) list_del(n) +#define axi_dma_scanf sprintf + + +/** + * struct fh_dma_platform_data - Controller configuration parameters + * @nr_channels: Number of channels supported by hardware (max 8) + * @is_private: The device channels should be marked as private and not for + * by the general purpose DMA channel allocator. + * @chan_allocation_order: Allocate channels starting from 0 or 7 + * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0. + * @block_size: Maximum block size supported by the controller + * @nr_masters: Number of AHB masters supported by the controller + * @data_width: Maximum data width supported by hardware per AHB master + * (0 - 8bits, 1 - 16bits, ..., 5 - 256bits) + * @sd: slave specific data. Used for configuring channels + * @sd_count: count of slave data structures passed. + */ +struct fh_dma_platform_data { + unsigned int nr_channels; + bool is_private; +#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ +#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */ + unsigned char chan_allocation_order; +#define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */ +#define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */ + unsigned char chan_priority; + unsigned short block_size; + unsigned char nr_masters; + unsigned char data_width[4]; + char *clk_name; +}; + + +struct fh_axi_dma_platform_data { +#define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */ +#define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */ + unsigned char chan_priority; + char *clk_name; +}; + +#endif diff --git a/arch/arm/mach-fh/include/mach/fh_dmac_plat.h b/arch/arm/mach-fh/include/mach/fh_dmac_plat.h new file mode 100644 index 00000000..581e06ba --- /dev/null +++ b/arch/arm/mach-fh/include/mach/fh_dmac_plat.h @@ -0,0 +1,44 @@ +/* + * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on + * AVR32 systems.) + * + * Copyright (C) 2007 Atmel Corporation + * Copyright (C) 2010-2011 ST Microelectronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef FH_DMAC_PLAT_H +#define FH_DMAC_PLAT_H + +#include +#ifdef CONFIG_FH_DMAC + +struct fh_dma_platform_data { + unsigned int nr_channels; + bool is_private; +#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ +#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */ + unsigned char chan_allocation_order; +#define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */ +#define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */ + unsigned char chan_priority; + unsigned short block_size; + unsigned char nr_masters; + unsigned char data_width[4]; + char *clk_name; +}; + +#else + +struct fh_axi_dma_platform_data { + //unsigned int nr_channels; +#define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */ +#define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */ + unsigned char chan_priority; + char *clk_name; +}; + +#endif +#endif diff --git a/arch/arm/mach-fh/include/mach/fh_efuse_plat.h b/arch/arm/mach-fh/include/mach/fh_efuse_plat.h new file mode 100644 index 00000000..bf63f460 --- /dev/null +++ b/arch/arm/mach-fh/include/mach/fh_efuse_plat.h @@ -0,0 +1,9 @@ +#ifndef __FH_EFUSE_PLAT_H__ +#define __FH_EFUSE_PLAT_H__ + +struct fh_efuse_platform_data { + u32 efuse_support_flag; + void *optee_uuid; +}; + +#endif \ No newline at end of file diff --git a/arch/arm/mach-fh/include/mach/fh_gmac_plat.h b/arch/arm/mach-fh/include/mach/fh_gmac_plat.h new file mode 100644 index 00000000..7526eac7 --- /dev/null +++ b/arch/arm/mach-fh/include/mach/fh_gmac_plat.h @@ -0,0 +1,10 @@ +#ifndef __FH_GMAC_PLAT_H__ +#define __FH_GMAC_PLAT_H__ + +struct fh_gmac_platform_data { + u32 phy_reset_pin; + u32 speed_switch_pmu_reg; + u32 speed_switch_bit_pos; + u32 speed_switch_100M_val; +}; +#endif \ No newline at end of file diff --git a/arch/arm/mach-fh/include/mach/fh_gpio_plat.h b/arch/arm/mach-fh/include/mach/fh_gpio_plat.h new file mode 100644 index 00000000..fe08911c --- /dev/null +++ b/arch/arm/mach-fh/include/mach/fh_gpio_plat.h @@ -0,0 +1,33 @@ +#ifndef __FH_GPIO_PLAT_H__ +#define __FH_GPIO_PLAT_H__ + +#define GPIO_NAME "FH_GPIO" + +#include + +enum trigger_type { + SOFTWARE, + HARDWARE, +}; + +struct gpio_irq_info { + int irq_gpio; + int irq_line; + int irq_type; + int irq_gpio_val; + int irq_gpio_mode; +}; + +struct fh_gpio_chip { + struct gpio_chip chip; + void __iomem *base; + struct irq_domain *irq_domain; + struct platform_device *pdev; + int irq; + spinlock_t lock; + + enum trigger_type type; + u32 gpio_wakeups; + u32 gpio_backups; +}; +#endif diff --git a/arch/arm/mach-fh/include/mach/fh_i2s_plat.h b/arch/arm/mach-fh/include/mach/fh_i2s_plat.h new file mode 100644 index 00000000..5a530f07 --- /dev/null +++ b/arch/arm/mach-fh/include/mach/fh_i2s_plat.h @@ -0,0 +1,16 @@ +#ifndef __FH_I2S_PLAT_H__ +#define __FH_I2S_PLAT_H__ + +struct fh_i2s_platform_data { + int dma_capture_channel; + int dma_playback_channel; + int dma_master; + int dma_rx_hs_num; + int dma_tx_hs_num; + char *clk; + char *pclk; + char *acodec_pclk; + char *acodec_mclk; +}; + +#endif diff --git a/arch/arm/mach-fh/include/mach/fh_l2mem.h b/arch/arm/mach-fh/include/mach/fh_l2mem.h new file mode 100644 index 00000000..f2888f23 --- /dev/null +++ b/arch/arm/mach-fh/include/mach/fh_l2mem.h @@ -0,0 +1,17 @@ +#ifndef __MACH_L2MEM_H +#define __MACH_L2MEM_H + +/* + * L2MEM allocations return a CPU virtual address, or NULL on error. + * If a DMA address is requested and the L2MEM supports DMA, its + * mapped address is also returned. + * + * Errors include L2MEM memory not being available, and requesting + * DMA mapped L2MEM on systems which don't allow that. + */ + +extern void *l2mem_alloc(size_t len); +extern void *l2mem_dma_alloc(size_t len, dma_addr_t *dma); +extern void l2mem_free(void *addr, size_t len); + +#endif /* __MACH_SRAL2MEM*/ diff --git a/arch/arm/mach-fh/include/mach/fh_mci_plat.h b/arch/arm/mach-fh/include/mach/fh_mci_plat.h new file mode 100644 index 00000000..910595fc --- /dev/null +++ b/arch/arm/mach-fh/include/mach/fh_mci_plat.h @@ -0,0 +1,79 @@ +#ifndef __FH_MCI_PLAT_H__ +#define __FH_MCI_PLAT_H__ + +struct fhmci_des { + unsigned long idmac_des_ctrl; + unsigned long idmac_des_buf_size; + unsigned long idmac_des_buf_addr; + unsigned long idmac_des_next_addr; +}; + +struct fhmci_host { + struct mmc_host *mmc; + spinlock_t lock; + struct mmc_request *mrq; + struct mmc_command *cmd; + struct mmc_data *data; + void __iomem *base; + unsigned int card_status; + struct scatterlist *dma_sg; + unsigned int dma_sg_num; + unsigned int dma_alloc_size; + unsigned int dma_dir; + dma_addr_t dma_paddr; + unsigned int *dma_vaddr; + struct timer_list timer; + unsigned int irq; + unsigned int irq_status; + unsigned int is_tuning; + wait_queue_head_t intr_wait; + unsigned long pending_events; + unsigned int id; + struct fh_mci_board *pdata; + int fifo_depth; + unsigned int bus_hz; + unsigned int (*get_cd)(struct fhmci_host *host); + unsigned int (*get_ro)(struct fhmci_host *host); +#define FHMCI_PEND_DTO_b (0) +#define FHMCI_PEND_DTO_m (1 << FHMCI_PEND_DTO_b) + char isr_name[10]; +}; + +/* Board platform data */ +struct fh_mci_board { + unsigned int num_slots; + + unsigned int quirks; /* Workaround / Quirk flags */ + unsigned int bus_hz; /* Bus speed */ + + unsigned int caps; /* Capabilities */ + + /* delay in mS before detecting cards after interrupt */ + unsigned int detect_delay_ms; + + int (*init)(unsigned int slot_id, void *irq_handler_t, void *); + unsigned int (*get_ro)(struct fhmci_host *host); + unsigned int (*get_cd)(struct fhmci_host *host); + int (*get_ocr)(unsigned int slot_id); + int (*get_bus_wd)(unsigned int slot_id); + /* + * Enable power to selected slot and set voltage to desired level. + * Voltage levels are specified using MMC_VDD_xxx defines defined + * in linux/mmc/host.h file. + */ + void (*setpower)(unsigned int slot_id, unsigned int volt); + void (*exit)(unsigned int slot_id); + void (*select_slot)(unsigned int slot_id); + + struct dw_mci_dma_ops *dma_ops; + struct dma_pdata *data; + struct block_settings *blk_settings; + int fifo_depth; + int drv_degree; + int sam_degree; + /*if rescan_max_num = 0 scan all times*/ + unsigned int rescan_max_num; +}; + +#endif + diff --git a/arch/arm/mach-fh/include/mach/fh_predefined.h b/arch/arm/mach-fh/include/mach/fh_predefined.h new file mode 100644 index 00000000..2e29254a --- /dev/null +++ b/arch/arm/mach-fh/include/mach/fh_predefined.h @@ -0,0 +1,33 @@ +#ifndef FH_PREDEFINED_H_ +#define FH_PREDEFINED_H_ + +typedef unsigned char UINT8; +typedef unsigned short UINT16; +typedef unsigned int UINT32; +typedef unsigned long long UINT64; + +typedef char SINT8; +typedef short SINT16; +typedef int SINT32; +typedef long long SINT64; +#define FALSE (0) +#define TRUE (!FALSE) +#define reg_read(addr) (*((volatile UINT32 *)(addr))) +#define reg_write(addr,value) (*(volatile UINT32 *)(addr)=(value)) + +#define GET_REG(addr) reg_read(addr) +#define SET_REG(addr,value) reg_write(addr,value) +#define SET_REG_M(addr,value,mask) reg_write(addr,(reg_read(addr)&(~(mask)))|((value)&(mask))) +#define SET_REG_B(addr,element,highbit,lowbit) SET_REG_M((addr),((element)<<(lowbit)),(((1<<((highbit)-(lowbit)+1))-1)<<(lowbit))) + +#define GET_REG8(addr) (*((volatile UINT8 *)(addr))) +#define SET_REG8(addr,value) (*(volatile UINT8 *)(addr)=(value)) + +#define LD8(addr) (*((volatile u8 *)(addr))) +#define ST8(addr,value) (*(volatile u8 *)(addr)=(value)) +#define LD16(addr) (*((volatile u16 *)(addr))) +#define ST16(addr,value) (*(volatile u16 *)(addr)=(value)) +#define LD32(addr) (*((volatile u32 *)(addr))) +#define ST32(addr,value) (*(volatile u32 *)(addr)=(value)) + +#endif /* FH_PREDEFINED_H_ */ diff --git a/arch/arm/mach-fh/include/mach/fh_pwm_plat.h b/arch/arm/mach-fh/include/mach/fh_pwm_plat.h new file mode 100644 index 00000000..22c06b1f --- /dev/null +++ b/arch/arm/mach-fh/include/mach/fh_pwm_plat.h @@ -0,0 +1,9 @@ +#ifndef __FH_PWM_PLAT_H__ +#define __FH_PWM_PLAT_H__ + +struct fh_pwm_data +{ + unsigned int npwm; +}; + +#endif diff --git a/arch/arm/mach-fh/include/mach/fh_rtc_plat.h b/arch/arm/mach-fh/include/mach/fh_rtc_plat.h new file mode 100644 index 00000000..33ed0330 --- /dev/null +++ b/arch/arm/mach-fh/include/mach/fh_rtc_plat.h @@ -0,0 +1,11 @@ +#ifndef __FH_RTC_PLAT_H__ +#define __FH_RTC_PLAT_H__ + +struct fh_rtc_plat_data { + int lut_cof; + int lut_offset; + int tsensor_cp_default_out; + char *clk_name; +}; + +#endif diff --git a/arch/arm/mach-fh/include/mach/fh_sadc_plat.h b/arch/arm/mach-fh/include/mach/fh_sadc_plat.h new file mode 100644 index 00000000..70b75a57 --- /dev/null +++ b/arch/arm/mach-fh/include/mach/fh_sadc_plat.h @@ -0,0 +1,8 @@ +#ifndef __FH_SADC_PLAT_H__ +#define __FH_SADC_PLAT_H__ + +struct fh_sadc_platform_data { + u32 ref_vol; + u32 active_bit; +}; +#endif diff --git a/arch/arm/mach-fh/include/mach/fh_spi_plat.h b/arch/arm/mach-fh/include/mach/fh_spi_plat.h new file mode 100644 index 00000000..a54c934d --- /dev/null +++ b/arch/arm/mach-fh/include/mach/fh_spi_plat.h @@ -0,0 +1,59 @@ +#ifndef __FH_SPI_PLAT_H__ +#define __FH_SPI_PLAT_H__ + +#include +#include + +/**************************************************************************** +* #define section +* add constant #define here if any +***************************************************************************/ +#define SPI_MASTER_CONTROLLER_MAX_SLAVE 2 +#define SPI_TRANSFER_USE_DMA (0x77888877) +#define SPI_DMA_PROTCTL_ENABLE (0x55) +#define SPI_DMA_MASTER_SEL_ENABLE (0x55) +/**************************************************************************** +* ADT section +* add Abstract Data Type definition here +***************************************************************************/ + +struct fh_spi_cs { + u32 GPIO_Pin; + char *name; +}; + + + +#define ONE_WIRE_SUPPORT (1<<0) +#define DUAL_WIRE_SUPPORT (1<<1) +#define QUAD_WIRE_SUPPORT (1<<2) +#define MULTI_WIRE_SUPPORT (1<<8) + +struct fh_spi_platform_data { + u32 apb_clock_in; + u32 slave_max_num; + u32 clock_source[8]; + u32 clock_source_num; + u32 clock_in_use; + struct fh_spi_cs cs_data[SPI_MASTER_CONTROLLER_MAX_SLAVE]; + u32 bus_no; + char *clk_name; + char *hclk_name; + char *pclk_name; + /* add support wire width*/ + u32 ctl_wire_support; + /* add dma para*/ + /*use dma, but need menuconfig open*/ + u32 dma_transfer_enable; + /*related soc*/ + u32 rx_handshake_num; + u32 dma_protctl_enable; + u32 rx_dma_channel; + u32 dma_protctl_data; + u32 dma_master_sel_enable; + u32 dma_master_ctl_sel; + u32 dma_master_mem_sel; +}; + + +#endif diff --git a/arch/arm/mach-fh/include/mach/fh_uart_plat.h b/arch/arm/mach-fh/include/mach/fh_uart_plat.h new file mode 100644 index 00000000..2be1e277 --- /dev/null +++ b/arch/arm/mach-fh/include/mach/fh_uart_plat.h @@ -0,0 +1,47 @@ +#ifndef __FH_UART_PLAT_H__ +#define __FH_UART_PLAT_H__ + +#include +#include +#include +#include +#include + +struct fh_uart_dma_transfer { + struct dma_chan *chan; + struct dma_slave_config cfg; + struct scatterlist sgl[128]; + unsigned int sgl_data_size[128]; + unsigned int actual_sgl_size; + struct dma_async_tx_descriptor *desc; +}; + +struct fh_uart_dma { + u32 tx_dumy_buff[128]; + u8 rx_dumy_buff[128]; + u32 tx_dma_add; + u32 rx_dma_add; + u32 tx_hs_no; + u32 rx_hs_no; + u32 tx_dma_channel; + u32 rx_dma_channel; + u32 tx_count; + u32 tx_done; + u32 paddr; + u32 rx_xmit_len; + u32 inited; + struct completion rx_cmp; + struct fh_uart_dma_transfer dma_rx; + struct fh_uart_dma_transfer dma_tx; +}; + +struct fh_platform_uart { + unsigned long mapbase; /* Physical address base */ + unsigned int fifo_size; /* UART FIFO SIZE */ + unsigned int irq; /* Interrupt vector */ + unsigned int uartclk; /* UART clock rate */ + unsigned int use_dma; + struct fh_uart_dma *dma_info; +}; + +#endif \ No newline at end of file diff --git a/arch/arm/mach-fh/include/mach/fh_usb_plat.h b/arch/arm/mach-fh/include/mach/fh_usb_plat.h new file mode 100644 index 00000000..e49f4ed5 --- /dev/null +++ b/arch/arm/mach-fh/include/mach/fh_usb_plat.h @@ -0,0 +1,9 @@ +#ifndef __FH_USB_PLAT_H__ +#define __FH_USB_PLAT_H__ + +struct fh_usb_platform_data { + char *dr_mode; + unsigned int vbus_pwren; +}; + +#endif diff --git a/arch/arm/mach-fh/include/mach/fh_wdt_plat.h b/arch/arm/mach-fh/include/mach/fh_wdt_plat.h new file mode 100644 index 00000000..4db09692 --- /dev/null +++ b/arch/arm/mach-fh/include/mach/fh_wdt_plat.h @@ -0,0 +1,11 @@ +#ifndef __FH_WDT_PLAT_H__ +#define __FH_WDT_PLAT_H__ + +struct fh_wdt_platform_data { + int mode; +#define MODE_CONTINUOUS 0 +#define MODE_DISCRETE 1 +}; + +#endif + diff --git a/arch/arm/mach-fh/include/mach/io.h b/arch/arm/mach-fh/include/mach/io.h new file mode 100644 index 00000000..80caae76 --- /dev/null +++ b/arch/arm/mach-fh/include/mach/io.h @@ -0,0 +1,26 @@ +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +/* + * We don't actually have real ISA nor PCI buses, but there is so many + * drivers out there that might just work if we fake them... + */ +#define __mem_pci(a) (a) +#define __mem_isa(a) (a) + +#define FH_VIRT 0xFE000000 + +#define VA_INTC_REG_BASE (FH_VIRT + 0x00000) +#define VA_TIMER_REG_BASE (FH_VIRT + 0x10000) +#define VA_UART0_REG_BASE (FH_VIRT + 0x20000) +#define VA_PMU_REG_BASE (FH_VIRT + 0x90000) +#define VA_UART1_REG_BASE (FH_VIRT + 0xa0000) +#define VA_UART2_REG_BASE (FH_VIRT + 0xb0000) +#define VA_UART3_REG_BASE (FH_VIRT + 0xc0000) + +#define VA_RAM_REG_BASE (FH_VIRT + 0xd0000) +#define VA_DDRC_REG_BASE (FH_VIRT + 0xe0000) + +#define VA_CONSOLE_REG_BASE VA_UART0_REG_BASE + +#endif /* __ASM_ARCH_IO_H */ diff --git a/arch/arm/mach-fh/include/mach/pinctrl.h b/arch/arm/mach-fh/include/mach/pinctrl.h new file mode 100644 index 00000000..56653744 --- /dev/null +++ b/arch/arm/mach-fh/include/mach/pinctrl.h @@ -0,0 +1,158 @@ +#ifndef PINCTRL_H_ +#define PINCTRL_H_ +#include "pinctrl_osdep.h" +#include + +#define MSC_3_3V (0) +#define MSC_1_8V (1) + +#define PINCTRL_UNUSED (-1) + +#define PUPD_NONE (0) +#define PUPD_UP (1) +#define PUPD_DOWN (2) + +#define INPUT_DISABLE (0) +#define INPUT_ENABLE (1) +#define OUTPUT_DISABLE (0) +#define OUTPUT_ENABLE (1) + +#if defined(CONFIG_MACH_FH8626V100) +#define PUPD_DISABLE (1) +#define PUPD_ENABLE (0) +#define PUPD_ZERO (0) +#else +#define PUPD_DISABLE (0) +#define PUPD_ENABLE (1) +#define PUPD_ZERO (0) +#endif + +#define FUNC0 (0) +#define FUNC1 (1) +#define FUNC2 (2) +#define FUNC3 (3) +#define FUNC4 (4) +#define FUNC5 (5) +#define FUNC6 (6) +#define FUNC7 (7) +#define FUNC8 (8) +#define FUNC9 (9) + + +#define NEED_CHECK_PINLIST (1) +#define PIN_BACKUP (1<<1) +#define PIN_RESTORE (1<<2) + +#define PINCTRL_FUNC(name, id, sel, pupd, ds) \ +PinCtrl_Pin PAD##id##_##name = \ +{ \ + .pad_id = id, \ + .func_name = #name, \ + .reg_offset = (id * 4), \ + .func_sel = sel, \ + .pullup_pulldown = pupd, \ + .driving_curr = ds, \ + .output_enable = 1, \ +} + +#define PARA_COUNT_N(_1, _2, _3, _4, _5, _6, _7, _8, _9, N, ...) N +#define PARA_COUNT(...) \ + PARA_COUNT_N(0, ##__VA_ARGS__, 8, 7, 6, 5, 4, 3, 2, 1, 0) + +#define PINCTRL_MUX(pname, sel, ...) \ +struct PinCtrl_Mux_##pname \ +{ \ + int cur_pin:16; \ + int mux_num:16; \ + PinCtrl_Pin *mux_pin[PARA_COUNT(__VA_ARGS__)]; \ +} MUX_##pname = \ +{ \ + .mux_pin = { __VA_ARGS__ }, \ + .cur_pin = sel, \ + .mux_num = PARA_COUNT(__VA_ARGS__), \ +}; + +#define PINCTRL_DEVICE(name, count, ...) \ +typedef struct \ +{ \ + char *dev_name; \ + int mux_count; \ + OS_LIST list; \ + void *mux[count]; \ +} PinCtrl_Device_##name; \ +PinCtrl_Device_##name pinctrl_dev_##name = \ +{ \ + .dev_name = #name, \ + .mux_count = count, \ + .mux = { __VA_ARGS__ }, \ +} + +typedef union { + struct { + unsigned int sl : 1; /*0*/ + unsigned int : 3; /*1~3*/ + unsigned int ds : 3; /*4~6*/ + unsigned int msc : 1; /*7*/ + unsigned int st : 1; /*8*/ + unsigned int : 3; /*9~11*/ + unsigned int ie : 1; /*12*/ + unsigned int : 3; /*13~15*/ + unsigned int pdn : 1; /*16*/ + unsigned int : 3; /*17~19*/ + unsigned int pun : 1; /*20*/ + unsigned int : 3; /*21~23*/ + unsigned int mfs : 4; /*24~27*/ + unsigned int oe : 1; /*28*/ + unsigned int : 3; /*29~31*/ + } bit; + unsigned int dw; +} PinCtrl_Register; + +typedef struct +{ + char *func_name; + PinCtrl_Register *reg; + unsigned int pad_id : 8; + unsigned int reg_offset : 12; + unsigned int func_sel : 4; + unsigned int input_enable : 1; + unsigned int output_enable : 1; + unsigned int pullup_pulldown : 2; + unsigned int volt_mode : 1; + unsigned int driving_curr : 3; +}PinCtrl_Pin; + +typedef struct +{ + int cur_pin:16; + int mux_num:16; + PinCtrl_Pin *mux_pin[0]; +} PinCtrl_Mux; + +typedef struct +{ + void *vbase; + void *pbase; + PinCtrl_Pin *pinlist[PAD_NUM]; +} PinCtrl_Object; + +typedef struct +{ + char *dev_name; + int mux_count; + OS_LIST list; + void *mux; +}PinCtrl_Device; + +void fh_pinctrl_init(unsigned int base); +void fh_pinctrl_prt(struct seq_file *sfile); +int fh_pinctrl_smux(char *devname, char* muxname, int muxsel, unsigned int flag); +int fh_pinctrl_sdev(char *devname, unsigned int flag); +int fh_pinctrl_spupd(char *pin_name, unsigned int pupd); +int fh_pinctrl_sds(char *pin_name, unsigned int ds); +int fh_pinctrl_set_oe(char *pin_name, unsigned int oe); +void fh_pinctrl_init_devicelist(OS_LIST *list); +char *fh_pinctrl_smux_backup(char *devname, char *muxname, int muxsel); +char *fh_pinctrl_smux_restore(char *devname, char *muxname, int muxsel); + +#endif /* PINCTRL_H_ */ diff --git a/arch/arm/mach-fh/include/mach/pinctrl_osdep.h b/arch/arm/mach-fh/include/mach/pinctrl_osdep.h new file mode 100644 index 00000000..52cec934 --- /dev/null +++ b/arch/arm/mach-fh/include/mach/pinctrl_osdep.h @@ -0,0 +1,21 @@ +#ifndef PINCTRL_OSDEP_H_ +#define PINCTRL_OSDEP_H_ + +#include +#include +#include +#include + +#define OS_LIST_INIT LIST_HEAD_INIT +#define OS_LIST struct list_head +#define OS_PRINT printk +#define OS_LIST_EMPTY INIT_LIST_HEAD +#define OS_NULL NULL + +#define PINCTRL_ADD_DEVICE(name) \ + list_add(&pinctrl_dev_##name.list, \ + list) + +#define PAD_NUM (77) + +#endif /* PINCTRL_OSDEP_H_ */ diff --git a/arch/arm/mach-fh/include/mach/pmu.h b/arch/arm/mach-fh/include/mach/pmu.h new file mode 100644 index 00000000..216152c1 --- /dev/null +++ b/arch/arm/mach-fh/include/mach/pmu.h @@ -0,0 +1,43 @@ +#ifndef _FH_PMU_H_ +#define _FH_PMU_H_ + +#include +#include + +#include "chip.h" + +void fh_get_chipid(unsigned int *plat_id, unsigned int *chip_id); +unsigned int fh_pmu_get_ptsl(void); +unsigned int fh_pmu_get_ptsh(void); +unsigned long long fh_get_pts64(void); +void fh_pmu_wdt_pause(void); +void fh_pmu_wdt_resume(void); +void fh_pmu_usb_utmi_rst(void); +void fh_pmu_usb_phy_rst(void); +void fh_pmu_usb_resume(void); + +unsigned int fh_pmu_get_tsensor_init_data(void); +unsigned int fh_pmu_get_ddrsize(void); +void fh_pmu_set_sdc1_funcsel(unsigned int val); + +void fh_pmu_sdc_reset(int slot_id); +void fh_pmu_mipi_reset(void); +void fh_pmu_enc_reset(void); +void fh_pmu_dwi2s_set_clk(unsigned int div_i2s, unsigned int div_mclk); +void fh_pmu_eth_set_speed(unsigned int speed); +void fh_pmu_eth_reset(void); +void fh_pmu_restart(void); + +int fh_pmu_internal_ephy_reset(void); +void fh_pmu_ephy_sel(__u32 phy_sel); +void fh_pmu_arxc_write_A625_INT_RAWSTAT(unsigned int val); +unsigned int fh_pmu_arxc_read_ARM_INT_RAWSTAT(void); +void fh_pmu_arxc_write_ARM_INT_RAWSTAT(unsigned int val); +unsigned int fh_pmu_arxc_read_ARM_INT_STAT(void); +void fh_pmu_arxc_reset(unsigned long phy_addr); +void fh_pmu_arxc_kickoff(void); + +int fh_pmu_init(void); + + +#endif /* _FH_PMU_H_ */ diff --git a/arch/arm/mach-fh/pinctrl.c b/arch/arm/mach-fh/pinctrl.c new file mode 100644 index 00000000..ec867a4f --- /dev/null +++ b/arch/arm/mach-fh/pinctrl.c @@ -0,0 +1,469 @@ +#include +#include +#include +#include + +#include "iopad.h" +#include "chip.h" + +/* #define FH_PINCTRL_DEBUG */ +#ifdef FH_PINCTRL_DEBUG +#define PRINT_DBG(fmt,args...) OS_PRINT(fmt,##args) +#else +#define PRINT_DBG(fmt,args...) do{} while(0) +#endif + +static PinCtrl_Object pinctrl_obj; +OS_LIST fh_pinctrl_devices = OS_LIST_INIT(fh_pinctrl_devices); + +static void fh_pinctrl_check_duplicate_pin(PinCtrl_Pin *pin, int start_pad) +{ + int i; + PinCtrl_Pin *p; + if (!pin) + return; + for (i = start_pad; i < PAD_NUM; i++) { + p = pinctrl_obj.pinlist[i]; + if (p && p != pin && !strcmp(pin->func_name, p->func_name)) { + OS_PRINT("WARNING: %s already exists in pad %d\n", + p->func_name, p->pad_id); + } + } +} + +static int fh_pinctrl_func_select(PinCtrl_Pin *pin, unsigned int flag) +{ + unsigned int reg; + + if (!pin) + { + OS_PRINT("ERROR: pin is null\n\n"); + return -1; + } + + if (flag & NEED_CHECK_PINLIST) + { + if (pinctrl_obj.pinlist[pin->pad_id]) + { + OS_PRINT("ERROR: pad %d has already been set\n\n", pin->pad_id); + return -2; + } + } + fh_pinctrl_check_duplicate_pin(pin, 0); + + reg = GET_REG(pinctrl_obj.vbase + pin->reg_offset); + + pin->reg = (PinCtrl_Register *)® + + pin->reg->bit.mfs = pin->func_sel; + + if (pin->pullup_pulldown == PUPD_DOWN) { + pin->reg->bit.pun = PUPD_DISABLE; + pin->reg->bit.pdn = PUPD_ENABLE; + } + else if(pin->pullup_pulldown == PUPD_UP) { + pin->reg->bit.pun = PUPD_ENABLE; + pin->reg->bit.pdn = PUPD_DISABLE; + } else { + pin->reg->bit.pdn = PUPD_ZERO; + pin->reg->bit.pun = PUPD_ZERO; + } + + pin->reg->bit.ds = pin->driving_curr; + pin->reg->bit.st = 1; + + pin->reg->bit.ie = 1; + pin->reg->bit.oe = pin->output_enable; + + SET_REG(pinctrl_obj.vbase + pin->reg_offset, pin->reg->dw); + + pinctrl_obj.pinlist[pin->pad_id] = pin; + + return 0; +} + +static int fh_pinctrl_mux_switch(PinCtrl_Mux *mux, unsigned int flag) +{ + if (mux->cur_pin >= mux->mux_num) { + OS_PRINT("ERROR: selected function is not exist, sel_func=%d\n\n", mux->cur_pin); + return -3; + } + + if (!mux->mux_pin[mux->cur_pin]) { + OS_PRINT("ERROR: %s mux->mux_pin[%d] has no pin\n\n", + mux->mux_pin[0]->func_name, mux->cur_pin); + return -4; + } + + PRINT_DBG("\t%s[%d]\n", mux->mux_pin[mux->cur_pin]->func_name, mux->cur_pin); + return fh_pinctrl_func_select(mux->mux_pin[mux->cur_pin], flag); +} + + +static int fh_pinctrl_device_switch(PinCtrl_Device *dev, unsigned int flag) +{ + int i, ret; + + for (i = 0; i < dev->mux_count; i++) { + unsigned int *mux_addr = (unsigned int *)((unsigned int)dev + + sizeof(*dev) - 4 + i*4); + PinCtrl_Mux *mux = (PinCtrl_Mux *)(*mux_addr); + + ret = fh_pinctrl_mux_switch(mux, flag); + if (ret) + return ret; + } + +#if defined(CONFIG_ARCH_FH885xV200) ||\ + defined(CONFIG_ARCH_FH865x) || \ + defined(CONFIG_ARCH_FH8636) || \ + defined(CONFIG_ARCH_FH8852V101) + if (strncmp(dev->dev_name, "SD1", 3) == 0) { + PinCtrl_Mux *mux = (PinCtrl_Mux *)dev->mux; + +#if defined(CONFIG_ARCH_FH8636) || defined(CONFIG_ARCH_FH8852V101) + static int sd1_func_map[] = {1, 0, 2}; /* func sel map */ +#else + static int sd1_func_map[] = {0, 1, 2, 3}; /* func sel map */ +#endif + /* for some platform, set SD1_FUNC_SEL after all mux switch */ + SET_REG(VA_PMU_REG_BASE + REG_PMU_SD1_FUNC_SEL, + sd1_func_map[mux->cur_pin]); + } +#endif + return 0; +} + +static PinCtrl_Device * fh_pinctrl_get_device_by_name(char *name) +{ + PinCtrl_Device *dev = OS_NULL; + + list_for_each_entry(dev, &fh_pinctrl_devices, list) + { + if (!strcmp(name, dev->dev_name)) + { + return dev; + } + } + + return 0; +} + +static PinCtrl_Mux *fh_pinctrl_get_mux_by_name(char *mux_name) +{ + int i; + PinCtrl_Device *dev; + + list_for_each_entry(dev, &fh_pinctrl_devices, list) { + for (i = 0; i < dev->mux_count; i++) { + unsigned int *mux_addr = (unsigned int *)( + (unsigned int)dev + sizeof(*dev) - 4 + i*4); + PinCtrl_Mux *mux = (PinCtrl_Mux *)(*mux_addr); + + if (!strcmp(mux_name, mux->mux_pin[0]->func_name)) + return mux; + } + } + + return NULL; +} + +int fh_pinctrl_check_pinlist(void) +{ + int i; + + for (i=0; idev_name); + ret = fh_pinctrl_device_switch(dev, flag); + PRINT_DBG("\n"); + if (ret) + return ret; + + } + + fh_pinctrl_check_pinlist(); + + return 0; + +} + +static void fh_pinctrl_init_pin(void) +{ + int i; + + for (i = 0; i < PAD_NUM; i++) + { + PinCtrl_Pin *pin = pinctrl_obj.pinlist[i]; + + if (!pin) { + PinCtrl_Register reg; + + PRINT_DBG("ERROR: pad %d is empty\n", i); + reg.dw = GET_REG(pinctrl_obj.vbase + i * 4); + reg.bit.ie = 0; + reg.bit.oe = 0; + SET_REG(pinctrl_obj.vbase + i * 4, reg.dw); + continue; + } + pin->reg->dw = GET_REG(pinctrl_obj.vbase + + pin->reg_offset); + + pin->input_enable = pin->reg->bit.ie; + pin->output_enable = pin->reg->bit.oe; + } +} + +void fh_pinctrl_init(unsigned int base) +{ + pinctrl_obj.vbase = pinctrl_obj.pbase = (void *)base; + + fh_pinctrl_init_devicelist(&fh_pinctrl_devices); + fh_pinctrl_init_devices(fh_pinctrl_selected_devices, + ARRAY_SIZE(fh_pinctrl_selected_devices), + NEED_CHECK_PINLIST); + fh_pinctrl_init_pin(); + +#if defined(CONFIG_ARCH_FH885xV200) ||\ + defined(CONFIG_ARCH_FH865x) + { + int boot_mode = GET_REG(VA_PMU_REG_BASE + REG_PMU_BOOT_MODE); + + /* REG_PMU_RESERVED0=4, boot from emmc */ + if (boot_mode == 4) + fh_pinctrl_sdev("SD1_EMMC", 0); + } +#endif +} + +void fh_pinctrl_prt(struct seq_file *sfile) +{ + int i; + static char *pupds[3] = { + [PUPD_NONE] = "none", + [PUPD_UP] = "up", + [PUPD_DOWN] = "down", + }; + + seq_printf(sfile, "%2s\t%8s\t%4s\t%8s\t%4s\t%4s\t%4s\t%4s\t%4s\n", + "id", "name", "addr", "reg", "sel", "ie", "oe", "pupd", "ds"); + for (i = 0; i < PAD_NUM; i++) { + if (!pinctrl_obj.pinlist[i]) { + OS_PRINT("ERROR: pad %d is empty\n", i); + continue; + } + fh_pinctrl_check_duplicate_pin(pinctrl_obj.pinlist[i], i+1); + seq_printf(sfile, "%02d\t%8s\t0x%04x\t0x%08x\t%04d\t%04d\t%04d\t%4s\t%04d\n", + pinctrl_obj.pinlist[i]->pad_id, + pinctrl_obj.pinlist[i]->func_name, + pinctrl_obj.pinlist[i]->reg_offset + 0x80, + GET_REG(pinctrl_obj.vbase + pinctrl_obj.pinlist[i]->reg_offset), + pinctrl_obj.pinlist[i]->func_sel, + pinctrl_obj.pinlist[i]->input_enable, + pinctrl_obj.pinlist[i]->output_enable, + pupds[pinctrl_obj.pinlist[i]->pullup_pulldown], + pinctrl_obj.pinlist[i]->driving_curr); + } + +} +EXPORT_SYMBOL(fh_pinctrl_prt); + + +int fh_pinctrl_smux(char *devname, char* muxname, int muxsel, unsigned int flag) +{ + PinCtrl_Device *dev; + int i, ret; + PinCtrl_Mux *foundmux = NULL; + char *oldfunc = NULL; + + if (flag & PIN_RESTORE) { + foundmux = fh_pinctrl_get_mux_by_name(muxname); + if (foundmux == NULL) { + OS_PRINT("ERROR: PIN_RESTORE, cannot found mux: %s\n", + muxname); + return -10; + } + goto mux_switch; + } + + dev = fh_pinctrl_get_device_by_name(devname); + + if (!dev) { + OS_PRINT("ERROR: cannot find device %s\n", devname); + return -4; + } + + for (i = 0; i < dev->mux_count; i++) { + unsigned int *mux_addr = (unsigned int *)((unsigned int)dev + + sizeof(*dev) - 4 + i*4); + PinCtrl_Mux *mux = (PinCtrl_Mux *)(*mux_addr); + + if (!strcmp(muxname, mux->mux_pin[0]->func_name)) { + foundmux = mux; + mux->cur_pin = muxsel; + goto mux_switch; + } + } + + if (i == dev->mux_count) { + OS_PRINT("ERROR: cannot find mux %s of device %s\n", + muxname, devname); + return -6; + } + +mux_switch: + if (flag & PIN_BACKUP) { + int id = foundmux->mux_pin[foundmux->cur_pin]->pad_id; + PinCtrl_Pin *pin = pinctrl_obj.pinlist[id]; + + if (pin == NULL) { + OS_PRINT("ERROR: PIN_BACKUP, oldpin is null\n"); + return 0; + } + oldfunc = pin->func_name; + } + ret = fh_pinctrl_mux_switch(foundmux, flag); + if (flag & PIN_BACKUP) + ret = (int)oldfunc; + + fh_pinctrl_check_pinlist(); + + return ret; +} +EXPORT_SYMBOL(fh_pinctrl_smux); + +char *fh_pinctrl_smux_backup(char *devname, char *muxname, int muxsel) +{ + return (char *)fh_pinctrl_smux(devname, muxname, muxsel, PIN_BACKUP); +} + +char *fh_pinctrl_smux_restore(char *devname, char *muxname, int muxsel) +{ + return (char *)fh_pinctrl_smux(devname, muxname, muxsel, PIN_RESTORE); +} + +EXPORT_SYMBOL(fh_pinctrl_smux_backup); +EXPORT_SYMBOL(fh_pinctrl_smux_restore); + + +int fh_pinctrl_sdev(char *devname, unsigned int flag) +{ + PinCtrl_Device *dev; + int ret; + + dev = fh_pinctrl_get_device_by_name(devname); + if (!dev) { + OS_PRINT("ERROR: cannot find device %s\n", devname); + return -7; + } + + OS_PRINT("%s:\n", dev->dev_name); + ret = fh_pinctrl_device_switch(dev, flag); + OS_PRINT("\n"); + if (ret) + return ret; + + fh_pinctrl_check_pinlist(); + + return 0; +} +EXPORT_SYMBOL(fh_pinctrl_sdev); + +static PinCtrl_Pin *fh_pinctrl_get_pin_by_name(char *pin_name) +{ + int i; + PinCtrl_Pin *pin = NULL; + + for (i = 0; i < PAD_NUM; i++) { + pin = pinctrl_obj.pinlist[i]; + if (!pin || !pin->func_name) + continue; + if (!strcmp(pin->func_name, pin_name)) + return pin; + } + + return NULL; +} + +int fh_pinctrl_spupd(char *pin_name, unsigned int pupd) +{ + PinCtrl_Pin *pin = NULL; + + pin = fh_pinctrl_get_pin_by_name(pin_name); + + if (!pin) { + OS_PRINT("ERROR: cannot find pin %s\n", pin_name); + return -ENXIO; + } + + pin->pullup_pulldown = pupd; + return fh_pinctrl_func_select(pin, 0); +} +EXPORT_SYMBOL(fh_pinctrl_spupd); + +int fh_pinctrl_sds(char *pin_name, unsigned int ds) +{ + PinCtrl_Pin *pin = NULL; + + if (ds > 7) { + OS_PRINT("ds val is in [0-7]\n"); + return -EINVAL; + } + + pin = fh_pinctrl_get_pin_by_name(pin_name); + + if (!pin) { + OS_PRINT("ERROR: cannot find pin %s\n", pin_name); + return -ENXIO; + } + + pin->driving_curr = ds; + return fh_pinctrl_func_select(pin, 0); +} +EXPORT_SYMBOL(fh_pinctrl_sds); + +int fh_pinctrl_set_oe(char *pin_name, unsigned int oe) +{ + PinCtrl_Pin *pin = NULL; + + if (oe > 1) { + OS_PRINT("oe is 0 or 1\n"); + return -1; + } + + pin = fh_pinctrl_get_pin_by_name(pin_name); + + if (!pin) { + OS_PRINT("ERROR: cannot find pin %s\n", pin_name); + return -2; + } + + pin->output_enable = oe; + return fh_pinctrl_func_select(pin, 0); +} +EXPORT_SYMBOL(fh_pinctrl_set_oe); diff --git a/arch/arm/mach-fh/platsmp.c b/arch/arm/mach-fh/platsmp.c new file mode 100644 index 00000000..935ae4e7 --- /dev/null +++ b/arch/arm/mach-fh/platsmp.c @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2013 Linaro Ltd. + * Copyright (c) 2013 Hisilicon Limited. + * Based on arch/arm/mach-vexpress/platsmp.c, Copyright (C) 2002 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + */ +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "core.h" + +static void __iomem *ctrl_base; +static int use_emc; + + +void fhca7_set_cpu_jump(int cpu, void *jump_addr) +{ + cpu = cpu_logical_map(cpu); + if (!cpu || !ctrl_base) + return; + if (use_emc == 1) + writel_relaxed(virt_to_phys(jump_addr), ctrl_base + 0x2000); + else + writel_relaxed(virt_to_phys(jump_addr), + ctrl_base + COH_FUN_BASE); +} + +int fhca7_get_cpu_jump(int cpu) +{ + cpu = cpu_logical_map(cpu); + if (!cpu || !ctrl_base) + return 0; + if (use_emc == 1) + return readl_relaxed(ctrl_base + 0x2000); + else + return readl_relaxed(ctrl_base + COH_FUN_BASE); +} + + + +static void __init fhca7_smp_prepare_cpus(unsigned int max_cpus) +{ + struct device_node *np = NULL; + void __iomem *pmu_base; + + if (!ctrl_base) { + np = of_find_compatible_node(NULL, NULL, "fh,fh-pmu"); + if (!np) { + pr_err("failed to find fh,fh-pmu node\n"); + return; + } + pmu_base = of_iomap(np, 0); + if (!pmu_base) { + pr_err("failed to map address\n"); + return; + } + if (readl(pmu_base + COH_MAGIC) != MPCORE_COH_MAGIC) { + use_emc = 1; + pr_err("mismatch magic ,return to emc to find coh-pen\n"); + np = of_find_compatible_node(NULL, NULL, "fh,emc-ram"); + if (!np) { + pr_err("failed to find fh,emc-ramnode\n"); + return; + } + ctrl_base = of_iomap(np, 0); + if (!ctrl_base) { + pr_err("failed to map address\n"); + return; + } + } else { + ctrl_base = pmu_base; + use_emc = 0; + } + } +} + +static int fhca7_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + fhca7_set_cpu(cpu, true); + fhca7_set_cpu_jump(cpu, secondary_startup); + arch_send_wakeup_ipi_mask(cpumask_of(cpu)); + return 0; +} + +static const struct smp_operations fhca7_smp_ops __initconst = { + .smp_prepare_cpus = fhca7_smp_prepare_cpus, + .smp_boot_secondary = fhca7_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_die = fhca7_cpu_die, + .cpu_kill = fhca7_cpu_kill, +#endif +}; + + +CPU_METHOD_OF_DECLARE(fhca7_smp, "fh,fh-ca7-smp", &fhca7_smp_ops); diff --git a/arch/arm/mach-fh/pmu.c b/arch/arm/mach-fh/pmu.c new file mode 100644 index 00000000..ac4d4161 --- /dev/null +++ b/arch/arm/mach-fh/pmu.c @@ -0,0 +1,583 @@ +#include +#include +#include +#include +#include +#include +#include "chip.h" +#include "soc.h" + +static int s_pmu_inited = 0; +static void __iomem *fh_pmu_regs = NULL; + +#ifndef INTERNAL_PHY +#define INTERNAL_PHY 0x55 +#endif +#ifndef EXTERNAL_PHY +#define EXTERNAL_PHY 0xaa +#endif + +void fh_pmu_set_reg(unsigned int offset, unsigned int data) +{ + + if (offset > FH_PMU_REG_SIZE) { + pr_err("fh_pmu_set_reg: offset is out of range"); + return; + } + + writel(data, fh_pmu_regs + offset); +} +EXPORT_SYMBOL(fh_pmu_set_reg); + +unsigned int fh_pmu_get_reg(unsigned int offset) +{ + + if (offset > FH_PMU_REG_SIZE) { + pr_err("fh_pmu_get_reg: offset is out of range"); + return 0; + } + return readl(fh_pmu_regs + offset); +} +EXPORT_SYMBOL(fh_pmu_get_reg); + +void fh_pmu_set_reg_m(unsigned int offset, unsigned int data, unsigned int mask) +{ + fh_pmu_set_reg(offset, (fh_pmu_get_reg(offset) & (~(mask))) | + ((data) & (mask))); +} +EXPORT_SYMBOL(fh_pmu_set_reg_m); + +void fh_get_chipid(unsigned int *plat_id, unsigned int *chip_id) +{ + unsigned int _plat_id = 0; + + _plat_id = fh_pmu_get_reg(REG_PMU_CHIP_ID); + if (plat_id != NULL) + *plat_id = _plat_id; + + if (chip_id != NULL) + *chip_id = fh_pmu_get_reg(REG_PMU_IP_VER); +} +EXPORT_SYMBOL(fh_get_chipid); + +unsigned int fh_pmu_get_ptsl(void) +{ + fh_pmu_set_reg(REG_PMU_PTSLO, 0x01); + return fh_pmu_get_reg(REG_PMU_PTSLO); +} +EXPORT_SYMBOL(fh_pmu_get_ptsl); + +unsigned int fh_pmu_get_ptsh(void) +{ + fh_pmu_set_reg(REG_PMU_PTSLO, 0x01); + return fh_pmu_get_reg(REG_PMU_PTSHI); +} +EXPORT_SYMBOL(fh_pmu_get_ptsh); + +unsigned long long fh_get_pts64(void) +{ + unsigned int high, low; + unsigned long long pts64; + + fh_pmu_set_reg(REG_PMU_PTSLO, 0x01); + high = fh_pmu_get_reg(REG_PMU_PTSHI); + low = fh_pmu_get_reg(REG_PMU_PTSLO); + pts64 = (((unsigned long long)high)<<32)|((unsigned long long)low); + return pts64; +} +EXPORT_SYMBOL(fh_get_pts64); + +void fh_pmu_wdt_pause(void) +{ + unsigned int reg; + + reg = fh_pmu_get_reg(REG_PMU_WDT_CTRL); + reg |= 0x100; + fh_pmu_set_reg(REG_PMU_WDT_CTRL, reg); +} +EXPORT_SYMBOL_GPL(fh_pmu_wdt_pause); + +void fh_pmu_wdt_resume(void) +{ + unsigned int reg; + + reg = fh_pmu_get_reg(REG_PMU_WDT_CTRL); + reg &= ~(0x100); + fh_pmu_set_reg(REG_PMU_WDT_CTRL, reg); +} +EXPORT_SYMBOL_GPL(fh_pmu_wdt_resume); + +void fh_pmu_usb_utmi_rst(void) +{ + unsigned int pmu_reg; + + pmu_reg = fh_pmu_get_reg(REG_PMU_SWRST_MAIN_CTRL); + pmu_reg &= ~(USB_UTMI_RST_BIT); + fh_pmu_set_reg(REG_PMU_SWRST_MAIN_CTRL, pmu_reg); + pmu_reg = fh_pmu_get_reg(REG_PMU_SWRST_MAIN_CTRL); + mdelay(1); + pmu_reg |= USB_UTMI_RST_BIT; + fh_pmu_set_reg(REG_PMU_SWRST_MAIN_CTRL, pmu_reg); + pmu_reg = fh_pmu_get_reg(REG_PMU_SWRST_MAIN_CTRL); + msleep(20); +} +EXPORT_SYMBOL_GPL(fh_pmu_usb_utmi_rst); + +void fh_pmu_usb_phy_rst(void) +{ + unsigned int pmu_reg; + + pmu_reg = fh_pmu_get_reg(REG_PMU_USB_SYS1); + pmu_reg &= (~USB_IDDQ_PWR_BIT); + fh_pmu_set_reg(REG_PMU_USB_SYS1, pmu_reg); + mdelay(1); + pmu_reg = fh_pmu_get_reg(REG_PMU_USB_SYS); + pmu_reg |= (USB_PHY_RST_BIT); + fh_pmu_set_reg(REG_PMU_USB_SYS, pmu_reg); + mdelay(1); + pmu_reg = fh_pmu_get_reg(REG_PMU_USB_SYS); + pmu_reg &= (~USB_PHY_RST_BIT); + fh_pmu_set_reg(REG_PMU_USB_SYS, pmu_reg); +} +EXPORT_SYMBOL_GPL(fh_pmu_usb_phy_rst); + +void fh_pmu_usb_resume(void) +{ + unsigned int pmu_reg; + + pmu_reg = fh_pmu_get_reg(REG_PMU_USB_SYS); + pmu_reg |= (USB_SLEEP_MODE_BIT); + fh_pmu_set_reg(REG_PMU_USB_SYS, pmu_reg); + mdelay(1); +} +EXPORT_SYMBOL_GPL(fh_pmu_usb_resume); + +void _pmu_main_reset(unsigned int reg, unsigned int retry, unsigned int udelay) +{ + fh_pmu_set_reg(REG_PMU_SWRST_MAIN_CTRL, reg); + + while (fh_pmu_get_reg(REG_PMU_SWRST_MAIN_CTRL) != 0xffffffff) { + if (retry-- <= 0) + return; + + udelay(udelay); + } +} + +#if defined(CONFIG_MACH_FH8856) || \ + defined(CONFIG_MACH_FH8852) || \ + defined(CONFIG_MACH_FH8626V100) + +void _pmu_axi_reset(unsigned int reg, unsigned int retry, unsigned int udelay) +{ + fh_pmu_set_reg(REG_PMU_SWRST_AXI_CTRL, reg); + + while (fh_pmu_get_reg(REG_PMU_SWRST_AXI_CTRL) != 0xffffffff) { + if (retry-- <= 0) + return; + + udelay(udelay); + } +} +#endif + +void _pmu_ahb_reset(unsigned int reg, unsigned int retry, unsigned int udelay) +{ + fh_pmu_set_reg(REG_PMU_SWRST_AHB_CTRL, reg); + + while (fh_pmu_get_reg(REG_PMU_SWRST_AHB_CTRL) != 0xffffffff) { + if (retry-- <= 0) + return; + + udelay(udelay); + } +} + +void _pmu_apb_reset(unsigned int reg, unsigned int retry, unsigned int udelay) +{ + fh_pmu_set_reg(REG_PMU_SWRST_APB_CTRL, reg); + + while (fh_pmu_get_reg(REG_PMU_SWRST_APB_CTRL) != 0xffffffff) { + if (retry-- <= 0) + return; + + udelay(udelay); + } +} + +void _pmu_nsr_reset(unsigned int reg, unsigned int reset_time) +{ + fh_pmu_set_reg(REG_PMU_SWRSTN_NSR, reg); + udelay(reset_time); + fh_pmu_set_reg(REG_PMU_SWRSTN_NSR, 0xFFFFFFFF); +} + +void fh_pmu_sdc_reset(int slot_id) +{ + unsigned int reg = 0; + + if (slot_id == 1) + reg = ~(1 << SDC1_HRSTN_BIT); + else if (slot_id == 0) + reg = ~(1 << SDC0_HRSTN_BIT); + else + reg = 0; + + _pmu_ahb_reset(reg, 1000, 1); +} +EXPORT_SYMBOL_GPL(fh_pmu_sdc_reset); + +void fh_pmu_mipi_reset(void) +{ + _pmu_apb_reset(~(1 << MIPIW_PRSTN_BIT | 1 << MIPIC_PRSTN_BIT), 1000, 1); +} +EXPORT_SYMBOL_GPL(fh_pmu_mipi_reset); + +void fh_pmu_enc_reset(void) +{ +#if !defined(CONFIG_ARCH_FH8626V100) \ + && !defined(CONFIG_ARCH_FH8636) \ + && !defined(CONFIG_ARCH_FH8852V101) + _pmu_ahb_reset(~(1 << VCU_HRSTN_BIT), 100, 10); +#endif +} +EXPORT_SYMBOL_GPL(fh_pmu_enc_reset); + +void fh_pmu_dwi2s_set_clk(unsigned int div_i2s, unsigned int div_mclk) +{ +#if !defined(CONFIG_ARCH_FH8636) && !defined(CONFIG_ARCH_FH8852V101) + unsigned int reg; + + reg = fh_pmu_get_reg(PMU_DWI2S_CLK_DIV_REG); + reg &= ~(0xffff << PMU_DWI2S_CLK_DIV_SHIFT); + reg |= ((div_i2s-1) << 8 | (div_mclk-1)) << PMU_DWI2S_CLK_DIV_SHIFT; + fh_pmu_set_reg(PMU_DWI2S_CLK_DIV_REG, reg); + + /* i2s_clk switch to PLLVCO */ + reg = fh_pmu_get_reg(PMU_DWI2S_CLK_SEL_REG); + reg &= ~(1 << PMU_DWI2S_CLK_SEL_SHIFT); + reg |= 1 << PMU_DWI2S_CLK_SEL_SHIFT; + fh_pmu_set_reg(PMU_DWI2S_CLK_SEL_REG, reg); +#endif +} +EXPORT_SYMBOL_GPL(fh_pmu_dwi2s_set_clk); + +void fh_pmu_eth_set_speed(unsigned int speed) +{ + unsigned int reg; + + reg = fh_pmu_get_reg(PMU_RMII_SPEED_MODE); + if (speed == 10) + reg &= ~(FH_GMAC_SPEED_100M); + else if (speed == 100) + reg |= FH_GMAC_SPEED_100M; + else + printk(KERN_ERR"ERROR: wrong param for emac set speed, %d\n", + speed); + + fh_pmu_set_reg(PMU_RMII_SPEED_MODE, reg); +} +EXPORT_SYMBOL_GPL(fh_pmu_eth_set_speed); + +void fh_pmu_eth_reset(void) +{ + _pmu_ahb_reset(~(1 << EMAC_HRSTN_BIT), 1000, 1); +} +EXPORT_SYMBOL_GPL(fh_pmu_eth_reset); + +void fh_pmu_restart(void) +{ + fh_pmu_set_reg(REG_PMU_SWRST_MAIN_CTRL, 0x7fffffff); +} + + +unsigned int fh_pmu_get_tsensor_init_data(void) +{ +#if defined(CONFIG_ARCH_FH885xV200) || \ +defined(CONFIG_ARCH_FH865x) || \ +defined(CONFIG_ARCH_FH8636) || \ +defined(CONFIG_ARCH_FH8852V101) + return fh_pmu_get_reg(REG_PMU_RTC_PARAM); +#else + return 0; +#endif +} +EXPORT_SYMBOL_GPL(fh_pmu_get_tsensor_init_data); + +unsigned int fh_pmu_get_ddrsize(void) +{ +#if defined(CONFIG_ARCH_FH885xV200) || \ +defined(CONFIG_ARCH_FH865x) || \ +defined(CONFIG_ARCH_FH8636) || \ +defined(CONFIG_ARCH_FH8852V101) + return fh_pmu_get_reg(REG_PMU_DDR_SIZE); +#else + return 0; +#endif +} +EXPORT_SYMBOL_GPL(fh_pmu_get_ddrsize); + +#if defined(CONFIG_ARCH_FH885xV200) || \ +defined(CONFIG_ARCH_FH865x) + +#define REFIX_TRAIN_DATA_OFFSET (0) +#define MIN_TRAINING_DATA -8 +#define MAX_TRAINING_DATA 7 +int __refix_train_data(int *pdata, int offset) +{ + int temp_data; + + temp_data = *pdata; + temp_data &= INSIDE_PHY_TRAINING_MASK; + + if (temp_data & 0x08) + temp_data = (~INSIDE_PHY_TRAINING_MASK) | temp_data; + + temp_data += offset; + + if (temp_data < MIN_TRAINING_DATA || temp_data > MAX_TRAINING_DATA) { + pr_err("cal data [%d] should limit in [%d , %d]\n", + temp_data, MIN_TRAINING_DATA, MAX_TRAINING_DATA); + return -1; + } + temp_data &= INSIDE_PHY_TRAINING_MASK; + + *pdata = temp_data; + return 0; +} + +void refix_train_data(int *pdata) +{ + __refix_train_data(pdata, REFIX_TRAIN_DATA_OFFSET); +} +#endif + +int fh_pmu_internal_ephy_reset(void) +{ +#if defined CONFIG_FH_EPHY + pr_err("fh_pmu_internal_ephy_reset v2 get in...\n"); + //add internal phy reset code below... +#elif defined(CONFIG_ARCH_FH885xV200) || \ +defined(CONFIG_ARCH_FH865x) + int train_data; + /*reset sunplus phy */ + /* + * ephy shutdown: ---____________________________ + * ephy rst : ___|<=L_10ms=>|--|<=H_12us=>|-- + * ephy clkin : _-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_ + */ + /* pull up shut down first.. */ + fh_pmu_set_reg_m(REG_PMU_ETHPHY_REG0, + 1 << INSIDE_PHY_SHUTDOWN_BIT_POS, + 1 << INSIDE_PHY_SHUTDOWN_BIT_POS); + + udelay(5); + /* pull down shut down and rst for 10ms. */ + fh_pmu_set_reg_m(REG_PMU_ETHPHY_REG0, 0, + 1 << INSIDE_PHY_SHUTDOWN_BIT_POS); + + fh_pmu_set_reg_m(REG_PMU_SWRSTN_NSR, 0, + 1 << INSIDE_PHY_RST_BIT_POS); + + mdelay(10); + /* pull up rst for 12us. */ + fh_pmu_set_reg_m(REG_PMU_SWRSTN_NSR, + 1 << INSIDE_PHY_RST_BIT_POS, + 1 << INSIDE_PHY_RST_BIT_POS); + + udelay(12); + + train_data = fh_pmu_get_reg(REG_PMU_EPHY_PARAM); + if (train_data & (1 << TRAINING_EFUSE_ACTIVE_BIT_POS)) { + /* train_data */ + refix_train_data(&train_data); + pr_info("ephy: training data is :%x\n", + train_data); + fh_pmu_set_reg_m(REG_PMU_ETHPHY_REG0, + (train_data & INSIDE_PHY_TRAINING_MASK) + << INSIDE_PHY_TRAINING_BIT_POS, + INSIDE_PHY_TRAINING_MASK << INSIDE_PHY_TRAINING_BIT_POS); + } else{ + /* todo set default value...*/ + train_data = 0; + pr_info("ephy: no training data, use default:%x\n", + train_data); + /* train_data */ + fh_pmu_set_reg_m(REG_PMU_ETHPHY_REG0, + train_data << INSIDE_PHY_TRAINING_BIT_POS, + INSIDE_PHY_TRAINING_MASK << INSIDE_PHY_TRAINING_BIT_POS); + } +#endif + return 0; +} +EXPORT_SYMBOL(fh_pmu_internal_ephy_reset); + +void fh_pmu_ephy_sel(__u32 phy_sel) +{ +#if defined CONFIG_FH_EPHY + pr_err("fh_pmu_ephy_sel v2 get in...\n"); + //add multi phy sel code below... + +#elif defined(CONFIG_ARCH_FH885xV200) || \ +defined(CONFIG_ARCH_FH865x) + fh_pmu_set_reg_m(REG_PMU_CLK_SEL, + 1 << CLK_SCAN_BIT_POS, 1 << CLK_SCAN_BIT_POS); + + if (phy_sel == EXTERNAL_PHY) { + /* close inside phy */ + fh_pmu_set_reg_m(REG_PMU_ETHPHY_REG0, + 0 << INSIDE_PHY_ENABLE_BIT_POS, 1 << INSIDE_PHY_ENABLE_BIT_POS); + /* gate inside phy */ + fh_pmu_set_reg_m(REG_PMU_CLK_GATE1, + 1 << INSIDE_CLK_GATE_BIT_POS, + 1 << INSIDE_CLK_GATE_BIT_POS); + /* set div */ + fh_pmu_set_reg_m(REG_PMU_CLK_DIV6, + 1 << MAC_REF_CLK_DIV_BIT_POS, + MAC_REF_CLK_DIV_MASK << MAC_REF_CLK_DIV_BIT_POS); + /* set pad */ + /* eth ref clk out Ungate */ + fh_pmu_set_reg_m(REG_PMU_CLK_GATE, + 0 << ETH_REF_CLK_OUT_GATE_BIT_POS, + 1 << ETH_REF_CLK_OUT_GATE_BIT_POS); + /* eth rmii clk Ungate */ + fh_pmu_set_reg_m(REG_PMU_CLK_GATE, + 0 << ETH_RMII_CLK_OUT_GATE_BIT_POS, + 1 << ETH_RMII_CLK_OUT_GATE_BIT_POS); + /* switch mac clk in */ + fh_pmu_set_reg_m(REG_PMU_CLK_SEL, + 1 << IN_OR_OUT_PHY_SEL_BIT_POS, + 1 << IN_OR_OUT_PHY_SEL_BIT_POS); + } else { + /* inside phy enable */ + fh_pmu_set_reg_m(REG_PMU_ETHPHY_REG0, + 1 << INSIDE_PHY_ENABLE_BIT_POS, + 1 << INSIDE_PHY_ENABLE_BIT_POS); + /* set pad no need */ + /* eth ref clk out gate */ + fh_pmu_set_reg_m(REG_PMU_CLK_GATE, + 1 << ETH_REF_CLK_OUT_GATE_BIT_POS, + 1 << ETH_REF_CLK_OUT_GATE_BIT_POS); + /* eth rmii clk gate */ + fh_pmu_set_reg_m(REG_PMU_CLK_GATE, + 1 << ETH_RMII_CLK_OUT_GATE_BIT_POS, + 1 << ETH_RMII_CLK_OUT_GATE_BIT_POS); + /* inside phy clk Ungate */ + fh_pmu_set_reg_m(REG_PMU_CLK_GATE1, + 0 << INSIDE_CLK_GATE_BIT_POS, + 1 << INSIDE_CLK_GATE_BIT_POS); + /* int rmii refclk mux */ + fh_pmu_set_reg_m(REG_PMU_CLK_SEL, + 0 << IN_OR_OUT_PHY_SEL_BIT_POS, + 1 << IN_OR_OUT_PHY_SEL_BIT_POS); + } +#else + return; +#endif +} +EXPORT_SYMBOL(fh_pmu_ephy_sel); + +void fh_pmu_set_sdc1_funcsel(unsigned int val) +{ +#if defined(CONFIG_ARCH_FH885xV200) || \ +defined(CONFIG_ARCH_FH865x) || \ +defined(CONFIG_ARCH_FH8636) || \ +defined(CONFIG_ARCH_FH8852V101) + fh_pmu_set_reg(REG_PMU_SD1_FUNC_SEL, val); +#endif +} +EXPORT_SYMBOL_GPL(fh_pmu_set_sdc1_funcsel); + +void fh_pmu_arxc_write_A625_INT_RAWSTAT(unsigned int val) +{ + fh_pmu_set_reg(PMU_A625_INT_RAWSTAT, val); +} +EXPORT_SYMBOL_GPL(fh_pmu_arxc_write_A625_INT_RAWSTAT); + +unsigned int fh_pmu_arxc_read_ARM_INT_RAWSTAT(void) +{ + return fh_pmu_get_reg(PMU_ARM_INT_RAWSTAT); +} +EXPORT_SYMBOL_GPL(fh_pmu_arxc_read_ARM_INT_RAWSTAT); + +void fh_pmu_arxc_write_ARM_INT_RAWSTAT(unsigned int val) +{ + fh_pmu_set_reg(PMU_ARM_INT_RAWSTAT, val); +} +EXPORT_SYMBOL_GPL(fh_pmu_arxc_write_ARM_INT_RAWSTAT); + +unsigned int fh_pmu_arxc_read_ARM_INT_STAT(void) +{ + return fh_pmu_get_reg(PMU_ARM_INT_STAT); +} +EXPORT_SYMBOL_GPL(fh_pmu_arxc_read_ARM_INT_STAT); + +void fh_pmu_arxc_reset(unsigned long phy_addr) +{ + unsigned int arc_addr; + + /*ARC Reset*/ + fh_pmu_set_reg(REG_PMU_SWRSTN_NSR, ~(1<> 16); + + fh_pmu_set_reg(REG_PMU_A625BOOT0, 0x7940266B); + /* Configure ARC Bootcode start address */ + fh_pmu_set_reg(REG_PMU_A625BOOT1, arc_addr); + fh_pmu_set_reg(REG_PMU_A625BOOT2, 0x0F802020); + fh_pmu_set_reg(REG_PMU_A625BOOT3, arc_addr); + + /*clear ARC ready flag*/ + fh_pmu_arxc_write_ARM_INT_RAWSTAT(0); + + /* don't let ARC run when release ARC */ + fh_pmu_set_reg(REG_PMU_A625_START_CTRL, 0); + udelay(2); + + /* ARC reset released */ + fh_pmu_set_reg(REG_PMU_SWRSTN_NSR, 0xFFFFFFFF); +} +EXPORT_SYMBOL_GPL(fh_pmu_arxc_reset); + +void fh_pmu_arxc_kickoff(void) +{ + //start ARC625 + fh_pmu_set_reg(REG_PMU_A625_START_CTRL, 0x10); +} +EXPORT_SYMBOL_GPL(fh_pmu_arxc_kickoff); + +#ifdef CONFIG_USE_OF +static const struct of_device_id fh_pmu_match[] = { + { + .compatible = "fh,fh-pmu", + }, + {}, +}; +#endif + +int fh_pmu_init(void) +{ + +#ifdef CONFIG_USE_OF + struct device_node *np; +#endif + + if (s_pmu_inited) + return 0; + +#ifdef CONFIG_USE_OF + np = of_find_matching_node(NULL, fh_pmu_match); + + if (np) { + fh_pmu_regs = of_iomap(np, 0); + } else { + pr_err("ERROR: cannot get pmu regs from dts\n"); + return -1; + } +#else + fh_pmu_regs = (void __iomem *)VA_PMU_REG_BASE; +#endif + + s_pmu_inited = 1; + return 0; +} diff --git a/arch/arm/mach-fh/soc.h b/arch/arm/mach-fh/soc.h new file mode 100644 index 00000000..8b5687cd --- /dev/null +++ b/arch/arm/mach-fh/soc.h @@ -0,0 +1,9 @@ +#ifndef _SOC_H_ +#define _SOC_H_ + +void fh_pmu_set_reg(u32 offset, u32 data); +u32 fh_pmu_get_reg(u32 offset); +void fh_pmu_set_reg_m(u32 offset, u32 data, u32 mask); +int fh_pmu_init(void); + +#endif /* _SOC_H_ */ diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index f7c74135..f8cc394d 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -63,16 +63,15 @@ pmdval_t user_pmd_table = _PAGE_USER_TABLE; #define CPOLICY_WRITEALLOC 4 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; -static unsigned int ecc_mask __initdata = 0; +static unsigned int ecc_mask __initdata; pgprot_t pgprot_user; +EXPORT_SYMBOL(pgprot_user); pgprot_t pgprot_kernel; +EXPORT_SYMBOL(pgprot_kernel); pgprot_t pgprot_hyp_device; pgprot_t pgprot_s2; pgprot_t pgprot_s2_device; -EXPORT_SYMBOL(pgprot_user); -EXPORT_SYMBOL(pgprot_kernel); - struct cachepolicy { const char policy[16]; unsigned int cr_mask; @@ -122,7 +121,7 @@ static struct cachepolicy cache_policies[] __initdata = { }; #ifdef CONFIG_CPU_CP15 -static unsigned long initial_pmd_value __initdata = 0; +static unsigned long initial_pmd_value __initdata; /* * Initialise the cache_policy variable with the initial state specified @@ -185,6 +184,7 @@ static int __init early_cachepolicy(char *p) if (selected != cachepolicy) { unsigned long cr = __clear_cr(cache_policies[selected].cr_mask); + cachepolicy = selected; flush_cache_all(); set_cr(cr); @@ -196,6 +196,7 @@ early_param("cachepolicy", early_cachepolicy); static int __init early_nocache(char *__unused) { char *p = "buffered"; + pr_warn("nocache is deprecated; use cachepolicy=%s\n", p); early_cachepolicy(p); return 0; @@ -653,6 +654,7 @@ static void __init build_mem_type_table(void) for (i = 0; i < 16; i++) { pteval_t v = pgprot_val(protection_map[i]); + protection_map[i] = __pgprot(v | user_pgprot); } @@ -690,6 +692,7 @@ static void __init build_mem_type_table(void) for (i = 0; i < ARRAY_SIZE(mem_types); i++) { struct mem_type *t = &mem_types[i]; + if (t->prot_l1) t->prot_l1 |= PMD_DOMAIN(t->domain); if (t->prot_sect) @@ -715,6 +718,7 @@ EXPORT_SYMBOL(phys_mem_access_prot); static void __init *early_alloc_aligned(unsigned long sz, unsigned long align) { void *ptr = __va(memblock_alloc(sz, align)); + memset(ptr, 0, sz); return ptr; } @@ -739,6 +743,7 @@ static pte_t * __init arm_pte_alloc(pmd_t *pmd, unsigned long addr, { if (pmd_none(*pmd)) { pte_t *pte = alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE); + __pmd_populate(pmd, __pa(pte), prot); } BUG_ON(pmd_bad(*pmd)); @@ -758,6 +763,7 @@ static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, bool ng) { pte_t *pte = arm_pte_alloc(pmd, addr, type->prot_l1, alloc); + do { set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), ng ? PTE_EXT_NG : 0); @@ -974,6 +980,7 @@ void __init create_mapping_late(struct mm_struct *mm, struct map_desc *md, { #ifdef CONFIG_ARM_LPAE pud_t *pud = pud_alloc(mm, pgd_offset(mm, md->virtual), md->virtual); + if (WARN_ON(!pud)) return; pmd_alloc(mm, pud, 0); diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index 2ed1b8a9..8a3b96b9 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -1006,3 +1006,9 @@ eco5_bx2 MACH_ECO5_BX2 ECO5_BX2 4572 eukrea_cpuimx28sd MACH_EUKREA_CPUIMX28SD EUKREA_CPUIMX28SD 4573 domotab MACH_DOMOTAB DOMOTAB 4574 pfla03 MACH_PFLA03 PFLA03 4575 +fh8856v200 MACH_FH8856V200 FH8856V200 9999 +fh8852v200 MACH_FH8852V200 FH8852V200 9999 +fh8858v200 MACH_FH8858V200 FH8858V200 9999 +fh8856v210 MACH_FH8856V210 FH8856V210 9999 +fh8852v210 MACH_FH8852V210 FH8852V210 9999 +fh8858v210 MACH_FH8858V210 FH8858V210 9999 diff --git a/crypto/Kconfig b/crypto/Kconfig index ab0d93ab..06e7f810 100644 --- a/crypto/Kconfig +++ b/crypto/Kconfig @@ -1649,7 +1649,7 @@ config CRYPTO_DRBG_CTR config CRYPTO_DRBG tristate - default CRYPTO_DRBG_MENU + default n select CRYPTO_RNG select CRYPTO_JITTERENTROPY diff --git a/crypto/ablkcipher.c b/crypto/ablkcipher.c index 860c9e5d..d35083bb 100644 --- a/crypto/ablkcipher.c +++ b/crypto/ablkcipher.c @@ -359,6 +359,23 @@ static int crypto_init_ablkcipher_ops(struct crypto_tfm *tfm, u32 type, return 0; } +struct crypto_ablkcipher *crypto_alloc_ablkcipher(const char *alg_name, + u32 type, u32 mask) +{ + struct crypto_tfm *t_crytfm = 0; + struct crypto_ablkcipher *tfm = 0; + int err; + + t_crytfm = crypto_alloc_base(alg_name, type, mask); + if (IS_ERR(t_crytfm)) { + pr_err("failed to alloc t_crytfm!\n"); + err = PTR_ERR(t_crytfm); + return err; + } + tfm = __crypto_ablkcipher_cast(t_crytfm); + return tfm; +} +EXPORT_SYMBOL_GPL(crypto_alloc_ablkcipher); #ifdef CONFIG_NET static int crypto_ablkcipher_report(struct sk_buff *skb, struct crypto_alg *alg) { diff --git a/crypto/af_alg.c b/crypto/af_alg.c index b5953f1d..d945d992 100644 --- a/crypto/af_alg.c +++ b/crypto/af_alg.c @@ -443,6 +443,7 @@ EXPORT_SYMBOL_GPL(af_alg_free_sg); int af_alg_cmsg_send(struct msghdr *msg, struct af_alg_control *con) { struct cmsghdr *cmsg; + struct af_alg_usr_def *p_usr_def; for_each_cmsghdr(cmsg, msg) { if (!CMSG_OK(msg, cmsg)) @@ -471,7 +472,12 @@ int af_alg_cmsg_send(struct msghdr *msg, struct af_alg_control *con) return -EINVAL; con->aead_assoclen = *(u32 *)CMSG_DATA(cmsg); break; + case ALG_USR_DEF: + p_usr_def = (struct af_alg_usr_def *)CMSG_DATA(cmsg); + memcpy(&con->usr_def, p_usr_def, + sizeof(struct af_alg_usr_def)); + break; default: return -EINVAL; } diff --git a/crypto/algif_skcipher.c b/crypto/algif_skcipher.c index aaf2f810..4455886e 100644 --- a/crypto/algif_skcipher.c +++ b/crypto/algif_skcipher.c @@ -307,6 +307,7 @@ static int skcipher_sendmsg(struct socket *sock, struct msghdr *msg, struct skcipher_ctx *ctx = ask->private; struct skcipher_tfm *skc = pask->private; struct crypto_skcipher *tfm = skc->skcipher; + struct af_alg_usr_def *p_usr_def = crypto_skcipher_usr_def(tfm); unsigned ivsize = crypto_skcipher_ivsize(tfm); struct skcipher_sg_list *sgl; struct af_alg_control con = {}; @@ -332,7 +333,8 @@ static int skcipher_sendmsg(struct socket *sock, struct msghdr *msg, default: return -EINVAL; } - + /* cpy usr def msg to tfm.... */ + memcpy(p_usr_def, &con.usr_def, sizeof(struct af_alg_usr_def)); if (con.iv && con.iv->ivlen != ivsize) return -EINVAL; } @@ -423,7 +425,6 @@ static int skcipher_sendmsg(struct socket *sock, struct msghdr *msg, ctx->merge = plen & (PAGE_SIZE - 1); } - err = 0; ctx->more = msg->msg_flags & MSG_MORE; @@ -665,7 +666,6 @@ static int skcipher_recvmsg_sync(struct socket *sock, struct msghdr *msg, } used = min_t(unsigned long, ctx->used, msg_data_left(msg)); - used = af_alg_make_sg(&ctx->rsgl, &msg->msg_iter, used); err = used; if (err < 0) @@ -704,7 +704,6 @@ static int skcipher_recvmsg_sync(struct socket *sock, struct msghdr *msg, skcipher_pull_sgl(sk, used, 1); iov_iter_advance(&msg->msg_iter, used); } - err = 0; unlock: diff --git a/crypto/skcipher.c b/crypto/skcipher.c index 93110d70..a3258db5 100644 --- a/crypto/skcipher.c +++ b/crypto/skcipher.c @@ -150,21 +150,26 @@ static int skcipher_setkey_ablkcipher(struct crypto_skcipher *tfm, static int skcipher_crypt_ablkcipher(struct skcipher_request *req, int (*crypt)(struct ablkcipher_request *)) { + + struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req); struct crypto_ablkcipher **ctx = crypto_skcipher_ctx(tfm); struct ablkcipher_request *subreq = skcipher_request_ctx(req); + /* bind to the tfm usr def... and then driver will parse it */ + subreq->usr_def = crypto_skcipher_usr_def(tfm); ablkcipher_request_set_tfm(subreq, *ctx); ablkcipher_request_set_callback(subreq, skcipher_request_flags(req), req->base.complete, req->base.data); ablkcipher_request_set_crypt(subreq, req->src, req->dst, req->cryptlen, req->iv); - + /* call aes driver.. */ return crypt(subreq); } static int skcipher_encrypt_ablkcipher(struct skcipher_request *req) { + struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req); struct crypto_tfm *tfm = crypto_skcipher_tfm(skcipher); struct ablkcipher_alg *alg = &tfm->__crt_alg->cra_ablkcipher; diff --git a/drivers/Kconfig b/drivers/Kconfig index e1e2066c..724edefb 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -88,8 +88,6 @@ source "drivers/regulator/Kconfig" source "drivers/media/Kconfig" -source "drivers/video/Kconfig" - source "sound/Kconfig" source "drivers/hid/Kconfig" @@ -202,4 +200,7 @@ source "drivers/hwtracing/intel_th/Kconfig" source "drivers/fpga/Kconfig" +source "drivers/tee/Kconfig" + +source "drivers/cryptodev-linux-master/Kconfig" endmenu diff --git a/drivers/Makefile b/drivers/Makefile index 7c3d58dc..5039fae4 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -17,7 +17,6 @@ obj-y += pwm/ obj-$(CONFIG_PCI) += pci/ obj-$(CONFIG_PARISC) += parisc/ obj-$(CONFIG_RAPIDIO) += rapidio/ -obj-y += video/ obj-y += idle/ # IPMI must come before ACPI in order to provide IPMI opregion support @@ -34,7 +33,7 @@ obj-y += clk/ # Many drivers will want to use DMA so this has to be made available # really early. obj-$(CONFIG_DMADEVICES) += dma/ - +obj-$(CONFIG_CRYPTODEV) += cryptodev-linux-master/ # SOC specific infrastructure drivers. obj-y += soc/ @@ -175,3 +174,5 @@ obj-$(CONFIG_STM) += hwtracing/stm/ obj-$(CONFIG_ANDROID) += android/ obj-$(CONFIG_NVMEM) += nvmem/ obj-$(CONFIG_FPGA) += fpga/ +obj-$(CONFIG_TEE) += tee/ + diff --git a/drivers/char/random.c b/drivers/char/random.c index 81b65d0e..46c9ba13 100644 --- a/drivers/char/random.c +++ b/drivers/char/random.c @@ -1791,10 +1791,10 @@ urandom_read(struct file *file, char __user *buf, size_t nbytes, loff_t *ppos) static int maxwarn = 10; int ret; - if (!crng_ready() && maxwarn > 0) { + if (crng_init == 0 && maxwarn > 0) { maxwarn--; if (__ratelimit(&urandom_warning)) - printk(KERN_NOTICE "random: %s: uninitialized " + printk_once(KERN_NOTICE "random: %s: uninitialized " "urandom read (%zd bytes read)\n", current->comm, nbytes); spin_lock_irqsave(&primary_crng.lock, flags); diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 42042c0a..722166e5 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -50,6 +50,8 @@ obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o # please keep this section sorted lexicographically by directory path name +ifeq ($(CONFIG_USE_OF),y) +endif obj-$(CONFIG_COMMON_CLK_AT91) += at91/ obj-$(CONFIG_ARCH_ARTPEC) += axis/ obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/ diff --git a/drivers/clk/fh/Makefile b/drivers/clk/fh/Makefile new file mode 100644 index 00000000..d38e9e86 --- /dev/null +++ b/drivers/clk/fh/Makefile @@ -0,0 +1,6 @@ +# +# Fullhan Clock specific Makefile +# +ifeq ($(CONFIG_USE_OF),y) +obj-$(CONFIG_ARCH_FH885xV200) += clk-fh885xv200.o +endif diff --git a/drivers/clk/fh/clk-fh885xv200.c b/drivers/clk/fh/clk-fh885xv200.c new file mode 100644 index 00000000..88fe2df5 --- /dev/null +++ b/drivers/clk/fh/clk-fh885xv200.c @@ -0,0 +1,972 @@ +/* + * Clock and PLL control for FH devices + * + * Copyright (C) 2014 Fullhan Microelectronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static DEFINE_SPINLOCK(clk_lock); + +/* Maximum number of parents our clocks have */ +#define FH_MAX_PARENTS 4 + +#define PROC_FILE "driver/clock" + +#define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw) + + +#define SETMASK(len, pos) (((1U << (len)) - 1) << (pos)) +#define CLRMASK(len, pos) (~(SETMASK(len, pos))) + +#define FACTOR_GET(bit, len, reg) (((reg) & SETMASK(len, bit)) >> (bit)) +#define FACTOR_SET(bit, len, reg, val) \ + (((reg) & CLRMASK(len, bit)) | (val << (bit))) + +#define CONFIG_ISP_CLK_RATE 240000000 +#define CONFIG_JPEG_CLK_RATE 200000000 +#define CONFIG_VEU_CLK_RATE 300000000 + +/* init clk base addr */ +void __iomem *base_addr; + +/* Matches for pll clocks */ +struct clk_factors { + struct clk_hw hw; + void __iomem *reg0; + void __iomem *reg1; + u32 m; + u32 n; + u32 pr; + u32 divcop; + spinlock_t *lock; +}; + +struct fh_clk_divider { + struct clk_hw hw; + void __iomem *reg; + u32 prediv; + u32 div_flag; + u32 div_reg_mask; + spinlock_t *lock; +}; + +struct fh_clk_phase { + struct clk_hw hw; + void __iomem *reg; + u32 mux; + spinlock_t *lock; +}; + +struct fh_clk_config { + char name[32]; + u32 rate; +}; + + + +static struct of_device_id clk_fix_match[] __initdata = { + {.compatible = "fixed-clock", .data = NULL,}, + {} +}; + +/* Matches for pll clocks */ +static struct of_device_id clk_factors_match[] = { + {.compatible = "fh pll-ddr-rclk", .data = NULL,}, + {.compatible = "fh pll-cpu-pclk", .data = NULL,}, + {.compatible = "fh pll-cpu-rclk", .data = NULL,}, + {.compatible = "fh pll-sys-pclk", .data = NULL,}, + {.compatible = "fh pll-sys-rclk", .data = NULL,}, + {} +}; + +/* Matches for divided outputs */ +static struct of_device_id clk_divs_match[] = { + {.compatible = "fh fh-arm-clk", .data = NULL,}, + {.compatible = "fh fh-arc-clk", .data = NULL,}, + {.compatible = "fh fh-ahb-clk", .data = NULL,}, + {.compatible = "fh sysp-div12-clk", .data = NULL,}, + {.compatible = "fh fh-ddr-clk", .data = NULL,}, + {.compatible = "fh fh-ispa-clk", .data = NULL,}, + {.compatible = "fh fh-ispb-clk", .data = NULL,}, + {.compatible = "fh fh-vpu-clk", .data = NULL,}, + {.compatible = "fh fh-pix-clk", .data = NULL,}, + {.compatible = "fh fh-jpeg-clk", .data = NULL,}, + {.compatible = "fh fh-bgm-clk", .data = NULL,}, + {.compatible = "fh fh-jpeg-adapt-clk", .data = NULL,}, + {.compatible = "fh fh-sdc0-clk", .data = NULL,}, + {.compatible = "fh fh-sdc1-clk", .data = NULL,}, + {.compatible = "fh fh-spi0-clk", .data = NULL,}, + {.compatible = "fh fh-spi1-clk", .data = NULL,}, + {.compatible = "fh fh-spi2-clk", .data = NULL,}, + {.compatible = "fh fh-veu-clk", .data = NULL,}, + {.compatible = "fh fh-veu-adapt-clk", .data = NULL,}, + {.compatible = "fh fh-cis-clk-out", .data = NULL,}, + {.compatible = "fh fh-ac-mclk", .data = NULL,}, + {.compatible = "fh fh-usb-clk", .data = NULL,}, + {.compatible = "fh fh-eth-clk", .data = NULL,}, + {.compatible = "fh fh-ethrmii-clk", .data = NULL,}, + {.compatible = "fh fh-uart0-clk", .data = NULL,}, + {.compatible = "fh fh-uart1-clk", .data = NULL,}, + {.compatible = "fh fh-uart2-clk", .data = NULL,}, + {.compatible = "fh fh-i2c0-clk", .data = NULL,}, + {.compatible = "fh fh-i2c1-clk", .data = NULL,}, + {.compatible = "fh fh-i2c2-clk", .data = NULL,}, + {.compatible = "fh fh-pwm-clk", .data = NULL,}, + {.compatible = "fh fh-pts-clk", .data = NULL,}, + {.compatible = "fh fh-efuse-clk", .data = NULL,}, + {.compatible = "fh fh-tmr0-clk", .data = NULL,}, + {.compatible = "fh fh-ac-clk", .data = NULL,}, + {.compatible = "fh fh-i2s-clk", .data = NULL,}, + {.compatible = "fh fh-sadc-clk", .data = NULL,}, + {.compatible = "fh fh-wdt-clk", .data = NULL,}, + {.compatible = "fh fh-gpio0-dbclk", .data = NULL,}, + {.compatible = "fh fh-gpio1-dbclk", .data = NULL,}, + {.compatible = "fh fh-emc-hclk", .data = NULL,}, + {.compatible = "fh fh-rtc-pclk", .data = NULL,}, + {.compatible = "fh fh-aes-hclk", .data = NULL,}, + {.compatible = "fh fh-mipi-dphy-clk", .data = NULL,}, + {.compatible = "fh fh-mipi-wrap-clk", .data = NULL,}, + {.compatible = "fh fh-rtc-hclk", .data = NULL,}, + {.compatible = "fh fh-emac-hclk", .data = NULL,}, + {.compatible = "fh fh-usb-clk", .data = NULL,}, + {.compatible = "fh fh-aes-hclk", .data = NULL,}, + {.compatible = "fh fh-ephy-clk", .data = NULL,}, + {.compatible = "fh fh-sdc08x-clk", .data = NULL,}, + {.compatible = "fh fh-sdc18x-clk", .data = NULL,}, + {.compatible = "fh fh-mipic-pclk", .data = NULL,}, + {.compatible = "fh fh-gpio0-pclk", .data = NULL,}, + {.compatible = "fh fh-gpio1-pclk", .data = NULL,}, + {.compatible = "fh fh-isp-hclk", .data = NULL,}, + {.compatible = "fh fh-veu-hclk", .data = NULL,}, + {.compatible = "fh fh-bgm-hclk", .data = NULL,}, + {.compatible = "fh fh-adapt-hclk", .data = NULL,}, + {.compatible = "fh fh-jpg-hclk", .data = NULL,}, + {.compatible = "fh fh-jpg-adapt-clk", .data = NULL,}, + {.compatible = "fh fh-vpu-hclk", .data = NULL,}, + {} +}; + +/* Matches for phase clocks */ + +static struct of_device_id clk_phase_match[] __initdata = { + {.compatible = "fh fh-sdc0-clk_sample", .data = NULL,}, + {.compatible = "fh fh-sdc0-clk_drv", .data = NULL,}, + {.compatible = "fh fh-sdc1-clk_sample", .data = NULL,}, + {.compatible = "fh fh-sdc1-clk_drv", .data = NULL,}, + {} +}; + +/* init clocks base*/ +static struct of_device_id clk_init_match[] __initdata = { + {.compatible = "fh,fh-clk", .data = NULL,}, + {} +}; + + +void __init fh_fixed_clk_setup(struct device_node *node, + void *name) +{ + struct clk *clk; + u32 out_values; + const char *clk_name; + + of_property_read_string(node, "clock-output-names", &clk_name); + strcpy(name, clk_name); + of_property_read_u32_array(node, + "clock-frequency", &out_values, + 1); + clk = clk_register_fixed_rate(NULL, clk_name, + NULL, + CLK_IS_ROOT, + out_values); + if (!IS_ERR(clk)) { + of_clk_add_provider(node, of_clk_src_simple_get, clk); + clk_register_clkdev(clk, clk_name, NULL); + } +} +#define DIVVCO_ONE_DEVISION 0x0 +#define DIVVCO_TWO_DEVISION 0x8 +#define DIVVCO_FOUR_DEVISION 0xc +#define DIVVCO_EIGHT_DEVISION 0xd +#define DIVVCO_SIXTEEN_DEVISION 0xe +#define DIVVCO_THIRTYTWO_DEVISION 0xf + +static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + unsigned int m = 0, n = 0, pr = 1; + unsigned int clk_vco, divvcop = 1, shift; + u32 reg; + unsigned long rate; + struct clk_factors *factors = to_clk_factors(hw); + unsigned int divcop = 0; + /* Fetch the register value */ + reg = readl(factors->reg0); + shift = ffs(factors->m)-1; + m = (reg&factors->m) >> shift; + + shift = ffs(factors->n)-1; + n = (reg&factors->n) >> shift; + + /*pll databook*/ + if (m < 4) + m = 128+m; + + if (m == 0xb) + m = 0xa; + + shift = ffs(factors->pr)-1; + pr = (reg&factors->pr) >> shift; + + reg = readl(factors->reg1); + shift = ffs(factors->divcop)-1; + divcop = ((reg&factors->divcop) >> shift); + + + /* Calculate the rate */ + switch (divcop){ + case DIVVCO_ONE_DEVISION: + divvcop = 1; + break; + + case DIVVCO_TWO_DEVISION: + divvcop = 2; + break; + + case DIVVCO_FOUR_DEVISION: + divvcop = 4; + break; + + case DIVVCO_EIGHT_DEVISION: + divvcop = 8; + break; + + case DIVVCO_SIXTEEN_DEVISION: + divvcop = 16; + break; + + case DIVVCO_THIRTYTWO_DEVISION: + divvcop = 32; + break; + default: + printk("divvcop error:%x\n",divvcop); + } + + clk_vco = parent_rate * m / (n+1); + rate = clk_vco/ (pr+1)/divvcop; + return rate; + +} + +static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) + { + unsigned int m = 0, n = 0, pr = 1; + unsigned int clk_vco, divvcop = 1, shift; + u32 reg; + struct clk_factors *factors = to_clk_factors(hw); + unsigned int divcop = 0; + + /* Fetch the register value */ + reg = readl(factors->reg0); + + shift = ffs(factors->m)-1; + m = (reg&factors->m) >> shift; + + shift = ffs(factors->n)-1; + n = (reg&factors->n) >> shift; + + + /*pll databook*/ + if(m < 4) + m = 128+m; + + if(m == 0xb) + m = 0xa; + + shift = ffs(factors->pr)-1; + pr = (reg&factors->pr) >> shift; + + reg = readl(factors->reg1); + shift = ffs(factors->divcop)-1; + divcop = (reg&factors->divcop) >> shift; + + + /* Calculate the rate */ + switch (divcop){ + case DIVVCO_ONE_DEVISION: + divvcop = 1; + break; + + case DIVVCO_TWO_DEVISION: + divvcop = 2; + break; + + case DIVVCO_FOUR_DEVISION: + divvcop = 4; + break; + + case DIVVCO_EIGHT_DEVISION: + divvcop = 8; + break; + + case DIVVCO_SIXTEEN_DEVISION: + divvcop = 16; + break; + + case DIVVCO_THIRTYTWO_DEVISION: + divvcop = 32; + break; + default: + printk("divvcop error:%x\n",divvcop); + } + + clk_vco = (*parent_rate) * m / (n+1); + rate = clk_vco / (pr+1) / divvcop; + return rate; + + } + + +static const struct clk_ops clk_pll_ops = { + .recalc_rate = clk_pll_recalc_rate, + .round_rate = clk_pll_round_rate, +}; + +static unsigned long fh_clk_divide_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + u32 reg; + u32 divide = 0; + struct fh_clk_divider *factors = (struct fh_clk_divider *)hw; + unsigned long rate; + unsigned long shift; + unsigned long flags = 0; + + if (factors->lock) + spin_lock_irqsave(factors->lock, flags); + if (factors->div_flag) { + /* Fetch the register value */ + reg = readl(factors->reg); + + /* Get each individual factor if applicable */ + shift = ffs(factors->div_reg_mask)-1; + divide = (factors->div_reg_mask & reg)>> shift; + + /* Calculate the rate */ + rate = (parent_rate) / (divide+1) / factors->prediv; + } else + rate = parent_rate / factors->prediv; + if (factors->lock) + spin_unlock_irqrestore(factors->lock, flags); + + return rate; +} + +static long fh_clk_divide_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + u32 reg; + u32 rount_rate = 0, divide; + struct fh_clk_divider *factors = (struct fh_clk_divider *)hw; + unsigned long flags = 0; + + if (factors->lock) + spin_lock_irqsave(factors->lock, flags); + + if (factors->div_flag) { + + /* Fetch the register value */ + reg = readl(factors->reg); + + /* Calculate the rate */ + divide = (*parent_rate) / factors->prediv / rate; + rount_rate = (*parent_rate) / divide / factors->prediv; + } else + pr_err("fh_clk_divide_round_rate not support divide\n"); + + if (factors->lock) + spin_unlock_irqrestore(factors->lock, flags); + + return rount_rate; +} + +static int fh_clk_divide_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + u32 reg; + struct fh_clk_divider *factors = (struct fh_clk_divider *)hw; + u32 divide = 0; + unsigned long flags = 0; + unsigned long shift = 0; + + if (factors->lock) + spin_lock_irqsave(factors->lock, flags); + + + if (factors->div_flag) { + + /* Fetch the register value */ + reg = readl(factors->reg); + + divide = parent_rate/rate/factors->prediv - 1; + /*printk("fh_clk_divide_set_rate:%x\n",divide);*/ + + shift = ffs(factors->div_reg_mask)-1; + + + reg &= ~(factors->div_reg_mask); + reg |= ((divide << shift) & factors->div_reg_mask); + + /* Apply them now */ + clk_writel(reg, factors->reg); + + } + if (factors->lock) + spin_unlock_irqrestore(factors->lock, flags); + + return 0; +} + + +static const struct clk_ops fh_clk_divider_ops = { + .recalc_rate = fh_clk_divide_recalc_rate, + .round_rate = fh_clk_divide_round_rate, + .set_rate = fh_clk_divide_set_rate, +}; + +static int __init fh_divs_clk_setup(struct device_node *node, + void *name) +{ + struct clk *clk; + struct clk_gate *gate = NULL; + struct clk_hw *clk_mux_hw = NULL; + struct clk_mux *mux = NULL; + struct clk_hw *clk_gate_hw = NULL; + struct clk_hw *clk_divider_hw = NULL; + struct fh_clk_divider *fh_divider = NULL; + const char *clk_name; + const char *parents[FH_MAX_PARENTS]; + void __iomem *reg = NULL; + int i = 0; + u32 div_mask = 0; + u32 gate_mask = 0; + u32 mux_mask = 0; + u32 prediv = 0; + + if (!base_addr) + return 0; + + /* if we have a mux, we will have >1 parents */ + while (i < FH_MAX_PARENTS && + (parents[i] = of_clk_get_parent_name(node, i)) != NULL) + i++; + + fh_divider = kzalloc(sizeof(*fh_divider), GFP_KERNEL); + if (!fh_divider) + return 0; + + fh_divider->lock = &clk_lock; + of_property_read_string(node, "clock-output-names", &clk_name); + strcpy(name, clk_name); + + if(!of_property_read_u32(node, "prediv", &prediv)) { + fh_divider->prediv = prediv; + clk_divider_hw = &fh_divider->hw; + } else + fh_divider->prediv = 1; + + + /* Leaves can be fixed or configurable divisors */ + if (!of_property_read_u32(node, "div", &div_mask)) { + reg = of_iomap(node, 0); + clk_divider_hw = &fh_divider->hw; + fh_divider->reg = reg; + fh_divider->div_flag = 1; + fh_divider->div_reg_mask= div_mask; + } + + /* Add a gate if this factor clock can be gated */ + if (!of_property_read_u32(node, "gate", &gate_mask)) { + gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); + if (!gate) { + kfree(fh_divider); + return 0; + } + + /* set up gate properties */ + reg = of_iomap(node, 1); + gate->reg = reg; + gate->bit_idx =ffs(gate_mask)-1; + gate->lock = &clk_lock; + gate->flags = CLK_GATE_SET_TO_DISABLE; + clk_gate_hw = &gate->hw; + } + + if (!of_property_read_u32(node, "mux", &mux_mask)) { + mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL); + + + /* set up gate properties */ + reg = of_iomap(node, 2); + mux->reg = reg; + mux->shift = ffs(mux_mask)-1; + mux->mask = mux_mask>>mux->shift; + mux->lock = &clk_lock; + clk_mux_hw = &mux->hw; + } + #if 1 + clk = clk_register_composite(NULL, clk_name, + parents, i, + clk_mux_hw, &clk_mux_ops, + clk_divider_hw, &fh_clk_divider_ops, + clk_gate_hw, &clk_gate_ops, CLK_IGNORE_UNUSED); + if (!IS_ERR(clk)) { + of_clk_add_provider(node, of_clk_src_simple_get, clk); + clk_register_clkdev(clk, clk_name, NULL); + } + #endif + return 1; +} + + +static int __init fh_pll_clk_setup(struct device_node *node, + void *name) +{ + struct clk *clk; + struct clk_factors *factors; + const char *clk_name = node->name; + const char *parents[FH_MAX_PARENTS]; + void __iomem *reg0; + void __iomem *reg1; + int i = 0; + u32 pr = 0; + u32 divcop = 0; + u32 m = 0; + u32 n = 0; + + if (!base_addr) + return 0; + + reg0 = of_iomap(node, 0); + reg1 = of_iomap(node, 1); + /* if we have a mux, we will have >1 parents */ + while (i < FH_MAX_PARENTS && + (parents[i] = of_clk_get_parent_name(node, i)) != NULL) + i++; + of_property_read_string(node, "clock-output-names", &clk_name); + strcpy(name, clk_name); + factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL); + if (!factors) + return 0; + + if (of_property_read_u32(node, "m", &m)) { + pr_err("%s:get node attr m error\n", __func__); + return -1; + } + factors->m = m; + + if (of_property_read_u32(node, "n", &n)) { + pr_err("%s get node attr n error\n", __func__); + return -1; + } + factors->n = n; + + if (of_property_read_u32(node, "pr", &pr)) { + pr_err("%s get node attr pr error\n", __func__); + return -1; + } + factors->pr = pr; + + if (of_property_read_u32(node, "divcop", &divcop)) { + pr_err("%s get node attr dicop error\n", __func__); + return -1; + } + factors->divcop = divcop; + + /* set up factors properties */ + factors->reg0 = reg0; + factors->reg1 = reg1; + factors->lock = &clk_lock; + clk = clk_register_composite(NULL, clk_name, + parents, i, + NULL, NULL, + &factors->hw, &clk_pll_ops, + NULL, NULL, CLK_IGNORE_UNUSED); + if (!IS_ERR(clk)) { + of_clk_add_provider(node, of_clk_src_simple_get, clk); + clk_register_clkdev(clk, clk_name, NULL); + } + return 1; +} + + +static int fh_clk_set_phase(struct clk_hw *hw, + int degree) +{ + u32 reg; + struct fh_clk_phase *phase = (struct fh_clk_phase *)hw; + unsigned long flags = 0; + u32 local_degree = 0; + u32 shift = 0; + + /*printk("fh_clk_set_phase:%d\n",degree);*/ + if (phase->lock) + spin_lock_irqsave(phase->lock, flags); + + /* Fetch the register value */ + reg = readl(phase->reg); + + local_degree = degree; + + shift = ffs(phase->mux)-1; + + reg |= (local_degree << shift); + + /* Apply them now */ + writel(reg, phase->reg); + if (phase->lock) + spin_unlock_irqrestore(phase->lock, flags); + + return 1; +} + +static int fh_clk_get_phase(struct clk_hw *hw) +{ + u32 reg; + struct fh_clk_phase *phase = (struct fh_clk_phase *)hw; + unsigned long flags = 0; + u32 local_degree = 0; + u32 shift; + + if (phase->lock) + spin_lock_irqsave(phase->lock, flags); + + /* Fetch the register value */ + reg = readl(phase->reg); + shift = ffs(phase->mux)-1; + + reg = reg&(phase->mux) >> shift; + local_degree = reg; + + /*printk("fh_clk_get_phase:%d\n",local_degree);*/ + + if (phase->lock) + spin_unlock_irqrestore(phase->lock, flags); + + return local_degree; +} + + +static const struct clk_ops fh_clk_phase_ops = { + .set_phase = fh_clk_set_phase, + .get_phase = fh_clk_get_phase, +}; + +static int __init fh_phase_clk_setup(struct device_node *node, + void*data) +{ + struct clk *clk; + const char *clk_name = node->name; + const char *parents[FH_MAX_PARENTS]; + void __iomem *reg; + struct fh_clk_phase *clk_phase = NULL; + int i = 0; + struct clk_init_data *init = NULL; + u32 mux_mask = 0; + + while (i < FH_MAX_PARENTS && + (parents[i] = of_clk_get_parent_name(node, i)) != NULL) + i++; + + of_property_read_string(node, "clock-output-names", &clk_name); + + if(of_property_read_u32(node, "mux", &mux_mask)) { + pr_err("%s get node attr mux error\n", __func__); + return -1; + } + + clk_phase = kzalloc(sizeof(struct fh_clk_phase), GFP_KERNEL); + if (!clk_phase) + return 0; + clk_phase->mux = mux_mask; + init = kzalloc(sizeof(struct clk_init_data), GFP_KERNEL); + + reg = of_iomap(node, 0); + /* set up gate properties */ + clk_phase->reg = reg; + clk_phase->lock = &clk_lock; + init->ops = &fh_clk_phase_ops; + init->parent_names = parents; + init->num_parents = i; + init->name = clk_name; + clk_phase->hw.init = init; + clk = clk_register(NULL, &clk_phase->hw); + + if (clk) { + of_clk_add_provider(node, of_clk_src_simple_get, clk); + clk_register_clkdev(clk, clk_name, NULL); + } + + return 1; +} + + +static void __init of_fh_table_clock_setup(const struct of_device_id *clk_match, + void *function) +{ + struct device_node *np; + const char *name; + const struct of_device_id *match; + int (*setup_function)(struct device_node *, const void *) = function; + + for_each_matching_node_and_match(np, clk_match, &match) { + name = match->name; + setup_function(np, name); + } +} + +static int __init fh_clk_setup(struct device_node *node, + void *data) +{ + if (!base_addr) + base_addr = of_iomap(node, 0); + return 1; +} + +static void __init fh_init_setup(struct fh_clk_config clocks[], int nclocks) +{ + int i = 0; + /* init clocks base*/ + of_fh_table_clock_setup(clk_init_match, fh_clk_setup); + + /* Register fixed clocks */ + of_fh_table_clock_setup(clk_fix_match, fh_fixed_clk_setup); + + /* Register factor clocks */ + of_fh_table_clock_setup(clk_factors_match, fh_pll_clk_setup); + + /* Register divided output clocks */ + of_fh_table_clock_setup(clk_divs_match, fh_divs_clk_setup); + + /* Register phase clocks */ + of_fh_table_clock_setup(clk_phase_match, fh_phase_clk_setup); + + /* Protect the clocks that needs to stay on */ + for (i = 0; i < nclocks; i++) { + struct clk *clk = clk_get(NULL, clocks[i].name); + + if (!IS_ERR(clk)) { + clk_set_rate(clk,clocks[i].rate); + clk_put(clk); + } + + } +} +static void del_char(char *str, char ch) +{ + char *p = str; + char *q = str; + + while (*q) { + if (*q != ch) + *p++ = *q; + q++; + } + *p = '\0'; +} + +static ssize_t fh_clk_proc_write(struct file *filp, const char *buf, + size_t len, loff_t *off) +{ + int i, ret; + char message[64] = {0}; + char * const delim = ","; + char *cur = message; + char *param_str[4]; + unsigned int param[4]; + struct clk *clk; + + len = (len > 64) ? 64 : len; + + if (copy_from_user(message, buf, len)) + return -EFAULT; + + for (i = 0; i < 3; i++) { + param_str[i] = strsep(&cur, delim); + if (!param_str[i]) { + pr_err("%s: ERROR: parameter[%d] is empty\n", + __func__, i); + pr_err("[clk name], [enable/disable], [clk rate]\n"); + return -EINVAL; + } + del_char(param_str[i], ' '); + del_char(param_str[i], '\n'); + } + + clk = clk_get(NULL, param_str[0]); + if (!clk) { + pr_err("%s: ERROR: clk %s is not found\n", + __func__, param_str[0]); + pr_err("[clk name], [enable/disable], [clk rate]\n"); + return -EINVAL; + } + + param[2] = (u32)simple_strtoul(param_str[2], NULL, 10); + if (param[2] < 0) { + pr_err("ERROR: parameter[2] is incorrect\n"); + return -EINVAL; + } + + if (!strcmp(param_str[1], "enable")) { + clk_prepare_enable(clk); + pr_err("clk %s enabled\n", param_str[0]); + } else if (!strcmp(param_str[1], "disable")) { + clk_disable_unprepare(clk); + pr_err("clk %s disabled\n", param_str[0]); + return len; + } else { + pr_err("%s: ERROR: parameter[1]:%s is incorrect\n", + __func__, param_str[1]); + pr_err("[clk name], [enable/disable], [clk rate]\n"); + return -EINVAL; + } + ret = clk_set_rate(clk, param[2]); + if (ret) + pr_err("set clk rate failed\n, ret=%d\n", ret); + + return len; +} +static void *v_seq_start(struct seq_file *s, loff_t *pos) +{ + static unsigned long counter = 0; + if (*pos == 0) + return &counter; + *pos = 0; + return NULL; +} + +static void *v_seq_next(struct seq_file *s, void *v, loff_t *pos) +{ + (*pos)++; + return NULL; +} + +static void v_seq_stop(struct seq_file *s, void *v) +{ + +} + +static int v_seq_show(struct seq_file *sfile, void *v) +{ + struct of_device_id *match; + struct clk *clk = NULL; + unsigned long rate; + char gate[32]; + + seq_printf(sfile, "\nPLL Information:\n"); + for (match = clk_factors_match; match->name[0]; match++) { + clk = clk_get(NULL, match->name); + rate = clk_get_rate(clk); + + if (__clk_is_enabled(clk)) + memcpy(gate, "enable", sizeof("enable")); + else + memcpy(gate, "disable", sizeof("disable")); + seq_printf(sfile, "\t%-20s \t%9luHZ \t%-10s\n", + match->name, rate, gate); + clk_put(clk); + } + for (match = clk_divs_match; match->compatible[0]; match++) { + if (!match->name[0]) + continue; + clk = NULL; + clk = clk_get(NULL, match->name); + if (IS_ERR(clk)) + continue; + rate = clk_get_rate(clk); + + if (__clk_is_enabled(clk)) + memcpy(gate, "enable", sizeof("enable")); + else + memcpy(gate, "disable", sizeof("disable")); + seq_printf(sfile, "\t%-20s \t%9luHZ \t%-10s\n", + match->name, rate, gate); + clk_put(clk); + } + return 0; +} + +static const struct seq_operations fh_clk_seq_ops = { + .start = v_seq_start, + .next = v_seq_next, + .stop = v_seq_stop, + .show = v_seq_show +}; +static int fh_clk_proc_open(struct inode *inode, struct file *file) +{ + return seq_open(file, &fh_clk_seq_ops); +} + +static const struct file_operations fh_clk_proc_ops = { + .owner = THIS_MODULE, + .open = fh_clk_proc_open, + .read = seq_read, + .write = fh_clk_proc_write, + .release = seq_release, +}; + +int fh_clk_procfs_init(void) +{ + struct proc_dir_entry *proc_file; + + proc_file = proc_create(PROC_FILE, 0644, NULL, &fh_clk_proc_ops); + if (!proc_file) + pr_err("clock, create proc fs failed\n"); + + return 0; +} + +static struct fh_clk_config fh_init_rate_clocks[] __initconst = { + {.name = "uart1_clk", .rate = 16666666,}, + {.name = "uart2_clk", .rate = 16666666,}, + {.name = "isp_aclk", .rate = CONFIG_ISP_CLK_RATE,}, + {.name = "veu_clk", .rate = CONFIG_VEU_CLK_RATE,}, + {.name = "jpeg_clk", .rate = CONFIG_JPEG_CLK_RATE,}, +}; + +static void __init fh_init_clocks(struct device_node *node) +{ + fh_init_setup(fh_init_rate_clocks, + ARRAY_SIZE(fh_init_rate_clocks)); +} + +CLK_OF_DECLARE(fh_clk_init, "fh,fh-clk", fh_init_clocks); +module_init(fh_clk_procfs_init); + + diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index e2c6e43c..93380bca 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -60,6 +60,16 @@ config DW_APB_TIMER_OF select DW_APB_TIMER select CLKSRC_OF +config FULLHAN_TIMER + bool + +config FH_SIMPLE_TIMER + bool "Fullhan simple timer" + default n + help + Enables Fullhan simple timer. + + config ROCKCHIP_TIMER bool "Rockchip timer driver" if COMPILE_TEST depends on ARM || ARM64 diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index cf87f407..2ca13034 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -15,6 +15,8 @@ obj-$(CONFIG_CLKSRC_MMIO) += mmio.o obj-$(CONFIG_DIGICOLOR_TIMER) += timer-digicolor.o obj-$(CONFIG_DW_APB_TIMER) += dw_apb_timer.o obj-$(CONFIG_DW_APB_TIMER_OF) += dw_apb_timer_of.o +obj-$(CONFIG_FULLHAN_TIMER) += timer-fh.o +obj-$(CONFIG_FH_SIMPLE_TIMER) += fh_simple_timer.o obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o obj-$(CONFIG_CLKSRC_NOMADIK_MTU) += nomadik-mtu.o obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index a2503db7..38131d0b 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -465,9 +465,13 @@ static u32 check_ppi_trigger(int irq) u32 flags = irq_get_trigger_type(irq); if (flags != IRQF_TRIGGER_HIGH && flags != IRQF_TRIGGER_LOW) { +#if defined(CONFIG_ARCH_FULLHAN) && !defined(CONFIG_USE_OF) + flags = IRQF_TRIGGER_HIGH; +#else pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq); pr_warn("WARNING: Please fix your firmware\n"); flags = IRQF_TRIGGER_LOW; +#endif } return flags; @@ -870,12 +874,32 @@ static int __init arch_timer_init(void) ret = arch_timer_common_init(); if (ret) return ret; - arch_timer_kvm_info.virtual_irq = arch_timer_ppi[VIRT_PPI]; return 0; } +#if defined(CONFIG_ARCH_FULLHAN) && !defined(CONFIG_USE_OF) +int arch_timer_noof_init( + u32 freq, u32 ppilist[4], int alwayson, int suspendstop) +{ + int i; + + arch_timer_rate = freq; + arch_timers_present |= ARCH_CP15_TIMER; + for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++) { + arch_timer_ppi[i] = irq_create_mapping(NULL, + ppilist[i]); + } + + arch_timer_c3stop = alwayson; + arch_timer_uses_ppi = PHYS_SECURE_PPI; + arch_counter_suspend_stop = suspendstop; + arch_timer_init(); + return 0; + +} +#endif static int __init arch_timer_of_init(struct device_node *np) { int i; diff --git a/drivers/clocksource/fh_simple_timer.c b/drivers/clocksource/fh_simple_timer.c new file mode 100644 index 00000000..d44e3ebc --- /dev/null +++ b/drivers/clocksource/fh_simple_timer.c @@ -0,0 +1,259 @@ +#include +#include + +//#define FH_TIMER_DEBUG +#ifdef FH_TIMER_DEBUG +#define PRINT_DBG(fmt,args...) printk(fmt,##args) +#else +#define PRINT_DBG(fmt,args...) do{} while(0) +#endif + +static unsigned int stmr_regbase = 0; +static unsigned int stmr_clkbase = 0; + + +static inline unsigned int timern_base(int n) +{ + unsigned int base = 0; + switch (n) { + case 0: + default: + base = stmr_regbase; + break; + case 1: + base = stmr_regbase + 0x14; + break; + case 2: + base = stmr_regbase + 0x28; + break; + case 3: + base = stmr_regbase + 0x3c; + break; + } + return base; +} + +#define TIMERN_REG_BASE(n) (timern_base(n)) + +#define REG_TIMER_LOADCNT(n) (timern_base(n) + 0x00) +#define REG_TIMER_CUR_VAL(n) (timern_base(n) + 0x04) +#define REG_TIMER_CTRL_REG(n) (timern_base(n) + 0x08) +#define REG_TIMER_EOI_REG(n) (timern_base(n) + 0x0C) +#define REG_TIMER_INTSTATUS(n) (timern_base(n) + 0x10) + + + + + + +enum SIMPLE_TIMER_WORKMODE { + SIMPLE_TIMER_SEQ, + SIMPLE_TIMER_PERIOD +}; + +struct simple_time_base +{ + struct timerqueue_head simple_timer_queue; + int state; + int workmode; +}; +struct fh_simple_timer periodic_timer; + + +static struct simple_time_base base; + +static void fh_timer_enable(void) +{ + SET_REG((REG_TIMER_CTRL_REG(SIMPLE_TIMER_BASE)), 0x3); +} + +static void fh_timer_disable(void) +{ + SET_REG((REG_TIMER_CTRL_REG(SIMPLE_TIMER_BASE)), 0x0); +} + +static void fh_timer_clearirq(void) +{ + GET_REG((REG_TIMER_EOI_REG(SIMPLE_TIMER_BASE))); +} + +void fh_simple_timer_set_next(long cycles) +{ + int sync_cnt = 0; + + PRINT_DBG("cycles: %lu\n", cycles); + cycles *= stmr_clkbase; + + if (cycles < 0) { + pr_err("ERROR: cycles is invaild: %lu\n", cycles); + fh_timer_clearirq(); + fh_timer_disable(); + base.state = SIMPLE_TIMER_ERROR; + return; + } + + SET_REG_M((REG_TIMER_CTRL_REG(SIMPLE_TIMER_BASE)), 0x00, 0x1); + /* zy/ticket/100 : update apb Timer LOADCNT */ + /* CURRENTVALE could,t be start from new LOADCOUNT */ + /* cause is timer clk 1M hz and apb is 150M hz */ + /* check current cnt for it is disabled */ + while (GET_REG((REG_TIMER_CUR_VAL(SIMPLE_TIMER_BASE))) != 0) { + sync_cnt++; + if (sync_cnt >= 50) { + /* typical cnt is 5 when in 1M timer clk */ + /* so here use 50 to check whether it is err */ + pr_err("timer problem,can't disable"); + } + } + SET_REG((REG_TIMER_LOADCNT(SIMPLE_TIMER_BASE)), cycles); + SET_REG_M((REG_TIMER_CTRL_REG(SIMPLE_TIMER_BASE)), 0x01, 0x1); + +} + +int fh_simple_timer_create(struct fh_simple_timer* new) +{ + timerqueue_init(&new->node); + new->node.expires = new->it_value; + timerqueue_add(&base.simple_timer_queue, &new->node); + return 0; +} +EXPORT_SYMBOL_GPL(fh_simple_timer_create); + +int fh_timer_start(void) +{ + struct fh_simple_timer *timer = NULL; + struct timerqueue_node *node; + + if (base.state == SIMPLE_TIMER_START) + return 0; + + + node = timerqueue_getnext(&base.simple_timer_queue); + + if(node == NULL) + { + pr_err("ERROR: timequeue is empty\n"); + return -1; + } + base.workmode = SIMPLE_TIMER_SEQ; + timer = container_of(node, struct fh_simple_timer, node); + + base.state = SIMPLE_TIMER_START; + fh_timer_enable(); + fh_simple_timer_set_next(ktime_to_us(ktime_sub(timer->it_value, timer->it_delay))); + return 0; +} +EXPORT_SYMBOL_GPL(fh_timer_start); + +int fh_simple_timer_interrupt_seq(void) +{ + ktime_t diff; + struct fh_simple_timer *curr = NULL, *next = NULL; + struct timerqueue_node *node; + + node = timerqueue_getnext(&base.simple_timer_queue); + + if(node == NULL) + { + pr_err("ERROR: timequeue is empty\n"); + fh_timer_clearirq(); + fh_timer_disable(); + base.state = SIMPLE_TIMER_ERROR; + return -1; + } + + curr = container_of(node, struct fh_simple_timer, node); + + timerqueue_del(&base.simple_timer_queue, &curr->node); + + curr->function(curr->param); + + node = timerqueue_getnext(&base.simple_timer_queue); + + if(node == NULL) + { + PRINT_DBG("finished all timers, close device\n"); + fh_timer_clearirq(); + fh_timer_disable(); + base.state = SIMPLE_TIMER_STOP; + return 0; + } + + next = container_of(node, struct fh_simple_timer, node); + + PRINT_DBG("sec: %lu, nsec: %lu\n", + ktime_to_timespec(next->it_value).tv_sec, + ktime_to_timespec(next->it_value).tv_nsec); + + diff = ktime_sub(next->it_value, curr->it_value); + + fh_simple_timer_set_next(ktime_to_us(ktime_sub(diff, next->it_delay))); + fh_timer_clearirq(); + return 0; +} +int fh_simple_timer_interrupt_period(void) +{ + + periodic_timer.function(periodic_timer.param); + fh_timer_clearirq(); + return 0; +} + +int fh_simple_timer_interrupt(void) +{ + if (base.workmode == SIMPLE_TIMER_SEQ) + return fh_simple_timer_interrupt_seq(); + else + return fh_simple_timer_interrupt_period(); +} + + +int fh_simple_timer_init(unsigned int regbase,unsigned int clkbase) +{ + base.state = SIMPLE_TIMER_STOP; + stmr_regbase = regbase; + if (clkbase % 1000000 != 0 || clkbase < 1000000) { + pr_err("simple timer clk not support %u\n",clkbase); + stmr_clkbase = 1; + } else { + stmr_clkbase = clkbase/1000000; + } + timerqueue_init_head(&base.simple_timer_queue); + memset(&periodic_timer, 0, sizeof(periodic_timer)); + fh_timer_disable(); + return 0; +} +EXPORT_SYMBOL_GPL(fh_simple_timer_init); + + +int fh_simple_timer_periodic_start(struct fh_simple_timer *tim) +{ + + if (base.state == SIMPLE_TIMER_START) + return 0; + + if (tim == NULL) + return 0; + + periodic_timer = *tim; + + + + base.state = SIMPLE_TIMER_START; + base.workmode = SIMPLE_TIMER_PERIOD; + fh_timer_enable(); + fh_simple_timer_set_next(ktime_to_us(ktime_sub(periodic_timer.it_value, + periodic_timer.it_delay))); + + return 0; +} +EXPORT_SYMBOL_GPL(fh_simple_timer_periodic_start); +int fh_simple_timer_periodic_stop(void) +{ + fh_timer_disable(); + base.state = SIMPLE_TIMER_STOP; + + return 0; +} +EXPORT_SYMBOL_GPL(fh_simple_timer_periodic_stop); + diff --git a/drivers/clocksource/timer-fh.c b/drivers/clocksource/timer-fh.c new file mode 100644 index 00000000..109b2986 --- /dev/null +++ b/drivers/clocksource/timer-fh.c @@ -0,0 +1,771 @@ +/* + * FH timer subsystem + * + * Copyright (C) 2014 Fullhan Microelectronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +static struct clocksource *g_cs; + +#ifdef CONFIG_ARCH_FH865x +#define TMR_CLK (50000000) +#else +#define TMR_CLK (1000000) +#endif + + +#define OFFSET_TIMER_LOADCNT (0x00) +#define OFFSET_TIMER_CUR_VAL (0x04) +#define OFFSET_TIMER_CTRL_REG (0x08) +#define OFFSET_TIMER_EOI_REG (0x0C) +#define OFFSET_TIMER_INTSTATUS (0x10) + +#define OFFSET_TIMERS_INTSTATUS (0xa0) + +#define TMR_CONTROL_ENABLE (1 << 0) +/* 1: periodic, 0:free running. */ +#define TMR_CONTROL_MODE_PERIODIC (1 << 1) +#define TMR_CONTROL_INT (1 << 2) + +struct fh_timer { + void __iomem *base; + unsigned long freq; + int irq; +}; + +struct fh_timer_clock_event_device { + struct clock_event_device ced; + struct fh_timer timer; + struct irqaction irqaction; + void (*eoi)(struct fh_timer *); +}; + +struct fh_timer_clocksource { + struct fh_timer timer; + struct clocksource cs; +}; + + + + +#if defined(CONFIG_SMP) +struct clock_event_device fh_bc_tmrevt; +#endif + +static inline struct fh_timer_clock_event_device * +ced_to_fh_timer_ced(struct clock_event_device *evt) +{ + return container_of(evt, struct fh_timer_clock_event_device, ced); +} + +static inline struct fh_timer_clocksource * +clocksource_to_fh_timer_clocksource(struct clocksource *cs) +{ + return container_of(cs, struct fh_timer_clocksource, cs); +} + +/** + * fh_timer_clocksource_read() - read the current value of a clocksource. + * + * @fh_cs: The clocksource to read. + */ +cycle_t fh_timer_clocksource_read(struct fh_timer_clocksource *fh_cs) +{ + return (cycle_t)~(readl(fh_cs->timer.base + OFFSET_TIMER_CUR_VAL)); +} + +static cycle_t fh_timer_read_clocksource(struct clocksource *cs) +{ + unsigned long current_count; + struct fh_timer_clocksource *fh_cs = + clocksource_to_fh_timer_clocksource(cs); + + current_count = ~(readl(fh_cs->timer.base + OFFSET_TIMER_CUR_VAL)); + + return current_count; +} + +/** + * fh_timer_clocksource_start() - start the clocksource counting. + * + * @fh_cs: The clocksource to start. + * + * This is used to start the clocksource before registration and can be used + * to enable calibration of timers. + */ +void fh_timer_clocksource_start(struct fh_timer_clocksource *fh_cs) +{ + /* + * start count down from 0xffff_ffff. this is done by toggling the + * enable bit then load initial load count to ~0. + */ + unsigned long ctrl = readl(fh_cs->timer.base + OFFSET_TIMER_CTRL_REG); + + ctrl &= ~TMR_CONTROL_ENABLE; + writel(ctrl, fh_cs->timer.base + OFFSET_TIMER_CTRL_REG); + writel(~0, fh_cs->timer.base + OFFSET_TIMER_LOADCNT); + /* enable, mask interrupt */ + ctrl &= ~TMR_CONTROL_MODE_PERIODIC; + ctrl |= (TMR_CONTROL_ENABLE | TMR_CONTROL_INT); + writel(ctrl, fh_cs->timer.base + OFFSET_TIMER_CTRL_REG); + /* read it once to get cached counter value initialized */ + fh_timer_clocksource_read(fh_cs); +} + +void fh_timer_clock_start(struct fh_timer *timer) +{ + /* + * start count down from 0xffff_ffff. this is done by toggling the + * enable bit then load initial load count to ~0. + */ + unsigned long ctrl = readl(timer->base + OFFSET_TIMER_CTRL_REG); + + ctrl &= ~TMR_CONTROL_ENABLE; + writel(ctrl, timer->base + OFFSET_TIMER_CTRL_REG); + writel(~0, timer->base + OFFSET_TIMER_LOADCNT); + /* enable, mask interrupt */ + ctrl &= ~TMR_CONTROL_MODE_PERIODIC; + ctrl |= (TMR_CONTROL_ENABLE | TMR_CONTROL_INT); + writel(ctrl, timer->base + OFFSET_TIMER_CTRL_REG); + /* read it once to get cached counter value initialized */ + readl(timer->base + OFFSET_TIMER_CUR_VAL); +} + +static void fh_timer_restart_clocksource(struct clocksource *cs) +{ + struct fh_timer_clocksource *fh_cs = + clocksource_to_fh_timer_clocksource(cs); + + fh_timer_clocksource_start(fh_cs); +} + +static void __init timer_get_base_and_rate(struct device_node *np, + int type, void __iomem **base, u32 *rate) +{ + struct clk *timer_clk; +#ifdef CONFIG_USE_OF + *base = of_iomap(np, 0); + + if (!*base) + pr_err("Unable to map regs for %s", np->name); + + timer_clk = clk_get(NULL, "tmr0_clk"); + + + if (!of_property_read_u32(np, "clock-frequency", rate)) { + if (!IS_ERR(timer_clk)) { + clk_set_rate(timer_clk, *rate); + clk_prepare_enable(timer_clk); + } else { + pr_err("No clock for %s", np->name); + } + } else { + pr_err(" No clock-frequency property for %s", np->name); + *rate = 0; + } +#else + timer_clk = clk_get(NULL, "tmr0_clk"); + if (!IS_ERR(timer_clk)) { + *rate = TMR_CLK; + clk_set_rate(timer_clk, *rate); + clk_prepare_enable(timer_clk); + } else + *rate = 1000000; + + if (type == 1) + *base = (void __iomem *)(((unsigned int)*base)+0x14); + +#endif + +} + +static void fh_timer_eoi(struct fh_timer *timer) +{ +#ifdef CONFIG_ARM_FULLHAN_CPUIDLE + extern void fhca7_wakeup_cpu(unsigned int cpu); + fhca7_wakeup_cpu(1); +#endif + readl(timer->base + OFFSET_TIMER_EOI_REG); +} + +static irqreturn_t fh_timer_clockevent_irq(int irq, void *data) +{ + struct clock_event_device *evt = data; + struct fh_timer_clock_event_device *fh_ced = ced_to_fh_timer_ced(evt); + +#ifdef CONFIG_FH_SIMPLE_TIMER + unsigned int status = + readl(fh_ced->timer.base + OFFSET_TIMERS_INTSTATUS); + + if (status & (1 << SIMPLE_TIMER_BASE)) + fh_simple_timer_interrupt(); +#endif + + + if (!evt->event_handler) { + pr_info("Spurious FH timer interrupt %d", irq); + return IRQ_NONE; + } + + if (fh_ced->eoi) + fh_ced->eoi(&fh_ced->timer); + + evt->event_handler(evt); +#if defined(CONFIG_SMP) + if (fh_bc_tmrevt.broadcast != NULL) + fh_bc_tmrevt.broadcast(fh_bc_tmrevt.cpumask); + +#endif + return IRQ_HANDLED; +} +static irqreturn_t fh_bc_timer_clockevent_irq(int irq, void *data) +{ + struct clock_event_device *evt = data; + struct fh_timer_clock_event_device *fh_ced = ced_to_fh_timer_ced(evt); + + if (!evt->event_handler) { + pr_info("Spurious FH bc timer interrupt %d", irq); + return IRQ_NONE; + } + + if (fh_ced->eoi) + fh_ced->eoi(&fh_ced->timer); + + evt->event_handler(evt); + return IRQ_HANDLED; +} + + + + +static void fh_timer_enable_int(struct fh_timer *timer) +{ + unsigned long ctrl = readl(timer->base + OFFSET_TIMER_CTRL_REG); + /* clear pending intr */ + readl(timer->base + OFFSET_TIMER_EOI_REG); + ctrl &= ~TMR_CONTROL_INT; + writel(ctrl, timer->base + OFFSET_TIMER_CTRL_REG); +} + +static int fh_timer_set_periodic(struct clock_event_device *evt) +{ + unsigned long ctrl; + unsigned long period; + int sync_cnt = 0; + struct fh_timer_clock_event_device *fh_ced = ced_to_fh_timer_ced(evt); + + period = DIV_ROUND_UP(fh_ced->timer.freq, HZ); + ctrl = readl(fh_ced->timer.base + OFFSET_TIMER_CTRL_REG); + ctrl |= TMR_CONTROL_MODE_PERIODIC; + writel(ctrl, fh_ced->timer.base + OFFSET_TIMER_CTRL_REG); + /* + * DW APB p. 46, have to disable timer before load counter, + * may cause sync problem. + */ + ctrl &= ~TMR_CONTROL_ENABLE; + writel(ctrl, fh_ced->timer.base + OFFSET_TIMER_CTRL_REG); + while (readl(fh_ced->timer.base + OFFSET_TIMER_CUR_VAL) != 0) { + sync_cnt++; + if (sync_cnt >= 50) { + /* typical cnt is 5 when in 1M timer clk */ + /* so here use 50 to check whether it is err */ + pr_err("timer problem,can't disable"); + } + } + pr_debug("Setting clock period %lu for HZ %d\n", period, HZ); + writel(period, fh_ced->timer.base + OFFSET_TIMER_LOADCNT); + ctrl |= TMR_CONTROL_ENABLE; + ctrl &= ~TMR_CONTROL_INT; + writel(ctrl, fh_ced->timer.base + OFFSET_TIMER_CTRL_REG); + return 0; +} +static int fh_timer_set_oneshot(struct clock_event_device *evt) +{ +#if 0 + unsigned long ctrl; + unsigned long period; + struct fh_timer_clock_event_device *fh_ced = ced_to_fh_timer_ced(evt); + + + ctrl = readl(fh_ced->timer.base + OFFSET_TIMER_CTRL_REG); + /* + * set free running mode, this mode will let timer reload max + * timeout which will give time (3min on 25MHz clock) to rearm + * the next event, therefore emulate the one-shot mode. + */ + ctrl &= ~TMR_CONTROL_ENABLE; + ctrl &= ~TMR_CONTROL_MODE_PERIODIC; + + writel(ctrl, fh_ced->timer.base + OFFSET_TIMER_CTRL_REG); + /* write again to set free running mode */ + writel(ctrl, fh_ced->timer.base + OFFSET_TIMER_CTRL_REG); + + /* + * DW APB p. 46, load counter with all 1s before starting free + * running mode. + */ + writel(~0, fh_ced->timer.base + OFFSET_TIMER_LOADCNT); + ctrl &= ~TMR_CONTROL_INT; + ctrl |= TMR_CONTROL_ENABLE; + writel(ctrl, fh_ced->timer.base + OFFSET_TIMER_CTRL_REG); +#endif + return 0; +} + +static int fh_timer_set_oneshot_stopped(struct clock_event_device *evt) +{ + unsigned long ctrl; + struct fh_timer_clock_event_device *fh_ced = ced_to_fh_timer_ced(evt); + + ctrl = readl(fh_ced->timer.base + OFFSET_TIMER_CTRL_REG); + ctrl &= ~TMR_CONTROL_ENABLE; + writel(ctrl, fh_ced->timer.base + OFFSET_TIMER_CTRL_REG); + return 0; +} + +static int fh_timer_set_shutdown(struct clock_event_device *evt) +{ + unsigned long ctrl; + struct fh_timer_clock_event_device *fh_ced = ced_to_fh_timer_ced(evt); + + ctrl = readl(fh_ced->timer.base + OFFSET_TIMER_CTRL_REG); + ctrl &= ~TMR_CONTROL_ENABLE; + writel(ctrl, fh_ced->timer.base + OFFSET_TIMER_CTRL_REG); + return 0; +} + +static int fh_timer_tick_resume(struct clock_event_device *evt) +{ + struct fh_timer_clock_event_device *fh_ced = ced_to_fh_timer_ced(evt); + + fh_timer_enable_int(&fh_ced->timer); + return 0; +} + + + +static int fh_timer_next_event(unsigned long delta, + struct clock_event_device *evt) +{ + unsigned long ctrl; + int sync_cnt = 0; + struct fh_timer_clock_event_device *fh_ced = ced_to_fh_timer_ced(evt); + + /* Disable timer */ + ctrl = readl(fh_ced->timer.base + OFFSET_TIMER_CTRL_REG); + ctrl &= ~TMR_CONTROL_ENABLE; + writel(ctrl, fh_ced->timer.base + OFFSET_TIMER_CTRL_REG); + /* zy/ticket/100 : update apb Timer LOADCNT */ + /* CURRENTVALE could,t be start from new LOADCOUNT */ + /* cause is timer clk 1M hz and apb is 150M hz */ + /* keep disable for 3us to ensure timer detect it */ + while (readl(fh_ced->timer.base + OFFSET_TIMER_CUR_VAL) != 0) { + sync_cnt++; + if (sync_cnt >= 50) { + /* typical cnt is 5 when in 1M timer clk */ + /* so here use 50 to check whether it is err */ + pr_err("timer problem,can't disable"); + } + } + /* write new count */ + writel(delta, fh_ced->timer.base + OFFSET_TIMER_LOADCNT); + ctrl |= TMR_CONTROL_ENABLE; + writel(ctrl, fh_ced->timer.base + OFFSET_TIMER_CTRL_REG); + + return 0; +} + + +/** + * fh_timer_clockevent_init() - use an fh timer as a clock_event_device + * + * @cpu: The CPU the events will be targeted at. + * @name: The name used for the timer and the IRQ for it. + * @rating: The rating to give the timer. + * @base: I/O base for the timer registers. + * @irq: The interrupt number to use for the timer. + * @freq: The frequency that the timer counts at. + * + * This creates a clock_event_device for using with the generic clock layer + * but does not start and register it. This should be done with + * fh_timer_clockevent_register() as the next step. If this is the first time + * it has been called for a timer then the IRQ will be requested, if not it + * just be enabled to allow CPU hotplug to avoid repeatedly requesting and + * releasing the IRQ. + */ +struct fh_timer_clock_event_device * +fh_timer_clockevent_init(int cpu, const char *name, unsigned int rating, + void __iomem *base, int irq, unsigned long freq) +{ + struct fh_timer_clock_event_device *fh_ced = + kzalloc(sizeof(*fh_ced), GFP_KERNEL); + int err; + + if (!fh_ced) + return NULL; + + fh_ced->timer.base = base; + fh_ced->timer.irq = irq; + fh_ced->timer.freq = freq; + /* TODO: maxsec == 4 ? */ + clockevents_calc_mult_shift(&fh_ced->ced, freq, 4); + fh_ced->ced.max_delta_ns = clockevent_delta2ns(0x7fffffff, + &fh_ced->ced); + fh_ced->ced.min_delta_ns = clockevent_delta2ns(0xf, &fh_ced->ced); + fh_ced->ced.cpumask = cpumask_of(cpu); + fh_ced->ced.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; + fh_ced->ced.set_state_periodic = fh_timer_set_periodic; + fh_ced->ced.set_state_oneshot = fh_timer_set_oneshot; + fh_ced->ced.set_state_oneshot_stopped = fh_timer_set_oneshot_stopped; + fh_ced->ced.set_state_shutdown = fh_timer_set_shutdown; + fh_ced->ced.tick_resume = fh_timer_tick_resume; + + + + fh_ced->ced.set_next_event = fh_timer_next_event; + fh_ced->ced.irq = fh_ced->timer.irq; + fh_ced->ced.rating = rating; + fh_ced->ced.name = name; + + fh_ced->irqaction.name = fh_ced->ced.name; + fh_ced->irqaction.handler = fh_timer_clockevent_irq; + fh_ced->irqaction.dev_id = &fh_ced->ced; + fh_ced->irqaction.irq = irq; + fh_ced->irqaction.flags = IRQF_TIMER | IRQF_IRQPOLL | + IRQF_NOBALANCING; + + fh_ced->eoi = fh_timer_eoi; + + err = setup_irq(irq, &fh_ced->irqaction); + if (err) { + pr_err("failed to request timer irq\n"); + kfree(fh_ced); + fh_ced = NULL; + } + + return fh_ced; +} + +struct fh_timer_clock_event_device * +fh_timer_bc_clockevent_init(int cpu, const char *name, unsigned int rating, + void __iomem *base, int irq, unsigned long freq) +{ + struct fh_timer_clock_event_device *fh_ced = + kzalloc(sizeof(*fh_ced), GFP_KERNEL); + int err; + + if (!fh_ced) + return NULL; + + fh_ced->timer.base = base; + fh_ced->timer.irq = irq; + fh_ced->timer.freq = freq; + /* TODO: maxsec == 4 ? */ + clockevents_calc_mult_shift(&fh_ced->ced, freq, 4); + fh_ced->ced.max_delta_ns = clockevent_delta2ns(0x7fffffff, + &fh_ced->ced); + fh_ced->ced.min_delta_ns = clockevent_delta2ns(0xf, &fh_ced->ced); + fh_ced->ced.cpumask = cpu_all_mask; + fh_ced->ced.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; + fh_ced->ced.set_state_periodic = fh_timer_set_periodic; + fh_ced->ced.set_state_oneshot = fh_timer_set_oneshot; + fh_ced->ced.set_state_oneshot_stopped = fh_timer_set_oneshot_stopped; + fh_ced->ced.set_state_shutdown = fh_timer_set_shutdown; + fh_ced->ced.tick_resume = fh_timer_tick_resume; + + + + fh_ced->ced.set_next_event = fh_timer_next_event; + fh_ced->ced.irq = fh_ced->timer.irq; + fh_ced->ced.rating = rating; + fh_ced->ced.name = "fh_bc_timer"; + + fh_ced->irqaction.name = fh_ced->ced.name; + fh_ced->irqaction.handler = fh_bc_timer_clockevent_irq; + fh_ced->irqaction.dev_id = &fh_ced->ced; + fh_ced->irqaction.irq = irq; + fh_ced->irqaction.flags = IRQF_TIMER | IRQF_IRQPOLL | + IRQF_NOBALANCING; + + + + fh_ced->eoi = fh_timer_eoi; + + err = setup_irq(irq, &fh_ced->irqaction); + if (err) { + pr_err("failed to request timer irq\n"); + kfree(fh_ced); + fh_ced = NULL; + } + + return fh_ced; +} + +static unsigned long fh_read_current_timer(void) +{ + return g_cs->read(g_cs); +} + +static struct delay_timer fh_delay_timer = { + .read_current_timer = fh_read_current_timer, +}; + +/** + * fh_timer_clocksource_init() - use an fh timer as a clocksource. + * + * @rating: The rating to give the clocksource. + * @name: The name for the clocksource. + * @base: The I/O base for the timer registers. + * @freq: The frequency that the timer counts at. + * + * This creates a clocksource using an APB timer but does not yet register it + * with the clocksource system. This should be done with + * fh_timer_clocksource_register() as the next step. + */ +struct fh_timer_clocksource * +fh_timer_clocksource_init(unsigned int rating, const char *name, + void __iomem *base, unsigned long freq) +{ + struct fh_timer_clocksource *fh_cs = + kzalloc(sizeof(*fh_cs), GFP_KERNEL); + + if (!fh_cs) + return NULL; + + fh_cs->timer.base = base; + fh_cs->timer.freq = freq; + fh_cs->cs.name = name; + fh_cs->cs.rating = rating; + fh_cs->cs.read = fh_timer_read_clocksource; + fh_cs->cs.mask = CLOCKSOURCE_MASK(32); + fh_cs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; + fh_cs->cs.resume = fh_timer_restart_clocksource; + + g_cs = &fh_cs->cs; + + fh_delay_timer.freq = freq; + register_current_timer_delay(&fh_delay_timer); + + return fh_cs; +} +/** + * fh_timer_clockevent_register() - register the clock with the generic layer + * + * @fh_ced: The fh clock to register as a clock_event_device. + */ +void fh_timer_clockevent_register(struct fh_timer_clock_event_device *fh_ced) +{ +#if defined(CONFIG_SMP) + int cpu = 0; + static struct cpumask bcmask; +#endif + writel(0, fh_ced->timer.base + OFFSET_TIMER_CTRL_REG); + clockevents_register_device(&fh_ced->ced); + fh_timer_enable_int(&fh_ced->timer); + +#if defined(CONFIG_SMP) + for_each_cpu(cpu, cpu_all_mask) { + if (cpu != 0) + cpumask_set_cpu(cpu, &bcmask); + } + /* register broadcast evt */ + fh_bc_tmrevt.name = "fh_broadcast_timer"; + fh_bc_tmrevt.cpumask = &bcmask; + fh_bc_tmrevt.rating = 300; + fh_bc_tmrevt.broadcast = tick_broadcast; + clockevents_register_device(&fh_bc_tmrevt); +#endif +} +void fh_bc_timer_clockevent_register(struct fh_timer_clock_event_device *fh_ced) +{ + writel(0, fh_ced->timer.base + OFFSET_TIMER_CTRL_REG); + clockevents_register_device(&fh_ced->ced); + fh_timer_enable_int(&fh_ced->timer); + +} + + +/** + * fh_timer_clocksource_register() - register the fh clocksource. + * + * @fh_cs: The clocksource to register. + */ +void fh_timer_clocksource_register(struct fh_timer_clocksource *fh_cs) +{ + clocksource_register_hz(&fh_cs->cs, fh_cs->timer.freq); +} + +void __init add_clockevent(struct device_node *event_timer, + unsigned int iovbase, unsigned int irqno) +{ + void __iomem *iobase = (void __iomem *)iovbase; + struct fh_timer_clock_event_device *ced; + u32 irq, rate; + const char *name = "timer0"; + irq = irq_of_parse_and_map(event_timer, 0); + if (irq == 0) /* no use_of */ + irq = irq_create_mapping(NULL, irqno); + + if (irq == 0) + panic("No IRQ for clock event timer"); + + if (event_timer != NULL) + name = event_timer->name; + + timer_get_base_and_rate(event_timer, 0, &iobase, &rate); + ced = fh_timer_clockevent_init(0, name, 300, iobase, irq, + rate); +#ifdef CONFIG_FH_SIMPLE_TIMER + fh_simple_timer_init((unsigned int)iobase, rate); +#endif + + + if (!ced) + panic("Unable to initialise clockevent device"); + + fh_timer_clockevent_register(ced); +} + +static void clk_event_handle(struct clock_event_device *evt) +{ +} + +void __init add_bc_clockevent(struct device_node *event_timer, + unsigned int iovbase, unsigned int irqno) +{ + void __iomem *iobase = (void __iomem *)iovbase; + struct fh_timer_clock_event_device *ced; + u32 irq, rate; + const char *name = "timer0"; + + irq = irq_of_parse_and_map(event_timer, 0); + if (irq == 0) /* no use_of */ + irq = irq_create_mapping(NULL, irqno); + + + if (irq == 0) + panic("No IRQ for clock event timer"); + + timer_get_base_and_rate(event_timer, 0, &iobase, &rate); + if (event_timer != NULL) + name = event_timer->name; + + + ced = fh_timer_bc_clockevent_init(0, name, + 300, iobase, irq, rate); + ced->ced.event_handler = clk_event_handle; + if (!ced) + panic("Unable to initialise clockevent device"); + + fh_bc_timer_clockevent_register(ced); +#ifdef CONFIG_ARM_FULLHAN_CPUIDLE + fh_timer_clock_start(&ced->timer); + fh_timer_set_periodic(&ced->ced); +#endif +} + +static void __iomem *sched_io_base; +static u32 sched_rate; + +void __init add_clocksource(struct device_node *source_timer, + unsigned int iovbase, unsigned int irqno) +{ + void __iomem *iobase = (void __iomem *)iovbase; + struct fh_timer_clocksource *cs; + u32 rate; + const char *name = "timer1"; + + if (source_timer != NULL) + name = source_timer->name; + + + timer_get_base_and_rate(source_timer, 1, &iobase, &rate); + cs = fh_timer_clocksource_init(300, name, iobase, rate); + + if (!cs) + panic("Unable to initialize clocksource device"); + + fh_timer_clocksource_start(cs); + fh_timer_clocksource_register(cs); + + /* + * Fallback to use the clocksource as sched_clock if no separate + * timer is found. sched_io_base then points to the current_value + * register of the clocksource timer. + */ + sched_io_base = iobase + 0x04; + + sched_rate = rate; + +} + +static u64 notrace read_sched_clock(void) +{ + return ~__raw_readl(sched_io_base); +} + +void __init init_sched_clock(void) +{ + sched_clock_register(read_sched_clock, 32, sched_rate); +} + +static int num_called; +static int __init fh_timer_init(struct device_node *timer) +{ + pr_debug("%s-%d\n", __func__, __LINE__); + switch (num_called) { +#if defined(CONFIG_HAVE_ARM_ARCH_TIMER) && defined(CONFIG_SMP) + case 0: + add_bc_clockevent(timer, 0, 0); + /* CREATE BroadCast Timer Only */ + default: + break; + } +#else + case 0: + pr_debug("%s: found clocksource timer\n", __func__); + add_clocksource(timer, 0, 0); + init_sched_clock(); + break; + case 1: + pr_debug("%s: found clockevent timer\n", __func__); + add_clockevent(timer, 0, 0); + break; + default: + break; + } +#endif + num_called++; + return 0; +} +CLOCKSOURCE_OF_DECLARE(fh_timer, "fh,fh-timer", fh_timer_init); + + +void __init fh_timer_init_no_of(unsigned int iovbase, + unsigned int irqno) +{ + add_clocksource(NULL, iovbase, irqno); + init_sched_clock(); + add_clockevent(NULL, iovbase, irqno); +} + diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm index 21340e0b..deb7a27a 100644 --- a/drivers/cpuidle/Kconfig.arm +++ b/drivers/cpuidle/Kconfig.arm @@ -11,6 +11,12 @@ config ARM_CPUIDLE initialized by calling the CPU operations init idle hook provided by architecture code. +config ARM_FULLHAN_CPUIDLE + bool "Fullhan CPU Idle Driver" + depends on ARCH_FULLHAN + help + Select this to enable cpuidle for Fullhan processors + config ARM_BIG_LITTLE_CPUIDLE bool "Support for ARM big.LITTLE processors" depends on ARCH_VEXPRESS_TC2_PM || ARCH_EXYNOS diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 4d2b81f2..ef622402 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -18,7 +18,7 @@ config CRYPTO_DEV_PADLOCK (so called VIA PadLock ACE, Advanced Cryptography Engine) that provides instructions for very fast cryptographic operations with supported algorithms. - + The instructions are used only when the CPU supports them. Otherwise software encryption is used. @@ -202,6 +202,10 @@ config CRYPTO_DEV_MARVELL_CESA This driver is aimed at replacing the mv_cesa driver. This will only happen once it has received proper testing. +config FH_CESA_SELF_TEST + bool "fh cesa self test" + depends on CRYPTO_DEV_FH_CESA + config CRYPTO_DEV_NIAGARA2 tristate "Niagara2 Stream Processing Unit driver" select CRYPTO_DES @@ -555,4 +559,39 @@ config CRYPTO_DEV_ROCKCHIP source "drivers/crypto/chelsio/Kconfig" +choice + bool "FH AES driver select" + default CRYPTO_DEV_FH_AES + +config CRYPTO_DEV_FH_AES + tristate "FH AES support(original)" +# select CRYPTO_BLKCIPHER +# select CRYPTO_SEQIV + + help + To compile this driver as a module, choose M here: the module will + be called fh_aes. + +config CRYPTO_DEV_FH_AES_TEE + tristate "FH AES driver for tee" + depends on TEE + + select CRYPTO_BLKCIPHER + select CRYPTO_SEQIV + help + the FH_AES_TEE driver can be chosen when tee is on. + +endchoice + +config CRYPTO_FH_AES_SUPPORT_DIRECT_MEM + bool "direct mem support" + depends on CRYPTO_DEV_FH_AES || CRYPTO_DEV_FH_AES_TEE + help + usr send direct mem to driver. + + +config FH_AES_SELF_TEST + bool "fh aes self test" + depends on CRYPTO_DEV_FH_AES || CRYPTO_DEV_FH_AES_TEE + endif # CRYPTO_HW diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index ad7250fa..420761fc 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -32,3 +32,7 @@ obj-$(CONFIG_CRYPTO_DEV_VMX) += vmx/ obj-$(CONFIG_CRYPTO_DEV_SUN4I_SS) += sunxi-ss/ obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rockchip/ obj-$(CONFIG_CRYPTO_DEV_CHELSIO) += chelsio/ +obj-$(CONFIG_CRYPTO_DEV_FH_AES) += fh_aes.o +obj-$(CONFIG_CRYPTO_DEV_FH_AES_TEE) += fh_aes_tee.o +obj-$(CONFIG_FH_AES_SELF_TEST) += fh_aes_test.o +ccflags-y += -I$(srctree)/drivers/tee/tee_api diff --git a/drivers/crypto/fh_aes.c b/drivers/crypto/fh_aes.c new file mode 100644 index 00000000..0d902e2b --- /dev/null +++ b/drivers/crypto/fh_aes.c @@ -0,0 +1,1629 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "fh_aes.h" +#include +#include +/***************************************************************************** + * Define section + * add all #define here + *****************************************************************************/ + +#define CRYPTO_QUEUE_LEN (1000) +#define CRYPTION_POS (0) +#define METHOD_POS (1) +#define EMODE_POS (4) + +#define aes_readl(aes, name) \ + __raw_readl(&(((struct fh_aes_reg *)aes->regs)->name)) + +#define aes_writel(aes, name, val) \ + __raw_writel((val), &(((struct fh_aes_reg *)aes->regs)->name)) + +#define aes_readw(aes, name) \ + __raw_readw(&(((struct fh_aes_reg *)aes->regs)->name)) + +#define aes_writew(aes, name, val) \ + __raw_writew((val), &(((struct fh_aes_reg *)aes->regs)->name)) + +#define aes_readb(aes, name) \ + __raw_readb(&(((struct fh_aes_reg *)aes->regs)->name)) + +#define aes_writeb(aes, name, val) \ + __raw_writeb((val), &(((struct fh_aes_reg *)aes->regs)->name)) + + +#ifdef CONFIG_FH_EFUSE +#define FH_AESV2 +#else +#undef FH_AESV2 +#endif + +#define FH_AES_ALLIGN_SIZE 64 +/* +crypto max malloc the buf size is 4096 for one sg, +here just cpy all the data to driver pri buf. +*/ +#define FH_AES_MALLOC_SIZE 2048 +#define FH_AES_CTL_MAX_PROCESS_SIZE (FH_AES_MALLOC_SIZE) + +#ifdef FH_AESV2 +#include +extern struct wrap_efuse_obj s_efuse_obj; +#endif +/**************************************************************************** + * ADT section + * add definition of user defined Data Type that only be used in this file here + ***************************************************************************/ +enum { + ENCRYPT = 0 << CRYPTION_POS, + DECRYPT = 1 << CRYPTION_POS, +}; + +enum { + ECB_MODE = 0 << EMODE_POS, + CBC_MODE = 1 << EMODE_POS, + CTR_MODE = 2 << EMODE_POS, + CFB_MODE = 4 << EMODE_POS, + OFB_MODE = 5 << EMODE_POS, +}; + +enum { + DES_METHOD = 0 << METHOD_POS, + TRIPLE_DES_METHOD = 1 << METHOD_POS, + AES_128_METHOD = 4 << METHOD_POS, + AES_192_METHOD = 5 << METHOD_POS, + AES_256_METHOD = 6 << METHOD_POS, +}; + +/***************************************************************************** + + * static fun; + *****************************************************************************/ + +static int fh_aes_handle_req(struct fh_aes_dev *dev, + struct ablkcipher_request *req); +/*aes*/ +static int fh_aes_crypt(struct ablkcipher_request *req, unsigned long mode); +static int fh_aes_ecb_encrypt(struct ablkcipher_request *req); +static int fh_aes_ecb_decrypt(struct ablkcipher_request *req); +static int fh_aes_cbc_encrypt(struct ablkcipher_request *req); +static int fh_aes_cbc_decrypt(struct ablkcipher_request *req); +static int fh_aes_ctr_encrypt(struct ablkcipher_request *req); +static int fh_aes_ctr_decrypt(struct ablkcipher_request *req); +static int fh_aes_ofb_encrypt(struct ablkcipher_request *req); +static int fh_aes_ofb_decrypt(struct ablkcipher_request *req); +static int fh_aes_cfb_encrypt(struct ablkcipher_request *req); +static int fh_aes_cfb_decrypt(struct ablkcipher_request *req); + +/*des*/ +static int fh_des_ecb_encrypt(struct ablkcipher_request *req); +static int fh_des_ecb_decrypt(struct ablkcipher_request *req); +static int fh_des_cbc_encrypt(struct ablkcipher_request *req); +static int fh_des_cbc_decrypt(struct ablkcipher_request *req); +static int fh_des_ofb_encrypt(struct ablkcipher_request *req); +static int fh_des_ofb_decrypt(struct ablkcipher_request *req); +static int fh_des_cfb_encrypt(struct ablkcipher_request *req); +static int fh_des_cfb_decrypt(struct ablkcipher_request *req); + +/*tri des*/ +static int fh_des_tri_ecb_encrypt(struct ablkcipher_request *req); +static int fh_des_tri_ecb_decrypt(struct ablkcipher_request *req); +static int fh_des_tri_cbc_encrypt(struct ablkcipher_request *req); +static int fh_des_tri_cbc_decrypt(struct ablkcipher_request *req); +static int fh_des_tri_ofb_encrypt(struct ablkcipher_request *req); +static int fh_des_tri_ofb_decrypt(struct ablkcipher_request *req); +static int fh_des_tri_cfb_encrypt(struct ablkcipher_request *req); +static int fh_des_tri_cfb_decrypt(struct ablkcipher_request *req); +static int fh_aes_setkey(struct crypto_ablkcipher *cipher, const uint8_t *key, + unsigned int keylen); +static int fh_aes_cra_init(struct crypto_tfm *tfm); +static void fh_aes_tx(struct fh_aes_dev *dev); +static void fh_aes_rx(struct fh_aes_dev *dev); +static irqreturn_t fh_aes_interrupt(int irq, void *dev_id); +static void aes_biglittle_swap(u8 *buf); +static int fh_set_indata(struct fh_aes_dev *dev, struct scatterlist *sg); +static int fh_set_outdata(struct fh_aes_dev *dev, struct scatterlist *sg); +static void fh_set_aes_key_reg(struct fh_aes_dev *dev, uint8_t *key, + uint8_t *iv, unsigned int keylen); +static void fh_set_dma_indata(struct fh_aes_dev *dev, + struct scatterlist *sg); +static void fh_set_dma_outdata(struct fh_aes_dev *dev, + struct scatterlist *sg); +static void fh_unset_indata(struct fh_aes_dev *dev); +static void fh_unset_outdata(struct fh_aes_dev *dev); +static void fh_aes_complete(struct fh_aes_dev *dev, int err); +static void fh_aes_crypt_start(struct fh_aes_dev *dev, unsigned long mode); +static void fh_aes_work_cb(struct work_struct *w); +static void fh_aes_crypt_with_sg(struct fh_aes_dev *dev, +unsigned long mode, struct crypto_tfm *tfm); +#define fh_des_setkey fh_aes_setkey +/***************************************************************************** + * Global variables section - Local + * define global variables(will be refered only in this file) here, + * static keyword should be used to limit scope of local variable to this file + * e.g. + * static uint8_t ufoo; + *****************************************************************************/ +struct fh_aes_dev *pobj_aes_dev = NULL; +static struct crypto_alg algs[] = { + { + .cra_name = "ecb(aes)", + .cra_driver_name = "ecb-aes-fh", + .cra_priority = 100, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct fh_aes_ctx), + .cra_alignmask = 0x0f, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = fh_aes_cra_init, + .cra_u.ablkcipher = { + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .setkey = fh_aes_setkey, + .encrypt = fh_aes_ecb_encrypt, + .decrypt = fh_aes_ecb_decrypt, + } + }, + { + .cra_name = "cbc(aes)", + .cra_driver_name = "cbc-aes-fh", + .cra_priority = 100, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, + + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct fh_aes_ctx), + .cra_alignmask = 0x0f, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = fh_aes_cra_init, + .cra_u.ablkcipher = { + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .ivsize = AES_BLOCK_SIZE, + .setkey = fh_aes_setkey, + .encrypt = fh_aes_cbc_encrypt, + .decrypt = fh_aes_cbc_decrypt, + } + }, + { + .cra_name = "ctr(aes)", + .cra_driver_name = "ctr-aes-fh", + .cra_priority = 100, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct fh_aes_ctx), + .cra_alignmask = 0x0f, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = fh_aes_cra_init, + .cra_u.ablkcipher = { + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .ivsize = AES_BLOCK_SIZE, + .setkey = fh_aes_setkey, + .encrypt = fh_aes_ctr_encrypt, + .decrypt = fh_aes_ctr_decrypt, + } + }, + { + .cra_name = "ofb(aes)", + .cra_driver_name = "ofb-aes-fh", + .cra_priority = 100, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct fh_aes_ctx), + .cra_alignmask = 0x0f, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = fh_aes_cra_init, + .cra_u.ablkcipher = { + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .ivsize = AES_BLOCK_SIZE, + .setkey = fh_aes_setkey, + .encrypt = fh_aes_ofb_encrypt, + .decrypt = fh_aes_ofb_decrypt, + } + }, + { + .cra_name = "cfb(aes)", + .cra_driver_name = "cfb-aes-fh", + .cra_priority = 100, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct fh_aes_ctx), + .cra_alignmask = 0x0f, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = fh_aes_cra_init, + .cra_u.ablkcipher = { + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .ivsize = AES_BLOCK_SIZE, + .setkey = fh_aes_setkey, + .encrypt = fh_aes_cfb_encrypt, + .decrypt = fh_aes_cfb_decrypt, + } + }, + { + .cra_name = "ecb(des)", + .cra_driver_name = "ecb-des-fh", + .cra_priority = 100, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, + + .cra_blocksize = DES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct fh_aes_ctx), + .cra_alignmask = 0x0f, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = fh_aes_cra_init, + .cra_u.ablkcipher = { + .min_keysize = DES_KEY_SIZE, + .max_keysize = DES_KEY_SIZE, + .setkey = fh_des_setkey, + .encrypt = fh_des_ecb_encrypt, + .decrypt = fh_des_ecb_decrypt, + } + }, + { + .cra_name = "cbc(des)", + .cra_driver_name = "cbc-des-fh", + .cra_priority = 100, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, + .cra_blocksize = DES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct fh_aes_ctx), + .cra_alignmask = 0x0f, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = fh_aes_cra_init, + .cra_u.ablkcipher = { + .min_keysize = DES_KEY_SIZE, + .max_keysize = DES_KEY_SIZE, + .ivsize = DES_BLOCK_SIZE, + .setkey = fh_des_setkey, + .encrypt = fh_des_cbc_encrypt, + .decrypt = fh_des_cbc_decrypt, + } + }, + { + .cra_name = "ofb(des)", + .cra_driver_name = "ofb-des-fh", + .cra_priority = 100, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, + .cra_blocksize = DES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct fh_aes_ctx), + .cra_alignmask = 0x0f, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = fh_aes_cra_init, + .cra_u.ablkcipher = { + .min_keysize = DES_KEY_SIZE, + .max_keysize = DES_KEY_SIZE, + .ivsize = DES_BLOCK_SIZE, + .setkey = fh_des_setkey, + .encrypt = fh_des_ofb_encrypt, + .decrypt = fh_des_ofb_decrypt, + } + }, + { + .cra_name = "cfb(des)", + .cra_driver_name = "cfb-des-fh", + .cra_priority = 100, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, + .cra_blocksize = DES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct fh_aes_ctx), + .cra_alignmask = 0x0f, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = fh_aes_cra_init, + .cra_u.ablkcipher = { + .min_keysize = DES_KEY_SIZE, + .max_keysize = DES_KEY_SIZE, + .ivsize = DES_BLOCK_SIZE, + .setkey = fh_des_setkey, + .encrypt = fh_des_cfb_encrypt, + .decrypt = fh_des_cfb_decrypt, + } + }, + { + .cra_name = "ecb(des3)", + .cra_driver_name = "ecb-des3-fh", + .cra_priority = 100, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, + + .cra_blocksize = DES3_EDE_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct fh_aes_ctx), + .cra_alignmask = 0x0f, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = fh_aes_cra_init, + .cra_u.ablkcipher = { + .min_keysize = DES3_EDE_KEY_SIZE, + .max_keysize = DES3_EDE_KEY_SIZE, + .setkey = fh_des_setkey, + .encrypt = fh_des_tri_ecb_encrypt, + .decrypt = fh_des_tri_ecb_decrypt, + } + }, + { + .cra_name = "cbc(des3)", + .cra_driver_name = "cbc-des3-fh", + .cra_priority = 100, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, + .cra_blocksize = DES3_EDE_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct fh_aes_ctx), + .cra_alignmask = 0x0f, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = fh_aes_cra_init, + .cra_u.ablkcipher = { + .min_keysize = DES3_EDE_KEY_SIZE, + .max_keysize = DES3_EDE_KEY_SIZE, + .ivsize = DES3_EDE_BLOCK_SIZE, + .setkey = fh_des_setkey, + .encrypt = fh_des_tri_cbc_encrypt, + .decrypt = fh_des_tri_cbc_decrypt, + } + }, + { + .cra_name = "ofb(des3)", + .cra_driver_name = "ofb-des3-fh", + .cra_priority = 100, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, + .cra_blocksize = DES3_EDE_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct fh_aes_ctx), + .cra_alignmask = 0x0f, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = fh_aes_cra_init, + .cra_u.ablkcipher = { + .min_keysize = DES3_EDE_KEY_SIZE, + .max_keysize = DES3_EDE_KEY_SIZE, + .ivsize = DES3_EDE_BLOCK_SIZE, + .setkey = fh_des_setkey, + .encrypt = fh_des_tri_ofb_encrypt, + .decrypt = fh_des_tri_ofb_decrypt, + } + }, + { + .cra_name = "cfb(des3)", + .cra_driver_name = "cfb-des3-fh", + .cra_priority = 100, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, + .cra_blocksize = DES3_EDE_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct fh_aes_ctx), + .cra_alignmask = 0x0f, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = fh_aes_cra_init, + .cra_u.ablkcipher = { + .min_keysize = DES3_EDE_KEY_SIZE, + .max_keysize = DES3_EDE_KEY_SIZE, + .ivsize = DES3_EDE_BLOCK_SIZE, + .setkey = fh_des_setkey, + .encrypt = fh_des_tri_cfb_encrypt, + .decrypt = fh_des_tri_cfb_decrypt, + } + }, +}; + +#ifdef CONFIG_FH_AES_SELF_TEST +extern void fh_aes_self_test_all(void); +#endif + +static unsigned int get_tfm_block_size(struct crypto_tfm *tfm) +{ + return tfm->__crt_alg->cra_blocksize; +} +/* function body */ +static int fh_aes_handle_req(struct fh_aes_dev *dev, + struct ablkcipher_request *req) +{ + unsigned long flags; + int err; + spin_lock_irqsave(&dev->lock, flags); + err = ablkcipher_enqueue_request(&dev->queue, req); + spin_unlock_irqrestore(&dev->lock, flags); + queue_work(dev->workqueue, &dev->work); + return err; +} + +static int fh_aes_crypt(struct ablkcipher_request *req, unsigned long mode) +{ + struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req); + struct fh_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm); + struct fh_aes_reqctx *reqctx = ablkcipher_request_ctx(req); + struct fh_aes_dev *dev = ctx->dev; + AES_DBG("%s\n", __func__); + dev->reqctx = reqctx; + /*if (!(mode & CFB_MODE)) {*/ + if ((!IS_ALIGNED(req->nbytes, AES_BLOCK_SIZE)) + && (!IS_ALIGNED(req->nbytes, DES_BLOCK_SIZE))) { + pr_err("request size is not exact amount of AES blocks\n"); + return -EINVAL; + } + /*}*/ + AES_DBG("reqctx->mode value: %x\n", (unsigned int)mode); + reqctx->mode = mode; + return fh_aes_handle_req(dev, req); +} + +static int fh_aes_ecb_encrypt(struct ablkcipher_request *req) +{ + struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req); + struct fh_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm); + u32 method = 0; + switch (ctx->keylen) { + case AES_KEYSIZE_128: + method = AES_128_METHOD; + break; + case AES_KEYSIZE_192: + method = AES_192_METHOD; + break; + case AES_KEYSIZE_256: + method = AES_256_METHOD; + break; + default: + break; + } + return fh_aes_crypt(req, method | ECB_MODE | ENCRYPT); +} + + +static int fh_aes_ecb_decrypt(struct ablkcipher_request *req) +{ + struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req); + struct fh_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm); + u32 method = 0; + + switch (ctx->keylen) { + case AES_KEYSIZE_128: + method = AES_128_METHOD; + break; + case AES_KEYSIZE_192: + method = AES_192_METHOD; + break; + case AES_KEYSIZE_256: + method = AES_256_METHOD; + break; + default: + break; + } + return fh_aes_crypt(req, method | ECB_MODE | DECRYPT); +} + +static int fh_aes_cbc_encrypt(struct ablkcipher_request *req) +{ + struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req); + struct fh_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm); + u32 method = 0; + + switch (ctx->keylen) { + case AES_KEYSIZE_128: + method = AES_128_METHOD; + break; + case AES_KEYSIZE_192: + method = AES_192_METHOD; + break; + case AES_KEYSIZE_256: + method = AES_256_METHOD; + break; + default: + break; + } + return fh_aes_crypt(req, method | CBC_MODE | ENCRYPT); +} + +static int fh_aes_cbc_decrypt(struct ablkcipher_request *req) +{ + struct crypto_ablkcipher *tfm; + struct fh_aes_ctx *ctx; + u32 method; + + tfm = crypto_ablkcipher_reqtfm(req); + ctx = crypto_ablkcipher_ctx(tfm); + method = 0; + AES_DBG("%s\n", __func__); + switch (ctx->keylen) { + case AES_KEYSIZE_128: + method = AES_128_METHOD; + break; + case AES_KEYSIZE_192: + method = AES_192_METHOD; + break; + case AES_KEYSIZE_256: + method = AES_256_METHOD; + break; + default: + break; + } + + return fh_aes_crypt(req, method | CBC_MODE | DECRYPT); +} + +static int fh_aes_ctr_encrypt(struct ablkcipher_request *req) +{ + struct crypto_ablkcipher *tfm; + struct fh_aes_ctx *ctx; + u32 method; + tfm = crypto_ablkcipher_reqtfm(req); + ctx = crypto_ablkcipher_ctx(tfm); + method = 0; + + switch (ctx->keylen) { + case AES_KEYSIZE_128: + method = AES_128_METHOD; + break; + case AES_KEYSIZE_192: + method = AES_192_METHOD; + break; + case AES_KEYSIZE_256: + method = AES_256_METHOD; + break; + default: + break; + } + + return fh_aes_crypt(req, method | CTR_MODE | ENCRYPT); +} + +static int fh_aes_ctr_decrypt(struct ablkcipher_request *req) +{ + struct crypto_ablkcipher *tfm; + struct fh_aes_ctx *ctx; + u32 method; + + tfm = crypto_ablkcipher_reqtfm(req); + ctx = crypto_ablkcipher_ctx(tfm); + method = 0; + AES_DBG("%s\n", __func__); + switch (ctx->keylen) { + case AES_KEYSIZE_128: + method = AES_128_METHOD; + break; + case AES_KEYSIZE_192: + method = AES_192_METHOD; + break; + case AES_KEYSIZE_256: + method = AES_256_METHOD; + break; + default: + break; + } + return fh_aes_crypt(req, method | CTR_MODE | DECRYPT); +} + +static int fh_aes_ofb_encrypt(struct ablkcipher_request *req) +{ + struct crypto_ablkcipher *tfm; + struct fh_aes_ctx *ctx; + u32 method; + + tfm = crypto_ablkcipher_reqtfm(req); + ctx = crypto_ablkcipher_ctx(tfm); + method = 0; + + switch (ctx->keylen) { + case AES_KEYSIZE_128: + method = AES_128_METHOD; + break; + case AES_KEYSIZE_192: + method = AES_192_METHOD; + break; + case AES_KEYSIZE_256: + method = AES_256_METHOD; + break; + default: + break; + } + return fh_aes_crypt(req, method | OFB_MODE | ENCRYPT); +} + +static int fh_aes_ofb_decrypt(struct ablkcipher_request *req) +{ + struct crypto_ablkcipher *tfm; + struct fh_aes_ctx *ctx; + u32 method; + + tfm = crypto_ablkcipher_reqtfm(req); + ctx = crypto_ablkcipher_ctx(tfm); + method = 0; + + AES_DBG("%s\n", __func__); + switch (ctx->keylen) { + case AES_KEYSIZE_128: + method = AES_128_METHOD; + break; + case AES_KEYSIZE_192: + method = AES_192_METHOD; + break; + case AES_KEYSIZE_256: + method = AES_256_METHOD; + break; + default: + break; + } + + return fh_aes_crypt(req, method | OFB_MODE | DECRYPT); +} + +static int fh_aes_cfb_encrypt(struct ablkcipher_request *req) +{ + struct crypto_ablkcipher *tfm; + struct fh_aes_ctx *ctx; + u32 method; + + tfm = crypto_ablkcipher_reqtfm(req); + ctx = crypto_ablkcipher_ctx(tfm); + method = 0; + + switch (ctx->keylen) { + case AES_KEYSIZE_128: + method = AES_128_METHOD; + break; + case AES_KEYSIZE_192: + method = AES_192_METHOD; + break; + case AES_KEYSIZE_256: + method = AES_256_METHOD; + break; + default: + break; + } + return fh_aes_crypt(req, method | CFB_MODE | ENCRYPT); +} + +static int fh_aes_cfb_decrypt(struct ablkcipher_request *req) +{ + struct crypto_ablkcipher *tfm; + struct fh_aes_ctx *ctx; + u32 method; + + tfm = crypto_ablkcipher_reqtfm(req); + ctx = crypto_ablkcipher_ctx(tfm); + method = 0; + + AES_DBG("%s\n", __func__); + switch (ctx->keylen) { + case AES_KEYSIZE_128: + method = AES_128_METHOD; + break; + case AES_KEYSIZE_192: + method = AES_192_METHOD; + break; + case AES_KEYSIZE_256: + method = AES_256_METHOD; + break; + default: + break; + } + + return fh_aes_crypt(req, method | CFB_MODE | DECRYPT); +} +static int fh_des_ecb_encrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = DES_METHOD; + + return fh_aes_crypt(req, method | ECB_MODE | ENCRYPT); +} + +static int fh_des_ecb_decrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = DES_METHOD; + + return fh_aes_crypt(req, method | ECB_MODE | DECRYPT); +} + +static int fh_des_cbc_encrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = DES_METHOD; + + return fh_aes_crypt(req, method | CBC_MODE | ENCRYPT); +} + +static int fh_des_cbc_decrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = DES_METHOD; + + return fh_aes_crypt(req, method | CBC_MODE | DECRYPT); +} + +static int fh_des_ofb_encrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = DES_METHOD; + + return fh_aes_crypt(req, method | OFB_MODE | ENCRYPT); +} + +static int fh_des_ofb_decrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = DES_METHOD; + + return fh_aes_crypt(req, method | OFB_MODE | DECRYPT); +} + +static int fh_des_cfb_encrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = DES_METHOD; + + return fh_aes_crypt(req, method | CFB_MODE | ENCRYPT); +} + +static int fh_des_cfb_decrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = DES_METHOD; + + return fh_aes_crypt(req, method | CFB_MODE | DECRYPT); +} +static int fh_des_tri_ecb_encrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = TRIPLE_DES_METHOD; + return fh_aes_crypt(req, method | ECB_MODE | ENCRYPT); +} + +static int fh_des_tri_ecb_decrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = TRIPLE_DES_METHOD; + return fh_aes_crypt(req, method | ECB_MODE | DECRYPT); +} + +static int fh_des_tri_cbc_encrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = TRIPLE_DES_METHOD; + return fh_aes_crypt(req, method | CBC_MODE | ENCRYPT); +} + +static int fh_des_tri_cbc_decrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = TRIPLE_DES_METHOD; + return fh_aes_crypt(req, method | CBC_MODE | DECRYPT); +} + +static int fh_des_tri_ofb_encrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = TRIPLE_DES_METHOD; + return fh_aes_crypt(req, method | OFB_MODE | ENCRYPT); +} + +static int fh_des_tri_ofb_decrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = TRIPLE_DES_METHOD; + return fh_aes_crypt(req, method | OFB_MODE | DECRYPT); +} + +static int fh_des_tri_cfb_encrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = TRIPLE_DES_METHOD; + return fh_aes_crypt(req, method | CFB_MODE | ENCRYPT); +} + +static int fh_des_tri_cfb_decrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = TRIPLE_DES_METHOD; + return fh_aes_crypt(req, method | CFB_MODE | DECRYPT); +} +static int fh_aes_setkey(struct crypto_ablkcipher *cipher, const uint8_t *key, + unsigned int keylen) +{ + struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher); + struct fh_aes_ctx *ctx = crypto_tfm_ctx(tfm); + int i = 0; + AES_DBG("%s\n", __func__); + + if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 + && keylen != AES_KEYSIZE_256 && keylen != DES_KEY_SIZE + && keylen != DES3_EDE_KEY_SIZE) + return -EINVAL; + + for (; i < keylen; i++) + AES_DBG("%x", key[i]); + AES_DBG("\n"); + + memcpy(ctx->aes_key, key, keylen); + ctx->keylen = keylen; + return 0; +} + +static int fh_aes_cra_init(struct crypto_tfm *tfm) +{ + struct fh_aes_ctx *ctx = crypto_tfm_ctx(tfm); + ctx->dev = pobj_aes_dev; + tfm->crt_ablkcipher.reqsize = sizeof(struct fh_aes_reqctx); + AES_DBG("%s\n", __func__); + return 0; +} +static void fh_aes_tx(struct fh_aes_dev *dev) +{ + /*cpy dri local buf to core sg buf*/ + unsigned char *dst_xbuf; + u32 size = dev->ot_size; + u32 cpy_size = 0; + u32 i = 0; + /* unmap driver buf first.*/ + fh_unset_outdata(dev); + dst_xbuf = &dev->ctl_dst_xbuf[0]; + do { + /*get the sg list offset left + and the xfer size lower one.*/ + cpy_size = min_t(u32, + sg_dma_len(dev->sg_dst) - dev->dst_sg_offset, size); + sg_pcopy_from_buffer(dev->sg_dst, 1, + &dst_xbuf[i], cpy_size, dev->dst_sg_offset); + i += cpy_size; + dev->dst_sg_offset += cpy_size; + size -= cpy_size; + if (dev->dst_sg_offset == sg_dma_len(dev->sg_dst)) { + /*if sg offset get to the end of sg list. + then find the next..*/ + dev->dst_sg_offset = 0; + dev->sg_dst = sg_next(dev->sg_dst); + } + } while (size); + +} + +static void fh_aes_rx(struct fh_aes_dev *dev) +{ + fh_unset_indata(dev); +} + + +static irqreturn_t fh_aes_interrupt(int irq, void *dev_id) +{ + + u32 isr_status; + /*unsigned long flags;*/ + struct platform_device *pdev = (struct platform_device *) dev_id; + struct fh_aes_dev *dev = platform_get_drvdata(pdev); + /*u32 isr = dev->en_isr;*/ + AES_DBG("%s\n", __func__); + /*spin_lock_irqsave(&dev->lock, flags);*/ + aes_writel(dev, dma_control, 0); + isr_status = aes_readl(dev, intr_src); + aes_writel(dev, intr_clear_status, 0x07); + aes_writel(dev, intr_enable, 0); + if (isr_status & 0x02) + pr_err("dma rev hreap error...\n"); + if (isr_status & 0x04) + pr_err("dma stop src ..\n"); + if (isr_status & 0x01) { + AES_DBG("dma done..\n"); + complete(&(dev->done)); + } + /*spin_unlock_irqrestore(&dev->lock, flags);*/ + return IRQ_HANDLED; +} + +static void aes_biglittle_swap(u8 *buf) +{ + u8 tmp, tmp1; + tmp = buf[0]; + tmp1 = buf[1]; + buf[0] = buf[3]; + buf[1] = buf[2]; + buf[2] = tmp1; + buf[3] = tmp; +} + +static int fh_set_indata(struct fh_aes_dev *dev, struct scatterlist *sg) +{ + /*cpy usr buf data to dri local buf*/ + unsigned char *src_xbuf; + int err; + u32 cpy_size = 0; + u32 i = 0; + u32 size = dev->ot_size; + src_xbuf = &dev->ctl_src_xbuf[0]; + + do { + /*get the sg list offset left and the xfer size lower one.*/ + cpy_size = min_t(u32, + sg_dma_len(dev->sg_src) - dev->src_sg_offset, size); + sg_pcopy_to_buffer(dev->sg_src, 1, + &src_xbuf[i], cpy_size, dev->src_sg_offset); + i += cpy_size; + dev->src_sg_offset += cpy_size; + size -= cpy_size; + if (dev->src_sg_offset == sg_dma_len(dev->sg_src)) { + /*if sg offset get to the end of sg list. + then find the next..*/ + dev->src_sg_offset = 0; + dev->sg_src = sg_next(dev->sg_src); + } + } while (size); + /* cpy core date to driver buf, map the driver sg*/ + sg_init_one(&dev->src_sg_array[0], &src_xbuf[0], dev->ot_size); + err = dma_map_sg(dev->dev, &dev->src_sg_array[0], 1, DMA_TO_DEVICE); + if (!err) + BUG(); + return err; +} + +static int fh_set_outdata(struct fh_aes_dev *dev, struct scatterlist *sg) +{ + int err; + /*out data to driver buf, then cpy to core buf*/ + sg_init_one(&dev->dst_sg_array[0], + &dev->ctl_dst_xbuf[0], dev->ot_size); + err = dma_map_sg(dev->dev, &dev->dst_sg_array[0], 1, DMA_FROM_DEVICE); + if (!err) + BUG(); + return err; +} + +/*if use (encrypt & secure boot & use efuse 0~15 entry). return err*/ +int fh_aes_secure_check(struct fh_aes_dev *dev) +{ + if (dev->control_reg & DECRYPT) { + return 0; + } + return fh_efuse_secure_check(&s_efuse_obj, + s_efuse_obj.trans_key_start_no, + s_efuse_obj.trans_key_size, dev->p_usr_def); +} + +static void fh_set_aes_key_reg(struct fh_aes_dev *dev, uint8_t *key, + uint8_t *iv, unsigned int keylen) +{ + + int i; + u32 method; + u32 temp_key_buf[32]; + u32 temp_iv_buf[32]; + u32 *p_dst = NULL; + u32 key_size = 0; + + if (dev->iv_flag == true) { + /*set iv*/ + /*if aes mode ....set 128 bit iv, des set 64bit iv..*/ + AES_DBG("set iv reg\n"); + if ((dev->control_reg & AES_128_METHOD) + || ((dev->control_reg & AES_192_METHOD)) + || (dev->control_reg & AES_256_METHOD)) { + AES_DBG("aes iv mode...\n"); + + memcpy((u8 *)&temp_iv_buf[0], iv, 16); + p_dst = &temp_iv_buf[0]; + for (i = 0; i < 16 / sizeof(u32); i++) + aes_biglittle_swap((u8 *)(p_dst + i)); + memcpy((u8 *)&((struct fh_aes_reg *) dev->regs)->initial_vector0, + temp_iv_buf, 16); + } else { + AES_DBG("des iv mode...\n"); + + memcpy((u8 *)&temp_iv_buf[0], iv, 8); + p_dst = &temp_iv_buf[0]; + for (i = 0; i < 8 / sizeof(u32); i++) + aes_biglittle_swap((u8 *)(p_dst + i)); + + memcpy((u8 *)&((struct fh_aes_reg *) dev->regs)->initial_vector0, + temp_iv_buf, 8); + + } + } + /*set key...*/ + method = dev->control_reg & 0x0e; + AES_DBG("set key reg\n"); + + switch (method) { + case AES_128_METHOD: + AES_DBG("set key aes 128 mode..\n"); + key_size = 16; + + break; + case AES_192_METHOD: + AES_DBG("set key aes 192 mode..\n"); + key_size = 24; + break; + + case AES_256_METHOD: + AES_DBG("set key aes 256 mode..\n"); + key_size = 32; + break; + + case DES_METHOD: + AES_DBG("set key des normal mode..\n"); + key_size = 8; + break; + + case TRIPLE_DES_METHOD: + AES_DBG("set key des triple mode..\n"); + key_size = 24; + break; + + default: + AES_DBG("error method!!\n"); + break; + } +#ifdef FH_AESV2 + if (dev->p_usr_def->mode & CRYPTO_EX_MEM_SET_KEY) { + s_efuse_obj.trans_key_start_no = 0; + s_efuse_obj.trans_key_size = key_size / 4; + if (fh_aes_secure_check(dev)) { + pr_err("secure check failed..\n"); + return; + } + efuse_trans_key(&s_efuse_obj, + s_efuse_obj.trans_key_start_no, + s_efuse_obj.trans_key_size, dev->p_usr_def); + } else { + s_efuse_obj.old_usr_def.mode &= ~CRYPTO_EX_MEM_SET_KEY; + s_efuse_obj.old_usr_def.mode |= CRYPTO_CPU_SET_KEY; + memcpy((u8 *)&temp_key_buf[0], key, key_size); + p_dst = &temp_key_buf[0]; + for (i = 0; i < key_size / sizeof(u32); i++) + aes_biglittle_swap((u8 *)(p_dst + i)); + memcpy((u8 *)&((struct fh_aes_reg *) dev->regs)->security_key0, + (u8 *)&temp_key_buf[0], + key_size); + } + +#else + memcpy((u8 *)&temp_key_buf[0], key, key_size); + p_dst = &temp_key_buf[0]; + for (i = 0; i < key_size / sizeof(u32); i++) + aes_biglittle_swap((u8 *)(p_dst + i)); + + memcpy((u8 *)&((struct fh_aes_reg *) dev->regs)->security_key0, + (u8 *)&temp_key_buf[0], + key_size); +#endif +} + +static void fh_set_dma_indata(struct fh_aes_dev *dev, + struct scatterlist *sg) +{ + aes_writel(dev, dma_src_add, sg_dma_address(sg)); + AES_DBG("%s :dma trans size is :%x,add is:%x\n", + __func__, sg_dma_len(sg), sg_dma_address(sg)); + aes_writel(dev, dma_trans_size, sg_dma_len(sg)); +} + +static void fh_set_dma_outdata(struct fh_aes_dev *dev, + struct scatterlist *sg) +{ + aes_writel(dev, dma_dst_add, sg_dma_address(sg)); +} +static void fh_unset_indata(struct fh_aes_dev *dev) +{ + dma_unmap_sg(dev->dev, &dev->src_sg_array[0], 1, DMA_TO_DEVICE); +} + +static void fh_unset_outdata(struct fh_aes_dev *dev) +{ + dma_unmap_sg(dev->dev, &dev->dst_sg_array[0], 1, DMA_FROM_DEVICE); +} +static void fh_aes_complete(struct fh_aes_dev *dev, int err) +{ + if (dev->req->base.complete) + dev->req->base.complete(&dev->req->base, err); +} + + +static void fh_aes_crypt_start(struct fh_aes_dev *dev, +unsigned long mode) +{ + struct crypto_tfm *tfm; + struct crypto_ablkcipher *p_tfm; + struct ablkcipher_request *req; + + req = dev->req; + p_tfm = crypto_ablkcipher_reqtfm(dev->req); + tfm = crypto_ablkcipher_tfm(p_tfm); + fh_aes_crypt_with_sg(dev, mode, tfm); + + return; + +} + +static u32 fh_aes_update_request_data_size(u32 max_xfer_size, +u32 *total_size, u32 *first) +{ + u32 step_size = 0; + + step_size = min_t(u32, *total_size, max_xfer_size); + if (*first == 0) + *first = 1; + + *total_size -= step_size; + return step_size; +} + +static void fh_aes_crypt_with_sg(struct fh_aes_dev *dev, +unsigned long mode, struct crypto_tfm *tfm) +{ + struct ablkcipher_request *req = dev->req; + u32 total_size; + u32 block_size_limit; + u32 ot_len; + u32 isr; + u32 outfifo_thold = 0; + u32 infifo_thold = 0; + u32 first_in = 0; + u32 control_reg = 0; + + total_size = req->nbytes; + block_size_limit = get_tfm_block_size(tfm); + dev->sg_src = req->src; + dev->sg_dst = req->dst; + dev->src_sg_offset = 0; + dev->dst_sg_offset = 0; + + while (total_size) { + init_completion(&dev->done); + if (((mode & CBC_MODE) || (mode & CTR_MODE) || (mode & CFB_MODE) + || (mode & OFB_MODE)) && (first_in == 0)) { + control_reg |= 1 << 7; + dev->iv_flag = true; + } else { + control_reg &= ~(1 << 7); + dev->iv_flag = false; + } + + /*emode & method*/ + control_reg |= (unsigned int) mode; + dev->control_reg = control_reg; + outfifo_thold = 0; + infifo_thold = 8; + isr = dev->en_isr; + aes_writel(dev, encrypt_control, control_reg); + /*set key...*/ + if (first_in == 0) + fh_set_aes_key_reg(dev, dev->ctx->aes_key, + req->info, dev->ctx->keylen); + + ot_len = fh_aes_update_request_data_size( + FH_AES_CTL_MAX_PROCESS_SIZE, + &total_size, &first_in); + if (ot_len % block_size_limit) + BUG(); + dev->ot_size = ot_len; + fh_set_indata(dev, &dev->src_sg_array[0]); + fh_set_outdata(dev, &dev->dst_sg_array[0]); + fh_set_dma_indata(dev, &dev->src_sg_array[0]); + fh_set_dma_outdata(dev, &dev->dst_sg_array[0]); + aes_writel(dev, fifo_threshold, + outfifo_thold << 8 | infifo_thold); + /*set isr..*/ + aes_writel(dev, intr_enable, isr); + /*enable dma go..*/ + aes_writel(dev, dma_control, 1); + wait_for_completion(&dev->done); + /*update dst sg...*/ + fh_aes_rx(dev); + fh_aes_tx(dev); + } + +} +#ifdef CONFIG_CRYPTODEV +void cryptodev_fix_key_mode(struct fh_aes_ctx *p_ctx, +struct af_alg_usr_def *p_usr_def) +{ + uint8_t *pkey; + + pkey = p_ctx->aes_key; + if (pkey[0] == 'f' && pkey[1] == 'u' && pkey[2] == 'l' + && pkey[3] == 'l' && pkey[4] == 'h' + && pkey[5] == 'a' && pkey[6] == 'n') { + p_usr_def->mode &= + ~(CRYPTO_CPU_SET_KEY | CRYPTO_EX_MEM_SET_KEY); + p_usr_def->mode |= + CRYPTO_EX_MEM_SET_KEY; + } +} +#endif + +static void fh_aes_work_cb(struct work_struct *w) +{ + struct fh_aes_dev *dev = container_of(w, struct fh_aes_dev, work); + struct crypto_async_request *async_req, *backlog; + struct fh_aes_reqctx *reqctx; + struct crypto_ablkcipher *p_tfm; + struct af_alg_usr_def *p_usr_def; + unsigned long flags; + struct ablkcipher_request *p_ablk_req; + + AES_DBG("%s\n", __func__); + /*get the req need to handle*/ + spin_lock_irqsave(&dev->lock, flags); + async_req = crypto_dequeue_request(&dev->queue); + backlog = crypto_get_backlog(&dev->queue); + spin_unlock_irqrestore(&dev->lock, flags); + if (!async_req) + return; + + dev->req = ablkcipher_request_cast(async_req); + p_tfm = crypto_ablkcipher_reqtfm(dev->req); + p_ablk_req = dev->req; + p_usr_def = p_ablk_req->usr_def; + /*p_usr_def = crypto_ablkcipher_usr_def(p_tfm);*/ + dev->p_usr_def = p_usr_def; + dev->ctx = crypto_tfm_ctx(dev->req->base.tfm); + reqctx = ablkcipher_request_ctx(dev->req); +#ifdef CONFIG_CRYPTODEV + cryptodev_fix_key_mode(dev->ctx, p_usr_def); +#endif + + fh_aes_crypt_start(dev, reqctx->mode); + fh_aes_complete(dev, 0); + if (backlog) { + if (backlog->complete) + backlog->complete(backlog, -EINPROGRESS); + } + /*call the queue work until empty.*/ + if (dev->queue.qlen != 0) + queue_work(dev->workqueue, &dev->work); +} + + +int fh_aes_ctl_mem_init(struct fh_aes_dev *pdata) +{ + unsigned int t1; + unsigned int t2; + unsigned int t3; + unsigned int t4; + + t1 = (unsigned int)kmalloc(FH_AES_MALLOC_SIZE + + FH_AES_ALLIGN_SIZE, GFP_KERNEL); + if (!t1) + goto err1; + + t2 = (unsigned int)kmalloc(FH_AES_MALLOC_SIZE + + FH_AES_ALLIGN_SIZE, GFP_KERNEL); + if (!t2) + goto err2; + + + t3 = ((t1 + FH_AES_ALLIGN_SIZE - 1) & (~(FH_AES_ALLIGN_SIZE - 1))); + t4 = ((t2 + FH_AES_ALLIGN_SIZE - 1) & (~(FH_AES_ALLIGN_SIZE - 1))); + + pdata->ctl_raw_src_xbuf = (unsigned char *)t1; + pdata->ctl_raw_dst_xbuf = (unsigned char *)t2; + pdata->ctl_src_xbuf = (unsigned char *)t3; + pdata->ctl_dst_xbuf = (unsigned char *)t4; + return 0; +err2: + kfree((void *)t1); +err1: + return -1; + +} + +static int fh_aes_probe(struct platform_device *pdev) +{ + + int i, j, err = -ENODEV; + struct fh_aes_dev *pdata; + struct resource *res; + struct device_node *np = pdev->dev.of_node; + struct device *dev = &pdev->dev; + + pdata = kzalloc(sizeof(struct fh_aes_dev), GFP_KERNEL); + if (!pdata) { + err = -ENOMEM; + goto err_malloc; + } + spin_lock_init(&pdata->lock); + + if (np && !IS_ERR(np)) { + pdata->regs = of_iomap(np, 0); + if (!pdata->regs) { + err = -EINVAL; + goto err_iomap; + } + pdata->irq_no = irq_of_parse_and_map(np, 0); + if (!pdata->irq_no) { + err = pdata->irq_no; + goto err_irq; + } + } else { + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "can't fetch device resource info\n"); + goto err_iomap; + } + + pdata->regs = ioremap(res->start, resource_size(res)); + if (pdata->regs == NULL) { + dev_err(&pdev->dev, "ioremap resource error\n"); + goto err_iomap; + } + + pdata->irq_no = irq_create_mapping(NULL, platform_get_irq(pdev, 0)); + if (pdata->irq_no < 0) { + dev_err(&pdev->dev, "aes interrupt is not available.\n"); + goto err_irq; + } + } + + pdata->en_isr = 1 << 0; + err = request_irq(pdata->irq_no, fh_aes_interrupt, 0, + "fh-aes", pdev); + if (err) { + dev_dbg(&pdev->dev, "request_irq failed, %d\n", err); + goto err_irq; + } + /*bind to plat dev..*/ + pdata->dev = dev; + /*bing to static para..only one aes controller in fh..*/ + pobj_aes_dev = pdata; + platform_set_drvdata(pdev, pdata); + + pdata->workqueue = create_singlethread_workqueue(dev_name(&pdev->dev)); + if (!pdata->workqueue) { + dev_err(&pdev->dev, "aes workqueue init error.\n"); + goto err_irq; + } + INIT_WORK(&pdata->work, fh_aes_work_cb); + crypto_init_queue(&pdata->queue, CRYPTO_QUEUE_LEN); + for (i = 0; i < ARRAY_SIZE(algs); i++) { + INIT_LIST_HEAD(&algs[i].cra_list); + err = crypto_register_alg(&algs[i]); + + if (err) { + dev_warn(dev, "register alg error...\n"); + goto err_algs; + } + } + + err = fh_aes_ctl_mem_init(pdata); + if (err) { + dev_err(&pdev->dev, "aes malloc mem error..\n"); + goto err_algs; + } + pr_info("aes driver registered\n"); + + +#ifdef CONFIG_FH_AES_SELF_TEST + + fh_aes_self_test_all(); +#endif + + return 0; +err_algs: + for (j = 0; j < i; j++) + crypto_unregister_alg(&algs[j]); + destroy_workqueue(pdata->workqueue); + platform_set_drvdata(pdev, NULL); + pobj_aes_dev = NULL; + free_irq(pdata->irq_no, pdata); + +err_irq: +err_iomap: + kfree(pdata); +err_malloc: + + return err; + +} + + +static int fh_aes_remove(struct platform_device *pdev) +{ + + int i; + struct fh_aes_dev *pdata = platform_get_drvdata(pdev); + + for (i = 0; i < ARRAY_SIZE(algs); i++) + crypto_unregister_alg(&algs[i]); + + destroy_workqueue(pdata->workqueue); + platform_set_drvdata(pdev, NULL); + pobj_aes_dev = NULL; + free_irq(pdata->irq_no, pdata); + iounmap(pdata->regs); + kfree(pdata->ctl_raw_src_xbuf); + kfree(pdata->ctl_raw_dst_xbuf); + pdata->ctl_raw_src_xbuf = NULL; + pdata->ctl_raw_dst_xbuf = NULL; + pdata->ctl_src_xbuf = NULL; + pdata->ctl_dst_xbuf = NULL; + kfree(pdata); + + return 0; +} + + + +/*add chenjn dsp use...*/ +typedef struct { + unsigned int base; + void *vbase; + unsigned int size; +} MEM_INFO; + +typedef struct { + MEM_INFO mem; + unsigned char *remap_base; +} RW_MEM_INFO; + +struct tcrypt_result { + struct completion completion; + int err; +}; + +static void tcrypt_complete(struct crypto_async_request *req, int err) +{ + struct tcrypt_result *res = req->data; + + if (err == -EINPROGRESS) + return; + complete(&res->completion); +} + +int aes_128_ecb_encrypt(char *key_128, RW_MEM_INFO in, +RW_MEM_INFO out, unsigned int data_len_align16) +{ + static char *xbuf; + static char *dst_xbuf; + static struct crypto_ablkcipher *tfm; + static struct ablkcipher_request *req; + static struct af_alg_usr_def usr_def = {0}; + static int malloc_flag; + /*const char *algo = NULL;*/ + struct scatterlist sg[8]; + struct scatterlist dst_sg[8]; + void *data; + void *dst_data; + struct tcrypt_result wait_result; + + /*malloc buf...*/ + if (malloc_flag != 0) + goto work_go; + malloc_flag = 1; + + usr_def.mode = CRYPTO_CPU_SET_KEY; + + xbuf = (void *)__get_free_page(GFP_KERNEL); + if (!xbuf) { + pr_err("no pages.\n"); + return -1; + } + dst_xbuf = (void *)__get_free_page(GFP_KERNEL); + if (!dst_xbuf) { + free_page((unsigned long)xbuf); + pr_err("no pages.\n"); + return -1; + } + tfm = crypto_alloc_ablkcipher("ecb-aes-fh", + CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, 0); + if (IS_ERR(tfm)) { + pr_err("aes_test: failed to alloc cipher!\n"); + free_page((unsigned long)xbuf); + free_page((unsigned long)dst_xbuf); + return -1; + } + req = ablkcipher_request_alloc(tfm, GFP_KERNEL); + if (!req) { + pr_err("alg: skcipher: Failed to allocate\n"); + return -1; + } + +work_go: + ablkcipher_request_set_usrdef(req, &usr_def); + init_completion(&wait_result.completion); + crypto_ablkcipher_setkey(tfm, (u8 *)key_128, 16); + + ablkcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, + tcrypt_complete, &wait_result); + + data = xbuf; + dst_data = dst_xbuf; + /*encrypt*/ + memcpy(data, in.remap_base, data_len_align16); + sg_init_one(&sg[0], data, data_len_align16); + sg_init_one(&dst_sg[0], dst_data, data_len_align16); + ablkcipher_request_set_crypt(req, sg, dst_sg, data_len_align16, NULL); + crypto_ablkcipher_encrypt(req); + wait_for_completion(&wait_result.completion); + memcpy(out.remap_base, dst_data, data_len_align16); + + return 0; + +} +EXPORT_SYMBOL(aes_128_ecb_encrypt); + +static const struct of_device_id fh_aes_of_match[] = { + {.compatible = "fh,fh-aes",}, + {}, +}; + +MODULE_DEVICE_TABLE(of, fh_aes_of_match); + +static struct platform_driver fh_aes_driver = { + .driver = { + .name = "fh_aes", + .of_match_table = fh_aes_of_match, + }, + .probe = fh_aes_probe, + .remove = fh_aes_remove, +}; + +module_platform_driver(fh_aes_driver); +MODULE_AUTHOR("yu.zhang "); +MODULE_DESCRIPTION("fullhan AES device driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/crypto/fh_aes.h b/drivers/crypto/fh_aes.h new file mode 100644 index 00000000..369a6761 --- /dev/null +++ b/drivers/crypto/fh_aes.h @@ -0,0 +1,118 @@ +#ifndef FH_AES_H_ +#define FH_AES_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct fh_aes_reg { + u32 encrypt_control; /*0*/ + u32 reserved_4_8; /*4*/ + u32 fifo_status; /*8*/ + u32 parity_error; /*c*/ + u32 security_key0; /*10*/ + u32 security_key1; /*14*/ + u32 security_key2; /*18*/ + u32 security_key3; /*1c*/ + u32 security_key4; /*20*/ + u32 security_key5; /*24*/ + u32 security_key6; /*28*/ + u32 security_key7; /*2c*/ + u32 initial_vector0; /*30*/ + u32 initial_vector1; /*34*/ + u32 initial_vector2; /*38*/ + u32 initial_vector3; /*3c*/ + u32 reserved_40_44; /*40*/ + u32 reserved_44_48; /*44*/ + u32 dma_src_add; /*48*/ + u32 dma_dst_add; /*4c*/ + u32 dma_trans_size; /*50*/ + u32 dma_control; /*54*/ + u32 fifo_threshold; /*58*/ + u32 intr_enable; /*5c*/ + u32 intr_src; /*60*/ + u32 mask_intr_status; /*64*/ + u32 intr_clear_status; /*68*/ + u32 reserved_6c_70; /*6c*/ + u32 revision; /*70*/ + u32 feature; /*74*/ + u32 reserved_78_7c; /*78*/ + u32 reserved_7c_80; /*7c*/ + u32 last_initial_vector0; /*80*/ + u32 last_initial_vector1; /*84*/ + u32 last_initial_vector2; /*88*/ + u32 last_initial_vector3; /*8c*/ +}; + +/*requst ctx.....*/ +struct fh_aes_reqctx { + unsigned long mode; +}; +/*aes ctx....*/ +struct fh_aes_ctx { + struct fh_aes_dev *dev; /*bind to aes dev..*/ + uint8_t aes_key[AES_MAX_KEY_SIZE]; /*rec key value..*/ + int keylen; /*rec key len.*/ +}; + +struct fh_aes_dev { + /*common driver paras..*/ + void *regs; + struct device *dev; /*bind to the platform dev...*/ + struct clk *clk; + spinlock_t lock; /*just lock...*/ + u32 irq_no; /*board info...*/ + u32 en_isr; /*software rec the isr src*/ + bool iv_flag; + u32 control_reg; + /*crypto need below...*/ + struct fh_aes_ctx *ctx; /*bind to the aes ctx...*/ + struct fh_aes_reqctx *reqctx; /*bind to the req ctx..*/ + struct scatterlist *sg_src; /*rec the src data need to be handled*/ + struct scatterlist *sg_dst; /*rec the dst data need to be handled*/ + struct tasklet_struct tasklet; /*async process the crypto*/ + struct ablkcipher_request *req; /*active req...*/ + struct crypto_queue queue; + unsigned char *ctl_src_xbuf; + unsigned char *ctl_dst_xbuf; + unsigned char *ctl_raw_src_xbuf; + unsigned char *ctl_raw_dst_xbuf; + u32 src_sg_offset; + u32 dst_sg_offset; + struct scatterlist src_sg_array[1]; + struct scatterlist dst_sg_array[1]; + u32 ot_size; + struct completion done; + struct workqueue_struct *workqueue; + struct work_struct work; + struct af_alg_usr_def *p_usr_def; +}; + + +/*#define FH_AES_SELF_TEST*/ +/*#define FH_AES_DEBUG*/ +#ifdef FH_AES_DEBUG +#define AES_DBG(fmt, args...) printk(fmt, ## args) +#else +#define AES_DBG(fmt, args...) do { } while (0) +#endif + +#define AES_PRINT_RESULT(fmt, args...) printk(fmt, ## args) + +#endif /* fh_AES_H_ */ + + diff --git a/drivers/crypto/fh_aes_tee.c b/drivers/crypto/fh_aes_tee.c new file mode 100644 index 00000000..2670a42e --- /dev/null +++ b/drivers/crypto/fh_aes_tee.c @@ -0,0 +1,1503 @@ +#define pr_fmt(fmt) "%s %d: " fmt, __func__, __LINE__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "fh_aes.h" +#include +#include +#include + +/***************************************************************************** + * Define section + * add all #define here + *****************************************************************************/ + +#define CRYPTO_QUEUE_LEN (1000) +#define CRYPTION_POS (0) +#define METHOD_POS (1) +#define EMODE_POS (4) + + +#define FH_AES_ALLIGN_SIZE 64 +#define FH_AES_MALLOC_SIZE 2048 +#define FH_AES_CTL_MAX_PROCESS_SIZE (FH_AES_MALLOC_SIZE) + +/**************************************************************************** + * ADT section + * add definition of user defined Data Type that only be used in this file here + ***************************************************************************/ +enum { + ENCRYPT = 0 << CRYPTION_POS, + DECRYPT = 1 << CRYPTION_POS, +}; + +enum { + ECB_MODE = 0 << EMODE_POS, + CBC_MODE = 1 << EMODE_POS, + CTR_MODE = 2 << EMODE_POS, + CFB_MODE = 4 << EMODE_POS, + OFB_MODE = 5 << EMODE_POS, +}; + +enum { + DES_METHOD = 0 << METHOD_POS, + TRIPLE_DES_METHOD = 1 << METHOD_POS, + AES_128_METHOD = 4 << METHOD_POS, + AES_192_METHOD = 5 << METHOD_POS, + AES_256_METHOD = 6 << METHOD_POS, +}; + +/* optee TA UUID and cmds defines */ +static TEEC_UUID TA_FH_AES_UUID = \ + { 0xdd00d7bd, 0xe9e3, 0x4dcb,\ + { 0xad, 0xbc, 0xda, 0x54, 0xa7, 0x1b, 0x9b, 0x65} }; + +#define TA_INVOKE_AES_PREPARE 1 +#define TA_INVOKE_AES_SET_KEY 2 +#define TA_INVOKE_AES_SET_IV 3 +#define TA_INVOKE_AES_ENCRYPT 4 +#define TA_INVOKE_AES_DECRYPT 5 +#define TA_INVOKE_AES_START_TRANSFER 6 + +static TEEC_Context ctx; +static TEEC_Session sess; + +static int tee_fh_aes_set_key(void *key, struct ex_key_map_para *key_map, size_t size) +{ + uint32_t paramTypes = TEEC_PARAM_TYPES(TEEC_MEMREF_TEMP_INPUT, TEEC_NONE, + TEEC_NONE, TEEC_NONE); + TEEC_Parameter params[TEEC_CONFIG_PAYLOAD_REF_COUNT]; + + memset(params, 0, sizeof(params)); + params[0].tmpref.buffer = key; + params[0].tmpref.size = size; + + if (key_map) { + paramTypes = TEEC_PARAM_TYPES(TEEC_MEMREF_TEMP_INPUT, TEEC_MEMREF_TEMP_INPUT, + TEEC_NONE, TEEC_NONE); + params[1].tmpref.buffer = key_map; + params[1].tmpref.size = sizeof(*key_map); + } + + return tee_invoke_cmd(&sess, TA_INVOKE_AES_SET_KEY, paramTypes, params); +} + +static int tee_fh_aes_set_iv(void *iv, size_t size) +{ + uint32_t paramTypes = TEEC_PARAM_TYPES(TEEC_MEMREF_TEMP_INPUT, TEEC_NONE, + TEEC_NONE, TEEC_NONE); + TEEC_Parameter params[TEEC_CONFIG_PAYLOAD_REF_COUNT]; + + memset(params, 0, sizeof(params)); + + params[0].tmpref.buffer = iv; + params[0].tmpref.size = size; + + return tee_invoke_cmd(&sess, TA_INVOKE_AES_SET_IV, paramTypes, params); +} + +static int tee_fh_aes_prepare(int type, int mode, int flag) +{ + uint32_t paramTypes = TEEC_PARAM_TYPES(TEEC_VALUE_INPUT, TEEC_VALUE_INPUT, + TEEC_VALUE_INPUT, TEEC_NONE); + TEEC_Parameter params[TEEC_CONFIG_PAYLOAD_REF_COUNT]; + + memset(params, 0, sizeof(params)); + + params[0].value.a = type; + params[1].value.a = mode; + params[2].value.a = flag; + + pr_debug("%x %x %x\n", type, mode, flag); + + return tee_invoke_cmd(&sess, TA_INVOKE_AES_PREPARE, paramTypes, params); +} + +static int tee_fh_aes_start_transfer(void) +{ + uint32_t paramTypes = TEEC_PARAM_TYPES(TEEC_NONE, TEEC_NONE, + TEEC_NONE, TEEC_NONE); + TEEC_Parameter params[TEEC_CONFIG_PAYLOAD_REF_COUNT]; + + memset(params, 0, sizeof(params)); + + + pr_debug("aes start transfer\n"); + + return tee_invoke_cmd(&sess, TA_INVOKE_AES_START_TRANSFER, paramTypes, params); +} + +static int tee_fh_aes_crypto_action(void *src, void *dst, size_t size, int action) +{ + uint32_t paramTypes = TEEC_PARAM_TYPES(TEEC_MEMREF_TEMP_INPUT, TEEC_MEMREF_TEMP_OUTPUT, + TEEC_NONE, TEEC_NONE); + TEEC_Parameter params[TEEC_CONFIG_PAYLOAD_REF_COUNT]; + + memset(params, 0, sizeof(params)); + params[0].tmpref.buffer = src; + params[0].tmpref.size = size; + params[1].tmpref.buffer = dst; + params[1].tmpref.size = size; + + return tee_invoke_cmd(&sess, action, paramTypes, params); +} + +static int tee_fh_aes_encrypt(void *src, void *dst, size_t size) +{ + return tee_fh_aes_crypto_action(src, dst, size, TA_INVOKE_AES_ENCRYPT); +} + +static int tee_fh_aes_decrypt(void *src, void *dst, size_t size) +{ + return tee_fh_aes_crypto_action(src, dst, size, TA_INVOKE_AES_DECRYPT); +} + + +/***************************************************************************** + + * static fun; + *****************************************************************************/ + +static int fh_aes_handle_req(struct fh_aes_dev *dev, + struct ablkcipher_request *req); +/*aes*/ +static int fh_aes_crypt(struct ablkcipher_request *req, unsigned long mode); +static int fh_aes_ecb_encrypt(struct ablkcipher_request *req); +static int fh_aes_ecb_decrypt(struct ablkcipher_request *req); +static int fh_aes_cbc_encrypt(struct ablkcipher_request *req); +static int fh_aes_cbc_decrypt(struct ablkcipher_request *req); +static int fh_aes_ctr_encrypt(struct ablkcipher_request *req); +static int fh_aes_ctr_decrypt(struct ablkcipher_request *req); +static int fh_aes_ofb_encrypt(struct ablkcipher_request *req); +static int fh_aes_ofb_decrypt(struct ablkcipher_request *req); +static int fh_aes_cfb_encrypt(struct ablkcipher_request *req); +static int fh_aes_cfb_decrypt(struct ablkcipher_request *req); + +/*des*/ +static int fh_des_ecb_encrypt(struct ablkcipher_request *req); +static int fh_des_ecb_decrypt(struct ablkcipher_request *req); +static int fh_des_cbc_encrypt(struct ablkcipher_request *req); +static int fh_des_cbc_decrypt(struct ablkcipher_request *req); +static int fh_des_ofb_encrypt(struct ablkcipher_request *req); +static int fh_des_ofb_decrypt(struct ablkcipher_request *req); +static int fh_des_cfb_encrypt(struct ablkcipher_request *req); +static int fh_des_cfb_decrypt(struct ablkcipher_request *req); + +/*tri des*/ +static int fh_des_tri_ecb_encrypt(struct ablkcipher_request *req); +static int fh_des_tri_ecb_decrypt(struct ablkcipher_request *req); +static int fh_des_tri_cbc_encrypt(struct ablkcipher_request *req); +static int fh_des_tri_cbc_decrypt(struct ablkcipher_request *req); +static int fh_des_tri_ofb_encrypt(struct ablkcipher_request *req); +static int fh_des_tri_ofb_decrypt(struct ablkcipher_request *req); +static int fh_des_tri_cfb_encrypt(struct ablkcipher_request *req); +static int fh_des_tri_cfb_decrypt(struct ablkcipher_request *req); +static int fh_aes_setkey(struct crypto_ablkcipher *cipher, const uint8_t *key, + unsigned int keylen); +static int fh_aes_cra_init(struct crypto_tfm *tfm); +static void fh_aes_tx(struct fh_aes_dev *dev); +static void fh_aes_rx(struct fh_aes_dev *dev); +static int fh_set_indata(struct fh_aes_dev *dev, struct scatterlist *sg); +static int fh_set_outdata(struct fh_aes_dev *dev, struct scatterlist *sg); +static void fh_set_aes_key_reg(struct fh_aes_dev *dev, uint8_t *key, + uint8_t *iv, unsigned int keylen); +static void fh_unset_indata(struct fh_aes_dev *dev); +static void fh_unset_outdata(struct fh_aes_dev *dev); +static void fh_aes_complete(struct fh_aes_dev *dev, int err); +static void fh_aes_crypt_start(struct fh_aes_dev *dev, unsigned long mode); +static void fh_aes_work_cb(struct work_struct *w); +static void fh_aes_crypt_with_sg(struct fh_aes_dev *dev, +unsigned long mode, struct crypto_tfm *tfm); +#define fh_des_setkey fh_aes_setkey +/***************************************************************************** + * Global variables section - Local + * define global variables(will be refered only in this file) here, + * static keyword should be used to limit scope of local variable to this file + * e.g. + * static uint8_t ufoo; + *****************************************************************************/ +struct fh_aes_dev *pobj_aes_dev = NULL; +static struct crypto_alg algs[] = { + { + + .cra_name = "ecb(aes)", + .cra_driver_name = "ecb-aes-fh", + .cra_priority = 100, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct fh_aes_ctx), + .cra_alignmask = 0x0f, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = fh_aes_cra_init, + .cra_u.ablkcipher = { + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .setkey = fh_aes_setkey, + .encrypt = fh_aes_ecb_encrypt, + .decrypt = fh_aes_ecb_decrypt, + } + }, + { + .cra_name = "cbc(aes)", + .cra_driver_name = "cbc-aes-fh", + .cra_priority = 100, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, + + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct fh_aes_ctx), + .cra_alignmask = 0x0f, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = fh_aes_cra_init, + .cra_u.ablkcipher = { + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .ivsize = AES_BLOCK_SIZE, + .setkey = fh_aes_setkey, + .encrypt = fh_aes_cbc_encrypt, + .decrypt = fh_aes_cbc_decrypt, + } + }, + { + .cra_name = "ctr(aes)", + .cra_driver_name = "ctr-aes-fh", + .cra_priority = 100, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct fh_aes_ctx), + .cra_alignmask = 0x0f, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = fh_aes_cra_init, + .cra_u.ablkcipher = { + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .ivsize = AES_BLOCK_SIZE, + .setkey = fh_aes_setkey, + .encrypt = fh_aes_ctr_encrypt, + .decrypt = fh_aes_ctr_decrypt, + } + }, + { + .cra_name = "ofb(aes)", + .cra_driver_name = "ofb-aes-fh", + .cra_priority = 100, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct fh_aes_ctx), + .cra_alignmask = 0x0f, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = fh_aes_cra_init, + .cra_u.ablkcipher = { + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .ivsize = AES_BLOCK_SIZE, + .setkey = fh_aes_setkey, + .encrypt = fh_aes_ofb_encrypt, + .decrypt = fh_aes_ofb_decrypt, + } + }, + { + .cra_name = "cfb(aes)", + .cra_driver_name = "cfb-aes-fh", + .cra_priority = 100, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, + .cra_blocksize = AES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct fh_aes_ctx), + .cra_alignmask = 0x0f, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = fh_aes_cra_init, + .cra_u.ablkcipher = { + .min_keysize = AES_MIN_KEY_SIZE, + .max_keysize = AES_MAX_KEY_SIZE, + .ivsize = AES_BLOCK_SIZE, + .setkey = fh_aes_setkey, + .encrypt = fh_aes_cfb_encrypt, + .decrypt = fh_aes_cfb_decrypt, + } + }, + { + .cra_name = "ecb(des)", + .cra_driver_name = "ecb-des-fh", + .cra_priority = 100, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, + + .cra_blocksize = DES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct fh_aes_ctx), + .cra_alignmask = 0x0f, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = fh_aes_cra_init, + .cra_u.ablkcipher = { + .min_keysize = DES_KEY_SIZE, + .max_keysize = DES_KEY_SIZE, + .setkey = fh_des_setkey, + .encrypt = fh_des_ecb_encrypt, + .decrypt = fh_des_ecb_decrypt, + } + }, + { + .cra_name = "cbc(des)", + .cra_driver_name = "cbc-des-fh", + .cra_priority = 100, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, + .cra_blocksize = DES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct fh_aes_ctx), + .cra_alignmask = 0x0f, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = fh_aes_cra_init, + .cra_u.ablkcipher = { + .min_keysize = DES_KEY_SIZE, + .max_keysize = DES_KEY_SIZE, + .ivsize = DES_BLOCK_SIZE, + .setkey = fh_des_setkey, + .encrypt = fh_des_cbc_encrypt, + .decrypt = fh_des_cbc_decrypt, + } + }, + { + .cra_name = "ofb(des)", + .cra_driver_name = "ofb-des-fh", + .cra_priority = 100, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, + .cra_blocksize = DES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct fh_aes_ctx), + .cra_alignmask = 0x0f, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = fh_aes_cra_init, + .cra_u.ablkcipher = { + .min_keysize = DES_KEY_SIZE, + .max_keysize = DES_KEY_SIZE, + .ivsize = DES_BLOCK_SIZE, + .setkey = fh_des_setkey, + .encrypt = fh_des_ofb_encrypt, + .decrypt = fh_des_ofb_decrypt, + } + }, + { + .cra_name = "cfb(des)", + .cra_driver_name = "cfb-des-fh", + .cra_priority = 100, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, + .cra_blocksize = DES_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct fh_aes_ctx), + .cra_alignmask = 0x0f, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = fh_aes_cra_init, + .cra_u.ablkcipher = { + .min_keysize = DES_KEY_SIZE, + .max_keysize = DES_KEY_SIZE, + .ivsize = DES_BLOCK_SIZE, + .setkey = fh_des_setkey, + .encrypt = fh_des_cfb_encrypt, + .decrypt = fh_des_cfb_decrypt, + } + }, + { + .cra_name = "ecb(des3)", + .cra_driver_name = "ecb-des3-fh", + .cra_priority = 100, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, + + .cra_blocksize = DES3_EDE_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct fh_aes_ctx), + .cra_alignmask = 0x0f, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = fh_aes_cra_init, + .cra_u.ablkcipher = { + .min_keysize = DES3_EDE_KEY_SIZE, + .max_keysize = DES3_EDE_KEY_SIZE, + .setkey = fh_des_setkey, + .encrypt = fh_des_tri_ecb_encrypt, + .decrypt = fh_des_tri_ecb_decrypt, + } + }, + { + .cra_name = "cbc(des3)", + .cra_driver_name = "cbc-des3-fh", + .cra_priority = 100, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, + .cra_blocksize = DES3_EDE_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct fh_aes_ctx), + .cra_alignmask = 0x0f, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = fh_aes_cra_init, + .cra_u.ablkcipher = { + .min_keysize = DES3_EDE_KEY_SIZE, + .max_keysize = DES3_EDE_KEY_SIZE, + .ivsize = DES3_EDE_BLOCK_SIZE, + .setkey = fh_des_setkey, + .encrypt = fh_des_tri_cbc_encrypt, + .decrypt = fh_des_tri_cbc_decrypt, + } + }, + { + .cra_name = "ofb(des3)", + .cra_driver_name = "ofb-des3-fh", + .cra_priority = 100, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, + .cra_blocksize = DES3_EDE_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct fh_aes_ctx), + .cra_alignmask = 0x0f, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = fh_aes_cra_init, + .cra_u.ablkcipher = { + .min_keysize = DES3_EDE_KEY_SIZE, + .max_keysize = DES3_EDE_KEY_SIZE, + .ivsize = DES3_EDE_BLOCK_SIZE, + .setkey = fh_des_setkey, + .encrypt = fh_des_tri_ofb_encrypt, + .decrypt = fh_des_tri_ofb_decrypt, + } + }, + { + .cra_name = "cfb(des3)", + .cra_driver_name = "cfb-des3-fh", + .cra_priority = 100, + .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, + .cra_blocksize = DES3_EDE_BLOCK_SIZE, + .cra_ctxsize = sizeof(struct fh_aes_ctx), + .cra_alignmask = 0x0f, + .cra_type = &crypto_ablkcipher_type, + .cra_module = THIS_MODULE, + .cra_init = fh_aes_cra_init, + .cra_u.ablkcipher = { + .min_keysize = DES3_EDE_KEY_SIZE, + .max_keysize = DES3_EDE_KEY_SIZE, + .ivsize = DES3_EDE_BLOCK_SIZE, + .setkey = fh_des_setkey, + .encrypt = fh_des_tri_cfb_encrypt, + .decrypt = fh_des_tri_cfb_decrypt, + } + }, + +}; + + + + +#ifdef CONFIG_FH_AES_SELF_TEST +extern void fh_aes_self_test_all(void); +static int fh_aes_test_func(void *arg) +{ + pr_info("%s\n", __func__); + + msleep(10000); + + fh_aes_self_test_all(); + return 0; +} +#endif + +static unsigned int get_tfm_block_size(struct crypto_tfm *tfm) +{ + return tfm->__crt_alg->cra_blocksize; +} +/* function body */ +static int fh_aes_handle_req(struct fh_aes_dev *dev, + struct ablkcipher_request *req) +{ + unsigned long flags; + int err; + //*(int *)0 = 1; + //BUG(); + spin_lock_irqsave(&dev->lock, flags); + + err = ablkcipher_enqueue_request(&dev->queue, req); + + spin_unlock_irqrestore(&dev->lock, flags); + + queue_work(dev->workqueue, &dev->work); + + return err; +} + +static int fh_aes_crypt(struct ablkcipher_request *req, unsigned long mode) +{ + struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req); + struct fh_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm); + struct fh_aes_reqctx *reqctx = ablkcipher_request_ctx(req); + struct fh_aes_dev *dev = ctx->dev; + AES_DBG("%s\n", __func__); + dev->reqctx = reqctx; + /*if (!(mode & CFB_MODE)) {*/ + if ((!IS_ALIGNED(req->nbytes, AES_BLOCK_SIZE)) + && (!IS_ALIGNED(req->nbytes, DES_BLOCK_SIZE))) { + pr_err("request size is not exact amount of AES blocks\n"); + return -EINVAL; + } + /*}*/ + AES_DBG("reqctx->mode value: %x\n", (unsigned int)mode); + reqctx->mode = mode; + + return fh_aes_handle_req(dev, req); +} + +static int fh_aes_ecb_encrypt(struct ablkcipher_request *req) +{ + + struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req); + struct fh_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm); + u32 method = 0; + switch (ctx->keylen) { + case AES_KEYSIZE_128: + method = AES_128_METHOD; + break; + case AES_KEYSIZE_192: + method = AES_192_METHOD; + break; + case AES_KEYSIZE_256: + method = AES_256_METHOD; + break; + default: + break; + } + return fh_aes_crypt(req, method | ECB_MODE | ENCRYPT); +} + + +static int fh_aes_ecb_decrypt(struct ablkcipher_request *req) +{ + struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req); + struct fh_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm); + u32 method = 0; + + switch (ctx->keylen) { + case AES_KEYSIZE_128: + method = AES_128_METHOD; + break; + case AES_KEYSIZE_192: + method = AES_192_METHOD; + break; + case AES_KEYSIZE_256: + method = AES_256_METHOD; + break; + default: + break; + } + return fh_aes_crypt(req, method | ECB_MODE | DECRYPT); +} + +static int fh_aes_cbc_encrypt(struct ablkcipher_request *req) +{ + struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req); + struct fh_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm); + u32 method = 0; + + switch (ctx->keylen) { + case AES_KEYSIZE_128: + method = AES_128_METHOD; + break; + case AES_KEYSIZE_192: + method = AES_192_METHOD; + break; + case AES_KEYSIZE_256: + method = AES_256_METHOD; + break; + default: + break; + } + return fh_aes_crypt(req, method | CBC_MODE | ENCRYPT); +} + +static int fh_aes_cbc_decrypt(struct ablkcipher_request *req) +{ + struct crypto_ablkcipher *tfm; + struct fh_aes_ctx *ctx; + u32 method; + + tfm = crypto_ablkcipher_reqtfm(req); + ctx = crypto_ablkcipher_ctx(tfm); + method = 0; + AES_DBG("%s\n", __func__); + switch (ctx->keylen) { + case AES_KEYSIZE_128: + method = AES_128_METHOD; + break; + case AES_KEYSIZE_192: + method = AES_192_METHOD; + break; + case AES_KEYSIZE_256: + method = AES_256_METHOD; + break; + default: + break; + } + + return fh_aes_crypt(req, method | CBC_MODE | DECRYPT); +} + +static int fh_aes_ctr_encrypt(struct ablkcipher_request *req) +{ + struct crypto_ablkcipher *tfm; + struct fh_aes_ctx *ctx; + u32 method; + tfm = crypto_ablkcipher_reqtfm(req); + ctx = crypto_ablkcipher_ctx(tfm); + method = 0; + + switch (ctx->keylen) { + case AES_KEYSIZE_128: + method = AES_128_METHOD; + break; + case AES_KEYSIZE_192: + method = AES_192_METHOD; + break; + case AES_KEYSIZE_256: + method = AES_256_METHOD; + break; + default: + break; + } + + return fh_aes_crypt(req, method | CTR_MODE | ENCRYPT); +} + +static int fh_aes_ctr_decrypt(struct ablkcipher_request *req) +{ + struct crypto_ablkcipher *tfm; + struct fh_aes_ctx *ctx; + u32 method; + + tfm = crypto_ablkcipher_reqtfm(req); + ctx = crypto_ablkcipher_ctx(tfm); + method = 0; + AES_DBG("%s\n", __func__); + switch (ctx->keylen) { + case AES_KEYSIZE_128: + method = AES_128_METHOD; + break; + case AES_KEYSIZE_192: + method = AES_192_METHOD; + break; + case AES_KEYSIZE_256: + method = AES_256_METHOD; + break; + default: + break; + } + return fh_aes_crypt(req, method | CTR_MODE | DECRYPT); +} + +static int fh_aes_ofb_encrypt(struct ablkcipher_request *req) +{ + struct crypto_ablkcipher *tfm; + struct fh_aes_ctx *ctx; + u32 method; + + tfm = crypto_ablkcipher_reqtfm(req); + ctx = crypto_ablkcipher_ctx(tfm); + method = 0; + + switch (ctx->keylen) { + case AES_KEYSIZE_128: + method = AES_128_METHOD; + break; + case AES_KEYSIZE_192: + method = AES_192_METHOD; + break; + case AES_KEYSIZE_256: + method = AES_256_METHOD; + break; + default: + break; + } + return fh_aes_crypt(req, method | OFB_MODE | ENCRYPT); +} + +static int fh_aes_ofb_decrypt(struct ablkcipher_request *req) +{ + struct crypto_ablkcipher *tfm; + struct fh_aes_ctx *ctx; + u32 method; + + tfm = crypto_ablkcipher_reqtfm(req); + ctx = crypto_ablkcipher_ctx(tfm); + method = 0; + + AES_DBG("%s\n", __func__); + switch (ctx->keylen) { + case AES_KEYSIZE_128: + method = AES_128_METHOD; + break; + case AES_KEYSIZE_192: + method = AES_192_METHOD; + break; + case AES_KEYSIZE_256: + method = AES_256_METHOD; + break; + default: + break; + } + + return fh_aes_crypt(req, method | OFB_MODE | DECRYPT); +} + +static int fh_aes_cfb_encrypt(struct ablkcipher_request *req) +{ + struct crypto_ablkcipher *tfm; + struct fh_aes_ctx *ctx; + u32 method; + + tfm = crypto_ablkcipher_reqtfm(req); + ctx = crypto_ablkcipher_ctx(tfm); + method = 0; + + switch (ctx->keylen) { + case AES_KEYSIZE_128: + method = AES_128_METHOD; + break; + case AES_KEYSIZE_192: + method = AES_192_METHOD; + break; + case AES_KEYSIZE_256: + method = AES_256_METHOD; + break; + default: + break; + } + return fh_aes_crypt(req, method | CFB_MODE | ENCRYPT); +} + +static int fh_aes_cfb_decrypt(struct ablkcipher_request *req) +{ + struct crypto_ablkcipher *tfm; + struct fh_aes_ctx *ctx; + u32 method; + + tfm = crypto_ablkcipher_reqtfm(req); + ctx = crypto_ablkcipher_ctx(tfm); + method = 0; + + AES_DBG("%s\n", __func__); + switch (ctx->keylen) { + case AES_KEYSIZE_128: + method = AES_128_METHOD; + break; + case AES_KEYSIZE_192: + method = AES_192_METHOD; + break; + case AES_KEYSIZE_256: + method = AES_256_METHOD; + break; + default: + break; + } + + return fh_aes_crypt(req, method | CFB_MODE | DECRYPT); +} +static int fh_des_ecb_encrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = DES_METHOD; + + return fh_aes_crypt(req, method | ECB_MODE | ENCRYPT); +} + +static int fh_des_ecb_decrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = DES_METHOD; + + return fh_aes_crypt(req, method | ECB_MODE | DECRYPT); +} + +static int fh_des_cbc_encrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = DES_METHOD; + + return fh_aes_crypt(req, method | CBC_MODE | ENCRYPT); +} + +static int fh_des_cbc_decrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = DES_METHOD; + + return fh_aes_crypt(req, method | CBC_MODE | DECRYPT); +} + +static int fh_des_ofb_encrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = DES_METHOD; + + return fh_aes_crypt(req, method | OFB_MODE | ENCRYPT); +} + +static int fh_des_ofb_decrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = DES_METHOD; + + return fh_aes_crypt(req, method | OFB_MODE | DECRYPT); +} + +static int fh_des_cfb_encrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = DES_METHOD; + + return fh_aes_crypt(req, method | CFB_MODE | ENCRYPT); +} + +static int fh_des_cfb_decrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = DES_METHOD; + + return fh_aes_crypt(req, method | CFB_MODE | DECRYPT); +} +static int fh_des_tri_ecb_encrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = TRIPLE_DES_METHOD; + return fh_aes_crypt(req, method | ECB_MODE | ENCRYPT); +} + +static int fh_des_tri_ecb_decrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = TRIPLE_DES_METHOD; + return fh_aes_crypt(req, method | ECB_MODE | DECRYPT); +} + +static int fh_des_tri_cbc_encrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = TRIPLE_DES_METHOD; + return fh_aes_crypt(req, method | CBC_MODE | ENCRYPT); +} + +static int fh_des_tri_cbc_decrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = TRIPLE_DES_METHOD; + return fh_aes_crypt(req, method | CBC_MODE | DECRYPT); +} + +static int fh_des_tri_ofb_encrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = TRIPLE_DES_METHOD; + return fh_aes_crypt(req, method | OFB_MODE | ENCRYPT); +} + +static int fh_des_tri_ofb_decrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = TRIPLE_DES_METHOD; + return fh_aes_crypt(req, method | OFB_MODE | DECRYPT); +} + +static int fh_des_tri_cfb_encrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = TRIPLE_DES_METHOD; + return fh_aes_crypt(req, method | CFB_MODE | ENCRYPT); +} + +static int fh_des_tri_cfb_decrypt(struct ablkcipher_request *req) +{ + u32 method; + method = 0; + method = TRIPLE_DES_METHOD; + return fh_aes_crypt(req, method | CFB_MODE | DECRYPT); +} +static int fh_aes_setkey(struct crypto_ablkcipher *cipher, const uint8_t *key, + unsigned int keylen) +{ + struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher); + struct fh_aes_ctx *ctx = crypto_tfm_ctx(tfm); + + AES_DBG("%s\n", __func__); + if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 + && keylen != AES_KEYSIZE_256 && keylen != DES_KEY_SIZE + && keylen != DES3_EDE_KEY_SIZE) + return -EINVAL; + + memcpy(ctx->aes_key, key, keylen); + ctx->keylen = keylen; + return 0; +} + +static int fh_aes_cra_init(struct crypto_tfm *tfm) +{ + struct fh_aes_ctx *ctx = crypto_tfm_ctx(tfm); + ctx->dev = pobj_aes_dev; + tfm->crt_ablkcipher.reqsize = sizeof(struct fh_aes_reqctx); + AES_DBG("%s\n", __func__); + return 0; +} + +static void fh_aes_tx(struct fh_aes_dev *dev) +{ + /*cpy dri local buf to core sg buf*/ + unsigned char *dst_xbuf; + u32 size = dev->ot_size; + u32 cpy_size = 0; + u32 i = 0; + /* unmap driver buf first.*/ + fh_unset_outdata(dev); + dst_xbuf = &dev->ctl_dst_xbuf[0]; + do { + /*get the sg list offset left + and the xfer size lower one.*/ + cpy_size = min_t(u32, + sg_dma_len(dev->sg_dst) - dev->dst_sg_offset, size); + sg_pcopy_from_buffer(dev->sg_dst, 1, + &dst_xbuf[i], cpy_size, dev->dst_sg_offset); + i += cpy_size; + dev->dst_sg_offset += cpy_size; + size -= cpy_size; + if (dev->dst_sg_offset == sg_dma_len(dev->sg_dst)) { + /*if sg offset get to the end of sg list. + then find the next..*/ + dev->dst_sg_offset = 0; + dev->sg_dst = sg_next(dev->sg_dst); + } + } while (size); + +} + +static void fh_aes_rx(struct fh_aes_dev *dev) +{ + fh_unset_indata(dev); +} + +static int fh_set_indata(struct fh_aes_dev *dev, struct scatterlist *sg) +{ + /*cpy usr buf data to dri local buf*/ + unsigned char *src_xbuf; + int err; + u32 cpy_size = 0; + u32 i = 0; + u32 size = dev->ot_size; + + src_xbuf = &dev->ctl_src_xbuf[0]; + + do { + /*get the sg list offset left and the xfer size lower one.*/ + cpy_size = min_t(u32, + sg_dma_len(dev->sg_src) - dev->src_sg_offset, size); + sg_pcopy_to_buffer(dev->sg_src, 1, + &src_xbuf[i], cpy_size, dev->src_sg_offset); + i += cpy_size; + dev->src_sg_offset += cpy_size; + size -= cpy_size; + if (dev->src_sg_offset == sg_dma_len(dev->sg_src)) { + /*if sg offset get to the end of sg list. + then find the next..*/ + dev->src_sg_offset = 0; + dev->sg_src = sg_next(dev->sg_src); + } + } while (size); + /* cpy core date to driver buf, map the driver sg*/ + sg_init_one(&dev->src_sg_array[0], &src_xbuf[0], dev->ot_size); + err = dma_map_sg(dev->dev, &dev->src_sg_array[0], 1, DMA_TO_DEVICE); + if (!err) + BUG(); + return err; +} + +static int fh_set_outdata(struct fh_aes_dev *dev, struct scatterlist *sg) +{ + int err; + /*out data to driver buf, then cpy to core buf*/ + sg_init_one(&dev->dst_sg_array[0], + &dev->ctl_dst_xbuf[0], dev->ot_size); + err = dma_map_sg(dev->dev, &dev->dst_sg_array[0], 1, DMA_FROM_DEVICE); + if (!err) + BUG(); + return err; +} + + +static void fh_set_aes_key_reg(struct fh_aes_dev *dev, uint8_t *key, + uint8_t *iv, unsigned int keylen) +{ + u32 method; + u32 key_size = 0; + u32 iv_size = 0; + void *key_map = NULL; + + if (dev->iv_flag == true) { + /*set iv*/ + /*if aes mode ....set 128 bit iv, des set 64bit iv..*/ + AES_DBG("set iv reg\n"); + if ((dev->control_reg & AES_128_METHOD) + || ((dev->control_reg & AES_192_METHOD)) + || (dev->control_reg & AES_256_METHOD)) { + AES_DBG("aes iv mode...\n"); + iv_size = 16; + } else { + AES_DBG("des iv mode...\n"); + iv_size = 8; + } + tee_fh_aes_set_iv(iv, iv_size); + } + /*set key...*/ + method = dev->control_reg & 0x0e; + AES_DBG("set key reg\n"); + + switch (method) { + case AES_128_METHOD: + AES_DBG("set key aes 128 mode..\n"); + key_size = 16; + + break; + case AES_192_METHOD: + AES_DBG("set key aes 192 mode..\n"); + key_size = 24; + break; + + case AES_256_METHOD: + AES_DBG("set key aes 256 mode..\n"); + key_size = 32; + break; + + case DES_METHOD: + AES_DBG("set key des normal mode..\n"); + key_size = 8; + break; + + case TRIPLE_DES_METHOD: + AES_DBG("set key des triple mode..\n"); + key_size = 24; + break; + + default: + AES_DBG("error method!!\n"); + break; + } + + if (dev->p_usr_def->mode & CRYPTO_EX_MEM_SWITCH_KEY) + key_map = &dev->p_usr_def->adv.ex_key_para; + else + key_map = NULL; + /* printk("usr def data is %x\n",dev->p_usr_def->mode); */ + tee_fh_aes_set_key(key, key_map, key_size); +} + +static void fh_unset_indata(struct fh_aes_dev *dev) +{ + dma_unmap_sg(dev->dev, &dev->src_sg_array[0], 1, DMA_TO_DEVICE); +} + +static void fh_unset_outdata(struct fh_aes_dev *dev) +{ + dma_unmap_sg(dev->dev, &dev->dst_sg_array[0], 1, DMA_FROM_DEVICE); +} + +static void fh_aes_complete(struct fh_aes_dev *dev, int err) +{ + if (dev->req->base.complete) + dev->req->base.complete(&dev->req->base, err); +} + +enum { + CRYPT_TYPE_AES, + CRYPT_TYPE_DES, + CRYPT_TYPE_DES3, +}; + +static void fh_aes_crypt_start(struct fh_aes_dev *dev, +unsigned long mode) +{ + struct crypto_tfm *tfm; + struct crypto_ablkcipher *p_tfm; + struct ablkcipher_request *req; + + req = dev->req; + p_tfm = crypto_ablkcipher_reqtfm(dev->req); + tfm = crypto_ablkcipher_tfm(p_tfm); + fh_aes_crypt_with_sg(dev, mode, tfm); + + return; + +} + +static u32 fh_aes_update_request_data_size(u32 max_xfer_size, +u32 *total_size, u32 *first) +{ + u32 step_size = 0; + + step_size = min_t(u32, *total_size, max_xfer_size); + if (*first == 0) + *first = 1; + + *total_size -= step_size; + return step_size; +} + +static void fh_aes_crypt_with_sg(struct fh_aes_dev *dev, + unsigned long mode, struct crypto_tfm *tfm) +{ + struct ablkcipher_request *req = dev->req; + u32 control_reg = 0; + int err; + int crypto_type, crypto_mode; + + u32 total_size; + u32 block_size_limit; + u32 ot_len; + u32 first_in = 0; + + total_size = req->nbytes; + block_size_limit = get_tfm_block_size(tfm); + dev->sg_src = req->src; + dev->sg_dst = req->dst; + dev->src_sg_offset = 0; + dev->dst_sg_offset = 0; + + err = tee_open_session(&ctx, &sess, &TA_FH_AES_UUID); + if (err) { + pr_err("open_session failed: %d\n", err); + return; + } + + while (total_size) { + if (((mode & CBC_MODE) || (mode & CTR_MODE) || (mode & CFB_MODE) + || (mode & OFB_MODE)) && (first_in == 0)) { + control_reg |= 1 << 7; + dev->iv_flag = true; + } else { + control_reg &= ~(1 << 7); + dev->iv_flag = false; + } + + /*emode & method*/ + control_reg |= (unsigned int) mode; + dev->control_reg = control_reg; + + crypto_mode = (mode & 0x7 << EMODE_POS); + crypto_type = mode & 0x0e; + if (crypto_type == DES_METHOD) + crypto_type = CRYPT_TYPE_DES; + else if (crypto_type == TRIPLE_DES_METHOD) + crypto_type = CRYPT_TYPE_DES3; + else + crypto_type = CRYPT_TYPE_AES; + + if (first_in == 0) { + tee_fh_aes_prepare(crypto_type, crypto_mode, dev->p_usr_def->mode); + fh_set_aes_key_reg(dev, dev->ctx->aes_key, req->info, dev->ctx->keylen); + tee_fh_aes_start_transfer(); + } + + ot_len = fh_aes_update_request_data_size( + FH_AES_CTL_MAX_PROCESS_SIZE, &total_size, &first_in); + if (ot_len % block_size_limit) + BUG(); + dev->ot_size = ot_len; + + fh_set_indata(dev, &dev->src_sg_array[0]); + fh_set_outdata(dev, &dev->dst_sg_array[0]); + + if ((mode & 0x1) == 0) + err = tee_fh_aes_encrypt(dev->ctl_src_xbuf, dev->ctl_dst_xbuf, ot_len); + else + err = tee_fh_aes_decrypt(dev->ctl_src_xbuf, dev->ctl_dst_xbuf, ot_len); + if (err) + goto error; + + /*update dst sg...*/ + fh_aes_rx(dev); + fh_aes_tx(dev); + } + +error: + tee_close_session(&ctx, &sess); +} + +static void fh_aes_work_cb(struct work_struct *w) +{ + struct fh_aes_dev *dev = container_of(w, struct fh_aes_dev, work); + struct crypto_async_request *async_req, *backlog; + struct fh_aes_reqctx *reqctx; + struct crypto_ablkcipher *p_tfm; + struct af_alg_usr_def *p_usr_def; + unsigned long flags; + struct ablkcipher_request *p_ablk_req; + + AES_DBG("%s\n", __func__); + /*get the req need to handle*/ + spin_lock_irqsave(&dev->lock, flags); + async_req = crypto_dequeue_request(&dev->queue); + backlog = crypto_get_backlog(&dev->queue); + spin_unlock_irqrestore(&dev->lock, flags); + if (!async_req) + return; + + dev->req = ablkcipher_request_cast(async_req); + p_tfm = crypto_ablkcipher_reqtfm(dev->req); + p_ablk_req = dev->req; + p_usr_def = p_ablk_req->usr_def; + //p_usr_def = crypto_ablkcipher_usr_def(p_tfm); + dev->p_usr_def = p_usr_def; + dev->ctx = crypto_tfm_ctx(dev->req->base.tfm); + reqctx = ablkcipher_request_ctx(dev->req); + fh_aes_crypt_start(dev, reqctx->mode); + fh_aes_complete(dev, 0); + if (backlog) { + if (backlog->complete) + backlog->complete(backlog, -EINPROGRESS); + } + /*call the queue work until empty.*/ + if (dev->queue.qlen != 0) + queue_work(dev->workqueue, &dev->work); +} + + +int fh_aes_ctl_mem_init(struct fh_aes_dev *pdata) +{ + unsigned int t1; + unsigned int t2; + unsigned int t3; + unsigned int t4; + + t1 = (unsigned int)kmalloc(FH_AES_MALLOC_SIZE + + FH_AES_ALLIGN_SIZE, GFP_KERNEL); + if (!t1) + goto err1; + + t2 = (unsigned int)kmalloc(FH_AES_MALLOC_SIZE + + FH_AES_ALLIGN_SIZE, GFP_KERNEL); + if (!t2) + goto err2; + + + t3 = ((t1 + FH_AES_ALLIGN_SIZE - 1) & (~(FH_AES_ALLIGN_SIZE - 1))); + t4 = ((t2 + FH_AES_ALLIGN_SIZE - 1) & (~(FH_AES_ALLIGN_SIZE - 1))); + + pdata->ctl_raw_src_xbuf = (unsigned char *)t1; + pdata->ctl_raw_dst_xbuf = (unsigned char *)t2; + pdata->ctl_src_xbuf = (unsigned char *)t3; + pdata->ctl_dst_xbuf = (unsigned char *)t4; + return 0; +err2: + kfree((void *)t1); +err1: + return -1; + +} + +static int fh_aes_probe(struct platform_device *pdev) +{ + int i, j, err = -ENODEV; + struct fh_aes_dev *pdata; + struct device *dev = &pdev->dev; + u32 uuid_array[11]; + TEEC_UUID uuid; +#ifdef CONFIG_USE_OF + struct device_node *np = pdev->dev.of_node; + + err = of_property_read_u32_array(np, "optee-uuid", uuid_array, 11); + if (err) { + dev_err(&pdev->dev, "error when parse optee-uuid %s", np->full_name); + return err; + } else { +#else + void *plat_data = dev_get_platdata(&pdev->dev); + + if (!plat_data) { + dev_err(&pdev->dev, "cannot get optee-uuid from plat_data"); + } else { + memcpy(uuid_array, plat_data, sizeof(uuid_array)); +#endif + + uuid = get_uuid_from_array(uuid_array); + dev_info(&pdev->dev, + "aes-uuid: %08x-%04x-%04x-%02x%02x-%02x%02x%02x%02x%02x%02x", + uuid.timeLow, uuid.timeMid, uuid.timeHiAndVersion, + uuid.clockSeqAndNode[0], uuid.clockSeqAndNode[1], + uuid.clockSeqAndNode[2], uuid.clockSeqAndNode[3], + uuid.clockSeqAndNode[4], uuid.clockSeqAndNode[5], + uuid.clockSeqAndNode[6], uuid.clockSeqAndNode[7]); + } + + TA_FH_AES_UUID = uuid; + + pdata = kzalloc(sizeof(struct fh_aes_dev), GFP_KERNEL); + if (!pdata) { + err = -ENOMEM; + goto err_malloc; + } + spin_lock_init(&pdata->lock); + + pdata->regs = NULL; + + pdata->en_isr = 1 << 0; + + /*bind to plat dev..*/ + pdata->dev = dev; + /*bing to static para..only one aes controller in fh..*/ + pobj_aes_dev = pdata; + platform_set_drvdata(pdev, pdata); + + pdata->workqueue = create_singlethread_workqueue(dev_name(&pdev->dev)); + if (!pdata->workqueue) { + dev_err(&pdev->dev, "aes workqueue init error.\n"); + goto err_irq; + } + INIT_WORK(&pdata->work, fh_aes_work_cb); + crypto_init_queue(&pdata->queue, CRYPTO_QUEUE_LEN); + for (i = 0; i < ARRAY_SIZE(algs); i++) { + INIT_LIST_HEAD(&algs[i].cra_list); + err = crypto_register_alg(&algs[i]); + + if (err) { + dev_warn(dev, "register alg error...\n"); + goto err_algs; + } + } + + err = fh_aes_ctl_mem_init(pdata); + if (err) { + dev_err(&pdev->dev, "aes malloc mem error..\n"); + goto err_algs; + } + dev_info(&pdev->dev, "aes driver registered\n"); + + +#ifdef CONFIG_FH_AES_SELF_TEST +#include + kthread_run(fh_aes_test_func, NULL, "aes_self_test"); +#endif + + return 0; +err_algs: + for (j = 0; j < i; j++) + crypto_unregister_alg(&algs[j]); + destroy_workqueue(pdata->workqueue); + platform_set_drvdata(pdev, NULL); + pobj_aes_dev = NULL; + +err_irq: + kfree(pdata); +err_malloc: + pr_info("%s %d\n", __func__, __LINE__); + + return err; +} + + +static int fh_aes_remove(struct platform_device *pdev) +{ + int i; + struct fh_aes_dev *pdata = platform_get_drvdata(pdev); + + for (i = 0; i < ARRAY_SIZE(algs); i++) + crypto_unregister_alg(&algs[i]); + + destroy_workqueue(pdata->workqueue); + platform_set_drvdata(pdev, NULL); + pobj_aes_dev = NULL; + free_irq(pdata->irq_no, pdata); + iounmap(pdata->regs); + kfree(pdata->ctl_raw_src_xbuf); + kfree(pdata->ctl_raw_dst_xbuf); + pdata->ctl_raw_src_xbuf = NULL; + pdata->ctl_raw_dst_xbuf = NULL; + pdata->ctl_src_xbuf = NULL; + pdata->ctl_dst_xbuf = NULL; + kfree(pdata); + + return 0; +} + +static const struct of_device_id fh_aes_of_match[] = { + {.compatible = "fh,fh-aes",}, + {}, +}; + +MODULE_DEVICE_TABLE(of, fh_aes_of_match); + +static struct platform_driver fh_aes_driver = { + .driver = { + .name = "fh_aes", + .of_match_table = fh_aes_of_match, + }, + .probe = fh_aes_probe, + .remove = fh_aes_remove, +}; + +module_platform_driver(fh_aes_driver); +MODULE_AUTHOR("FULLHAN"); +MODULE_DESCRIPTION("fullhan AES device driver for tee"); +MODULE_LICENSE("GPL"); diff --git a/drivers/crypto/fh_aes_test.c b/drivers/crypto/fh_aes_test.c new file mode 100644 index 00000000..0988ec32 --- /dev/null +++ b/drivers/crypto/fh_aes_test.c @@ -0,0 +1,1448 @@ +/* + * fh_aes_test.c + * + * Created on: May 7, 2015 + * Author: yu.zhang + */ +#ifdef CONFIG_FH_AES_SELF_TEST +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "fh_aes.h" +//cbc aes 128 +#define AES_IV0 0x00010203 +#define AES_IV1 0x04050607 +#define AES_IV2 0x08090a0b +#define AES_IV3 0x0c0d0e0f + +#define AES_KEY0 0x2b7e1516 +#define AES_KEY1 0x28aed2a6 +#define AES_KEY2 0xabf71588 +#define AES_KEY3 0x09cf4f3c + + +static const unsigned char aes_cbc_iv_buf[] = { + 0x00,0x01,0x02,0x03, 0x04,0x05,0x06,0x07, 0x08,0x09,0x0a,0x0b, 0x0c,0x0d,0x0e,0x0f, +}; + +static const unsigned char aes_cbc_key_buf[] = { + 0x2b,0x7e,0x15,0x16, 0x28,0xae,0xd2,0xa6, 0xab,0xf7,0x15,0x88, 0x09,0xcf,0x4f,0x3c, +}; + + +//ecb aes 256 +#define AES_ECB_KEY0 0x603deb10 +#define AES_ECB_KEY1 0x15ca71be +#define AES_ECB_KEY2 0x2b73aef0 +#define AES_ECB_KEY3 0x857d7781 +#define AES_ECB_KEY4 0x1f352c07 +#define AES_ECB_KEY5 0x3b6108d7 +#define AES_ECB_KEY6 0x2d9810a3 +#define AES_ECB_KEY7 0x0914dff4 + + +static const unsigned char aes_ecb_key_buf[] = { + 0x60,0x3d,0xeb,0x10, 0x15,0xca,0x71,0xbe, 0x2b,0x73,0xae,0xf0, 0x85,0x7d,0x77,0x81, + 0x1f,0x35,0x2c,0x07, 0x3b,0x61,0x08,0xd7, 0x2d,0x98,0x10,0xa3, 0x09,0x14,0xdf,0xf4, +}; + +//ctr aes 192 +#define AES_CTR_KEY0 0x8e73b0f7 +#define AES_CTR_KEY1 0xda0e6452 +#define AES_CTR_KEY2 0xc810f32b +#define AES_CTR_KEY3 0x809079e5 +#define AES_CTR_KEY4 0x62f8ead2 +#define AES_CTR_KEY5 0x522c6b7b + +#define AES_CTR_IV0 0xf0f1f2f3 +#define AES_CTR_IV1 0xf4f5f6f7 +#define AES_CTR_IV2 0xf8f9fafb +#define AES_CTR_IV3 0xfcfdfeff + + +static const unsigned char aes_ctr_iv_buf[] = { + 0xf0,0xf1,0xf2,0xf3, 0xf4,0xf5,0xf6,0xf7, 0xf8,0xf9,0xfa,0xfb, 0xfc,0xfd,0xfe,0xff, +}; + +static const unsigned char aes_ctr_key_buf[] = { + 0x8e,0x73,0xb0,0xf7, 0xda,0x0e,0x64,0x52, 0xc8,0x10,0xf3,0x2b, 0x80,0x90,0x79,0xe5, + 0x62,0xf8,0xea,0xd2, 0x52,0x2c,0x6b,0x7b, +}; + + +//ofb aes 256 +#define AES_OFB_256_KEY0 0x603deb10 +#define AES_OFB_256_KEY1 0x15ca71be +#define AES_OFB_256_KEY2 0x2b73aef0 +#define AES_OFB_256_KEY3 0x857d7781 +#define AES_OFB_256_KEY4 0x1f352c07 +#define AES_OFB_256_KEY5 0x3b6108d7 +#define AES_OFB_256_KEY6 0x2d9810a3 +#define AES_OFB_256_KEY7 0x0914dff4 + +#define AES_OFB_IV0 0x00010203 +#define AES_OFB_IV1 0x04050607 +#define AES_OFB_IV2 0x08090a0b +#define AES_OFB_IV3 0x0c0d0e0f + +static const unsigned char aes_ofb_iv_buf[] = { + 0x00,0x01,0x02,0x03, 0x04,0x05,0x06,0x07, 0x08,0x09,0x0a,0x0b, 0x0c,0x0d,0x0e,0x0f, +}; + +static const unsigned char aes_ofb_key_buf[] = { + 0x60,0x3d,0xeb,0x10, 0x15,0xca,0x71,0xbe, 0x2b,0x73,0xae,0xf0, 0x85,0x7d,0x77,0x81, + 0x1f,0x35,0x2c,0x07, 0x3b,0x61,0x08,0xd7, 0x2d,0x98,0x10,0xa3, 0x09,0x14,0xdf,0xf4, +}; + +//des ecb +#define DES_ECB_KEY0 0x01010101 +#define DES_ECB_KEY1 0x01010101 + +static const unsigned char des_ecb_key_buf[] = { + 0x01,0x01,0x01,0x01, 0x01,0x01,0x01,0x01, +}; +//des cbc +#define DES_CBC_KEY0 0x01234567 +#define DES_CBC_KEY1 0x89abcdef + +#define DES_CBC_IV0 0x12345678 +#define DES_CBC_IV1 0x90abcdef + + +static const unsigned char des_cbc_key_buf[] = { + 0x01,0x23,0x45,0x67, 0x89,0xab,0xcd,0xef, +}; + +static const unsigned char des_cbc_iv_buf[] = { + 0x12,0x34,0x56,0x78, 0x90,0xab,0xcd,0xef, +}; + + +//ofb cbc +#define DES_OFB_KEY0 0x01234567 +#define DES_OFB_KEY1 0x89abcdef + +#define DES_OFB_IV0 0x12345678 +#define DES_OFB_IV1 0x90abcdef + +static const unsigned char des_ofb_key_buf[] = { + 0x01,0x23,0x45,0x67, 0x89,0xab,0xcd,0xef, +}; + +static const unsigned char des_ofb_iv_buf[] = { + 0x12,0x34,0x56,0x78, 0x90,0xab,0xcd,0xef, +}; + +//ecb tri-des +#define DES_TRI_ECB_KEY0 0x01234567 +#define DES_TRI_ECB_KEY1 0x89abcdef + +#define DES_TRI_ECB_KEY2 0x23456789 +#define DES_TRI_ECB_KEY3 0xabcdef01 + +#define DES_TRI_ECB_KEY4 0x456789ab +#define DES_TRI_ECB_KEY5 0xcdef0123 + +static const unsigned char des3_ecb_key_buf[] = { + 0x01,0x23,0x45,0x67, 0x89,0xab,0xcd,0xef, 0x23,0x45,0x67,0x89, 0xab,0xcd,0xef,0x01, + 0x45,0x67,0x89,0xab, 0xcd,0xef,0x01,0x23, +}; + +//cbc tri-des +#define DES_TRI_CBC_KEY0 0x01234567 +#define DES_TRI_CBC_KEY1 0x89abcdef + +#define DES_TRI_CBC_KEY2 0x23456789 +#define DES_TRI_CBC_KEY3 0xabcdef01 + +#define DES_TRI_CBC_KEY4 0x456789ab +#define DES_TRI_CBC_KEY5 0xcdef0123 + +#define DES_TRI_CBC_IV0 0x12345678 +#define DES_TRI_CBC_IV1 0x90abcdef + +static const unsigned char des3_cbc_key_buf[] = { + 0x01,0x23,0x45,0x67, 0x89,0xab,0xcd,0xef, 0x23,0x45,0x67,0x89, 0xab,0xcd,0xef,0x01, + 0x45,0x67,0x89,0xab, 0xcd,0xef,0x01,0x23, +}; +static const unsigned char des3_cbc_iv_buf[] = { + 0x12,0x34,0x56,0x78, 0x90,0xab,0xcd,0xef, +}; +#define XBUFSIZE 512 + +struct tcrypt_result { + struct completion completion; + int err; +}; + +static inline void hexdump(unsigned char *buf, unsigned int len); +static void tcrypt_complete(struct crypto_async_request *req, int err); +static int testmgr_alloc_buf(char *buf[XBUFSIZE]); + + +static struct tcrypt_result result; +static const unsigned char plain_text[] = { + 0x6b,0xc1,0xbe,0xe2, 0x2e,0x40,0x9f,0x96, 0xe9,0x3d,0x7e,0x11, 0x73,0x93,0x17,0x2a, + 0xae,0x2d,0x8a,0x57, 0x1e,0x03,0xac,0x9c, 0x9e,0xb7,0x6f,0xac, 0x45,0xaf,0x8e,0x51, + 0x30,0xc8,0x1c,0x46, 0xa3,0x5c,0xe4,0x11, 0xe5,0xfb,0xc1,0x19, 0x1a,0x0a,0x52,0xef, + 0xf6,0x9f,0x24,0x45, 0xdf,0x4f,0x9b,0x17, 0xad,0x2b,0x41,0x7b, 0xe6,0x6c,0x37,0x10, +}; + +static const unsigned char cipher_text[] = { + 0x76,0x49,0xab,0xac, 0x81,0x19,0xb2,0x46, 0xce,0xe9,0x8e,0x9b, 0x12,0xe9,0x19,0x7d, + 0x50,0x86,0xcb,0x9b, 0x50,0x72,0x19,0xee, 0x95,0xdb,0x11,0x3a, 0x91,0x76,0x78,0xb2, + 0x73,0xbe,0xd6,0xb8, 0xe3,0xc1,0x74,0x3b, 0x71,0x16,0xe6,0x9e, 0x22,0x22,0x95,0x16, + 0x3f,0xf1,0xca,0xa1, 0x68,0x1f,0xac,0x09, 0x12,0x0e,0xca,0x30, 0x75,0x86,0xe1,0xa7, +}; + +static const unsigned char plain_ecb_256_text[] = { + 0x6b,0xc1,0xbe,0xe2, 0x2e,0x40,0x9f,0x96, 0xe9,0x3d,0x7e,0x11, 0x73,0x93,0x17,0x2a, + 0xae,0x2d,0x8a,0x57, 0x1e,0x03,0xac,0x9c, 0x9e,0xb7,0x6f,0xac, 0x45,0xaf,0x8e,0x51, + 0x30,0xc8,0x1c,0x46, 0xa3,0x5c,0xe4,0x11, 0xe5,0xfb,0xc1,0x19, 0x1a,0x0a,0x52,0xef, + 0xf6,0x9f,0x24,0x45, 0xdf,0x4f,0x9b,0x17, 0xad,0x2b,0x41,0x7b, 0xe6,0x6c,0x37,0x10, +}; + +static const unsigned char cipher_ecb_256_text[] = { + 0xf3,0xee,0xd1,0xbd, 0xb5,0xd2,0xa0,0x3c, 0x06,0x4b,0x5a,0x7e, 0x3d,0xb1,0x81,0xf8, + 0x59,0x1c,0xcb,0x10, 0xd4,0x10,0xed,0x26, 0xdc,0x5b,0xa7,0x4a, 0x31,0x36,0x28,0x70, + 0xb6,0xed,0x21,0xb9, 0x9c,0xa6,0xf4,0xf9, 0xf1,0x53,0xe7,0xb1, 0xbe,0xaf,0xed,0x1d, + 0x23,0x30,0x4b,0x7a, 0x39,0xf9,0xf3,0xff, 0x06,0x7d,0x8d,0x8f, 0x9e,0x24,0xec,0xc7, +}; + +static const unsigned char plain_ctr_192_text[] = { + 0x6b,0xc1,0xbe,0xe2, 0x2e,0x40,0x9f,0x96, 0xe9,0x3d,0x7e,0x11, 0x73,0x93,0x17,0x2a, + 0xae,0x2d,0x8a,0x57, 0x1e,0x03,0xac,0x9c, 0x9e,0xb7,0x6f,0xac, 0x45,0xaf,0x8e,0x51, + 0x30,0xc8,0x1c,0x46, 0xa3,0x5c,0xe4,0x11, 0xe5,0xfb,0xc1,0x19, 0x1a,0x0a,0x52,0xef, + 0xf6,0x9f,0x24,0x45, 0xdf,0x4f,0x9b,0x17, 0xad,0x2b,0x41,0x7b, 0xe6,0x6c,0x37,0x10, +}; + +static const unsigned char cipher_ctr_192_text[] = { + 0x1a,0xbc,0x93,0x24, 0x17,0x52,0x1c,0xa2, 0x4f,0x2b,0x04,0x59, 0xfe,0x7e,0x6e,0x0b, + 0x09,0x03,0x39,0xec, 0x0a,0xa6,0xfa,0xef, 0xd5,0xcc,0xc2,0xc6, 0xf4,0xce,0x8e,0x94, + 0x1e,0x36,0xb2,0x6b, 0xd1,0xeb,0xc6,0x70, 0xd1,0xbd,0x1d,0x66, 0x56,0x20,0xab,0xf7, + 0x4f,0x78,0xa7,0xf6, 0xd2,0x98,0x09,0x58, 0x5a,0x97,0xda,0xec, 0x58,0xc6,0xb0,0x50, +}; + +static const unsigned char plain_ofb_256_text[] = { + 0x6b,0xc1,0xbe,0xe2, 0x2e,0x40,0x9f,0x96, 0xe9,0x3d,0x7e,0x11, 0x73,0x93,0x17,0x2a, + 0xae,0x2d,0x8a,0x57, 0x1e,0x03,0xac,0x9c, 0x9e,0xb7,0x6f,0xac, 0x45,0xaf,0x8e,0x51, + 0x30,0xc8,0x1c,0x46, 0xa3,0x5c,0xe4,0x11, 0xe5,0xfb,0xc1,0x19, 0x1a,0x0a,0x52,0xef, + 0xf6,0x9f,0x24,0x45, 0xdf,0x4f,0x9b,0x17, 0xad,0x2b,0x41,0x7b, 0xe6,0x6c,0x37,0x10, +}; + +static const unsigned char cipher_ofb_256_text[] = { + 0xdc,0x7e,0x84,0xbf,0xda,0x79,0x16,0x4b,0x7e,0xcd,0x84,0x86,0x98,0x5d,0x38,0x60, + 0x4f,0xeb,0xdc,0x67,0x40,0xd2,0x0b,0x3a,0xc8,0x8f,0x6a,0xd8,0x2a,0x4f,0xb0,0x8d, + 0x71,0xab,0x47,0xa0,0x86,0xe8,0x6e,0xed,0xf3,0x9d,0x1c,0x5b,0xba,0x97,0xc4,0x08, + 0x01,0x26,0x14,0x1d,0x67,0xf3,0x7b,0xe8,0x53,0x8f,0x5a,0x8b,0xe7,0x40,0xe4,0x84, +}; + +static const unsigned char plain_des_ecb_text[] = { + 0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, +}; + +static const unsigned char cipher_des_ecb_text[] = { + 0x95,0xF8,0xA5,0xE5,0xDD,0x31,0xD9,0x00,0xDD,0x7F,0x12,0x1C,0xA5,0x01,0x56,0x19, + 0x2E,0x86,0x53,0x10,0x4F,0x38,0x34,0xEA,0x4B,0xD3,0x88,0xFF,0x6C,0xD8,0x1D,0x4F, + 0x20,0xB9,0xE7,0x67,0xB2,0xFB,0x14,0x56,0x55,0x57,0x93,0x80,0xD7,0x71,0x38,0xEF, + 0x6C,0xC5,0xDE,0xFA,0xAF,0x04,0x51,0x2F,0x0D,0x9F,0x27,0x9B,0xA5,0xD8,0x72,0x60, +}; + +static const unsigned char plain_des_cbc_text[] = { + 0x4e,0x6f,0x77,0x20,0x69,0x73,0x20,0x74,0x68,0x65,0x20,0x74,0x69,0x6d,0x65,0x20, + 0x66,0x6f,0x72,0x20,0x61,0x6c,0x6c,0x20, +}; + +static const unsigned char cipher_des_cbc_text[] = { + 0xe5,0xc7,0xcd,0xde,0x87,0x2b,0xf2,0x7c,0x43,0xe9,0x34,0x00,0x8c,0x38,0x9c,0x0f, + 0x68,0x37,0x88,0x49,0x9a,0x7c,0x05,0xf6, +}; + +static const unsigned char plain_des_ofb_text[] = { + 0x4e,0x6f,0x77,0x20,0x69,0x73,0x20,0x74,0x43,0xe9,0x34,0x00,0x8c,0x38,0x9c,0x0f, + 0x68,0x37,0x88,0x49,0x9a,0x7c,0x05,0xf6, +}; + +static const unsigned char cipher_des_ofb_text[] = { + 0xf3,0x09,0x62,0x49,0xc7,0xf4,0x6e,0x51,0x1e,0x7e,0x5e,0x50,0xcb,0xbe,0xc4,0x10, + 0x33,0x35,0xa1,0x8a,0xde,0x4a,0x91,0x15, +}; + +static const unsigned char plain_des_tri_ecb_text[] = { + 0x4e,0x6f,0x77,0x20,0x69,0x73,0x20,0x74,0x43,0xe9,0x34,0x00,0x8c,0x38,0x9c,0x0f, + 0x68,0x37,0x88,0x49,0x9a,0x7c,0x05,0xf6, +}; + +static const unsigned char cipher_des_tri_ecb_text[] = { + 0x31,0x4f,0x83,0x27,0xfa,0x7a,0x09,0xa8,0xd5,0x89,0x5f,0xad,0xe9,0x8f,0xae,0xdf, + 0x98,0xf4,0x70,0xeb,0x35,0x53,0xa5,0xda, +}; + +static const unsigned char plain_des_tri_cbc_text[] = { + 0x4e,0x6f,0x77,0x20,0x69,0x73,0x20,0x74,0x43,0xe9,0x34,0x00,0x8c,0x38,0x9c,0x0f, + 0x68,0x37,0x88,0x49,0x9a,0x7c,0x05,0xf6, +}; + +static const unsigned char cipher_des_tri_cbc_text[] = { + 0xf3,0xc0,0xff,0x02,0x6c,0x02,0x30,0x89,0xc4,0x3a,0xdd,0x8f,0xd8,0xcd,0x5e,0x43, + 0x2b,0xfd,0x41,0xd3,0x13,0x0b,0xcf,0x40, +}; + +static inline void hexdump(unsigned char *buf, unsigned int len) +{ + while (len--) + AES_DBG("%02x", *buf++); + AES_DBG("\n"); +} + +static void tcrypt_complete(struct crypto_async_request *req, int err) +{ + struct tcrypt_result *res = req->data; + if (err == -EINPROGRESS) + return; + + AES_DBG("crypt all over....\n"); + complete(&res->completion); + +} + +static int testmgr_alloc_buf(char *buf[XBUFSIZE]) +{ + int i; + for (i = 0; i < XBUFSIZE; i++) { + buf[i] = (void *)__get_free_page(GFP_KERNEL); + if (!buf[i]) + goto err_free_buf; + } + + return 0; +err_free_buf: + while (i-- > 0) + free_page((unsigned long)buf[i]); + + return -ENOMEM; +} + +void fh_aes_set_crypto_key_source(struct af_alg_usr_def *p_def, u32 key_source){ + p_def->mode = key_source; +} + +static int fh_aes_cbc128_self_test(void * xbuf, void* dst_xbuf, + struct af_alg_usr_def *p_def) +{ + struct crypto_ablkcipher *tfm; + struct ablkcipher_request *req; + struct crypto_tfm * t_crytfm; + struct scatterlist sg[8]; + struct scatterlist dst_sg[8]; + const char *algo; + + void *data; + void *dst_data; + + u32 key[4] = { AES_KEY0, AES_KEY1, AES_KEY2, AES_KEY3 }; + u32 iv[4] = { AES_IV0, AES_IV1, AES_IV2, AES_IV3 }; + + memcpy(&key[0],&aes_cbc_key_buf[0],sizeof(aes_cbc_key_buf)); + memcpy(&iv[0],&aes_cbc_iv_buf[0],sizeof(aes_cbc_iv_buf)); + + AES_DBG("aes self test get in...\n"); + AES_DBG(" *_* step 1\n"); + t_crytfm = crypto_alloc_base("cbc-aes-fh", + CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, 0); + if (IS_ERR(t_crytfm)) { + AES_DBG("aes_test: failed to alloc t_crytfm!\n"); + return -1; + } + tfm = __crypto_ablkcipher_cast(t_crytfm); + if (IS_ERR(tfm)) { + AES_DBG("aes_test: failed to alloc cipher!\n"); + return -1; + } + algo = crypto_tfm_alg_driver_name(crypto_ablkcipher_tfm(tfm)); + pr_info("driver name %s\n",algo); + init_completion(&result.completion); + AES_DBG(" *_* step 3\n"); + crypto_ablkcipher_setkey(tfm, (u8 *) key, 16); + + AES_DBG(" *_* step 4\n"); + req = ablkcipher_request_alloc(tfm, GFP_KERNEL); + if (!req) { + AES_DBG(KERN_ERR "alg: skcipher: Failed to allocate request " + "for %s\n", algo); + return -1; + } + + AES_DBG(" *_* step 5\n"); + ablkcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, + tcrypt_complete, &result); + + AES_DBG(" *_* step 6\n"); + data = xbuf; + dst_data = dst_xbuf; + + //encrypt + memcpy(data, plain_text, 64); + memset(dst_data, 0, 64); + sg_init_one(&sg[0], data, 64); + sg_init_one(&dst_sg[0], dst_data, 64); + + AES_DBG(" *_* step 7\n"); + ablkcipher_request_set_crypt(req, sg, dst_sg, 64, (void *)iv); + fh_aes_set_crypto_key_source(p_def, CRYPTO_CPU_SET_KEY); + ablkcipher_request_set_usrdef(req, p_def); + AES_DBG(" *_* step 8\n"); + crypto_ablkcipher_encrypt(req); + + wait_for_completion(&result.completion); + + if (memcmp(dst_data, cipher_text, 64)) + AES_PRINT_RESULT(" encrypt error....\n"); + else + AES_PRINT_RESULT(" encrypt ok....\n"); + + //decrypt + memcpy(data, cipher_text, 64); + memset(dst_data, 0, 64); + sg_init_one(&sg[0], data, 64); + sg_init_one(&dst_sg[0], dst_data, 64); + AES_DBG(" *_* step 8\n"); + ablkcipher_request_set_crypt(req, sg, dst_sg, 64, (void *)iv); + AES_DBG(" *_* step 9\n"); + crypto_ablkcipher_decrypt(req); + wait_for_completion(&result.completion); + + if (memcmp(dst_data, plain_text, 64)) + AES_PRINT_RESULT(" decrypt error....\n"); + else + AES_PRINT_RESULT(" decrypt ok....\n"); + + return 0; + +} + +static int fh_aes_ecb256_self_test(void * xbuf, void* dst_xbuf, + struct af_alg_usr_def *p_def) +{ + struct crypto_ablkcipher *tfm; + struct ablkcipher_request *req; + const char *algo; + struct crypto_tfm * t_crytfm; + struct scatterlist sg[8]; + struct scatterlist dst_sg[8]; + u32 key[8] = { + AES_ECB_KEY0, AES_ECB_KEY1, AES_ECB_KEY2, AES_ECB_KEY3, + AES_ECB_KEY4, AES_ECB_KEY5, AES_ECB_KEY6, AES_ECB_KEY7 + }; + void *data; + void *dst_data; + memcpy(&key[0],&aes_ecb_key_buf[0],sizeof(aes_ecb_key_buf)); + AES_DBG("aes self test get in...\n"); + AES_DBG(" *_* step 1\n"); + t_crytfm = crypto_alloc_base("ecb-aes-fh", + CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, 0); + if (IS_ERR(t_crytfm)) { + AES_DBG("aes_test: failed to alloc t_crytfm!\n"); + return -1; + } + tfm = __crypto_ablkcipher_cast(t_crytfm); + if (IS_ERR(tfm)) { + AES_DBG("aes_test: failed to alloc cipher!\n"); + return -1; + } + + AES_DBG(" *_* step 2\n"); + algo = crypto_tfm_alg_driver_name(crypto_ablkcipher_tfm(tfm)); + init_completion(&result.completion); + + AES_DBG(" *_* step 3\n"); + crypto_ablkcipher_setkey(tfm, (u8 *) key, 32); + + AES_DBG(" *_* step 4\n"); + req = ablkcipher_request_alloc(tfm, GFP_KERNEL); + if (!req) { + AES_DBG(KERN_ERR "alg: skcipher: Failed to allocate request " + "for %s\n", algo); + return -1; + } + + AES_DBG(" *_* step 5\n"); + ablkcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, + tcrypt_complete, &result); + + AES_DBG(" *_* step 6\n"); + data = xbuf; + dst_data = dst_xbuf; + + //encrypt + memcpy(data, plain_ecb_256_text, 64); + memset(dst_data, 0, 64); + sg_init_one(&sg[0], data, 64); + sg_init_one(&dst_sg[0], dst_data, 64); + AES_DBG(" *_* step 7\n"); + ablkcipher_request_set_crypt(req, sg, dst_sg, 64, NULL); + fh_aes_set_crypto_key_source(p_def, CRYPTO_CPU_SET_KEY); + ablkcipher_request_set_usrdef(req, p_def); + AES_DBG(" *_* step 8\n"); + crypto_ablkcipher_encrypt(req); + + wait_for_completion(&result.completion); + + if (memcmp(dst_data, cipher_ecb_256_text, 64)) + AES_PRINT_RESULT(" encrypt error....\n"); + else + AES_PRINT_RESULT(" encrypt ok....\n"); + + //decrypt + memcpy(data, cipher_ecb_256_text, 64); + memset(dst_data, 0, 64); + sg_init_one(&sg[0], data, 64); + sg_init_one(&dst_sg[0], dst_data, 64); + + AES_DBG(" *_* step 8\n"); + ablkcipher_request_set_crypt(req, sg, dst_sg, 64, NULL); + + AES_DBG(" *_* step 9\n"); + crypto_ablkcipher_decrypt(req); + + wait_for_completion(&result.completion); + + if (memcmp(dst_data, plain_ecb_256_text, 64)) + AES_PRINT_RESULT(" decrypt error....\n"); + else + AES_PRINT_RESULT(" decrypt ok....\n"); + + return 0; + +} + +static int fh_aes_ofb256_self_test(void * xbuf, void* dst_xbuf, + struct af_alg_usr_def *p_def) +{ + struct crypto_ablkcipher *tfm; + struct ablkcipher_request *req; + const char *algo; + struct crypto_tfm * t_crytfm; + struct scatterlist sg[8]; + struct scatterlist dst_sg[8]; + u32 key[8] = { + AES_OFB_256_KEY0, AES_OFB_256_KEY1, AES_OFB_256_KEY2, + AES_OFB_256_KEY3, + AES_OFB_256_KEY4, AES_OFB_256_KEY5, AES_OFB_256_KEY6, + AES_OFB_256_KEY7 + }; + u32 iv[4] = + { AES_OFB_IV0, AES_OFB_IV1, AES_OFB_IV2, AES_OFB_IV3 }; + + void *data; + void *dst_data; + memcpy(&key[0],&aes_ofb_key_buf[0],sizeof(aes_ofb_key_buf)); + memcpy(&iv[0],&aes_ofb_iv_buf[0],sizeof(aes_ofb_iv_buf)); + + AES_DBG("aes self test get in...\n"); + AES_DBG(" *_* step 1\n"); + + t_crytfm = crypto_alloc_base("ofb-aes-fh", + CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, 0); + if (IS_ERR(t_crytfm)) { + AES_DBG("aes_test: failed to alloc t_crytfm!\n"); + return -1; + } + tfm = __crypto_ablkcipher_cast(t_crytfm); + if (IS_ERR(tfm)) { + AES_DBG("aes_test: failed to alloc cipher!\n"); + return -1; + } + + AES_DBG(" *_* step 2\n"); + algo = crypto_tfm_alg_driver_name(crypto_ablkcipher_tfm(tfm)); + init_completion(&result.completion); + + AES_DBG(" *_* step 3\n"); + crypto_ablkcipher_setkey(tfm, (u8 *) key, 32); + + AES_DBG(" *_* step 4\n"); + req = ablkcipher_request_alloc(tfm, GFP_KERNEL); + if (!req) { + AES_DBG(KERN_ERR "alg: skcipher: Failed to allocate request " + "for %s\n", algo); + return -1; + } + + AES_DBG(" *_* step 5\n"); + ablkcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, + tcrypt_complete, &result); + + AES_DBG(" *_* step 6\n"); + data = xbuf; + dst_data = dst_xbuf; + //encrypt + memcpy(data, plain_ofb_256_text, 64); + memset(dst_data, 0, 64); + sg_init_one(&sg[0], data, 64); + sg_init_one(&dst_sg[0], dst_data, 64); + + AES_DBG(" *_* step 7\n"); + ablkcipher_request_set_crypt(req, sg, dst_sg, 64, (void *)iv); + fh_aes_set_crypto_key_source(p_def, CRYPTO_CPU_SET_KEY); + ablkcipher_request_set_usrdef(req, p_def); + AES_DBG(" *_* step 8\n"); + crypto_ablkcipher_encrypt(req); + wait_for_completion(&result.completion); + if (memcmp(dst_data, cipher_ofb_256_text, 64)) + AES_PRINT_RESULT(" encrypt error....\n"); + else + AES_PRINT_RESULT(" encrypt ok....\n"); + //decrypt + memcpy(data, cipher_ofb_256_text, 64); + memset(dst_data, 0, 64); + sg_init_one(&sg[0], data, 64); + sg_init_one(&dst_sg[0], dst_data, 64); + AES_DBG(" *_* step 8\n"); + ablkcipher_request_set_crypt(req, sg, dst_sg, 64, (void *)iv); + AES_DBG(" *_* step 9\n"); + crypto_ablkcipher_decrypt(req); + + wait_for_completion(&result.completion); + + if (memcmp(dst_data, plain_ofb_256_text, 64)) + AES_PRINT_RESULT(" decrypt error....\n"); + else + AES_PRINT_RESULT(" decrypt ok....\n"); + + return 0; +} + +static int fh_des_ecb_self_test(void * xbuf, void* dst_xbuf, + struct af_alg_usr_def *p_def) +{ + struct crypto_ablkcipher *tfm; + struct ablkcipher_request *req; + const char *algo; + struct crypto_tfm * t_crytfm; + struct scatterlist sg[8]; + struct scatterlist dst_sg[8]; + u32 key[2] = { DES_ECB_KEY0, DES_ECB_KEY1 }; + + void *data; + void *dst_data; + + memcpy(&key[0],&des_ecb_key_buf[0],sizeof(des_ecb_key_buf)); + AES_DBG("aes self test get in...\n"); + AES_DBG(" *_* step 1\n"); + + t_crytfm = crypto_alloc_base("ecb-des-fh", + CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, 0); + if (IS_ERR(t_crytfm)) { + AES_DBG("aes_test: failed to alloc t_crytfm!\n"); + return -1; + } + tfm = __crypto_ablkcipher_cast(t_crytfm); + if (IS_ERR(tfm)) { + AES_DBG("aes_test: failed to alloc cipher!\n"); + return -1; + } + + + AES_DBG(" *_* step 2\n"); + algo = crypto_tfm_alg_driver_name(crypto_ablkcipher_tfm(tfm)); + init_completion(&result.completion); + + AES_DBG(" *_* step 3\n"); + crypto_ablkcipher_setkey(tfm, (u8 *) key, 8); + + AES_DBG(" *_* step 4\n"); + req = ablkcipher_request_alloc(tfm, GFP_KERNEL); + if (!req) { + AES_DBG(KERN_ERR "alg: skcipher: Failed to allocate request " + "for %s\n", algo); + return -1; + } + + AES_DBG(" *_* step 5\n"); + ablkcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, + tcrypt_complete, &result); + + AES_DBG(" *_* step 6\n"); + data = xbuf; + dst_data = dst_xbuf; + + //encrypt + memcpy(data, plain_des_ecb_text, 64); + memset(dst_data, 0, 64); + sg_init_one(&sg[0], data, 64); + sg_init_one(&dst_sg[0], dst_data, 64); + + AES_DBG(" *_* step 7\n"); + ablkcipher_request_set_crypt(req, sg, dst_sg, 64, NULL); + fh_aes_set_crypto_key_source(p_def, CRYPTO_CPU_SET_KEY); + ablkcipher_request_set_usrdef(req, p_def); + AES_DBG(" *_* step 8\n"); + crypto_ablkcipher_encrypt(req); + + wait_for_completion(&result.completion); + + if (memcmp(dst_data, cipher_des_ecb_text, 64)) + AES_PRINT_RESULT(" encrypt error....\n"); + else + AES_PRINT_RESULT(" encrypt ok....\n"); + + //decrypt + memcpy(data, cipher_des_ecb_text, 64); + memset(dst_data, 0, 64); + sg_init_one(&sg[0], data, 64); + sg_init_one(&dst_sg[0], dst_data, 64); + + AES_DBG(" *_* step 8\n"); + ablkcipher_request_set_crypt(req, sg, dst_sg, 64, NULL); + + AES_DBG(" *_* step 9\n"); + crypto_ablkcipher_decrypt(req); + + wait_for_completion(&result.completion); + + if (memcmp(dst_data, plain_des_ecb_text, 64)) + AES_PRINT_RESULT(" decrypt error....\n"); + else + AES_PRINT_RESULT(" decrypt ok....\n"); + + return 0; + +} + +static int fh_des_cbc_self_test(void * xbuf, void* dst_xbuf, + struct af_alg_usr_def *p_def) +{ + struct crypto_ablkcipher *tfm; + struct ablkcipher_request *req; + const char *algo; + struct scatterlist sg[8]; + struct scatterlist dst_sg[8]; + struct crypto_tfm * t_crytfm; + u32 key[2] = { DES_CBC_KEY0, DES_CBC_KEY1 }; + u32 iv[2] = { DES_CBC_IV0, DES_CBC_IV1 }; + void *data; + void *dst_data; + + + memcpy(&key[0],&des_cbc_key_buf[0],sizeof(des_cbc_key_buf)); + memcpy(&iv[0],&des_cbc_iv_buf[0],sizeof(des_cbc_iv_buf)); + + AES_DBG("aes self test get in...\n"); + AES_DBG(" *_* step 1\n"); + + t_crytfm = crypto_alloc_base("cbc-des-fh", + CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, 0); + if (IS_ERR(t_crytfm)) { + AES_DBG("aes_test: failed to alloc t_crytfm!\n"); + return -1; + } + tfm = __crypto_ablkcipher_cast(t_crytfm); + if (IS_ERR(tfm)) { + AES_DBG("aes_test: failed to alloc cipher!\n"); + return -1; + } + + + AES_DBG(" *_* step 2\n"); + algo = crypto_tfm_alg_driver_name(crypto_ablkcipher_tfm(tfm)); + init_completion(&result.completion); + + AES_DBG(" *_* step 3\n"); + crypto_ablkcipher_setkey(tfm, (u8 *) key, 8); + + AES_DBG(" *_* step 4\n"); + req = ablkcipher_request_alloc(tfm, GFP_KERNEL); + if (!req) { + AES_DBG(KERN_ERR "alg: skcipher: Failed to allocate request " + "for %s\n", algo); + return -1; + } + + AES_DBG(" *_* step 5\n"); + ablkcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, + tcrypt_complete, &result); + + AES_DBG(" *_* step 6\n"); + data = xbuf; + dst_data = dst_xbuf; + + //encrypt + memcpy(data, plain_des_cbc_text, 24); + memset(dst_data, 0, 24); + sg_init_one(&sg[0], data, 24); + sg_init_one(&dst_sg[0], dst_data, 24); + + AES_DBG(" *_* step 7\n"); + ablkcipher_request_set_crypt(req, sg, dst_sg, 24, (void *)iv); + fh_aes_set_crypto_key_source(p_def, CRYPTO_CPU_SET_KEY); + ablkcipher_request_set_usrdef(req, p_def); + AES_DBG(" *_* step 8\n"); + crypto_ablkcipher_encrypt(req); + + wait_for_completion(&result.completion); + + if (memcmp(dst_data, cipher_des_cbc_text, 24)) + AES_PRINT_RESULT(" encrypt error....\n"); + else + AES_PRINT_RESULT(" encrypt ok....\n"); + + //decrypt + memcpy(data, cipher_des_cbc_text, 24); + memset(dst_data, 0, 24); + sg_init_one(&sg[0], data, 24); + sg_init_one(&dst_sg[0], dst_data, 24); + + AES_DBG(" *_* step 8\n"); + ablkcipher_request_set_crypt(req, sg, dst_sg, 24, (void *)iv); + + AES_DBG(" *_* step 9\n"); + crypto_ablkcipher_decrypt(req); + + wait_for_completion(&result.completion); + + if (memcmp(dst_data, plain_des_cbc_text, 24)) + AES_PRINT_RESULT(" decrypt error....\n"); + else + AES_PRINT_RESULT(" decrypt ok....\n"); + + return 0; +} + +static int fh_des_ofb_self_test(void * xbuf, void* dst_xbuf, + struct af_alg_usr_def *p_def) +{ + struct crypto_ablkcipher *tfm; + struct ablkcipher_request *req; + const char *algo; + struct crypto_tfm * t_crytfm; + struct scatterlist sg[8]; + struct scatterlist dst_sg[8]; + u32 key[2] = { DES_OFB_KEY0, DES_OFB_KEY1 }; + u32 iv[2] = { DES_OFB_IV0, DES_OFB_IV1 }; + void *data; + void *dst_data; + + memcpy(&key[0],&des_ofb_key_buf[0],sizeof(des_ofb_key_buf)); + memcpy(&iv[0],&des_ofb_iv_buf[0],sizeof(des_ofb_iv_buf)); + + AES_DBG("aes self test get in...\n"); + AES_DBG(" *_* step 1\n"); + + t_crytfm = crypto_alloc_base("ofb-des-fh", + CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, 0); + if (IS_ERR(t_crytfm)) { + AES_DBG("aes_test: failed to alloc t_crytfm!\n"); + return -1; + } + tfm = __crypto_ablkcipher_cast(t_crytfm); + if (IS_ERR(tfm)) { + AES_DBG("aes_test: failed to alloc cipher!\n"); + return -1; + } + + AES_DBG(" *_* step 2\n"); + algo = crypto_tfm_alg_driver_name(crypto_ablkcipher_tfm(tfm)); + init_completion(&result.completion); + + AES_DBG(" *_* step 3\n"); + crypto_ablkcipher_setkey(tfm, (u8 *) key, 8); + + AES_DBG(" *_* step 4\n"); + req = ablkcipher_request_alloc(tfm, GFP_KERNEL); + if (!req) { + AES_DBG(KERN_ERR "alg: skcipher: Failed to allocate request " + "for %s\n", algo); + return -1; + } + + AES_DBG(" *_* step 5\n"); + ablkcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, + tcrypt_complete, &result); + + AES_DBG(" *_* step 6\n"); + data = xbuf; + dst_data = dst_xbuf; + + //encrypt + memcpy(data, plain_des_ofb_text, 24); + memset(dst_data, 0, 24); + sg_init_one(&sg[0], data, 24); + sg_init_one(&dst_sg[0], dst_data, 24); + + AES_DBG(" *_* step 7\n"); + ablkcipher_request_set_crypt(req, sg, dst_sg, 24, (void *)iv); + fh_aes_set_crypto_key_source(p_def, CRYPTO_CPU_SET_KEY); + ablkcipher_request_set_usrdef(req, p_def); + AES_DBG(" *_* step 8\n"); + crypto_ablkcipher_encrypt(req); + wait_for_completion(&result.completion); + if (memcmp(dst_data, cipher_des_ofb_text, 24)) + AES_PRINT_RESULT(" encrypt error....\n"); + else + AES_PRINT_RESULT(" encrypt ok....\n"); + + //decrypt + memcpy(data, cipher_des_ofb_text, 24); + memset(dst_data, 0, 24); + sg_init_one(&sg[0], data, 24); + sg_init_one(&dst_sg[0], dst_data, 24); + AES_DBG(" *_* step 8\n"); + ablkcipher_request_set_crypt(req, sg, dst_sg, 24, (void *)iv); + + AES_DBG(" *_* step 9\n"); + crypto_ablkcipher_decrypt(req); + wait_for_completion(&result.completion); + if (memcmp(dst_data, plain_des_ofb_text, 24)) + AES_PRINT_RESULT(" decrypt error....\n"); + else + AES_PRINT_RESULT(" decrypt ok....\n"); + + return 0; + +} + +static int fh_des_tri_ecb_self_test(void * xbuf, void* dst_xbuf, + struct af_alg_usr_def *p_def) +{ + struct crypto_ablkcipher *tfm; + struct ablkcipher_request *req; + const char *algo; + struct crypto_tfm * t_crytfm; + struct scatterlist sg[8]; + struct scatterlist dst_sg[8]; + u32 key[6] = { + DES_TRI_ECB_KEY0, DES_TRI_ECB_KEY1, DES_TRI_ECB_KEY2, + DES_TRI_ECB_KEY3, DES_TRI_ECB_KEY4, DES_TRI_ECB_KEY5 + }; + + void *data; + void *dst_data; + + memcpy(&key[0],&des3_ecb_key_buf[0],sizeof(des3_ecb_key_buf)); + + AES_DBG("aes self test get in...\n"); + AES_DBG(" *_* step 1\n"); + + t_crytfm = crypto_alloc_base("ecb-des3-fh", + CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, 0); + if (IS_ERR(t_crytfm)) { + AES_DBG("aes_test: failed to alloc t_crytfm!\n"); + return -1; + } + tfm = __crypto_ablkcipher_cast(t_crytfm); + if (IS_ERR(tfm)) { + AES_DBG("aes_test: failed to alloc cipher!\n"); + return -1; + } + + AES_DBG(" *_* step 2\n"); + algo = crypto_tfm_alg_driver_name(crypto_ablkcipher_tfm(tfm)); + init_completion(&result.completion); + + AES_DBG(" *_* step 3\n"); + crypto_ablkcipher_setkey(tfm, (u8 *) key, 24); + + AES_DBG(" *_* step 4\n"); + req = ablkcipher_request_alloc(tfm, GFP_KERNEL); + if (!req) { + AES_DBG(KERN_ERR "alg: skcipher: Failed to allocate request " + "for %s\n", algo); + return -1; + } + + AES_DBG(" *_* step 5\n"); + ablkcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, + tcrypt_complete, &result); + + AES_DBG(" *_* step 6\n"); + data = xbuf; + dst_data = dst_xbuf; + + //encrypt + memcpy(data, plain_des_tri_ecb_text, 24); + memset(dst_data, 0, 24); + sg_init_one(&sg[0], data, 24); + sg_init_one(&dst_sg[0], dst_data, 24); + + AES_DBG(" *_* step 7\n"); + ablkcipher_request_set_crypt(req, sg, dst_sg, 24, (void *)NULL); + fh_aes_set_crypto_key_source(p_def, CRYPTO_CPU_SET_KEY); + ablkcipher_request_set_usrdef(req, p_def); + AES_DBG(" *_* step 8\n"); + crypto_ablkcipher_encrypt(req); + + wait_for_completion(&result.completion); + + if (memcmp(dst_data, cipher_des_tri_ecb_text, 24)) + AES_PRINT_RESULT(" encrypt error....\n"); + else + AES_PRINT_RESULT(" encrypt ok....\n"); + + //decrypt + memcpy(data, cipher_des_tri_ecb_text, 24); + memset(dst_data, 0, 24); + sg_init_one(&sg[0], data, 24); + sg_init_one(&dst_sg[0], dst_data, 24); + + AES_DBG(" *_* step 8\n"); + ablkcipher_request_set_crypt(req, sg, dst_sg, 24, (void *)NULL); + + AES_DBG(" *_* step 9\n"); + crypto_ablkcipher_decrypt(req); + + wait_for_completion(&result.completion); + + if (memcmp(dst_data, plain_des_tri_ecb_text, 24)) + AES_PRINT_RESULT(" decrypt error....\n"); + else + AES_PRINT_RESULT(" decrypt ok....\n"); + + return 0; + +} + +static int fh_des_tri_cbc_self_test(void * xbuf, void* dst_xbuf, + struct af_alg_usr_def *p_def) +{ + struct crypto_ablkcipher *tfm; + struct ablkcipher_request *req; + const char *algo; + struct crypto_tfm * t_crytfm; + struct scatterlist sg[8]; + struct scatterlist dst_sg[8]; + u32 key[6] = { + DES_TRI_CBC_KEY0, DES_TRI_CBC_KEY1, DES_TRI_CBC_KEY2, + DES_TRI_CBC_KEY3, DES_TRI_CBC_KEY4, DES_TRI_CBC_KEY5 + }; + u32 iv[2] = { DES_TRI_CBC_IV0, DES_TRI_CBC_IV1 }; + + void *data; + void *dst_data; + + + memcpy(&key[0],&des3_cbc_key_buf[0],sizeof(des3_cbc_key_buf)); + memcpy(&iv[0],&des3_cbc_iv_buf[0],sizeof(des3_cbc_iv_buf)); + + AES_DBG("aes self test get in...\n"); + + AES_DBG(" *_* step 1\n"); + + + t_crytfm = crypto_alloc_base("cbc-des3-fh", + CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, 0); + if (IS_ERR(t_crytfm)) { + AES_DBG("aes_test: failed to alloc t_crytfm!\n"); + return -1; + } + tfm = __crypto_ablkcipher_cast(t_crytfm); + if (IS_ERR(tfm)) { + AES_DBG("aes_test: failed to alloc cipher!\n"); + return -1; + } + + + AES_DBG(" *_* step 2\n"); + algo = crypto_tfm_alg_driver_name(crypto_ablkcipher_tfm(tfm)); + init_completion(&result.completion); + + AES_DBG(" *_* step 3\n"); + crypto_ablkcipher_setkey(tfm, (u8 *) key, 24); + + AES_DBG(" *_* step 4\n"); + req = ablkcipher_request_alloc(tfm, GFP_KERNEL); + if (!req) { + AES_DBG(KERN_ERR "alg: skcipher: Failed to allocate request " + "for %s\n", algo); + return -1; + } + + AES_DBG(" *_* step 5\n"); + ablkcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, + tcrypt_complete, &result); + + AES_DBG(" *_* step 6\n"); + data = xbuf; + dst_data = dst_xbuf; + + //encrypt + memcpy(data, plain_des_tri_cbc_text, 24); + memset(dst_data, 0, 24); + sg_init_one(&sg[0], data, 24); + sg_init_one(&dst_sg[0], dst_data, 24); + + AES_DBG(" *_* step 7\n"); + ablkcipher_request_set_crypt(req, sg, dst_sg, 24, (void *)iv); + fh_aes_set_crypto_key_source(p_def, CRYPTO_CPU_SET_KEY); + ablkcipher_request_set_usrdef(req, p_def); + AES_DBG(" *_* step 8\n"); + crypto_ablkcipher_encrypt(req); + + wait_for_completion(&result.completion); + + if (memcmp(dst_data, cipher_des_tri_cbc_text, 24)) + AES_PRINT_RESULT(" encrypt error....\n"); + else + AES_PRINT_RESULT(" encrypt ok....\n"); + + //decrypt + memcpy(data, cipher_des_tri_cbc_text, 24); + memset(dst_data, 0, 24); + sg_init_one(&sg[0], data, 24); + sg_init_one(&dst_sg[0], dst_data, 24); + + AES_DBG(" *_* step 8\n"); + ablkcipher_request_set_crypt(req, sg, dst_sg, 24, (void *)iv); + + AES_DBG(" *_* step 9\n"); + crypto_ablkcipher_decrypt(req); + + wait_for_completion(&result.completion); + + if (memcmp(dst_data, plain_des_tri_cbc_text, 24)) + AES_PRINT_RESULT(" decrypt error....\n"); + else + AES_PRINT_RESULT(" decrypt ok....\n"); + + return 0; + +} + +#if(0) + +typedef struct +{ + unsigned int base; + void * vbase; + unsigned int size; +}MEM_INFO; +typedef struct { + MEM_INFO mem; + unsigned char *remap_base; /**<已用大小*/ +} RW_MEM_INFO; + + +static unsigned char aes_128_key_buf[] = { + 0x2b,0x7e,0x15,0x16, 0x28,0xae,0xd2,0xa6, 0xab,0xf7,0x15,0x88, 0x09,0xcf,0x4f,0x3c, +}; +static unsigned char plain_aes_128_text[] = { + 0x6b,0xc1,0xbe,0xe2, 0x2e,0x40,0x9f,0x96, 0xe9,0x3d,0x7e,0x11, 0x73,0x93,0x17,0x2a, + 0xae,0x2d,0x8a,0x57, 0x1e,0x03,0xac,0x9c, 0x9e,0xb7,0x6f,0xac, 0x45,0xaf,0x8e,0x51, + 0x30,0xc8,0x1c,0x46, 0xa3,0x5c,0xe4,0x11, 0xe5,0xfb,0xc1,0x19, 0x1a,0x0a,0x52,0xef, + 0xf6,0x9f,0x24,0x45, 0xdf,0x4f,0x9b,0x17, 0xad,0x2b,0x41,0x7b, 0xe6,0x6c,0x37,0x10, +}; + +static unsigned char cipher_aes_128_text[] = { + 0x3A,0xD7,0x7B,0xB4, 0x0D,0x7A,0x36,0x60, 0xA8,0x9E,0xCA,0xF3, 0x24,0x66,0xEF,0x97, + 0xf5,0xd3,0xd5,0x85, 0x03,0xb9,0x69,0x9d, 0xe7,0x85,0x89,0x5a, 0x96,0xfd,0xba,0xaf, + 0x43,0xb1,0xcd,0x7f, 0x59,0x8e,0xce,0x23, 0x88,0x1b,0x00,0xe3, 0xed,0x03,0x06,0x88, + 0x7b,0x0c,0x78,0x5e, 0x27,0xe8,0xad,0x3f, 0x82,0x23,0x20,0x71, 0x04,0x72,0x5d,0xd4, +}; + +int aes_128_ecb_encrypt(char *key_128, RW_MEM_INFO in, + RW_MEM_INFO out, unsigned int data_len_align16){ + + static char *xbuf; + static char *dst_xbuf; + static struct crypto_ablkcipher *tfm; + static struct ablkcipher_request *req; + static malloc_flag = 0; + const char *algo; + struct scatterlist sg[8]; + struct scatterlist dst_sg[8]; + void *data; + void *dst_data; + struct tcrypt_result wait_result; + +//malloc buf... + if(malloc_flag != 0){ + goto work_go; + } + malloc_flag = 1; + xbuf = (void *)__get_free_page(GFP_KERNEL); + if (!xbuf) { + printk("no pages.\n"); + return -1; + } + + dst_xbuf = (void *)__get_free_page(GFP_KERNEL); + if (!dst_xbuf) { + free_page((unsigned long)xbuf); + printk("no pages.\n"); + return -1; + } + + tfm = + cryptd_alloc_ablkcipher("ecb-aes-fh", + CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, 0); + if (IS_ERR(tfm)) { + printk("aes_test: failed to alloc cipher!\n"); + free_page((unsigned long)xbuf); + free_page((unsigned long)dst_xbuf); + return -1; + } + req = ablkcipher_request_alloc(tfm, GFP_KERNEL); + if (!req) { + printk(KERN_ERR "alg: skcipher: Failed to allocate request " + "for %s\n", algo); + return -1; + } + + +work_go: + printk("aes self test get in...\n"); + printk(" *_* step 1\n"); + + printk(" *_* step 2\n"); + algo = crypto_tfm_alg_driver_name(crypto_ablkcipher_tfm(tfm)); + init_completion(&wait_result.completion); + + printk(" *_* step 3\n"); + crypto_ablkcipher_setkey(tfm, (u8 *)key_128, 16); + + printk(" *_* step 4\n"); + + + printk(" *_* step 5\n"); + ablkcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, + tcrypt_complete, &wait_result); + + printk(" *_* step 6\n"); + data = xbuf; + dst_data = dst_xbuf; + + //encrypt + memcpy(data, in.remap_base, data_len_align16); + //memset(dst_data, 0, data_len_align16); + sg_init_one(&sg[0], data, data_len_align16); + sg_init_one(&dst_sg[0], dst_data, data_len_align16); + + printk(" *_* step 7\n"); + ablkcipher_request_set_crypt(req, sg, dst_sg, data_len_align16, NULL); + + printk(" *_* step 8\n"); + crypto_ablkcipher_encrypt(req); + + wait_for_completion(&wait_result.completion); + + memcpy(out.remap_base, dst_data, data_len_align16); + + return 0; + +} +#endif + +#if (0) +/* keymap test with efuse, must set keys in efuse first */ + +static struct ex_key_map_para ex_key_para = { + .map_size = sizeof(aes_cbc_key_buf) / sizeof(uint32_t), + .map = { {0, 0}, {1, 4}, {2, 8}, {3, 12} }, +}; + +static int fh_aes_cbc128_keymap_self_test(void *xbuf, void *dst_xbuf, + struct af_alg_usr_def *p_def) +{ + struct crypto_ablkcipher *tfm; + struct ablkcipher_request *req; + struct crypto_tfm *t_crytfm; + struct scatterlist sg[8]; + struct scatterlist dst_sg[8]; + const char *algo; + + void *data; + void *dst_data; + + u32 key[4] = { AES_KEY0, AES_KEY1, AES_KEY2, AES_KEY3 }; + u32 iv[4] = { AES_IV0, AES_IV1, AES_IV2, AES_IV3 }; + + memcpy(&key[0], &aes_cbc_key_buf[0], sizeof(aes_cbc_key_buf)); + memcpy(&iv[0], &aes_cbc_iv_buf[0], sizeof(aes_cbc_iv_buf)); + + AES_DBG("aes self test get in...\n"); + AES_DBG(" *_* step 1\n"); + t_crytfm = crypto_alloc_base("cbc-aes-fh", + CRYPTO_ALG_TYPE_ABLKCIPHER | + CRYPTO_ALG_ASYNC, 0); + if (IS_ERR(t_crytfm)) { + AES_DBG("aes_test: failed to alloc t_crytfm!\n"); + return -1; + } + tfm = __crypto_ablkcipher_cast(t_crytfm); + if (IS_ERR(tfm)) { + AES_DBG("aes_test: failed to alloc cipher!\n"); + return -1; + } + algo = crypto_tfm_alg_driver_name(crypto_ablkcipher_tfm(tfm)); + pr_info("driver name %s\n", algo); + init_completion(&result.completion); + AES_DBG(" *_* step 3\n"); + crypto_ablkcipher_setkey(tfm, (u8 *) key, 16); + + AES_DBG(" *_* step 4\n"); + req = ablkcipher_request_alloc(tfm, GFP_KERNEL); + if (!req) { + AES_DBG(KERN_ERR "alg: skcipher: Failed to allocate request " + "for %s\n", algo); + return -1; + } + + AES_DBG(" *_* step 5\n"); + ablkcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG, + tcrypt_complete, &result); + + AES_DBG(" *_* step 6\n"); + data = xbuf; + dst_data = dst_xbuf; + + //encrypt + memcpy(data, plain_text, 64); + memset(dst_data, 0, 64); + sg_init_one(&sg[0], data, 64); + sg_init_one(&dst_sg[0], dst_data, 64); + + AES_DBG(" *_* step 7\n"); + ablkcipher_request_set_crypt(req, sg, dst_sg, 64, (void *)iv); + + ablkcipher_request_set_usrdef(req, p_def); + AES_DBG(" *_* step 8\n"); + crypto_ablkcipher_encrypt(req); + + wait_for_completion(&result.completion); + + if (memcmp(dst_data, cipher_text, 64)) + AES_PRINT_RESULT(" encrypt error....\n"); + else + AES_PRINT_RESULT(" encrypt ok....\n"); + + //decrypt + memcpy(data, cipher_text, 64); + memset(dst_data, 0, 64); + sg_init_one(&sg[0], data, 64); + sg_init_one(&dst_sg[0], dst_data, 64); + AES_DBG(" *_* step 8\n"); + ablkcipher_request_set_crypt(req, sg, dst_sg, 64, (void *)iv); + AES_DBG(" *_* step 9\n"); + crypto_ablkcipher_decrypt(req); + wait_for_completion(&result.completion); + + if (memcmp(dst_data, plain_text, 64)) + AES_PRINT_RESULT(" decrypt error....\n"); + else + AES_PRINT_RESULT(" decrypt ok....\n"); + + return 0; +} +#endif + +int fh_aes_self_test_all(void) +{ + + static char *xbuf; + static char *dst_xbuf; + struct af_alg_usr_def usr_def = {0}; + + xbuf = (void *)__get_free_page(GFP_KERNEL); + if (!xbuf) { + printk("no pages.\n"); + return -1; + } + + dst_xbuf = (void *)__get_free_page(GFP_KERNEL); + if (!dst_xbuf) { + free_page((unsigned long)xbuf); + printk("no pages.\n"); + return -1; + } + + pr_info("aes cbc128 self test go...\n"); + fh_aes_cbc128_self_test(xbuf, dst_xbuf, &usr_def); + pr_info("aes ecb256 self test go...\n"); + fh_aes_ecb256_self_test(xbuf, dst_xbuf, &usr_def); + pr_info("aes ofb 256 self test go...\n"); + fh_aes_ofb256_self_test(xbuf, dst_xbuf, &usr_def); + pr_info("des ecb self test go...\n"); + fh_des_ecb_self_test(xbuf, dst_xbuf, &usr_def); + pr_info("des cbc self test go...\n"); + fh_des_cbc_self_test(xbuf, dst_xbuf, &usr_def); + pr_info("des ofb self test go...\n"); + fh_des_ofb_self_test(xbuf, dst_xbuf, &usr_def); + pr_info("des tri ecb self test go...\n"); + fh_des_tri_ecb_self_test(xbuf, dst_xbuf, &usr_def); + pr_info("des tri cbc self test go...\n"); + fh_des_tri_cbc_self_test(xbuf, dst_xbuf, &usr_def); + +#if (0) + pr_info("########## fh_aes_cbc128_keymap_self_test ###########\n"); + usr_def.mode = CRYPTO_EX_MEM_SET_KEY; + usr_def.adv.ex_key_para = ex_key_para; + fh_aes_cbc128_keymap_self_test(xbuf, dst_xbuf, &usr_def); + usr_def.mode = CRYPTO_EX_MEM_SWITCH_KEY | CRYPTO_EX_MEM_4_ENTRY_1_KEY + | CRYPTO_EX_MEM_SET_KEY; + fh_aes_cbc128_keymap_self_test(xbuf, dst_xbuf, &usr_def); +#endif + +#if (0) + RW_MEM_INFO in; + RW_MEM_INFO out; + unsigned char temp_buf[64] = {0}; + + in.remap_base = &plain_aes_128_text[0]; + out.remap_base = &temp_buf[0]; + + pr_info("chenjn self test go.....\n"); + + aes_128_ecb_encrypt(&aes_128_key_buf[0], in, + out, 64); + for (i = 0; i < sizeof(temp_buf); i++) + printk("cipher data[%d]:0x%x\n", i, temp_buf[i]); +#endif + + return 0; +} + +#endif diff --git a/drivers/cryptodev-linux-master/.gitignore b/drivers/cryptodev-linux-master/.gitignore new file mode 100644 index 00000000..685e8ebf --- /dev/null +++ b/drivers/cryptodev-linux-master/.gitignore @@ -0,0 +1,29 @@ +.*.cmd +.tmp_versions/ +*~ +Module.markers +Module.symvers +*.ko +*.o +*.mod.c +modules.order +tests/async_cipher +tests/async_hmac +tests/async_speed +tests/cipher +tests/cipher_comp +tests/hmac +tests/hmac_comp +tests/speed +tests/sha_speed +tests/hash_comp +tests/hashcrypt_speed +releases +scripts +version.h +tests/cipher-aead +tests/fullspeed +examples/aes +lib/benchmark +tests/cipher-aead-srtp +tests/cipher-gcm diff --git a/drivers/cryptodev-linux-master/AUTHORS b/drivers/cryptodev-linux-master/AUTHORS new file mode 100644 index 00000000..6f9408ec --- /dev/null +++ b/drivers/cryptodev-linux-master/AUTHORS @@ -0,0 +1,19 @@ +Michal Ludvig: + Initial implementation for linux 2.6.8 + +Nikos Mavrogiannopoulos: + Port to 2.6.27 and later, better compatibility + with OpenBSD (and FreeBSD) cryptodev and maintanance. + +Michael Weiser: + Porting to blkcipher async API. Several hardware drivers + only implemented this API. + +Phil Sutter: + Implemented a zero copy version of the internal engine. + +Dmitry Kasatkin: + Multi-update support for hash calculation. + + +Maintained by Nikos Mavrogiannopoulos (nmav [at] gnutls [dot] org) diff --git a/drivers/cryptodev-linux-master/COPYING b/drivers/cryptodev-linux-master/COPYING new file mode 100644 index 00000000..d159169d --- /dev/null +++ b/drivers/cryptodev-linux-master/COPYING @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. diff --git a/drivers/cryptodev-linux-master/INSTALL b/drivers/cryptodev-linux-master/INSTALL new file mode 100644 index 00000000..2754c593 --- /dev/null +++ b/drivers/cryptodev-linux-master/INSTALL @@ -0,0 +1,32 @@ +=== Installation instructions === + +Simply run: +$ make +# make install + +The first command compiles the code and generates the kernel module +and the latter installs the header files and the kernel module. + +After that you should set your system to load the kernel module on system +load. In most systems this can be done as: +# echo "cryptodev" >>/etc/modules + +or in systemd-enabled systems: +# echo "cryptodev" > /etc/modules-load.d/cryptodev.conf + +=== Testing installation === + +* cryptodev-linux: +Check whether cryptodev-linux is operating as expected using the following +command. +$ make check + +* OpenSSL: +run the following commands prior and after installation and compare. +$ openssl speed -evp aes-128-cbc +$ openssl speed -evp sha1 + +* GnuTLS 3.x: +run the following command prior and after installation and compare. +$ gnutls-cli --benchmark-ciphers + diff --git a/drivers/cryptodev-linux-master/Kconfig b/drivers/cryptodev-linux-master/Kconfig new file mode 100644 index 00000000..e6c382e9 --- /dev/null +++ b/drivers/cryptodev-linux-master/Kconfig @@ -0,0 +1,6 @@ + +config CRYPTODEV +tristate "Support cryptodev" +default n +help + Support \dev\crypto diff --git a/drivers/cryptodev-linux-master/Makefile b/drivers/cryptodev-linux-master/Makefile new file mode 100644 index 00000000..6c3bc8ba --- /dev/null +++ b/drivers/cryptodev-linux-master/Makefile @@ -0,0 +1,68 @@ +# +# Since version 1.6 the asynchronous mode has been +# disabled by default. To re-enable it uncomment the +# corresponding CFLAG. +# + +CRYPTODEV_CFLAGS ?= #-DENABLE_ASYNC +KBUILD_CFLAGS += -I$(src) $(CRYPTODEV_CFLAGS) -Wvla +KERNEL_DIR ?= /lib/modules/$(shell uname -r)/build +VERSION = 1.11 + +prefix ?= /usr/local +includedir = $(prefix)/include + +cryptodev-objs = ioctl.o main.o cryptlib.o authenc.o zc.o util.o + +obj-$(CONFIG_CRYPTODEV) += cryptodev.o + +KERNEL_MAKE_OPTS := -C $(KERNEL_DIR) M=$(CURDIR) +ifneq ($(ARCH),) +KERNEL_MAKE_OPTS += ARCH=$(ARCH) +endif +ifneq ($(CROSS_COMPILE),) +KERNEL_MAKE_OPTS += CROSS_COMPILE=$(CROSS_COMPILE) +endif + +build: version.h + $(MAKE) $(KERNEL_MAKE_OPTS) modules + +version.h: Makefile + @echo "#define VERSION \"$(VERSION)\"" > version.h + +install: modules_install + +modules_install: + $(MAKE) $(KERNEL_MAKE_OPTS) modules_install + install -m 644 -D crypto/cryptodev.h $(DESTDIR)/$(includedir)/crypto/cryptodev.h + +clean: + $(MAKE) $(KERNEL_MAKE_OPTS) clean + rm -f $(hostprogs) *~ + CFLAGS=$(CRYPTODEV_CFLAGS) KERNEL_DIR=$(KERNEL_DIR) $(MAKE) -C tests clean + +check: + CFLAGS=$(CRYPTODEV_CFLAGS) KERNEL_DIR=$(KERNEL_DIR) $(MAKE) -C tests check + +CPOPTS = +ifneq ($(SHOW_TYPES),) +CPOPTS += --show-types +endif +ifneq ($(IGNORE_TYPES),) +CPOPTS += --ignore $(IGNORE_TYPES) +endif + +checkpatch: + $(KERNEL_DIR)/scripts/checkpatch.pl $(CPOPTS) --file *.c *.h + +VERSIONTAG = refs/tags/cryptodev-linux-$(VERSION) +FILEBASE = cryptodev-linux-$(VERSION) +OUTPUT = $(FILEBASE).tar.gz + +dist: clean + @echo Packing + @rm -f *.tar.gz + @git archive --format=tar.gz --prefix=$(FILEBASE)/ --output=$(OUTPUT) $(VERSIONTAG) + @echo Signing $(OUTPUT) + @gpg --output $(OUTPUT).sig -sb $(OUTPUT) + @gpg --verify $(OUTPUT).sig $(OUTPUT) diff --git a/drivers/cryptodev-linux-master/NEWS b/drivers/cryptodev-linux-master/NEWS new file mode 100644 index 00000000..54b58bd6 --- /dev/null +++ b/drivers/cryptodev-linux-master/NEWS @@ -0,0 +1,261 @@ +Version 1.11 (released 2020-7-28) + +* Fix Module loading with Linux kernel <= 5.0 +* Fix compilation issues against Linux kernel >= 5.5 +* Fix compilation issues against Linux kernel >= 5.8 +* enable support for TLS1.1 - AES128-SHA1 and AES256-SHA1 +* fix cipher-aead-strp dts buffer alignment issue +* remove VLA usage from authenc.c + +Version 1.10 (released 2018-12-20) + +* Fix compilation issues against Linux kernel >= 4.11 and gcc >= 5 +* Add CIOCCPHASH ioctl +* Fix tests build for OpenSSL 1.1 +* Convert to new AEAD kernel crypto interface +* A variety of bug fixes + +Version 1.9 (released 2017-04-22) + +* fix benchmarks linking + +* fix Makefile to allow parallel make with -j option + +* use Linux kernel conventions for Makefile variables + +* for consistency, use $(...) instead of ${...} in makefiles + +* fix clean-up on error path for crypto_create_session + +* remove code duplication in cryptodev_hash_init + +* add separate target for building tests + +* fix destination for staged installs + +* add install target for tests + +* fix comment typo + +* avoid calls to kmalloc on hotpaths + +* avoid redundant checks in cryptodev_hash_deinit + +* Fix test compile time warnings + +* Support skcipher in addition to ablkcipher API + +* Adjust to recent user page API changes + +* Adjust to another change in the user page API + +* fix issues with install target + +* setting KERNEL_DIR is not necessary to build tests + +* fix ignored SIGALRM signals on some platforms + +* fix incorrect return code in case of error from openssl_cioccrypt + +* remove not used local variables + +* fix warnings of "implicit declaration of function" in async_speed + +* rename header file to clarify purpose + +* use buf_align macro to reduce code duplication + +* avoid implicit conversion between signed and unsigned char + +* do more strict code checking to avoid maintenance issues + +* adjust to API changes in kernel >=4.10 + +* zc: Use the power of #elif + +* Fix ablkcipher algorithms usage in v4.8+ kernels + +Version 1.8 (released 2015-11-28) + +* Fixed compilation against linux-3.19. + +* Tests: cixed arg passing to CC in implicit rule. + +* Fix tag printing in cipher-gcm test by Fridolin Pokorny. + +* Fix compilation against linux 4.3 by Gustavo Zacarias. + +Version 1.7 (released 2015-02-07) + +* Added support for composite AEAD keys by Cristian Stoica. + +* Added support for sysctl to modify verbosity by Nikolaos Tsakalakis. + +* Several bugfixes by Cristian Stoica. + +* When a driver requires aligned data but unaligned are provided, then + zero copy is disabled to prevent driver failing to encrypt. + +* Compatibility to kernel version 3.13 and above by Cosmin Paraschiv. + +* Various checkpatch.pl fixes. + +* Introduced ddebug, dinfo, dwarning and derr macros wrapping dprintk. + +* Improved support for cross-compiling. + +* Hmac_comp test has become more picky when checking results. + +* Fixed allocated resource cleanup in error case, patch by Cristian Stoica. + +* Buffer size allocation fixup for AEAD modes by Nikos Mavrogiannopoulos. + +* Support for composite AEAD keys added by Cristian Stoica. + +* Fixed tag and dsl_len calculation for AEAD ciphers, patch by Cristian Stoica. + +* Documentation updates by Nikos Mavrogiannopoulos. + + +Version 1.6 (released 2013-03-20) + +* Added modules_install target in Makefile + +* Added SHA224. Patch by Yashpal Dutta. + +* Asynchronous operations will not be scheduled if zero copy is disabled. + +* Asynchronous operations are disabled by default, unless -DENABLE_ASYNC + is enabled on Makefile. + + +Version 1.5 (released 2012-08-04) + +* Fixes in AEAD support. Patches by Jaren Johnston. + +* Simplifications in memory locking. Patch by Phil Sutter. + +* Allow empty plaintext and authenticated data in AEAD ciphers. + Patch by Jaren Johnston. + + +Version 1.4 (released 2012-03-15) + +* Correctly report hw accelerated ciphers. + + +Version 1.3 (released 2012-02-29) + +* Return EBADMSG instead of ECANCELED on tag verification failure in + authenc modes. + +* COP_FLAG_RESET can be combined with COP_FLAG_UPDATE for efficiency. + +* Added more test cases. + +* Automatically set public permissions for the device + + +Version 1.2 (released 2012-02-24) + +* In kernels that do not distinguish between hw accelerated ciphers or + not set the SIOP_FLAG_KERNEL_DRIVER_ONLY flag based on driver name. + +* camelia was renamed to camellia. + +* Added COP_FLAG_RESET to allow resetting the state in multi-update. + +* Corrected issue in ARM processors with mv_cesa. + + +Version 1.1 (released 2012-02-20) + +* Fixed alignment issue in speed.c + +* Defined HASH_MAX_LEN in cryptodev.h + +* CIOCGSESSINFO ioctl() sets the SIOP_FLAG_KERNEL_DRIVER_ONLY flag if the + driver is only available through kernel driver (and is not just software + cipher). + +* Added new encryption ioctl, CIOCAUTHCRYPT, which combines authentication + and encryption. Operates in AEAD, TLS and SRTP modes (the API might change + in later versions). + + +Version 1.0 (released 2011-04-12) + +* Several fixes in the included examples. Based on patches by Vladimir + Zapolskiy. + + +Version 0.9 (released 2011-02-11) + +* Added additional test tools: + - sha_speed does performance testing of SHA1 and SHA256 + - hashcrypt_speed additionally encrypts with AES128 and AES256 + +* Allow updating the IV in userspace via the COP_FLAG_WRITE_IV flag. + +* Export the alignmask in an OCF compatible way. + +* Fix for kernel crash on passing incorrect session ID. + +* Added CIOCGSESSINFO to export additional information for each session. + + +Version 0.8 (released 2010-11-06) + +* Made cryptodev aware of alignment constraints. + +* Added support for CRYPTO_AES_ECB. + +* Added asynchronous operation support using + CIOCASYNCCRYPT, CIOCASYNCFETCH ioctls and poll(). + + +Version 0.7 (released 2010-10-08) + +* Added COP_FLAG_FINAL to make multi-update more efficient. + +* Added CRIOGET_NOT_NEEDED definition to allow users of the API to + distinguish from the bare OpenBSD API that requires the CRIOGET. + + +Version 0.6 (released 2010-09-16) + +* multi-update support for hash calculation using the new flag + COP_FLAG_UPDATE. + +* Relicensed under GPLv2. + +* Added AES-CTR. + +* Corrected fallback to non-zero copy when referenced pages were + not writable. + + +Version 0.5 (released 2010-07-06) + +* Corrected issue with zero copy on multiple pages. + +* Fallback to normal operation if user pages cannot be mapped. + + +Version 0.4 (released 2010-07-03) + +* Internal engine supports operations with zero copy from user space. + + +Version 0.3 (released 2010-06-19) + +* Corrected bug when initializing unsupported algorithms. + + +Version 0.2 (released 2010-06-18) + +* Added compat_ioctl() to allow working on systems where userspace is 32bits + and kernel is operating in 64bit mode (Phil Sutter) + +* Added several sanity checks to input. + diff --git a/drivers/cryptodev-linux-master/README b/drivers/cryptodev-linux-master/README new file mode 100644 index 00000000..eb192046 --- /dev/null +++ b/drivers/cryptodev-linux-master/README @@ -0,0 +1,40 @@ +This is a /dev/crypto device driver, equivalent to those in OpenBSD or +FreeBSD. The main idea is to access of existing ciphers in kernel space +from userspace, thus enabling the re-use of a hardware implementation of a +cipher. + +For questions and suggestions please use the mailing lists at: +http://cryptodev-linux.org/lists.html + + +=== How to combine with cryptographic libraries === + +* GnuTLS: + +GnuTLS needs to be compiled with --enable-cryptodev in order to take +advantage of /dev/crypto. GnuTLS 3.0.14 or later is recommended. + +* OpenSSL: + +Note that OpenSSL's cryptodev implementation is outdated, and there +are issues with it. For that we recommend to use the patches +below, that we have provided to the openssl project. + +http://rt.openssl.org/Ticket/Display.html?id=2770&user=guest&pass=guest + +After applying the patches you can add cryptodev support by using the +-DHAVE_CRYPTODEV and -DUSE_CRYPTODEV_DIGESTS flags during compilation. +Note that the latter flag (digests) may induce a performance penalty +in some systems. + + +=== Modifying and viewing verbosity at runtime === + +For debugging often the verbosity of the driver needs to be adjusted. +The sysctl tool can be used for that. + +# sysctl ioctl.cryptodev_verbosity +ioctl.cryptodev_verbosity = 0 + +# sysctl ioctl.cryptodev_verbosity=3 +ioctl.cryptodev_verbosity = 3 diff --git a/drivers/cryptodev-linux-master/authenc.c b/drivers/cryptodev-linux-master/authenc.c new file mode 100644 index 00000000..269b826d --- /dev/null +++ b/drivers/cryptodev-linux-master/authenc.c @@ -0,0 +1,850 @@ +/* + * Driver for /dev/crypto device (aka CryptoDev) + * + * Copyright (c) 2011, 2012 OpenSSL Software Foundation, Inc. + * + * Author: Nikos Mavrogiannopoulos + * + * This file is part of linux cryptodev. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +/* + * This file handles the AEAD part of /dev/crypto. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cryptodev_int.h" +#include "zc.h" +#include "util.h" +#include "cryptlib.h" +#include "version.h" + + +/* make caop->dst available in scatterlist. + * (caop->src is assumed to be equal to caop->dst) + */ +static int get_userbuf_tls(struct csession *ses, struct kernel_crypt_auth_op *kcaop, + struct scatterlist **dst_sg) +{ + int pagecount = 0; + struct crypt_auth_op *caop = &kcaop->caop; + int rc; + + if (caop->dst == NULL) + return -EINVAL; + + if (ses->alignmask) { + if (!IS_ALIGNED((unsigned long)caop->dst, ses->alignmask + 1)) + dwarning(2, "careful - source address %p is not %d byte aligned", + caop->dst, ses->alignmask + 1); + } + + if (kcaop->dst_len == 0) { + dwarning(1, "Destination length cannot be zero"); + return -EINVAL; + } + + pagecount = PAGECOUNT(caop->dst, kcaop->dst_len); + + ses->used_pages = pagecount; + ses->readonly_pages = 0; + + rc = adjust_sg_array(ses, pagecount); + if (rc) + return rc; + + rc = __get_userbuf(caop->dst, kcaop->dst_len, 1, pagecount, + ses->pages, ses->sg, kcaop->task, kcaop->mm); + if (unlikely(rc)) { + derr(1, "failed to get user pages for data input"); + return -EINVAL; + } + + (*dst_sg) = ses->sg; + + return 0; +} + + +#define MAX_SRTP_AUTH_DATA_DIFF 256 + +/* Makes caop->auth_src available as scatterlist. + * It also provides a pointer to caop->dst, which however, + * is assumed to be within the caop->auth_src buffer. If not + * (if their difference exceeds MAX_SRTP_AUTH_DATA_DIFF) it + * returns error. + */ +static int get_userbuf_srtp(struct csession *ses, struct kernel_crypt_auth_op *kcaop, + struct scatterlist **auth_sg, struct scatterlist **dst_sg) +{ + int pagecount, diff; + int auth_pagecount = 0; + struct crypt_auth_op *caop = &kcaop->caop; + int rc; + + if (caop->dst == NULL && caop->auth_src == NULL) { + derr(1, "dst and auth_src cannot be both null"); + return -EINVAL; + } + + if (ses->alignmask) { + if (!IS_ALIGNED((unsigned long)caop->dst, ses->alignmask + 1)) + dwarning(2, "careful - source address %p is not %d byte aligned", + caop->dst, ses->alignmask + 1); + if (!IS_ALIGNED((unsigned long)caop->auth_src, ses->alignmask + 1)) + dwarning(2, "careful - source address %p is not %d byte aligned", + caop->auth_src, ses->alignmask + 1); + } + + if (unlikely(kcaop->dst_len == 0 || caop->auth_len == 0)) { + dwarning(1, "Destination length cannot be zero"); + return -EINVAL; + } + + /* Note that in SRTP auth data overlap with data to be encrypted (dst) + */ + + auth_pagecount = PAGECOUNT(caop->auth_src, caop->auth_len); + diff = (int)(caop->src - caop->auth_src); + if (diff > MAX_SRTP_AUTH_DATA_DIFF || diff < 0) { + dwarning(1, "auth_src must overlap with src (diff: %d).", diff); + return -EINVAL; + } + + pagecount = auth_pagecount; + + rc = adjust_sg_array(ses, pagecount*2); /* double pages to have pages for dst(=auth_src) */ + if (rc) { + derr(1, "cannot adjust sg array"); + return rc; + } + + rc = __get_userbuf(caop->auth_src, caop->auth_len, 1, auth_pagecount, + ses->pages, ses->sg, kcaop->task, kcaop->mm); + if (unlikely(rc)) { + derr(1, "failed to get user pages for data input"); + return -EINVAL; + } + + ses->used_pages = pagecount; + ses->readonly_pages = 0; + + (*auth_sg) = ses->sg; + + (*dst_sg) = ses->sg + auth_pagecount; + sg_init_table(*dst_sg, auth_pagecount); + sg_copy(ses->sg, (*dst_sg), caop->auth_len); + (*dst_sg) = sg_advance(*dst_sg, diff); + if (*dst_sg == NULL) { + release_user_pages(ses); + derr(1, "failed to get enough pages for auth data"); + return -EINVAL; + } + + return 0; +} + +/* + * Return tag (digest) length for authenticated encryption + * If the cipher and digest are separate, hdata.init is set - just return + * digest length. Otherwise return digest length for aead ciphers + */ +static int cryptodev_get_tag_len(struct csession *ses_ptr) +{ + if (ses_ptr->hdata.init) + return ses_ptr->hdata.digestsize; + else + return cryptodev_cipher_get_tag_size(&ses_ptr->cdata); +} + +/* + * Calculate destination buffer length for authenticated encryption. The + * expectation is that user-space code allocates exactly the same space for + * destination buffer before calling cryptodev. The result is cipher-dependent. + */ +static int cryptodev_get_dst_len(struct crypt_auth_op *caop, struct csession *ses_ptr) +{ + int dst_len = caop->len; + if (caop->op == COP_DECRYPT) + return dst_len; + + dst_len += caop->tag_len; + + /* for TLS always add some padding so the total length is rounded to + * cipher block size */ + if (caop->flags & COP_FLAG_AEAD_TLS_TYPE) { + int bs = ses_ptr->cdata.blocksize; + dst_len += bs - (dst_len % bs); + } + + return dst_len; +} + +static int fill_kcaop_from_caop(struct kernel_crypt_auth_op *kcaop, struct fcrypt *fcr) +{ + struct crypt_auth_op *caop = &kcaop->caop; + struct csession *ses_ptr; + int ret; + + /* this also enters ses_ptr->sem */ + ses_ptr = crypto_get_session_by_sid(fcr, caop->ses); + if (unlikely(!ses_ptr)) { + derr(1, "invalid session ID=0x%08X", caop->ses); + return -EINVAL; + } + + if (caop->flags & COP_FLAG_AEAD_TLS_TYPE || caop->flags & COP_FLAG_AEAD_SRTP_TYPE) { + if (caop->src != caop->dst) { + derr(1, "Non-inplace encryption and decryption is not efficient and not implemented"); + ret = -EINVAL; + goto out_unlock; + } + } + + if (caop->tag_len == 0) + caop->tag_len = cryptodev_get_tag_len(ses_ptr); + + kcaop->ivlen = caop->iv ? ses_ptr->cdata.ivsize : 0; + kcaop->dst_len = cryptodev_get_dst_len(caop, ses_ptr); + kcaop->task = current; + kcaop->mm = current->mm; + + if (caop->iv) { + ret = copy_from_user(kcaop->iv, caop->iv, kcaop->ivlen); + if (unlikely(ret)) { + derr(1, "error copying IV (%d bytes), copy_from_user returned %d for address %p", + kcaop->ivlen, ret, caop->iv); + ret = -EFAULT; + goto out_unlock; + } + } + + ret = 0; + +out_unlock: + crypto_put_session(ses_ptr); + return ret; + +} + +static int fill_caop_from_kcaop(struct kernel_crypt_auth_op *kcaop, struct fcrypt *fcr) +{ + int ret; + + kcaop->caop.len = kcaop->dst_len; + + if (kcaop->ivlen && kcaop->caop.flags & COP_FLAG_WRITE_IV) { + ret = copy_to_user(kcaop->caop.iv, + kcaop->iv, kcaop->ivlen); + if (unlikely(ret)) { + derr(1, "Error in copying to userspace"); + return -EFAULT; + } + } + return 0; +} + + +int kcaop_from_user(struct kernel_crypt_auth_op *kcaop, + struct fcrypt *fcr, void __user *arg) +{ + if (unlikely(copy_from_user(&kcaop->caop, arg, sizeof(kcaop->caop)))) { + derr(1, "Error in copying from userspace"); + return -EFAULT; + } + + return fill_kcaop_from_caop(kcaop, fcr); +} + +int kcaop_to_user(struct kernel_crypt_auth_op *kcaop, + struct fcrypt *fcr, void __user *arg) +{ + int ret; + + ret = fill_caop_from_kcaop(kcaop, fcr); + if (unlikely(ret)) { + derr(1, "fill_caop_from_kcaop"); + return ret; + } + + if (unlikely(copy_to_user(arg, &kcaop->caop, sizeof(kcaop->caop)))) { + derr(1, "Error in copying to userspace"); + return -EFAULT; + } + return 0; +} + +static void copy_tls_hash(struct scatterlist *dst_sg, int len, void *hash, int hash_len) +{ + scatterwalk_map_and_copy(hash, dst_sg, len, hash_len, 1); +} + +static void read_tls_hash(struct scatterlist *dst_sg, int len, void *hash, int hash_len) +{ + scatterwalk_map_and_copy(hash, dst_sg, len - hash_len, hash_len, 0); +} + +#define TLS_MAX_PADDING_SIZE 256 +static int pad_record(struct scatterlist *dst_sg, int len, int block_size) +{ + uint8_t pad[TLS_MAX_PADDING_SIZE]; + int pad_size = block_size - (len % block_size); + + memset(pad, pad_size - 1, pad_size); + + scatterwalk_map_and_copy(pad, dst_sg, len, pad_size, 1); + + return pad_size; +} + +static int verify_tls_record_pad(struct scatterlist *dst_sg, int len, int block_size) +{ + uint8_t pad[TLS_MAX_PADDING_SIZE]; + uint8_t pad_size; + int i; + + scatterwalk_map_and_copy(&pad_size, dst_sg, len - 1, 1, 0); + + if (pad_size + 1 > len) { + derr(1, "Pad size: %d", pad_size); + return -EBADMSG; + } + + scatterwalk_map_and_copy(pad, dst_sg, len - pad_size - 1, pad_size + 1, 0); + + for (i = 0; i < pad_size; i++) + if (pad[i] != pad_size) { + derr(1, "Pad size: %u, pad: %d", pad_size, pad[i]); + return -EBADMSG; + } + + return pad_size + 1; +} + +/* Authenticate and encrypt the TLS way (also perform padding). + * During decryption it verifies the pad and tag and returns -EBADMSG on error. + */ +static int +tls_auth_n_crypt(struct csession *ses_ptr, struct kernel_crypt_auth_op *kcaop, + struct scatterlist *auth_sg, uint32_t auth_len, + struct scatterlist *dst_sg, uint32_t len) +{ + int ret, fail = 0; + struct crypt_auth_op *caop = &kcaop->caop; + uint8_t vhash[AALG_MAX_RESULT_LEN]; + uint8_t hash_output[AALG_MAX_RESULT_LEN]; + + /* TLS authenticates the plaintext except for the padding. + */ + if (caop->op == COP_ENCRYPT) { + if (ses_ptr->hdata.init != 0) { + if (auth_len > 0) { + ret = cryptodev_hash_update(&ses_ptr->hdata, + auth_sg, auth_len); + if (unlikely(ret)) { + derr(0, "cryptodev_hash_update: %d", ret); + return ret; + } + } + + if (len > 0) { + ret = cryptodev_hash_update(&ses_ptr->hdata, + dst_sg, len); + if (unlikely(ret)) { + derr(0, "cryptodev_hash_update: %d", ret); + return ret; + } + } + + ret = cryptodev_hash_final(&ses_ptr->hdata, hash_output); + if (unlikely(ret)) { + derr(0, "cryptodev_hash_final: %d", ret); + return ret; + } + + copy_tls_hash(dst_sg, len, hash_output, caop->tag_len); + len += caop->tag_len; + } + + if (ses_ptr->cdata.init != 0) { + if (ses_ptr->cdata.blocksize > 1) { + ret = pad_record(dst_sg, len, ses_ptr->cdata.blocksize); + len += ret; + } + + ret = cryptodev_cipher_encrypt(&ses_ptr->cdata, + dst_sg, dst_sg, len); + if (unlikely(ret)) { + derr(0, "cryptodev_cipher_encrypt: %d", ret); + return ret; + } + } + } else { + if (ses_ptr->cdata.init != 0) { + ret = cryptodev_cipher_decrypt(&ses_ptr->cdata, + dst_sg, dst_sg, len); + + if (unlikely(ret)) { + derr(0, "cryptodev_cipher_decrypt: %d", ret); + return ret; + } + + if (ses_ptr->cdata.blocksize > 1) { + ret = verify_tls_record_pad(dst_sg, len, ses_ptr->cdata.blocksize); + if (unlikely(ret < 0)) { + derr(2, "verify_record_pad: %d", ret); + fail = 1; + } else { + len -= ret; + } + } + } + + if (ses_ptr->hdata.init != 0) { + if (unlikely(caop->tag_len > sizeof(vhash) || caop->tag_len > len)) { + derr(1, "Illegal tag len size"); + return -EINVAL; + } + + read_tls_hash(dst_sg, len, vhash, caop->tag_len); + len -= caop->tag_len; + + if (auth_len > 0) { + ret = cryptodev_hash_update(&ses_ptr->hdata, + auth_sg, auth_len); + if (unlikely(ret)) { + derr(0, "cryptodev_hash_update: %d", ret); + return ret; + } + } + + if (len > 0) { + ret = cryptodev_hash_update(&ses_ptr->hdata, + dst_sg, len); + if (unlikely(ret)) { + derr(0, "cryptodev_hash_update: %d", ret); + return ret; + } + } + + ret = cryptodev_hash_final(&ses_ptr->hdata, hash_output); + if (unlikely(ret)) { + derr(0, "cryptodev_hash_final: %d", ret); + return ret; + } + + if (memcmp(vhash, hash_output, caop->tag_len) != 0 || fail != 0) { + derr(2, "MAC verification failed (tag_len: %d)", caop->tag_len); + return -EBADMSG; + } + } + } + kcaop->dst_len = len; + return 0; +} + +/* Authenticate and encrypt the SRTP way. During decryption + * it verifies the tag and returns -EBADMSG on error. + */ +static int +srtp_auth_n_crypt(struct csession *ses_ptr, struct kernel_crypt_auth_op *kcaop, + struct scatterlist *auth_sg, uint32_t auth_len, + struct scatterlist *dst_sg, uint32_t len) +{ + int ret, fail = 0; + struct crypt_auth_op *caop = &kcaop->caop; + uint8_t vhash[AALG_MAX_RESULT_LEN]; + uint8_t hash_output[AALG_MAX_RESULT_LEN]; + + /* SRTP authenticates the encrypted data. + */ + if (caop->op == COP_ENCRYPT) { + if (ses_ptr->cdata.init != 0) { + ret = cryptodev_cipher_encrypt(&ses_ptr->cdata, + dst_sg, dst_sg, len); + if (unlikely(ret)) { + derr(0, "cryptodev_cipher_encrypt: %d", ret); + return ret; + } + } + + if (ses_ptr->hdata.init != 0) { + if (auth_len > 0) { + ret = cryptodev_hash_update(&ses_ptr->hdata, + auth_sg, auth_len); + if (unlikely(ret)) { + derr(0, "cryptodev_hash_update: %d", ret); + return ret; + } + } + + ret = cryptodev_hash_final(&ses_ptr->hdata, hash_output); + if (unlikely(ret)) { + derr(0, "cryptodev_hash_final: %d", ret); + return ret; + } + + if (unlikely(copy_to_user(caop->tag, hash_output, caop->tag_len))) + return -EFAULT; + } + + } else { + if (ses_ptr->hdata.init != 0) { + if (unlikely(caop->tag_len > sizeof(vhash) || caop->tag_len > len)) { + derr(1, "Illegal tag len size"); + return -EINVAL; + } + + if (unlikely(copy_from_user(vhash, caop->tag, caop->tag_len))) + return -EFAULT; + + ret = cryptodev_hash_update(&ses_ptr->hdata, + auth_sg, auth_len); + if (unlikely(ret)) { + derr(0, "cryptodev_hash_update: %d", ret); + return ret; + } + + ret = cryptodev_hash_final(&ses_ptr->hdata, hash_output); + if (unlikely(ret)) { + derr(0, "cryptodev_hash_final: %d", ret); + return ret; + } + + if (memcmp(vhash, hash_output, caop->tag_len) != 0 || fail != 0) { + derr(2, "MAC verification failed"); + return -EBADMSG; + } + } + + if (ses_ptr->cdata.init != 0) { + ret = cryptodev_cipher_decrypt(&ses_ptr->cdata, + dst_sg, dst_sg, len); + + if (unlikely(ret)) { + derr(0, "cryptodev_cipher_decrypt: %d", ret); + return ret; + } + } + + } + kcaop->dst_len = len; + return 0; +} + +/* Typical AEAD (i.e. GCM) encryption/decryption. + * During decryption the tag is verified. + */ +static int +auth_n_crypt(struct csession *ses_ptr, struct kernel_crypt_auth_op *kcaop, + struct scatterlist *auth_sg, uint32_t auth_len, + struct scatterlist *src_sg, + struct scatterlist *dst_sg, uint32_t len) +{ + int ret; + struct crypt_auth_op *caop = &kcaop->caop; + int max_tag_len; + + max_tag_len = cryptodev_cipher_get_tag_size(&ses_ptr->cdata); + if (unlikely(caop->tag_len > max_tag_len)) { + derr(0, "Illegal tag length: %d", caop->tag_len); + return -EINVAL; + } + + if (caop->tag_len) + cryptodev_cipher_set_tag_size(&ses_ptr->cdata, caop->tag_len); + else + caop->tag_len = max_tag_len; + + cryptodev_cipher_auth(&ses_ptr->cdata, auth_sg, auth_len); + + if (caop->op == COP_ENCRYPT) { + ret = cryptodev_cipher_encrypt(&ses_ptr->cdata, + src_sg, dst_sg, len); + if (unlikely(ret)) { + derr(0, "cryptodev_cipher_encrypt: %d", ret); + return ret; + } + kcaop->dst_len = len + caop->tag_len; + caop->tag = caop->dst + len; + } else { + ret = cryptodev_cipher_decrypt(&ses_ptr->cdata, + src_sg, dst_sg, len); + + if (unlikely(ret)) { + derr(0, "cryptodev_cipher_decrypt: %d", ret); + return ret; + } + kcaop->dst_len = len - caop->tag_len; + caop->tag = caop->dst + len - caop->tag_len; + } + + return 0; +} + +static int crypto_auth_zc_srtp(struct csession *ses_ptr, struct kernel_crypt_auth_op *kcaop) +{ + struct scatterlist *dst_sg, *auth_sg; + struct crypt_auth_op *caop = &kcaop->caop; + int ret; + + if (unlikely(ses_ptr->cdata.init != 0 && + (ses_ptr->cdata.stream == 0 || ses_ptr->cdata.aead != 0))) { + derr(0, "Only stream modes are allowed in SRTP mode (but not AEAD)"); + return -EINVAL; + } + + ret = get_userbuf_srtp(ses_ptr, kcaop, &auth_sg, &dst_sg); + if (unlikely(ret)) { + derr(1, "get_userbuf_srtp(): Error getting user pages."); + return ret; + } + + ret = srtp_auth_n_crypt(ses_ptr, kcaop, auth_sg, caop->auth_len, + dst_sg, caop->len); + + release_user_pages(ses_ptr); + + return ret; +} + +static int crypto_auth_zc_tls(struct csession *ses_ptr, struct kernel_crypt_auth_op *kcaop) +{ + struct crypt_auth_op *caop = &kcaop->caop; + struct scatterlist *dst_sg, *auth_sg; + unsigned char *auth_buf = NULL; + struct scatterlist tmp; + int ret; + + if (unlikely(caop->auth_len > PAGE_SIZE)) { + derr(1, "auth data len is excessive."); + return -EINVAL; + } + + auth_buf = (char *)__get_free_page(GFP_KERNEL); + if (unlikely(!auth_buf)) { + derr(1, "unable to get a free page."); + return -ENOMEM; + } + + if (caop->auth_src && caop->auth_len > 0) { + if (unlikely(copy_from_user(auth_buf, caop->auth_src, caop->auth_len))) { + derr(1, "unable to copy auth data from userspace."); + ret = -EFAULT; + goto free_auth_buf; + } + + sg_init_one(&tmp, auth_buf, caop->auth_len); + auth_sg = &tmp; + } else { + auth_sg = NULL; + } + + ret = get_userbuf_tls(ses_ptr, kcaop, &dst_sg); + if (unlikely(ret)) { + derr(1, "get_userbuf_tls(): Error getting user pages."); + goto free_auth_buf; + } + + ret = tls_auth_n_crypt(ses_ptr, kcaop, auth_sg, caop->auth_len, + dst_sg, caop->len); + release_user_pages(ses_ptr); + +free_auth_buf: + free_page((unsigned long)auth_buf); + return ret; +} + +static int crypto_auth_zc_aead(struct csession *ses_ptr, struct kernel_crypt_auth_op *kcaop) +{ + struct scatterlist *dst_sg; + struct scatterlist *src_sg; + struct crypt_auth_op *caop = &kcaop->caop; + unsigned char *auth_buf = NULL; + int ret; + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 2, 0)) + struct scatterlist tmp; + struct scatterlist *auth_sg; +#else + struct scatterlist auth1[2]; + struct scatterlist auth2[2]; +#endif + + if (unlikely(ses_ptr->cdata.init == 0 || + (ses_ptr->cdata.stream == 0 && ses_ptr->cdata.aead == 0))) { + derr(0, "Only stream and AEAD ciphers are allowed for authenc"); + return -EINVAL; + } + + if (unlikely(caop->auth_len > PAGE_SIZE)) { + derr(1, "auth data len is excessive."); + return -EINVAL; + } + + auth_buf = (char *)__get_free_page(GFP_KERNEL); + if (unlikely(!auth_buf)) { + derr(1, "unable to get a free page."); + return -ENOMEM; + } + + ret = get_userbuf(ses_ptr, caop->src, caop->len, caop->dst, kcaop->dst_len, + kcaop->task, kcaop->mm, &src_sg, &dst_sg); + if (unlikely(ret)) { + derr(1, "get_userbuf(): Error getting user pages."); + goto free_auth_buf; + } + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 2, 0)) + if (caop->auth_src && caop->auth_len > 0) { + if (unlikely(copy_from_user(auth_buf, caop->auth_src, caop->auth_len))) { + derr(1, "unable to copy auth data from userspace."); + ret = -EFAULT; + goto free_pages; + } + + sg_init_one(&tmp, auth_buf, caop->auth_len); + auth_sg = &tmp; + } else { + auth_sg = NULL; + } + + ret = auth_n_crypt(ses_ptr, kcaop, auth_sg, caop->auth_len, + src_sg, dst_sg, caop->len); +#else + if (caop->auth_src && caop->auth_len > 0) { + if (unlikely(copy_from_user(auth_buf, caop->auth_src, caop->auth_len))) { + derr(1, "unable to copy auth data from userspace."); + ret = -EFAULT; + goto free_pages; + } + + sg_init_table(auth1, 2); + sg_set_buf(auth1, auth_buf, caop->auth_len); + sg_chain(auth1, 2, src_sg); + + if (src_sg == dst_sg) { + src_sg = auth1; + dst_sg = auth1; + } else { + sg_init_table(auth2, 2); + sg_set_buf(auth2, auth_buf, caop->auth_len); + sg_chain(auth2, 2, dst_sg); + src_sg = auth1; + dst_sg = auth2; + } + } + + ret = auth_n_crypt(ses_ptr, kcaop, NULL, caop->auth_len, + src_sg, dst_sg, caop->len); +#endif + +free_pages: + release_user_pages(ses_ptr); + +free_auth_buf: + free_page((unsigned long)auth_buf); + + return ret; +} + +static int +__crypto_auth_run_zc(struct csession *ses_ptr, struct kernel_crypt_auth_op *kcaop) +{ + struct crypt_auth_op *caop = &kcaop->caop; + int ret; + + if (caop->flags & COP_FLAG_AEAD_SRTP_TYPE) { + ret = crypto_auth_zc_srtp(ses_ptr, kcaop); + } else if (caop->flags & COP_FLAG_AEAD_TLS_TYPE && + ses_ptr->cdata.aead == 0) { + ret = crypto_auth_zc_tls(ses_ptr, kcaop); + } else if (ses_ptr->cdata.aead) { + ret = crypto_auth_zc_aead(ses_ptr, kcaop); + } else { + ret = -EINVAL; + } + + return ret; +} + + +int crypto_auth_run(struct fcrypt *fcr, struct kernel_crypt_auth_op *kcaop) +{ + struct csession *ses_ptr; + struct crypt_auth_op *caop = &kcaop->caop; + int ret; + + if (unlikely(caop->op != COP_ENCRYPT && caop->op != COP_DECRYPT)) { + ddebug(1, "invalid operation op=%u", caop->op); + return -EINVAL; + } + + /* this also enters ses_ptr->sem */ + ses_ptr = crypto_get_session_by_sid(fcr, caop->ses); + if (unlikely(!ses_ptr)) { + derr(1, "invalid session ID=0x%08X", caop->ses); + return -EINVAL; + } + + if (unlikely(ses_ptr->cdata.init == 0)) { + derr(1, "cipher context not initialized"); + ret = -EINVAL; + goto out_unlock; + } + + /* If we have a hash/mac handle reset its state */ + if (ses_ptr->hdata.init != 0) { + ret = cryptodev_hash_reset(&ses_ptr->hdata); + if (unlikely(ret)) { + derr(1, "error in cryptodev_hash_reset()"); + goto out_unlock; + } + } + + cryptodev_cipher_set_iv(&ses_ptr->cdata, kcaop->iv, + min(ses_ptr->cdata.ivsize, kcaop->ivlen)); + + ret = __crypto_auth_run_zc(ses_ptr, kcaop); + if (unlikely(ret)) { + derr(1, "error in __crypto_auth_run_zc()"); + goto out_unlock; + } + + ret = 0; + + cryptodev_cipher_get_iv(&ses_ptr->cdata, kcaop->iv, + min(ses_ptr->cdata.ivsize, kcaop->ivlen)); + +out_unlock: + crypto_put_session(ses_ptr); + return ret; +} diff --git a/drivers/cryptodev-linux-master/cipherapi.h b/drivers/cryptodev-linux-master/cipherapi.h new file mode 100644 index 00000000..b6ed6c27 --- /dev/null +++ b/drivers/cryptodev-linux-master/cipherapi.h @@ -0,0 +1,56 @@ +#ifndef CIPHERAPI_H +# define CIPHERAPI_H + +#include + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 8, 0)) +# include + +typedef struct crypto_ablkcipher cryptodev_crypto_blkcipher_t; +typedef struct ablkcipher_request cryptodev_blkcipher_request_t; + +# define cryptodev_crypto_alloc_blkcipher crypto_alloc_ablkcipher +# define cryptodev_crypto_blkcipher_blocksize crypto_ablkcipher_blocksize +# define cryptodev_crypto_blkcipher_ivsize crypto_ablkcipher_ivsize +# define cryptodev_crypto_blkcipher_alignmask crypto_ablkcipher_alignmask +# define cryptodev_crypto_blkcipher_setkey crypto_ablkcipher_setkey + +static inline void cryptodev_crypto_free_blkcipher(cryptodev_crypto_blkcipher_t *c) { + if (c) + crypto_free_ablkcipher(c); +} + +# define cryptodev_blkcipher_request_alloc ablkcipher_request_alloc +# define cryptodev_blkcipher_request_set_callback ablkcipher_request_set_callback + +static inline void cryptodev_blkcipher_request_free(cryptodev_blkcipher_request_t *r) { + if (r) + ablkcipher_request_free(r); +} + +# define cryptodev_blkcipher_request_set_crypt ablkcipher_request_set_crypt +# define cryptodev_crypto_blkcipher_encrypt crypto_ablkcipher_encrypt +# define cryptodev_crypto_blkcipher_decrypt crypto_ablkcipher_decrypt +# define cryptodev_crypto_blkcipher_tfm crypto_ablkcipher_tfm +#else +#include + +typedef struct crypto_skcipher cryptodev_crypto_blkcipher_t; +typedef struct skcipher_request cryptodev_blkcipher_request_t; + +# define cryptodev_crypto_alloc_blkcipher crypto_alloc_skcipher +# define cryptodev_crypto_blkcipher_blocksize crypto_skcipher_blocksize +# define cryptodev_crypto_blkcipher_ivsize crypto_skcipher_ivsize +# define cryptodev_crypto_blkcipher_alignmask crypto_skcipher_alignmask +# define cryptodev_crypto_blkcipher_setkey crypto_skcipher_setkey +# define cryptodev_crypto_free_blkcipher crypto_free_skcipher +# define cryptodev_blkcipher_request_alloc skcipher_request_alloc +# define cryptodev_blkcipher_request_set_callback skcipher_request_set_callback +# define cryptodev_blkcipher_request_free skcipher_request_free +# define cryptodev_blkcipher_request_set_crypt skcipher_request_set_crypt +# define cryptodev_crypto_blkcipher_encrypt crypto_skcipher_encrypt +# define cryptodev_crypto_blkcipher_decrypt crypto_skcipher_decrypt +# define cryptodev_crypto_blkcipher_tfm crypto_skcipher_tfm +#endif + +#endif diff --git a/drivers/cryptodev-linux-master/cryptlib.c b/drivers/cryptodev-linux-master/cryptlib.c new file mode 100644 index 00000000..e2a4198a --- /dev/null +++ b/drivers/cryptodev-linux-master/cryptlib.c @@ -0,0 +1,492 @@ +/* + * Driver for /dev/crypto device (aka CryptoDev) + * + * Copyright (c) 2010,2011 Nikos Mavrogiannopoulos + * Portions Copyright (c) 2010 Michael Weiser + * Portions Copyright (c) 2010 Phil Sutter + * + * This file is part of linux cryptodev. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cryptodev_int.h" +#include "cipherapi.h" + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) +extern const struct crypto_type crypto_givcipher_type; +#endif + +static void cryptodev_complete(struct crypto_async_request *req, int err) +{ + struct cryptodev_result *res = req->data; + + if (err == -EINPROGRESS) + return; + + res->err = err; + complete(&res->completion); +} + +int cryptodev_get_cipher_keylen(unsigned int *keylen, struct session_op *sop, + int aead) +{ + /* + * For blockciphers (AES-CBC) or non-composite aead ciphers (like AES-GCM), + * the key length is simply the cipher keylen obtained from userspace. If + * the cipher is composite aead, the keylen is the sum of cipher keylen, + * hmac keylen and a key header length. This key format is the one used in + * Linux kernel for composite aead ciphers (crypto/authenc.c) + */ + unsigned int klen = sop->keylen; + + if (unlikely(sop->keylen > CRYPTO_CIPHER_MAX_KEY_LEN)) + return -EINVAL; + + if (aead && sop->mackeylen) { + if (unlikely(sop->mackeylen > CRYPTO_HMAC_MAX_KEY_LEN)) + return -EINVAL; + klen += sop->mackeylen; + klen += RTA_SPACE(sizeof(struct crypto_authenc_key_param)); + } + + *keylen = klen; + return 0; +} + +int cryptodev_get_cipher_key(uint8_t *key, struct session_op *sop, int aead) +{ + /* + * Get cipher key from user-space. For blockciphers just copy it from + * user-space. For composite aead ciphers combine it with the hmac key in + * the format used by Linux kernel in crypto/authenc.c: + * + * [[AUTHENC_KEY_HEADER + CIPHER_KEYLEN] [AUTHENTICATION KEY] [CIPHER KEY]] + */ + struct crypto_authenc_key_param *param; + struct rtattr *rta; + int ret = 0; + + if (aead && sop->mackeylen) { + /* + * Composite aead ciphers. The first four bytes are the header type and + * header length for aead keys + */ + rta = (void *)key; + rta->rta_type = CRYPTO_AUTHENC_KEYA_PARAM; + rta->rta_len = RTA_LENGTH(sizeof(*param)); + + /* + * The next four bytes hold the length of the encryption key + */ + param = RTA_DATA(rta); + param->enckeylen = cpu_to_be32(sop->keylen); + + /* Advance key pointer eight bytes and copy the hmac key */ + key += RTA_SPACE(sizeof(*param)); + if (unlikely(copy_from_user(key, sop->mackey, sop->mackeylen))) { + ret = -EFAULT; + goto error; + } + /* Advance key pointer past the hmac key */ + key += sop->mackeylen; + } + /* now copy the blockcipher key */ + if (unlikely(copy_from_user(key, sop->key, sop->keylen))) + ret = -EFAULT; + +error: + return ret; +} + +/* Was correct key length supplied? */ +static int check_key_size(size_t keylen, const char *alg_name, + unsigned int min_keysize, unsigned int max_keysize) +{ + if (max_keysize > 0 && unlikely((keylen < min_keysize) || + (keylen > max_keysize))) { + ddebug(1, "Wrong keylen '%zu' for algorithm '%s'. Use %u to %u.", + keylen, alg_name, min_keysize, max_keysize); + return -EINVAL; + } + + return 0; +} + +int cryptodev_cipher_init(struct cipher_data *out, const char *alg_name, + uint8_t *keyp, size_t keylen, int stream, int aead) +{ + int ret; + + if (aead == 0) { + unsigned int min_keysize, max_keysize; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0)) + struct crypto_tfm *tfm; +#else + struct ablkcipher_alg *alg; +#endif + + out->async.s = cryptodev_crypto_alloc_blkcipher(alg_name, 0, 0); + if (unlikely(IS_ERR(out->async.s))) { + ddebug(1, "Failed to load cipher %s", alg_name); + return -EINVAL; + } + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0)) + tfm = crypto_skcipher_tfm(out->async.s); +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(5, 4, 0)) + if ((tfm->__crt_alg->cra_type == &crypto_ablkcipher_type) +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0)) + || (tfm->__crt_alg->cra_type == &crypto_givcipher_type) +#endif + ) { + struct ablkcipher_alg *alg; + + alg = &tfm->__crt_alg->cra_ablkcipher; + min_keysize = alg->min_keysize; + max_keysize = alg->max_keysize; + } else +#endif + { + struct skcipher_alg *alg; + + alg = crypto_skcipher_alg(out->async.s); + min_keysize = alg->min_keysize; + max_keysize = alg->max_keysize; + } +#else + alg = crypto_ablkcipher_alg(out->async.s); + min_keysize = alg->min_keysize; + max_keysize = alg->max_keysize; +#endif + ret = check_key_size(keylen, alg_name, min_keysize, + max_keysize); + if (ret) + goto error; + + out->blocksize = cryptodev_crypto_blkcipher_blocksize(out->async.s); + out->ivsize = cryptodev_crypto_blkcipher_ivsize(out->async.s); + out->alignmask = cryptodev_crypto_blkcipher_alignmask(out->async.s); + + ret = cryptodev_crypto_blkcipher_setkey(out->async.s, keyp, keylen); + } else { + out->async.as = crypto_alloc_aead(alg_name, 0, 0); + if (unlikely(IS_ERR(out->async.as))) { + ddebug(1, "Failed to load cipher %s", alg_name); + return -EINVAL; + } + + out->blocksize = crypto_aead_blocksize(out->async.as); + out->ivsize = crypto_aead_ivsize(out->async.as); + out->alignmask = crypto_aead_alignmask(out->async.as); + + ret = crypto_aead_setkey(out->async.as, keyp, keylen); + } + + if (unlikely(ret)) { + ddebug(1, "Setting key failed for %s-%zu.", alg_name, keylen*8); + ret = -EINVAL; + goto error; + } + + out->stream = stream; + out->aead = aead; + + init_completion(&out->async.result.completion); + + if (aead == 0) { + out->async.request = cryptodev_blkcipher_request_alloc(out->async.s, GFP_KERNEL); + if (unlikely(!out->async.request)) { + derr(1, "error allocating async crypto request"); + ret = -ENOMEM; + goto error; + } + + cryptodev_blkcipher_request_set_callback(out->async.request, + CRYPTO_TFM_REQ_MAY_BACKLOG, + cryptodev_complete, &out->async.result); + } else { + out->async.arequest = aead_request_alloc(out->async.as, GFP_KERNEL); + if (unlikely(!out->async.arequest)) { + derr(1, "error allocating async crypto request"); + ret = -ENOMEM; + goto error; + } + + aead_request_set_callback(out->async.arequest, + CRYPTO_TFM_REQ_MAY_BACKLOG, + cryptodev_complete, &out->async.result); + } + + out->init = 1; + return 0; +error: + if (aead == 0) { + cryptodev_blkcipher_request_free(out->async.request); + cryptodev_crypto_free_blkcipher(out->async.s); + } else { + if (out->async.arequest) + aead_request_free(out->async.arequest); + if (out->async.as) + crypto_free_aead(out->async.as); + } + + return ret; +} + +void cryptodev_cipher_deinit(struct cipher_data *cdata) +{ + if (cdata->init) { + if (cdata->aead == 0) { + cryptodev_blkcipher_request_free(cdata->async.request); + cryptodev_crypto_free_blkcipher(cdata->async.s); + } else { + if (cdata->async.arequest) + aead_request_free(cdata->async.arequest); + if (cdata->async.as) + crypto_free_aead(cdata->async.as); + } + + cdata->init = 0; + } +} + +static inline int waitfor(struct cryptodev_result *cr, ssize_t ret) +{ + switch (ret) { + case 0: + break; + case -EINPROGRESS: + case -EBUSY: + wait_for_completion(&cr->completion); + /* At this point we known for sure the request has finished, + * because wait_for_completion above was not interruptible. + * This is important because otherwise hardware or driver + * might try to access memory which will be freed or reused for + * another request. */ + + if (unlikely(cr->err)) { + derr(0, "error from async request: %d", cr->err); + return cr->err; + } + + break; + default: + return ret; + } + + return 0; +} + +ssize_t cryptodev_cipher_encrypt(struct cipher_data *cdata, + const struct scatterlist *src, struct scatterlist *dst, + size_t len) +{ + int ret; + + reinit_completion(&cdata->async.result.completion); + + if (cdata->aead == 0) { + cryptodev_blkcipher_request_set_crypt(cdata->async.request, + (struct scatterlist *)src, dst, + len, cdata->async.iv); + ret = cryptodev_crypto_blkcipher_encrypt(cdata->async.request); + } else { + aead_request_set_crypt(cdata->async.arequest, + (struct scatterlist *)src, dst, + len, cdata->async.iv); + ret = crypto_aead_encrypt(cdata->async.arequest); + } + + return waitfor(&cdata->async.result, ret); +} + +ssize_t cryptodev_cipher_decrypt(struct cipher_data *cdata, + const struct scatterlist *src, struct scatterlist *dst, + size_t len) +{ + int ret; + + reinit_completion(&cdata->async.result.completion); + if (cdata->aead == 0) { + cryptodev_blkcipher_request_set_crypt(cdata->async.request, + (struct scatterlist *)src, dst, + len, cdata->async.iv); + ret = cryptodev_crypto_blkcipher_decrypt(cdata->async.request); + } else { + aead_request_set_crypt(cdata->async.arequest, + (struct scatterlist *)src, dst, + len, cdata->async.iv); + ret = crypto_aead_decrypt(cdata->async.arequest); + } + + return waitfor(&cdata->async.result, ret); +} + +/* Hash functions */ + +int cryptodev_hash_init(struct hash_data *hdata, const char *alg_name, + int hmac_mode, void *mackey, size_t mackeylen) +{ + int ret; + + hdata->async.s = crypto_alloc_ahash(alg_name, 0, 0); + if (unlikely(IS_ERR(hdata->async.s))) { + ddebug(1, "Failed to load transform for %s", alg_name); + return -EINVAL; + } + + /* Copy the key from user and set to TFM. */ + if (hmac_mode != 0) { + ret = crypto_ahash_setkey(hdata->async.s, mackey, mackeylen); + if (unlikely(ret)) { + ddebug(1, "Setting hmac key failed for %s-%zu.", + alg_name, mackeylen*8); + ret = -EINVAL; + goto error; + } + } + + hdata->digestsize = crypto_ahash_digestsize(hdata->async.s); + hdata->alignmask = crypto_ahash_alignmask(hdata->async.s); + + init_completion(&hdata->async.result.completion); + + hdata->async.request = ahash_request_alloc(hdata->async.s, GFP_KERNEL); + if (unlikely(!hdata->async.request)) { + derr(0, "error allocating async crypto request"); + ret = -ENOMEM; + goto error; + } + + ahash_request_set_callback(hdata->async.request, + CRYPTO_TFM_REQ_MAY_BACKLOG, + cryptodev_complete, &hdata->async.result); + hdata->init = 1; + return 0; + +error: + crypto_free_ahash(hdata->async.s); + return ret; +} + +void cryptodev_hash_deinit(struct hash_data *hdata) +{ + if (hdata->init) { + ahash_request_free(hdata->async.request); + crypto_free_ahash(hdata->async.s); + hdata->init = 0; + } +} + +int cryptodev_hash_reset(struct hash_data *hdata) +{ + int ret; + + ret = crypto_ahash_init(hdata->async.request); + if (unlikely(ret)) { + derr(0, "error in crypto_hash_init()"); + return ret; + } + + return 0; + +} + +ssize_t cryptodev_hash_update(struct hash_data *hdata, + struct scatterlist *sg, size_t len) +{ + int ret; + + reinit_completion(&hdata->async.result.completion); + ahash_request_set_crypt(hdata->async.request, sg, NULL, len); + + ret = crypto_ahash_update(hdata->async.request); + + return waitfor(&hdata->async.result, ret); +} + +int cryptodev_hash_final(struct hash_data *hdata, void *output) +{ + int ret; + + reinit_completion(&hdata->async.result.completion); + ahash_request_set_crypt(hdata->async.request, NULL, output, 0); + + ret = crypto_ahash_final(hdata->async.request); + + return waitfor(&hdata->async.result, ret); +} + +#ifdef CIOCCPHASH +/* import the current hash state of src to dst */ +int cryptodev_hash_copy(struct hash_data *dst, struct hash_data *src) +{ + int ret, statesize; + void *statedata = NULL; + struct crypto_tfm *tfm; + + if (unlikely(src == NULL || dst == NULL)) { + return -EINVAL; + } + + reinit_completion(&src->async.result.completion); + + statesize = crypto_ahash_statesize(src->async.s); + if (unlikely(statesize <= 0)) { + return -EINVAL; + } + + statedata = kzalloc(statesize, GFP_KERNEL); + if (unlikely(statedata == NULL)) { + return -ENOMEM; + } + + ret = crypto_ahash_export(src->async.request, statedata); + if (unlikely(ret < 0)) { + if (unlikely(ret == -ENOSYS)) { + tfm = crypto_ahash_tfm(src->async.s); + derr(0, "cryptodev_hash_copy: crypto_ahash_export not implemented for " + "alg='%s', driver='%s'", crypto_tfm_alg_name(tfm), + crypto_tfm_alg_driver_name(tfm)); + } + goto out; + } + + ret = crypto_ahash_import(dst->async.request, statedata); + if (unlikely(ret == -ENOSYS)) { + tfm = crypto_ahash_tfm(dst->async.s); + derr(0, "cryptodev_hash_copy: crypto_ahash_import not implemented for " + "alg='%s', driver='%s'", crypto_tfm_alg_name(tfm), + crypto_tfm_alg_driver_name(tfm)); + } +out: + kfree(statedata); + return ret; +} +#endif /* CIOCCPHASH */ diff --git a/drivers/cryptodev-linux-master/cryptlib.h b/drivers/cryptodev-linux-master/cryptlib.h new file mode 100644 index 00000000..9330ff57 --- /dev/null +++ b/drivers/cryptodev-linux-master/cryptlib.h @@ -0,0 +1,109 @@ +#ifndef CRYPTLIB_H +# define CRYPTLIB_H + +#include + +struct cryptodev_result { + struct completion completion; + int err; +}; + +#include "cipherapi.h" + +struct cipher_data { + int init; /* 0 uninitialized */ + int blocksize; + int aead; + int stream; + int ivsize; + int alignmask; + struct { + /* block ciphers */ + cryptodev_crypto_blkcipher_t *s; + cryptodev_blkcipher_request_t *request; + + /* AEAD ciphers */ + struct crypto_aead *as; + struct aead_request *arequest; + + struct cryptodev_result result; + uint8_t iv[EALG_MAX_BLOCK_LEN]; + } async; +}; + +int cryptodev_cipher_init(struct cipher_data *out, const char *alg_name, + uint8_t *key, size_t keylen, int stream, int aead); +void cryptodev_cipher_deinit(struct cipher_data *cdata); +int cryptodev_get_cipher_key(uint8_t *key, struct session_op *sop, int aead); +int cryptodev_get_cipher_keylen(unsigned int *keylen, struct session_op *sop, + int aead); +ssize_t cryptodev_cipher_decrypt(struct cipher_data *cdata, + const struct scatterlist *sg1, + struct scatterlist *sg2, size_t len); +ssize_t cryptodev_cipher_encrypt(struct cipher_data *cdata, + const struct scatterlist *sg1, + struct scatterlist *sg2, size_t len); + +/* AEAD */ +static inline void cryptodev_cipher_auth(struct cipher_data *cdata, + struct scatterlist *sg1, size_t len) +{ + /* for some reason we _have_ to call that even for zero length sgs */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 3, 0)) + aead_request_set_assoc(cdata->async.arequest, len ? sg1 : NULL, len); +#else + aead_request_set_ad(cdata->async.arequest, len); +#endif +} + +static inline void cryptodev_cipher_set_tag_size(struct cipher_data *cdata, int size) +{ + if (likely(cdata->aead != 0)) + crypto_aead_setauthsize(cdata->async.as, size); +} + +static inline int cryptodev_cipher_get_tag_size(struct cipher_data *cdata) +{ + if (likely(cdata->init && cdata->aead != 0)) + return crypto_aead_authsize(cdata->async.as); + else + return 0; +} + +static inline void cryptodev_cipher_set_iv(struct cipher_data *cdata, + void *iv, size_t iv_size) +{ + memcpy(cdata->async.iv, iv, min(iv_size, sizeof(cdata->async.iv))); +} + +static inline void cryptodev_cipher_get_iv(struct cipher_data *cdata, + void *iv, size_t iv_size) +{ + memcpy(iv, cdata->async.iv, min(iv_size, sizeof(cdata->async.iv))); +} + +/* Hash */ +struct hash_data { + int init; /* 0 uninitialized */ + int digestsize; + int alignmask; + struct { + struct crypto_ahash *s; + struct cryptodev_result result; + struct ahash_request *request; + } async; +}; + +int cryptodev_hash_final(struct hash_data *hdata, void *output); +ssize_t cryptodev_hash_update(struct hash_data *hdata, + struct scatterlist *sg, size_t len); +int cryptodev_hash_reset(struct hash_data *hdata); +void cryptodev_hash_deinit(struct hash_data *hdata); +int cryptodev_hash_init(struct hash_data *hdata, const char *alg_name, + int hmac_mode, void *mackey, size_t mackeylen); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) +int cryptodev_hash_copy(struct hash_data *dst, struct hash_data *src); +#endif + + +#endif diff --git a/drivers/cryptodev-linux-master/crypto/cryptodev.h b/drivers/cryptodev-linux-master/crypto/cryptodev.h new file mode 100644 index 00000000..1def37a0 --- /dev/null +++ b/drivers/cryptodev-linux-master/crypto/cryptodev.h @@ -0,0 +1,319 @@ +/* This is a source compatible implementation with the original API of + * cryptodev by Angelos D. Keromytis, found at openbsd cryptodev.h. + * Placed under public domain */ + +#ifndef L_CRYPTODEV_H +#define L_CRYPTODEV_H + +#include +#include +#ifndef __KERNEL__ +#define __user +#endif + +/* API extensions for linux */ +#define CRYPTO_HMAC_MAX_KEY_LEN 512 +#define CRYPTO_CIPHER_MAX_KEY_LEN 64 + +/* All the supported algorithms + */ +enum cryptodev_crypto_op_t { + CRYPTO_DES_CBC = 1, + CRYPTO_3DES_CBC = 2, + CRYPTO_BLF_CBC = 3, + CRYPTO_CAST_CBC = 4, + CRYPTO_SKIPJACK_CBC = 5, + CRYPTO_MD5_HMAC = 6, + CRYPTO_SHA1_HMAC = 7, + CRYPTO_RIPEMD160_HMAC = 8, + CRYPTO_MD5_KPDK = 9, + CRYPTO_SHA1_KPDK = 10, + CRYPTO_RIJNDAEL128_CBC = 11, + CRYPTO_AES_CBC = CRYPTO_RIJNDAEL128_CBC, + CRYPTO_ARC4 = 12, + CRYPTO_MD5 = 13, + CRYPTO_SHA1 = 14, + CRYPTO_DEFLATE_COMP = 15, + CRYPTO_NULL = 16, + CRYPTO_LZS_COMP = 17, + CRYPTO_SHA2_256_HMAC = 18, + CRYPTO_SHA2_384_HMAC = 19, + CRYPTO_SHA2_512_HMAC = 20, + CRYPTO_AES_CTR = 21, + CRYPTO_AES_XTS = 22, + CRYPTO_AES_ECB = 23, + CRYPTO_AES_GCM = 50, + + CRYPTO_CAMELLIA_CBC = 101, + CRYPTO_RIPEMD160, + CRYPTO_SHA2_224, + CRYPTO_SHA2_256, + CRYPTO_SHA2_384, + CRYPTO_SHA2_512, + CRYPTO_SHA2_224_HMAC, + CRYPTO_TLS11_AES_CBC_HMAC_SHA1, + CRYPTO_TLS12_AES_CBC_HMAC_SHA256, + CRYPTO_ALGORITHM_ALL, /* Keep updated - see below */ +}; + +#define CRYPTO_ALGORITHM_MAX (CRYPTO_ALGORITHM_ALL - 1) + +/* Values for ciphers */ +#define DES_BLOCK_LEN 8 +#define DES3_BLOCK_LEN 8 +#define RIJNDAEL128_BLOCK_LEN 16 +#define AES_BLOCK_LEN RIJNDAEL128_BLOCK_LEN +#define CAMELLIA_BLOCK_LEN 16 +#define BLOWFISH_BLOCK_LEN 8 +#define SKIPJACK_BLOCK_LEN 8 +#define CAST128_BLOCK_LEN 8 + +/* the maximum of the above */ +#define EALG_MAX_BLOCK_LEN 16 + +/* Values for hashes/MAC */ +#define AALG_MAX_RESULT_LEN 64 + +/* maximum length of verbose alg names (depends on CRYPTO_MAX_ALG_NAME) */ +#define CRYPTODEV_MAX_ALG_NAME 64 + +#define HASH_MAX_LEN 64 + +/* input of CIOCGSESSION */ +struct session_op { + /* Specify either cipher or mac + */ + __u32 cipher; /* cryptodev_crypto_op_t */ + __u32 mac; /* cryptodev_crypto_op_t */ + + __u32 keylen; + __u8 __user *key; + __u32 mackeylen; + __u8 __user *mackey; + + __u32 ses; /* session identifier */ +}; + +struct session_info_op { + __u32 ses; /* session identifier */ + + /* verbose names for the requested ciphers */ + struct alg_info { + char cra_name[CRYPTODEV_MAX_ALG_NAME]; + char cra_driver_name[CRYPTODEV_MAX_ALG_NAME]; + } cipher_info, hash_info; + + __u16 alignmask; /* alignment constraints */ + __u32 flags; /* SIOP_FLAGS_* */ +}; + +/* If this flag is set then this algorithm uses + * a driver only available in kernel (software drivers, + * or drivers based on instruction sets do not set this flag). + * + * If multiple algorithms are involved (as in AEAD case), then + * if one of them is kernel-driver-only this flag will be set. + */ +#define SIOP_FLAG_KERNEL_DRIVER_ONLY 1 + +#define COP_ENCRYPT 0 +#define COP_DECRYPT 1 + +/* input of CIOCCRYPT */ +struct crypt_op { + __u32 ses; /* session identifier */ + __u16 op; /* COP_ENCRYPT or COP_DECRYPT */ + __u16 flags; /* see COP_FLAG_* */ + __u32 len; /* length of source data */ + __u8 __user *src; /* source data */ + __u8 __user *dst; /* pointer to output data */ + /* pointer to output data for hash/MAC operations */ + __u8 __user *mac; + /* initialization vector for encryption operations */ + __u8 __user *iv; +}; + +/* input of CIOCAUTHCRYPT */ +struct crypt_auth_op { + __u32 ses; /* session identifier */ + __u16 op; /* COP_ENCRYPT or COP_DECRYPT */ + __u16 flags; /* see COP_FLAG_AEAD_* */ + __u32 len; /* length of source data */ + __u32 auth_len; /* length of auth data */ + __u8 __user *auth_src; /* authenticated-only data */ + + /* The current implementation is more efficient if data are + * encrypted in-place (src==dst). */ + __u8 __user *src; /* data to be encrypted and authenticated */ + __u8 __user *dst; /* pointer to output data. Must have + * space for tag. For TLS this should be at least + * len + tag_size + block_size for padding */ + + __u8 __user *tag; /* where the tag will be copied to. TLS mode + * doesn't use that as tag is copied to dst. + * SRTP mode copies tag there. */ + __u32 tag_len; /* the length of the tag. Use zero for digest size or max tag. */ + + /* initialization vector for encryption operations */ + __u8 __user *iv; + __u32 iv_len; +}; + +/* In plain AEAD mode the following are required: + * flags : 0 + * iv : the initialization vector (12 bytes) + * auth_len: the length of the data to be authenticated + * auth_src: the data to be authenticated + * len : length of data to be encrypted + * src : the data to be encrypted + * dst : space to hold encrypted data. It must have + * at least a size of len + tag_size. + * tag_size: the size of the desired authentication tag or zero to use + * the maximum tag output. + * + * Note tag isn't being used because the Linux AEAD interface + * copies the tag just after data. + */ + +/* In TLS mode (used for CBC ciphers that required padding) + * the following are required: + * flags : COP_FLAG_AEAD_TLS_TYPE + * iv : the initialization vector + * auth_len: the length of the data to be authenticated only + * len : length of data to be encrypted + * auth_src: the data to be authenticated + * src : the data to be encrypted + * dst : space to hold encrypted data (preferably in-place). It must have + * at least a size of len + tag_size + blocksize. + * tag_size: the size of the desired authentication tag or zero to use + * the default mac output. + * + * Note that the padding used is the minimum padding. + */ + +/* In SRTP mode the following are required: + * flags : COP_FLAG_AEAD_SRTP_TYPE + * iv : the initialization vector + * auth_len: the length of the data to be authenticated. This must + * include the SRTP header + SRTP payload (data to be encrypted) + rest + * + * len : length of data to be encrypted + * auth_src: pointer the data to be authenticated. Should point at the same buffer as src. + * src : pointer to the data to be encrypted. + * dst : This is mandatory to be the same as src (in-place only). + * tag_size: the size of the desired authentication tag or zero to use + * the default mac output. + * tag : Pointer to an address where the authentication tag will be copied. + */ + + +/* struct crypt_op flags */ + +#define COP_FLAG_NONE (0 << 0) /* totally no flag */ +#define COP_FLAG_UPDATE (1 << 0) /* multi-update hash mode */ +#define COP_FLAG_FINAL (1 << 1) /* multi-update final hash mode */ +#define COP_FLAG_WRITE_IV (1 << 2) /* update the IV during operation */ +#define COP_FLAG_NO_ZC (1 << 3) /* do not zero-copy */ +#define COP_FLAG_AEAD_TLS_TYPE (1 << 4) /* authenticate and encrypt using the + * TLS protocol rules */ +#define COP_FLAG_AEAD_SRTP_TYPE (1 << 5) /* authenticate and encrypt using the + * SRTP protocol rules */ +#define COP_FLAG_RESET (1 << 6) /* multi-update reset the state. + * should be used in combination + * with COP_FLAG_UPDATE */ + + +#define COP_FLAG_ZC (1 << 10) + +/* Stuff for bignum arithmetic and public key + * cryptography - not supported yet by linux + * cryptodev. + */ + +#define CRYPTO_ALG_FLAG_SUPPORTED 1 +#define CRYPTO_ALG_FLAG_RNG_ENABLE 2 +#define CRYPTO_ALG_FLAG_DSA_SHA 4 + +struct crparam { + __u8 *crp_p; + __u32 crp_nbits; +}; + +#define CRK_MAXPARAM 8 + +/* input of CIOCKEY */ +struct crypt_kop { + __u32 crk_op; /* cryptodev_crk_op_t */ + __u32 crk_status; + __u16 crk_iparams; + __u16 crk_oparams; + __u32 crk_pad1; + struct crparam crk_param[CRK_MAXPARAM]; +}; + +enum cryptodev_crk_op_t { + CRK_MOD_EXP = 0, + CRK_MOD_EXP_CRT = 1, + CRK_DSA_SIGN = 2, + CRK_DSA_VERIFY = 3, + CRK_DH_COMPUTE_KEY = 4, + CRK_ALGORITHM_ALL +}; + +/* input of CIOCCPHASH + * dst_ses : destination session identifier + * src_ses : source session identifier + * dst_ses must have been created with CIOGSESSION first + */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) +struct cphash_op { + __u32 dst_ses; + __u32 src_ses; +}; +#endif + +#define CRK_ALGORITHM_MAX (CRK_ALGORITHM_ALL-1) + +/* features to be queried with CIOCASYMFEAT ioctl + */ +#define CRF_MOD_EXP (1 << CRK_MOD_EXP) +#define CRF_MOD_EXP_CRT (1 << CRK_MOD_EXP_CRT) +#define CRF_DSA_SIGN (1 << CRK_DSA_SIGN) +#define CRF_DSA_VERIFY (1 << CRK_DSA_VERIFY) +#define CRF_DH_COMPUTE_KEY (1 << CRK_DH_COMPUTE_KEY) + + +/* ioctl's. Compatible with old linux cryptodev.h + */ +#define CRIOGET _IOWR('c', 101, __u32) +#define CIOCGSESSION _IOWR('c', 102, struct session_op) +#define CIOCFSESSION _IOW('c', 103, __u32) +#define CIOCCRYPT _IOWR('c', 104, struct crypt_op) +#define CIOCKEY _IOWR('c', 105, struct crypt_kop) +#define CIOCASYMFEAT _IOR('c', 106, __u32) +#define CIOCGSESSINFO _IOWR('c', 107, struct session_info_op) + +/* to indicate that CRIOGET is not required in linux + */ +#define CRIOGET_NOT_NEEDED 1 + +/* additional ioctls for AEAD */ +#define CIOCAUTHCRYPT _IOWR('c', 109, struct crypt_auth_op) + +/* additional ioctls for asynchronous operation. + * These are conditionally enabled since version 1.6. + */ +#define CIOCASYNCCRYPT _IOW('c', 110, struct crypt_op) +#define CIOCASYNCFETCH _IOR('c', 111, struct crypt_op) + +/* additional ioctl for copying of hash/mac session state data + * between sessions. + * The cphash_op parameter should contain the session id of + * the source and destination sessions. Both sessions + * must have been created with CIOGSESSION. + */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) +#define CIOCCPHASH _IOW('c', 112, struct cphash_op) +#endif + +#endif /* L_CRYPTODEV_H */ diff --git a/drivers/cryptodev-linux-master/cryptodev_int.h b/drivers/cryptodev-linux-master/cryptodev_int.h new file mode 100644 index 00000000..d7660fac --- /dev/null +++ b/drivers/cryptodev-linux-master/cryptodev_int.h @@ -0,0 +1,145 @@ +/* cipher stuff */ +#ifndef CRYPTODEV_INT_H +# define CRYPTODEV_INT_H + +#include + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 13, 0)) +# define reinit_completion(x) INIT_COMPLETION(*(x)) +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PFX "cryptodev: " +#define dprintk(level, severity, format, a...) \ + do { \ + if (level <= cryptodev_verbosity) \ + printk(severity PFX "%s[%u] (%s:%u): " format "\n", \ + current->comm, current->pid, \ + __func__, __LINE__, \ + ##a); \ + } while (0) +#define derr(level, format, a...) dprintk(level, KERN_ERR, format, ##a) +#define dwarning(level, format, a...) dprintk(level, KERN_WARNING, format, ##a) +#define dinfo(level, format, a...) dprintk(level, KERN_INFO, format, ##a) +#define ddebug(level, format, a...) dprintk(level, KERN_DEBUG, format, ##a) + + +extern int cryptodev_verbosity; + +struct fcrypt { + struct list_head list; + struct mutex sem; +}; + +/* compatibility stuff */ +#ifdef CONFIG_COMPAT +#include + +/* input of CIOCGSESSION */ +struct compat_session_op { + /* Specify either cipher or mac + */ + uint32_t cipher; /* cryptodev_crypto_op_t */ + uint32_t mac; /* cryptodev_crypto_op_t */ + + uint32_t keylen; + compat_uptr_t key; /* pointer to key data */ + uint32_t mackeylen; + compat_uptr_t mackey; /* pointer to mac key data */ + + uint32_t ses; /* session identifier */ +}; + +/* input of CIOCCRYPT */ +struct compat_crypt_op { + uint32_t ses; /* session identifier */ + uint16_t op; /* COP_ENCRYPT or COP_DECRYPT */ + uint16_t flags; /* see COP_FLAG_* */ + uint32_t len; /* length of source data */ + compat_uptr_t src; /* source data */ + compat_uptr_t dst; /* pointer to output data */ + compat_uptr_t mac;/* pointer to output data for hash/MAC operations */ + compat_uptr_t iv;/* initialization vector for encryption operations */ +}; + +/* compat ioctls, defined for the above structs */ +#define COMPAT_CIOCGSESSION _IOWR('c', 102, struct compat_session_op) +#define COMPAT_CIOCCRYPT _IOWR('c', 104, struct compat_crypt_op) +#define COMPAT_CIOCASYNCCRYPT _IOW('c', 107, struct compat_crypt_op) +#define COMPAT_CIOCASYNCFETCH _IOR('c', 108, struct compat_crypt_op) + +#endif /* CONFIG_COMPAT */ + +/* kernel-internal extension to struct crypt_op */ +struct kernel_crypt_op { + struct crypt_op cop; + + int ivlen; + __u8 iv[EALG_MAX_BLOCK_LEN]; + + int digestsize; + uint8_t hash_output[AALG_MAX_RESULT_LEN]; + + struct task_struct *task; + struct mm_struct *mm; +}; + +struct kernel_crypt_auth_op { + struct crypt_auth_op caop; + + int dst_len; /* based on src_len + pad + tag */ + int ivlen; + __u8 iv[EALG_MAX_BLOCK_LEN]; + + struct task_struct *task; + struct mm_struct *mm; +}; + +/* auth */ + +int kcaop_from_user(struct kernel_crypt_auth_op *kcop, + struct fcrypt *fcr, void __user *arg); +int kcaop_to_user(struct kernel_crypt_auth_op *kcaop, + struct fcrypt *fcr, void __user *arg); +int crypto_auth_run(struct fcrypt *fcr, struct kernel_crypt_auth_op *kcaop); +int crypto_run(struct fcrypt *fcr, struct kernel_crypt_op *kcop); + +#include + +/* other internal structs */ +struct csession { + struct list_head entry; + struct mutex sem; + struct cipher_data cdata; + struct hash_data hdata; + uint32_t sid; + uint32_t alignmask; + + unsigned int array_size; + unsigned int used_pages; /* the number of pages that are used */ + /* the number of pages marked as NOT-writable; they preceed writeables */ + unsigned int readonly_pages; + struct page **pages; + struct scatterlist *sg; +}; + +struct csession *crypto_get_session_by_sid(struct fcrypt *fcr, uint32_t sid); + +static inline void crypto_put_session(struct csession *ses_ptr) +{ + mutex_unlock(&ses_ptr->sem); +} +int adjust_sg_array(struct csession *ses, int pagecount); + +#endif /* CRYPTODEV_INT_H */ diff --git a/drivers/cryptodev-linux-master/examples/aes-gcm.c b/drivers/cryptodev-linux-master/examples/aes-gcm.c new file mode 100644 index 00000000..6791f4eb --- /dev/null +++ b/drivers/cryptodev-linux-master/examples/aes-gcm.c @@ -0,0 +1,139 @@ +/* + * Demo on how to use /dev/crypto device for ciphering. + * + * Placed under public domain. + * + */ +#include +#include +#include +#include +#include +#include +#include "aes-gcm.h" + +int aes_gcm_ctx_init(struct cryptodev_ctx* ctx, int cfd, const uint8_t *key, unsigned int key_size) +{ +#ifdef CIOCGSESSINFO + struct session_info_op siop; +#endif + + memset(ctx, 0, sizeof(*ctx)); + ctx->cfd = cfd; + + ctx->sess.cipher = CRYPTO_AES_GCM; + ctx->sess.keylen = key_size; + ctx->sess.key = (void*)key; + if (ioctl(ctx->cfd, CIOCGSESSION, &ctx->sess)) { + perror("ioctl(CIOCGSESSION)"); + return -1; + } + +#ifdef CIOCGSESSINFO + siop.ses = ctx->sess.ses; + if (ioctl(ctx->cfd, CIOCGSESSINFO, &siop)) { + perror("ioctl(CIOCGSESSINFO)"); + return -1; + } + printf("Got %s with driver %s\n", + siop.cipher_info.cra_name, siop.cipher_info.cra_driver_name); + if (!(siop.flags & SIOP_FLAG_KERNEL_DRIVER_ONLY)) { + printf("Note: This is not an accelerated cipher\n"); + } + /*printf("Alignmask is %x\n", (unsigned int)siop.alignmask); */ + ctx->alignmask = siop.alignmask; +#endif + return 0; +} + +void aes_gcm_ctx_deinit(struct cryptodev_ctx* ctx) +{ + if (ioctl(ctx->cfd, CIOCFSESSION, &ctx->sess.ses)) { + perror("ioctl(CIOCFSESSION)"); + } +} + +int +aes_gcm_encrypt(struct cryptodev_ctx* ctx, const void* iv, + const void* auth, size_t auth_size, + const void* plaintext, void* ciphertext, size_t size) +{ + struct crypt_auth_op cryp; + void* p; + + /* check plaintext and ciphertext alignment */ + if (ctx->alignmask) { + p = (void*)(((unsigned long)plaintext + ctx->alignmask) & ~ctx->alignmask); + if (plaintext != p) { + fprintf(stderr, "plaintext is not aligned\n"); + return -1; + } + + p = (void*)(((unsigned long)ciphertext + ctx->alignmask) & ~ctx->alignmask); + if (ciphertext != p) { + fprintf(stderr, "ciphertext is not aligned\n"); + return -1; + } + } + + memset(&cryp, 0, sizeof(cryp)); + + /* Encrypt data.in to data.encrypted */ + cryp.ses = ctx->sess.ses; + cryp.iv = (void*)iv; + cryp.op = COP_ENCRYPT; + cryp.auth_len = auth_size; + cryp.auth_src = (void*)auth; + cryp.len = size; + cryp.src = (void*)plaintext; + cryp.dst = ciphertext; + if (ioctl(ctx->cfd, CIOCAUTHCRYPT, &cryp)) { + perror("ioctl(CIOCAUTHCRYPT)"); + return -1; + } + + return 0; +} + +int +aes_gcm_decrypt(struct cryptodev_ctx* ctx, const void* iv, + const void* auth, size_t auth_size, + const void* ciphertext, void* plaintext, size_t size) +{ + struct crypt_auth_op cryp; + void* p; + + /* check plaintext and ciphertext alignment */ + if (ctx->alignmask) { + p = (void*)(((unsigned long)plaintext + ctx->alignmask) & ~ctx->alignmask); + if (plaintext != p) { + fprintf(stderr, "plaintext is not aligned\n"); + return -1; + } + + p = (void*)(((unsigned long)ciphertext + ctx->alignmask) & ~ctx->alignmask); + if (ciphertext != p) { + fprintf(stderr, "ciphertext is not aligned\n"); + return -1; + } + } + + memset(&cryp, 0, sizeof(cryp)); + + /* Encrypt data.in to data.encrypted */ + cryp.ses = ctx->sess.ses; + cryp.iv = (void*)iv; + cryp.op = COP_DECRYPT; + cryp.auth_len = auth_size; + cryp.auth_src = (void*)auth; + cryp.len = size; + cryp.src = (void*)ciphertext; + cryp.dst = plaintext; + if (ioctl(ctx->cfd, CIOCAUTHCRYPT, &cryp)) { + perror("ioctl(CIOCAUTHCRYPT)"); + return -1; + } + + return 0; +} + diff --git a/drivers/cryptodev-linux-master/examples/aes-gcm.h b/drivers/cryptodev-linux-master/examples/aes-gcm.h new file mode 100644 index 00000000..1ddc5fe4 --- /dev/null +++ b/drivers/cryptodev-linux-master/examples/aes-gcm.h @@ -0,0 +1,28 @@ +#ifndef AES_H +# define AES_H + +#include + +struct cryptodev_ctx { + int cfd; + struct session_op sess; + uint16_t alignmask; +}; + +#define AES_BLOCK_SIZE 16 + +int aes_gcm_ctx_init(struct cryptodev_ctx* ctx, int cfd, const uint8_t *key, unsigned int key_size); +void aes_gcm_ctx_deinit(); + +/* Note that encryption assumes that ciphertext has enough size + * for the tag to be appended. In decryption the tag is assumed + * to be the last bytes of ciphertext. + */ +int aes_gcm_encrypt(struct cryptodev_ctx* ctx, const void* iv, + const void* auth, size_t auth_size, + const void* plaintext, void* ciphertext, size_t size); +int aes_gcm_decrypt(struct cryptodev_ctx* ctx, const void* iv, + const void* auth, size_t auth_size, + const void* ciphertext, void* plaintext, size_t size); + +#endif diff --git a/drivers/cryptodev-linux-master/examples/aes-sha1.c b/drivers/cryptodev-linux-master/examples/aes-sha1.c new file mode 100644 index 00000000..e93e3c44 --- /dev/null +++ b/drivers/cryptodev-linux-master/examples/aes-sha1.c @@ -0,0 +1,139 @@ +/* + * Demo on how to use /dev/crypto device for ciphering. + * + * Placed under public domain. + * + */ +#include +#include +#include +#include +#include +#include +#include "aes-sha1.h" + +/* This is the TLS version of AES-CBC with HMAC-SHA1. + */ + +int aes_sha1_ctx_init(struct cryptodev_ctx* ctx, int cfd, + const uint8_t *key, unsigned int key_size, + const uint8_t *mac_key, unsigned int mac_key_size) +{ +#ifdef CIOCGSESSINFO + struct session_info_op siop; +#endif + + memset(ctx, 0, sizeof(*ctx)); + ctx->cfd = cfd; + + ctx->sess.cipher = CRYPTO_AES_CBC; + ctx->sess.keylen = key_size; + ctx->sess.key = (void*)key; + + ctx->sess.mac = CRYPTO_SHA1_HMAC; + ctx->sess.mackeylen = mac_key_size; + ctx->sess.mackey = (void*)mac_key; + + if (ioctl(ctx->cfd, CIOCGSESSION, &ctx->sess)) { + perror("ioctl(CIOCGSESSION)"); + return -1; + } + +#ifdef CIOCGSESSINFO + siop.ses = ctx->sess.ses; + if (ioctl(ctx->cfd, CIOCGSESSINFO, &siop)) { + perror("ioctl(CIOCGSESSINFO)"); + return -1; + } + printf("Got %s with driver %s\n", + siop.cipher_info.cra_name, siop.cipher_info.cra_driver_name); + if (!(siop.flags & SIOP_FLAG_KERNEL_DRIVER_ONLY)) { + printf("Note: This is not an accelerated cipher\n"); + } + /*printf("Alignmask is %x\n", (unsigned int)siop.alignmask); */ + ctx->alignmask = siop.alignmask; +#endif + return 0; +} + +void aes_sha1_ctx_deinit(struct cryptodev_ctx* ctx) +{ + if (ioctl(ctx->cfd, CIOCFSESSION, &ctx->sess.ses)) { + perror("ioctl(CIOCFSESSION)"); + } +} + +int +aes_sha1_encrypt(struct cryptodev_ctx* ctx, const void* iv, + const void* auth, size_t auth_size, + void* plaintext, size_t size) +{ + struct crypt_auth_op cryp; + void* p; + + /* check plaintext and ciphertext alignment */ + if (ctx->alignmask) { + p = (void*)(((unsigned long)plaintext + ctx->alignmask) & ~ctx->alignmask); + if (plaintext != p) { + fprintf(stderr, "plaintext is not aligned\n"); + return -1; + } + } + + memset(&cryp, 0, sizeof(cryp)); + + /* Encrypt data.in to data.encrypted */ + cryp.ses = ctx->sess.ses; + cryp.iv = (void*)iv; + cryp.op = COP_ENCRYPT; + cryp.auth_len = auth_size; + cryp.auth_src = (void*)auth; + cryp.len = size; + cryp.src = (void*)plaintext; + cryp.dst = plaintext; + cryp.flags = COP_FLAG_AEAD_TLS_TYPE; + if (ioctl(ctx->cfd, CIOCAUTHCRYPT, &cryp)) { + perror("ioctl(CIOCAUTHCRYPT)"); + return -1; + } + + return 0; +} + +int +aes_sha1_decrypt(struct cryptodev_ctx* ctx, const void* iv, + const void* auth, size_t auth_size, + void* ciphertext, size_t size) +{ + struct crypt_auth_op cryp; + void* p; + + /* check plaintext and ciphertext alignment */ + if (ctx->alignmask) { + p = (void*)(((unsigned long)ciphertext + ctx->alignmask) & ~ctx->alignmask); + if (ciphertext != p) { + fprintf(stderr, "ciphertext is not aligned\n"); + return -1; + } + } + + memset(&cryp, 0, sizeof(cryp)); + + /* Encrypt data.in to data.encrypted */ + cryp.ses = ctx->sess.ses; + cryp.iv = (void*)iv; + cryp.op = COP_DECRYPT; + cryp.auth_len = auth_size; + cryp.auth_src = (void*)auth; + cryp.len = size; + cryp.src = (void*)ciphertext; + cryp.dst = ciphertext; + cryp.flags = COP_FLAG_AEAD_TLS_TYPE; + if (ioctl(ctx->cfd, CIOCAUTHCRYPT, &cryp)) { + perror("ioctl(CIOCAUTHCRYPT)"); + return -1; + } + + return 0; +} + diff --git a/drivers/cryptodev-linux-master/examples/aes-sha1.h b/drivers/cryptodev-linux-master/examples/aes-sha1.h new file mode 100644 index 00000000..a07334cf --- /dev/null +++ b/drivers/cryptodev-linux-master/examples/aes-sha1.h @@ -0,0 +1,31 @@ +#ifndef AES_H +# define AES_H + +#include + +struct cryptodev_ctx { + int cfd; + struct session_op sess; + uint16_t alignmask; +}; + +#define AES_BLOCK_SIZE 16 + +int aes_sha1_ctx_init(struct cryptodev_ctx* ctx, int cfd, + const uint8_t *key, unsigned int key_size, + const uint8_t *mac_key, unsigned int mac_key_size); +void aes_sha1_ctx_deinit(); + +/* Note that encryption assumes that ciphertext has enough size + * for the tag and padding to be appended. + * + * Only in-place encryption and decryption are supported. + */ +int aes_sha1_encrypt(struct cryptodev_ctx* ctx, const void* iv, + const void* auth, size_t auth_size, + void* plaintext, size_t size); +int aes_sha1_decrypt(struct cryptodev_ctx* ctx, const void* iv, + const void* auth, size_t auth_size, + void* ciphertext, size_t size); + +#endif diff --git a/drivers/cryptodev-linux-master/examples/aes.c b/drivers/cryptodev-linux-master/examples/aes.c new file mode 100644 index 00000000..02f7613b --- /dev/null +++ b/drivers/cryptodev-linux-master/examples/aes.c @@ -0,0 +1,242 @@ +/* + * Demo on how to use /dev/crypto device for ciphering. + * + * Placed under public domain. + * + */ +#include +#include +#include +#include +#include +#include +#include "aes.h" + +#define KEY_SIZE 16 + + +int aes_ctx_init(struct cryptodev_ctx* ctx, int cfd, const uint8_t *key, unsigned int key_size) +{ +#ifdef CIOCGSESSINFO + struct session_info_op siop; +#endif + + memset(ctx, 0, sizeof(*ctx)); + ctx->cfd = cfd; + + ctx->sess.cipher = CRYPTO_AES_CBC; + ctx->sess.keylen = key_size; + ctx->sess.key = (void*)key; + if (ioctl(ctx->cfd, CIOCGSESSION, &ctx->sess)) { + perror("ioctl(CIOCGSESSION)"); + return -1; + } + +#ifdef CIOCGSESSINFO + memset(&siop, 0, sizeof(siop)); + + siop.ses = ctx->sess.ses; + if (ioctl(ctx->cfd, CIOCGSESSINFO, &siop)) { + perror("ioctl(CIOCGSESSINFO)"); + return -1; + } + printf("Got %s with driver %s\n", + siop.cipher_info.cra_name, siop.cipher_info.cra_driver_name); + if (!(siop.flags & SIOP_FLAG_KERNEL_DRIVER_ONLY)) { + printf("Note: This is not an accelerated cipher\n"); + } + /*printf("Alignmask is %x\n", (unsigned int)siop.alignmask); */ + ctx->alignmask = siop.alignmask; +#endif + return 0; +} + +void aes_ctx_deinit(struct cryptodev_ctx* ctx) +{ + if (ioctl(ctx->cfd, CIOCFSESSION, &ctx->sess.ses)) { + perror("ioctl(CIOCFSESSION)"); + } +} + +int +aes_encrypt(struct cryptodev_ctx* ctx, const void* iv, const void* plaintext, void* ciphertext, size_t size) +{ + struct crypt_op cryp; + void* p; + + /* check plaintext and ciphertext alignment */ + if (ctx->alignmask) { + p = (void*)(((unsigned long)plaintext + ctx->alignmask) & ~ctx->alignmask); + if (plaintext != p) { + fprintf(stderr, "plaintext is not aligned\n"); + return -1; + } + + p = (void*)(((unsigned long)ciphertext + ctx->alignmask) & ~ctx->alignmask); + if (ciphertext != p) { + fprintf(stderr, "ciphertext is not aligned\n"); + return -1; + } + } + + memset(&cryp, 0, sizeof(cryp)); + + /* Encrypt data.in to data.encrypted */ + cryp.ses = ctx->sess.ses; + cryp.len = size; + cryp.src = (void*)plaintext; + cryp.dst = ciphertext; + cryp.iv = (void*)iv; + cryp.op = COP_ENCRYPT; + if (ioctl(ctx->cfd, CIOCCRYPT, &cryp)) { + perror("ioctl(CIOCCRYPT)"); + return -1; + } + + return 0; +} + +int +aes_decrypt(struct cryptodev_ctx* ctx, const void* iv, const void* ciphertext, void* plaintext, size_t size) +{ + struct crypt_op cryp; + void* p; + + /* check plaintext and ciphertext alignment */ + if (ctx->alignmask) { + p = (void*)(((unsigned long)plaintext + ctx->alignmask) & ~ctx->alignmask); + if (plaintext != p) { + fprintf(stderr, "plaintext is not aligned\n"); + return -1; + } + + p = (void*)(((unsigned long)ciphertext + ctx->alignmask) & ~ctx->alignmask); + if (ciphertext != p) { + fprintf(stderr, "ciphertext is not aligned\n"); + return -1; + } + } + + memset(&cryp, 0, sizeof(cryp)); + + /* Encrypt data.in to data.encrypted */ + cryp.ses = ctx->sess.ses; + cryp.len = size; + cryp.src = (void*)ciphertext; + cryp.dst = plaintext; + cryp.iv = (void*)iv; + cryp.op = COP_DECRYPT; + if (ioctl(ctx->cfd, CIOCCRYPT, &cryp)) { + perror("ioctl(CIOCCRYPT)"); + return -1; + } + + return 0; +} + +static int test_aes(int cfd) +{ + char plaintext1_raw[AES_BLOCK_SIZE + 63], *plaintext1; + char ciphertext1[AES_BLOCK_SIZE] = { 0xdf, 0x55, 0x6a, 0x33, 0x43, 0x8d, 0xb8, 0x7b, 0xc4, 0x1b, 0x17, 0x52, 0xc5, 0x5e, 0x5e, 0x49 }; + char iv1[AES_BLOCK_SIZE]; + uint8_t key1[KEY_SIZE] = { 0xff, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + char plaintext2_data[AES_BLOCK_SIZE] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x00 }; + char plaintext2_raw[AES_BLOCK_SIZE + 63], *plaintext2; + char ciphertext2[AES_BLOCK_SIZE] = { 0xb7, 0x97, 0x2b, 0x39, 0x41, 0xc4, 0x4b, 0x90, 0xaf, 0xa7, 0xb2, 0x64, 0xbf, 0xba, 0x73, 0x87 }; + char iv2[AES_BLOCK_SIZE]; + uint8_t key2[KEY_SIZE]; + struct cryptodev_ctx ctx; + + aes_ctx_init(&ctx, cfd, key1, sizeof(key1)); + + if (ctx.alignmask) + plaintext1 = (char *)(((unsigned long)plaintext1_raw + ctx.alignmask) & ~ctx.alignmask); + else + plaintext1 = plaintext1_raw; + + memset(plaintext1, 0x0, AES_BLOCK_SIZE); + memset(iv1, 0x0, sizeof(iv1)); + + aes_encrypt(&ctx, iv1, plaintext1, plaintext1, AES_BLOCK_SIZE); + + /* Verify the result */ + if (memcmp(plaintext1, ciphertext1, AES_BLOCK_SIZE) != 0) { + fprintf(stderr, + "FAIL: Decrypted data are different from the input data.\n"); + return -1; + } + + aes_ctx_deinit(&ctx); + + /* Test 2 */ + + memset(key2, 0x0, sizeof(key2)); + memset(iv2, 0x0, sizeof(iv2)); + + aes_ctx_init(&ctx, cfd, key2, sizeof(key2)); + + if (ctx.alignmask) { + plaintext2 = (char *)(((unsigned long)plaintext2_raw + ctx.alignmask) & ~ctx.alignmask); + } else { + plaintext2 = plaintext2_raw; + } + memcpy(plaintext2, plaintext2_data, AES_BLOCK_SIZE); + + /* Encrypt data.in to data.encrypted */ + aes_encrypt(&ctx, iv2, plaintext2, plaintext2, AES_BLOCK_SIZE); + + /* Verify the result */ + if (memcmp(plaintext2, ciphertext2, AES_BLOCK_SIZE) != 0) { + int i; + fprintf(stderr, + "FAIL: Decrypted data are different from the input data.\n"); + printf("plaintext:"); + for (i = 0; i < AES_BLOCK_SIZE; i++) { + printf("%02x ", plaintext2[i]); + } + printf("ciphertext:"); + for (i = 0; i < AES_BLOCK_SIZE; i++) { + printf("%02x ", ciphertext2[i]); + } + printf("\n"); + return 1; + } + + aes_ctx_deinit(&ctx); + + printf("AES Test passed\n"); + + return 0; +} + +int +main() +{ + int cfd = -1; + + /* Open the crypto device */ + cfd = open("/dev/crypto", O_RDWR, 0); + if (cfd < 0) { + perror("open(/dev/crypto)"); + return 1; + } + + /* Set close-on-exec (not really neede here) */ + if (fcntl(cfd, F_SETFD, 1) == -1) { + perror("fcntl(F_SETFD)"); + return 1; + } + + /* Run the test itself */ + if (test_aes(cfd)) + return 1; + + /* Close the original descriptor */ + if (close(cfd)) { + perror("close(cfd)"); + return 1; + } + + return 0; +} + diff --git a/drivers/cryptodev-linux-master/examples/aes.h b/drivers/cryptodev-linux-master/examples/aes.h new file mode 100644 index 00000000..ade90c92 --- /dev/null +++ b/drivers/cryptodev-linux-master/examples/aes.h @@ -0,0 +1,19 @@ +#ifndef AES_H +# define AES_H + +#include + +struct cryptodev_ctx { + int cfd; + struct session_op sess; + uint16_t alignmask; +}; + +#define AES_BLOCK_SIZE 16 + +int aes_ctx_init(struct cryptodev_ctx* ctx, int cfd, const uint8_t *key, unsigned int key_size); +void aes_ctx_deinit(); +int aes_encrypt(struct cryptodev_ctx* ctx, const void* iv, const void* plaintext, void* ciphertext, size_t size); +int aes_decrypt(struct cryptodev_ctx* ctx, const void* iv, const void* ciphertext, void* plaintext, size_t size); + +#endif diff --git a/drivers/cryptodev-linux-master/examples/sha-copy.c b/drivers/cryptodev-linux-master/examples/sha-copy.c new file mode 100644 index 00000000..6bf8d2f8 --- /dev/null +++ b/drivers/cryptodev-linux-master/examples/sha-copy.c @@ -0,0 +1,240 @@ +/* + * Demo on how to use /dev/crypto device for calculating a hash + * at once, using init->hash, and compare it to using: + * using init->update->final, and init->update->copy-> update -> final + * init->----\> update -> final + * + * Placed under public domain. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include "sha-copy.h" + +int sha_ctx_init(struct cryptodev_ctx* ctx, int cfd, const uint8_t *key, unsigned int key_size) +{ + struct session_info_op siop; + + memset(ctx, 0, sizeof(*ctx)); + ctx->cfd = cfd; + + if (key == NULL) + ctx->sess.mac = CRYPTO_SHA1; + else { + ctx->sess.mac = CRYPTO_SHA1_HMAC; + ctx->sess.mackeylen = key_size; + ctx->sess.mackey = (void*)key; + } + if (ioctl(ctx->cfd, CIOCGSESSION, &ctx->sess)) { + perror("ioctl(CIOCGSESSION)"); + return -1; + } +#ifdef DEBUG + fprintf(stderr, "sha_ctx_init: cfd=%d, ses=%04x\n", ctx->cfd, ctx->sess.ses); +#endif + + siop.ses = ctx->sess.ses; + if (ioctl(ctx->cfd, CIOCGSESSINFO, &siop)) { + perror("ioctl(CIOCGSESSINFO)"); + return -1; + } + printf("Got %s with driver %s\n", + siop.hash_info.cra_name, siop.hash_info.cra_driver_name); + if (!(siop.flags & SIOP_FLAG_KERNEL_DRIVER_ONLY)) { + printf("Note: This is not an accelerated cipher\n"); + } + return 0; +} + +static int sha_call_crypt(struct cryptodev_ctx* ctx, const void* text, + size_t size, void *digest, unsigned int flags) +{ + struct crypt_op cryp; + + memset(&cryp, 0, sizeof(cryp)); + + /* Fill out the fields with text, size, digest result and flags */ + cryp.ses = ctx->sess.ses; + cryp.len = size; + cryp.src = (void*)text; + cryp.mac = digest; + cryp.flags = flags; +#ifdef DEBUG + fprintf(stderr, "sha_call_crypt: cfd=%d, ses=%04x, CIOCCRYPT(len=%d, src='%s', flags=%04x)\n", + ctx->cfd, ctx->sess.ses, cryp.len, (char *)cryp.src, cryp.flags); +#endif + return ioctl(ctx->cfd, CIOCCRYPT, &cryp); +} + +int sha_hash(struct cryptodev_ctx* ctx, const void* text, size_t size, void* digest) +{ +#ifdef DEBUG + fprintf(stderr, "sha_hash: cfd=%d, ses=%04x, text='%s', size=%ld\n", + ctx->cfd, ctx->sess.ses, (char *) text, size); +#endif + if (sha_call_crypt(ctx, text, size, digest, 0)) { + perror("sha_hash: ioctl(CIOCCRYPT)"); + return -1; + } + + return 0; +} + +int sha_update(struct cryptodev_ctx* ctx, const void* text, size_t size) +{ +#ifdef DEBUG + fprintf(stderr, "sha_update: cfd=%d, ses=%04x, text='%s', size=%ld\n", + ctx->cfd, ctx->sess.ses, (char *) text, size); +#endif + if (sha_call_crypt(ctx, text, size, NULL, COP_FLAG_UPDATE)) { + perror("sha_update: ioctl(CIOCCRYPT)"); + return -1; + } + + return 0; +} + +int sha_copy(struct cryptodev_ctx* to_ctx, const struct cryptodev_ctx* from_ctx) +{ + struct cphash_op cphash; + +#ifdef DEBUG + fprintf(stderr, "sha_copy: from= cfd=%d, ses=%04x\n" + " to= cfd=%d, ses=%04x\n", + from_ctx->cfd, from_ctx->sess.ses, to_ctx->cfd, to_ctx->sess.ses); +#endif + memset(&cphash, 0, sizeof(cphash)); + + cphash.src_ses = from_ctx->sess.ses; + cphash.dst_ses = to_ctx->sess.ses; + if (ioctl(to_ctx->cfd, CIOCCPHASH, &cphash)) { + perror("ioctl(CIOCCPHASH)"); + return -1; + } + + return 0; +} + +int sha_final(struct cryptodev_ctx* ctx, const void* text, size_t size, void* digest) +{ +#ifdef DEBUG + fprintf(stderr, "sha_final: cfd=%d, ses=%04x, text='%s', size=%ld\n", + ctx->cfd, ctx->sess.ses, (char *) text, size); +#endif + if (sha_call_crypt(ctx, text, size, digest, COP_FLAG_FINAL)) { + perror("sha_final: ioctl(CIOCCRYPT)"); + return -1; + } + + return 0; +} + +void sha_ctx_deinit(struct cryptodev_ctx* ctx) +{ +#ifdef DEBUG + fprintf(stderr, "sha_ctx_deinit: cfd=%d, ses=%04x\n", ctx->cfd, ctx->sess.ses); +#endif + if (ioctl(ctx->cfd, CIOCFSESSION, &ctx->sess.ses)) { + perror("ioctl(CIOCFSESSION)"); + } +} + +static int print_digest(uint8_t *digest, uint8_t *expected) +{ + int i; + + if (memcmp(digest, expected, 20) != 0) { + fprintf(stderr, "SHA1 hashing failed\n"); + } + + printf("digest: "); + for (i = 0; i < 20; i++) { + printf("%02x:", *digest); + digest++; + } + printf("\n"); +} + +int +main() +{ + int cfd = -1; + struct cryptodev_ctx ctx1, ctx2; + uint8_t digest[20]; + char text[] = "The quick brown fox jumps over the lazy dog"; + char text1[] = "The quick brown fox"; + char text2[] = " jumps over the lazy dog"; + char text3[] = " jumps over the lazy dogs"; + uint8_t expected[] = "\x2f\xd4\xe1\xc6\x7a\x2d\x28\xfc\xed\x84\x9e\xe1\xbb\x76\xe7\x39\x1b\x93\xeb\x12"; + uint8_t expected2[] = "\xf8\xc3\xc5\x41\x25\x7a\x6c\x31\xf6\xfb\xc6\x97\xa5\x0f\x46\xd9\xfc\x8b\xcc\x30"; + + /* Open the crypto device */ + cfd = open("/dev/crypto", O_RDWR, 0); + if (cfd < 0) { + perror("open(/dev/crypto)"); + return 1; + } + + /* Set close-on-exec (not really neede here) */ + if (fcntl(cfd, F_SETFD, 1) == -1) { + perror("fcntl(F_SETFD)"); + return 1; + } + + printf("Computing digest in one operation\n"); + sha_ctx_init(&ctx1, cfd, NULL, 0); + sha_hash(&ctx1, text, strlen(text), digest); + sha_ctx_deinit(&ctx1); + print_digest(digest, expected); + + printf("\n\nComputing digest using update/final\n"); + sha_ctx_init(&ctx1, cfd, NULL, 0); + sha_update(&ctx1, text1, strlen(text1)); + sha_final(&ctx1, text2, strlen(text2), digest); + sha_ctx_deinit(&ctx1); + print_digest(digest, expected); + + printf("\n\nComputing digest using update/copy/final\n"); + sha_ctx_init(&ctx1, cfd, NULL, 0); + sha_update(&ctx1, text1, strlen(text1)); + sha_ctx_init(&ctx2, cfd, NULL, 0); + sha_copy(&ctx2, &ctx1); + printf("\nOriginal operation:\n"); + sha_update(&ctx1, text2, strlen(text2)); + sha_final(&ctx1, NULL, 0, digest); + print_digest(digest, expected); + printf("\nCopied operation:\n"); + sha_final(&ctx2, text2, strlen(text2), digest); + sha_ctx_deinit(&ctx1); + sha_ctx_deinit(&ctx2); + print_digest(digest, expected); + + printf("\n\nComputing digest using update/copy/final with different texts\n"); + sha_ctx_init(&ctx1, cfd, NULL, 0); + sha_update(&ctx1, text1, strlen(text1)); + sha_ctx_init(&ctx2, cfd, NULL, 0); + sha_copy(&ctx2, &ctx1); + printf("\nOriginal operation, with original text:\n"); + sha_update(&ctx1, text2, strlen(text2)); + sha_final(&ctx1, NULL, 0, digest); + print_digest(digest, expected); + printf("\nCopied operation, with different text:\n"); + sha_update(&ctx2, text3, strlen(text3)); + sha_final(&ctx2, NULL, 0, digest); + sha_ctx_deinit(&ctx1); + sha_ctx_deinit(&ctx2); + print_digest(digest, expected2); + + /* Close the original descriptor */ + if (close(cfd)) { + perror("close(cfd)"); + return 1; + } + + return 0; +} diff --git a/drivers/cryptodev-linux-master/examples/sha-copy.h b/drivers/cryptodev-linux-master/examples/sha-copy.h new file mode 100644 index 00000000..8b2114e6 --- /dev/null +++ b/drivers/cryptodev-linux-master/examples/sha-copy.h @@ -0,0 +1,18 @@ +#ifndef SHA_COPY_H +#define SHA_COPY_H + +#include + +struct cryptodev_ctx { + int cfd; + struct session_op sess; +}; + +int sha_ctx_init(struct cryptodev_ctx* ctx, int cfd, const uint8_t *key, unsigned int key_size); +int sha_hash(struct cryptodev_ctx* ctx, const void* text, size_t size, void* digest); +int sha_update(struct cryptodev_ctx* ctx, const void* text, size_t size); +int sha_copy(struct cryptodev_ctx* to_ctx, const struct cryptodev_ctx* from_ctx); +int sha_final(struct cryptodev_ctx* ctx, const void* text, size_t size, void* digest); +void sha_ctx_deinit(struct cryptodev_ctx* ctx); + +#endif /* SHA_COPY_H */ diff --git a/drivers/cryptodev-linux-master/examples/sha.c b/drivers/cryptodev-linux-master/examples/sha.c new file mode 100644 index 00000000..4f45a6b0 --- /dev/null +++ b/drivers/cryptodev-linux-master/examples/sha.c @@ -0,0 +1,137 @@ +/* + * Demo on how to use /dev/crypto device for ciphering. + * + * Placed under public domain. + * + */ +#include +#include +#include +#include +#include +#include +#include "sha.h" + +int sha_ctx_init(struct cryptodev_ctx* ctx, int cfd, const uint8_t *key, unsigned int key_size) +{ +#ifdef CIOCGSESSINFO + struct session_info_op siop; +#endif + + memset(ctx, 0, sizeof(*ctx)); + ctx->cfd = cfd; + + if (key == NULL) + ctx->sess.mac = CRYPTO_SHA1; + else { + ctx->sess.mac = CRYPTO_SHA1_HMAC; + ctx->sess.mackeylen = key_size; + ctx->sess.mackey = (void*)key; + } + if (ioctl(ctx->cfd, CIOCGSESSION, &ctx->sess)) { + perror("ioctl(CIOCGSESSION)"); + return -1; + } + +#ifdef CIOCGSESSINFO + siop.ses = ctx->sess.ses; + if (ioctl(ctx->cfd, CIOCGSESSINFO, &siop)) { + perror("ioctl(CIOCGSESSINFO)"); + return -1; + } + printf("Got %s with driver %s\n", + siop.hash_info.cra_name, siop.hash_info.cra_driver_name); + if (!(siop.flags & SIOP_FLAG_KERNEL_DRIVER_ONLY)) { + printf("Note: This is not an accelerated cipher\n"); + } + /*printf("Alignmask is %x\n", (unsigned int)siop.alignmask);*/ + ctx->alignmask = siop.alignmask; +#endif + return 0; +} + +void sha_ctx_deinit(struct cryptodev_ctx* ctx) +{ + if (ioctl(ctx->cfd, CIOCFSESSION, &ctx->sess.ses)) { + perror("ioctl(CIOCFSESSION)"); + } +} + +int +sha_hash(struct cryptodev_ctx* ctx, const void* text, size_t size, void* digest) +{ + struct crypt_op cryp; + void* p; + + /* check text and ciphertext alignment */ + if (ctx->alignmask) { + p = (void*)(((unsigned long)text + ctx->alignmask) & ~ctx->alignmask); + if (text != p) { + fprintf(stderr, "text is not aligned\n"); + return -1; + } + } + + memset(&cryp, 0, sizeof(cryp)); + + /* Encrypt data.in to data.encrypted */ + cryp.ses = ctx->sess.ses; + cryp.len = size; + cryp.src = (void*)text; + cryp.mac = digest; + if (ioctl(ctx->cfd, CIOCCRYPT, &cryp)) { + perror("ioctl(CIOCCRYPT)"); + return -1; + } + + return 0; +} + +int +main() +{ + int cfd = -1, i; + struct cryptodev_ctx ctx; + uint8_t digest[20]; + char text[] = "The quick brown fox jumps over the lazy dog"; + uint8_t expected[] = "\x2f\xd4\xe1\xc6\x7a\x2d\x28\xfc\xed\x84\x9e\xe1\xbb\x76\xe7\x39\x1b\x93\xeb\x12"; + + /* Open the crypto device */ + cfd = open("/dev/crypto", O_RDWR, 0); + if (cfd < 0) { + perror("open(/dev/crypto)"); + return 1; + } + + /* Set close-on-exec (not really neede here) */ + if (fcntl(cfd, F_SETFD, 1) == -1) { + perror("fcntl(F_SETFD)"); + return 1; + } + + sha_ctx_init(&ctx, cfd, NULL, 0); + + sha_hash(&ctx, text, strlen(text), digest); + + sha_ctx_deinit(&ctx); + + printf("digest: "); + for (i = 0; i < 20; i++) { + printf("%02x:", digest[i]); + } + printf("\n"); + + if (memcmp(digest, expected, 20) != 0) { + fprintf(stderr, "SHA1 hashing failed\n"); + return 1; + } + + /* Close the original descriptor */ + if (close(cfd)) { + perror("close(cfd)"); + return 1; + } + + return 0; +} + diff --git a/drivers/cryptodev-linux-master/examples/sha.h b/drivers/cryptodev-linux-master/examples/sha.h new file mode 100644 index 00000000..ed0b8cee --- /dev/null +++ b/drivers/cryptodev-linux-master/examples/sha.h @@ -0,0 +1,16 @@ +#ifndef SHA_H +# define SHA_H + +#include + +struct cryptodev_ctx { + int cfd; + struct session_op sess; + uint16_t alignmask; +}; + +int sha_ctx_init(struct cryptodev_ctx* ctx, int cfd, const uint8_t *key, unsigned int key_size); +void sha_ctx_deinit(); +int sha_hash(struct cryptodev_ctx* ctx, const void* text, size_t size, void* digest); + +#endif diff --git a/drivers/cryptodev-linux-master/ioctl.c b/drivers/cryptodev-linux-master/ioctl.c new file mode 100644 index 00000000..3d332380 --- /dev/null +++ b/drivers/cryptodev-linux-master/ioctl.c @@ -0,0 +1,1227 @@ +/* + * Driver for /dev/crypto device (aka CryptoDev) + * + * Copyright (c) 2004 Michal Ludvig , SuSE Labs + * Copyright (c) 2009,2010,2011 Nikos Mavrogiannopoulos + * Copyright (c) 2010 Phil Sutter + * + * This file is part of linux cryptodev. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +/* + * Device /dev/crypto provides an interface for + * accessing kernel CryptoAPI algorithms (ciphers, + * hashes) from userspace programs. + * + * /dev/crypto interface was originally introduced in + * OpenBSD and this module attempts to keep the API. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "cryptodev_int.h" +#include "zc.h" +#include "version.h" +#include "cipherapi.h" + +MODULE_AUTHOR("Nikos Mavrogiannopoulos "); +MODULE_DESCRIPTION("CryptoDev driver"); +MODULE_LICENSE("GPL"); + +/* ====== Compile-time config ====== */ + +/* Default (pre-allocated) and maximum size of the job queue. + * These are free, pending and done items all together. */ +#define DEF_COP_RINGSIZE 16 +#define MAX_COP_RINGSIZE 64 + +/* ====== Module parameters ====== */ + +int cryptodev_verbosity; +module_param(cryptodev_verbosity, int, 0644); +MODULE_PARM_DESC(cryptodev_verbosity, "0: normal, 1: verbose, 2: debug"); + +/* ====== CryptoAPI ====== */ +struct todo_list_item { + struct list_head __hook; + struct kernel_crypt_op kcop; + int result; +}; + +struct locked_list { + struct list_head list; + struct mutex lock; +}; + +struct crypt_priv { + struct fcrypt fcrypt; + struct locked_list free, todo, done; + int itemcount; + struct work_struct cryptask; + wait_queue_head_t user_waiter; +}; + +#define FILL_SG(sg, ptr, len) \ + do { \ + (sg)->page = virt_to_page(ptr); \ + (sg)->offset = offset_in_page(ptr); \ + (sg)->length = len; \ + (sg)->dma_address = 0; \ + } while (0) + +/* cryptodev's own workqueue, keeps crypto tasks from disturbing the force */ +static struct workqueue_struct *cryptodev_wq; + +/* Prepare session for future use. */ +static int +crypto_create_session(struct fcrypt *fcr, struct session_op *sop) +{ + struct csession *ses_new = NULL, *ses_ptr; + int ret = 0; + const char *alg_name = NULL; + const char *hash_name = NULL; + int hmac_mode = 1, stream = 0, aead = 0; + /* + * With composite aead ciphers, only ckey is used and it can cover all the + * structure space; otherwise both keys may be used simultaneously but they + * are confined to their spaces + */ + struct { + uint8_t ckey[CRYPTO_CIPHER_MAX_KEY_LEN]; + uint8_t mkey[CRYPTO_HMAC_MAX_KEY_LEN]; + /* padding space for aead keys */ + uint8_t pad[RTA_SPACE(sizeof(struct crypto_authenc_key_param))]; + } keys; + + /* Does the request make sense? */ + if (unlikely(!sop->cipher && !sop->mac)) { + ddebug(1, "Both 'cipher' and 'mac' unset."); + return -EINVAL; + } + + switch (sop->cipher) { + case 0: + break; + case CRYPTO_DES_CBC: + alg_name = "cbc(des)"; + break; + case CRYPTO_3DES_CBC: + alg_name = "cbc(des3_ede)"; + break; + case CRYPTO_BLF_CBC: + alg_name = "cbc(blowfish)"; + break; + case CRYPTO_AES_CBC: + alg_name = "cbc(aes)"; + break; + case CRYPTO_AES_ECB: + alg_name = "ecb(aes)"; + break; + case CRYPTO_CAMELLIA_CBC: + alg_name = "cbc(camellia)"; + break; + case CRYPTO_AES_CTR: + alg_name = "ctr(aes)"; + stream = 1; + break; + case CRYPTO_AES_GCM: + alg_name = "gcm(aes)"; + stream = 1; + aead = 1; + break; + case CRYPTO_TLS11_AES_CBC_HMAC_SHA1: + alg_name = "tls11(hmac(sha1),cbc(aes))"; + stream = 0; + aead = 1; + break; + case CRYPTO_TLS12_AES_CBC_HMAC_SHA256: + alg_name = "tls12(hmac(sha256),cbc(aes))"; + stream = 0; + aead = 1; + break; + case CRYPTO_NULL: + alg_name = "ecb(cipher_null)"; + stream = 1; + break; + default: + ddebug(1, "bad cipher: %d", sop->cipher); + return -EINVAL; + } + + switch (sop->mac) { + case 0: + break; + case CRYPTO_MD5_HMAC: + hash_name = "hmac(md5)"; + break; + case CRYPTO_RIPEMD160_HMAC: + hash_name = "hmac(rmd160)"; + break; + case CRYPTO_SHA1_HMAC: + hash_name = "hmac(sha1)"; + break; + case CRYPTO_SHA2_224_HMAC: + hash_name = "hmac(sha224)"; + break; + + case CRYPTO_SHA2_256_HMAC: + hash_name = "hmac(sha256)"; + break; + case CRYPTO_SHA2_384_HMAC: + hash_name = "hmac(sha384)"; + break; + case CRYPTO_SHA2_512_HMAC: + hash_name = "hmac(sha512)"; + break; + + /* non-hmac cases */ + case CRYPTO_MD5: + hash_name = "md5"; + hmac_mode = 0; + break; + case CRYPTO_RIPEMD160: + hash_name = "rmd160"; + hmac_mode = 0; + break; + case CRYPTO_SHA1: + hash_name = "sha1"; + hmac_mode = 0; + break; + case CRYPTO_SHA2_224: + hash_name = "sha224"; + hmac_mode = 0; + break; + case CRYPTO_SHA2_256: + hash_name = "sha256"; + hmac_mode = 0; + break; + case CRYPTO_SHA2_384: + hash_name = "sha384"; + hmac_mode = 0; + break; + case CRYPTO_SHA2_512: + hash_name = "sha512"; + hmac_mode = 0; + break; + default: + ddebug(1, "bad mac: %d", sop->mac); + return -EINVAL; + } + + /* Create a session and put it to the list. Zeroing the structure helps + * also with a single exit point in case of errors */ + ses_new = kzalloc(sizeof(*ses_new), GFP_KERNEL); + if (!ses_new) + return -ENOMEM; + + /* Set-up crypto transform. */ + if (alg_name) { + unsigned int keylen; + ret = cryptodev_get_cipher_keylen(&keylen, sop, aead); + if (unlikely(ret < 0)) { + ddebug(1, "Setting key failed for %s-%zu.", + alg_name, (size_t)sop->keylen*8); + goto session_error; + } + + ret = cryptodev_get_cipher_key(keys.ckey, sop, aead); + if (unlikely(ret < 0)) + goto session_error; + + ret = cryptodev_cipher_init(&ses_new->cdata, alg_name, keys.ckey, + keylen, stream, aead); + if (ret < 0) { + ddebug(1, "Failed to load cipher for %s", alg_name); + ret = -EINVAL; + goto session_error; + } + } + + if (hash_name && aead == 0) { + if (unlikely(sop->mackeylen > CRYPTO_HMAC_MAX_KEY_LEN)) { + ddebug(1, "Setting key failed for %s-%zu.", + hash_name, (size_t)sop->mackeylen*8); + ret = -EINVAL; + goto session_error; + } + + if (sop->mackey && unlikely(copy_from_user(keys.mkey, sop->mackey, + sop->mackeylen))) { + ret = -EFAULT; + goto session_error; + } + + ret = cryptodev_hash_init(&ses_new->hdata, hash_name, hmac_mode, + keys.mkey, sop->mackeylen); + if (ret != 0) { + ddebug(1, "Failed to load hash for %s", hash_name); + ret = -EINVAL; + goto session_error; + } + + ret = cryptodev_hash_reset(&ses_new->hdata); + if (ret != 0) { + goto session_error; + } + } + + ses_new->alignmask = max(ses_new->cdata.alignmask, + ses_new->hdata.alignmask); + ddebug(2, "got alignmask %d", ses_new->alignmask); + + ses_new->array_size = DEFAULT_PREALLOC_PAGES; + ddebug(2, "preallocating for %d user pages", ses_new->array_size); + ses_new->pages = kzalloc(ses_new->array_size * + sizeof(struct page *), GFP_KERNEL); + ses_new->sg = kzalloc(ses_new->array_size * + sizeof(struct scatterlist), GFP_KERNEL); + if (ses_new->sg == NULL || ses_new->pages == NULL) { + ddebug(0, "Memory error"); + ret = -ENOMEM; + goto session_error; + } + + /* put the new session to the list */ + get_random_bytes(&ses_new->sid, sizeof(ses_new->sid)); + mutex_init(&ses_new->sem); + + mutex_lock(&fcr->sem); +restart: + list_for_each_entry(ses_ptr, &fcr->list, entry) { + /* Check for duplicate SID */ + if (unlikely(ses_new->sid == ses_ptr->sid)) { + get_random_bytes(&ses_new->sid, sizeof(ses_new->sid)); + /* Unless we have a broken RNG this + shouldn't loop forever... ;-) */ + goto restart; + } + } + + list_add(&ses_new->entry, &fcr->list); + mutex_unlock(&fcr->sem); + + /* Fill in some values for the user. */ + sop->ses = ses_new->sid; + return 0; + + /* We count on ses_new to be initialized with zeroes + * Since hdata and cdata are embedded within ses_new, it follows that + * hdata->init and cdata->init are either zero or one as they have been + * initialized or not */ +session_error: + cryptodev_hash_deinit(&ses_new->hdata); + cryptodev_cipher_deinit(&ses_new->cdata); + kfree(ses_new->sg); + kfree(ses_new->pages); + kfree(ses_new); + return ret; +} + +/* Everything that needs to be done when removing a session. */ +static inline void +crypto_destroy_session(struct csession *ses_ptr) +{ + if (!mutex_trylock(&ses_ptr->sem)) { + ddebug(2, "Waiting for semaphore of sid=0x%08X", ses_ptr->sid); + mutex_lock(&ses_ptr->sem); + } + ddebug(2, "Removed session 0x%08X", ses_ptr->sid); + cryptodev_cipher_deinit(&ses_ptr->cdata); + cryptodev_hash_deinit(&ses_ptr->hdata); + ddebug(2, "freeing space for %d user pages", ses_ptr->array_size); + kfree(ses_ptr->pages); + kfree(ses_ptr->sg); + mutex_unlock(&ses_ptr->sem); + mutex_destroy(&ses_ptr->sem); + kfree(ses_ptr); +} + +/* Look up a session by ID and remove. */ +static int +crypto_finish_session(struct fcrypt *fcr, uint32_t sid) +{ + struct csession *tmp, *ses_ptr; + struct list_head *head; + int ret = 0; + + mutex_lock(&fcr->sem); + head = &fcr->list; + list_for_each_entry_safe(ses_ptr, tmp, head, entry) { + if (ses_ptr->sid == sid) { + list_del(&ses_ptr->entry); + crypto_destroy_session(ses_ptr); + break; + } + } + + if (unlikely(!ses_ptr)) { + derr(1, "Session with sid=0x%08X not found!", sid); + ret = -ENOENT; + } + mutex_unlock(&fcr->sem); + + return ret; +} + +/* Remove all sessions when closing the file */ +static int +crypto_finish_all_sessions(struct fcrypt *fcr) +{ + struct csession *tmp, *ses_ptr; + struct list_head *head; + + mutex_lock(&fcr->sem); + + head = &fcr->list; + list_for_each_entry_safe(ses_ptr, tmp, head, entry) { + list_del(&ses_ptr->entry); + crypto_destroy_session(ses_ptr); + } + mutex_unlock(&fcr->sem); + + return 0; +} + +/* Look up session by session ID. The returned session is locked. */ +struct csession * +crypto_get_session_by_sid(struct fcrypt *fcr, uint32_t sid) +{ + struct csession *ses_ptr, *retval = NULL; + + if (unlikely(fcr == NULL)) + return NULL; + + mutex_lock(&fcr->sem); + list_for_each_entry(ses_ptr, &fcr->list, entry) { + if (ses_ptr->sid == sid) { + mutex_lock(&ses_ptr->sem); + retval = ses_ptr; + break; + } + } + mutex_unlock(&fcr->sem); + + return retval; +} + +#ifdef CIOCCPHASH +/* Copy the hash state from one session to another */ +static int +crypto_copy_hash_state(struct fcrypt *fcr, uint32_t dst_sid, uint32_t src_sid) +{ + struct csession *src_ses, *dst_ses; + int ret; + + src_ses = crypto_get_session_by_sid(fcr, src_sid); + if (unlikely(src_ses == NULL)) { + derr(1, "Session with sid=0x%08X not found!", src_sid); + return -ENOENT; + } + + dst_ses = crypto_get_session_by_sid(fcr, dst_sid); + if (unlikely(dst_ses == NULL)) { + derr(1, "Session with sid=0x%08X not found!", dst_sid); + crypto_put_session(src_ses); + return -ENOENT; + } + + ret = cryptodev_hash_copy(&dst_ses->hdata, &src_ses->hdata); + crypto_put_session(src_ses); + crypto_put_session(dst_ses); + return ret; +} +#endif /* CIOCCPHASH */ + +static void cryptask_routine(struct work_struct *work) +{ + struct crypt_priv *pcr = container_of(work, struct crypt_priv, cryptask); + struct todo_list_item *item; + LIST_HEAD(tmp); + + /* fetch all pending jobs into the temporary list */ + mutex_lock(&pcr->todo.lock); + list_cut_position(&tmp, &pcr->todo.list, pcr->todo.list.prev); + mutex_unlock(&pcr->todo.lock); + + /* handle each job locklessly */ + list_for_each_entry(item, &tmp, __hook) { + item->result = crypto_run(&pcr->fcrypt, &item->kcop); + if (unlikely(item->result)) + derr(0, "crypto_run() failed: %d", item->result); + } + + /* push all handled jobs to the done list at once */ + mutex_lock(&pcr->done.lock); + list_splice_tail(&tmp, &pcr->done.list); + mutex_unlock(&pcr->done.lock); + + /* wake for POLLIN */ + wake_up_interruptible(&pcr->user_waiter); +} + +/* ====== /dev/crypto ====== */ + +static int +cryptodev_open(struct inode *inode, struct file *filp) +{ + struct todo_list_item *tmp, *tmp_next; + struct crypt_priv *pcr; + int i; + + pcr = kzalloc(sizeof(*pcr), GFP_KERNEL); + if (!pcr) + return -ENOMEM; + filp->private_data = pcr; + + mutex_init(&pcr->fcrypt.sem); + mutex_init(&pcr->free.lock); + mutex_init(&pcr->todo.lock); + mutex_init(&pcr->done.lock); + + INIT_LIST_HEAD(&pcr->fcrypt.list); + INIT_LIST_HEAD(&pcr->free.list); + INIT_LIST_HEAD(&pcr->todo.list); + INIT_LIST_HEAD(&pcr->done.list); + + INIT_WORK(&pcr->cryptask, cryptask_routine); + + init_waitqueue_head(&pcr->user_waiter); + + for (i = 0; i < DEF_COP_RINGSIZE; i++) { + tmp = kzalloc(sizeof(struct todo_list_item), GFP_KERNEL); + if (!tmp) + goto err_ringalloc; + pcr->itemcount++; + ddebug(2, "allocated new item at %p", tmp); + list_add(&tmp->__hook, &pcr->free.list); + } + + ddebug(2, "Cryptodev handle initialised, %d elements in queue", + DEF_COP_RINGSIZE); + return 0; + +/* In case of errors, free any memory allocated so far */ +err_ringalloc: + list_for_each_entry_safe(tmp, tmp_next, &pcr->free.list, __hook) { + list_del(&tmp->__hook); + kfree(tmp); + } + mutex_destroy(&pcr->done.lock); + mutex_destroy(&pcr->todo.lock); + mutex_destroy(&pcr->free.lock); + mutex_destroy(&pcr->fcrypt.sem); + kfree(pcr); + filp->private_data = NULL; + return -ENOMEM; +} + +static int +cryptodev_release(struct inode *inode, struct file *filp) +{ + struct crypt_priv *pcr = filp->private_data; + struct todo_list_item *item, *item_safe; + int items_freed = 0; + + if (!pcr) + return 0; + + cancel_work_sync(&pcr->cryptask); + + list_splice_tail(&pcr->todo.list, &pcr->free.list); + list_splice_tail(&pcr->done.list, &pcr->free.list); + + list_for_each_entry_safe(item, item_safe, &pcr->free.list, __hook) { + ddebug(2, "freeing item at %p", item); + list_del(&item->__hook); + kfree(item); + items_freed++; + } + + if (items_freed != pcr->itemcount) { + derr(0, "freed %d items, but %d should exist!", + items_freed, pcr->itemcount); + } + + crypto_finish_all_sessions(&pcr->fcrypt); + + mutex_destroy(&pcr->done.lock); + mutex_destroy(&pcr->todo.lock); + mutex_destroy(&pcr->free.lock); + mutex_destroy(&pcr->fcrypt.sem); + + kfree(pcr); + filp->private_data = NULL; + + ddebug(2, "Cryptodev handle deinitialised, %d elements freed", + items_freed); + return 0; +} + +static int +clonefd(struct file *filp) +{ + int ret; + ret = get_unused_fd_flags(0); + if (ret >= 0) { + get_file(filp); + fd_install(ret, filp); + } + + return ret; +} + +#ifdef ENABLE_ASYNC +/* enqueue a job for asynchronous completion + * + * returns: + * -EBUSY when there are no free queue slots left + * (and the number of slots has reached it MAX_COP_RINGSIZE) + * -EFAULT when there was a memory allocation error + * 0 on success */ +static int crypto_async_run(struct crypt_priv *pcr, struct kernel_crypt_op *kcop) +{ + struct todo_list_item *item = NULL; + + if (unlikely(kcop->cop.flags & COP_FLAG_NO_ZC)) + return -EINVAL; + + mutex_lock(&pcr->free.lock); + if (likely(!list_empty(&pcr->free.list))) { + item = list_first_entry(&pcr->free.list, + struct todo_list_item, __hook); + list_del(&item->__hook); + } else if (pcr->itemcount < MAX_COP_RINGSIZE) { + pcr->itemcount++; + } else { + mutex_unlock(&pcr->free.lock); + return -EBUSY; + } + mutex_unlock(&pcr->free.lock); + + if (unlikely(!item)) { + item = kzalloc(sizeof(struct todo_list_item), GFP_KERNEL); + if (unlikely(!item)) + return -EFAULT; + dinfo(1, "increased item count to %d", pcr->itemcount); + } + + memcpy(&item->kcop, kcop, sizeof(struct kernel_crypt_op)); + + mutex_lock(&pcr->todo.lock); + list_add_tail(&item->__hook, &pcr->todo.list); + mutex_unlock(&pcr->todo.lock); + + queue_work(cryptodev_wq, &pcr->cryptask); + return 0; +} + +/* get the first completed job from the "done" queue + * + * returns: + * -EBUSY if no completed jobs are ready (yet) + * the return value of crypto_run() otherwise */ +static int crypto_async_fetch(struct crypt_priv *pcr, + struct kernel_crypt_op *kcop) +{ + struct todo_list_item *item; + int retval; + + mutex_lock(&pcr->done.lock); + if (list_empty(&pcr->done.list)) { + mutex_unlock(&pcr->done.lock); + return -EBUSY; + } + item = list_first_entry(&pcr->done.list, struct todo_list_item, __hook); + list_del(&item->__hook); + mutex_unlock(&pcr->done.lock); + + memcpy(kcop, &item->kcop, sizeof(struct kernel_crypt_op)); + retval = item->result; + + mutex_lock(&pcr->free.lock); + list_add_tail(&item->__hook, &pcr->free.list); + mutex_unlock(&pcr->free.lock); + + /* wake for POLLOUT */ + wake_up_interruptible(&pcr->user_waiter); + + return retval; +} +#endif + +/* this function has to be called from process context */ +static int fill_kcop_from_cop(struct kernel_crypt_op *kcop, struct fcrypt *fcr) +{ + struct crypt_op *cop = &kcop->cop; + struct csession *ses_ptr; + int rc; + + /* this also enters ses_ptr->sem */ + ses_ptr = crypto_get_session_by_sid(fcr, cop->ses); + if (unlikely(!ses_ptr)) { + derr(1, "invalid session ID=0x%08X", cop->ses); + return -EINVAL; + } + kcop->ivlen = cop->iv ? ses_ptr->cdata.ivsize : 0; + kcop->digestsize = 0; /* will be updated during operation */ + + crypto_put_session(ses_ptr); + + kcop->task = current; + kcop->mm = current->mm; + + if (cop->iv) { + rc = copy_from_user(kcop->iv, cop->iv, kcop->ivlen); + if (unlikely(rc)) { + derr(1, "error copying IV (%d bytes), copy_from_user returned %d for address %p", + kcop->ivlen, rc, cop->iv); + return -EFAULT; + } + } + + return 0; +} + +/* this function has to be called from process context */ +static int fill_cop_from_kcop(struct kernel_crypt_op *kcop, struct fcrypt *fcr) +{ + int ret; + + if (kcop->digestsize) { + ret = copy_to_user(kcop->cop.mac, + kcop->hash_output, kcop->digestsize); + if (unlikely(ret)) + return -EFAULT; + } + if (kcop->ivlen && kcop->cop.flags & COP_FLAG_WRITE_IV) { + ret = copy_to_user(kcop->cop.iv, + kcop->iv, kcop->ivlen); + if (unlikely(ret)) + return -EFAULT; + } + return 0; +} + +static int kcop_from_user(struct kernel_crypt_op *kcop, + struct fcrypt *fcr, void __user *arg) +{ + if (unlikely(copy_from_user(&kcop->cop, arg, sizeof(kcop->cop)))) + return -EFAULT; + + return fill_kcop_from_cop(kcop, fcr); +} + +static int kcop_to_user(struct kernel_crypt_op *kcop, + struct fcrypt *fcr, void __user *arg) +{ + int ret; + + ret = fill_cop_from_kcop(kcop, fcr); + if (unlikely(ret)) { + derr(1, "Error in fill_cop_from_kcop"); + return ret; + } + + if (unlikely(copy_to_user(arg, &kcop->cop, sizeof(kcop->cop)))) { + derr(1, "Cannot copy to userspace"); + return -EFAULT; + } + return 0; +} + +static inline void tfm_info_to_alg_info(struct alg_info *dst, struct crypto_tfm *tfm) +{ + snprintf(dst->cra_name, CRYPTODEV_MAX_ALG_NAME, + "%s", crypto_tfm_alg_name(tfm)); + snprintf(dst->cra_driver_name, CRYPTODEV_MAX_ALG_NAME, + "%s", crypto_tfm_alg_driver_name(tfm)); +} + +#ifndef CRYPTO_ALG_KERN_DRIVER_ONLY +static unsigned int is_known_accelerated(struct crypto_tfm *tfm) +{ + const char *name = crypto_tfm_alg_driver_name(tfm); + + if (name == NULL) + return 1; /* assume accelerated */ + + /* look for known crypto engine names */ + if (strstr(name, "-talitos") || + !strncmp(name, "mv-", 3) || + !strncmp(name, "atmel-", 6) || + strstr(name, "geode") || + strstr(name, "hifn") || + strstr(name, "-ixp4xx") || + strstr(name, "-omap") || + strstr(name, "-picoxcell") || + strstr(name, "-s5p") || + strstr(name, "-ppc4xx") || + strstr(name, "-caam") || + strstr(name, "-n2")) + return 1; + + return 0; +} +#endif + +static int get_session_info(struct fcrypt *fcr, struct session_info_op *siop) +{ + struct csession *ses_ptr; + struct crypto_tfm *tfm; + + /* this also enters ses_ptr->sem */ + ses_ptr = crypto_get_session_by_sid(fcr, siop->ses); + if (unlikely(!ses_ptr)) { + derr(1, "invalid session ID=0x%08X", siop->ses); + return -EINVAL; + } + + siop->flags = 0; + + if (ses_ptr->cdata.init) { + if (ses_ptr->cdata.aead == 0) + tfm = cryptodev_crypto_blkcipher_tfm(ses_ptr->cdata.async.s); + else + tfm = crypto_aead_tfm(ses_ptr->cdata.async.as); + tfm_info_to_alg_info(&siop->cipher_info, tfm); +#ifdef CRYPTO_ALG_KERN_DRIVER_ONLY + if (tfm->__crt_alg->cra_flags & CRYPTO_ALG_KERN_DRIVER_ONLY) + siop->flags |= SIOP_FLAG_KERNEL_DRIVER_ONLY; +#else + if (is_known_accelerated(tfm)) + siop->flags |= SIOP_FLAG_KERNEL_DRIVER_ONLY; +#endif + } + if (ses_ptr->hdata.init) { + tfm = crypto_ahash_tfm(ses_ptr->hdata.async.s); + tfm_info_to_alg_info(&siop->hash_info, tfm); +#ifdef CRYPTO_ALG_KERN_DRIVER_ONLY + if (tfm->__crt_alg->cra_flags & CRYPTO_ALG_KERN_DRIVER_ONLY) + siop->flags |= SIOP_FLAG_KERNEL_DRIVER_ONLY; +#else + if (is_known_accelerated(tfm)) + siop->flags |= SIOP_FLAG_KERNEL_DRIVER_ONLY; +#endif + } + + siop->alignmask = ses_ptr->alignmask; + + crypto_put_session(ses_ptr); + return 0; +} + +static long +cryptodev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg_) +{ + void __user *arg = (void __user *)arg_; + int __user *p = arg; + struct session_op sop; + struct kernel_crypt_op kcop; + struct kernel_crypt_auth_op kcaop; + struct crypt_priv *pcr = filp->private_data; + struct fcrypt *fcr; + struct session_info_op siop; +#ifdef CIOCCPHASH + struct cphash_op cphop; +#endif + uint32_t ses; + int ret, fd; + + if (unlikely(!pcr)) + BUG(); + + fcr = &pcr->fcrypt; + + switch (cmd) { + case CIOCASYMFEAT: + return put_user(0, p); + case CRIOGET: + fd = clonefd(filp); + ret = put_user(fd, p); + if (unlikely(ret)) { +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 17, 0)) + sys_close(fd); +#else + ksys_close(fd); +#endif + return ret; + } + return ret; + case CIOCGSESSION: + if (unlikely(copy_from_user(&sop, arg, sizeof(sop)))) + return -EFAULT; + + ret = crypto_create_session(fcr, &sop); + if (unlikely(ret)) + return ret; + ret = copy_to_user(arg, &sop, sizeof(sop)); + if (unlikely(ret)) { + crypto_finish_session(fcr, sop.ses); + return -EFAULT; + } + return ret; + case CIOCFSESSION: + ret = get_user(ses, (uint32_t __user *)arg); + if (unlikely(ret)) + return ret; + ret = crypto_finish_session(fcr, ses); + return ret; + case CIOCGSESSINFO: + if (unlikely(copy_from_user(&siop, arg, sizeof(siop)))) + return -EFAULT; + + ret = get_session_info(fcr, &siop); + if (unlikely(ret)) + return ret; + return copy_to_user(arg, &siop, sizeof(siop)); +#ifdef CIOCCPHASH + case CIOCCPHASH: + if (unlikely(copy_from_user(&cphop, arg, sizeof(cphop)))) + return -EFAULT; + return crypto_copy_hash_state(fcr, cphop.dst_ses, cphop.src_ses); +#endif /* CIOCPHASH */ + case CIOCCRYPT: + if (unlikely(ret = kcop_from_user(&kcop, fcr, arg))) { + dwarning(1, "Error copying from user"); + return ret; + } + + ret = crypto_run(fcr, &kcop); + if (unlikely(ret)) { + dwarning(1, "Error in crypto_run"); + return ret; + } + + return kcop_to_user(&kcop, fcr, arg); + case CIOCAUTHCRYPT: + if (unlikely(ret = kcaop_from_user(&kcaop, fcr, arg))) { + dwarning(1, "Error copying from user"); + return ret; + } + + ret = crypto_auth_run(fcr, &kcaop); + if (unlikely(ret)) { + dwarning(1, "Error in crypto_auth_run"); + return ret; + } + return kcaop_to_user(&kcaop, fcr, arg); +#ifdef ENABLE_ASYNC + case CIOCASYNCCRYPT: + if (unlikely(ret = kcop_from_user(&kcop, fcr, arg))) + return ret; + + return crypto_async_run(pcr, &kcop); + case CIOCASYNCFETCH: + ret = crypto_async_fetch(pcr, &kcop); + if (unlikely(ret)) + return ret; + + return kcop_to_user(&kcop, fcr, arg); +#endif + default: + return -EINVAL; + } +} + +/* compatibility code for 32bit userlands */ +#ifdef CONFIG_COMPAT + +static inline void +compat_to_session_op(struct compat_session_op *compat, struct session_op *sop) +{ + sop->cipher = compat->cipher; + sop->mac = compat->mac; + sop->keylen = compat->keylen; + + sop->key = compat_ptr(compat->key); + sop->mackeylen = compat->mackeylen; + sop->mackey = compat_ptr(compat->mackey); + sop->ses = compat->ses; +} + +static inline void +session_op_to_compat(struct session_op *sop, struct compat_session_op *compat) +{ + compat->cipher = sop->cipher; + compat->mac = sop->mac; + compat->keylen = sop->keylen; + + compat->key = ptr_to_compat(sop->key); + compat->mackeylen = sop->mackeylen; + compat->mackey = ptr_to_compat(sop->mackey); + compat->ses = sop->ses; +} + +static inline void +compat_to_crypt_op(struct compat_crypt_op *compat, struct crypt_op *cop) +{ + cop->ses = compat->ses; + cop->op = compat->op; + cop->flags = compat->flags; + cop->len = compat->len; + + cop->src = compat_ptr(compat->src); + cop->dst = compat_ptr(compat->dst); + cop->mac = compat_ptr(compat->mac); + cop->iv = compat_ptr(compat->iv); +} + +static inline void +crypt_op_to_compat(struct crypt_op *cop, struct compat_crypt_op *compat) +{ + compat->ses = cop->ses; + compat->op = cop->op; + compat->flags = cop->flags; + compat->len = cop->len; + + compat->src = ptr_to_compat(cop->src); + compat->dst = ptr_to_compat(cop->dst); + compat->mac = ptr_to_compat(cop->mac); + compat->iv = ptr_to_compat(cop->iv); +} + +static int compat_kcop_from_user(struct kernel_crypt_op *kcop, + struct fcrypt *fcr, void __user *arg) +{ + struct compat_crypt_op compat_cop; + + if (unlikely(copy_from_user(&compat_cop, arg, sizeof(compat_cop)))) + return -EFAULT; + compat_to_crypt_op(&compat_cop, &kcop->cop); + + return fill_kcop_from_cop(kcop, fcr); +} + +static int compat_kcop_to_user(struct kernel_crypt_op *kcop, + struct fcrypt *fcr, void __user *arg) +{ + int ret; + struct compat_crypt_op compat_cop; + + ret = fill_cop_from_kcop(kcop, fcr); + if (unlikely(ret)) { + dwarning(1, "Error in fill_cop_from_kcop"); + return ret; + } + crypt_op_to_compat(&kcop->cop, &compat_cop); + + if (unlikely(copy_to_user(arg, &compat_cop, sizeof(compat_cop)))) { + dwarning(1, "Error copying to user"); + return -EFAULT; + } + return 0; +} + +static long +cryptodev_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg_) +{ + void __user *arg = (void __user *)arg_; + struct crypt_priv *pcr = file->private_data; + struct fcrypt *fcr; + struct session_op sop; + struct compat_session_op compat_sop; + struct kernel_crypt_op kcop; + int ret; + + if (unlikely(!pcr)) + BUG(); + + fcr = &pcr->fcrypt; + + switch (cmd) { + case CIOCASYMFEAT: + case CRIOGET: + case CIOCFSESSION: + case CIOCGSESSINFO: + return cryptodev_ioctl(file, cmd, arg_); + + case COMPAT_CIOCGSESSION: + if (unlikely(copy_from_user(&compat_sop, arg, + sizeof(compat_sop)))) + return -EFAULT; + compat_to_session_op(&compat_sop, &sop); + + ret = crypto_create_session(fcr, &sop); + if (unlikely(ret)) + return ret; + + session_op_to_compat(&sop, &compat_sop); + ret = copy_to_user(arg, &compat_sop, sizeof(compat_sop)); + if (unlikely(ret)) { + crypto_finish_session(fcr, sop.ses); + return -EFAULT; + } + return ret; + + case COMPAT_CIOCCRYPT: + ret = compat_kcop_from_user(&kcop, fcr, arg); + if (unlikely(ret)) + return ret; + + ret = crypto_run(fcr, &kcop); + if (unlikely(ret)) + return ret; + + return compat_kcop_to_user(&kcop, fcr, arg); +#ifdef ENABLE_ASYNC + case COMPAT_CIOCASYNCCRYPT: + if (unlikely(ret = compat_kcop_from_user(&kcop, fcr, arg))) + return ret; + + return crypto_async_run(pcr, &kcop); + case COMPAT_CIOCASYNCFETCH: + ret = crypto_async_fetch(pcr, &kcop); + if (unlikely(ret)) + return ret; + + return compat_kcop_to_user(&kcop, fcr, arg); +#endif + default: + return -EINVAL; + } +} + +#endif /* CONFIG_COMPAT */ + +static unsigned int cryptodev_poll(struct file *file, poll_table *wait) +{ + struct crypt_priv *pcr = file->private_data; + unsigned int ret = 0; + + poll_wait(file, &pcr->user_waiter, wait); + + if (!list_empty_careful(&pcr->done.list)) + ret |= POLLIN | POLLRDNORM; + if (!list_empty_careful(&pcr->free.list) || pcr->itemcount < MAX_COP_RINGSIZE) + ret |= POLLOUT | POLLWRNORM; + + return ret; +} + +static const struct file_operations cryptodev_fops = { + .owner = THIS_MODULE, + .open = cryptodev_open, + .release = cryptodev_release, + .unlocked_ioctl = cryptodev_ioctl, +#ifdef CONFIG_COMPAT + .compat_ioctl = cryptodev_compat_ioctl, +#endif /* CONFIG_COMPAT */ + .poll = cryptodev_poll, +}; + +static struct miscdevice cryptodev = { + .minor = MISC_DYNAMIC_MINOR, + .name = "crypto", + .fops = &cryptodev_fops, + .mode = S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH|S_IWOTH, +}; + +static int __init +cryptodev_register(void) +{ + int rc; + + rc = misc_register(&cryptodev); + if (unlikely(rc)) { + pr_err(PFX "registration of /dev/crypto failed\n"); + return rc; + } + + return 0; +} + +static void __exit +cryptodev_deregister(void) +{ + misc_deregister(&cryptodev); +} + +/* ====== Module init/exit ====== */ +static struct ctl_table verbosity_ctl_dir[] = { + { + .procname = "cryptodev_verbosity", + .data = &cryptodev_verbosity, + .maxlen = sizeof(int), + .mode = 0644, + .proc_handler = proc_dointvec, + }, + {}, +}; + +static struct ctl_table verbosity_ctl_root[] = { + { + .procname = "ioctl", + .mode = 0555, + .child = verbosity_ctl_dir, + }, + {}, +}; +static struct ctl_table_header *verbosity_sysctl_header; +static int __init init_cryptodev(void) +{ + int rc; + + cryptodev_wq = create_workqueue("cryptodev_queue"); + if (unlikely(!cryptodev_wq)) { + pr_err(PFX "failed to allocate the cryptodev workqueue\n"); + return -EFAULT; + } + + rc = cryptodev_register(); + if (unlikely(rc)) { + destroy_workqueue(cryptodev_wq); + return rc; + } + + verbosity_sysctl_header = register_sysctl_table(verbosity_ctl_root); + + pr_info(PFX "driver %s loaded.\n", VERSION); + + return 0; +} + +static void __exit exit_cryptodev(void) +{ + flush_workqueue(cryptodev_wq); + destroy_workqueue(cryptodev_wq); + + if (verbosity_sysctl_header) + unregister_sysctl_table(verbosity_sysctl_header); + + cryptodev_deregister(); + pr_info(PFX "driver unloaded.\n"); +} + +module_init(init_cryptodev); +module_exit(exit_cryptodev); + diff --git a/drivers/cryptodev-linux-master/lib/Makefile b/drivers/cryptodev-linux-master/lib/Makefile new file mode 100644 index 00000000..3bedc341 --- /dev/null +++ b/drivers/cryptodev-linux-master/lib/Makefile @@ -0,0 +1,15 @@ +CFLAGS=-g -O2 -Wall + +all: benchmark + +benchmark: main.c libthreshold.a + gcc $(CFLAGS) -DDEBUG -o $@ $^ -lssl -lcrypto libthreshold.a + +.o: + gcc $(CCFLAGS) -c $< -o $@ + +libthreshold.a: benchmark.o hash.o threshold.o combo.o + ar rcs $@ $^ + +clean: + rm -f *.o *~ benchmark libthreshold.a diff --git a/drivers/cryptodev-linux-master/lib/benchmark.c b/drivers/cryptodev-linux-master/lib/benchmark.c new file mode 100644 index 00000000..a04efbc4 --- /dev/null +++ b/drivers/cryptodev-linux-master/lib/benchmark.c @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2011 Free Software Foundation, Inc. + * + * This file is part of GnuTLS. + * + * GnuTLS is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * GnuTLS is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include +#include +#include "benchmark.h" + +int benchmark_must_finish = 0; + +static void +alarm_handler (int signo) +{ + benchmark_must_finish = 1; +} + +int start_benchmark(struct benchmark_st * st) +{ + int ret; + struct itimerval timer; + + memset(st, 0, sizeof(*st)); + + st->old_handler = signal (SIGPROF, alarm_handler); + + ret = gettimeofday (&st->start, NULL); + if (ret < 0) { + perror("gettimeofday"); + return -1; + } + + benchmark_must_finish = 0; + + memset(&timer, 0, sizeof(timer)); + timer.it_value.tv_sec = 0; + timer.it_value.tv_usec = 100*1000; + + ret = setitimer(ITIMER_PROF, &timer, NULL); + if (ret < 0) { + perror("setitimer"); + return -1; + } + + return 0; +} + +/* Returns -1 on error or 0 on success. + * elapsed: the elapsed time in milliseconds + */ +int stop_benchmark(struct benchmark_st * st, unsigned long * elapsed) +{ + unsigned long msecs; + struct timeval stop; + int ret; + + signal(SIGPROF, st->old_handler); + + ret = gettimeofday (&stop, NULL); + if (ret < 0) + return -1; + + msecs = (stop.tv_sec * 1000 + stop.tv_usec / 1000 - + (st->start.tv_sec * 1000 + st->start.tv_usec / (1000))); + + if (elapsed) *elapsed = msecs; + + return 0; +} + diff --git a/drivers/cryptodev-linux-master/lib/benchmark.h b/drivers/cryptodev-linux-master/lib/benchmark.h new file mode 100644 index 00000000..173552ec --- /dev/null +++ b/drivers/cryptodev-linux-master/lib/benchmark.h @@ -0,0 +1,18 @@ +#include +#include +#include +#include + +typedef void (*sighandler_t)(int); + +struct benchmark_st +{ + struct timeval start; + sighandler_t old_handler; +}; + +extern int benchmark_must_finish; + +int start_benchmark(struct benchmark_st * st); +int stop_benchmark(struct benchmark_st * st, unsigned long * elapsed); + diff --git a/drivers/cryptodev-linux-master/lib/combo.c b/drivers/cryptodev-linux-master/lib/combo.c new file mode 100644 index 00000000..b26da0a5 --- /dev/null +++ b/drivers/cryptodev-linux-master/lib/combo.c @@ -0,0 +1,171 @@ +/* + * Demo on how to use /dev/crypto device for ciphering. + * + * Placed under public domain. + * + */ +#include +#include +#include +#include +#include +#include +#include "benchmark.h" +#include "hash.h" + +int aead_ctx_init(struct cryptodev_ctx* ctx, int cipher, int hash, void* key, int key_size, int cfd) +{ +#ifdef CIOCGSESSINFO + struct session_info_op siop; +#endif + + memset(ctx, 0, sizeof(*ctx)); + ctx->cfd = cfd; + + ctx->sess.mac = hash; + ctx->sess.cipher = cipher; + ctx->sess.key = key; + ctx->sess.keylen = key_size; + + if (ioctl(ctx->cfd, CIOCGSESSION, &ctx->sess)) { + perror("ioctl(CIOCGSESSION)"); + return -1; + } + +#ifdef CIOCGSESSINFO + memset(&siop, 0, sizeof(siop)); + siop.ses = ctx->sess.ses; + if (ioctl(ctx->cfd, CIOCGSESSINFO, &siop)) { + perror("ioctl(CIOCGSESSINFO)"); + return -1; + } +#ifdef DEBUG + printf("Got %s-%s with drivers %s and %s\n", + siop.cipher_info.cra_name, siop.hash_info.cra_name, + siop.cipher_info.cra_driver_name, siop.hash_info.cra_driver_name); +#endif + /*printf("Alignmask is %x\n", (unsigned int)siop.alignmask);*/ + ctx->alignmask = siop.alignmask; +#endif + return 0; +} + +void aead_ctx_deinit(struct cryptodev_ctx* ctx) +{ + if (ioctl(ctx->cfd, CIOCFSESSION, &ctx->sess.ses)) { + perror("ioctl(CIOCFSESSION)"); + } +} + +int +aead_encrypt(struct cryptodev_ctx* ctx, const void* iv, const void* plaintext, void* ciphertext, size_t size, void* digest) +{ + struct crypt_auth_op cryp; + + memset(&cryp, 0, sizeof(cryp)); + + /* Encrypt data.in to data.encrypted */ + cryp.ses = ctx->sess.ses; + cryp.len = size; + cryp.iv = (void*)iv; + cryp.iv_len = 16; + cryp.src = (void*)plaintext; + cryp.dst = (void*)ciphertext; + cryp.flags = COP_FLAG_AEAD_TLS_TYPE; + + if (ioctl(ctx->cfd, CIOCAUTHCRYPT, &cryp)) { + perror("ioctl(CIOCAUTHCRYPT)"); + return -1; + } + + return 0; +} + +static const int sizes[] = {64, 256, 512, 1024, 4096, 16*1024}; + + +int aead_test(int cipher, int mac, void* ukey, int ukey_size, + void* user_ctx, void (*user_combo)(void* user_ctx, void* plaintext, void* ciphertext, int size, void* res)) +{ + int cfd = -1, i, ret; + struct cryptodev_ctx ctx; + uint8_t digest[AALG_MAX_RESULT_LEN]; + char text[16*1024]; + char ctext[16*1024]; + char iv[16]; + unsigned long elapsed, counted; + double t1, t2; + struct benchmark_st bst; + + /* Open the crypto device */ + cfd = open("/dev/crypto", O_RDWR, 0); + if (cfd < 0) { + perror("open(/dev/crypto)"); + return -1; + } + + aead_ctx_init(&ctx, cipher, mac, ukey, ukey_size, cfd); + + for (i=0;i t2) { + ret = sizes[i]; + goto finish; + } + } + + ret = -1; +finish: + aead_ctx_deinit(&ctx); + + /* Close the original descriptor */ + if (close(cfd)) { + perror("close(cfd)"); + return 1; + } + return ret; +} diff --git a/drivers/cryptodev-linux-master/lib/hash.c b/drivers/cryptodev-linux-master/lib/hash.c new file mode 100644 index 00000000..386fd7e8 --- /dev/null +++ b/drivers/cryptodev-linux-master/lib/hash.c @@ -0,0 +1,161 @@ +/* + * Demo on how to use /dev/crypto device for ciphering. + * + * Placed under public domain. + * + */ +#include +#include +#include +#include +#include +#include +#include "hash.h" +#include "benchmark.h" + +int hash_ctx_init(struct cryptodev_ctx* ctx, int hash, int cfd) +{ +#ifdef CIOCGSESSINFO + struct session_info_op siop; +#endif + + memset(ctx, 0, sizeof(*ctx)); + ctx->cfd = cfd; + + ctx->sess.mac = hash; + + if (ioctl(ctx->cfd, CIOCGSESSION, &ctx->sess)) { + perror("ioctl(CIOCGSESSION)"); + return -1; + } + +#ifdef CIOCGSESSINFO + memset(&siop, 0, sizeof(siop)); + siop.ses = ctx->sess.ses; + if (ioctl(ctx->cfd, CIOCGSESSINFO, &siop)) { + perror("ioctl(CIOCGSESSINFO)"); + return -1; + } +#ifdef DEBUG + printf("Got %s with driver %s\n", + siop.hash_info.cra_name, siop.hash_info.cra_driver_name); +#endif + /*printf("Alignmask is %x\n", (unsigned int)siop.alignmask);*/ + ctx->alignmask = siop.alignmask; +#endif + return 0; +} + +void hash_ctx_deinit(struct cryptodev_ctx* ctx) +{ + if (ioctl(ctx->cfd, CIOCFSESSION, &ctx->sess.ses)) { + perror("ioctl(CIOCFSESSION)"); + } +} + +int +hash(struct cryptodev_ctx* ctx, const void* text, size_t size, void* digest) +{ + struct crypt_op cryp; + + memset(&cryp, 0, sizeof(cryp)); + + /* Encrypt data.in to data.encrypted */ + cryp.ses = ctx->sess.ses; + cryp.len = size; + cryp.src = (void*)text; + cryp.mac = digest; + if (ioctl(ctx->cfd, CIOCCRYPT, &cryp)) { + perror("ioctl(CIOCCRYPT)"); + return -1; + } + + return 0; +} + +static const int sizes[] = {64, 256, 512, 1024, 4096, 16*1024}; + +/* Worst case running time: around 1.2 secs + */ +int hash_test(int algo, void (*user_hash)(void* text, int size, void* res)) +{ + int cfd = -1, i, ret; + struct cryptodev_ctx ctx; + uint8_t digest[AALG_MAX_RESULT_LEN]; + char text[16*1024]; + unsigned long elapsed, counted; + double t1, t2; + struct benchmark_st bst; + + /* Open the crypto device */ + cfd = open("/dev/crypto", O_RDWR, 0); + if (cfd < 0) { + perror("open(/dev/crypto)"); + return -1; + } + + hash_ctx_init(&ctx, algo, cfd); + + for (i=0;i t2) { + ret = sizes[i]; + goto finish; + } +#ifdef DEBUG + printf("%d: kernel: %.4f bytes/msec, user: %.4f bytes/msec\n", sizes[i], t1, t2); +#endif + } + + ret = -1; +finish: + hash_ctx_deinit(&ctx); + + /* Close the original descriptor */ + if (close(cfd)) { + perror("close(cfd)"); + return 1; + } + return ret; +} + diff --git a/drivers/cryptodev-linux-master/lib/hash.h b/drivers/cryptodev-linux-master/lib/hash.h new file mode 100644 index 00000000..7c32ceaa --- /dev/null +++ b/drivers/cryptodev-linux-master/lib/hash.h @@ -0,0 +1,20 @@ +#ifndef HASH_H +# define HASH_H + +#include + +struct cryptodev_ctx { + int cfd; + struct session_op sess; + uint16_t alignmask; +}; + +int hash_ctx_init(struct cryptodev_ctx* ctx, int hash, int cfd); +void hash_ctx_deinit(struct cryptodev_ctx* ctx); +int hash(struct cryptodev_ctx* ctx, const void* text, size_t size, void* digest); +int hash_test(int algo, void (*user_hash)(void* text, int size, void* res)); + +int aead_test(int cipher, int mac, void* ukey, int ukey_size, + void* user_ctx, void (*user_combo)(void* user_ctx, void* plaintext, void* ciphertext, int size, void* res)); + +#endif diff --git a/drivers/cryptodev-linux-master/lib/main.c b/drivers/cryptodev-linux-master/lib/main.c new file mode 100644 index 00000000..443779af --- /dev/null +++ b/drivers/cryptodev-linux-master/lib/main.c @@ -0,0 +1,28 @@ +/* + * Demo on how to use /dev/crypto device for ciphering. + * + * Placed under public domain. + * + */ +#include +#include +#include +#include +#include +#include +#include "threshold.h" + +int main() +{ +int ret; + + ret = get_sha1_threshold(); + if (ret > 0) + printf("SHA1 in kernel outperforms user-space after %d input bytes\n", ret); + + ret = get_aes_sha1_threshold(); + if (ret > 0) + printf("AES-SHA1 in kernel outperforms user-space after %d input bytes\n", ret); + + return 0; +} diff --git a/drivers/cryptodev-linux-master/lib/threshold.c b/drivers/cryptodev-linux-master/lib/threshold.c new file mode 100644 index 00000000..b002d58e --- /dev/null +++ b/drivers/cryptodev-linux-master/lib/threshold.c @@ -0,0 +1,61 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "hash.h" +#include "threshold.h" + +void sha_hash(void* text, int size, void* digest) +{ +SHA_CTX ctx; + + SHA_Init(&ctx); + + SHA_Update(&ctx, text, size); + + SHA_Final(digest, &ctx); +} + +void aes_sha_combo(void* ctx, void* plaintext, void* ciphertext, int size, void* tag) +{ +uint8_t iv[16]; +AES_KEY* key = ctx; +HMAC_CTX hctx; +unsigned int rlen = 20; + + HMAC_CTX_init(&hctx); + HMAC_Init_ex(&hctx, iv, 16, EVP_sha1(), NULL); + + HMAC_Update(&hctx, plaintext, size); + + HMAC_Final(&hctx, tag, &rlen); + HMAC_CTX_cleanup(&hctx); + + AES_cbc_encrypt(plaintext, ciphertext, size, key, iv, 1); +} + +int get_sha1_threshold() +{ + return hash_test(CRYPTO_SHA1, sha_hash); +} + +int get_aes_sha1_threshold() +{ +AES_KEY key; +uint8_t ukey[16]; + + ENGINE_load_builtin_engines(); + ENGINE_register_all_complete(); + + memset(ukey, 0xaf, sizeof(ukey)); + AES_set_encrypt_key(ukey, 16*8, &key); + + return aead_test(CRYPTO_AES_CBC, CRYPTO_SHA1, ukey, 16, &key, aes_sha_combo); +} + diff --git a/drivers/cryptodev-linux-master/lib/threshold.h b/drivers/cryptodev-linux-master/lib/threshold.h new file mode 100644 index 00000000..6c11019b --- /dev/null +++ b/drivers/cryptodev-linux-master/lib/threshold.h @@ -0,0 +1,10 @@ +/* Return the number of bytes after which the + * kernel operation is more efficient to use. + * If return value is -1, then kernel operation + * cannot, or shouldn't be used, because it is always + * slower. + * + * Running time ~= 1.2 seconds per call. + */ +int get_sha1_threshold(); +int get_aes_sha1_threshold(); diff --git a/drivers/cryptodev-linux-master/main.c b/drivers/cryptodev-linux-master/main.c new file mode 100644 index 00000000..b2ef5f7e --- /dev/null +++ b/drivers/cryptodev-linux-master/main.c @@ -0,0 +1,269 @@ +/* + * Driver for /dev/crypto device (aka CryptoDev) + * + * Copyright (c) 2004 Michal Ludvig , SuSE Labs + * Copyright (c) 2009-2013 Nikos Mavrogiannopoulos + * + * This file is part of linux cryptodev. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +/* + * Device /dev/crypto provides an interface for + * accessing kernel CryptoAPI algorithms (ciphers, + * hashes) from userspace programs. + * + * /dev/crypto interface was originally introduced in + * OpenBSD and this module attempts to keep the API. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cryptodev_int.h" +#include "zc.h" +#include "cryptlib.h" +#include "version.h" + +/* This file contains the traditional operations of encryption + * and hashing of /dev/crypto. + */ + +static int +hash_n_crypt(struct csession *ses_ptr, struct crypt_op *cop, + struct scatterlist *src_sg, struct scatterlist *dst_sg, + uint32_t len) +{ + int ret; + + /* Always hash before encryption and after decryption. Maybe + * we should introduce a flag to switch... TBD later on. + */ + if (cop->op == COP_ENCRYPT) { + if (ses_ptr->hdata.init != 0) { + ret = cryptodev_hash_update(&ses_ptr->hdata, + src_sg, len); + if (unlikely(ret)) + goto out_err; + } + if (ses_ptr->cdata.init != 0) { + ret = cryptodev_cipher_encrypt(&ses_ptr->cdata, + src_sg, dst_sg, len); + + if (unlikely(ret)) + goto out_err; + } + } else { + if (ses_ptr->cdata.init != 0) { + ret = cryptodev_cipher_decrypt(&ses_ptr->cdata, + src_sg, dst_sg, len); + + if (unlikely(ret)) + goto out_err; + } + + if (ses_ptr->hdata.init != 0) { + ret = cryptodev_hash_update(&ses_ptr->hdata, + dst_sg, len); + if (unlikely(ret)) + goto out_err; + } + } + return 0; +out_err: + derr(0, "CryptoAPI failure: %d", ret); + return ret; +} + +/* This is the main crypto function - feed it with plaintext + and get a ciphertext (or vice versa :-) */ +static int +__crypto_run_std(struct csession *ses_ptr, struct crypt_op *cop) +{ + char *data; + char __user *src, *dst; + struct scatterlist sg; + size_t nbytes, bufsize; + int ret = 0; + + nbytes = cop->len; + data = (char *)__get_free_page(GFP_KERNEL); + + if (unlikely(!data)) { + derr(1, "Error getting free page."); + return -ENOMEM; + } + + bufsize = PAGE_SIZE < nbytes ? PAGE_SIZE : nbytes; + + src = cop->src; + dst = cop->dst; + + while (nbytes > 0) { + size_t current_len = nbytes > bufsize ? bufsize : nbytes; + + if (unlikely(copy_from_user(data, src, current_len))) { + derr(1, "Error copying %zu bytes from user address %p.", current_len, src); + ret = -EFAULT; + break; + } + + sg_init_one(&sg, data, current_len); + + ret = hash_n_crypt(ses_ptr, cop, &sg, &sg, current_len); + + if (unlikely(ret)) { + derr(1, "hash_n_crypt failed."); + break; + } + + if (ses_ptr->cdata.init != 0) { + if (unlikely(copy_to_user(dst, data, current_len))) { + derr(1, "could not copy to user."); + ret = -EFAULT; + break; + } + } + + dst += current_len; + nbytes -= current_len; + src += current_len; + } + + free_page((unsigned long)data); + return ret; +} + + + +/* This is the main crypto function - zero-copy edition */ +static int +__crypto_run_zc(struct csession *ses_ptr, struct kernel_crypt_op *kcop) +{ + struct scatterlist *src_sg, *dst_sg; + struct crypt_op *cop = &kcop->cop; + int ret = 0; + + ret = get_userbuf(ses_ptr, cop->src, cop->len, cop->dst, cop->len, + kcop->task, kcop->mm, &src_sg, &dst_sg); + if (unlikely(ret)) { + derr(1, "Error getting user pages. Falling back to non zero copy."); + return __crypto_run_std(ses_ptr, cop); + } + + ret = hash_n_crypt(ses_ptr, cop, src_sg, dst_sg, cop->len); + + release_user_pages(ses_ptr); + return ret; +} + +int crypto_run(struct fcrypt *fcr, struct kernel_crypt_op *kcop) +{ + struct csession *ses_ptr; + struct crypt_op *cop = &kcop->cop; + int ret = 0; + + if (unlikely(cop->op != COP_ENCRYPT && cop->op != COP_DECRYPT)) { + ddebug(1, "invalid operation op=%u", cop->op); + return -EINVAL; + } + + /* this also enters ses_ptr->sem */ + ses_ptr = crypto_get_session_by_sid(fcr, cop->ses); + if (unlikely(!ses_ptr)) { + derr(1, "invalid session ID=0x%08X", cop->ses); + return -EINVAL; + } + + if (ses_ptr->hdata.init != 0 && (cop->flags == 0 || cop->flags & COP_FLAG_RESET)) { + ret = cryptodev_hash_reset(&ses_ptr->hdata); + if (unlikely(ret)) { + derr(1, "error in cryptodev_hash_reset()"); + goto out_unlock; + } + } + + if (ses_ptr->cdata.init != 0) { + int blocksize = ses_ptr->cdata.blocksize; + + if (unlikely(cop->len % blocksize)) { + derr(1, "data size (%u) isn't a multiple of block size (%u)", + cop->len, blocksize); + ret = -EINVAL; + goto out_unlock; + } + + cryptodev_cipher_set_iv(&ses_ptr->cdata, kcop->iv, + min(ses_ptr->cdata.ivsize, kcop->ivlen)); + } + + if (likely(cop->len)) { + if(!(cop->flags & COP_FLAG_ZC)){ + if (!(cop->flags & COP_FLAG_NO_ZC)) { + if (unlikely(ses_ptr->alignmask && !IS_ALIGNED((unsigned long)cop->src, ses_ptr->alignmask + 1))) { + dwarning(2, "source address %p is not %d byte aligned - disabling zero copy", + cop->src, ses_ptr->alignmask + 1); + cop->flags |= COP_FLAG_NO_ZC; + } + + if (unlikely(ses_ptr->alignmask && !IS_ALIGNED((unsigned long)cop->dst, ses_ptr->alignmask + 1))) { + dwarning(2, "destination address %p is not %d byte aligned - disabling zero copy", + cop->dst, ses_ptr->alignmask + 1); + cop->flags |= COP_FLAG_NO_ZC; + } + } + } + + if (cop->flags & COP_FLAG_NO_ZC) + ret = __crypto_run_std(ses_ptr, &kcop->cop); + else + ret = __crypto_run_zc(ses_ptr, kcop); + if (unlikely(ret)) + goto out_unlock; + } + + if (ses_ptr->cdata.init != 0) { + cryptodev_cipher_get_iv(&ses_ptr->cdata, kcop->iv, + min(ses_ptr->cdata.ivsize, kcop->ivlen)); + } + + if (ses_ptr->hdata.init != 0 && + ((cop->flags & COP_FLAG_FINAL) || + (!(cop->flags & COP_FLAG_UPDATE) || cop->len == 0))) { + + ret = cryptodev_hash_final(&ses_ptr->hdata, kcop->hash_output); + if (unlikely(ret)) { + derr(0, "CryptoAPI failure: %d", ret); + goto out_unlock; + } + kcop->digestsize = ses_ptr->hdata.digestsize; + } + +out_unlock: + crypto_put_session(ses_ptr); + return ret; +} diff --git a/drivers/cryptodev-linux-master/tests/Makefile b/drivers/cryptodev-linux-master/tests/Makefile new file mode 100644 index 00000000..2502f32b --- /dev/null +++ b/drivers/cryptodev-linux-master/tests/Makefile @@ -0,0 +1,47 @@ +CFLAGS += -I.. $(CRYPTODEV_CFLAGS) -Wall -Werror + +comp_progs := cipher_comp hash_comp hmac_comp + +hostprogs := cipher cipher-aead hmac speed async_cipher async_hmac \ + async_speed sha_speed hashcrypt_speed fullspeed cipher-gcm \ + cipher-aead-srtp $(comp_progs) + +example-cipher-objs := cipher.o +example-cipher-aead-objs := cipher-aead.o +example-hmac-objs := hmac.o +example-speed-objs := speed.c +example-fullspeed-objs := fullspeed.c +example-sha-speed-objs := sha_speed.c +example-async-cipher-objs := async_cipher.o +example-async-hmac-objs := async_hmac.o +example-async-speed-objs := async_speed.o +example-hashcrypt-speed-objs := hashcrypt_speed.c + +prefix ?= /usr/local +execprefix ?= $(prefix) +bindir = $(execprefix)/bin + +all: $(hostprogs) + +check: $(hostprogs) + ./cipher + ./hmac + ./async_cipher + ./async_hmac + ./cipher-aead-srtp + ./cipher-gcm + ./cipher-aead + +install: + install -d $(DESTDIR)/$(bindir) + for prog in $(hostprogs); do \ + install -m 755 $$prog $(DESTDIR)/$(bindir); \ + done + +clean: + rm -f *.o *~ $(hostprogs) + +${comp_progs}: LDLIBS += -lssl -lcrypto +${comp_progs}: %: %.o openssl_wrapper.o + +.PHONY: all clean check install diff --git a/drivers/cryptodev-linux-master/tests/async_cipher.c b/drivers/cryptodev-linux-master/tests/async_cipher.c new file mode 100644 index 00000000..7a184e5a --- /dev/null +++ b/drivers/cryptodev-linux-master/tests/async_cipher.c @@ -0,0 +1,339 @@ +/* + * Demo on how to use /dev/crypto device for ciphering. + * + * Placed under public domain. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "asynchelper.h" +#include "testhelper.h" + +#ifdef ENABLE_ASYNC + +static int debug = 0; + +#define DATA_SIZE 8*1024 +#define BLOCK_SIZE 16 +#define KEY_SIZE 16 + +static int +test_crypto(int cfd) +{ + uint8_t plaintext_raw[DATA_SIZE + 63], *plaintext; + uint8_t ciphertext_raw[DATA_SIZE + 63], *ciphertext; + uint8_t iv[BLOCK_SIZE]; + uint8_t key[KEY_SIZE]; + + struct session_op sess; +#ifdef CIOCGSESSINFO + struct session_info_op siop; +#endif + struct crypt_op cryp; + + if (debug) printf("running %s\n", __func__); + + memset(&sess, 0, sizeof(sess)); + memset(&cryp, 0, sizeof(cryp)); + + memset(key, 0x33, sizeof(key)); + memset(iv, 0x03, sizeof(iv)); + + /* Get crypto session for AES128 */ + sess.cipher = CRYPTO_AES_CBC; + sess.keylen = KEY_SIZE; + sess.key = key; + if (ioctl(cfd, CIOCGSESSION, &sess)) { + perror("ioctl(CIOCGSESSION)"); + return 1; + } + + if (debug) printf("%s: got the session\n", __func__); + +#ifdef CIOCGSESSINFO + siop.ses = sess.ses; + if (ioctl(cfd, CIOCGSESSINFO, &siop)) { + perror("ioctl(CIOCGSESSINFO)"); + return 1; + } + plaintext = buf_align(plaintext_raw, siop.alignmask); + ciphertext = buf_align(ciphertext_raw, siop.alignmask); +#else + plaintext = plaintext_raw; + ciphertext = ciphertext_raw; +#endif + memset(plaintext, 0x15, DATA_SIZE); + + /* Encrypt data.in to data.encrypted */ + cryp.ses = sess.ses; + cryp.len = DATA_SIZE; + cryp.src = plaintext; + cryp.dst = ciphertext; + cryp.iv = iv; + cryp.op = COP_ENCRYPT; + + DO_OR_DIE(do_async_crypt(cfd, &cryp), 0); + DO_OR_DIE(do_async_fetch(cfd, &cryp), 0); + + if (debug) printf("%s: data encrypted\n", __func__); + + if (ioctl(cfd, CIOCFSESSION, &sess.ses)) { + perror("ioctl(CIOCFSESSION)"); + return 1; + } + if (debug) printf("%s: session finished\n", __func__); + + if (ioctl(cfd, CIOCGSESSION, &sess)) { + perror("ioctl(CIOCGSESSION)"); + return 1; + } + if (debug) printf("%s: got new session\n", __func__); + + /* Decrypt data.encrypted to data.decrypted */ + cryp.ses = sess.ses; + cryp.len = DATA_SIZE; + cryp.src = ciphertext; + cryp.dst = ciphertext; + cryp.iv = iv; + cryp.op = COP_DECRYPT; + + DO_OR_DIE(do_async_crypt(cfd, &cryp), 0); + DO_OR_DIE(do_async_fetch(cfd, &cryp), 0); + + if (debug) printf("%s: data encrypted\n", __func__); + + /* Verify the result */ + if (memcmp(plaintext, ciphertext, DATA_SIZE) != 0) { + fprintf(stderr, + "FAIL: Decrypted data are different from the input data.\n"); + return 1; + } else if (debug) + printf("Test passed\n"); + + /* Finish crypto session */ + if (ioctl(cfd, CIOCFSESSION, &sess.ses)) { + perror("ioctl(CIOCFSESSION)"); + return 1; + } + + return 0; +} + +static int test_aes(int cfd) +{ + uint8_t plaintext1_raw[BLOCK_SIZE + 63], *plaintext1; + uint8_t ciphertext1[BLOCK_SIZE] = { 0xdf, 0x55, 0x6a, 0x33, 0x43, 0x8d, 0xb8, 0x7b, 0xc4, 0x1b, 0x17, 0x52, 0xc5, 0x5e, 0x5e, 0x49 }; + uint8_t iv1[BLOCK_SIZE]; + uint8_t key1[KEY_SIZE] = { 0xff, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + uint8_t plaintext2_data[BLOCK_SIZE] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x00 }; + uint8_t plaintext2_raw[BLOCK_SIZE + 63], *plaintext2; + uint8_t ciphertext2[BLOCK_SIZE] = { 0xb7, 0x97, 0x2b, 0x39, 0x41, 0xc4, 0x4b, 0x90, 0xaf, 0xa7, 0xb2, 0x64, 0xbf, 0xba, 0x73, 0x87 }; + uint8_t iv2[BLOCK_SIZE]; + uint8_t key2[KEY_SIZE]; + + struct session_op sess1, sess2; +#ifdef CIOCGSESSINFO + struct session_info_op siop1, siop2; +#endif + struct crypt_op cryp1, cryp2; + + memset(&sess1, 0, sizeof(sess1)); + memset(&sess2, 0, sizeof(sess2)); + memset(&cryp1, 0, sizeof(cryp1)); + memset(&cryp2, 0, sizeof(cryp2)); + + /* Get crypto session for AES128 */ + sess1.cipher = CRYPTO_AES_CBC; + sess1.keylen = KEY_SIZE; + sess1.key = key1; + if (ioctl(cfd, CIOCGSESSION, &sess1)) { + perror("ioctl(CIOCGSESSION)"); + return 1; + } +#ifdef CIOCGSESSINFO + siop1.ses = sess1.ses; + if (ioctl(cfd, CIOCGSESSINFO, &siop1)) { + perror("ioctl(CIOCGSESSINFO)"); + return 1; + } + plaintext1 = buf_align(plaintext1_raw, siop1.alignmask); +#else + plaintext1 = plaintext1_raw; +#endif + memset(plaintext1, 0x0, BLOCK_SIZE); + + memset(iv1, 0x0, sizeof(iv1)); + memset(key2, 0x0, sizeof(key2)); + + /* Get second crypto session for AES128 */ + sess2.cipher = CRYPTO_AES_CBC; + sess2.keylen = KEY_SIZE; + sess2.key = key2; + if (ioctl(cfd, CIOCGSESSION, &sess2)) { + perror("ioctl(CIOCGSESSION)"); + return 1; + } +#ifdef CIOCGSESSINFO + siop2.ses = sess2.ses; + if (ioctl(cfd, CIOCGSESSINFO, &siop2)) { + perror("ioctl(CIOCGSESSINFO)"); + return 1; + } + plaintext2 = buf_align(plaintext2_raw, siop2.alignmask); +#else + plaintext2 = plaintext2_raw; +#endif + memcpy(plaintext2, plaintext2_data, BLOCK_SIZE); + + /* Encrypt data.in to data.encrypted */ + cryp1.ses = sess1.ses; + cryp1.len = BLOCK_SIZE; + cryp1.src = plaintext1; + cryp1.dst = plaintext1; + cryp1.iv = iv1; + cryp1.op = COP_ENCRYPT; + + DO_OR_DIE(do_async_crypt(cfd, &cryp1), 0); + if (debug) printf("cryp1 written out\n"); + + memset(iv2, 0x0, sizeof(iv2)); + + /* Encrypt data.in to data.encrypted */ + cryp2.ses = sess2.ses; + cryp2.len = BLOCK_SIZE; + cryp2.src = plaintext2; + cryp2.dst = plaintext2; + cryp2.iv = iv2; + cryp2.op = COP_ENCRYPT; + + DO_OR_DIE(do_async_crypt(cfd, &cryp2), 0); + if (debug) printf("cryp2 written out\n"); + + DO_OR_DIE(do_async_fetch(cfd, &cryp1), 0); + DO_OR_DIE(do_async_fetch(cfd, &cryp2), 0); + if (debug) printf("cryp1 + cryp2 successfully read\n"); + + /* Verify the result */ + if (memcmp(plaintext1, ciphertext1, BLOCK_SIZE) != 0) { + int i; + fprintf(stderr, + "FAIL: Decrypted data are different from the input data.\n"); + printf("plaintext:"); + for (i = 0; i < BLOCK_SIZE; i++) { + if ((i % 30) == 0) + printf("\n"); + printf("%02x ", plaintext1[i]); + } + printf("ciphertext:"); + for (i = 0; i < BLOCK_SIZE; i++) { + if ((i % 30) == 0) + printf("\n"); + printf("%02x ", ciphertext1[i]); + } + printf("\n"); + return 1; + } else { + if (debug) printf("result 1 passed\n"); + } + + /* Test 2 */ + + /* Verify the result */ + if (memcmp(plaintext2, ciphertext2, BLOCK_SIZE) != 0) { + int i; + fprintf(stderr, + "FAIL: Decrypted data are different from the input data.\n"); + printf("plaintext:"); + for (i = 0; i < BLOCK_SIZE; i++) { + if ((i % 30) == 0) + printf("\n"); + printf("%02x ", plaintext2[i]); + } + printf("ciphertext:"); + for (i = 0; i < BLOCK_SIZE; i++) { + if ((i % 30) == 0) + printf("\n"); + printf("%02x ", ciphertext2[i]); + } + printf("\n"); + return 1; + } else { + if (debug) printf("result 2 passed\n"); + } + + if (debug) printf("AES Test passed\n"); + + /* Finish crypto session */ + if (ioctl(cfd, CIOCFSESSION, &sess1.ses)) { + perror("ioctl(CIOCFSESSION)"); + return 1; + } + if (ioctl(cfd, CIOCFSESSION, &sess2.ses)) { + perror("ioctl(CIOCFSESSION)"); + return 1; + } + + return 0; +} + +int +main(int argc, char** argv) +{ + int fd = -1, cfd = -1; + + if (argc > 1) debug = 1; + + /* Open the crypto device */ + fd = open("/dev/crypto", O_RDWR, 0); + if (fd < 0) { + perror("open(/dev/crypto)"); + return 1; + } + + /* Clone file descriptor */ + if (ioctl(fd, CRIOGET, &cfd)) { + perror("ioctl(CRIOGET)"); + return 1; + } + + /* Set close-on-exec (not really neede here) */ + if (fcntl(cfd, F_SETFD, 1) == -1) { + perror("fcntl(F_SETFD)"); + return 1; + } + + /* Run the test itself */ + if (test_aes(cfd)) + return 1; + + if (test_crypto(cfd)) + return 1; + + /* Close cloned descriptor */ + if (close(cfd)) { + perror("close(cfd)"); + return 1; + } + + /* Close the original descriptor */ + if (close(fd)) { + perror("close(fd)"); + return 1; + } + + return 0; +} +#else +int +main(int argc, char** argv) +{ + return (0); +} +#endif diff --git a/drivers/cryptodev-linux-master/tests/async_hmac.c b/drivers/cryptodev-linux-master/tests/async_hmac.c new file mode 100644 index 00000000..014b8ed7 --- /dev/null +++ b/drivers/cryptodev-linux-master/tests/async_hmac.c @@ -0,0 +1,301 @@ +/* + * Demo on how to use /dev/crypto device for HMAC. + * + * Placed under public domain. + * + */ +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "asynchelper.h" + +#ifdef ENABLE_ASYNC + +static int debug = 0; + +#define DATA_SIZE 4096 +#define BLOCK_SIZE 16 +#define KEY_SIZE 16 +#define SHA1_HASH_LEN 20 + +static int +test_crypto(int cfd) +{ + struct { + uint8_t in[DATA_SIZE], + encrypted[DATA_SIZE], + decrypted[DATA_SIZE], + iv[BLOCK_SIZE], + key[KEY_SIZE]; + } data; + struct session_op sess; + struct crypt_op cryp; + uint8_t mac[AALG_MAX_RESULT_LEN]; + uint8_t oldmac[AALG_MAX_RESULT_LEN]; + uint8_t md5_hmac_out[] = "\x75\x0c\x78\x3e\x6a\xb0\xb5\x03\xea\xa8\x6e\x31\x0a\x5d\xb7\x38"; + uint8_t sha1_out[] = "\x8f\x82\x03\x94\xf9\x53\x35\x18\x20\x45\xda\x24\xf3\x4d\xe5\x2b\xf8\xbc\x34\x32"; + int i; + + memset(&sess, 0, sizeof(sess)); + memset(&cryp, 0, sizeof(cryp)); + + /* Use the garbage that is on the stack :-) */ + /* memset(&data, 0, sizeof(data)); */ + + /* SHA1 plain test */ + memset(mac, 0, sizeof(mac)); + + sess.cipher = 0; + sess.mac = CRYPTO_SHA1; + if (ioctl(cfd, CIOCGSESSION, &sess)) { + perror("ioctl(CIOCGSESSION)"); + return 1; + } + + cryp.ses = sess.ses; + cryp.len = sizeof("what do ya want for nothing?")-1; + cryp.src = (uint8_t *)"what do ya want for nothing?"; + cryp.mac = mac; + cryp.op = COP_ENCRYPT; + + DO_OR_DIE(do_async_crypt(cfd, &cryp), 0); + DO_OR_DIE(do_async_fetch(cfd, &cryp), 0); + + if (memcmp(mac, sha1_out, 20)!=0) { + printf("mac: "); + for (i=0;i + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef ENABLE_ASYNC + +static double udifftimeval(struct timeval start, struct timeval end) +{ + return (double)(end.tv_usec - start.tv_usec) + + (double)(end.tv_sec - start.tv_sec) * 1000 * 1000; +} + +static volatile int must_finish; +static struct pollfd pfd; + +static void alarm_handler(int signo) +{ + must_finish = 1; + pfd.events = POLLIN; +} + +static char *units[] = { "", "Ki", "Mi", "Gi", "Ti", 0}; + +static void value2human(double bytes, double time, double* data, double* speed,char* metric) +{ + int unit = 0; + + *data = bytes; + while (*data > 1024 && units[unit + 1]) { + *data /= 1024; + unit++; + } + *speed = *data / time; + sprintf(metric, "%sB", units[unit]); +} + + +int encrypt_data(struct session_op *sess, int fdc, int chunksize, int alignmask) +{ + struct crypt_op cop; + char *buffer[64], iv[32]; + static int val = 23; + struct timeval start, end; + double total = 0; + double secs, ddata, dspeed; + char metric[16]; + int rc, wqueue = 0, bufidx = 0; + + memset(iv, 0x23, 32); + + printf("\tEncrypting in chunks of %d bytes: ", chunksize); + fflush(stdout); + + for (rc = 0; rc < 64; rc++) { + if (alignmask) { + if (posix_memalign((void **)(buffer + rc), alignmask + 1, chunksize)) { + printf("posix_memalign() failed!\n"); + return 1; + } + } else { + if (!(buffer[rc] = malloc(chunksize))) { + perror("malloc()"); + return 1; + } + } + memset(buffer[rc], val++, chunksize); + } + pfd.fd = fdc; + pfd.events = POLLOUT | POLLIN; + + must_finish = 0; + alarm(5); + + gettimeofday(&start, NULL); + do { + if ((rc = poll(&pfd, 1, 100)) < 0) { + if (errno & (ERESTART | EINTR)) + continue; + fprintf(stderr, "errno = %d ", errno); + perror("poll()"); + return 1; + } + + if (pfd.revents & POLLOUT) { + memset(&cop, 0, sizeof(cop)); + cop.ses = sess->ses; + cop.len = chunksize; + cop.iv = (unsigned char *)iv; + cop.op = COP_ENCRYPT; + cop.src = cop.dst = (unsigned char *)buffer[bufidx]; + bufidx = (bufidx + 1) % 64; + + if (ioctl(fdc, CIOCASYNCCRYPT, &cop)) { + perror("ioctl(CIOCASYNCCRYPT)"); + return 1; + } + wqueue++; + } + if (pfd.revents & POLLIN) { + if (ioctl(fdc, CIOCASYNCFETCH, &cop)) { + perror("ioctl(CIOCASYNCFETCH)"); + return 1; + } + wqueue--; + total += cop.len; + } + } while(!must_finish || wqueue); + gettimeofday(&end, NULL); + + secs = udifftimeval(start, end)/ 1000000.0; + + value2human(total, secs, &ddata, &dspeed, metric); + printf ("done. %.2f %s in %.2f secs: ", ddata, metric, secs); + printf ("%.2f %s/sec\n", dspeed, metric); + + for (rc = 0; rc < 64; rc++) + free(buffer[rc]); + return 0; +} + +int main(void) +{ + int fd, i, fdc = -1, alignmask = 0; + struct session_op sess; +#ifdef CIOCGSESSINFO + struct session_info_op siop; +#endif + char keybuf[32]; + + signal(SIGALRM, alarm_handler); + + if ((fd = open("/dev/crypto", O_RDWR, 0)) < 0) { + perror("open()"); + return 1; + } + if (ioctl(fd, CRIOGET, &fdc)) { + perror("ioctl(CRIOGET)"); + return 1; + } + + fprintf(stderr, "Testing NULL cipher: \n"); + memset(&sess, 0, sizeof(sess)); + sess.cipher = CRYPTO_NULL; + sess.keylen = 0; + sess.key = (unsigned char *)keybuf; + if (ioctl(fdc, CIOCGSESSION, &sess)) { + perror("ioctl(CIOCGSESSION)"); + return 1; + } +#ifdef CIOCGSESSINFO + siop.ses = sess.ses; + if (ioctl(fdc, CIOCGSESSINFO, &siop)) { + perror("ioctl(CIOCGSESSINFO)"); + return 1; + } + alignmask = siop.alignmask; +#endif + + for (i = 256; i <= (64 * 4096); i *= 2) { + if (encrypt_data(&sess, fdc, i, alignmask)) + break; + } + + fprintf(stderr, "\nTesting AES-128-CBC cipher: \n"); + memset(&sess, 0, sizeof(sess)); + sess.cipher = CRYPTO_AES_CBC; + sess.keylen = 16; + memset(keybuf, 0x42, 16); + sess.key = (unsigned char *)keybuf; + if (ioctl(fdc, CIOCGSESSION, &sess)) { + perror("ioctl(CIOCGSESSION)"); + return 1; + } +#ifdef CIOCGSESSINFO + siop.ses = sess.ses; + if (ioctl(fdc, CIOCGSESSINFO, &siop)) { + perror("ioctl(CIOCGSESSINFO)"); + return 1; + } + alignmask = siop.alignmask; +#endif + + for (i = 256; i <= (64 * 1024); i *= 2) { + if (encrypt_data(&sess, fdc, i, alignmask)) + break; + } + + close(fdc); + close(fd); + return 0; +} + +#else +int +main(int argc, char** argv) +{ + return (0); +} +#endif diff --git a/drivers/cryptodev-linux-master/tests/asynchelper.h b/drivers/cryptodev-linux-master/tests/asynchelper.h new file mode 100644 index 00000000..b5ab16c8 --- /dev/null +++ b/drivers/cryptodev-linux-master/tests/asynchelper.h @@ -0,0 +1,54 @@ +#ifndef __ASYNCHELPER_H +#define __ASYNCHELPER_H + +/* poll until POLLOUT, then call CIOCASYNCCRYPT */ +inline int do_async_crypt(int cfd, struct crypt_op *cryp) +{ + struct pollfd pfd; + + pfd.fd = cfd; + pfd.events = POLLOUT; + + if (poll(&pfd, 1, -1) < 1) { + perror("poll()"); + return 1; + } + + if (ioctl(cfd, CIOCASYNCCRYPT, cryp)) { + perror("ioctl(CIOCCRYPT)"); + return 1; + } + return 0; +} + +/* poll until POLLIN, then call CIOCASYNCFETCH */ +inline int do_async_fetch(int cfd, struct crypt_op *cryp) +{ + struct pollfd pfd; + + pfd.fd = cfd; + pfd.events = POLLIN; + + if (poll(&pfd, 1, -1) < 1) { + perror("poll()"); + return 1; + } + + if (ioctl(cfd, CIOCASYNCFETCH, cryp)) { + perror("ioctl(CIOCCRYPT)"); + return 1; + } + return 0; +} + +/* Check return value of stmt for identity with goodval. If they + * don't match, call return with the value of stmt. */ +#define DO_OR_DIE(stmt, goodval) { \ + int __rc_val; \ + if ((__rc_val = stmt) != goodval) { \ + perror("DO_OR_DIE(" #stmt "," #goodval ")"); \ + return __rc_val; \ + } \ +} + +#endif /* __ASYNCHELPER_H */ diff --git a/drivers/cryptodev-linux-master/tests/cipher-aead-srtp.c b/drivers/cryptodev-linux-master/tests/cipher-aead-srtp.c new file mode 100644 index 00000000..b1b0a219 --- /dev/null +++ b/drivers/cryptodev-linux-master/tests/cipher-aead-srtp.c @@ -0,0 +1,595 @@ +/* + * Demo on how to use /dev/crypto device for ciphering. + * + * Placed under public domain. + * + */ +#include +#include +#include +#include +#include + +#include +#include +#include "testhelper.h" + +#define DATA_SIZE (8*1024) +#define HEADER_SIZE 193 +#define PLAINTEXT_SIZE 1021 +#define FOOTER_SIZE 15 +#define BLOCK_SIZE 16 +#define KEY_SIZE 16 + +#define MAC_SIZE 20 /* SHA1 */ + +static int debug = 0; + +static int +get_sha1_hmac(int cfd, void* key, int key_size, void* data, int data_size, void* mac) +{ + struct session_op sess; + struct crypt_op cryp; + + memset(&sess, 0, sizeof(sess)); + memset(&cryp, 0, sizeof(cryp)); + + sess.cipher = 0; + sess.mac = CRYPTO_SHA1_HMAC; + sess.mackeylen = key_size; + sess.mackey = key; + if (ioctl(cfd, CIOCGSESSION, &sess)) { + perror("ioctl(CIOCGSESSION)"); + return 1; + } + + /* Encrypt data.in to data.encrypted */ + cryp.ses = sess.ses; + cryp.len = data_size; + cryp.src = data; + cryp.dst = NULL; + cryp.iv = NULL; + cryp.mac = mac; + cryp.op = COP_ENCRYPT; + if (ioctl(cfd, CIOCCRYPT, &cryp)) { + perror("ioctl(CIOCCRYPT)"); + return 1; + } + + /* Finish crypto session */ + if (ioctl(cfd, CIOCFSESSION, &sess.ses)) { + perror("ioctl(CIOCFSESSION)"); + return 1; + } + + return 0; +} + +static void print_buf(char* desc, unsigned char* buf, int size) +{ +int i; + fputs(desc, stderr); + for (i=0;i 1) debug = 1; + + /* Open the crypto device */ + fd = open("/dev/crypto", O_RDWR, 0); + if (fd < 0) { + perror("open(/dev/crypto)"); + return 1; + } + + /* Clone file descriptor */ + if (ioctl(fd, CRIOGET, &cfd)) { + perror("ioctl(CRIOGET)"); + return 1; + } + + /* Set close-on-exec (not really neede here) */ + if (fcntl(cfd, F_SETFD, 1) == -1) { + perror("fcntl(F_SETFD)"); + return 1; + } + + /* Run the test itself */ + + if (test_crypto(cfd)) + return 1; + + if (test_encrypt_decrypt(cfd)) + return 1; + + if (test_encrypt_decrypt_error(cfd,0)) + return 1; + + if (test_encrypt_decrypt_error(cfd,1)) + return 1; + + /* Close cloned descriptor */ + if (close(cfd)) { + perror("close(cfd)"); + return 1; + } + + /* Close the original descriptor */ + if (close(fd)) { + perror("close(fd)"); + return 1; + } + + return 0; +} + diff --git a/drivers/cryptodev-linux-master/tests/cipher-aead.c b/drivers/cryptodev-linux-master/tests/cipher-aead.c new file mode 100644 index 00000000..305b7206 --- /dev/null +++ b/drivers/cryptodev-linux-master/tests/cipher-aead.c @@ -0,0 +1,575 @@ +/* + * Demo on how to use /dev/crypto device for ciphering. + * + * Placed under public domain. + * + */ +#include +#include +#include +#include +#include + +#include +#include +#include "testhelper.h" + +#define DATA_SIZE (8*1024) +#define AUTH_SIZE 31 +#define BLOCK_SIZE 16 +#define KEY_SIZE 16 + +#define MAC_SIZE 20 /* SHA1 */ + +static int debug = 0; + +static int +get_sha1_hmac(int cfd, void* key, int key_size, void* data1, int data1_size, void* data2, int data2_size, void* mac) +{ + struct session_op sess; + struct crypt_op cryp; + + memset(&sess, 0, sizeof(sess)); + memset(&cryp, 0, sizeof(cryp)); + + sess.cipher = 0; + sess.mac = CRYPTO_SHA1_HMAC; + sess.mackeylen = key_size; + sess.mackey = key; + if (ioctl(cfd, CIOCGSESSION, &sess)) { + perror("ioctl(CIOCGSESSION)"); + return 1; + } + + /* Encrypt data.in to data.encrypted */ + cryp.ses = sess.ses; + cryp.len = data1_size; + cryp.src = data1; + cryp.dst = NULL; + cryp.iv = NULL; + cryp.mac = mac; + cryp.op = COP_ENCRYPT; + cryp.flags = COP_FLAG_UPDATE; + if (ioctl(cfd, CIOCCRYPT, &cryp)) { + perror("ioctl(CIOCCRYPT)"); + return 1; + } + + cryp.ses = sess.ses; + cryp.len = data2_size; + cryp.src = data2; + cryp.dst = NULL; + cryp.iv = NULL; + cryp.mac = mac; + cryp.op = COP_ENCRYPT; + cryp.flags = COP_FLAG_FINAL; + if (ioctl(cfd, CIOCCRYPT, &cryp)) { + perror("ioctl(CIOCCRYPT)"); + return 1; + } + + /* Finish crypto session */ + if (ioctl(cfd, CIOCFSESSION, &sess.ses)) { + perror("ioctl(CIOCFSESSION)"); + return 1; + } + + return 0; +} + +static void print_buf(char* desc, unsigned char* buf, int size) +{ +int i; + fputs(desc, stdout); + for (i=0;i +#include +#include +#include +#include + +#include +#include +#include "testhelper.h" + +#define DATA_SIZE (8*1024) +#define AUTH_SIZE 31 +#define BLOCK_SIZE 16 +#define KEY_SIZE 16 + +#define my_perror(x) {fprintf(stderr, "%s: %d\n", __func__, __LINE__); perror(x); } + +static int debug = 0; + +static void print_buf(char *desc, const unsigned char *buf, int size) +{ + int i; + fputs(desc, stdout); + for (i = 0; i < size; i++) { + printf("%.2x", (uint8_t) buf[i]); + } + fputs("\n", stdout); +} + +struct aes_gcm_vectors_st { + const uint8_t *key; + const uint8_t *auth; + int auth_size; + const uint8_t *plaintext; + int plaintext_size; + const uint8_t *iv; + const uint8_t *ciphertext; + const uint8_t *tag; +}; + +struct aes_gcm_vectors_st aes_gcm_vectors[] = { + { + .key = (uint8_t *) + "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", + .auth = NULL, + .auth_size = 0, + .plaintext = (uint8_t *) + "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", + .plaintext_size = 16, + .ciphertext = (uint8_t *) + "\x03\x88\xda\xce\x60\xb6\xa3\x92\xf3\x28\xc2\xb9\x71\xb2\xfe\x78", + .iv = (uint8_t *)"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", + .tag = (uint8_t *) + "\xab\x6e\x47\xd4\x2c\xec\x13\xbd\xf5\x3a\x67\xb2\x12\x57\xbd\xdf" + }, + { + .key = (uint8_t *) + "\xfe\xff\xe9\x92\x86\x65\x73\x1c\x6d\x6a\x8f\x94\x67\x30\x83\x08", + .auth = NULL, + .auth_size = 0, + .plaintext = (uint8_t *) + "\xd9\x31\x32\x25\xf8\x84\x06\xe5\xa5\x59\x09\xc5\xaf\xf5\x26\x9a\x86\xa7\xa9\x53\x15\x34\xf7\xda\x2e\x4c\x30\x3d\x8a\x31\x8a\x72\x1c\x3c\x0c\x95\x95\x68\x09\x53\x2f\xcf\x0e\x24\x49\xa6\xb5\x25\xb1\x6a\xed\xf5\xaa\x0d\xe6\x57\xba\x63\x7b\x39\x1a\xaf\xd2\x55", + .plaintext_size = 64, + .ciphertext = (uint8_t *) + "\x42\x83\x1e\xc2\x21\x77\x74\x24\x4b\x72\x21\xb7\x84\xd0\xd4\x9c\xe3\xaa\x21\x2f\x2c\x02\xa4\xe0\x35\xc1\x7e\x23\x29\xac\xa1\x2e\x21\xd5\x14\xb2\x54\x66\x93\x1c\x7d\x8f\x6a\x5a\xac\x84\xaa\x05\x1b\xa3\x0b\x39\x6a\x0a\xac\x97\x3d\x58\xe0\x91\x47\x3f\x59\x85", + .iv = (uint8_t *)"\xca\xfe\xba\xbe\xfa\xce\xdb\xad\xde\xca\xf8\x88", + .tag = (uint8_t *)"\x4d\x5c\x2a\xf3\x27\xcd\x64\xa6\x2c\xf3\x5a\xbd\x2b\xa6\xfa\xb4" + }, + { + .key = (uint8_t *) + "\xfe\xff\xe9\x92\x86\x65\x73\x1c\x6d\x6a\x8f\x94\x67\x30\x83\x08", + .auth = (uint8_t *) + "\xfe\xed\xfa\xce\xde\xad\xbe\xef\xfe\xed\xfa\xce\xde\xad\xbe\xef\xab\xad\xda\xd2", + .auth_size = 20, + .plaintext = (uint8_t *) + "\xd9\x31\x32\x25\xf8\x84\x06\xe5\xa5\x59\x09\xc5\xaf\xf5\x26\x9a\x86\xa7\xa9\x53\x15\x34\xf7\xda\x2e\x4c\x30\x3d\x8a\x31\x8a\x72\x1c\x3c\x0c\x95\x95\x68\x09\x53\x2f\xcf\x0e\x24\x49\xa6\xb5\x25\xb1\x6a\xed\xf5\xaa\x0d\xe6\x57\xba\x63\x7b\x39", + .plaintext_size = 60, + .ciphertext = (uint8_t *) + "\x42\x83\x1e\xc2\x21\x77\x74\x24\x4b\x72\x21\xb7\x84\xd0\xd4\x9c\xe3\xaa\x21\x2f\x2c\x02\xa4\xe0\x35\xc1\x7e\x23\x29\xac\xa1\x2e\x21\xd5\x14\xb2\x54\x66\x93\x1c\x7d\x8f\x6a\x5a\xac\x84\xaa\x05\x1b\xa3\x0b\x39\x6a\x0a\xac\x97\x3d\x58\xe0\x91", + .iv = (uint8_t *)"\xca\xfe\xba\xbe\xfa\xce\xdb\xad\xde\xca\xf8\x88", + .tag = (uint8_t *) + "\x5b\xc9\x4f\xbc\x32\x21\xa5\xdb\x94\xfa\xe9\x5a\xe7\x12\x1a\x47" + } +}; + + +/* Test against AES-GCM test vectors. + */ +static int test_crypto(int cfd) +{ + int i; + uint8_t tmp[128]; + + struct session_op sess; + struct crypt_auth_op cao; + + /* Get crypto session for AES128 */ + + if (debug) { + fprintf(stdout, "Tests on AES-GCM vectors: "); + fflush(stdout); + } + for (i = 0; + i < sizeof(aes_gcm_vectors) / sizeof(aes_gcm_vectors[0]); + i++) { + memset(&sess, 0, sizeof(sess)); + memset(tmp, 0, sizeof(tmp)); + + sess.cipher = CRYPTO_AES_GCM; + sess.keylen = 16; + sess.key = (void *) aes_gcm_vectors[i].key; + + if (ioctl(cfd, CIOCGSESSION, &sess)) { + my_perror("ioctl(CIOCGSESSION)"); + return 1; + } + + memset(&cao, 0, sizeof(cao)); + + cao.ses = sess.ses; + cao.dst = tmp; + cao.iv = (void *) aes_gcm_vectors[i].iv; + cao.iv_len = 12; + cao.op = COP_ENCRYPT; + cao.flags = 0; + + if (aes_gcm_vectors[i].auth_size > 0) { + cao.auth_src = (void *) aes_gcm_vectors[i].auth; + cao.auth_len = aes_gcm_vectors[i].auth_size; + } + + if (aes_gcm_vectors[i].plaintext_size > 0) { + cao.src = (void *) aes_gcm_vectors[i].plaintext; + cao.len = aes_gcm_vectors[i].plaintext_size; + } + + if (ioctl(cfd, CIOCAUTHCRYPT, &cao)) { + my_perror("ioctl(CIOCAUTHCRYPT)"); + return 1; + } + + if (aes_gcm_vectors[i].plaintext_size > 0) + if (memcmp + (tmp, aes_gcm_vectors[i].ciphertext, + aes_gcm_vectors[i].plaintext_size) != 0) { + fprintf(stderr, + "AES-GCM test vector %d failed!\n", + i); + + print_buf("Cipher: ", tmp, aes_gcm_vectors[i].plaintext_size); + print_buf("Expected: ", aes_gcm_vectors[i].ciphertext, aes_gcm_vectors[i].plaintext_size); + return 1; + } + + if (memcmp + (&tmp[cao.len - cao.tag_len], aes_gcm_vectors[i].tag, + 16) != 0) { + fprintf(stderr, + "AES-GCM test vector %d failed (tag)!\n", + i); + + print_buf("Tag: ", &tmp[cao.len - cao.tag_len], cao.tag_len); + print_buf("Expected tag: ", + aes_gcm_vectors[i].tag, 16); + return 1; + } + + } + + if (debug) { + fprintf(stdout, "ok\n"); + fprintf(stdout, "\n"); + } + + /* Finish crypto session */ + if (ioctl(cfd, CIOCFSESSION, &sess.ses)) { + my_perror("ioctl(CIOCFSESSION)"); + return 1; + } + + return 0; +} + +/* Checks if encryption and subsequent decryption + * produces the same data. + */ +static int test_encrypt_decrypt(int cfd) +{ + uint8_t plaintext_raw[DATA_SIZE + 63], *plaintext; + uint8_t ciphertext_raw[DATA_SIZE + 63], *ciphertext; + uint8_t iv[BLOCK_SIZE]; + uint8_t key[KEY_SIZE]; + uint8_t auth[AUTH_SIZE]; + int enc_len; + + struct session_op sess; + struct crypt_auth_op cao; + struct session_info_op siop; + + if (debug) { + fprintf(stdout, "Tests on AES-GCM encryption/decryption: "); + fflush(stdout); + } + + memset(&sess, 0, sizeof(sess)); + memset(&cao, 0, sizeof(cao)); + + memset(key, 0x33, sizeof(key)); + memset(iv, 0x03, sizeof(iv)); + memset(auth, 0xf1, sizeof(auth)); + + /* Get crypto session for AES128 */ + sess.cipher = CRYPTO_AES_GCM; + sess.keylen = KEY_SIZE; + sess.key = key; + + if (ioctl(cfd, CIOCGSESSION, &sess)) { + my_perror("ioctl(CIOCGSESSION)"); + return 1; + } + + siop.ses = sess.ses; + if (ioctl(cfd, CIOCGSESSINFO, &siop)) { + my_perror("ioctl(CIOCGSESSINFO)"); + return 1; + } +// printf("requested cipher CRYPTO_AES_CBC/HMAC-SHA1, got %s with driver %s\n", +// siop.cipher_info.cra_name, siop.cipher_info.cra_driver_name); + + plaintext = (uint8_t *)buf_align(plaintext_raw, siop.alignmask); + ciphertext = (uint8_t *)buf_align(ciphertext_raw, siop.alignmask); + + memset(plaintext, 0x15, DATA_SIZE); + + /* Encrypt data.in to data.encrypted */ + cao.ses = sess.ses; + cao.auth_src = auth; + cao.auth_len = sizeof(auth); + cao.len = DATA_SIZE; + cao.src = plaintext; + cao.dst = ciphertext; + cao.iv = iv; + cao.iv_len = 12; + cao.op = COP_ENCRYPT; + cao.flags = 0; + + if (ioctl(cfd, CIOCAUTHCRYPT, &cao)) { + my_perror("ioctl(CIOCAUTHCRYPT)"); + return 1; + } + + enc_len = cao.len; + //printf("Original plaintext size: %d, ciphertext: %d\n", DATA_SIZE, enc_len); + + if (ioctl(cfd, CIOCFSESSION, &sess.ses)) { + my_perror("ioctl(CIOCFSESSION)"); + return 1; + } + + /* Get crypto session for AES128 */ + memset(&sess, 0, sizeof(sess)); + sess.cipher = CRYPTO_AES_GCM; + sess.keylen = KEY_SIZE; + sess.key = key; + + if (ioctl(cfd, CIOCGSESSION, &sess)) { + my_perror("ioctl(CIOCGSESSION)"); + return 1; + } + + /* Decrypt data.encrypted to data.decrypted */ + cao.ses = sess.ses; + cao.auth_src = auth; + cao.auth_len = sizeof(auth); + cao.len = enc_len; + cao.src = ciphertext; + cao.dst = ciphertext; + cao.iv = iv; + cao.iv_len = 12; + cao.op = COP_DECRYPT; + cao.flags = 0; + + if (ioctl(cfd, CIOCAUTHCRYPT, &cao)) { + my_perror("ioctl(CIOCAUTHCRYPT)"); + return 1; + } + + if (cao.len != DATA_SIZE) { + fprintf(stderr, "decrypted data size incorrect!\n"); + return 1; + } + + /* Verify the result */ + if (memcmp(plaintext, ciphertext, DATA_SIZE) != 0) { + int i; + fprintf(stderr, + "FAIL: Decrypted data are different from the input data.\n"); + printf("plaintext:"); + for (i = 0; i < DATA_SIZE; i++) { + if ((i % 30) == 0) + printf("\n"); + printf("%02x ", plaintext[i]); + } + printf("ciphertext:"); + for (i = 0; i < DATA_SIZE; i++) { + if ((i % 30) == 0) + printf("\n"); + printf("%02x ", ciphertext[i]); + } + printf("\n"); + return 1; + } + + /* Finish crypto session */ + if (ioctl(cfd, CIOCFSESSION, &sess.ses)) { + my_perror("ioctl(CIOCFSESSION)"); + return 1; + } + + if (debug) { + fprintf(stdout, "ok\n"); + fprintf(stdout, "\n"); + } + + return 0; +} + +static int test_encrypt_decrypt_error(int cfd, int err) +{ + uint8_t plaintext_raw[DATA_SIZE + 63], *plaintext; + uint8_t ciphertext_raw[DATA_SIZE + 63], *ciphertext; + uint8_t iv[BLOCK_SIZE]; + uint8_t key[KEY_SIZE]; + uint8_t auth[AUTH_SIZE]; + int enc_len; + + struct session_op sess; + struct crypt_op co; + struct crypt_auth_op cao; + struct session_info_op siop; + + if (debug) { + fprintf(stdout, "Tests on AES-GCM tag verification: "); + fflush(stdout); + } + + memset(&sess, 0, sizeof(sess)); + memset(&cao, 0, sizeof(cao)); + memset(&co, 0, sizeof(co)); + + memset(key, 0x33, sizeof(key)); + memset(iv, 0x03, sizeof(iv)); + memset(auth, 0xf1, sizeof(auth)); + + /* Get crypto session for AES128 */ + sess.cipher = CRYPTO_AES_CBC; + sess.keylen = KEY_SIZE; + sess.key = key; + + sess.mac = CRYPTO_SHA1_HMAC; + sess.mackeylen = 16; + sess.mackey = + (uint8_t *) + "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"; + + if (ioctl(cfd, CIOCGSESSION, &sess)) { + my_perror("ioctl(CIOCGSESSION)"); + return 1; + } + + siop.ses = sess.ses; + if (ioctl(cfd, CIOCGSESSINFO, &siop)) { + my_perror("ioctl(CIOCGSESSINFO)"); + return 1; + } +// printf("requested cipher CRYPTO_AES_CBC/HMAC-SHA1, got %s with driver %s\n", +// siop.cipher_info.cra_name, siop.cipher_info.cra_driver_name); + + plaintext = (uint8_t *)buf_align(plaintext_raw, siop.alignmask); + ciphertext = (uint8_t *)buf_align(ciphertext_raw, siop.alignmask); + + memset(plaintext, 0x15, DATA_SIZE); + memcpy(ciphertext, plaintext, DATA_SIZE); + + /* Encrypt data.in to data.encrypted */ + cao.ses = sess.ses; + cao.auth_src = auth; + cao.auth_len = sizeof(auth); + cao.len = DATA_SIZE; + cao.src = ciphertext; + cao.dst = ciphertext; + cao.iv = iv; + cao.op = COP_ENCRYPT; + cao.flags = COP_FLAG_AEAD_TLS_TYPE; + + if (ioctl(cfd, CIOCAUTHCRYPT, &cao)) { + my_perror("ioctl(CIOCAUTHCRYPT)"); + return 1; + } + + enc_len = cao.len; + //printf("Original plaintext size: %d, ciphertext: %d\n", DATA_SIZE, enc_len); + + if (ioctl(cfd, CIOCFSESSION, &sess.ses)) { + my_perror("ioctl(CIOCFSESSION)"); + return 1; + } + + /* Get crypto session for AES128 */ + memset(&sess, 0, sizeof(sess)); + sess.cipher = CRYPTO_AES_CBC; + sess.keylen = KEY_SIZE; + sess.key = key; + sess.mac = CRYPTO_SHA1_HMAC; + sess.mackeylen = 16; + sess.mackey = + (uint8_t *) + "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"; + + if (ioctl(cfd, CIOCGSESSION, &sess)) { + my_perror("ioctl(CIOCGSESSION)"); + return 1; + } + + if (err == 0) + auth[2]++; + else + ciphertext[4]++; + + /* Decrypt data.encrypted to data.decrypted */ + cao.ses = sess.ses; + cao.auth_src = auth; + cao.auth_len = sizeof(auth); + cao.len = enc_len; + cao.src = ciphertext; + cao.dst = ciphertext; + cao.iv = iv; + cao.op = COP_DECRYPT; + cao.flags = COP_FLAG_AEAD_TLS_TYPE; + if (ioctl(cfd, CIOCAUTHCRYPT, &cao)) { + if (ioctl(cfd, CIOCFSESSION, &sess.ses)) { + my_perror("ioctl(CIOCFSESSION)"); + return 1; + } + + if (debug) { + fprintf(stdout, "ok\n"); + fprintf(stdout, "\n"); + } + return 0; + } + + /* Finish crypto session */ + if (ioctl(cfd, CIOCFSESSION, &sess.ses)) { + my_perror("ioctl(CIOCFSESSION)"); + return 1; + } + + + fprintf(stderr, "Modification to ciphertext was not detected\n"); + return 1; +} + +int main(int argc, char** argv) +{ + int fd = -1, cfd = -1; + + if (argc > 1) debug = 1; + + /* Open the crypto device */ + fd = open("/dev/crypto", O_RDWR, 0); + if (fd < 0) { + my_perror("open(/dev/crypto)"); + return 1; + } + + /* Clone file descriptor */ + if (ioctl(fd, CRIOGET, &cfd)) { + my_perror("ioctl(CRIOGET)"); + return 1; + } + + /* Set close-on-exec (not really neede here) */ + if (fcntl(cfd, F_SETFD, 1) == -1) { + my_perror("fcntl(F_SETFD)"); + return 1; + } + + /* Run the test itself */ + + if (test_crypto(cfd)) + return 1; + + if (test_encrypt_decrypt(cfd)) + return 1; + + if (test_encrypt_decrypt_error(cfd, 0)) + return 1; + + if (test_encrypt_decrypt_error(cfd, 1)) + return 1; + + /* Close cloned descriptor */ + if (close(cfd)) { + my_perror("close(cfd)"); + return 1; + } + + /* Close the original descriptor */ + if (close(fd)) { + my_perror("close(fd)"); + return 1; + } + + return 0; +} diff --git a/drivers/cryptodev-linux-master/tests/cipher.c b/drivers/cryptodev-linux-master/tests/cipher.c new file mode 100644 index 00000000..fab3de6b --- /dev/null +++ b/drivers/cryptodev-linux-master/tests/cipher.c @@ -0,0 +1,327 @@ +/* + * Demo on how to use /dev/crypto device for ciphering. + * + * Placed under public domain. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include "testhelper.h" + +static int debug = 0; + +#define DATA_SIZE 8*1024 +#define BLOCK_SIZE 16 +#define KEY_SIZE 16 + +static int +test_crypto(int cfd) +{ + uint8_t plaintext_raw[DATA_SIZE + 63], *plaintext; + uint8_t ciphertext_raw[DATA_SIZE + 63], *ciphertext; + uint8_t iv[BLOCK_SIZE]; + uint8_t key[KEY_SIZE]; + + struct session_op sess; +#ifdef CIOCGSESSINFO + struct session_info_op siop; +#endif + struct crypt_op cryp; + + memset(&sess, 0, sizeof(sess)); + memset(&cryp, 0, sizeof(cryp)); + + memset(key, 0x33, sizeof(key)); + memset(iv, 0x03, sizeof(iv)); + + /* Get crypto session for AES128 */ + sess.cipher = CRYPTO_AES_CBC; + sess.keylen = KEY_SIZE; + sess.key = key; + if (ioctl(cfd, CIOCGSESSION, &sess)) { + perror("ioctl(CIOCGSESSION)"); + return 1; + } + +#ifdef CIOCGSESSINFO + siop.ses = sess.ses; + if (ioctl(cfd, CIOCGSESSINFO, &siop)) { + perror("ioctl(CIOCGSESSINFO)"); + return 1; + } + if (debug) + printf("requested cipher CRYPTO_AES_CBC, got %s with driver %s\n", + siop.cipher_info.cra_name, siop.cipher_info.cra_driver_name); + + plaintext = buf_align(plaintext_raw, siop.alignmask); + ciphertext = buf_align(ciphertext_raw, siop.alignmask); +#else + plaintext = plaintext_raw; + ciphertext = ciphertext_raw; +#endif + memset(plaintext, 0x15, DATA_SIZE); + + /* Encrypt data.in to data.encrypted */ + cryp.ses = sess.ses; + cryp.len = DATA_SIZE; + cryp.src = plaintext; + cryp.dst = ciphertext; + cryp.iv = iv; + cryp.op = COP_ENCRYPT; + if (ioctl(cfd, CIOCCRYPT, &cryp)) { + perror("ioctl(CIOCCRYPT)"); + return 1; + } + + if (ioctl(cfd, CIOCFSESSION, &sess.ses)) { + perror("ioctl(CIOCFSESSION)"); + return 1; + } + + if (ioctl(cfd, CIOCGSESSION, &sess)) { + perror("ioctl(CIOCGSESSION)"); + return 1; + } + +#ifdef CIOCGSESSINFO + siop.ses = sess.ses; + if (ioctl(cfd, CIOCGSESSINFO, &siop)) { + perror("ioctl(CIOCGSESSINFO)"); + return 1; + } + if (debug) + printf("requested cipher CRYPTO_AES_CBC, got %s with driver %s\n", + siop.cipher_info.cra_name, siop.cipher_info.cra_driver_name); +#endif + + /* Decrypt data.encrypted to data.decrypted */ + cryp.ses = sess.ses; + cryp.len = DATA_SIZE; + cryp.src = ciphertext; + cryp.dst = ciphertext; + cryp.iv = iv; + cryp.op = COP_DECRYPT; + if (ioctl(cfd, CIOCCRYPT, &cryp)) { + perror("ioctl(CIOCCRYPT)"); + return 1; + } + + /* Verify the result */ + if (memcmp(plaintext, ciphertext, DATA_SIZE) != 0) { + int i; + fprintf(stderr, + "FAIL: Decrypted data are different from the input data.\n"); + printf("plaintext:"); + for (i = 0; i < DATA_SIZE; i++) { + if ((i % 30) == 0) + printf("\n"); + printf("%02x ", plaintext[i]); + } + printf("ciphertext:"); + for (i = 0; i < DATA_SIZE; i++) { + if ((i % 30) == 0) + printf("\n"); + printf("%02x ", ciphertext[i]); + } + printf("\n"); + return 1; + } else if (debug) + printf("Test passed\n"); + + /* Finish crypto session */ + if (ioctl(cfd, CIOCFSESSION, &sess.ses)) { + perror("ioctl(CIOCFSESSION)"); + return 1; + } + + return 0; +} + +static int test_aes(int cfd) +{ + uint8_t plaintext1_raw[BLOCK_SIZE + 63], *plaintext1; + uint8_t ciphertext1[BLOCK_SIZE] = { 0xdf, 0x55, 0x6a, 0x33, 0x43, 0x8d, 0xb8, 0x7b, 0xc4, 0x1b, 0x17, 0x52, 0xc5, 0x5e, 0x5e, 0x49 }; + uint8_t iv1[BLOCK_SIZE]; + uint8_t key1[KEY_SIZE] = { 0xff, 0xff, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + uint8_t plaintext2_data[BLOCK_SIZE] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xc0, 0x00 }; + uint8_t plaintext2_raw[BLOCK_SIZE + 63], *plaintext2; + uint8_t ciphertext2[BLOCK_SIZE] = { 0xb7, 0x97, 0x2b, 0x39, 0x41, 0xc4, 0x4b, 0x90, 0xaf, 0xa7, 0xb2, 0x64, 0xbf, 0xba, 0x73, 0x87 }; + uint8_t iv2[BLOCK_SIZE]; + uint8_t key2[KEY_SIZE]; + + struct session_op sess; +#ifdef CIOCGSESSINFO + struct session_info_op siop; +#endif + struct crypt_op cryp; + + memset(&sess, 0, sizeof(sess)); + memset(&cryp, 0, sizeof(cryp)); + + /* Get crypto session for AES128 */ + sess.cipher = CRYPTO_AES_CBC; + sess.keylen = KEY_SIZE; + sess.key = key1; + if (ioctl(cfd, CIOCGSESSION, &sess)) { + perror("ioctl(CIOCGSESSION)"); + return 1; + } +#ifdef CIOCGSESSINFO + siop.ses = sess.ses; + if (ioctl(cfd, CIOCGSESSINFO, &siop)) { + perror("ioctl(CIOCGSESSINFO)"); + return 1; + } + plaintext1 = buf_align(plaintext1_raw, siop.alignmask); +#else + plaintext1 = plaintext1_raw; +#endif + memset(plaintext1, 0x0, BLOCK_SIZE); + memset(iv1, 0x0, sizeof(iv1)); + + /* Encrypt data.in to data.encrypted */ + cryp.ses = sess.ses; + cryp.len = BLOCK_SIZE; + cryp.src = plaintext1; + cryp.dst = plaintext1; + cryp.iv = iv1; + cryp.op = COP_ENCRYPT; + if (ioctl(cfd, CIOCCRYPT, &cryp)) { + perror("ioctl(CIOCCRYPT)"); + return 1; + } + + /* Verify the result */ + if (memcmp(plaintext1, ciphertext1, BLOCK_SIZE) != 0) { + fprintf(stderr, + "FAIL: Decrypted data are different from the input data.\n"); + return 1; + } + + /* Test 2 */ + + memset(key2, 0x0, sizeof(key2)); + memset(iv2, 0x0, sizeof(iv2)); + + /* Get crypto session for AES128 */ + sess.cipher = CRYPTO_AES_CBC; + sess.keylen = KEY_SIZE; + sess.key = key2; + if (ioctl(cfd, CIOCGSESSION, &sess)) { + perror("ioctl(CIOCGSESSION)"); + return 1; + } + +#ifdef CIOCGSESSINFO + siop.ses = sess.ses; + if (ioctl(cfd, CIOCGSESSINFO, &siop)) { + perror("ioctl(CIOCGSESSINFO)"); + return 1; + } + if (debug) + printf("requested cipher CRYPTO_AES_CBC, got %s with driver %s\n", + siop.cipher_info.cra_name, siop.cipher_info.cra_driver_name); + + plaintext2 = buf_align(plaintext2_raw, siop.alignmask); +#else + plaintext2 = plaintext2_raw; +#endif + memcpy(plaintext2, plaintext2_data, BLOCK_SIZE); + + /* Encrypt data.in to data.encrypted */ + cryp.ses = sess.ses; + cryp.len = BLOCK_SIZE; + cryp.src = plaintext2; + cryp.dst = plaintext2; + cryp.iv = iv2; + cryp.op = COP_ENCRYPT; + if (ioctl(cfd, CIOCCRYPT, &cryp)) { + perror("ioctl(CIOCCRYPT)"); + return 1; + } + + /* Verify the result */ + if (memcmp(plaintext2, ciphertext2, BLOCK_SIZE) != 0) { + int i; + fprintf(stderr, + "FAIL: Decrypted data are different from the input data.\n"); + printf("plaintext:"); + for (i = 0; i < BLOCK_SIZE; i++) { + if ((i % 30) == 0) + printf("\n"); + printf("%02x ", plaintext2[i]); + } + printf("ciphertext:"); + for (i = 0; i < BLOCK_SIZE; i++) { + if ((i % 30) == 0) + printf("\n"); + printf("%02x ", ciphertext2[i]); + } + printf("\n"); + return 1; + } + + if (debug) printf("AES Test passed\n"); + + /* Finish crypto session */ + if (ioctl(cfd, CIOCFSESSION, &sess.ses)) { + perror("ioctl(CIOCFSESSION)"); + return 1; + } + + return 0; +} + +int +main(int argc, char** argv) +{ + int fd = -1, cfd = -1; + + if (argc > 1) debug = 1; + + /* Open the crypto device */ + fd = open("/dev/crypto", O_RDWR, 0); + if (fd < 0) { + perror("open(/dev/crypto)"); + return 1; + } + + /* Clone file descriptor */ + if (ioctl(fd, CRIOGET, &cfd)) { + perror("ioctl(CRIOGET)"); + return 1; + } + + /* Set close-on-exec (not really neede here) */ + if (fcntl(cfd, F_SETFD, 1) == -1) { + perror("fcntl(F_SETFD)"); + return 1; + } + + /* Run the test itself */ + if (test_aes(cfd)) + return 1; + + if (test_crypto(cfd)) + return 1; + + /* Close cloned descriptor */ + if (close(cfd)) { + perror("close(cfd)"); + return 1; + } + + /* Close the original descriptor */ + if (close(fd)) { + perror("close(fd)"); + return 1; + } + + return 0; +} + diff --git a/drivers/cryptodev-linux-master/tests/cipher_comp.c b/drivers/cryptodev-linux-master/tests/cipher_comp.c new file mode 100644 index 00000000..dbf99778 --- /dev/null +++ b/drivers/cryptodev-linux-master/tests/cipher_comp.c @@ -0,0 +1,159 @@ +/* + * Compare encryption results with ones from openssl. + * + * Placed under public domain. + * + */ +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "openssl_wrapper.h" + +#define BLOCK_SIZE 16 +#define KEY_SIZE 16 +#define MAX_DATALEN (64 * 1024) + + +static int +test_crypto(int cfd, struct session_op *sess, int datalen) +{ + uint8_t *data, *encrypted; + uint8_t *encrypted_comp; + + uint8_t iv_in[BLOCK_SIZE]; + uint8_t iv[BLOCK_SIZE]; + uint8_t iv_comp[BLOCK_SIZE]; + + struct crypt_op cryp; + + int ret = 0; + + data = malloc(datalen); + encrypted = malloc(datalen); + encrypted_comp = malloc(datalen); + memset(data, datalen & 0xff, datalen); + memset(encrypted, 0x27, datalen); + memset(encrypted_comp, 0x41, datalen); + + memset(iv_in, 0x23, sizeof(iv_in)); + memcpy(iv, iv_in, sizeof(iv)); + memcpy(iv_comp, iv_in, sizeof(iv_comp)); + + memset(&cryp, 0, sizeof(cryp)); + + /* Encrypt data.in to data.encrypted */ + cryp.ses = sess->ses; + cryp.len = datalen; + cryp.src = data; + cryp.dst = encrypted; + cryp.iv = iv; + cryp.op = COP_ENCRYPT; + cryp.flags = COP_FLAG_WRITE_IV; + if ((ret = ioctl(cfd, CIOCCRYPT, &cryp))) { + perror("ioctl(CIOCCRYPT)"); + goto out; + } + + cryp.dst = encrypted_comp; + cryp.iv = iv_comp; + + if ((ret = openssl_cioccrypt(sess, &cryp))) { + fprintf(stderr, "openssl_cioccrypt() failed!\n"); + goto out; + } + + if ((ret = memcmp(encrypted, encrypted_comp, cryp.len))) { + printf("fail for datalen %d, cipher texts do not match!\n", datalen); + } + if ((ret = memcmp(iv, iv_comp, BLOCK_SIZE))) { + printf("fail for datalen %d, IVs do not match!\n", datalen); + } +out: + free(data); + free(encrypted); + free(encrypted_comp); + return ret; +} + +#define max(a, b) ((a) > (b) ? (a) : (b)) +#define min(a, b) ((a) < (b) ? (a) : (b)) + +int +main(int argc, char **argv) +{ + int fd; + struct session_op sess; + uint8_t key[KEY_SIZE]; + int datalen = BLOCK_SIZE; + int datalen_end = MAX_DATALEN; + int i; + + if (argc > 1) { + datalen = min(max(atoi(argv[1]), BLOCK_SIZE), MAX_DATALEN); + datalen_end = datalen; + } + if (argc > 2) { + datalen_end = min(atoi(argv[2]), MAX_DATALEN); + if (datalen_end < datalen) + datalen_end = datalen; + } + + /* Open the crypto device */ + fd = open("/dev/crypto", O_RDWR, 0); + if (fd < 0) { + perror("open(/dev/crypto)"); + return 1; + } + + for (i = 0; i < KEY_SIZE; i++) + key[i] = i & 0xff; + memset(&sess, 0, sizeof(sess)); + + /* encryption test */ + sess.cipher = CRYPTO_AES_CBC; + sess.keylen = KEY_SIZE; + sess.key = key; + if (ioctl(fd, CIOCGSESSION, &sess)) { + perror("ioctl(CIOCGSESSION)"); + return 1; + } + +#ifdef CIOCGSESSINFO + { + struct session_info_op siop = { + .ses = sess.ses, + }; + + if (ioctl(fd, CIOCGSESSINFO, &siop)) { + perror("ioctl(CIOCGSESSINFO)"); + } else { + printf("requested cipher CRYPTO_AES_CBC and mac CRYPTO_SHA1_HMAC," + " got cipher %s with driver %s and hash %s with driver %s\n", + siop.cipher_info.cra_name, siop.cipher_info.cra_driver_name, + siop.hash_info.cra_name, siop.hash_info.cra_driver_name); + } + } +#endif + + for (; datalen <= datalen_end; datalen += BLOCK_SIZE) { + if (test_crypto(fd, &sess, datalen)) { + printf("test_crypto() failed for datalen of %d\n", datalen); + return 1; + } + } + + /* Finish crypto session */ + if (ioctl(fd, CIOCFSESSION, &sess.ses)) { + perror("ioctl(CIOCFSESSION)"); + } + + close(fd); + return 0; +} diff --git a/drivers/cryptodev-linux-master/tests/fullspeed.c b/drivers/cryptodev-linux-master/tests/fullspeed.c new file mode 100644 index 00000000..4e97965f --- /dev/null +++ b/drivers/cryptodev-linux-master/tests/fullspeed.c @@ -0,0 +1,185 @@ +/* cryptodev_test - simple benchmark tool for cryptodev + * + * Copyright (C) 2010 by Phil Sutter + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +static int si = 1; /* SI by default */ + +static double udifftimeval(struct timeval start, struct timeval end) +{ + return (double)(end.tv_usec - start.tv_usec) + + (double)(end.tv_sec - start.tv_sec) * 1000 * 1000; +} + +static int must_finish = 0; + +static void alarm_handler(int signo) +{ + must_finish = 1; +} + +static char *units[] = { "", "Ki", "Mi", "Gi", "Ti", 0}; +static char *si_units[] = { "", "K", "M", "G", "T", 0}; + +static void value2human(int si, double bytes, double time, double* data, double* speed,char* metric) +{ + int unit = 0; + + *data = bytes; + + if (si) { + while (*data > 1000 && si_units[unit + 1]) { + *data /= 1000; + unit++; + } + *speed = *data / time; + sprintf(metric, "%sB", si_units[unit]); + } else { + while (*data > 1024 && units[unit + 1]) { + *data /= 1024; + unit++; + } + *speed = *data / time; + sprintf(metric, "%sB", units[unit]); + } +} + +#define MAX(x,y) ((x)>(y)?(x):(y)) + +int encrypt_data(int algo, void* keybuf, int key_size, int fdc, int chunksize) +{ + struct crypt_op cop; + uint8_t *buffer, iv[32]; + static int val = 23; + struct timeval start, end; + double total = 0; + double secs, ddata, dspeed; + char metric[16]; + struct session_op sess; + + if (posix_memalign((void **)&buffer, 16, chunksize)) { + printf("posix_memalign() failed! (mask %x, size: %d)\n", 16, chunksize); + return 1; + } + + memset(iv, 0x23, 32); + + printf("\tEncrypting in chunks of %d bytes: ", chunksize); + fflush(stdout); + + memset(buffer, val++, chunksize); + + must_finish = 0; + alarm(5); + + gettimeofday(&start, NULL); + do { + memset(&sess, 0, sizeof(sess)); + sess.cipher = algo; + sess.keylen = key_size; + sess.key = keybuf; + if (ioctl(fdc, CIOCGSESSION, &sess)) { + perror("ioctl(CIOCGSESSION)"); + return 1; + } + + memset(&cop, 0, sizeof(cop)); + cop.ses = sess.ses; + cop.len = chunksize; + cop.iv = (unsigned char *)iv; + cop.op = COP_ENCRYPT; + cop.src = (unsigned char *)buffer; + cop.dst = buffer; + + if (ioctl(fdc, CIOCCRYPT, &cop)) { + perror("ioctl(CIOCCRYPT)"); + return 1; + } + + ioctl(fdc, CIOCFSESSION, &sess.ses); + + total+=chunksize; + } while(must_finish==0); + gettimeofday(&end, NULL); + + secs = udifftimeval(start, end)/ 1000000.0; + + value2human(si, total, secs, &ddata, &dspeed, metric); + printf ("done. %.2f %s in %.2f secs: ", ddata, metric, secs); + printf ("%.2f %s/sec\n", dspeed, metric); + + free(buffer); + return 0; +} + +int main(int argc, char** argv) +{ + int fd, i, fdc = -1; + char keybuf[32]; + + signal(SIGALRM, alarm_handler); + + if (argc > 1) { + if (strcmp(argv[1], "--help") == 0 || strcmp(argv[1], "-h") == 0) { + printf("Usage: speed [--kib]\n"); + exit(0); + } + if (strcmp(argv[1], "--kib") == 0) { + si = 0; + } + } + + if ((fd = open("/dev/crypto", O_RDWR, 0)) < 0) { + perror("open()"); + return 1; + } + if (ioctl(fd, CRIOGET, &fdc)) { + perror("ioctl(CRIOGET)"); + return 1; + } + + fprintf(stderr, "Testing NULL cipher: \n"); + + for (i = 512; i <= (64 * 1024); i *= 2) { + if (encrypt_data(CRYPTO_NULL, keybuf, 0, fdc, i)) + break; + } + + fprintf(stderr, "\nTesting AES-128-CBC cipher: \n"); + memset(keybuf, 0x42, 16); + + for (i = 512; i <= (64 * 1024); i *= 2) { + if (encrypt_data(CRYPTO_AES_CBC, keybuf, 16, fdc, i)) + break; + } + + close(fdc); + close(fd); + return 0; +} diff --git a/drivers/cryptodev-linux-master/tests/hash_comp.c b/drivers/cryptodev-linux-master/tests/hash_comp.c new file mode 100644 index 00000000..73f85ede --- /dev/null +++ b/drivers/cryptodev-linux-master/tests/hash_comp.c @@ -0,0 +1,147 @@ +/* + * Compare digest results with ones from openssl. + * + * Placed under public domain. + * + */ +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "openssl_wrapper.h" + +#define BLOCK_SIZE 16 +#define MAX_DATALEN (64 * 1024) + +static void printhex(unsigned char *buf, int buflen) +{ + while (buflen-- > 0) { + printf("\\x%.2x", *(buf++)); + } + printf("\n"); +} + +static int +test_crypto(int cfd, struct session_op *sess, int datalen) +{ + uint8_t *data; + uint8_t mac[AALG_MAX_RESULT_LEN]; + uint8_t mac_comp[AALG_MAX_RESULT_LEN]; + + struct crypt_op cryp; + + int ret = 0; + + data = malloc(datalen); + memset(data, datalen & 0xff, datalen); + + memset(mac, 0, sizeof(mac)); + memset(mac_comp, 0, sizeof(mac_comp)); + + memset(&cryp, 0, sizeof(cryp)); + + /* Encrypt data.in to data.encrypted */ + cryp.ses = sess->ses; + cryp.len = datalen; + cryp.src = data; + cryp.mac = mac; + cryp.op = COP_ENCRYPT; + if ((ret = ioctl(cfd, CIOCCRYPT, &cryp))) { + perror("ioctl(CIOCCRYPT)"); + goto out; + } + + cryp.mac = mac_comp; + + if ((ret = openssl_cioccrypt(sess, &cryp))) { + fprintf(stderr, "openssl_cioccrypt() failed!\n"); + goto out; + } + + if (memcmp(mac, mac_comp, AALG_MAX_RESULT_LEN)) { + printf("fail for datalen %d, MACs do not match!\n", datalen); + ret = 1; + printf("wrong mac: "); + printhex(mac, 20); + printf("right mac: "); + printhex(mac_comp, 20); + } + +out: + free(data); + return ret; +} + +#define max(a, b) ((a) > (b) ? (a) : (b)) +#define min(a, b) ((a) < (b) ? (a) : (b)) + +int +main(int argc, char **argv) +{ + int fd; + struct session_op sess; + int datalen = BLOCK_SIZE; + int datalen_end = MAX_DATALEN; + + if (argc > 1) { + datalen = min(max(atoi(argv[1]), BLOCK_SIZE), MAX_DATALEN); + datalen_end = datalen; + } + if (argc > 2) { + datalen_end = min(atoi(argv[2]), MAX_DATALEN); + if (datalen_end < datalen) + datalen_end = datalen; + } + + /* Open the crypto device */ + fd = open("/dev/crypto", O_RDWR, 0); + if (fd < 0) { + perror("open(/dev/crypto)"); + return 1; + } + + memset(&sess, 0, sizeof(sess)); + + /* Hash test */ + sess.mac = CRYPTO_SHA1; + if (ioctl(fd, CIOCGSESSION, &sess)) { + perror("ioctl(CIOCGSESSION)"); + return 1; + } + +#ifdef CIOCGSESSINFO + { + struct session_info_op siop = { + .ses = sess.ses, + }; + + if (ioctl(fd, CIOCGSESSINFO, &siop)) { + perror("ioctl(CIOCGSESSINFO)"); + } else { + printf("requested mac CRYPTO_SHA1, got hash %s with driver %s\n", + siop.hash_info.cra_name, siop.hash_info.cra_driver_name); + } + } +#endif + + for (; datalen <= datalen_end; datalen += BLOCK_SIZE) { + if (test_crypto(fd, &sess, datalen)) { + printf("test_crypto() failed for datalen of %d\n", datalen); + return 1; + } + } + + /* Finish crypto session */ + if (ioctl(fd, CIOCFSESSION, &sess.ses)) { + perror("ioctl(CIOCFSESSION)"); + } + + close(fd); + return 0; +} diff --git a/drivers/cryptodev-linux-master/tests/hashcrypt_speed.c b/drivers/cryptodev-linux-master/tests/hashcrypt_speed.c new file mode 100644 index 00000000..2b49f2b6 --- /dev/null +++ b/drivers/cryptodev-linux-master/tests/hashcrypt_speed.c @@ -0,0 +1,207 @@ +/* hashcrypt_speed - simple SHA+AES benchmark tool for cryptodev + * + * Copyright (C) 2011 by Phil Sutter + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX(x,y) ((x)>(y)?(x):(y)) + +static double udifftimeval(struct timeval start, struct timeval end) +{ + return (double)(end.tv_usec - start.tv_usec) + + (double)(end.tv_sec - start.tv_sec) * 1000 * 1000; +} + +static int must_finish = 0; + +static void alarm_handler(int signo) +{ + must_finish = 1; +} + +static char *units[] = { "", "Ki", "Mi", "Gi", "Ti", 0}; +static char *si_units[] = { "", "K", "M", "G", "T", 0}; + +static void value2human(int si, double bytes, double time, double* data, double* speed,char* metric) +{ + int unit = 0; + + *data = bytes; + + if (si) { + while (*data > 1000 && si_units[unit + 1]) { + *data /= 1000; + unit++; + } + *speed = *data / time; + sprintf(metric, "%sB", si_units[unit]); + } else { + while (*data > 1024 && units[unit + 1]) { + *data /= 1024; + unit++; + } + *speed = *data / time; + sprintf(metric, "%sB", units[unit]); + } +} + + +int hash_data(struct session_op *sess, int fdc, int chunksize, int align) +{ + struct crypt_op cop; + char *buffer; + static int val = 23; + struct timeval start, end; + double total = 0; + double secs, ddata, dspeed; + char metric[16]; + uint8_t mac[AALG_MAX_RESULT_LEN]; + + if (align) { + if (posix_memalign((void **)&buffer, align, chunksize)) { + printf("posix_memalign() failed, align: %d, size: %d!\n", align, chunksize); + return 1; + } + } else { + if (!(buffer = malloc(chunksize))) { + perror("malloc()"); + return 1; + } + } + + printf("\tEncrypting in chunks of %d bytes: ", chunksize); + fflush(stdout); + + memset(buffer, val++, chunksize); + + must_finish = 0; + alarm(5); + + gettimeofday(&start, NULL); + do { + memset(&cop, 0, sizeof(cop)); + cop.ses = sess->ses; + cop.len = chunksize; + cop.op = COP_ENCRYPT; + cop.src = cop.dst = (unsigned char *)buffer; + cop.mac = mac; + + if (ioctl(fdc, CIOCCRYPT, &cop)) { + perror("ioctl(CIOCCRYPT)"); + return 1; + } + total+=chunksize; + } while(must_finish==0); + gettimeofday(&end, NULL); + + secs = udifftimeval(start, end)/ 1000000.0; + + value2human(1, total, secs, &ddata, &dspeed, metric); + printf ("done. %.2f %s in %.2f secs: ", ddata, metric, secs); + printf ("%.2f %s/sec\n", dspeed, metric); + + free(buffer); + return 0; +} + +int main(void) +{ + int fd, i, fdc = -1, align = 0; + struct session_op sess; + char keybuf[32]; +#ifdef CIOCGSESSINFO + struct session_info_op siop; +#endif + + signal(SIGALRM, alarm_handler); + + if ((fd = open("/dev/crypto", O_RDWR, 0)) < 0) { + perror("open()"); + return 1; + } + if (ioctl(fd, CRIOGET, &fdc)) { + perror("ioctl(CRIOGET)"); + return 1; + } + + fprintf(stderr, "Testing AES128 with SHA1 Hash: \n"); + memset(&sess, 0, sizeof(sess)); + sess.cipher = CRYPTO_AES_CBC; + sess.keylen = 16; + memset(keybuf, 0x42, 32); + sess.key = (unsigned char *)keybuf; + sess.mac = CRYPTO_SHA1; + if (ioctl(fdc, CIOCGSESSION, &sess)) { + perror("ioctl(CIOCGSESSION)"); + return 1; + } +#ifdef CIOCGSESSINFO + siop.ses = sess.ses; + if (ioctl(fdc, CIOCGSESSINFO, &siop)) { + perror("ioctl(CIOCGSESSINFO)"); + return 1; + } + printf("requested hash CRYPTO_SHA1, got %s with driver %s\n", + siop.hash_info.cra_name, siop.hash_info.cra_driver_name); + align = MAX(sizeof(void*), siop.alignmask+1); +#endif + + for (i = 256; i <= (64 * 1024); i *= 4) { + if (hash_data(&sess, fdc, i, align)) + break; + } + + fprintf(stderr, "\nTesting AES256 with SHA256 Hash: \n"); + memset(&sess, 0, sizeof(sess)); + sess.cipher = CRYPTO_AES_CBC; + sess.keylen = 32; + sess.key = (unsigned char *)keybuf; + sess.mac = CRYPTO_SHA2_256; + if (ioctl(fdc, CIOCGSESSION, &sess)) { + perror("ioctl(CIOCGSESSION)"); + return 1; + } +#ifdef CIOCGSESSINFO + siop.ses = sess.ses; + if (ioctl(fdc, CIOCGSESSINFO, &siop)) { + perror("ioctl(CIOCGSESSINFO)"); + return 1; + } + printf("requested hash CRYPTO_SHA2_256, got %s with driver %s\n", + siop.hash_info.cra_name, siop.hash_info.cra_driver_name); + align = MAX(sizeof(void*), siop.alignmask+1); +#endif + + for (i = 256; i <= (64 * 1024); i *= 4) { + if (hash_data(&sess, fdc, i, align)) + break; + } + + close(fdc); + close(fd); + return 0; +} diff --git a/drivers/cryptodev-linux-master/tests/hmac.c b/drivers/cryptodev-linux-master/tests/hmac.c new file mode 100644 index 00000000..8d6492e1 --- /dev/null +++ b/drivers/cryptodev-linux-master/tests/hmac.c @@ -0,0 +1,336 @@ +/* + * Demo on how to use /dev/crypto device for HMAC. + * + * Placed under public domain. + * + */ +#include +#include +#include +#include +#include + +#include +#include + +static int debug = 0; + +#define DATA_SIZE 4096 +#define BLOCK_SIZE 16 +#define KEY_SIZE 16 +#define SHA1_HASH_LEN 20 + +static int +test_crypto(int cfd) +{ + struct { + uint8_t in[DATA_SIZE], + encrypted[DATA_SIZE], + decrypted[DATA_SIZE], + iv[BLOCK_SIZE], + key[KEY_SIZE]; + } data; + struct session_op sess; +#ifdef CIOCGSESSINFO + struct session_info_op siop; +#endif + struct crypt_op cryp; + uint8_t mac[AALG_MAX_RESULT_LEN]; + uint8_t oldmac[AALG_MAX_RESULT_LEN]; + uint8_t md5_hmac_out[] = "\x75\x0c\x78\x3e\x6a\xb0\xb5\x03\xea\xa8\x6e\x31\x0a\x5d\xb7\x38"; + uint8_t sha1_out[] = "\x8f\x82\x03\x94\xf9\x53\x35\x18\x20\x45\xda\x24\xf3\x4d\xe5\x2b\xf8\xbc\x34\x32"; + int i; + + memset(&sess, 0, sizeof(sess)); + memset(&cryp, 0, sizeof(cryp)); + + /* Use the garbage that is on the stack :-) */ + /* memset(&data, 0, sizeof(data)); */ + + /* SHA1 plain test */ + memset(mac, 0, sizeof(mac)); + + sess.cipher = 0; + sess.mac = CRYPTO_SHA1; + if (ioctl(cfd, CIOCGSESSION, &sess)) { + perror("ioctl(CIOCGSESSION)"); + return 1; + } + +#ifdef CIOCGSESSINFO + siop.ses = sess.ses; + if (ioctl(cfd, CIOCGSESSINFO, &siop)) { + perror("ioctl(CIOCGSESSINFO)"); + return 1; + } + if (debug) printf("requested mac CRYPTO_SHA1, got %s with driver %s\n", + siop.hash_info.cra_name, siop.hash_info.cra_driver_name); +#endif + + cryp.ses = sess.ses; + cryp.len = sizeof("what do ya want for nothing?")-1; + cryp.src = (uint8_t *)"what do ya want for nothing?"; + cryp.mac = mac; + cryp.op = COP_ENCRYPT; + if (ioctl(cfd, CIOCCRYPT, &cryp)) { + perror("ioctl(CIOCCRYPT)"); + return 1; + } + + if (memcmp(mac, sha1_out, 20)!=0) { + printf("mac: "); + for (i=0;i 1) debug = 1; + + /* Open the crypto device */ + fd = open("/dev/crypto", O_RDWR, 0); + if (fd < 0) { + perror("open(/dev/crypto)"); + return 1; + } + + /* Clone file descriptor */ + if (ioctl(fd, CRIOGET, &cfd)) { + perror("ioctl(CRIOGET)"); + return 1; + } + + /* Set close-on-exec (not really neede here) */ + if (fcntl(cfd, F_SETFD, 1) == -1) { + perror("fcntl(F_SETFD)"); + return 1; + } + + /* Run the test itself */ + if (test_crypto(cfd)) + return 1; + + if (test_extras(cfd)) + return 1; + + /* Close cloned descriptor */ + if (close(cfd)) { + perror("close(cfd)"); + return 1; + } + + /* Close the original descriptor */ + if (close(fd)) { + perror("close(fd)"); + return 1; + } + + return 0; +} diff --git a/drivers/cryptodev-linux-master/tests/hmac_comp.c b/drivers/cryptodev-linux-master/tests/hmac_comp.c new file mode 100644 index 00000000..a8709cbb --- /dev/null +++ b/drivers/cryptodev-linux-master/tests/hmac_comp.c @@ -0,0 +1,187 @@ +/* + * Compare HMAC results with ones from openssl. + * + * Placed under public domain. + * + */ +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "openssl_wrapper.h" + +#define BLOCK_SIZE 16 +#define KEY_SIZE 16 +#define MACKEY_SIZE 20 +#define MAX_DATALEN (64 * 1024) + +static void printhex(unsigned char *buf, int buflen) +{ + while (buflen-- > 0) { + printf("\\x%.2x", *(buf++)); + } + printf("\n"); +} + +static int +test_crypto(int cfd, struct session_op *sess, int datalen) +{ + unsigned char *data, *encrypted; + unsigned char *encrypted_comp; + + unsigned char iv[BLOCK_SIZE]; + unsigned char mac[AALG_MAX_RESULT_LEN]; + + unsigned char iv_comp[BLOCK_SIZE]; + unsigned char mac_comp[AALG_MAX_RESULT_LEN]; + + struct crypt_op cryp; + + int ret = 0; + + data = malloc(datalen); + encrypted = malloc(datalen); + encrypted_comp = malloc(datalen); + memset(data, datalen & 0xff, datalen); + memset(encrypted, 0x27, datalen); + memset(encrypted_comp, 0x28, datalen); + + memset(iv, 0x23, sizeof(iv)); + memset(iv_comp, 0x23, sizeof(iv)); + memset(mac, 0, sizeof(mac)); + memset(mac_comp, 1, sizeof(mac_comp)); + + memset(&cryp, 0, sizeof(cryp)); + + /* Encrypt data.in to data.encrypted */ + cryp.ses = sess->ses; + cryp.len = datalen; + cryp.src = data; + cryp.dst = encrypted; + cryp.iv = iv; + cryp.mac = mac; + cryp.op = COP_ENCRYPT; + cryp.flags = COP_FLAG_WRITE_IV; + if ((ret = ioctl(cfd, CIOCCRYPT, &cryp))) { + perror("ioctl(CIOCCRYPT)"); + goto out; + } + + cryp.dst = encrypted_comp; + cryp.mac = mac_comp; + cryp.iv = iv_comp; + + if ((ret = openssl_cioccrypt(sess, &cryp))) { + fprintf(stderr, "openssl_cioccrypt() failed!\n"); + goto out; + } + + if ((ret = memcmp(encrypted, encrypted_comp, cryp.len))) { + printf("fail for datalen %d, cipher texts do not match!\n", datalen); + } + if ((ret = memcmp(iv, iv_comp, BLOCK_SIZE))) { + printf("fail for datalen %d, updated IVs do not match!\n", datalen); + } + if ((ret = memcmp(mac, mac_comp, AALG_MAX_RESULT_LEN))) { + printf("fail for datalen 0x%x, MACs do not match!\n", datalen); + printf("wrong mac: "); + printhex(mac, 20); + printf("right mac: "); + printhex(mac_comp, 20); + + } + +out: + free(data); + free(encrypted); + free(encrypted_comp); + return ret; +} + +#define max(a, b) ((a) > (b) ? (a) : (b)) +#define min(a, b) ((a) < (b) ? (a) : (b)) + +int +main(int argc, char **argv) +{ + int fd; + struct session_op sess; + unsigned char key[KEY_SIZE], mackey[MACKEY_SIZE]; + int datalen = BLOCK_SIZE; + int datalen_end = MAX_DATALEN; + int i; + + if (argc > 1) { + datalen = min(max(atoi(argv[1]), BLOCK_SIZE), MAX_DATALEN); + datalen_end = datalen; + } + if (argc > 2) { + datalen_end = min(atoi(argv[2]), MAX_DATALEN); + if (datalen_end < datalen) + datalen_end = datalen; + } + + /* Open the crypto device */ + fd = open("/dev/crypto", O_RDWR, 0); + if (fd < 0) { + perror("open(/dev/crypto)"); + return 1; + } + + for (i = 0; i < KEY_SIZE; i++) + key[i] = i & 0xff; + for (i = 0; i < MACKEY_SIZE; i++) + mackey[i] = i & 0xff; + + memset(&sess, 0, sizeof(sess)); + + /* Hash and encryption in one step test */ + sess.cipher = CRYPTO_AES_CBC; + sess.mac = CRYPTO_SHA1_HMAC; + sess.keylen = KEY_SIZE; + sess.key = key; + sess.mackeylen = MACKEY_SIZE; + sess.mackey = mackey; + if (ioctl(fd, CIOCGSESSION, &sess)) { + perror("ioctl(CIOCGSESSION)"); + return 1; + } + +#ifdef CIOCGSESSINFO + { + struct session_info_op siop = { + .ses = sess.ses, + }; + + if (ioctl(fd, CIOCGSESSINFO, &siop)) { + perror("ioctl(CIOCGSESSINFO)"); + } else { + printf("requested cipher CRYPTO_AES_CBC and mac CRYPTO_SHA1_HMAC," + " got cipher %s with driver %s and hash %s with driver %s\n", + siop.cipher_info.cra_name, siop.cipher_info.cra_driver_name, + siop.hash_info.cra_name, siop.hash_info.cra_driver_name); + } + } +#endif + + for (; datalen <= datalen_end; datalen += BLOCK_SIZE) { + if (test_crypto(fd, &sess, datalen)) { + printf("test_crypto() failed for datalen of %d\n", datalen); + return 1; + } + } + + /* Finish crypto session */ + if (ioctl(fd, CIOCFSESSION, &sess.ses)) { + perror("ioctl(CIOCFSESSION)"); + } + + close(fd); + return 0; +} diff --git a/drivers/cryptodev-linux-master/tests/openssl_wrapper.c b/drivers/cryptodev-linux-master/tests/openssl_wrapper.c new file mode 100644 index 00000000..dea2496d --- /dev/null +++ b/drivers/cryptodev-linux-master/tests/openssl_wrapper.c @@ -0,0 +1,300 @@ +#include +#include +#include +#include +#include +#include +#include + +//#define DEBUG + +#ifdef DEBUG +# define dbgp(...) { \ + fprintf(stderr, "%s:%d: ", __FILE__, __LINE__); \ + fprintf(stderr, __VA_ARGS__); \ + fprintf(stderr, "\n"); \ +} +#else +# define dbgp(...) /* nothing */ +#endif + +enum ctx_type { + ctx_type_none = 0, + ctx_type_hmac, + ctx_type_md, +}; + +#if OPENSSL_VERSION_NUMBER >= 0x10100000L +union openssl_ctx { + HMAC_CTX *hmac; + EVP_MD_CTX *md; +}; +#else +union openssl_ctx { + HMAC_CTX hmac; + EVP_MD_CTX md; +}; +#endif + +struct ctx_mapping { + __u32 ses; + enum ctx_type type; + union openssl_ctx ctx; +}; + +static struct ctx_mapping ctx_map[512]; + +static struct ctx_mapping *find_mapping(__u32 ses) +{ + int i; + + for (i = 0; i < 512; i++) { + if (ctx_map[i].ses == ses) + return &ctx_map[i]; + } + return NULL; +} + +static struct ctx_mapping *new_mapping(void) +{ + return find_mapping(0); +} + +static void remove_mapping(__u32 ses) +{ + struct ctx_mapping *mapping; + + if (!(mapping = find_mapping(ses))) { + printf("%s: failed to find mapping for session %d\n", __func__, ses); + return; + } + switch (mapping->type) { + case ctx_type_none: + break; +#if OPENSSL_VERSION_NUMBER >= 0x10100000L + case ctx_type_hmac: + dbgp("%s: calling HMAC_CTX_free\n", __func__); + HMAC_CTX_free(mapping->ctx.hmac); + break; + case ctx_type_md: + dbgp("%s: calling EVP_MD_CTX_free\n", __func__); + EVP_MD_CTX_free(mapping->ctx.md); + break; +#else + case ctx_type_hmac: + dbgp("%s: calling HMAC_CTX_cleanup\n", __func__); + HMAC_CTX_cleanup(&mapping->ctx.hmac); + break; + case ctx_type_md: + dbgp("%s: calling EVP_MD_CTX_cleanup\n", __func__); + EVP_MD_CTX_cleanup(&mapping->ctx.md); + break; +#endif + } + memset(mapping, 0, sizeof(*mapping)); +} + +static union openssl_ctx *__ses_to_ctx(__u32 ses) +{ + struct ctx_mapping *mapping; + + if (!(mapping = find_mapping(ses))) + return NULL; + return &mapping->ctx; +} + +static HMAC_CTX *ses_to_hmac(__u32 ses) { return (HMAC_CTX *)__ses_to_ctx(ses); } +static EVP_MD_CTX *ses_to_md(__u32 ses) { return (EVP_MD_CTX *)__ses_to_ctx(ses); } + +static const EVP_MD *sess_to_evp_md(struct session_op *sess) +{ + switch (sess->mac) { +#ifndef OPENSSL_NO_MD5 + case CRYPTO_MD5_HMAC: return EVP_md5(); +#endif +#ifndef OPENSSL_NO_SHA + case CRYPTO_SHA1_HMAC: + case CRYPTO_SHA1: + return EVP_sha1(); +#endif +#ifndef OPENSSL_NO_RIPEMD + case CRYPTO_RIPEMD160_HMAC: return EVP_ripemd160(); +#endif +#ifndef OPENSSL_NO_SHA256 + case CRYPTO_SHA2_256_HMAC: return EVP_sha256(); +#endif +#ifndef OPENSSL_NO_SHA512 + case CRYPTO_SHA2_384_HMAC: return EVP_sha384(); + case CRYPTO_SHA2_512_HMAC: return EVP_sha512(); +#endif + default: + printf("%s: failed to get an EVP, things will be broken!\n", __func__); + return NULL; + } +} + +static int openssl_hmac(struct session_op *sess, struct crypt_op *cop) +{ + HMAC_CTX *ctx = ses_to_hmac(sess->ses); + + if (!ctx) { + struct ctx_mapping *mapping = new_mapping(); + if (!mapping) { + printf("%s: failed to get new mapping\n", __func__); + return 1; + } + + mapping->ses = sess->ses; + mapping->type = ctx_type_hmac; +#if OPENSSL_VERSION_NUMBER >= 0x10100000L + ctx = mapping->ctx.hmac; + + dbgp("calling HMAC_CTX_new"); + ctx = HMAC_CTX_new(); +#else + ctx = &mapping->ctx.hmac; + + dbgp("calling HMAC_CTX_init"); + HMAC_CTX_init(ctx); +#endif + dbgp("calling HMAC_Init_ex"); + if (!HMAC_Init_ex(ctx, sess->mackey, sess->mackeylen, + sess_to_evp_md(sess), NULL)) { + printf("%s: HMAC_Init_ex failed\n", __func__); + return 1; + } + } + + if (cop->len) { + dbgp("calling HMAC_Update"); + if (!HMAC_Update(ctx, cop->src, cop->len)) { + printf("%s: HMAC_Update failed\n", __func__); + return 1; + } + } + if (cop->flags & COP_FLAG_FINAL || + (cop->len && !(cop->flags & COP_FLAG_UPDATE))) { + dbgp("calling HMAC_Final"); + if (!HMAC_Final(ctx, cop->mac, 0)) { + printf("%s: HMAC_Final failed\n", __func__); + remove_mapping(sess->ses); + return 1; + } + remove_mapping(sess->ses); + } + return 0; +} + +static int openssl_md(struct session_op *sess, struct crypt_op *cop) +{ + EVP_MD_CTX *ctx = ses_to_md(sess->ses); + + if (!ctx) { + struct ctx_mapping *mapping = new_mapping(); + if (!mapping) { + printf("%s: failed to get new mapping\n", __func__); + return 1; + } + + mapping->ses = sess->ses; + mapping->type = ctx_type_md; +#if OPENSSL_VERSION_NUMBER >= 0x10100000L + ctx = mapping->ctx.md; + + dbgp("calling EVP_MD_CTX_new"); + ctx = EVP_MD_CTX_new(); +#else + ctx = &mapping->ctx.md; + + dbgp("calling EVP_MD_CTX_init"); + EVP_MD_CTX_init(ctx); +#endif + dbgp("calling EVP_DigestInit"); + EVP_DigestInit(ctx, sess_to_evp_md(sess)); + } + + if (cop->len) { + dbgp("calling EVP_DigestUpdate"); + EVP_DigestUpdate(ctx, cop->src, cop->len); + } + if (cop->flags & COP_FLAG_FINAL || + (cop->len && !(cop->flags & COP_FLAG_UPDATE))) { + dbgp("calling EVP_DigestFinal"); + EVP_DigestFinal(ctx, cop->mac, 0); + remove_mapping(sess->ses); + } + + return 0; +} + +static int openssl_aes(struct session_op *sess, struct crypt_op *cop) +{ + AES_KEY key; + int i, enc; + unsigned char ivec[AES_BLOCK_SIZE]; + + if (cop->len % AES_BLOCK_SIZE) { + printf("%s: illegal length passed, " + "not a multiple of AES_BLOCK_SIZE\n", __func__); + return 1; + } + + switch (cop->op) { + case COP_ENCRYPT: + AES_set_encrypt_key(sess->key, sess->keylen * 8, &key); + enc = 1; + break; + case COP_DECRYPT: + AES_set_decrypt_key(sess->key, sess->keylen * 8, &key); + enc = 0; + break; + default: + printf("%s: unknown cop->op received!\n", __func__); + return 1; + } + + switch (sess->cipher) { + case CRYPTO_AES_CBC: + memcpy(ivec, cop->iv, AES_BLOCK_SIZE); + AES_cbc_encrypt(cop->src, cop->dst, cop->len, &key, ivec, enc); + if (cop->flags & COP_FLAG_WRITE_IV) + memcpy(cop->iv, ivec, AES_BLOCK_SIZE); + break; +#if 0 + /* XXX: TODO: implement this stuff */ + case CRYPTO_AES_CTR: + AES_ctr128_encrypt(cop->src, cop->dst, &key, cop->iv, + case CRYPTO_AES_XTS: +#endif + case CRYPTO_AES_ECB: + for (i = 0; i < cop->len; i += AES_BLOCK_SIZE) + AES_ecb_encrypt(cop->src + i, cop->dst + i, &key, enc); + break; + } + return 0; +} + +int openssl_cioccrypt(struct session_op *sess, struct crypt_op *cop) +{ + if (sess->mac && sess->mackey && sess->mackeylen) + openssl_hmac(sess, cop); + else if (sess->mac) + openssl_md(sess, cop); + + switch (sess->cipher) { + case CRYPTO_AES_CBC: + case CRYPTO_AES_CTR: + case CRYPTO_AES_XTS: + case CRYPTO_AES_ECB: + openssl_aes(sess, cop); + break; + case 0: + /* no encryption wanted, everythings fine */ + break; + default: + printf("%s: unknown cipher passed!\n", __func__); + break; + } + + return 0; +} diff --git a/drivers/cryptodev-linux-master/tests/openssl_wrapper.h b/drivers/cryptodev-linux-master/tests/openssl_wrapper.h new file mode 100644 index 00000000..5f1f5162 --- /dev/null +++ b/drivers/cryptodev-linux-master/tests/openssl_wrapper.h @@ -0,0 +1,6 @@ +#ifndef __OPENSSL_WRAPPER_H +#define __OPENSSL_WRAPPER_H + +int openssl_cioccrypt(struct session_op *, struct crypt_op *); + +#endif /* __OPENSSL_WRAPPER_H */ diff --git a/drivers/cryptodev-linux-master/tests/sha_speed.c b/drivers/cryptodev-linux-master/tests/sha_speed.c new file mode 100644 index 00000000..1e672603 --- /dev/null +++ b/drivers/cryptodev-linux-master/tests/sha_speed.c @@ -0,0 +1,198 @@ +/* sha_speed - simple SHA benchmark tool for cryptodev + * + * Copyright (C) 2011 by Phil Sutter + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +static double udifftimeval(struct timeval start, struct timeval end) +{ + return (double)(end.tv_usec - start.tv_usec) + + (double)(end.tv_sec - start.tv_sec) * 1000 * 1000; +} + +static int must_finish = 0; + +static void alarm_handler(int signo) +{ + must_finish = 1; +} + +static char *units[] = { "", "Ki", "Mi", "Gi", "Ti", 0}; +static char *si_units[] = { "", "K", "M", "G", "T", 0}; + +static void value2human(int si, double bytes, double time, double* data, double* speed,char* metric) +{ + int unit = 0; + + *data = bytes; + + if (si) { + while (*data > 1000 && si_units[unit + 1]) { + *data /= 1000; + unit++; + } + *speed = *data / time; + sprintf(metric, "%sB", si_units[unit]); + } else { + while (*data > 1024 && units[unit + 1]) { + *data /= 1024; + unit++; + } + *speed = *data / time; + sprintf(metric, "%sB", units[unit]); + } +} + + +int hash_data(struct session_op *sess, int fdc, int chunksize, int alignmask) +{ + struct crypt_op cop; + char *buffer; + static int val = 23; + struct timeval start, end; + double total = 0; + double secs, ddata, dspeed; + char metric[16]; + uint8_t mac[AALG_MAX_RESULT_LEN]; + + if (alignmask) { + if (posix_memalign((void **)&buffer, alignmask + 1, chunksize)) { + printf("posix_memalign() failed!\n"); + return 1; + } + } else { + if (!(buffer = malloc(chunksize))) { + perror("malloc()"); + return 1; + } + } + + printf("\tEncrypting in chunks of %d bytes: ", chunksize); + fflush(stdout); + + memset(buffer, val++, chunksize); + + must_finish = 0; + alarm(5); + + gettimeofday(&start, NULL); + do { + memset(&cop, 0, sizeof(cop)); + cop.ses = sess->ses; + cop.len = chunksize; + cop.op = COP_ENCRYPT; + cop.src = (unsigned char *)buffer; + cop.mac = mac; + + if (ioctl(fdc, CIOCCRYPT, &cop)) { + perror("ioctl(CIOCCRYPT)"); + return 1; + } + total+=chunksize; + } while(must_finish==0); + gettimeofday(&end, NULL); + + secs = udifftimeval(start, end)/ 1000000.0; + + value2human(1, total, secs, &ddata, &dspeed, metric); + printf ("done. %.2f %s in %.2f secs: ", ddata, metric, secs); + printf ("%.2f %s/sec\n", dspeed, metric); + + free(buffer); + return 0; +} + +int main(void) +{ + int fd, i, fdc = -1, alignmask = 0; + struct session_op sess; +#ifdef CIOCGSESSINFO + struct session_info_op siop; +#endif + + signal(SIGALRM, alarm_handler); + + if ((fd = open("/dev/crypto", O_RDWR, 0)) < 0) { + perror("open()"); + return 1; + } + if (ioctl(fd, CRIOGET, &fdc)) { + perror("ioctl(CRIOGET)"); + return 1; + } + + fprintf(stderr, "Testing SHA1 Hash: \n"); + memset(&sess, 0, sizeof(sess)); + sess.mac = CRYPTO_SHA1; + if (ioctl(fdc, CIOCGSESSION, &sess)) { + perror("ioctl(CIOCGSESSION)"); + return 1; + } +#ifdef CIOCGSESSINFO + siop.ses = sess.ses; + if (ioctl(fdc, CIOCGSESSINFO, &siop)) { + perror("ioctl(CIOCGSESSINFO)"); + return 1; + } + printf("requested hash CRYPTO_SHA1, got %s with driver %s\n", + siop.hash_info.cra_name, siop.hash_info.cra_driver_name); + alignmask = siop.alignmask; +#endif + + for (i = 256; i <= (64 * 1024); i *= 4) { + if (hash_data(&sess, fdc, i, alignmask)) + break; + } + + fprintf(stderr, "\nTesting SHA256 Hash: \n"); + memset(&sess, 0, sizeof(sess)); + sess.mac = CRYPTO_SHA2_256; + if (ioctl(fdc, CIOCGSESSION, &sess)) { + perror("ioctl(CIOCGSESSION)"); + return 1; + } +#ifdef CIOCGSESSINFO + siop.ses = sess.ses; + if (ioctl(fdc, CIOCGSESSINFO, &siop)) { + perror("ioctl(CIOCGSESSINFO)"); + return 1; + } + printf("requested hash CRYPTO_SHA2_256, got %s with driver %s\n", + siop.hash_info.cra_name, siop.hash_info.cra_driver_name); + alignmask = siop.alignmask; +#endif + + for (i = 256; i <= (64 * 1024); i *= 4) { + if (hash_data(&sess, fdc, i, alignmask)) + break; + } + + close(fdc); + close(fd); + return 0; +} diff --git a/drivers/cryptodev-linux-master/tests/speed.c b/drivers/cryptodev-linux-master/tests/speed.c new file mode 100644 index 00000000..951ae096 --- /dev/null +++ b/drivers/cryptodev-linux-master/tests/speed.c @@ -0,0 +1,213 @@ +/* cryptodev_test - simple benchmark tool for cryptodev + * + * Copyright (C) 2010 by Phil Sutter + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +static int si = 1; /* SI by default */ + +static double udifftimeval(struct timeval start, struct timeval end) +{ + return (double)(end.tv_usec - start.tv_usec) + + (double)(end.tv_sec - start.tv_sec) * 1000 * 1000; +} + +static volatile int must_finish; + +static void alarm_handler(int signo) +{ + must_finish = 1; +} + +static char *units[] = { "", "Ki", "Mi", "Gi", "Ti", 0}; +static char *si_units[] = { "", "K", "M", "G", "T", 0}; + +static void value2human(int si, double bytes, double time, double* data, double* speed,char* metric) +{ + int unit = 0; + + *data = bytes; + + if (si) { + while (*data > 1000 && si_units[unit + 1]) { + *data /= 1000; + unit++; + } + *speed = *data / time; + sprintf(metric, "%sB", si_units[unit]); + } else { + while (*data > 1024 && units[unit + 1]) { + *data /= 1024; + unit++; + } + *speed = *data / time; + sprintf(metric, "%sB", units[unit]); + } +} + +#define MAX(x,y) ((x)>(y)?(x):(y)) + +int encrypt_data(struct session_op *sess, int fdc, int chunksize, int alignmask) +{ + struct crypt_op cop; + char *buffer, iv[32]; + static int val = 23; + struct timeval start, end; + double total = 0; + double secs, ddata, dspeed; + char metric[16]; + + if (alignmask) { + if (posix_memalign((void **)&buffer, MAX(alignmask + 1, sizeof(void*)), chunksize)) { + printf("posix_memalign() failed! (mask %x, size: %d)\n", alignmask+1, chunksize); + return 1; + } + } else { + if (!(buffer = malloc(chunksize))) { + perror("malloc()"); + return 1; + } + } + + memset(iv, 0x23, 32); + + printf("\tEncrypting in chunks of %d bytes: ", chunksize); + fflush(stdout); + + memset(buffer, val++, chunksize); + + must_finish = 0; + alarm(5); + + gettimeofday(&start, NULL); + do { + memset(&cop, 0, sizeof(cop)); + cop.ses = sess->ses; + cop.len = chunksize; + cop.iv = (unsigned char *)iv; + cop.op = COP_ENCRYPT; + cop.src = cop.dst = (unsigned char *)buffer; + + if (ioctl(fdc, CIOCCRYPT, &cop)) { + perror("ioctl(CIOCCRYPT)"); + return 1; + } + total+=chunksize; + } while(must_finish==0); + gettimeofday(&end, NULL); + + secs = udifftimeval(start, end)/ 1000000.0; + + value2human(si, total, secs, &ddata, &dspeed, metric); + printf ("done. %.2f %s in %.2f secs: ", ddata, metric, secs); + printf ("%.2f %s/sec\n", dspeed, metric); + + free(buffer); + return 0; +} + +int main(int argc, char** argv) +{ + int fd, i, fdc = -1, alignmask = 0; + struct session_op sess; +#ifdef CIOCGSESSINFO + struct session_info_op siop; +#endif + char keybuf[32]; + + signal(SIGALRM, alarm_handler); + + if (argc > 1) { + if (strcmp(argv[1], "--help") == 0 || strcmp(argv[1], "-h") == 0) { + printf("Usage: speed [--kib]\n"); + exit(0); + } + if (strcmp(argv[1], "--kib") == 0) { + si = 0; + } + } + + if ((fd = open("/dev/crypto", O_RDWR, 0)) < 0) { + perror("open()"); + return 1; + } + if (ioctl(fd, CRIOGET, &fdc)) { + perror("ioctl(CRIOGET)"); + return 1; + } + + fprintf(stderr, "Testing NULL cipher: \n"); + memset(&sess, 0, sizeof(sess)); + sess.cipher = CRYPTO_NULL; + sess.keylen = 0; + sess.key = (unsigned char *)keybuf; + if (ioctl(fdc, CIOCGSESSION, &sess)) { + perror("ioctl(CIOCGSESSION)"); + return 1; + } +#ifdef CIOCGSESSINFO + siop.ses = sess.ses; + if (ioctl(fdc, CIOCGSESSINFO, &siop)) { + perror("ioctl(CIOCGSESSINFO)"); + return 1; + } + alignmask = siop.alignmask; +#endif + + for (i = 512; i <= (64 * 1024); i *= 2) { + if (encrypt_data(&sess, fdc, i, alignmask)) + break; + } + + fprintf(stderr, "\nTesting AES-128-CBC cipher: \n"); + memset(&sess, 0, sizeof(sess)); + sess.cipher = CRYPTO_AES_CBC; + sess.keylen = 16; + memset(keybuf, 0x42, 16); + sess.key = (unsigned char *)keybuf; + if (ioctl(fdc, CIOCGSESSION, &sess)) { + perror("ioctl(CIOCGSESSION)"); + return 1; + } +#ifdef CIOCGSESSINFO + siop.ses = sess.ses; + if (ioctl(fdc, CIOCGSESSINFO, &siop)) { + perror("ioctl(CIOCGSESSINFO)"); + return 1; + } + alignmask = siop.alignmask; +#endif + + for (i = 512; i <= (64 * 1024); i *= 2) { + if (encrypt_data(&sess, fdc, i, alignmask)) + break; + } + + close(fdc); + close(fd); + return 0; +} diff --git a/drivers/cryptodev-linux-master/tests/testhelper.h b/drivers/cryptodev-linux-master/tests/testhelper.h new file mode 100644 index 00000000..800d10db --- /dev/null +++ b/drivers/cryptodev-linux-master/tests/testhelper.h @@ -0,0 +1,9 @@ +/* + * Some helper stuff shared between the sample programs. + */ +#ifndef __TESTHELPER_H +#define __TESTHELPER_H + +#define buf_align(buf, align) (void *)(((unsigned long)(buf) + (align)) & ~(align)) + +#endif /* __TESTHELPER_H */ diff --git a/drivers/cryptodev-linux-master/util.c b/drivers/cryptodev-linux-master/util.c new file mode 100644 index 00000000..9eba4836 --- /dev/null +++ b/drivers/cryptodev-linux-master/util.c @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2011 Maxim Levitsky + * + * This file is part of linux cryptodev. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include +#include +#include "util.h" + +/* These were taken from Maxim Levitsky's patch to lkml. + */ +struct scatterlist *sg_advance(struct scatterlist *sg, int consumed) +{ + while (consumed >= sg->length) { + consumed -= sg->length; + + sg = sg_next(sg); + if (!sg) + break; + } + + WARN_ON(!sg && consumed); + + if (!sg) + return NULL; + + sg->offset += consumed; + sg->length -= consumed; + + if (sg->offset >= PAGE_SIZE) { + struct page *page = + nth_page(sg_page(sg), sg->offset / PAGE_SIZE); + sg_set_page(sg, page, sg->length, sg->offset % PAGE_SIZE); + } + + return sg; +} + +/** + * sg_copy - copies sg entries from sg_from to sg_to, such + * as sg_to covers first 'len' bytes from sg_from. + */ +int sg_copy(struct scatterlist *sg_from, struct scatterlist *sg_to, int len) +{ + while (len > sg_from->length) { + len -= sg_from->length; + + sg_set_page(sg_to, sg_page(sg_from), + sg_from->length, sg_from->offset); + + sg_to = sg_next(sg_to); + sg_from = sg_next(sg_from); + + if (len && (!sg_from || !sg_to)) + return -ENOMEM; + } + + if (len) + sg_set_page(sg_to, sg_page(sg_from), + len, sg_from->offset); + sg_mark_end(sg_to); + return 0; +} + diff --git a/drivers/cryptodev-linux-master/util.h b/drivers/cryptodev-linux-master/util.h new file mode 100644 index 00000000..204de758 --- /dev/null +++ b/drivers/cryptodev-linux-master/util.h @@ -0,0 +1,2 @@ +int sg_copy(struct scatterlist *sg_from, struct scatterlist *sg_to, int len); +struct scatterlist *sg_advance(struct scatterlist *sg, int consumed); diff --git a/drivers/cryptodev-linux-master/zc.c b/drivers/cryptodev-linux-master/zc.c new file mode 100644 index 00000000..fdf7da17 --- /dev/null +++ b/drivers/cryptodev-linux-master/zc.c @@ -0,0 +1,235 @@ +/* + * Driver for /dev/crypto device (aka CryptoDev) + * + * Copyright (c) 2009-2013 Nikos Mavrogiannopoulos + * Copyright (c) 2010 Phil Sutter + * Copyright (c) 2011, 2012 OpenSSL Software Foundation, Inc. + * + * This file is part of linux cryptodev. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cryptodev_int.h" +#include "zc.h" +#include "version.h" + +/* Helper functions to assist zero copy. + * This needs to be redesigned and moved out of the session. --nmav + */ + +/* offset of buf in it's first page */ +#define PAGEOFFSET(buf) ((unsigned long)buf & ~PAGE_MASK) + +/* fetch the pages addr resides in into pg and initialise sg with them */ +int __get_userbuf(uint8_t __user *addr, uint32_t len, int write, + unsigned int pgcount, struct page **pg, struct scatterlist *sg, + struct task_struct *task, struct mm_struct *mm) +{ + int ret, pglen, i = 0; + struct scatterlist *sgp; + + if (unlikely(!pgcount || !len || !addr)) { + sg_mark_end(sg); + return 0; + } + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0)) + down_read(&mm->mmap_sem); +#else + mmap_read_lock(mm); +#endif +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 168)) + ret = get_user_pages(task, mm, + (unsigned long)addr, pgcount, write, 0, pg, NULL); +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(4, 6, 0)) + ret = get_user_pages(task, mm, + (unsigned long)addr, pgcount, write, pg, NULL); +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(4, 9, 0)) + ret = get_user_pages_remote(task, mm, + (unsigned long)addr, pgcount, write, 0, pg, NULL); +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(4, 10, 0)) + ret = get_user_pages_remote(task, mm, + (unsigned long)addr, pgcount, write ? FOLL_WRITE : 0, + pg, NULL); +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(5, 9, 0)) + ret = get_user_pages_remote(task, mm, + (unsigned long)addr, pgcount, write ? FOLL_WRITE : 0, + pg, NULL, NULL); +#else + ret = get_user_pages_remote(mm, + (unsigned long)addr, pgcount, write ? FOLL_WRITE : 0, + pg, NULL, NULL); +#endif +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 8, 0)) + up_read(&mm->mmap_sem); +#else + mmap_read_unlock(mm); +#endif + if (ret != pgcount) + return -EINVAL; + + sg_init_table(sg, pgcount); + + pglen = min((ptrdiff_t)(PAGE_SIZE - PAGEOFFSET(addr)), (ptrdiff_t)len); + sg_set_page(sg, pg[i++], pglen, PAGEOFFSET(addr)); + + len -= pglen; + for (sgp = sg_next(sg); len; sgp = sg_next(sgp)) { + pglen = min((uint32_t)PAGE_SIZE, len); + sg_set_page(sgp, pg[i++], pglen, 0); + len -= pglen; + } + sg_mark_end(sg_last(sg, pgcount)); + return 0; +} + +int adjust_sg_array(struct csession *ses, int pagecount) +{ + struct scatterlist *sg; + struct page **pages; + int array_size; + + for (array_size = ses->array_size; array_size < pagecount; + array_size *= 2) + ; + ddebug(0, "reallocating from %d to %d pages", + ses->array_size, array_size); + pages = krealloc(ses->pages, array_size * sizeof(struct page *), + GFP_KERNEL); + if (unlikely(!pages)) + return -ENOMEM; + ses->pages = pages; + sg = krealloc(ses->sg, array_size * sizeof(struct scatterlist), + GFP_KERNEL); + if (unlikely(!sg)) + return -ENOMEM; + ses->sg = sg; + ses->array_size = array_size; + + return 0; +} + +void release_user_pages(struct csession *ses) +{ + unsigned int i; + + for (i = 0; i < ses->used_pages; i++) { + if (!PageReserved(ses->pages[i])) + SetPageDirty(ses->pages[i]); + + if (ses->readonly_pages == 0) + flush_dcache_page(ses->pages[i]); + else + ses->readonly_pages--; + + put_page(ses->pages[i]); + } + ses->used_pages = 0; +} + +/* make src and dst available in scatterlists. + * dst might be the same as src. + */ +int get_userbuf(struct csession *ses, + void *__user src, unsigned int src_len, + void *__user dst, unsigned int dst_len, + struct task_struct *task, struct mm_struct *mm, + struct scatterlist **src_sg, + struct scatterlist **dst_sg) +{ + int src_pagecount, dst_pagecount; + int rc; + + /* Empty input is a valid option to many algorithms & is tested by NIST/FIPS */ + /* Make sure NULL input has 0 length */ + if (!src && src_len) + src_len = 0; + + /* I don't know that null output is ever useful, but we can handle it gracefully */ + /* Make sure NULL output has 0 length */ + if (!dst && dst_len) + dst_len = 0; + + src_pagecount = PAGECOUNT(src, src_len); + dst_pagecount = PAGECOUNT(dst, dst_len); + + ses->used_pages = (src == dst) ? max(src_pagecount, dst_pagecount) + : src_pagecount + dst_pagecount; + + ses->readonly_pages = (src == dst) ? 0 : src_pagecount; + + if (ses->used_pages > ses->array_size) { + rc = adjust_sg_array(ses, ses->used_pages); + if (rc) + return rc; + } + + if (src == dst) { /* inplace operation */ + /* When we encrypt for authenc modes we need to write + * more data than the ones we read. */ + if (src_len < dst_len) + src_len = dst_len; + rc = __get_userbuf(src, src_len, 1, ses->used_pages, + ses->pages, ses->sg, task, mm); + if (unlikely(rc)) { + derr(1, "failed to get user pages for data IO"); + return rc; + } + (*src_sg) = (*dst_sg) = ses->sg; + return 0; + } + + *src_sg = NULL; /* default to no input */ + *dst_sg = NULL; /* default to ignore output */ + + if (likely(src)) { + rc = __get_userbuf(src, src_len, 0, ses->readonly_pages, + ses->pages, ses->sg, task, mm); + if (unlikely(rc)) { + derr(1, "failed to get user pages for data input"); + return rc; + } + *src_sg = ses->sg; + } + + if (likely(dst)) { + const unsigned int writable_pages = + ses->used_pages - ses->readonly_pages; + struct page **dst_pages = ses->pages + ses->readonly_pages; + *dst_sg = ses->sg + ses->readonly_pages; + + rc = __get_userbuf(dst, dst_len, 1, writable_pages, + dst_pages, *dst_sg, task, mm); + if (unlikely(rc)) { + derr(1, "failed to get user pages for data output"); + release_user_pages(ses); /* FIXME: use __release_userbuf(src, ...) */ + return rc; + } + } + return 0; +} diff --git a/drivers/cryptodev-linux-master/zc.h b/drivers/cryptodev-linux-master/zc.h new file mode 100644 index 00000000..666c4a54 --- /dev/null +++ b/drivers/cryptodev-linux-master/zc.h @@ -0,0 +1,25 @@ +#ifndef ZC_H +# define ZC_H + +/* For zero copy */ +int __get_userbuf(uint8_t __user *addr, uint32_t len, int write, + unsigned int pgcount, struct page **pg, struct scatterlist *sg, + struct task_struct *task, struct mm_struct *mm); +void release_user_pages(struct csession *ses); + +int get_userbuf(struct csession *ses, + void *__user src, unsigned int src_len, + void *__user dst, unsigned int dst_len, + struct task_struct *task, struct mm_struct *mm, + struct scatterlist **src_sg, + struct scatterlist **dst_sg); + +/* buflen ? (last page - first page + 1) : 0 */ +#define PAGECOUNT(buf, buflen) ((buflen) \ + ? ((((unsigned long)(buf + buflen - 1)) >> PAGE_SHIFT) - \ + (((unsigned long)(buf )) >> PAGE_SHIFT) + 1) \ + : 0) + +#define DEFAULT_PREALLOC_PAGES 32 + +#endif diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 141aefbe..1a69fb51 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -75,6 +75,61 @@ config AMCC_PPC440SPE_ADMA help Enable support for the AMCC PPC440SPe RAID engines. +config DW_DMAC + tristate "Synopsys DesignWare AHB DMA support" + depends on HAVE_CLK + select DMA_ENGINE + default y if CPU_AT32AP7000 + help + Support the Synopsys DesignWare AHB DMA controller. This + can be integrated in chips such as the Atmel AT32ap7000. + +config CHANNEL_ALLOC_MEM_CLASSICS + bool "chose malloc desc with classics, not from dma pool" + help + the pool size default is 256KB. + default y + +config FH_DMAC + tristate "FH DesignWare AHB DMA support" + depends on HAVE_CLK + select CHANNEL_ALLOC_MEM_CLASSICS + select DMA_ENGINE + + help + Support the Synopsys DesignWare AHB DMA controller. This + can be integrated in chips such as the FullHan. + + +if !FH_DMAC + config FH_AXI_DMAC + tristate "FH DesignWare AXI DMA support" + depends on HAVE_CLK + select CHANNEL_ALLOC_MEM_CLASSICS + select DMA_ENGINE + + help + Support the Synopsys DesignWare AHB DMA controller. This + can be integrated in chips such as the FullHan. +endif + +if FH_DMAC || FH_AXI_DMAC + +config FH_DMAC_MISC + bool "FH DMAC Misc Device Enable" + default y + help + FH DMAC Misc Device Enable + +menu "dma tinyconfig" + +config CHANNEL_ALLOC_DESC_NUM + int "CHANNEL_ALLOC_DESC_NUM" + default 256 +endmenu + +endif + config AT_HDMAC tristate "Atmel AHB DMA support" depends on ARCH_AT91 diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index e4dc9cac..a0a28152 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -67,6 +67,8 @@ obj-$(CONFIG_TI_DMA_CROSSBAR) += ti-dma-crossbar.o obj-$(CONFIG_TI_EDMA) += edma.o obj-$(CONFIG_XGENE_DMA) += xgene-dma.o obj-$(CONFIG_ZX_DMA) += zx296702_dma.o +obj-$(CONFIG_FH_DMAC) += fh_dmac.o +obj-$(CONFIG_FH_AXI_DMAC) += fh_axi_dma_driver.o fh_axi_dma_adapt.o obj-y += qcom/ obj-y += xilinx/ diff --git a/drivers/dma/fh_axi_dma_adapt.c b/drivers/dma/fh_axi_dma_adapt.c new file mode 100644 index 00000000..14f3f4f8 --- /dev/null +++ b/drivers/dma/fh_axi_dma_adapt.c @@ -0,0 +1,829 @@ +#include "fh_axi_dma_adapt.h" + +static inline struct fh_axi_dma_adapt *to_fh_axi_dma(struct dma_device *ddev); +static inline struct fh_axi_dma_channel_adapt *to_fh_axi_dma_chan(struct dma_chan *chan); +static dma_cookie_t fh_axi_dma_adapt_submit(struct dma_async_tx_descriptor *tx); +static int adapt_alloc_chan_resources(struct dma_chan *chan); +static void adapt_free_chan_resources(struct dma_chan *chan); +static FH_UINT32 cal_data_width(dma_addr_t dest, dma_addr_t src, size_t len); +static void adapt_prep_callback(void *p); +static struct dma_async_tx_descriptor *adapt_prep_dma_memcpy(struct dma_chan *chan, +dma_addr_t dest, dma_addr_t src, size_t len, unsigned long flags); +static FH_UINT32 width_from_core_to_driver(FH_UINT32 core_width); +static FH_UINT32 burst_from_core_to_driver(FH_UINT32 core_width); + +static struct dma_async_tx_descriptor * +adapt_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, + unsigned int sg_len, enum dma_transfer_direction direction, + unsigned long flags, void *context); + +static int adapt_device_config(struct dma_chan *chan, struct dma_slave_config *config); +static int adapt_device_pause(struct dma_chan *chan); +static int adapt_device_resume(struct dma_chan *chan); + +static enum dma_status +adapt_tx_status(struct dma_chan *chan, +dma_cookie_t cookie, struct dma_tx_state *txstate); + +static irqreturn_t adapt_dma_interrupt(int irq, void *dev_id); +static void adapt_axi_dma_tasklet(unsigned long data); +static struct fh_axi_dma * adapt_to_driver_handle(struct fh_axi_dma_adapt *p_adapt); +static void adapt_device_issue_pending(struct dma_chan *chan); +static int adapt_device_terminate_all(struct dma_chan *chan); +static int fh_axi_dma_adapt_probe(struct platform_device *pdev); +static int fh_axi_dma_adapt_remove(struct platform_device *pdev); +static int __init fh_axi_dma_adapt_init(void); +static void __exit fh_axi_dma_adapt_exit(void); + +static inline struct fh_axi_dma_adapt *to_fh_axi_dma(struct dma_device *ddev) +{ + return container_of(ddev, struct fh_axi_dma_adapt, dma); +} + +static inline struct fh_axi_dma_channel_adapt *to_fh_axi_dma_chan(struct dma_chan *chan) +{ + return container_of(chan, struct fh_axi_dma_channel_adapt, core_chan); +} + +static struct fh_axi_dma * adapt_to_driver_handle(struct fh_axi_dma_adapt *p_adapt) +{ + return p_adapt->driver_pri; +} + +static void fh_axi_adapt_isr_prep_func_callback(void *p) +{ + dma_cookie_complete((struct dma_async_tx_descriptor *)p); +} + +static dma_cookie_t fh_axi_dma_adapt_submit(struct dma_async_tx_descriptor *tx) +{ + dma_cookie_t cookie; + struct axi_dma_ops *p_ops; + struct dma_transfer *p_trans; + struct fh_axi_dma_channel_adapt *fhc_adapt; + struct dma_chan *chan = tx->chan; + struct fh_axi_dma_adapt *fhd = to_fh_axi_dma(chan->device); + + cookie = dma_cookie_assign(tx); + fhc_adapt = to_fh_axi_dma_chan(chan); + p_trans = &fhc_adapt->trans; + p_trans->isr_prepare_callback = fh_axi_adapt_isr_prep_func_callback; + p_trans->isr_prepare_para = (void *)tx; + p_trans->complete_callback = tx->callback; + p_trans->complete_para = tx->callback_param; + p_ops = get_fh_axi_dma_ops(fhd->driver_pri); + p_ops->axi_dma_control(fhd->driver_pri, AXI_DMA_CTRL_DMA_SINGLE_TRANSFER, p_trans); + return cookie; +} + + +static int adapt_alloc_chan_resources(struct dma_chan *chan) +{ + + struct axi_dma_ops *p_ops; + struct dma_transfer *p_trans; + int i; + struct dma_async_tx_descriptor *p_async; + FH_UINT32 desc_no; + FH_UINT32 each_desc_size; + FH_UINT32 driver_desc_phy_base; + FH_UINT32 desc_cap; + struct fh_axi_dma_channel_adapt *fhc_adapt; + struct fh_axi_dma_adapt *fhd = to_fh_axi_dma(chan->device); + + fhc_adapt = to_fh_axi_dma_chan(chan); + p_trans = &fhc_adapt->trans; + dma_cookie_init(chan); + p_ops = get_fh_axi_dma_ops(fhd->driver_pri); + p_trans->dma_number = fhd->dma.dev_id; + p_trans->channel_number = chan->chan_id; + p_ops->axi_dma_control(fhd->driver_pri, AXI_DMA_CTRL_DMA_REQUEST_CHANNEL, p_trans); + p_ops->axi_dma_get_desc_para(fhd->driver_pri, p_trans, &desc_no, &driver_desc_phy_base, &each_desc_size, &desc_cap); + fhc_adapt->ch_adapt_desc_base = (struct dma_async_tx_descriptor *)devm_kzalloc(&fhd->pdev->dev, + sizeof(struct dma_async_tx_descriptor) * desc_no, GFP_KERNEL); + for(i = 0, p_async = fhc_adapt->ch_adapt_desc_base; i < desc_no; i++, p_async++){ + dma_async_tx_descriptor_init(p_async, chan); + p_async->tx_submit = fh_axi_dma_adapt_submit; + p_async->flags = DMA_CTRL_ACK; + p_async->phys = driver_desc_phy_base + (i * each_desc_size); + } + + return desc_no; +} + + +static void adapt_free_chan_resources(struct dma_chan *chan) +{ + struct axi_dma_ops *p_ops; + struct dma_transfer *p_trans; + struct fh_axi_dma_channel_adapt *fhc_adapt; + struct fh_axi_dma_adapt *fhd = to_fh_axi_dma(chan->device); + + fhc_adapt = to_fh_axi_dma_chan(chan); + p_trans = &fhc_adapt->trans; + p_ops = get_fh_axi_dma_ops(fhd->driver_pri); + p_ops->axi_dma_control(fhd->driver_pri, AXI_DMA_CTRL_DMA_RELEASE_CHANNEL, p_trans); + if(fhc_adapt->ch_adapt_desc_base) + devm_kfree(&fhd->pdev->dev, fhc_adapt->ch_adapt_desc_base); +} + +static FH_UINT32 cal_data_width(dma_addr_t dest, dma_addr_t src, size_t len) +{ + FH_UINT32 data_width = 0; + + if (!((src % 4) || (dest % 4) || (len % 4))) + data_width = DW_DMA_SLAVE_WIDTH_32BIT; + else if (!((src % 2) || (dest % 2) || (len % 2))) + data_width = DW_DMA_SLAVE_WIDTH_16BIT; + else + data_width = DW_DMA_SLAVE_WIDTH_8BIT; + + return data_width; +} + +static void adapt_prep_callback(void *p) +{ + struct dma_chan *chan = (struct dma_chan *)p; + struct fh_axi_dma_channel_adapt *fhc_adapt; + struct fh_axi_dma_adapt *fhd = to_fh_axi_dma(chan->device); + + fhc_adapt = to_fh_axi_dma_chan(chan); + devm_kfree(&fhd->pdev->dev, fhc_adapt->desc_head); +} + + +static struct dma_async_tx_descriptor * +adapt_prep_dma_memcpy(struct dma_chan *chan, +dma_addr_t dest, dma_addr_t src, +size_t len, unsigned long flags) +{ + struct axi_dma_ops *p_ops; + struct dma_transfer *p_trans; + int i; + FH_UINT32 desc_no; + FH_UINT32 each_desc_size; + FH_UINT32 driver_desc_phy_base; + FH_UINT32 width; + FH_UINT32 ot_len; + FH_UINT32 need_trans_size; + FH_UINT32 desc_cap; + struct dma_transfer_desc *p_desc; + struct fh_axi_dma_channel_adapt *fhc_adapt; + struct fh_axi_dma_adapt *fhd = to_fh_axi_dma(chan->device); + + fhc_adapt = to_fh_axi_dma_chan(chan); + p_ops = get_fh_axi_dma_ops(fhd->driver_pri); + p_trans = &fhc_adapt->trans; + width = cal_data_width(dest, src, len); + + p_ops->axi_dma_get_desc_para(fhd->driver_pri, p_trans, &desc_no, &driver_desc_phy_base, &each_desc_size, &desc_cap); + + //cal size with width + len = len / ( 1 << width ); + need_trans_size = len / desc_cap; + if(len % desc_cap) + need_trans_size++; + + fhc_adapt->desc_size = need_trans_size; + fhc_adapt->desc_head = devm_kzalloc(&fhd->pdev->dev, + sizeof(struct dma_transfer_desc) * need_trans_size, GFP_KERNEL); + + BUG_ON(!fhc_adapt->desc_head); + p_desc = fhc_adapt->desc_head; + + p_trans->fc_mode = DMA_M2M; + i = 0; + while(len != 0){ + ot_len = min_t(unsigned int, desc_cap, len); + p_desc->src_add = src + i * desc_cap * (1 << width); + p_desc->src_width = width; + p_desc->src_msize = DW_DMA_SLAVE_MSIZE_32; + p_desc->src_inc_mode = DW_DMA_SLAVE_INC; + + p_desc->dst_add = dest + i * desc_cap * (1 << width); + p_desc->dst_width = width; + p_desc->dst_msize = DW_DMA_SLAVE_MSIZE_32; + p_desc->dst_inc_mode = DW_DMA_SLAVE_INC; + p_desc->size = ot_len; + p_desc++; + i++; + len -= ot_len; + } + p_trans->p_desc = fhc_adapt->desc_head; + p_trans->desc_size = need_trans_size; + + p_trans->prepare_callback = adapt_prep_callback; + p_trans->prepare_para = chan; + + return fhc_adapt->ch_adapt_desc_base; +} + + +static FH_UINT32 width_from_core_to_driver(FH_UINT32 core_width) +{ + FH_UINT32 ret; + + switch(core_width){ + case DMA_SLAVE_BUSWIDTH_1_BYTE : + ret = DW_DMA_SLAVE_WIDTH_8BIT; + break; + + case DMA_SLAVE_BUSWIDTH_2_BYTES : + ret = DW_DMA_SLAVE_WIDTH_16BIT; + break; + + case DMA_SLAVE_BUSWIDTH_4_BYTES : + ret = DW_DMA_SLAVE_WIDTH_32BIT; + break; + + default : + BUG_ON(1); + } + return ret; +} + + +static FH_UINT32 burst_from_core_to_driver(FH_UINT32 core_width) +{ + FH_UINT32 ret; + switch(core_width){ + case 1 : + ret = DW_DMA_SLAVE_MSIZE_1; + break; + + case 4 : + ret = DW_DMA_SLAVE_MSIZE_4; + break; + + case 8 : + ret = DW_DMA_SLAVE_MSIZE_8; + break; + + case 16 : + ret = DW_DMA_SLAVE_MSIZE_16; + break; + + case 32 : + ret = DW_DMA_SLAVE_MSIZE_32; + break; + + default : + BUG_ON(1); + } + return ret; +} + + +static struct dma_async_tx_descriptor * +adapt_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, + unsigned int sg_len, enum dma_transfer_direction direction, + unsigned long flags, void *context) +{ + + struct dma_transfer *p_trans; + int i; + struct scatterlist *sg; + FH_UINT32 dev_width, dev_add; + FH_UINT32 mem_width, mem_add; + FH_UINT32 ot_len; + struct fh_dma_extra *ext_para = (struct fh_dma_extra *)context; + struct dma_slave_config *sconfig; + struct dma_transfer_desc *p_desc; + struct fh_axi_dma_channel_adapt *fhc_adapt; + struct fh_axi_dma_adapt *fhd = to_fh_axi_dma(chan->device); + + fhc_adapt = to_fh_axi_dma_chan(chan); + p_trans = &fhc_adapt->trans; + fhc_adapt->desc_size = sg_len; + + fhc_adapt->desc_head = devm_kzalloc(&fhd->pdev->dev, + sizeof(struct dma_transfer_desc) * sg_len, GFP_KERNEL); + BUG_ON(!fhc_adapt->desc_head); + p_desc = fhc_adapt->desc_head; + sconfig = &fhc_adapt->sconfig; + + if (ext_para) + memcpy(&fhc_adapt->ext_para, ext_para, sizeof(struct fh_dma_extra)); + + + switch (direction) { + case DMA_MEM_TO_DEV: + p_trans->fc_mode = DMA_M2P; + p_trans->dst_per = sconfig->slave_id; + dev_width = width_from_core_to_driver(sconfig->dst_addr_width); + dev_add = sconfig->dst_addr; + mem_width = width_from_core_to_driver(sconfig->src_addr_width); + + + for_each_sg(sgl, sg, sg_len, i) { + mem_add = sg_dma_address(sg); + ot_len = sg_dma_len(sg); + p_desc->src_add = mem_add; + p_desc->src_width = mem_width; + ot_len = ot_len >> p_desc->src_width; + p_desc->src_msize = burst_from_core_to_driver(sconfig->src_maxburst); + p_desc->src_inc_mode = DW_DMA_SLAVE_INC; + p_desc->dst_add = dev_add; + p_desc->dst_width = dev_width; + p_desc->dst_msize = burst_from_core_to_driver(sconfig->dst_maxburst); + p_desc->dst_inc_mode = DW_DMA_SLAVE_FIX; + if (ext_para){ + p_desc->dst_inc_mode = ext_para->dinc; + } + p_desc->size = ot_len; + p_desc++; + } + break; + + case DMA_DEV_TO_MEM: + p_trans->fc_mode = DMA_P2M; + p_trans->src_per = sconfig->slave_id; + dev_width = width_from_core_to_driver(sconfig->src_addr_width); + dev_add = sconfig->src_addr; + mem_width = width_from_core_to_driver(sconfig->dst_addr_width); + + for_each_sg(sgl, sg, sg_len, i) { + mem_add = sg_dma_address(sg); + ot_len = sg_dma_len(sg); + + p_desc->src_add = dev_add; + p_desc->src_width = dev_width; + ot_len = ot_len >> p_desc->src_width; + p_desc->src_msize = burst_from_core_to_driver(sconfig->src_maxburst); + p_desc->src_inc_mode = DW_DMA_SLAVE_FIX; + if (ext_para) + p_desc->src_inc_mode = ext_para->sinc; + p_desc->dst_add = mem_add; + p_desc->dst_width = mem_width; + p_desc->dst_msize = burst_from_core_to_driver(sconfig->dst_maxburst); + p_desc->dst_inc_mode = DW_DMA_SLAVE_INC; + p_desc->size = ot_len; + + p_desc++; + } + + break; + + default: + return NULL; + } + p_trans->p_desc = fhc_adapt->desc_head; + p_trans->desc_size = fhc_adapt->desc_size; + p_trans->prepare_callback = adapt_prep_callback; + p_trans->prepare_para = chan; + + return fhc_adapt->ch_adapt_desc_base; +} + + +static int adapt_device_config(struct dma_chan *chan, struct dma_slave_config *config) +{ + struct fh_axi_dma_channel_adapt *fhc_adapt; + + fhc_adapt = to_fh_axi_dma_chan(chan); + memcpy(&fhc_adapt->sconfig, config, sizeof(struct dma_slave_config)); + return 0; +} + + +static int adapt_device_pause(struct dma_chan *chan) +{ + struct axi_dma_ops *p_ops; + struct dma_transfer *p_trans; + struct fh_axi_dma_channel_adapt *fhc_adapt; + struct fh_axi_dma_adapt *fhd = to_fh_axi_dma(chan->device); + + fhc_adapt = to_fh_axi_dma_chan(chan); + p_trans = &fhc_adapt->trans; + + p_ops = get_fh_axi_dma_ops(fhd->driver_pri); + p_ops->axi_dma_control(fhd->driver_pri, AXI_DMA_CTRL_DMA_PAUSE, p_trans); + + + return 0; +} + +static int adapt_device_resume(struct dma_chan *chan) +{ + struct axi_dma_ops *p_ops; + struct dma_transfer *p_trans; + struct fh_axi_dma_channel_adapt *fhc_adapt; + struct fh_axi_dma_adapt *fhd = to_fh_axi_dma(chan->device); + + fhc_adapt = to_fh_axi_dma_chan(chan); + p_trans = &fhc_adapt->trans; + + p_ops = get_fh_axi_dma_ops(fhd->driver_pri); + p_ops->axi_dma_control(fhd->driver_pri, AXI_DMA_CTRL_DMA_RESUME, p_trans); + + + return 0; +} + + + +static enum dma_status +adapt_tx_status(struct dma_chan *chan, +dma_cookie_t cookie, struct dma_tx_state *txstate) +{ + enum dma_status ret; + + ret = dma_cookie_status(chan, cookie, txstate); + return ret; +} + + +static irqreturn_t adapt_dma_interrupt(int irq, void *dev_id) +{ + struct fh_axi_dma_adapt *fh_axi_adapt_obj; + struct axi_dma_ops *p_ops; + struct fh_axi_dma *p_driver_handle; + + fh_axi_adapt_obj = (struct fh_axi_dma_adapt *)dev_id; + p_driver_handle = adapt_to_driver_handle(fh_axi_adapt_obj); + p_ops = get_fh_axi_dma_ops(p_driver_handle); + // close dma isr .tasklet will reopen + p_ops->axi_dma_isr_enable_set(p_driver_handle, DMA_COMMON_ISR_CLOSE); + tasklet_schedule(&fh_axi_adapt_obj->tasklet); + + return IRQ_HANDLED; +} + + +static void adapt_axi_dma_tasklet(unsigned long data) +{ + struct axi_dma_ops *p_ops; + struct fh_axi_dma *p_driver_handle; + struct fh_axi_dma_adapt *p_adapt = (struct fh_axi_dma_adapt *)data; + + p_driver_handle = adapt_to_driver_handle(p_adapt); + p_ops = get_fh_axi_dma_ops(p_driver_handle); + p_ops->axi_dma_isr_process(p_driver_handle); + p_ops->axi_dma_isr_enable_set(p_driver_handle, DMA_COMMON_ISR_OPEN); +} + +/**** + * + * adapt cyclic + * +****/ + +inline dma_addr_t fh_dma_get_src_addr(struct dma_chan *chan) +{ + struct dma_transfer *p_trans; + struct axi_dma_ops * p_ops; + struct fh_axi_dma_channel_adapt *fhc_adapt; + struct fh_axi_dma_adapt *fhd = to_fh_axi_dma(chan->device); + + fhc_adapt = to_fh_axi_dma_chan(chan); + p_trans = &fhc_adapt->trans; + p_ops = get_fh_axi_dma_ops(fhd->driver_pri); + return (dma_addr_t)p_ops->axi_dma_control(fhd->driver_pri, AXI_DMA_CTRL_DMA_GET_SAR, p_trans); + +} +EXPORT_SYMBOL(fh_dma_get_src_addr); + +inline dma_addr_t fh_dma_get_dst_addr(struct dma_chan *chan) +{ + struct dma_transfer *p_trans; + struct axi_dma_ops * p_ops; + struct fh_axi_dma_channel_adapt *fhc_adapt; + struct fh_axi_dma_adapt *fhd = to_fh_axi_dma(chan->device); + + fhc_adapt = to_fh_axi_dma_chan(chan); + p_trans = &fhc_adapt->trans; + p_ops = get_fh_axi_dma_ops(fhd->driver_pri); + return (dma_addr_t)p_ops->axi_dma_control(fhd->driver_pri, AXI_DMA_CTRL_DMA_GET_DAR, p_trans); +} +EXPORT_SYMBOL(fh_dma_get_dst_addr); + + +int fh_dma_cyclic_start(struct dma_chan *chan) +{ + struct dma_transfer *p_trans; + struct axi_dma_ops * p_ops; + struct fh_cyclic_desc *p_cyclic; + struct fh_axi_dma_channel_adapt *fhc_adapt; + struct fh_axi_dma_adapt *fhd = to_fh_axi_dma(chan->device); + + fhc_adapt = to_fh_axi_dma_chan(chan); + p_cyclic = &fhc_adapt->cyclic; + p_trans = &fhc_adapt->trans; + + p_trans->complete_callback = p_cyclic->period_callback; + p_trans->complete_para = p_cyclic->period_callback_param; + p_ops = get_fh_axi_dma_ops(fhd->driver_pri); + p_ops->axi_dma_control(fhd->driver_pri, AXI_DMA_CTRL_DMA_CYCLIC_START, p_trans); + + return 0; +} +EXPORT_SYMBOL(fh_dma_cyclic_start); + + +void fh_dma_cyclic_stop(struct dma_chan *chan) +{ + struct dma_transfer *p_trans; + struct axi_dma_ops * p_ops; + struct fh_axi_dma_channel_adapt *fhc_adapt; + struct fh_axi_dma_adapt *fhd = to_fh_axi_dma(chan->device); + + fhc_adapt = to_fh_axi_dma_chan(chan); + p_trans = &fhc_adapt->trans; + p_ops = get_fh_axi_dma_ops(fhd->driver_pri); + p_ops->axi_dma_control(fhd->driver_pri, AXI_DMA_CTRL_DMA_CYCLIC_STOP, p_trans); +} +EXPORT_SYMBOL(fh_dma_cyclic_stop); + + +struct fh_cyclic_desc *fh_dma_cyclic_prep(struct dma_chan *chan, + dma_addr_t buf_addr, size_t buf_len, size_t period_len, + enum dma_transfer_direction direction) +{ + struct dma_transfer *p_trans; + int i; + FH_UINT32 ot_len; + FH_UINT32 periods; + struct axi_dma_ops * p_ops; + struct fh_dma_slave *fhs = chan->private; + struct dma_transfer_desc *p_desc; + struct fh_axi_dma_channel_adapt *fhc_adapt; + struct fh_axi_dma_adapt *fhd = to_fh_axi_dma(chan->device); + + fhc_adapt = to_fh_axi_dma_chan(chan); + p_trans = &fhc_adapt->trans; + periods = buf_len / period_len; + fhc_adapt->desc_size = periods; + fhc_adapt->desc_head = devm_kzalloc(&fhd->pdev->dev, + sizeof(struct dma_transfer_desc) * periods, GFP_KERNEL); + + BUG_ON(!fhc_adapt->desc_head); + p_desc = fhc_adapt->desc_head; + + switch (direction) { + case DMA_MEM_TO_DEV: + p_trans->fc_mode = DMA_M2P; + p_trans->dst_per = fhs->cfg_hi; + for (i = 0; i < periods; i++){ + p_desc->src_add = buf_addr + (period_len * i); + p_desc->src_width = DW_DMA_SLAVE_WIDTH_32BIT; + ot_len = period_len >> p_desc->src_width; + p_desc->src_msize = fhs->src_msize; + p_desc->src_inc_mode = DW_DMA_SLAVE_INC; + + p_desc->dst_add = fhs->tx_reg; + p_desc->dst_width = fhs->reg_width; + p_desc->dst_msize = fhs->dst_msize; + p_desc->dst_inc_mode = DW_DMA_SLAVE_FIX; + p_desc->size = ot_len; + p_desc++; + } + break; + + case DMA_DEV_TO_MEM: + + p_trans->fc_mode = DMA_P2M; + p_trans->src_per = fhs->cfg_hi; + + for (i = 0; i < periods; i++){ + p_desc->src_add = fhs->rx_reg; + p_desc->src_width = fhs->reg_width; + ot_len = period_len >> p_desc->src_width; + p_desc->src_msize = fhs->src_msize; + p_desc->src_inc_mode = DW_DMA_SLAVE_FIX; + + p_desc->dst_add = buf_addr + (period_len * i); + p_desc->dst_width = DW_DMA_SLAVE_WIDTH_32BIT; + p_desc->dst_msize = fhs->dst_msize; + p_desc->dst_inc_mode = DW_DMA_SLAVE_INC; + p_desc->size = ot_len; + p_desc++; + } + break; + default: + return NULL; + } + + p_trans->p_desc = fhc_adapt->desc_head; + p_trans->desc_size = fhc_adapt->desc_size; + p_trans->prepare_callback = adapt_prep_callback; + p_trans->cyclic_periods = periods; + p_trans->prepare_para = chan; + p_ops = get_fh_axi_dma_ops(fhd->driver_pri); + p_ops->axi_dma_control(fhd->driver_pri, AXI_DMA_CTRL_DMA_CYCLIC_PREPARE, p_trans); + + return &fhc_adapt->cyclic; + +} +EXPORT_SYMBOL(fh_dma_cyclic_prep); + + + +void fh_dma_cyclic_free(struct dma_chan *chan) +{ + + struct dma_transfer *p_trans; + struct fh_axi_dma_channel_adapt *fhc_adapt; + struct fh_axi_dma_adapt *fhd = to_fh_axi_dma(chan->device); + fhc_adapt = to_fh_axi_dma_chan(chan); + p_trans = &fhc_adapt->trans; + + if(fhc_adapt->ch_adapt_desc_base) + devm_kfree(&fhd->pdev->dev, fhc_adapt->ch_adapt_desc_base); +} +EXPORT_SYMBOL(fh_dma_cyclic_free); + + +static void adapt_device_issue_pending(struct dma_chan *chan) +{ + +} + +static int adapt_device_terminate_all(struct dma_chan *chan) +{ + return 0; +} + +static void adapt_plat_info_get(struct fh_axi_dma_platform_data *p_info, +struct platform_device *pdev){ +#ifndef CONFIG_OF + /* just cpy plat data.*/ + memcpy((void *)p_info, (void *)pdev->dev.platform_data, + sizeof(struct fh_axi_dma_platform_data)); +#endif +} + + +static int fh_axi_dma_adapt_probe(struct platform_device *pdev) +{ + struct fh_axi_dma_platform_data p_axi_plat; + struct dma_transfer trans; + size_t size; + void __iomem *regs; + int irq; + int err; + int i; + int channel_no; + struct clk *clk; + struct resource *res; + struct fh_axi_dma_adapt *fh_axi_adapt_obj; + struct axi_dma_platform_data driver_plat_data; + struct axi_dma_ops * p_ops; + struct device_node *np = pdev->dev.of_node; + + if (np && !IS_ERR(np)) { + regs = of_iomap(np, 0); + if (!regs) { + err = -ENOMEM; + goto err_release_r; + } + irq = irq_of_parse_and_map(np, 0); + clk = of_clk_get(np, 0); + } else { + adapt_plat_info_get(&p_axi_plat, pdev); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "can't fetch device resource info\n"); + goto err_release_r; + } + regs = ioremap(res->start, resource_size(res)); + if (regs == NULL) { + dev_err(&pdev->dev, "ioremap resource error\n"); + goto err_release_r; + } + irq = platform_get_irq(pdev, 0); + irq = irq_create_mapping(NULL, irq); + clk = clk_get(&pdev->dev, p_axi_plat.clk_name); + if (IS_ERR(clk)) { + err = -EINVAL; + goto err_release_r; + } + } + clk_prepare_enable(clk); + channel_no = cal_axi_dma_channel(regs); + size = sizeof(struct fh_axi_dma_adapt) + channel_no * sizeof(struct fh_axi_dma_channel_adapt); + fh_axi_adapt_obj = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); + + if (!pdev->dev.dma_mask) { + pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; + pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); + } + fh_axi_adapt_obj->pdev = pdev; + fh_axi_adapt_obj->clk = clk; + + INIT_LIST_HEAD(&fh_axi_adapt_obj->dma.channels); + for (i = 0; i < channel_no; i++) { + struct dma_chan *dma_channel; + spin_lock_init(&fh_axi_adapt_obj->chan[i].lock); + dma_channel = &fh_axi_adapt_obj->chan[i].core_chan; + dma_channel->device = &fh_axi_adapt_obj->dma; + dma_cookie_init(dma_channel); + list_add_tail(&dma_channel->device_node, + &fh_axi_adapt_obj->dma.channels); + } + + driver_plat_data.id = pdev->id; + driver_plat_data.name = "axi_dma_driver"; + driver_plat_data.base = (unsigned int)regs; + driver_plat_data.kernel_pri = (void *)fh_axi_adapt_obj->dma.dev; + driver_plat_data.adapt_pri = fh_axi_adapt_obj; + + + fh_axi_adapt_obj->driver_pri = fh_axi_dma_probe(&driver_plat_data); + if(!fh_axi_adapt_obj->driver_pri) + BUG_ON(1); + + platform_set_drvdata(pdev, fh_axi_adapt_obj); + fh_axi_adapt_obj->dma.dev = &pdev->dev; + fh_axi_adapt_obj->dma.device_alloc_chan_resources = adapt_alloc_chan_resources; + fh_axi_adapt_obj->dma.device_free_chan_resources = adapt_free_chan_resources; + fh_axi_adapt_obj->dma.device_prep_dma_memcpy = adapt_prep_dma_memcpy; + fh_axi_adapt_obj->dma.device_prep_slave_sg = adapt_prep_slave_sg; + fh_axi_adapt_obj->dma.device_config = adapt_device_config; + fh_axi_adapt_obj->dma.device_pause = adapt_device_pause; + fh_axi_adapt_obj->dma.device_resume = adapt_device_resume; + fh_axi_adapt_obj->dma.device_terminate_all = adapt_device_terminate_all; + fh_axi_adapt_obj->dma.device_tx_status = adapt_tx_status; + fh_axi_adapt_obj->dma.device_issue_pending = adapt_device_issue_pending; + + tasklet_init(&fh_axi_adapt_obj->tasklet, adapt_axi_dma_tasklet, (unsigned long)fh_axi_adapt_obj); + err = devm_request_irq(&pdev->dev, irq, adapt_dma_interrupt, 0, + "fh-axi-dmac", fh_axi_adapt_obj); + BUG_ON(err); + + dma_cap_set(DMA_MEMCPY, fh_axi_adapt_obj->dma.cap_mask); + dma_cap_set(DMA_SLAVE, fh_axi_adapt_obj->dma.cap_mask); + + trans.dma_number = pdev->id; + p_ops = get_fh_axi_dma_ops(fh_axi_adapt_obj->driver_pri); + p_ops->axi_dma_control(fh_axi_adapt_obj->driver_pri, AXI_DMA_CTRL_DMA_OPEN, &trans); + err = dma_async_device_register(&fh_axi_adapt_obj->dma); + if (err) + pr_err("dma register failed, ret %d\n", err); + + dev_info(&pdev->dev, "FH DMA Controller, %d channels\n", channel_no); + return 0; + +err_release_r: + return err; +} + +static int fh_axi_dma_adapt_remove(struct platform_device *pdev) +{ + + struct fh_axi_dma_adapt *fh_axi_adapt_obj; + struct dma_transfer trans; + struct axi_dma_ops * p_ops; + + //dma off + trans.dma_number = pdev->id; + fh_axi_adapt_obj = platform_get_drvdata(pdev); + p_ops = get_fh_axi_dma_ops(fh_axi_adapt_obj->driver_pri); + p_ops->axi_dma_control(fh_axi_adapt_obj->driver_pri, AXI_DMA_CTRL_DMA_CLOSE, &trans); + //kill tasklet + tasklet_kill(&fh_axi_adapt_obj->tasklet); + //unregister dma + dma_async_device_unregister(&fh_axi_adapt_obj->dma); + devm_kfree(&pdev->dev, fh_axi_adapt_obj); + return 0; +} + +void fh_axi_dma_adapt_shutdown(struct platform_device *pdev){ + pr_err("%s : %d.....\n",__func__,__LINE__); +} + + + + +static const struct of_device_id fh_axi_dma_adapt_of_id_table[] = { + { .compatible = "fh,fh-axi-dmac" }, + {} +}; + +MODULE_DEVICE_TABLE(of, fh_axi_dma_adapt_of_id_table); + +static struct platform_driver fh_dma_axi_adapt_driver = { + .probe = fh_axi_dma_adapt_probe, + .remove = fh_axi_dma_adapt_remove, + .shutdown = fh_axi_dma_adapt_shutdown, + .driver = { + .name = "fh_axi_dmac", + .of_match_table = fh_axi_dma_adapt_of_id_table, + }, +}; + +static int __init fh_axi_dma_adapt_init(void) +{ + return platform_driver_register(&fh_dma_axi_adapt_driver); +} +subsys_initcall(fh_axi_dma_adapt_init); + +static void __exit fh_axi_dma_adapt_exit(void) +{ + platform_driver_unregister(&fh_dma_axi_adapt_driver); +} +module_exit(fh_axi_dma_adapt_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("fullhan AXI-DMA devive driver"); + + diff --git a/drivers/dma/fh_axi_dma_adapt.h b/drivers/dma/fh_axi_dma_adapt.h new file mode 100644 index 00000000..a1e57f67 --- /dev/null +++ b/drivers/dma/fh_axi_dma_adapt.h @@ -0,0 +1,213 @@ +#ifndef _FH_AXI_DMA_ADAPT_H +#define _FH_AXI_DMA_ADAPT_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dmaengine.h" +#include +#include + + +enum { + AXI_DMA_RET_OK = 0, + AXI_DMA_RET_NO_MEM = 1, +}; + +enum { + AXI_DMA_CTRL_DMA_OPEN = 0, + AXI_DMA_CTRL_DMA_CLOSE, + AXI_DMA_CTRL_DMA_REQUEST_CHANNEL, + AXI_DMA_CTRL_DMA_RELEASE_CHANNEL, + AXI_DMA_CTRL_DMA_SINGLE_TRANSFER, + AXI_DMA_CTRL_DMA_CYCLIC_PREPARE, + AXI_DMA_CTRL_DMA_CYCLIC_START, + AXI_DMA_CTRL_DMA_CYCLIC_STOP, + AXI_DMA_CTRL_DMA_CYCLIC_FREE, + AXI_DMA_CTRL_DMA_PAUSE, + AXI_DMA_CTRL_DMA_RESUME, + AXI_DMA_CTRL_DMA_GET_DAR, + AXI_DMA_CTRL_DMA_GET_SAR, +}; + +#define FH_CHANNEL_MAX_TRANSFER_SIZE (4096) +#define MASTER_SEL_ENABLE 0x55 +#ifdef CONFIG_CHANNEL_ALLOC_MEM_CLASSICS +#define DESC_MAX_SIZE CONFIG_CHANNEL_ALLOC_DESC_NUM +#else +#define DESC_MAX_SIZE 128 +#endif +#define DMA_CONTROLLER_NUMBER 1 + +#define DMA_COMMON_ISR_OPEN 1 +#define DMA_COMMON_ISR_CLOSE 0 +#define DW_DMA_SLAVE_WIDTH_8BIT (0) +#define DW_DMA_SLAVE_WIDTH_16BIT (1) +#define DW_DMA_SLAVE_WIDTH_32BIT (2) + + +/* the user should reference the hw handshaking watermark.. */ +#define DW_DMA_SLAVE_MSIZE_1 (0) +#define DW_DMA_SLAVE_MSIZE_4 (1) +#define DW_DMA_SLAVE_MSIZE_8 (2) +#define DW_DMA_SLAVE_MSIZE_16 (3) +#define DW_DMA_SLAVE_MSIZE_32 (4) +#define DW_DMA_SLAVE_MSIZE_64 (5) +#define DW_DMA_SLAVE_MSIZE_128 (6) +#define DW_DMA_SLAVE_MSIZE_256 (7) + + +#define DW_DMA_SLAVE_INC (0) +#define DW_DMA_SLAVE_DEC (1) +#define DW_DMA_SLAVE_FIX (2) +#define DMA_M2M (0) /* MEM <=> MEM */ +#define DMA_M2P (1) /* MEM => peripheral A */ +#define DMA_P2M (2) /* MEM <= peripheral A */ +#define DMA_P2P (3) /* peripheral A <=> peripheral B */ +#define AUTO_FIND_CHANNEL (0xff) +#define DMA_HW_HANDSHAKING (0) +#define DMA_SW_HANDSHAKING (1) +#define ADDR_RELOAD (0x55) + +/* Platform-configurable bits in CFG_HI */ +#define FHC_CFGH_FCMODE (1 << 0) +#define FHC_CFGH_FIFO_MODE (1 << 1) +#define FHC_CFGH_PROTCTL(x) ((x) << 2) +#define FHC_CFGH_SRC_PER(x) ((x) << 7) +#define FHC_CFGH_DST_PER(x) ((x) << 11) + +/* Platform-configurable bits in CFG_LO */ +#define FHC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */ +#define FHC_CFGL_LOCK_CH_BLOCK (1 << 12) +#define FHC_CFGL_LOCK_CH_XACT (2 << 12) +#define FHC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */ +#define FHC_CFGL_LOCK_BUS_BLOCK (1 << 14) +#define FHC_CFGL_LOCK_BUS_XACT (2 << 14) +#define FHC_CFGL_LOCK_CH (1 << 15) /* channel lockout */ +#define FHC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */ +#define FHC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */ +#define FHC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */ + + +typedef void (*dma_complete_callback)(void *complete_para); + + +/* controller private para... */ +struct fh_axi_dma; +struct dma_transfer; + +struct axi_dma_ops { + void (*axi_dma_isr_process)(struct fh_axi_dma *param); + void (*axi_dma_isr_enable_set)(struct fh_axi_dma *param, + FH_UINT32 enable); + FH_SINT32(*axi_dma_control)(struct fh_axi_dma *dma, + FH_UINT32 cmd, struct dma_transfer *arg); + void (*axi_dma_get_desc_para)(struct fh_axi_dma *dma, + struct dma_transfer *p_transfer, + FH_UINT32 *desc_size, FH_UINT32 *base_phy_add, + FH_UINT32 *each_desc_size, FH_UINT32 *each_desc_cap); +}; + +struct axi_dma_platform_data { + FH_UINT32 id; + FH_UINT8 *name; + //FH_UINT32 irq; + FH_UINT32 base; + FH_UINT32 channel_max_number; + //bind to kernel pri + void *kernel_pri; + void *adapt_pri; +}; + +struct dma_transfer_desc { + FH_UINT32 src_width; + FH_UINT32 src_msize; + FH_UINT32 src_add; + FH_UINT32 src_inc_mode; + + FH_UINT32 dst_width; + FH_UINT32 dst_msize; + FH_UINT32 dst_add; + FH_UINT32 dst_inc_mode; + + FH_UINT32 size; +}; +/* transfer use below */ +struct dma_transfer { + axi_dma_list transfer_list; + struct fh_axi_dma *dma_controller; + void *first_lli; + FH_UINT32 lli_size; + /* new add for allign get desc... */ + FH_UINT32 actual_lli_size; + FH_UINT32 channel_number; + /* which dma you want to use...for fh81....only 0!!! */ + FH_UINT32 dma_number; + FH_UINT32 fc_mode; /* ip->mem. mem->mem. mem->ip */ + FH_UINT32 src_hs; /* src */ + FH_UINT32 src_per; /* src hw handshake number */ + FH_UINT32 dst_hs; /* src */ + FH_UINT32 dst_per; + FH_UINT32 trans_len; + /* this is used when dma finish transfer job */ + dma_complete_callback complete_callback; + void *complete_para; /* for the driver data use the dma driver. */ + /* private para.. */ + void (*prepare_callback)(void *p); + void *prepare_para; + + void (*isr_prepare_callback)(void *p); + void *isr_prepare_para; + + FH_UINT32 period_len; + FH_UINT32 master_flag; + FH_UINT32 src_master; + FH_UINT32 dst_master; + FH_UINT32 cyclic_periods; + + struct dma_transfer_desc *p_desc; + FH_UINT32 desc_size; + +}; + + +struct fh_axi_dma_channel_adapt { + struct dma_chan core_chan; + struct dma_transfer trans; + struct fh_dma_extra ext_para; + struct dma_async_tx_descriptor *ch_adapt_desc_base; + struct dma_transfer_desc *desc_head; + u32 desc_size; + struct dma_slave_config sconfig; + struct fh_cyclic_desc cyclic; + spinlock_t lock; +}; + +struct fh_axi_dma_adapt { + struct dma_device dma; + struct tasklet_struct tasklet; + struct clk *clk; + //bind to driver data. help to find the driver handle + struct fh_axi_dma *driver_pri; + struct platform_device *pdev; + struct fh_axi_dma_channel_adapt chan[0]; + +}; + +FH_UINT32 cal_axi_dma_channel(void *regs); +struct axi_dma_ops *get_fh_axi_dma_ops(struct fh_axi_dma *p_axi_dma); +struct fh_axi_dma *fh_axi_dma_probe(struct axi_dma_platform_data *priv_data); + +#endif diff --git a/drivers/dma/fh_axi_dma_driver.c b/drivers/dma/fh_axi_dma_driver.c new file mode 100644 index 00000000..b806bd69 --- /dev/null +++ b/drivers/dma/fh_axi_dma_driver.c @@ -0,0 +1,1400 @@ +#include "fh_axi_dma_adapt.h" + + +#ifndef BIT +#define BIT(x) (1 << (x)) +#endif + +//#define AXI_DMA_DEBUG +#define AXI_DESC_ALLIGN 64 /*DO NOT TOUCH!!!*/ +#define AXI_DESC_ALLIGN_BIT_MASK 0x7f /*DO NOT TOUCH!!!*/ +#define lift_shift_bit_num(bit_num) (1 << bit_num) +#define AXI_DMA_MAX_NR_CHANNELS 8 +#ifndef GENMASK +#define GENMASK(h, l) (((~0UL) << (l)) & (~0UL >> (sizeof(long) * 8 - 1 - (h)))) +#endif +#ifndef GENMASK_ULL +#define GENMASK_ULL(h, l) \ + (((~0ULL) << (l)) & (~0ULL >> (sizeof(long long) * 8 - 1 - (h)))) +#endif + +/* DMAC_CFG */ +#define DMAC_EN_POS 0 +#define DMAC_EN_MASK BIT(DMAC_EN_POS) +#define INT_EN_POS 1 +#define INT_EN_MASK BIT(INT_EN_POS) +/* CH_CTL_H */ +#define CH_CTL_H_ARLEN_EN(n) ((n) << 6) /* 32+6 = 38 */ +#define CH_CTL_H_ARLEN(n) ((n) << 7) /* 32+7 = 39 */ +#define CH_CTL_H_AWLEN_EN(n) ((n) << 15) /* 32+15 = 47 */ +#define CH_CTL_H_AWLEN(n) ((n) << 16) /* 32+16 = 48 */ +#define CH_CTL_H_IOC_BLKTFR BIT(26) +#define CH_CTL_H_LLI_LAST BIT(30) +#define CH_CTL_H_LLI_VALID BIT(31) + +/* CH_CTL_L */ +#define CH_CTL_L_LAST_WRITE_EN BIT(30) +#define CH_CTL_L_AR_CACHE(n) ((n) << 22) +#define CH_CTL_L_AW_CACHE(n) ((n) << 26) +#define CH_CTL_L_DST_WIDTH_POS 11 +#define CH_CTL_L_SRC_WIDTH_POS 8 +#define CH_CTL_L_DST_INC_POS 6 +#define CH_CTL_L_SRC_INC_POS 4 +#define CH_CTL_L_DST_MAST BIT(2) +#define CH_CTL_L_SRC_MAST BIT(0) + +/* CH_CFG_H */ +#define CH_CFG_H_PRIORITY_POS 17 +#define CH_CFG_H_HS_SEL_DST_POS 4 +#define CH_CFG_H_HS_SEL_SRC_POS 3 +#define CH_CFG_H_TT_FC_POS 0 + +#define CH_CFG_H_DST_OSR_LMT(n) ((n) << 27) +#define CH_CFG_H_SRC_OSR_LMT(n) ((n) << 23) +/* CH_CFG_L */ +#define CH_CFG_L_DST_MULTBLK_TYPE_POS 2 +#define CH_CFG_L_SRC_MULTBLK_TYPE_POS 0 + +#define AXI_DMA_CTLL_DST_WIDTH(n) ((n) << 11) /* bytes per element */ +#define AXI_DMA_CTLL_SRC_WIDTH(n) ((n) << 8) +#define AXI_DMA_CTLL_DST_INC_MODE(n) ((n) << 6) +#define AXI_DMA_CTLL_SRC_INC_MODE(n) ((n) << 4) + +#define AXI_DMA_CTLL_DST_MSIZE(n) ((n) << 18) +#define AXI_DMA_CTLL_SRC_MSIZE(n) ((n) << 14) + + +#define AXI_DMA_CTLL_DMS(n) ((n) << 2) +#define AXI_DMA_CTLL_SMS(n) ((n) << 0) +/* caution ,diff with ahb dma */ +#define AXI_DMA_CFGH_FC(n) ((n) << 0) +#define AXI_DMA_CFGH_DST_PER(n) ((n) << 3) + +#define DW_REG(name) \ + FH_UINT32 name; \ + FH_UINT32 __pad_##name + + +#define __dma_raw_writeb(v, a) (*(volatile FH_UINT8 *)(a) = (v)) +#define __dma_raw_writew(v, a) (*(volatile FH_UINT16 *)(a) = (v)) +#define __dma_raw_writel(v, a) (*(volatile FH_UINT32 *)(a) = (v)) + +#define __dma_raw_readb(a) (*(volatile FH_UINT8 *)(a)) +#define __dma_raw_readw(a) (*(volatile FH_UINT16 *)(a)) +#define __dma_raw_readl(a) (*(volatile FH_UINT32 *)(a)) + +#define dw_readl(dw, name) \ + __dma_raw_readl(&(((struct dw_axi_dma_regs *)dw->regs)->name)) +#define dw_writel(dw, name, val) \ + __dma_raw_writel((val), &(((struct dw_axi_dma_regs *)dw->regs)->name)) +#define dw_readw(dw, name) \ + __dma_raw_readw(&(((struct dw_axi_dma_regs *)dw->regs)->name)) +#define dw_writew(dw, name, val) \ + __dma_raw_writew((val), &(((struct dw_axi_dma_regs *)dw->regs)->name)) + +#define CONTROLLER_STATUS_CLOSED (0) +#define CONTROLLER_STATUS_OPEN (1) + +#define CHANNEL_STATUS_CLOSED (0) +#define CHANNEL_STATUS_OPEN (1) +#define CHANNEL_STATUS_IDLE (2) +#define CHANNEL_STATUS_BUSY (3) +#define SINGLE_TRANSFER (0) +#define CYCLIC_TRANSFER (1) +#define DEFAULT_TRANSFER SINGLE_TRANSFER +#define CHANNEL_REAL_FREE (0) +#define CHANNEL_NOT_FREE (1) + +#define axi_dma_list_entry(node, type, member) \ + ((type *)((char *)(node) - (unsigned long)(&((type *)0)->member))) + +#define axi_dma_list_for_each_entry_safe(pos, n, head, member) \ + for (pos = axi_dma_list_entry((head)->next, typeof(*pos), member), \ + n = axi_dma_list_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = axi_dma_list_entry(n->member.next, typeof(*n), member)) +/**************************************************************************** + * ADT section + * add definition of user defined Data Type that only be used in this file here + ***************************************************************************/ +enum { + DWAXIDMAC_ARWLEN_1 = 0, + DWAXIDMAC_ARWLEN_2 = 1, + DWAXIDMAC_ARWLEN_4 = 3, + DWAXIDMAC_ARWLEN_8 = 7, + DWAXIDMAC_ARWLEN_16 = 15, + DWAXIDMAC_ARWLEN_32 = 31, + DWAXIDMAC_ARWLEN_64 = 63, + DWAXIDMAC_ARWLEN_128 = 127, + DWAXIDMAC_ARWLEN_256 = 255, + DWAXIDMAC_ARWLEN_MIN = DWAXIDMAC_ARWLEN_1, + DWAXIDMAC_ARWLEN_MAX = DWAXIDMAC_ARWLEN_256 +}; + +enum { + DWAXIDMAC_BURST_TRANS_LEN_1 = 0, + DWAXIDMAC_BURST_TRANS_LEN_4, + DWAXIDMAC_BURST_TRANS_LEN_8, + DWAXIDMAC_BURST_TRANS_LEN_16, + DWAXIDMAC_BURST_TRANS_LEN_32, + DWAXIDMAC_BURST_TRANS_LEN_64, + DWAXIDMAC_BURST_TRANS_LEN_128, + DWAXIDMAC_BURST_TRANS_LEN_256, + DWAXIDMAC_BURST_TRANS_LEN_512, + DWAXIDMAC_BURST_TRANS_LEN_1024 +}; + +enum { + DWAXIDMAC_CH_CTL_L_INC = 0, + DWAXIDMAC_CH_CTL_L_NOINC +}; + +enum { + DWAXIDMAC_HS_SEL_HW = 0, + DWAXIDMAC_HS_SEL_SW +}; + +enum { + DWAXIDMAC_TT_FC_MEM_TO_MEM_DMAC = 0, + DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC, + DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC, + DWAXIDMAC_TT_FC_PER_TO_PER_DMAC, + DWAXIDMAC_TT_FC_PER_TO_MEM_SRC, + DWAXIDMAC_TT_FC_PER_TO_PER_SRC, + DWAXIDMAC_TT_FC_MEM_TO_PER_DST, + DWAXIDMAC_TT_FC_PER_TO_PER_DST +}; + +enum { + DWAXIDMAC_MBLK_TYPE_CONTIGUOUS = 0, + DWAXIDMAC_MBLK_TYPE_RELOAD, + DWAXIDMAC_MBLK_TYPE_SHADOW_REG, + DWAXIDMAC_MBLK_TYPE_LL +}; + + +/** + * DW AXI DMA channel interrupts + * + * @DWAXIDMAC_IRQ_NONE: Bitmask of no one interrupt + * @DWAXIDMAC_IRQ_BLOCK_TRF: Block transfer complete + * @DWAXIDMAC_IRQ_DMA_TRF: Dma transfer complete + * @DWAXIDMAC_IRQ_SRC_TRAN: Source transaction complete + * @DWAXIDMAC_IRQ_DST_TRAN: Destination transaction complete + * @DWAXIDMAC_IRQ_SRC_DEC_ERR: Source decode error + * @DWAXIDMAC_IRQ_DST_DEC_ERR: Destination decode error + * @DWAXIDMAC_IRQ_SRC_SLV_ERR: Source slave error + * @DWAXIDMAC_IRQ_DST_SLV_ERR: Destination slave error + * @DWAXIDMAC_IRQ_LLI_RD_DEC_ERR: LLI read decode error + * @DWAXIDMAC_IRQ_LLI_WR_DEC_ERR: LLI write decode error + * @DWAXIDMAC_IRQ_LLI_RD_SLV_ERR: LLI read slave error + * @DWAXIDMAC_IRQ_LLI_WR_SLV_ERR: LLI write slave error + * @DWAXIDMAC_IRQ_INVALID_ERR: LLI invalid error or Shadow register error + * @DWAXIDMAC_IRQ_MULTIBLKTYPE_ERR: Slave Interface Multiblock type error + * @DWAXIDMAC_IRQ_DEC_ERR: Slave Interface decode error + * @DWAXIDMAC_IRQ_WR2RO_ERR: Slave Interface write to read only error + * @DWAXIDMAC_IRQ_RD2RWO_ERR: Slave Interface read to write only error + * @DWAXIDMAC_IRQ_WRONCHEN_ERR: Slave Interface write to channel error + * @DWAXIDMAC_IRQ_SHADOWREG_ERR: Slave Interface shadow reg error + * @DWAXIDMAC_IRQ_WRONHOLD_ERR: Slave Interface hold error + * @DWAXIDMAC_IRQ_LOCK_CLEARED: Lock Cleared Status + * @DWAXIDMAC_IRQ_SRC_SUSPENDED: Source Suspended Status + * @DWAXIDMAC_IRQ_SUSPENDED: Channel Suspended Status + * @DWAXIDMAC_IRQ_DISABLED: Channel Disabled Status + * @DWAXIDMAC_IRQ_ABORTED: Channel Aborted Status + * @DWAXIDMAC_IRQ_ALL_ERR: Bitmask of all error interrupts + * @DWAXIDMAC_IRQ_ALL: Bitmask of all interrupts + */ +enum { + DWAXIDMAC_IRQ_NONE = 0, + DWAXIDMAC_IRQ_BLOCK_TRF = BIT(0), + DWAXIDMAC_IRQ_DMA_TRF = BIT(1), + DWAXIDMAC_IRQ_SRC_TRAN = BIT(3), + DWAXIDMAC_IRQ_DST_TRAN = BIT(4), + DWAXIDMAC_IRQ_SRC_DEC_ERR = BIT(5), + DWAXIDMAC_IRQ_DST_DEC_ERR = BIT(6), + DWAXIDMAC_IRQ_SRC_SLV_ERR = BIT(7), + DWAXIDMAC_IRQ_DST_SLV_ERR = BIT(8), + DWAXIDMAC_IRQ_LLI_RD_DEC_ERR = BIT(9), + DWAXIDMAC_IRQ_LLI_WR_DEC_ERR = BIT(10), + DWAXIDMAC_IRQ_LLI_RD_SLV_ERR = BIT(11), + DWAXIDMAC_IRQ_LLI_WR_SLV_ERR = BIT(12), + DWAXIDMAC_IRQ_INVALID_ERR = BIT(13), + DWAXIDMAC_IRQ_MULTIBLKTYPE_ERR = BIT(14), + DWAXIDMAC_IRQ_DEC_ERR = BIT(16), + DWAXIDMAC_IRQ_WR2RO_ERR = BIT(17), + DWAXIDMAC_IRQ_RD2RWO_ERR = BIT(18), + DWAXIDMAC_IRQ_WRONCHEN_ERR = BIT(19), + DWAXIDMAC_IRQ_SHADOWREG_ERR = BIT(20), + DWAXIDMAC_IRQ_WRONHOLD_ERR = BIT(21), + DWAXIDMAC_IRQ_LOCK_CLEARED = BIT(27), + DWAXIDMAC_IRQ_SRC_SUSPENDED = BIT(28), + DWAXIDMAC_IRQ_SUSPENDED = BIT(29), + DWAXIDMAC_IRQ_DISABLED = BIT(30), + DWAXIDMAC_IRQ_ABORTED = BIT(31), + DWAXIDMAC_IRQ_ALL_ERR = (GENMASK(21, 16) | GENMASK(14, 5)), + DWAXIDMAC_IRQ_ALL = GENMASK(31, 0) +}; + +struct axi_dma_lli { + FH_UINT32 sar_lo; + FH_UINT32 sar_hi; + FH_UINT32 dar_lo; + FH_UINT32 dar_hi; + FH_UINT32 block_ts_lo; + FH_UINT32 block_ts_hi; + FH_UINT32 llp_lo; + FH_UINT32 llp_hi; + FH_UINT32 ctl_lo; + FH_UINT32 ctl_hi; + FH_UINT32 sstat; + FH_UINT32 dstat; + FH_UINT32 status_lo; + FH_UINT32 status_hi; + FH_UINT32 reserved_lo; + FH_UINT32 reserved_hi; +}; + +/* Hardware register definitions. */ +struct dw_axi_dma_chan_regs { + DW_REG(SAR); /* 0x0 ~ 0x7*/ + DW_REG(DAR); /* 0x8 ~ 0xf*/ + DW_REG(BLOCK_TS); /* 0x10 ~ 0x17*/ + FH_UINT32 CTL_LO; + FH_UINT32 CTL_HI; /* 0x18 ~ 0x1f*/ + FH_UINT32 CFG_LO; + FH_UINT32 CFG_HI; /* 0x20 ~ 0x27*/ + DW_REG(LLP); /* 0x28 ~ 0x2f*/ + FH_UINT32 STATUS_LO; + FH_UINT32 STATUS_HI; /* 0x30 ~ 0x37*/ + DW_REG(SWHS_SRC); /* 0x38 ~ 0x3f*/ + DW_REG(SWHS_DST); /* 0x40 ~ 0x47*/ + DW_REG(BLK_TFR_RESU); + DW_REG(ID); + DW_REG(QOS); + DW_REG(SSTAT); + DW_REG(DSTAT); + DW_REG(SSTATAR); + DW_REG(DSTATAR); + FH_UINT32 INTSTATUS_EN_LO; + FH_UINT32 INTSTATUS_EN_HI; + FH_UINT32 INTSTATUS_LO; + FH_UINT32 INTSTATUS_HI; + FH_UINT32 INTSIGNAL_LO; + FH_UINT32 INTSIGNAL_HI; + FH_UINT32 INTCLEAR_LO; + FH_UINT32 INTCLEAR_HI; + FH_UINT32 rev[24]; +}; + +struct dw_axi_dma_regs { + DW_REG(ID); /* 0x0 */ + DW_REG(COMPVER); /* 0x8 */ + DW_REG(CFG); /* 0x10 */ + FH_UINT32 CHEN_LO; /* 0x18 */ + FH_UINT32 CHEN_HI; /* 0x1c */ + DW_REG(reserved_20_27); /* 0x20 */ + DW_REG(reserved_28_2f); /* 0x28 */ + DW_REG(INTSTATUS); /* 0x30 */ + DW_REG(COM_INTCLEAR); /* 0x38 */ + DW_REG(COM_INTSTATUS_EN); /* 0x40 */ + DW_REG(COM_INTSIGNAL_EN); /* 0x48 */ + DW_REG(COM_INTSTATUS); /* 0x50 */ + DW_REG(RESET); /* 0x58 */ + FH_UINT32 reserved[40]; /* 0x60 */ + struct dw_axi_dma_chan_regs CHAN[AXI_DMA_MAX_NR_CHANNELS];/* 0x100 */ +}; + +struct dw_axi_dma { + /* vadd */ + void *regs; + FH_UINT32 channel_max_number; + FH_UINT32 controller_status; + FH_UINT32 id; + char name[20]; +}; + +struct dma_channel { + FH_UINT32 channel_status; /* open, busy ,closed */ + FH_UINT32 desc_trans_size; + axi_dma_lock_t channel_lock; + axi_dma_list queue; + struct dma_transfer *active_trans; + FH_UINT32 open_flag; + FH_UINT32 desc_total_no; + FH_UINT32 free_index; + FH_UINT32 used_index; + FH_UINT32 desc_left_cnt; + /*malloc maybe not allign; driver will malloc (size + cache line) incase*/ + FH_UINT32 allign_malloc; + FH_UINT32 allign_phy; + struct axi_dma_lli *base_lli; + FH_UINT32 base_lli_phy; + FH_UINT32 int_sig; + FH_UINT32 status; +}; + +struct fh_axi_dma { + /* myown */ + void *kernel_pri;// used for malloc........ + void *adapt_pri;// use for call adapt driver + struct axi_dma_ops ops; + struct dw_axi_dma dwc; + /* channel obj */ + struct dma_channel dma_channel[AXI_DMA_MAX_NR_CHANNELS]; +}; + +/****************************************************************************** + * Function prototype section + * add prototypes for all functions called by this file,execepting those + * declared in header file + *****************************************************************************/ + +/***************************************************************************** + * Global variables section - Exported + * add declaration of global variables that will be exported here + * e.g. + * int8_t foo; + ****************************************************************************/ + + +/***************************************************************************** + * static fun; + *****************************************************************************/ +static void fh_axi_dma_cyclic_stop(struct dma_transfer *p); +static void fh_axi_dma_cyclic_start(struct dma_transfer *p); +static void fh_axi_dma_cyclic_prep(struct fh_axi_dma *fh_dma_p, +struct dma_transfer *p); +static void fh_axi_dma_cyclic_free(struct dma_transfer *p); +static void fh_axi_dma_cyclic_pause(struct dma_transfer *p); +static void fh_axi_dma_cyclic_resume(struct dma_transfer *p); +static FH_UINT32 vir_lli_to_phy_lli(struct axi_dma_lli *base_lli, +FH_UINT32 base_lli_phy, struct axi_dma_lli *cal_lli); +/***************************************************************************** + * Global variables section - Local + * define global variables(will be refered only in this file) here, + * static keyword should be used to limit scope of local variable to this file + * e.g. + * static uint8_t ufoo; + *****************************************************************************/ + +/* function body */ +/***************************************************************************** + * Description: + * add funtion description here + * Parameters: + * description for each argument, new argument starts at new line + * Return: + * what does this function returned? + *****************************************************************************/ + +static void dump_lli(struct axi_dma_lli *p_lli, struct axi_dma_lli *base_lli, FH_UINT32 base_lli_phy) +{ + FH_UINT32 phy_add; + + phy_add = vir_lli_to_phy_lli(base_lli, base_lli_phy, p_lli); + + FH_AXI_DMA_PRINT("SAR: 0x%08x DAR: 0x%08x LLP: 0x%08x BTS 0x%08x CTL: 0x%08x:%08x LLI_PHY_ADD: 0x%x\n", + (p_lli->sar_lo), + (p_lli->dar_lo), + (p_lli->llp_lo), + (p_lli->block_ts_lo), + (p_lli->ctl_hi), + (p_lli->ctl_lo), + (FH_UINT32)phy_add); + +} + +static void dump_channel_reg(struct fh_axi_dma *p_dma, struct dma_transfer *p_transfer) +{ + struct dw_axi_dma *temp_dwc; + + FH_UINT32 chan_no = p_transfer->channel_number; + + temp_dwc = &p_dma->dwc; + + FH_AXI_DMA_PRINT("[CHAN : %d]SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x CFG: 0x%x:%08x INTEN :0x%x INTSTATUS: 0x%x\n", + chan_no, + dw_readl(temp_dwc, CHAN[chan_no].SAR), + dw_readl(temp_dwc, CHAN[chan_no].DAR), + dw_readl(temp_dwc, CHAN[chan_no].LLP), + dw_readl(temp_dwc, CHAN[chan_no].CTL_HI), + dw_readl(temp_dwc, CHAN[chan_no].CTL_LO), + dw_readl(temp_dwc, CHAN[chan_no].CFG_HI), + dw_readl(temp_dwc, CHAN[chan_no].CFG_LO), + dw_readl(temp_dwc, CHAN[chan_no].INTSTATUS_EN_LO), + dw_readl(temp_dwc, CHAN[chan_no].INTSTATUS_LO) + ); + +} + +static void dump_dma_common_reg(struct fh_axi_dma *p_dma) +{ + struct dw_axi_dma *temp_dwc; + + temp_dwc = &p_dma->dwc; + if (!temp_dwc->regs) + return; + FH_AXI_DMA_PRINT("ID: 0x%x COMPVER: 0x%x CFG: 0x%x CHEN: 0x%x:%08x INTSTATUS: 0x%x\ + COM_INTSTATUS_EN: 0x%x COM_INTSIGNAL_EN: %x COM_INTSTATUS: %x\n", + dw_readl(temp_dwc, ID), + dw_readl(temp_dwc, COMPVER), + dw_readl(temp_dwc, CFG), + dw_readl(temp_dwc, CHEN_HI), + dw_readl(temp_dwc, CHEN_LO), + dw_readl(temp_dwc, INTSTATUS), + dw_readl(temp_dwc, COM_INTSTATUS_EN), + dw_readl(temp_dwc, COM_INTSIGNAL_EN), + dw_readl(temp_dwc, COM_INTSTATUS) + ); + +} + + +static void dump_chan_xfer_info(struct fh_axi_dma *p_dma, struct dma_transfer *p_transfer) +{ + FH_UINT32 i; + struct axi_dma_lli *p_lli; + + p_lli = (struct axi_dma_lli *)p_transfer->first_lli; + dump_dma_common_reg(p_dma); + dump_channel_reg(p_dma, p_transfer); + for (i = 0; i < p_transfer->desc_size; i++) { + dump_lli(&p_lli[i], p_dma->dma_channel[p_transfer->channel_number].base_lli, + p_dma->dma_channel[p_transfer->channel_number].base_lli_phy); + } +} + +static FH_UINT32 allign_func(FH_UINT32 in_addr, FH_UINT32 allign_size, FH_UINT32 *phy_back_allign) +{ + *phy_back_allign = (*phy_back_allign + allign_size - 1) & (~(allign_size - 1)); + return (in_addr + allign_size - 1) & (~(allign_size - 1)); +} + +static FH_UINT32 vir_lli_to_phy_lli(struct axi_dma_lli *base_lli, +FH_UINT32 base_lli_phy, struct axi_dma_lli *cal_lli) +{ + FH_UINT32 ret; + + ret = base_lli_phy + ((FH_UINT32)cal_lli - (FH_UINT32)base_lli); + return ret; +} + +struct axi_dma_lli *get_desc(struct fh_axi_dma *p_dma, +struct dma_transfer *p_transfer, FH_UINT32 lli_size) +{ + struct axi_dma_lli *ret_lli; + FH_UINT32 free_index; + FH_UINT32 allign_left; + FH_UINT32 totoal_desc; + FH_UINT32 actual_get_desc = 0; + FH_UINT32 totoal_free_desc; + + totoal_free_desc = + p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt; + free_index = p_dma->dma_channel[p_transfer->channel_number].free_index; + totoal_desc = p_dma->dma_channel[p_transfer->channel_number].desc_total_no; + allign_left = totoal_desc - free_index; + + /* check first.. */ + if (totoal_free_desc < lli_size) { + FH_AXI_DMA_PRINT("not enough desc to get...\n"); + FH_AXI_DMA_PRINT("get size is %d,left is %d\n", lli_size, totoal_free_desc); + return AXI_DMA_NULL; + } + + if (lli_size > allign_left) { + /* if allign desc not enough...just reset null.... */ + if ((totoal_free_desc - allign_left) < lli_size) { + FH_AXI_DMA_PRINT("not enough desc to get...\n"); + FH_AXI_DMA_PRINT( + "app need size is %d, totoal left is %d, allign left is %d\n", + lli_size, totoal_free_desc, allign_left); + FH_AXI_DMA_PRINT("from head to get desc size is %d, actual get is %d\n", + (totoal_free_desc - allign_left), + (allign_left + lli_size)); + return AXI_DMA_NULL; + } else { + actual_get_desc = allign_left + lli_size; + free_index = 0; + } + } + + ret_lli = &p_dma->dma_channel[p_transfer->channel_number].base_lli[free_index]; + p_dma->dma_channel[p_transfer->channel_number].free_index += + actual_get_desc; + p_dma->dma_channel[p_transfer->channel_number].free_index %= + p_dma->dma_channel[p_transfer->channel_number].desc_total_no; + p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt -= + actual_get_desc; + p_transfer->lli_size = lli_size; + p_transfer->actual_lli_size = actual_get_desc; + return ret_lli; +} + +FH_UINT32 put_desc(struct fh_axi_dma *p_dma, struct dma_transfer *p_transfer) +{ + FH_UINT32 lli_size; + + lli_size = p_transfer->actual_lli_size; + p_dma->dma_channel[p_transfer->channel_number].used_index += lli_size; + p_dma->dma_channel[p_transfer->channel_number].used_index %= + p_dma->dma_channel[p_transfer->channel_number].desc_total_no; + p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt += lli_size; + p_transfer->lli_size = 0; + p_transfer->actual_lli_size = 0; + return AXI_DMA_RET_OK; +} + +#if defined CONFIG_ARCH_FH8636 || defined CONFIG_ARCH_FH8852V101 +#define axi_dma_reset(...) +#else +static void axi_dma_reset(struct dw_axi_dma *axi_dma_obj) +{ + FH_UINT32 ret; + FH_UINT32 time_out = 0xffffff; + + dw_writel(axi_dma_obj, RESET, 1); + do { + ret = dw_readl(axi_dma_obj, RESET); + time_out--; + } while (ret && time_out); + + if (!time_out) + FH_AXI_DMA_PRINT("%s : time out..\n", __func__); +} +#endif + +static void axi_dma_enable(struct dw_axi_dma *axi_dma_obj) +{ + FH_UINT32 ret; + + ret = dw_readl(axi_dma_obj, CFG); + ret |= BIT(DMAC_EN_POS); + dw_writel(axi_dma_obj, CFG, ret); +} + +static void axi_dma_isr_common_enable(struct dw_axi_dma *axi_dma_obj) +{ + FH_UINT32 ret; + + ret = dw_readl(axi_dma_obj, CFG); + ret |= BIT(INT_EN_POS); + dw_writel(axi_dma_obj, CFG, ret); +} + +static void axi_dma_isr_common_disable(struct dw_axi_dma *axi_dma_obj) +{ + FH_UINT32 ret; + + ret = dw_readl(axi_dma_obj, CFG); + ret &= ~(BIT(INT_EN_POS)); + dw_writel(axi_dma_obj, CFG, ret); +} + +static void handle_dma_open(struct fh_axi_dma *p_dma) +{ + struct dw_axi_dma *temp_dwc; + + temp_dwc = &p_dma->dwc; + axi_dma_enable(temp_dwc); + axi_dma_isr_common_enable(temp_dwc); + p_dma->dwc.controller_status = CONTROLLER_STATUS_OPEN; +} + +static void handle_dma_close(struct fh_axi_dma *p_dma) +{ + FH_UINT32 i; + struct dw_axi_dma *temp_dwc; + + temp_dwc = &p_dma->dwc; + /* take lock */ + for (i = 0; i < p_dma->dwc.channel_max_number; i++) + p_dma->dma_channel[i].channel_status = CHANNEL_STATUS_CLOSED; + + axi_dma_reset(temp_dwc); + p_dma->dwc.controller_status = CONTROLLER_STATUS_CLOSED; + +} + + +static FH_UINT32 check_channel_real_free(struct fh_axi_dma *p_dma, +FH_UINT32 channel_number) +{ + struct dw_axi_dma *temp_dwc; + FH_UINT32 ret_status; + + temp_dwc = &p_dma->dwc; + AXI_DMA_ASSERT(channel_number < p_dma->dwc.channel_max_number); + + ret_status = dw_readl(temp_dwc, CHEN_LO); + if (ret_status & lift_shift_bit_num(channel_number)) { + FH_AXI_DMA_PRINT("channel_number : %d is busy....\n", channel_number); + return CHANNEL_NOT_FREE; + } + return CHANNEL_REAL_FREE; +} + +static FH_ERR handle_request_channel(struct fh_axi_dma *p_dma, +struct dma_transfer *p_transfer) +{ + FH_UINT32 i; + FH_ERR ret_status = AXI_DMA_RET_OK; + + if (p_transfer->channel_number == AUTO_FIND_CHANNEL) { + /* check each channel lock,find a free channel... */ + for (i = 0; i < p_dma->dwc.channel_max_number; i++) { + ret_status = axi_dma_trylock(&p_dma->dma_channel[i].channel_lock); + if (ret_status == AXI_DMA_RET_OK) + break; + } + + if (i < p_dma->dwc.channel_max_number) { + ret_status = check_channel_real_free(p_dma, i); + if (ret_status != CHANNEL_REAL_FREE) { + FH_AXI_DMA_PRINT("auto request channel error\n"); + AXI_DMA_ASSERT(ret_status == CHANNEL_REAL_FREE); + } + /* caution : channel is already locked here.... */ + p_transfer->channel_number = i; + /* bind to the controller. */ + /* p_transfer->dma_controller = p_dma; */ + p_dma->dma_channel[i].channel_status = CHANNEL_STATUS_OPEN; + } else { + FH_AXI_DMA_PRINT("[dma]: auto request err, no free channel\n"); + return -AXI_DMA_RET_NO_MEM; + } + } + /* request channel by user */ + else { + AXI_DMA_ASSERT(p_transfer->channel_number < p_dma->dwc.channel_max_number); + ret_status = axi_dma_lock( + &p_dma->dma_channel[p_transfer->channel_number].channel_lock, + AXI_DMA_TICK_PER_SEC * 2); + if (ret_status != AXI_DMA_RET_OK) { + FH_AXI_DMA_PRINT("[dma]: request %d channel err.\n", p_transfer->channel_number); + return -AXI_DMA_RET_NO_MEM; + } + + /*enter_critical();*/ + ret_status = check_channel_real_free(p_dma, p_transfer->channel_number); + if (ret_status != CHANNEL_REAL_FREE) { + FH_AXI_DMA_PRINT("user request channel error\n"); + AXI_DMA_ASSERT(ret_status == CHANNEL_REAL_FREE); + } + /* bind to the controller */ + /* p_transfer->dma_controller = p_dma; */ + p_dma->dma_channel[p_transfer->channel_number].channel_status = + CHANNEL_STATUS_OPEN; + /* exit_critical(); */ + } + + /* malloc desc for this one channel... */ + /* fix me.... */ + + p_dma->dma_channel[p_transfer->channel_number].allign_malloc = + (FH_UINT32)axi_dma_malloc_desc(p_dma->kernel_pri, + (p_dma->dma_channel[p_transfer->channel_number].desc_total_no * + sizeof(struct axi_dma_lli)) + + AXI_DESC_ALLIGN, &p_dma->dma_channel[p_transfer->channel_number].allign_phy); + + if (!p_dma->dma_channel[p_transfer->channel_number].allign_malloc) { + /* release channel */ + FH_AXI_DMA_PRINT("[dma]: no mem to malloc channel%d desc..\n", + p_transfer->channel_number); + p_dma->dma_channel[p_transfer->channel_number].channel_status = + CHANNEL_STATUS_CLOSED; + axi_dma_unlock( + &p_dma->dma_channel[p_transfer->channel_number].channel_lock); + return -AXI_DMA_RET_NO_MEM; + } + + p_dma->dma_channel[p_transfer->channel_number].base_lli_phy = + p_dma->dma_channel[p_transfer->channel_number].allign_phy; + p_dma->dma_channel[p_transfer->channel_number].base_lli = + (struct axi_dma_lli *)allign_func( + p_dma->dma_channel[p_transfer->channel_number].allign_malloc, + AXI_DESC_ALLIGN, &p_dma->dma_channel[p_transfer->channel_number].base_lli_phy); + + if (!p_dma->dma_channel[p_transfer->channel_number].base_lli) { + FH_AXI_DMA_PRINT("request desc failed..\n"); + AXI_DMA_ASSERT(p_dma->dma_channel[p_transfer->channel_number].base_lli != + AXI_DMA_NULL); + } + + if ((FH_UINT32)p_dma->dma_channel[p_transfer->channel_number].base_lli % + AXI_DESC_ALLIGN) { + FH_AXI_DMA_PRINT("malloc is not cache allign.."); + } + + /* axi_dma_memset((void *)dma_trans_desc->first_lli, 0, lli_size * sizeof(struct */ + /* axi_dma_lli)); */ + axi_dma_memset((void *)p_dma->dma_channel[p_transfer->channel_number].base_lli, + 0, p_dma->dma_channel[p_transfer->channel_number].desc_total_no * + sizeof(struct axi_dma_lli)); + + p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt = + p_dma->dma_channel[p_transfer->channel_number].desc_total_no; + p_dma->dma_channel[p_transfer->channel_number].free_index = 0; + p_dma->dma_channel[p_transfer->channel_number].used_index = 0; + + + return AXI_DMA_RET_OK; +} + +static void fhc_chan_able_set(struct fh_axi_dma *p_dma, +struct dma_transfer *p_transfer, FH_SINT32 enable) +{ + struct dw_axi_dma *temp_dwc; + FH_SINT32 ret, ret_read; + FH_UINT32 time_out = 0xffffff; + FH_UINT32 chan_mask = lift_shift_bit_num(p_transfer->channel_number); + + temp_dwc = &p_dma->dwc; + ret = dw_readl(temp_dwc, CHEN_LO); + ret &= ~(chan_mask); + ret |= enable ? ((chan_mask) | (chan_mask << 8)) : (chan_mask << 8); + + dw_writel(temp_dwc, CHEN_LO, ret); + /*enable == 1 do not check. maybe just isr break. the bit dma will self clear*/ + if (enable == 0) { + do { + ret_read = dw_readl(temp_dwc, CHEN_LO); + time_out--; + } while ((!!(ret_read & chan_mask) != enable) && time_out); + } + + if (!time_out) + dump_chan_xfer_info(p_dma, p_transfer); +} + +static void fhc_chan_susp_set(struct fh_axi_dma *p_dma, +struct dma_transfer *p_transfer, FH_SINT32 enable) +{ + struct dw_axi_dma *temp_dwc; + FH_SINT32 ret; + FH_UINT32 time_out = 0xffffff; + FH_SINT32 chan_no = p_transfer->channel_number; + FH_UINT32 chan_mask = lift_shift_bit_num(p_transfer->channel_number); + + temp_dwc = &p_dma->dwc; + ret = dw_readl(temp_dwc, CHEN_LO); + ret &= ~(chan_mask << 16); + ret |= enable ? ((chan_mask << 16) | (chan_mask << 24)) : (chan_mask << 24); + dw_writel(temp_dwc, CHEN_LO, ret); + + if (enable) { + do { + ret = dw_readl(temp_dwc, CHAN[chan_no].INTSTATUS_LO); + time_out--; + } while ((!!(ret & DWAXIDMAC_IRQ_SUSPENDED) != enable) && time_out); + + if (!time_out) { + dump_chan_xfer_info(p_dma, p_transfer); + return; + } + /*clear susp irp*/ + dw_writel(temp_dwc, CHAN[chan_no].INTCLEAR_LO, DWAXIDMAC_IRQ_SUSPENDED); + } +} + +static FH_UINT32 handle_release_channel(struct fh_axi_dma *p_dma, +struct dma_transfer *p_transfer) +{ + FH_UINT32 ret_status; + /* enter_critical(); */ + ret_status = p_dma->dma_channel[p_transfer->channel_number].channel_status; + + AXI_DMA_ASSERT(p_transfer->channel_number < p_dma->dwc.channel_max_number); + + if (ret_status == CHANNEL_STATUS_CLOSED) { + FH_AXI_DMA_PRINT( + "release channel error,reason: release a closed channel!!\n"); + AXI_DMA_ASSERT(ret_status != CHANNEL_STATUS_CLOSED); + } + fhc_chan_able_set(p_dma, p_transfer, 0); + + axi_dma_unlock( + &p_dma->dma_channel[p_transfer->channel_number].channel_lock); + /* p_transfer->dma_controller = AXI_DMA_NULL; */ + p_dma->dma_channel[p_transfer->channel_number].channel_status = + CHANNEL_STATUS_CLOSED; + p_dma->dma_channel[p_transfer->channel_number].open_flag = + DEFAULT_TRANSFER; + /* exit_critical(); */ + + axi_dma_free_desc(p_dma->kernel_pri, + p_dma->dma_channel[p_transfer->channel_number].desc_total_no * + sizeof(struct axi_dma_lli) + AXI_DESC_ALLIGN, + (void *)p_dma->dma_channel[p_transfer->channel_number].allign_malloc, + p_dma->dma_channel[p_transfer->channel_number].allign_phy); + + p_dma->dma_channel[p_transfer->channel_number].allign_malloc = AXI_DMA_NULL; + p_dma->dma_channel[p_transfer->channel_number].base_lli = AXI_DMA_NULL; + p_dma->dma_channel[p_transfer->channel_number].allign_phy = AXI_DMA_NULL; + p_dma->dma_channel[p_transfer->channel_number].base_lli_phy = AXI_DMA_NULL; + + p_dma->dma_channel[p_transfer->channel_number].desc_left_cnt = + p_dma->dma_channel[p_transfer->channel_number].desc_total_no; + p_dma->dma_channel[p_transfer->channel_number].free_index = 0; + p_dma->dma_channel[p_transfer->channel_number].used_index = 0; + + return AXI_DMA_RET_OK; +} + +void axi_dma_ctl_init(FH_UINT32 *low, FH_UINT32 *high) +{ + /*cache*/ + *low |= CH_CTL_L_AR_CACHE(3) | CH_CTL_L_AW_CACHE(0); + /*burst len*/ + *high |= CH_CTL_H_ARLEN_EN(1) | CH_CTL_H_ARLEN(0xf) | CH_CTL_H_AWLEN_EN(0) | CH_CTL_H_AWLEN(0xf); +} + +void axi_dma_cfg_init(FH_UINT32 *low, FH_UINT32 *high) +{ + /*out standing*/ + *high |= CH_CFG_H_DST_OSR_LMT(7) | CH_CFG_H_SRC_OSR_LMT(7); +} + +void handle_transfer(struct fh_axi_dma *p_dma, +struct dma_transfer *p_transfer) +{ + FH_UINT32 desc_size; + FH_UINT32 i; + FH_UINT32 lli_phy_add; + FH_UINT32 dst_inc_mode; + FH_UINT32 src_inc_mode; + FH_UINT32 ret_status; + FH_UINT32 cfg_low; + FH_UINT32 cfg_high; + struct dma_transfer *dma_trans_desc; + struct axi_dma_lli *p_lli_base; + FH_UINT32 lli_phy_base; + struct axi_dma_lli *p_lli = AXI_DMA_NULL; + struct dw_axi_dma *temp_dwc; + struct dma_transfer_desc *p_head_desc; + + FH_UINT32 isr = DWAXIDMAC_IRQ_DMA_TRF | DWAXIDMAC_IRQ_BLOCK_TRF | DWAXIDMAC_IRQ_SUSPENDED; + FH_UINT32 isr_sig = DWAXIDMAC_IRQ_DMA_TRF | DWAXIDMAC_IRQ_BLOCK_TRF; + + dma_trans_desc = p_transfer; + temp_dwc = &p_dma->dwc; + p_head_desc = p_transfer->p_desc; + desc_size = p_transfer->desc_size; + p_transfer->dma_controller->dma_channel[p_transfer->channel_number].active_trans = dma_trans_desc; + + dma_trans_desc->first_lli = get_desc(p_dma, p_transfer, desc_size); + + /* not enough mem.. */ + if (dma_trans_desc->first_lli == AXI_DMA_NULL) { + FH_AXI_DMA_PRINT("transfer error,reason: not enough mem..\n"); + AXI_DMA_ASSERT(dma_trans_desc->first_lli != AXI_DMA_NULL); + } + axi_dma_invalidate_desc((FH_UINT32)dma_trans_desc->first_lli, + desc_size * sizeof(struct axi_dma_lli)); + axi_dma_memset((void *)dma_trans_desc->first_lli, 0, + desc_size * sizeof(struct axi_dma_lli)); + p_lli = dma_trans_desc->first_lli; + lli_phy_base = p_dma->dma_channel[p_transfer->channel_number].base_lli_phy; + p_lli_base = p_dma->dma_channel[p_transfer->channel_number].base_lli; + + AXI_DMA_ASSERT(((FH_UINT32)p_lli & AXI_DESC_ALLIGN_BIT_MASK) == 0); + for (i = 0; i < desc_size; i++, p_head_desc++) { + /*parse each desc*/ + dst_inc_mode = (p_head_desc->dst_inc_mode == DW_DMA_SLAVE_INC) ? 0 : 1; + src_inc_mode = (p_head_desc->src_inc_mode == DW_DMA_SLAVE_INC) ? 0 : 1; + p_lli[i].sar_lo = p_head_desc->src_add; + p_lli[i].dar_lo = p_head_desc->dst_add; + p_lli[i].ctl_lo = + AXI_DMA_CTLL_DST_WIDTH(p_head_desc->dst_width) | + AXI_DMA_CTLL_SRC_WIDTH(p_head_desc->src_width) | + AXI_DMA_CTLL_DST_MSIZE(p_head_desc->dst_msize) | + AXI_DMA_CTLL_SRC_MSIZE(p_head_desc->src_msize) | + AXI_DMA_CTLL_DST_INC_MODE(dst_inc_mode) | + AXI_DMA_CTLL_SRC_INC_MODE(src_inc_mode); + p_lli[i].ctl_hi = CH_CTL_H_LLI_VALID; + if (p_dma->dma_channel[p_transfer->channel_number].open_flag == CYCLIC_TRANSFER) + p_lli[i].ctl_hi |= CH_CTL_H_IOC_BLKTFR; + + axi_dma_ctl_init(&p_lli[i].ctl_lo, &p_lli[i].ctl_hi); + + p_lli[i].block_ts_lo = p_head_desc->size - 1; + + if ((i + 1) < desc_size) { + lli_phy_add = vir_lli_to_phy_lli(p_lli_base, lli_phy_base, &p_lli[i + 1]); + p_lli[i].llp_lo = lli_phy_add; + } else { + if (p_dma->dma_channel[p_transfer->channel_number].open_flag == SINGLE_TRANSFER) + p_lli[i].ctl_hi |= CH_CTL_H_LLI_LAST; + else { + /*cyclic make a ring..*/ + lli_phy_add = vir_lli_to_phy_lli(p_lli_base, lli_phy_base, &p_lli[0]); + p_lli[i].llp_lo = lli_phy_add; + } + } + axi_dma_clean_desc((FH_UINT32)&p_lli[i], + sizeof(struct axi_dma_lli)); +#ifdef AXI_DMA_DEBUG + dump_lli(&p_lli[i], p_lli_base, lli_phy_base); +#endif + } + + dw_writel(temp_dwc, CHAN[dma_trans_desc->channel_number].CFG_LO, + 3 << CH_CFG_L_DST_MULTBLK_TYPE_POS | 3 << CH_CFG_L_SRC_MULTBLK_TYPE_POS); + /* set flow mode */ + dw_writel(temp_dwc, CHAN[dma_trans_desc->channel_number].CFG_HI, + AXI_DMA_CFGH_FC(dma_trans_desc->fc_mode)); + /* set base link add */ + lli_phy_add = vir_lli_to_phy_lli(p_lli_base, lli_phy_base, &p_lli[0]); + dw_writel(temp_dwc, CHAN[dma_trans_desc->channel_number].LLP, lli_phy_add); + /* clear isr */ + dw_writel(temp_dwc, CHAN[dma_trans_desc->channel_number].INTCLEAR_LO, 0xffffffff); + dw_writel(temp_dwc, CHAN[dma_trans_desc->channel_number].INTCLEAR_HI, 0xffffffff); + /* open isr */ + dw_writel(temp_dwc, CHAN[dma_trans_desc->channel_number].INTSTATUS_EN_LO, isr); + dw_writel(temp_dwc, CHAN[dma_trans_desc->channel_number].INTSIGNAL_LO, isr_sig); + AXI_DMA_ASSERT(dma_trans_desc->dst_hs <= DMA_SW_HANDSHAKING); + AXI_DMA_ASSERT(dma_trans_desc->src_hs <= DMA_SW_HANDSHAKING); + /* only hw handshaking need this.. */ + switch (dma_trans_desc->fc_mode) { + case DMA_M2M: + break; + case DMA_M2P: + ret_status = dw_readl(temp_dwc, CHAN[dma_trans_desc->channel_number].CFG_HI); + ret_status &= ~0x18; + ret_status |= dma_trans_desc->dst_per << 12; + dw_writel(temp_dwc, CHAN[dma_trans_desc->channel_number].CFG_HI, ret_status); + break; + case DMA_P2M: + ret_status = dw_readl(temp_dwc, CHAN[dma_trans_desc->channel_number].CFG_HI); + ret_status &= ~0x18; + ret_status |= dma_trans_desc->src_per << 7; + dw_writel(temp_dwc, CHAN[dma_trans_desc->channel_number].CFG_HI, ret_status); + break; + default: + break; + } + + /*rewrite cfg..*/ + cfg_low = dw_readl(temp_dwc, CHAN[dma_trans_desc->channel_number].CFG_LO); + cfg_high = dw_readl(temp_dwc, CHAN[dma_trans_desc->channel_number].CFG_HI); + axi_dma_cfg_init(&cfg_low, &cfg_high); + dw_writel(temp_dwc, CHAN[dma_trans_desc->channel_number].CFG_LO, cfg_low); + dw_writel(temp_dwc, CHAN[dma_trans_desc->channel_number].CFG_HI, cfg_high); + + dma_trans_desc->dma_controller + ->dma_channel[dma_trans_desc->channel_number] + .channel_status = CHANNEL_STATUS_BUSY; + + if (dma_trans_desc->prepare_callback) + dma_trans_desc->prepare_callback(dma_trans_desc->prepare_para); + +#ifdef AXI_DMA_DEBUG + dump_dma_common_reg(p_dma); + dump_channel_reg(p_dma, dma_trans_desc); +#endif + fhc_chan_able_set(p_dma, dma_trans_desc, 1); +} + +static void handle_single_transfer(struct fh_axi_dma *p_dma, +struct dma_transfer *p_transfer) +{ + FH_UINT32 ret_status; + axi_dma_list *p_controller_list; + FH_UINT32 max_trans_size; + struct dma_transfer *dma_trans_desc; + struct dma_transfer *_dma_trans_desc; + + AXI_DMA_ASSERT(p_transfer->channel_number < p_dma->dwc.channel_max_number); + AXI_DMA_ASSERT(p_transfer->dma_number < DMA_CONTROLLER_NUMBER); + /* when the dma transfer....the lock should be 0!!!! */ + /* or user may not request the channel... */ + + ret_status = p_dma->dma_channel[p_transfer->channel_number].channel_status; + if (ret_status == CHANNEL_STATUS_CLOSED) { + FH_AXI_DMA_PRINT("transfer error,reason: use a closed channel..\n"); + AXI_DMA_ASSERT(ret_status != CHANNEL_STATUS_CLOSED); + } + p_transfer->dma_controller = p_dma; + + axi_dma_list_init(&p_transfer->transfer_list); + max_trans_size = + p_transfer->dma_controller->dma_channel[p_transfer->channel_number] + .desc_trans_size; + if (p_transfer->period_len != 0) + max_trans_size = axi_dma_min(max_trans_size, p_transfer->period_len); + + /* add transfer to the controller's queue list */ + /* here should insert before and handle after....this could be a fifo... */ + axi_dma_list_insert_before(&p_dma->dma_channel[p_transfer->channel_number].queue, + &p_transfer->transfer_list); + + p_controller_list = &p_dma->dma_channel[p_transfer->channel_number].queue; + + /* here the driver could make a queue to cache the transfer and kick a */ + /* thread to handle the queue~~~ */ + /* but now,this is a easy version...,just handle the transfer now!!! */ + axi_dma_list_for_each_entry_safe(dma_trans_desc, _dma_trans_desc, + p_controller_list, transfer_list) { + handle_transfer(p_dma, dma_trans_desc); + } + +} + +FH_SINT32 axi_dma_driver_control(struct fh_axi_dma *dma, +FH_UINT32 cmd, struct dma_transfer *arg) +{ + struct fh_axi_dma *my_own = dma; + struct dw_axi_dma *temp_dwc = &my_own->dwc; + FH_ERR ret = AXI_DMA_RET_OK; + struct dma_transfer *p_dma_transfer = arg; + + switch (cmd) { + case AXI_DMA_CTRL_DMA_OPEN: + /* open the controller.. */ + handle_dma_open(my_own); + break; + case AXI_DMA_CTRL_DMA_CLOSE: + /* close the controller.. */ + handle_dma_close(my_own); + break; + case AXI_DMA_CTRL_DMA_REQUEST_CHANNEL: + /* request a channel for the user */ + ret = handle_request_channel(my_own, p_dma_transfer); + break; + case AXI_DMA_CTRL_DMA_RELEASE_CHANNEL: + /* release a channel */ + AXI_DMA_ASSERT(p_dma_transfer != AXI_DMA_NULL); + ret = handle_release_channel(my_own, p_dma_transfer); + break; + case AXI_DMA_CTRL_DMA_SINGLE_TRANSFER: + /* make a channel to transfer data. */ + AXI_DMA_ASSERT(p_dma_transfer != AXI_DMA_NULL); + /* check if the dma channel is open,or return error. */ + my_own->dma_channel[p_dma_transfer->channel_number].open_flag = + SINGLE_TRANSFER; + handle_single_transfer(my_own, p_dma_transfer); + /* then wait for the channel is complete.. */ + /* caution that::we should be in the "enter_critical()"when set the */ + /* dma to work. */ + break; + + case AXI_DMA_CTRL_DMA_CYCLIC_PREPARE: + AXI_DMA_ASSERT(p_dma_transfer != AXI_DMA_NULL); + my_own->dma_channel[p_dma_transfer->channel_number].open_flag = + CYCLIC_TRANSFER; + fh_axi_dma_cyclic_prep(my_own, p_dma_transfer); + break; + + case AXI_DMA_CTRL_DMA_CYCLIC_START: + fh_axi_dma_cyclic_start(p_dma_transfer); + break; + + case AXI_DMA_CTRL_DMA_CYCLIC_STOP: + fh_axi_dma_cyclic_stop(p_dma_transfer); + break; + + case AXI_DMA_CTRL_DMA_CYCLIC_FREE: + fh_axi_dma_cyclic_free(p_dma_transfer); + break; + case AXI_DMA_CTRL_DMA_PAUSE: + fh_axi_dma_cyclic_pause(p_dma_transfer); + break; + case AXI_DMA_CTRL_DMA_RESUME: + fh_axi_dma_cyclic_resume(p_dma_transfer); + break; + case AXI_DMA_CTRL_DMA_GET_DAR: + return dw_readl(temp_dwc, CHAN[p_dma_transfer->channel_number].DAR); + case AXI_DMA_CTRL_DMA_GET_SAR: + return dw_readl(temp_dwc, CHAN[p_dma_transfer->channel_number].SAR); + + default: + break; + } + + return ret; +} + +static void fh_isr_single_process(struct fh_axi_dma *my_own, +struct dma_transfer *p_transfer) +{ + if (p_transfer->isr_prepare_callback) + p_transfer->isr_prepare_callback(p_transfer->isr_prepare_para); + + if (p_transfer->complete_callback) + p_transfer->complete_callback(p_transfer->complete_para); + p_transfer->dma_controller + ->dma_channel[p_transfer->channel_number] + .channel_status = CHANNEL_STATUS_IDLE; + put_desc(my_own, p_transfer); + axi_dma_list_remove(&p_transfer->transfer_list); +} + +static void fh_isr_cyclic_process(struct fh_axi_dma *my_own, +struct dma_transfer *p_transfer) +{ + FH_UINT32 index; + struct dw_axi_dma *temp_dwc; + struct axi_dma_lli *p_lli; + + temp_dwc = &my_own->dwc; + p_lli = AXI_DMA_NULL; + + if (p_transfer->isr_prepare_callback) + p_transfer->isr_prepare_callback(p_transfer->isr_prepare_para); + + if (p_transfer->complete_callback) + p_transfer->complete_callback(p_transfer->complete_para); + p_lli = p_transfer->first_lli; + /*invaild desc mem to cache...*/ + axi_dma_invalidate_desc((uint32_t)p_lli, + sizeof(struct axi_dma_lli) * p_transfer->cyclic_periods); + for (index = 0; index < p_transfer->cyclic_periods; index++) { + if (!(p_lli[index].ctl_hi & CH_CTL_H_LLI_VALID)) + p_lli[index].ctl_hi |= CH_CTL_H_LLI_VALID; + } + /*flush cache..*/ + axi_dma_clean_desc((uint32_t)p_lli, + sizeof(struct axi_dma_lli) * p_transfer->cyclic_periods); + /*kick dma again.*/ + dw_writel(temp_dwc, CHAN[p_transfer->channel_number].BLK_TFR_RESU, 1); +} + +static void dma_channel_isr_enable(struct dw_axi_dma *dwc, int chan, int val) +{ + dw_writel(dwc, CHAN[chan].INTSIGNAL_LO, val); +} + +static int dma_channel_isr_disable(struct dw_axi_dma *dwc, int chan) +{ + int raw = dw_readl(dwc, CHAN[chan].INTSIGNAL_LO); + + dw_writel(dwc, CHAN[chan].INTSIGNAL_LO, 0); + return raw; +} + +void fh_axi_dma_isr_enable_set(struct fh_axi_dma *param, FH_UINT32 enable) +{ + struct fh_axi_dma *my_own = param; + struct dw_axi_dma *temp_dwc = &my_own->dwc; + FH_UINT32 i; + + /* enable channel int */ + for (i = 0; i < my_own->dwc.channel_max_number; i++) { + if (enable) { + int int_sig = my_own->dma_channel[i].int_sig; + + if (int_sig) { + dma_channel_isr_enable(temp_dwc, i, int_sig); + my_own->dma_channel[i].int_sig = 0; + } + } else { + int status = dw_readl(temp_dwc, CHAN[i].INTSTATUS_LO) + & (~DWAXIDMAC_IRQ_SUSPENDED); + if (!status) + continue; + /* backup channel int, then disable it */ + my_own->dma_channel[i].status = status; + my_own->dma_channel[i].int_sig = + dma_channel_isr_disable(temp_dwc, i); + /* clear int */ + dw_writel(temp_dwc, CHAN[i].INTCLEAR_LO, status); + if (status & DWAXIDMAC_IRQ_ALL_ERR) { + FH_AXI_DMA_PRINT("bug status is %x\n", status); + AXI_DMA_ASSERT(0); + } + } + } +} + +void fh_axi_dma_isr(struct fh_axi_dma *param) +{ + FH_UINT32 status; + FH_UINT32 i; + struct dw_axi_dma *temp_dwc; + struct fh_axi_dma *my_own = param; + temp_dwc = &my_own->dwc; + + for (i = 0; i < my_own->dwc.channel_max_number; i++) { + if (!my_own->dma_channel[i].status) + continue; + status = my_own->dma_channel[i].status; + if (my_own->dma_channel[i].open_flag == SINGLE_TRANSFER) { + if (status & DWAXIDMAC_IRQ_DMA_TRF) { + fh_isr_single_process(my_own, + my_own->dma_channel[i].active_trans); + } + } + if (my_own->dma_channel[i].open_flag == CYCLIC_TRANSFER) { + if (status & DWAXIDMAC_IRQ_BLOCK_TRF) { + fh_isr_cyclic_process(my_own, + my_own->dma_channel[i].active_trans); + } + } + my_own->dma_channel[i].status = 0; + } +} + +const char *channel_lock_name[AXI_DMA_MAX_NR_CHANNELS] = { + "channel_0_lock", "channel_1_lock", "channel_2_lock", "channel_3_lock", + "channel_4_lock", "channel_5_lock", "channel_6_lock", "channel_7_lock", +}; + +static void fh_axi_dma_cyclic_pause(struct dma_transfer *p) +{ + struct fh_axi_dma *my_own = p->dma_controller; + + fhc_chan_susp_set(my_own, p, 1); +} + +static void fh_axi_dma_cyclic_resume(struct dma_transfer *p) +{ + struct fh_axi_dma *my_own = p->dma_controller; + + fhc_chan_susp_set(my_own, p, 0); +} + +static void fh_axi_dma_cyclic_stop(struct dma_transfer *p) +{ + struct fh_axi_dma *my_own = p->dma_controller; + + fhc_chan_susp_set(my_own, p, 1); + fhc_chan_able_set(my_own, p, 0); +} + +static void fh_axi_dma_cyclic_start(struct dma_transfer *p) +{ + struct fh_axi_dma *my_own = p->dma_controller; + struct dw_axi_dma *dwc; + struct axi_dma_lli *p_lli = AXI_DMA_NULL; + + dwc = &my_own->dwc; + p_lli = p->first_lli; + + /* warnning!!!!must check if the add is 64Byte ally... */ + AXI_DMA_ASSERT(((FH_UINT32)p_lli & AXI_DESC_ALLIGN_BIT_MASK) == 0); + handle_transfer(my_own, p); +} + +static void fh_axi_dma_cyclic_prep(struct fh_axi_dma *fh_dma_p, +struct dma_transfer *p) +{ + /* bind the controller to the transfer */ + p->dma_controller = fh_dma_p; + /* bind active transfer */ + fh_dma_p->dma_channel[p->channel_number].active_trans = p; +} + +static void fh_axi_dma_cyclic_free(struct dma_transfer *p) +{ + struct fh_axi_dma *my_own = p->dma_controller; + + put_desc(my_own, p); +} + +FH_UINT32 cal_axi_dma_channel(void *regs) +{ +#ifdef DMA_FIXED_CHANNEL_NUM + return DMA_FIXED_CHANNEL_NUM; +#else + FH_UINT32 ret; + FH_UINT32 i; + FH_UINT32 time_out = 0xffffff; + + /*reset first..*/ + __dma_raw_writel(1, &(((struct dw_axi_dma_regs *)regs)->RESET)); + do { + ret = __dma_raw_readl(&(((struct dw_axi_dma_regs *)regs)->RESET)); + time_out--; + } while (ret && time_out); + + if (!time_out) + FH_AXI_DMA_PRINT("%s :: %d : time out..\n", __func__, __LINE__); + time_out = 0xffffff; + /*enable dma.*/ + __dma_raw_writel(1, &(((struct dw_axi_dma_regs *)regs)->CFG)); + + /*write channel.*/ + for (i = 0; i < AXI_DMA_MAX_NR_CHANNELS; i++) { + __dma_raw_writel(1 << i | 1 << (8+i), &(((struct dw_axi_dma_regs *)regs)->CHEN_LO)); + ret = __dma_raw_readl(&(((struct dw_axi_dma_regs *)regs)->CHEN_LO)); + if (ret < 1 << i) + break; + } + + /*reset again*/ + __dma_raw_writel(1, &(((struct dw_axi_dma_regs *)regs)->RESET)); + do { + ret = __dma_raw_readl(&(((struct dw_axi_dma_regs *)regs)->RESET)); + time_out--; + } while (ret && time_out); + + if (!time_out) + FH_AXI_DMA_PRINT("%s :: %d : time out..\n", __func__, __LINE__); + + return i; +#endif +} + + +struct axi_dma_ops *get_fh_axi_dma_ops(struct fh_axi_dma *p_axi_dma) +{ + AXI_DMA_ASSERT(p_axi_dma != AXI_DMA_NULL); + return &p_axi_dma->ops; +} + + +void get_desc_para(struct fh_axi_dma *dma, struct dma_transfer *p_transfer, +FH_UINT32 *desc_size, FH_UINT32 *base_phy_add, +FH_UINT32 *each_desc_size, FH_UINT32 *each_desc_cap) +{ + *desc_size = dma->dma_channel[p_transfer->channel_number] + .desc_total_no; + *base_phy_add = dma->dma_channel[p_transfer->channel_number] + .base_lli_phy; + *each_desc_size = sizeof(struct axi_dma_lli); + *each_desc_cap = dma->dma_channel[p_transfer->channel_number] + .desc_trans_size; +} + +struct fh_axi_dma *fh_axi_dma_probe(struct axi_dma_platform_data *priv_data) +{ + FH_UINT32 i; + struct fh_axi_dma *fh_dma_p; + struct axi_dma_platform_data *plat = priv_data; + + fh_dma_p = (struct fh_axi_dma *)axi_dma_malloc(sizeof(struct fh_axi_dma)); + if (!fh_dma_p) { + FH_AXI_DMA_PRINT("ERROR: %s, malloc failed\n", __func__); + return AXI_DMA_NULL; + } + axi_dma_memset(fh_dma_p, 0, sizeof(struct fh_axi_dma)); + axi_dma_scanf(fh_dma_p->dwc.name, "%s%d", + plat->name, (FH_SINT32)plat->id); + + fh_dma_p->dwc.regs = (void *)plat->base; + fh_dma_p->dwc.channel_max_number = + cal_axi_dma_channel(fh_dma_p->dwc.regs); + fh_dma_p->dwc.controller_status = CONTROLLER_STATUS_CLOSED; + fh_dma_p->dwc.id = plat->id; + fh_dma_p->kernel_pri = plat->kernel_pri; + fh_dma_p->adapt_pri = plat->adapt_pri; + fh_dma_p->ops.axi_dma_isr_process = fh_axi_dma_isr; + fh_dma_p->ops.axi_dma_control = axi_dma_driver_control; + fh_dma_p->ops.axi_dma_get_desc_para = get_desc_para; + fh_dma_p->ops.axi_dma_isr_enable_set = fh_axi_dma_isr_enable_set; + + /* channel set */ + for (i = 0; i < fh_dma_p->dwc.channel_max_number; i++) { + fh_dma_p->dma_channel[i].channel_status = CHANNEL_STATUS_CLOSED; + fh_dma_p->dma_channel[i].desc_total_no = DESC_MAX_SIZE; + fh_dma_p->dma_channel[i].int_sig = 0; + fh_dma_p->dma_channel[i].status = 0; + axi_dma_list_init(&(fh_dma_p->dma_channel[i].queue)); + fh_dma_p->dma_channel[i].desc_trans_size = + FH_CHANNEL_MAX_TRANSFER_SIZE; + axi_dma_lock_init(&fh_dma_p->dma_channel[i].channel_lock, + channel_lock_name[i]); + } + return fh_dma_p; +} diff --git a/drivers/dma/fh_dmac.c b/drivers/dma/fh_dmac.c new file mode 100644 index 00000000..7c985173 --- /dev/null +++ b/drivers/dma/fh_dmac.c @@ -0,0 +1,2101 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dmaengine.h" +#include +#include +#include +#include +#include +#include +#include + +#define FH_DMA_MAX_NR_CHANNELS 8 +#define FH_DMA_MAX_NR_REQUESTS 16 + +/* Platform-configurable bits in CFG_LO */ +#define FHC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */ +#define FHC_CFGL_LOCK_CH_BLOCK (1 << 12) +#define FHC_CFGL_LOCK_CH_XACT (2 << 12) +#define FHC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */ +#define FHC_CFGL_LOCK_BUS_BLOCK (1 << 14) +#define FHC_CFGL_LOCK_BUS_XACT (2 << 14) +#define FHC_CFGL_LOCK_CH (1 << 15) /* channel lockout */ +#define FHC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */ +#define FHC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */ +#define FHC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */ + +/* Bitfields in FH_PARAMS */ +#define FH_PARAMS_NR_CHAN 8 /* number of channels */ +#define FH_PARAMS_NR_MASTER 11 /* number of AHB masters */ +#define FH_PARAMS_DATA_WIDTH(n) (15 + 2 * (n)) +#define FH_PARAMS_DATA_WIDTH1 15 /* master 1 data width */ +#define FH_PARAMS_DATA_WIDTH2 17 /* master 2 data width */ +#define FH_PARAMS_DATA_WIDTH3 19 /* master 3 data width */ +#define FH_PARAMS_DATA_WIDTH4 21 /* master 4 data width */ +#define FH_PARAMS_EN 28 /* encoded parameters */ + +/* Bitfields in FHC_PARAMS */ +#define FHC_PARAMS_MBLK_EN 11 /* multi block transfer */ + +/* Bitfields in CTL_LO */ +#define FHC_CTLL_INT_EN (1 << 0) /* irqs enabled? */ +#define FHC_CTLL_DST_WIDTH(n) ((n)<<1) /* bytes per element */ +#define FHC_CTLL_SRC_WIDTH(n) ((n)<<4) +#define FHC_CTLL_DST_INC (0<<7) /* DAR update/not */ +#define FHC_CTLL_DST_DEC (1<<7) +#define FHC_CTLL_DST_FIX (2<<7) +#define FHC_CTLL_SRC_INC (0<<9) /* SAR update/not */ +#define FHC_CTLL_SRC_DEC (1<<9) +#define FHC_CTLL_SRC_FIX (2<<9) +#define FHC_CTLL_DST_MSIZE(n) ((n)<<11) /* burst, #elements */ +#define FHC_CTLL_SRC_MSIZE(n) ((n)<<14) +#define FHC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */ +#define FHC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */ +#define FHC_CTLL_FC(n) ((n) << 20) +#define FHC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */ +#define FHC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */ +#define FHC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */ +#define FHC_CTLL_FC_P2P (3 << 20) /* periph-to-periph */ +/* plus 4 transfer types for peripheral-as-flow-controller */ +#define FHC_CTLL_DMS(n) ((n)<<23) /* dst master select */ +#define FHC_CTLL_SMS(n) ((n)<<25) /* src master select */ +#define FHC_CTLL_LLP_D_EN (1 << 27) /* dest block chain */ +#define FHC_CTLL_LLP_S_EN (1 << 28) /* src block chain */ + +/* Bitfields in CTL_HI */ +#define FHC_CTLH_DONE 0x00001000 +#define FHC_CTLH_BLOCK_TS_MASK 0x00000fff +#define FHC_PROTCTL_MASK (7 << 2) +#define FHC_PROTCTL(n) ((n) << 2) +/* Bitfields in CFG_LO. Platform-configurable bits are in */ +#define FHC_CFGL_CH_PRIOR_MASK (0x7 << 5) /* priority mask */ +#define FHC_CFGL_CH_PRIOR(x) ((x) << 5) /* priority */ +#define FHC_CFGL_CH_SUSP (1 << 8) /* pause xfer */ +#define FHC_CFGL_FIFO_EMPTY (1 << 9) /* pause xfer */ +#define FHC_CFGL_HS_DST (1 << 10) /* handshake w/dst */ +#define FHC_CFGL_HS_SRC (1 << 11) /* handshake w/src */ +#define FHC_CFGL_MAX_BURST(x) ((x) << 20) +#define FHC_CFGL_RELOAD_SAR (1 << 30) +#define FHC_CFGL_RELOAD_DAR (1 << 31) + +/* Bitfields in CFG_HI. Platform-configurable bits are in */ +#define FHC_CFGH_DS_UPD_EN (1 << 5) +#define FHC_CFGH_SS_UPD_EN (1 << 6) + +/* Bitfields in SGR */ +#define FHC_SGR_SGI(x) ((x) << 0) +#define FHC_SGR_SGC(x) ((x) << 20) + +/* Bitfields in DSR */ +#define FHC_DSR_DSI(x) ((x) << 0) +#define FHC_DSR_DSC(x) ((x) << 20) + +/* Bitfields in CFG */ +#define FH_CFG_DMA_EN (1 << 0) + +#define FH_REGLEN 0x400 +#define PROTCTL_ENABLE 0x55 +#define MASTER_SEL_ENABLE 0x55 + +/* + * Redefine this macro to handle differences between 32- and 64-bit + * addressing, big vs. little endian, etc. + */ +#define FH_REG(name) u32 name; u32 __pad_##name + +/* Hardware register definitions. */ +struct fh_dma_chan_regs { + FH_REG(SAR); /* Source Address Register */ + FH_REG(DAR); /* Destination Address Register */ + FH_REG(LLP); /* Linked List Pointer */ + u32 CTL_LO; /* Control Register Low */ + u32 CTL_HI; /* Control Register High */ + FH_REG(SSTAT); + FH_REG(DSTAT); + FH_REG(SSTATAR); + FH_REG(DSTATAR); + u32 CFG_LO; /* Configuration Register Low */ + u32 CFG_HI; /* Configuration Register High */ + FH_REG(SGR); + FH_REG(DSR); +}; + +struct fh_dma_irq_regs { + FH_REG(XFER); + FH_REG(BLOCK); + FH_REG(SRC_TRAN); + FH_REG(DST_TRAN); + FH_REG(ERROR); +}; + +struct fh_dma_regs { + /* per-channel registers */ + struct fh_dma_chan_regs CHAN[FH_DMA_MAX_NR_CHANNELS]; + + /* irq handling */ + struct fh_dma_irq_regs RAW; /* r */ + struct fh_dma_irq_regs STATUS; /* r (raw & mask) */ + struct fh_dma_irq_regs MASK; /* rw (set = irq enabled) */ + struct fh_dma_irq_regs CLEAR; /* w (ack, affects "raw") */ + + FH_REG(STATUS_INT); /* r */ + + /* software handshaking */ + FH_REG(REQ_SRC); + FH_REG(REQ_DST); + FH_REG(SGL_REQ_SRC); + FH_REG(SGL_REQ_DST); + FH_REG(LAST_SRC); + FH_REG(LAST_DST); + + /* miscellaneous */ + FH_REG(CFG); + FH_REG(CH_EN); + FH_REG(ID); + FH_REG(TEST); + + /* reserved */ + FH_REG(__reserved0); + FH_REG(__reserved1); + + /* optional encoded params, 0x3c8..0x3f7 */ + u32 __reserved; + + /* per-channel configuration registers */ + u32 FHC_PARAMS[FH_DMA_MAX_NR_CHANNELS]; + u32 MULTI_BLK_TYPE; + u32 MAX_BLK_SIZE; + + /* top-level parameters */ + u32 FH_PARAMS; +}; + +/* To access the registers in early stage of probe */ +#define dma_read_byaddr(addr, name) \ + dma_readl_native((addr) + offsetof(struct fh_dma_regs, name)) + +#define channel_readl(fhc, name) \ + dma_readl_native(&(__fhc_regs(fhc)->name)) +#define channel_writel(fhc, name, val) \ + dma_writel_native((val), &(__fhc_regs(fhc)->name)) + +#define dma_readl(dw, name) \ + dma_readl_native(&(__fh_regs(dw)->name)) +#define dma_writel(dw, name, val) \ + dma_writel_native((val), &(__fh_regs(dw)->name)) + +#define channel_set_bit(dw, reg, mask) \ + dma_writel(dw, reg, ((mask) << 8) | (mask)) +#define channel_clear_bit(dw, reg, mask) \ + dma_writel(dw, reg, ((mask) << 8) | 0) + +#define dma_readl_native readl +#define dma_writel_native writel + +static inline struct fh_dma_chan_regs __iomem * +__fhc_regs(struct fh_dma_chan *fhc) +{ + return fhc->ch_regs; +} +static inline struct fh_dma_regs __iomem *__fh_regs(struct fh_dma *dw) +{ + return dw->regs; +} + +static inline unsigned int fhc_get_dms(struct fh_dma_slave *slave) +{ +#ifdef CONFIG_ARCH_FHYG + return slave ? slave->dst_master : 0; +#else + return slave ? slave->dst_master : 1; +#endif +} + +static inline unsigned int fhc_get_sms(struct fh_dma_slave *slave) +{ +#ifdef CONFIG_ARCH_FHYG + return slave ? slave->src_master : 0; +#else + return slave ? slave->src_master : 1; +#endif +} + +static inline void fhc_set_masters(struct fh_dma_chan *fhc) +{ + struct fh_dma *fhd = to_fh_dma(fhc->chan.device); + struct fh_dma_slave *dms = fhc->chan.private; + unsigned char mmax = fhd->nr_masters - 1; + + if (fhc->request_line == ~0) { + fhc->src_master = min_t(unsigned char, mmax, fhc_get_sms(dms)); + fhc->dst_master = min_t(unsigned char, mmax, fhc_get_dms(dms)); + } +} + +#define FHC_DEFAULT_CTLLO(_chan) ({ \ + struct fh_dma_chan *_fhc = to_fh_dma_chan(_chan); \ + struct dma_slave_config *_sconfig = &_fhc->dma_sconfig; \ + bool _is_slave = is_slave_direction(_fhc->direction); \ + u8 _smsize = _is_slave ? _sconfig->src_maxburst : \ + FH_DMA_MSIZE_16; \ + u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \ + FH_DMA_MSIZE_16; \ + \ + (FHC_CTLL_DST_MSIZE(_dmsize) \ + | FHC_CTLL_SRC_MSIZE(_smsize) \ + | FHC_CTLL_LLP_D_EN \ + | FHC_CTLL_LLP_S_EN \ + | FHC_CTLL_DMS(_fhc->dst_master) \ + | FHC_CTLL_SMS(_fhc->src_master)); \ + }) + +#define FHC_DEFAULT_CTLLO_OLD(private) ({ \ + struct fh_dma_slave *__slave = (private); \ + int dms = __slave ? __slave->dst_master : 0; \ + int sms = __slave ? __slave->src_master : 0; \ + u8 smsize = __slave ? __slave->src_msize : FH_DMA_MSIZE_16; \ + u8 dmsize = __slave ? __slave->dst_msize : FH_DMA_MSIZE_16; \ + \ + (FHC_CTLL_DST_MSIZE(dmsize) \ + | FHC_CTLL_SRC_MSIZE(smsize) \ + | FHC_CTLL_LLP_D_EN \ + | FHC_CTLL_LLP_S_EN \ + | FHC_CTLL_DMS(dms) \ + | FHC_CTLL_SMS(sms)); \ + }) + +/* + * Number of descriptors to allocate for each channel. This should be + * made configurable somehow; preferably, the clients (at least the + * ones using slave transfers) should be able to give us a hint. + */ +#ifdef CONFIG_CHANNEL_ALLOC_MEM_CLASSICS +#define NR_DESCS_PER_CHANNEL CONFIG_CHANNEL_ALLOC_DESC_NUM +#else +#define NR_DESCS_PER_CHANNEL 4096 +#endif + + +/*----------------------------------------------------------------------*/ + +static struct device *chan2dev(struct dma_chan *chan) +{ + return &chan->dev->device; +} +static struct device *chan2parent(struct dma_chan *chan) +{ + return chan->dev->device.parent; +} + +static struct fh_desc *fhc_first_active(struct fh_dma_chan *fhc) +{ + return to_fh_desc(fhc->active_list.next); +} + +static struct fh_desc *fhc_desc_get(struct fh_dma_chan *fhc) +{ + struct fh_desc *desc, *_desc; + struct fh_desc *ret = NULL; + unsigned int i = 0; + unsigned long flags; + + spin_lock_irqsave(&fhc->lock, flags); + list_for_each_entry_safe(desc, _desc, &fhc->free_list, desc_node) { + i++; + if (async_tx_test_ack(&desc->txd)) { + list_del(&desc->desc_node); + ret = desc; + break; + } + dev_dbg(chan2dev(&fhc->chan), "desc %p not ACKed\n", desc); + } + spin_unlock_irqrestore(&fhc->lock, flags); + + dev_vdbg(chan2dev(&fhc->chan), "scanned %u descriptors on freelist\n", i); + + return ret; +} + +/* + * Move a descriptor, including any children, to the free list. + * `desc' must not be on any lists. + */ +static void fhc_desc_put(struct fh_dma_chan *fhc, struct fh_desc *desc) +{ + unsigned long flags; + + if (desc) { + struct fh_desc *child; + + spin_lock_irqsave(&fhc->lock, flags); + list_for_each_entry(child, &desc->tx_list, desc_node) + dev_vdbg(chan2dev(&fhc->chan), + "moving child desc %p to freelist\n", + child); + list_splice_init(&desc->tx_list, &fhc->free_list); + dev_vdbg(chan2dev(&fhc->chan), "moving desc %p to freelist\n", desc); + list_add(&desc->desc_node, &fhc->free_list); + spin_unlock_irqrestore(&fhc->lock, flags); + } +} + +static void fhc_initialize(struct fh_dma_chan *fhc) +{ + struct fh_dma *fhd = to_fh_dma(fhc->chan.device); + struct fh_dma_slave *dms = fhc->chan.private; + u32 cfghi = FHC_CFGH_FIFO_MODE; + u32 cfglo = FHC_CFGL_CH_PRIOR(fhc->priority); + struct fh_dma_extra *ext_para = &fhc->ext_para; + + if (fhc->initialized == true) + return; + + if (dms) { + cfghi = dms->cfg_hi; + cfglo |= dms->cfg_lo & ~FHC_CFGL_CH_PRIOR_MASK; + } else { + if (fhc->direction == DMA_MEM_TO_DEV) { + cfghi = FHC_CFGH_DST_PER(fhc->request_line); + if (ext_para->protctl_flag == PROTCTL_ENABLE) { + cfghi &= ~FHC_PROTCTL_MASK; + cfghi |= FHC_PROTCTL(ext_para->protctl_data); + } + } else if (fhc->direction == DMA_DEV_TO_MEM) { + cfghi = FHC_CFGH_SRC_PER(fhc->request_line); + if (ext_para->protctl_flag == PROTCTL_ENABLE) { + cfghi &= ~FHC_PROTCTL_MASK; + cfghi |= FHC_PROTCTL(ext_para->protctl_data); + } + } else if (fhc->direction == DMA_MEM_TO_MEM) { + cfghi &= ~FHC_PROTCTL_MASK; + cfghi |= FHC_PROTCTL(2); + } + } + channel_writel(fhc, CFG_LO, cfglo); + channel_writel(fhc, CFG_HI, cfghi); + + /* Enable interrupts */ + channel_set_bit(fhd, MASK.XFER, fhc->mask); + channel_set_bit(fhd, MASK.BLOCK, fhc->mask); + channel_set_bit(fhd, MASK.ERROR, fhc->mask); + + fhc->initialized = true; +} + +/*----------------------------------------------------------------------*/ + +static inline unsigned int fhc_fast_fls(unsigned long long v) +{ + /* + * We can be a lot more clever here, but this should take care + * of the most common optimization. + */ + if (!(v & 7)) + return 3; + else if (!(v & 3)) + return 2; + else if (!(v & 1)) + return 1; + return 0; +} + +static inline void fhc_dump_chan_regs(struct fh_dma_chan *fhc) +{ + dev_err(chan2dev(&fhc->chan), + " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", + channel_readl(fhc, SAR), + channel_readl(fhc, DAR), + channel_readl(fhc, LLP), + channel_readl(fhc, CTL_HI), + channel_readl(fhc, CTL_LO)); +} + +static inline void fhc_chan_disable(struct fh_dma *fhd, struct fh_dma_chan *fhc) +{ + channel_clear_bit(fhd, CH_EN, fhc->mask); + while (dma_readl(fhd, CH_EN) & fhc->mask) + cpu_relax(); +} + +/*----------------------------------------------------------------------*/ + +/* Perform single block transfer */ +static inline void fhc_do_single_block(struct fh_dma_chan *fhc, + struct fh_desc *desc) +{ + struct fh_dma *fhd = to_fh_dma(fhc->chan.device); + u32 ctllo; + + /* Software emulation of LLP mode relies on interrupts to continue + * multi block transfer. */ + ctllo = desc->lli.ctllo | FHC_CTLL_INT_EN; + + channel_writel(fhc, SAR, desc->lli.sar); + channel_writel(fhc, DAR, desc->lli.dar); + channel_writel(fhc, CTL_LO, ctllo); + channel_writel(fhc, CTL_HI, desc->lli.ctlhi); + channel_set_bit(fhd, CH_EN, fhc->mask); + + /* Move pointer to next descriptor */ + fhc->tx_node_active = fhc->tx_node_active->next; +} + +/* Called with fhc->lock held and bh disabled */ +static void fhc_dostart(struct fh_dma_chan *fhc, struct fh_desc *first) +{ + struct fh_dma *fhd = to_fh_dma(fhc->chan.device); + unsigned long was_soft_llp; + + /* ASSERT: channel is idle */ + if (dma_readl(fhd, CH_EN) & fhc->mask) { + dev_err(chan2dev(&fhc->chan), + "BUG: Attempted to start non-idle channel\n"); + fhc_dump_chan_regs(fhc); + + /* The tasklet will hopefully advance the queue... */ + return; + } + + if (fhc->nollp) { + was_soft_llp = test_and_set_bit(FH_DMA_IS_SOFT_LLP, + &fhc->flags); + if (was_soft_llp) { + dev_err(chan2dev(&fhc->chan), + "BUG: Attempted to start new LLP transfer " + "inside ongoing one\n"); + return; + } + + fhc_initialize(fhc); + + fhc->residue = first->total_len; + fhc->tx_node_active = &first->tx_list; + + /* Submit first block */ + fhc_do_single_block(fhc, first); + + return; + } + + fhc_initialize(fhc); + + channel_writel(fhc, LLP, first->txd.phys); + channel_writel(fhc, CTL_LO, + FHC_CTLL_LLP_D_EN | FHC_CTLL_LLP_S_EN); + channel_writel(fhc, CTL_HI, 0); + channel_set_bit(fhd, CH_EN, fhc->mask); +} + +/*----------------------------------------------------------------------*/ + +static void +fhc_descriptor_complete(struct fh_dma_chan *fhc, struct fh_desc *desc, + bool callback_required) +{ + dma_async_tx_callback callback = NULL; + void *param = NULL; + struct dma_async_tx_descriptor *txd = &desc->txd; + struct fh_desc *child; + unsigned long flags; + + dev_vdbg(chan2dev(&fhc->chan), "descriptor %u complete\n", txd->cookie); + + spin_lock_irqsave(&fhc->lock, flags); + dma_cookie_complete(txd); + if (callback_required) { + callback = txd->callback; + param = txd->callback_param; + } + + /* async_tx_ack */ + list_for_each_entry(child, &desc->tx_list, desc_node) + async_tx_ack(&child->txd); + async_tx_ack(&desc->txd); + + list_splice_init(&desc->tx_list, &fhc->free_list); + list_move(&desc->desc_node, &fhc->free_list); + + dma_descriptor_unmap(txd); + + spin_unlock_irqrestore(&fhc->lock, flags); + + if (callback) + callback(param); +} + +static void fhc_complete_all(struct fh_dma *fhd, struct fh_dma_chan *fhc) +{ + struct fh_desc *desc, *_desc; + LIST_HEAD(list); + unsigned long flags; + + spin_lock_irqsave(&fhc->lock, flags); + if (dma_readl(fhd, CH_EN) & fhc->mask) { + dev_err(chan2dev(&fhc->chan), + "BUG: XFER bit set, but channel not idle!\n"); + + /* Try to continue after resetting the channel... */ + fhc_chan_disable(fhd, fhc); + } + + /* + * Submit queued descriptors ASAP, i.e. before we go through + * the completed ones. + */ + list_splice_init(&fhc->active_list, &list); + if (!list_empty(&fhc->queue)) { + list_move(fhc->queue.next, &fhc->active_list); + fhc_dostart(fhc, fhc_first_active(fhc)); + } + + spin_unlock_irqrestore(&fhc->lock, flags); + + list_for_each_entry_safe(desc, _desc, &list, desc_node) + fhc_descriptor_complete(fhc, desc, true); +} + +/* Returns how many bytes were already received from source */ +static inline u32 fhc_get_sent(struct fh_dma_chan *fhc) +{ + u32 ctlhi = channel_readl(fhc, CTL_HI); + u32 ctllo = channel_readl(fhc, CTL_LO); + + return (ctlhi & FHC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7)); +} + +static void fhc_scan_descriptors(struct fh_dma *fhd, struct fh_dma_chan *fhc) +{ + dma_addr_t llp; + struct fh_desc *desc, *_desc; + struct fh_desc *child; + u32 status_xfer; + unsigned long flags; + + spin_lock_irqsave(&fhc->lock, flags); + /* + * Clear block interrupt flag before scanning so that we don't + * miss any, and read LLP before RAW_XFER to ensure it is + * valid if we decide to scan the list. + */ + dma_writel(fhd, CLEAR.BLOCK, fhc->mask); + llp = channel_readl(fhc, LLP); + status_xfer = dma_readl(fhd, RAW.XFER); + + if (status_xfer & fhc->mask) { + /* Everything we've submitted is done */ + dma_writel(fhd, CLEAR.XFER, fhc->mask); + if (test_bit(FH_DMA_IS_SOFT_LLP, &fhc->flags)) { + struct list_head *head, *active = fhc->tx_node_active; + + /* + * We are inside first active descriptor. + * Otherwise something is really wrong. + */ + desc = fhc_first_active(fhc); + + head = &desc->tx_list; + if (active != head) { + /* Update desc to reflect last sent one */ + if (active != head->next) + desc = to_fh_desc(active->prev); + + fhc->residue -= desc->len; + + child = to_fh_desc(active); + + /* Submit next block */ + fhc_do_single_block(fhc, child); + + spin_unlock_irqrestore(&fhc->lock, flags); + return; + } + + /* We are done here */ + clear_bit(FH_DMA_IS_SOFT_LLP, &fhc->flags); + } + fhc->residue = 0; + + spin_unlock_irqrestore(&fhc->lock, flags); + + fhc_complete_all(fhd, fhc); + return; + } + + if (list_empty(&fhc->active_list)) { + fhc->residue = 0; + spin_unlock_irqrestore(&fhc->lock, flags); + return; + } + + if (test_bit(FH_DMA_IS_SOFT_LLP, &fhc->flags)) { + dev_vdbg(chan2dev(&fhc->chan), "%s: soft LLP mode\n", __func__); + spin_unlock_irqrestore(&fhc->lock, flags); + return; + } + + dev_vdbg(chan2dev(&fhc->chan), "%s: llp=0x%llx\n", __func__, + (unsigned long long)llp); + + list_for_each_entry_safe(desc, _desc, &fhc->active_list, desc_node) { + /* Initial residue value */ + fhc->residue = desc->total_len; + + /* Check first descriptors addr */ + if (desc->txd.phys == llp) { + spin_unlock_irqrestore(&fhc->lock, flags); + return; + } + + /* Check first descriptors llp */ + if (desc->lli.llp == llp) { + /* This one is currently in progress */ + fhc->residue -= fhc_get_sent(fhc); + spin_unlock_irqrestore(&fhc->lock, flags); + return; + } + + fhc->residue -= desc->len; + list_for_each_entry(child, &desc->tx_list, desc_node) { + if (child->lli.llp == llp) { + /* Currently in progress */ + fhc->residue -= fhc_get_sent(fhc); + spin_unlock_irqrestore(&fhc->lock, flags); + return; + } + fhc->residue -= child->len; + } + + /* + * No descriptors so far seem to be in progress, i.e. + * this one must be done. + */ + spin_unlock_irqrestore(&fhc->lock, flags); + fhc_descriptor_complete(fhc, desc, true); + spin_lock_irqsave(&fhc->lock, flags); + } + + dev_err(chan2dev(&fhc->chan), + "BUG: All descriptors done, but channel not idle!\n"); + + /* Try to continue after resetting the channel... */ + fhc_chan_disable(fhd, fhc); + + if (!list_empty(&fhc->queue)) { + list_move(fhc->queue.next, &fhc->active_list); + fhc_dostart(fhc, fhc_first_active(fhc)); + } + spin_unlock_irqrestore(&fhc->lock, flags); +} + +static inline void fhc_dump_lli(struct fh_dma_chan *fhc, struct fh_lli *lli) +{ + dev_crit(chan2dev(&fhc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", + lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo); + +} + +static void fhc_handle_error(struct fh_dma *fhd, struct fh_dma_chan *fhc) +{ + struct fh_desc *bad_desc; + struct fh_desc *child; + unsigned long flags; + + fhc_scan_descriptors(fhd, fhc); + + spin_lock_irqsave(&fhc->lock, flags); + + /* + * The descriptor currently at the head of the active list is + * borked. Since we don't have any way to report errors, we'll + * just have to scream loudly and try to carry on. + */ + bad_desc = fhc_first_active(fhc); + list_del_init(&bad_desc->desc_node); + list_move(fhc->queue.next, fhc->active_list.prev); + + /* Clear the error flag and try to restart the controller */ + dma_writel(fhd, CLEAR.ERROR, fhc->mask); + if (!list_empty(&fhc->active_list)) + fhc_dostart(fhc, fhc_first_active(fhc)); + + /* + * WARN may seem harsh, but since this only happens + * when someone submits a bad physical address in a + * descriptor, we should consider ourselves lucky that the + * controller flagged an error instead of scribbling over + * random memory locations. + */ + dev_WARN(chan2dev(&fhc->chan), "Bad descriptor submitted for DMA!\n" + " cookie: %d\n", bad_desc->txd.cookie); + fhc_dump_lli(fhc, &bad_desc->lli); + list_for_each_entry(child, &bad_desc->tx_list, desc_node) + fhc_dump_lli(fhc, &child->lli); + + spin_unlock_irqrestore(&fhc->lock, flags); + + /* Pretend the descriptor completed successfully */ + fhc_descriptor_complete(fhc, bad_desc, true); +} + +/* --------------------- Cyclic DMA API extensions -------------------- */ + +inline dma_addr_t fh_dma_get_src_addr(struct dma_chan *chan) +{ + struct fh_dma_chan *fhc = to_fh_dma_chan(chan); + + return channel_readl(fhc, SAR); +} +EXPORT_SYMBOL(fh_dma_get_src_addr); + +inline dma_addr_t fh_dma_get_dst_addr(struct dma_chan *chan) +{ + struct fh_dma_chan *fhc = to_fh_dma_chan(chan); + + return channel_readl(fhc, DAR); +} +EXPORT_SYMBOL(fh_dma_get_dst_addr); + +/* Called with fhc->lock held and all DMAC interrupts disabled */ +static void fhc_handle_cyclic(struct fh_dma *fhd, struct fh_dma_chan *fhc, + u32 status_err, u32 status_xfer, u32 status_block) +{ + unsigned long flags; + + if (status_block & fhc->mask) { + void (*callback) (void *param); + void *callback_param; + + dev_vdbg(chan2dev(&fhc->chan), "new cyclic period llp 0x%08x\n", + channel_readl(fhc, LLP)); + dma_writel(fhd, CLEAR.BLOCK, fhc->mask); + + callback = fhc->cdesc->period_callback; + callback_param = fhc->cdesc->period_callback_param; + + if (callback) + callback(callback_param); + } + + /* + * Error and transfer complete are highly unlikely, and will most + * likely be due to a configuration error by the user. + */ + if (unlikely(status_err & fhc->mask) || + unlikely(status_xfer & fhc->mask)) { + int i; + + dev_err(chan2dev(&fhc->chan), "cyclic DMA unexpected %s " + "interrupt, stopping DMA transfer\n", + status_xfer ? "xfer" : "error"); + + spin_lock_irqsave(&fhc->lock, flags); + + fhc_dump_chan_regs(fhc); + + fhc_chan_disable(fhd, fhc); + + /* Make sure DMA does not restart by loading a new list */ + channel_writel(fhc, LLP, 0); + channel_writel(fhc, CTL_LO, 0); + channel_writel(fhc, CTL_HI, 0); + + dma_writel(fhd, CLEAR.ERROR, fhc->mask); + dma_writel(fhd, CLEAR.XFER, fhc->mask); + dma_writel(fhd, CLEAR.BLOCK, fhc->mask); + + for (i = 0; i < fhc->cdesc->periods; i++) + fhc_dump_lli(fhc, &fhc->cdesc->desc[i]->lli); + + spin_unlock_irqrestore(&fhc->lock, flags); + } +} + +/* ------------------------------------------------------------------------- */ + +static void fh_dma_tasklet(unsigned long data) +{ + struct fh_dma *fhd = (struct fh_dma *)data; + struct fh_dma_chan *fhc; + u32 status_xfer; + u32 status_err; + u32 status_block; + int i; + + status_xfer = dma_readl(fhd, RAW.XFER); + status_block = dma_readl(fhd, RAW.BLOCK); + status_err = dma_readl(fhd, RAW.ERROR); + + dev_vdbg(fhd->dma.dev, "%s: status_err=%x\n", __func__, status_err); + + for (i = 0; i < fhd->dma.chancnt; i++) { + fhc = &fhd->chan[i]; + if (test_bit(FH_DMA_IS_CYCLIC, &fhc->flags)) + fhc_handle_cyclic(fhd, fhc, status_err, + status_xfer, status_block); + else if (status_err & (1 << i)) + fhc_handle_error(fhd, fhc); + else if (status_xfer & (1 << i)) + fhc_scan_descriptors(fhd, fhc); + } + + /* + * Re-enable interrupts. + */ + channel_set_bit(fhd, MASK.XFER, fhd->all_chan_mask); + channel_set_bit(fhd, MASK.BLOCK, fhd->all_chan_mask); + channel_set_bit(fhd, MASK.ERROR, fhd->all_chan_mask); +} + +static irqreturn_t fh_dma_interrupt(int irq, void *dev_id) +{ + struct fh_dma *fhd = dev_id; + u32 status; + + dev_vdbg(fhd->dma.dev, "%s: status=0x%x\n", __func__, + dma_readl(fhd, STATUS_INT)); + + /* + * Just disable the interrupts. We'll turn them back on in the + * softirq handler. + */ + channel_clear_bit(fhd, MASK.XFER, fhd->all_chan_mask); + channel_clear_bit(fhd, MASK.BLOCK, fhd->all_chan_mask); + channel_clear_bit(fhd, MASK.ERROR, fhd->all_chan_mask); + + status = dma_readl(fhd, STATUS_INT); + if (status) { + dev_err(fhd->dma.dev, + "BUG: Unexpected interrupts pending: 0x%x\n", + status); + + /* Try to recover */ + channel_clear_bit(fhd, MASK.XFER, (1 << 8) - 1); + channel_clear_bit(fhd, MASK.BLOCK, (1 << 8) - 1); + channel_clear_bit(fhd, MASK.SRC_TRAN, (1 << 8) - 1); + channel_clear_bit(fhd, MASK.DST_TRAN, (1 << 8) - 1); + channel_clear_bit(fhd, MASK.ERROR, (1 << 8) - 1); + } + + tasklet_schedule(&fhd->tasklet); + + return IRQ_HANDLED; +} + +/*----------------------------------------------------------------------*/ + +static dma_cookie_t fhc_tx_submit(struct dma_async_tx_descriptor *tx) +{ + struct fh_desc *desc = txd_to_fh_desc(tx); + struct fh_dma_chan *fhc = to_fh_dma_chan(tx->chan); + dma_cookie_t cookie; + unsigned long flags; + + spin_lock_irqsave(&fhc->lock, flags); + cookie = dma_cookie_assign(tx); + + /* + * REVISIT: We should attempt to chain as many descriptors as + * possible, perhaps even appending to those already submitted + * for DMA. But this is hard to do in a race-free manner. + */ + if (list_empty(&fhc->active_list)) { + dev_vdbg(chan2dev(tx->chan), "%s: started %u\n", __func__, + desc->txd.cookie); + list_add_tail(&desc->desc_node, &fhc->active_list); + fhc_dostart(fhc, fhc_first_active(fhc)); + } else { + dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__, + desc->txd.cookie); + + list_add_tail(&desc->desc_node, &fhc->queue); + } + + spin_unlock_irqrestore(&fhc->lock, flags); + + return cookie; +} + +static struct dma_async_tx_descriptor * +fhc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, + size_t len, unsigned long flags) +{ + struct fh_dma_chan *fhc = to_fh_dma_chan(chan); + struct fh_dma *fhd = to_fh_dma(chan->device); + struct fh_desc *desc; + struct fh_desc *first; + struct fh_desc *prev; + size_t xfer_count; + size_t offset; + unsigned int src_width; + unsigned int dst_width; + unsigned int data_width; + u32 ctllo; + + dev_vdbg(chan2dev(chan), + "%s: d0x%llx s0x%llx l0x%zx f0x%lx\n", __func__, + (unsigned long long)dest, (unsigned long long)src, + len, flags); + + if (unlikely(!len)) { + dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); + return NULL; + } + + fhc->direction = DMA_MEM_TO_MEM; + + data_width = min_t(unsigned int, fhd->data_width[fhc->src_master], + fhd->data_width[fhc->dst_master]); + + src_width = dst_width = min_t(unsigned int, data_width, + fhc_fast_fls(src | dest | len)); + + ctllo = FHC_DEFAULT_CTLLO(chan) + | FHC_CTLL_DST_WIDTH(dst_width) + | FHC_CTLL_SRC_WIDTH(src_width) + | FHC_CTLL_DST_INC + | FHC_CTLL_SRC_INC + | FHC_CTLL_FC_M2M; + prev = first = NULL; + + for (offset = 0; offset < len; offset += xfer_count << src_width) { + xfer_count = min_t(size_t, (len - offset) >> src_width, + fhc->block_size); + + desc = fhc_desc_get(fhc); + if (!desc) + goto err_desc_get; + + desc->lli.sar = src + offset; + desc->lli.dar = dest + offset; + desc->lli.ctllo = ctllo; + desc->lli.ctlhi = xfer_count; + desc->len = xfer_count << src_width; + + if (!first) { + first = desc; + } else { + prev->lli.llp = desc->txd.phys; + list_add_tail(&desc->desc_node, + &first->tx_list); + } + prev = desc; + } + + if (flags & DMA_PREP_INTERRUPT) + /* Trigger interrupt after last block */ + prev->lli.ctllo |= FHC_CTLL_INT_EN; + + prev->lli.llp = 0; + first->txd.flags = flags; + first->total_len = len; + + return &first->txd; + +err_desc_get: + fhc_desc_put(fhc, first); + return NULL; +} + +static struct dma_async_tx_descriptor * +fhc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, + unsigned int sg_len, enum dma_transfer_direction direction, + unsigned long flags, void *context) +{ + struct fh_dma_chan *fhc = to_fh_dma_chan(chan); + /*struct fh_dma *fhd = to_fh_dma(chan->device);*/ + struct dma_slave_config *sconfig = &fhc->dma_sconfig; + struct fh_desc *prev; + struct fh_desc *first; + u32 ctllo; + dma_addr_t reg; + unsigned int reg_width; + unsigned int mem_width; + unsigned int data_width; + unsigned int i; + struct scatterlist *sg; + size_t total_len = 0; + struct fh_dma_extra *ext_para = (struct fh_dma_extra *)context; + dev_vdbg(chan2dev(chan), "%s\n", __func__); + + if (unlikely(!is_slave_direction(direction) || !sg_len)) + return NULL; + + fhc->direction = direction; + + prev = first = NULL; + if (ext_para) + memcpy(&fhc->ext_para, ext_para, sizeof(struct fh_dma_extra)); + + switch (direction) { + case DMA_MEM_TO_DEV: + reg_width = __fls(sconfig->dst_addr_width); + reg = sconfig->dst_addr; + if(!ext_para){ + ctllo = (FHC_DEFAULT_CTLLO(chan) + | FHC_CTLL_DST_WIDTH(reg_width) + | FHC_CTLL_DST_FIX + | FHC_CTLL_SRC_INC); + } + else{ + ctllo = (FHC_DEFAULT_CTLLO(chan) | FHC_CTLL_DST_WIDTH(reg_width)); + ctllo |= ext_para->sinc << 9; + ctllo |= ext_para->dinc << 7; + ctllo &= ~(FHC_CTLL_SMS(3)); + ctllo &= ~(FHC_CTLL_DMS(3)); + ctllo |= FHC_CTLL_SMS(ext_para->src_master); + ctllo |= FHC_CTLL_DMS(ext_para->dst_master); + } + + ctllo |= sconfig->device_fc ? FHC_CTLL_FC(FH_DMA_FC_P_M2P) : + FHC_CTLL_FC(FH_DMA_FC_D_M2P); + + /*data_width = fhd->data_width[fhc->src_master];*/ + data_width = __fls(sconfig->src_addr_width); + for_each_sg(sgl, sg, sg_len, i) { + struct fh_desc *desc; + u32 len, dlen, mem; + + mem = sg_dma_address(sg); + len = sg_dma_len(sg); + + mem_width = min_t(unsigned int, + data_width, fhc_fast_fls(mem | len)); + +slave_sg_todev_fill_desc: + desc = fhc_desc_get(fhc); + if (!desc) { + dev_err(chan2dev(chan), + "not enough descriptors available\n"); + goto err_desc_get; + } + + desc->lli.sar = mem; + desc->lli.dar = reg; + desc->lli.ctllo = ctllo | FHC_CTLL_SRC_WIDTH(mem_width); + if ((len >> mem_width) > fhc->block_size) { + dlen = fhc->block_size << mem_width; + mem += dlen; + len -= dlen; + } else { + dlen = len; + len = 0; + } + + desc->lli.ctlhi = dlen >> mem_width; + desc->len = dlen; + + if (!first) { + first = desc; + } else { + prev->lli.llp = desc->txd.phys; + list_add_tail(&desc->desc_node, + &first->tx_list); + } + prev = desc; + total_len += dlen; + + if (len) + goto slave_sg_todev_fill_desc; + } + break; + case DMA_DEV_TO_MEM: + reg_width = __fls(sconfig->src_addr_width); + reg = sconfig->src_addr; + + if(!ext_para){ + ctllo = (FHC_DEFAULT_CTLLO(chan) + | FHC_CTLL_SRC_WIDTH(reg_width) + | FHC_CTLL_DST_INC + | FHC_CTLL_SRC_FIX); + } + else{ + ctllo = (FHC_DEFAULT_CTLLO(chan) | FHC_CTLL_SRC_WIDTH(reg_width)); + ctllo |= ext_para->sinc << 9; + ctllo |= ext_para->dinc << 7; + ctllo &= ~(FHC_CTLL_SMS(3)); + ctllo &= ~(FHC_CTLL_DMS(3)); + ctllo |= FHC_CTLL_SMS(ext_para->src_master); + ctllo |= FHC_CTLL_DMS(ext_para->dst_master); + } + + + ctllo |= sconfig->device_fc ? FHC_CTLL_FC(FH_DMA_FC_P_P2M) : + FHC_CTLL_FC(FH_DMA_FC_D_P2M); + + /*data_width = fhd->data_width[fhc->dst_master];*/ + data_width = __fls(sconfig->dst_addr_width); + for_each_sg(sgl, sg, sg_len, i) { + struct fh_desc *desc; + u32 len, dlen, mem; + + mem = sg_dma_address(sg); + len = sg_dma_len(sg); + + mem_width = min_t(unsigned int, + data_width, fhc_fast_fls(mem | len)); + +slave_sg_fromdev_fill_desc: + desc = fhc_desc_get(fhc); + if (!desc) { + dev_err(chan2dev(chan), + "not enough descriptors available\n"); + goto err_desc_get; + } + + desc->lli.sar = reg; + desc->lli.dar = mem; + desc->lli.ctllo = ctllo | FHC_CTLL_DST_WIDTH(mem_width); + if ((len >> reg_width) > fhc->block_size) { + dlen = fhc->block_size << reg_width; + mem += dlen; + len -= dlen; + } else { + dlen = len; + len = 0; + } + desc->lli.ctlhi = dlen >> reg_width; + desc->len = dlen; + + if (!first) { + first = desc; + } else { + prev->lli.llp = desc->txd.phys; + list_add_tail(&desc->desc_node, + &first->tx_list); + } + prev = desc; + total_len += dlen; + + if (len) + goto slave_sg_fromdev_fill_desc; + } + break; + default: + return NULL; + } + + if (flags & DMA_PREP_INTERRUPT) + /* Trigger interrupt after last block */ + prev->lli.ctllo |= FHC_CTLL_INT_EN; + + prev->lli.llp = 0; + first->total_len = total_len; + + return &first->txd; + +err_desc_get: + fhc_desc_put(fhc, first); + return NULL; +} + +/* + * Fix sconfig's burst size according to fh_dmac. We need to convert them as: + * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. + * + * NOTE: burst size 2 is not supported by controller. + * + * This can be done by finding least significant bit set: n & (n - 1) + */ +static inline void convert_burst(u32 *maxburst) +{ + if (*maxburst > 1) + *maxburst = fls(*maxburst) - 2; + else + *maxburst = 0; +} + +static int +set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig) +{ + struct fh_dma_chan *fhc = to_fh_dma_chan(chan); + + /* Check if chan will be configured for slave transfers */ + if (!is_slave_direction(sconfig->direction)) + return -EINVAL; + + memcpy(&fhc->dma_sconfig, sconfig, sizeof(*sconfig)); + fhc->direction = sconfig->direction; + + /* Take the request line from slave_id member */ + if (fhc->request_line == ~0) + fhc->request_line = sconfig->slave_id; + + convert_burst(&fhc->dma_sconfig.src_maxburst); + convert_burst(&fhc->dma_sconfig.dst_maxburst); + + return 0; +} + +static inline void fhc_chan_pause(struct fh_dma_chan *fhc) +{ + u32 cfglo = channel_readl(fhc, CFG_LO); + unsigned int count = 20; /* timeout iterations */ + + channel_writel(fhc, CFG_LO, cfglo | FHC_CFGL_CH_SUSP); + while (!(channel_readl(fhc, CFG_LO) & FHC_CFGL_FIFO_EMPTY) && count--) + udelay(2); + + fhc->paused = true; +} + +static inline void fhc_chan_resume(struct fh_dma_chan *fhc) +{ + u32 cfglo = channel_readl(fhc, CFG_LO); + + channel_writel(fhc, CFG_LO, cfglo & ~FHC_CFGL_CH_SUSP); + + fhc->paused = false; +} + +static int fhc_device_config(struct dma_chan *chan, struct dma_slave_config *config) +{ + return set_runtime_config(chan, config); +} + +static int fhc_device_pause(struct dma_chan *chan) +{ + struct fh_dma_chan *fhc = to_fh_dma_chan(chan); + unsigned long flags; + + spin_lock_irqsave(&fhc->lock, flags); + + fhc_chan_pause(fhc); + + spin_unlock_irqrestore(&fhc->lock, flags); + + return 0; +} + +static int fhc_device_resume(struct dma_chan *chan) +{ + struct fh_dma_chan *fhc = to_fh_dma_chan(chan); + unsigned long flags; + + if (!fhc->paused) + return 0; + + spin_lock_irqsave(&fhc->lock, flags); + + fhc_chan_resume(fhc); + + spin_unlock_irqrestore(&fhc->lock, flags); + + return 0; +} + +static int fhc_device_terminate_all(struct dma_chan *chan) +{ + struct fh_dma_chan *fhc = to_fh_dma_chan(chan); + struct fh_dma *fhd = to_fh_dma(chan->device); + struct fh_desc *desc, *_desc; + unsigned long flags; + LIST_HEAD(list); + + spin_lock_irqsave(&fhc->lock, flags); + + clear_bit(FH_DMA_IS_SOFT_LLP, &fhc->flags); + + fhc_chan_disable(fhd, fhc); + + fhc_chan_resume(fhc); + + /* active_list entries will end up before queued entries */ + list_splice_init(&fhc->queue, &list); + list_splice_init(&fhc->active_list, &list); + + spin_unlock_irqrestore(&fhc->lock, flags); + + /* Flush all pending and queued descriptors */ + list_for_each_entry_safe(desc, _desc, &list, desc_node) + fhc_descriptor_complete(fhc, desc, false); + + return 0; +} + +static inline u32 fhc_get_residue(struct fh_dma_chan *fhc) +{ + unsigned long flags; + u32 residue; + + spin_lock_irqsave(&fhc->lock, flags); + + residue = fhc->residue; + if (test_bit(FH_DMA_IS_SOFT_LLP, &fhc->flags) && residue) + residue -= fhc_get_sent(fhc); + + spin_unlock_irqrestore(&fhc->lock, flags); + return residue; +} + +static enum dma_status +fhc_tx_status(struct dma_chan *chan, + dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + struct fh_dma_chan *fhc = to_fh_dma_chan(chan); + enum dma_status ret; + + ret = dma_cookie_status(chan, cookie, txstate); + if (ret != DMA_COMPLETE) { + fhc_scan_descriptors(to_fh_dma(chan->device), fhc); + + ret = dma_cookie_status(chan, cookie, txstate); + } + + if (ret != DMA_COMPLETE) + dma_set_residue(txstate, fhc_get_residue(fhc)); + + if (fhc->paused) + return DMA_PAUSED; + + return ret; +} + +static void fhc_issue_pending(struct dma_chan *chan) +{ + struct fh_dma_chan *fhc = to_fh_dma_chan(chan); + + if (!list_empty(&fhc->queue)) + fhc_scan_descriptors(to_fh_dma(chan->device), fhc); +} + +static int fhc_alloc_chan_resources(struct dma_chan *chan) +{ + struct fh_dma_chan *fhc = to_fh_dma_chan(chan); + struct fh_dma *fhd = to_fh_dma(chan->device); + struct fh_desc *desc; + int i; + unsigned long flags; +#ifdef CONFIG_CHANNEL_ALLOC_MEM_CLASSICS + int j; + dma_addr_t phys; +#endif + dev_vdbg(chan2dev(chan), "%s\n", __func__); + + /* ASSERT: channel is idle */ + if (dma_readl(fhd, CH_EN) & fhc->mask) { + dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); + return -EIO; + } + + dma_cookie_init(chan); + + /* + * NOTE: some controllers may have additional features that we + * need to initialize here, like "scatter-gather" (which + * doesn't mean what you think it means), and status writeback. + */ + + fhc_set_masters(fhc); + + spin_lock_irqsave(&fhc->lock, flags); + i = fhc->descs_allocated; +#ifdef CONFIG_CHANNEL_ALLOC_MEM_CLASSICS + desc = (struct fh_desc *)dma_alloc_coherent(fhd->dma.dev, + sizeof(struct fh_desc) * NR_DESCS_PER_CHANNEL, &phys, GFP_KERNEL); + if (!desc) + goto err_desc_alloc; + fhc->dma_vaddr = (void *)desc; + fhc->dma_paddr = phys; + memset(desc, 0, sizeof(struct fh_desc) * NR_DESCS_PER_CHANNEL); + for (j = 0; j < NR_DESCS_PER_CHANNEL; j++, desc++) + { + INIT_LIST_HEAD(&desc->tx_list); + dma_async_tx_descriptor_init(&desc->txd, chan); + desc->txd.tx_submit = fhc_tx_submit; + desc->txd.flags = DMA_CTRL_ACK; + desc->txd.phys = phys + (j * sizeof(struct fh_desc)); + fhc_desc_put(fhc, desc); + i = ++fhc->descs_allocated; + } +#else + while (fhc->descs_allocated < NR_DESCS_PER_CHANNEL) { + dma_addr_t phys; + + spin_unlock_irqrestore(&fhc->lock, flags); + + desc = dma_pool_alloc(fhd->desc_pool, GFP_ATOMIC, &phys); + if (!desc) + goto err_desc_alloc; + + memset(desc, 0, sizeof(struct fh_desc)); + + INIT_LIST_HEAD(&desc->tx_list); + dma_async_tx_descriptor_init(&desc->txd, chan); + desc->txd.tx_submit = fhc_tx_submit; + desc->txd.flags = DMA_CTRL_ACK; + desc->txd.phys = phys; + + fhc_desc_put(fhc, desc); + + spin_lock_irqsave(&fhc->lock, flags); + i = ++fhc->descs_allocated; + } +#endif + + spin_unlock_irqrestore(&fhc->lock, flags); + + return i; + +err_desc_alloc: + dev_err(chan2dev(chan), "only allocated %d descriptors\n", i); + + return i; +} + +static void fhc_free_chan_resources(struct dma_chan *chan) +{ + struct fh_dma_chan *fhc = to_fh_dma_chan(chan); + struct fh_dma *fhd = to_fh_dma(chan->device); +#ifndef CONFIG_CHANNEL_ALLOC_MEM_CLASSICS + struct fh_desc *desc, *_desc; +#endif + unsigned long flags; + LIST_HEAD(list); + + dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, + fhc->descs_allocated); + + /* ASSERT: channel is idle */ + BUG_ON(!list_empty(&fhc->active_list)); + BUG_ON(!list_empty(&fhc->queue)); + BUG_ON(dma_readl(to_fh_dma(chan->device), CH_EN) & fhc->mask); + + spin_lock_irqsave(&fhc->lock, flags); + list_splice_init(&fhc->free_list, &list); + fhc->descs_allocated = 0; + fhc->initialized = false; + fhc->request_line = ~0; + + /* Disable interrupts */ + channel_clear_bit(fhd, MASK.XFER, fhc->mask); + channel_clear_bit(fhd, MASK.BLOCK, fhc->mask); + channel_clear_bit(fhd, MASK.ERROR, fhc->mask); + + spin_unlock_irqrestore(&fhc->lock, flags); +#ifdef CONFIG_CHANNEL_ALLOC_MEM_CLASSICS + dma_free_coherent(fhd->dma.dev, + sizeof(struct fh_desc) * NR_DESCS_PER_CHANNEL, + fhc->dma_vaddr, fhc->dma_paddr); +#else + + list_for_each_entry_safe(desc, _desc, &list, desc_node) { + dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); + dma_pool_free(fhd->desc_pool, desc, desc->txd.phys); + } +#endif + + + dev_vdbg(chan2dev(chan), "%s: done\n", __func__); +} + + +/* --------------------- Cyclic DMA API extensions -------------------- */ + +/** + * fh_dma_cyclic_start - start the cyclic DMA transfer + * @chan: the DMA channel to start + * + * Must be called with soft interrupts disabled. Returns zero on success or + * -errno on failure. + */ +int fh_dma_cyclic_start(struct dma_chan *chan) +{ + struct fh_dma_chan *fhc = to_fh_dma_chan(chan); + struct fh_dma *fhd = to_fh_dma(fhc->chan.device); + unsigned long flags; + + if (!test_bit(FH_DMA_IS_CYCLIC, &fhc->flags)) { + dev_err(chan2dev(&fhc->chan), "missing prep for cyclic DMA\n"); + return -ENODEV; + } + + spin_lock_irqsave(&fhc->lock, flags); + + /* Assert channel is idle */ + if (dma_readl(fhd, CH_EN) & fhc->mask) { + dev_err(chan2dev(&fhc->chan), + "BUG: Attempted to start non-idle channel\n"); + fhc_dump_chan_regs(fhc); + spin_unlock_irqrestore(&fhc->lock, flags); + return -EBUSY; + } + + dma_writel(fhd, CLEAR.ERROR, fhc->mask); + dma_writel(fhd, CLEAR.XFER, fhc->mask); + dma_writel(fhd, CLEAR.BLOCK, fhc->mask); + + fhc_initialize(fhc); + + /* Setup DMAC channel registers */ + channel_writel(fhc, LLP, fhc->cdesc->desc[0]->txd.phys); + channel_writel(fhc, CTL_LO, FHC_CTLL_LLP_D_EN | FHC_CTLL_LLP_S_EN); + channel_writel(fhc, CTL_HI, 0); + + channel_set_bit(fhd, CH_EN, fhc->mask); + + spin_unlock_irqrestore(&fhc->lock, flags); + + return 0; +} +EXPORT_SYMBOL(fh_dma_cyclic_start); + +/** + * fh_dma_cyclic_stop - stop the cyclic DMA transfer + * @chan: the DMA channel to stop + * + * Must be called with soft interrupts disabled. + */ +void fh_dma_cyclic_stop(struct dma_chan *chan) +{ + struct fh_dma_chan *fhc = to_fh_dma_chan(chan); + struct fh_dma *fhd = to_fh_dma(fhc->chan.device); + unsigned long flags; + + spin_lock_irqsave(&fhc->lock, flags); + + fhc_chan_disable(fhd, fhc); + + spin_unlock_irqrestore(&fhc->lock, flags); +} +EXPORT_SYMBOL(fh_dma_cyclic_stop); + +/** + * fh_dma_cyclic_prep - prepare the cyclic DMA transfer + * @chan: the DMA channel to prepare + * @buf_addr: physical DMA address where the buffer starts + * @buf_len: total number of bytes for the entire buffer + * @period_len: number of bytes for each period + * @direction: transfer direction, to or from device + * + * Must be called before trying to start the transfer. Returns a valid struct + * fh_cyclic_desc if successful or an ERR_PTR(-errno) if not successful. + */ +struct fh_cyclic_desc *fh_dma_cyclic_prep(struct dma_chan *chan, + dma_addr_t buf_addr, size_t buf_len, size_t period_len, + enum dma_transfer_direction direction) +{ + struct fh_dma_chan *fhc = to_fh_dma_chan(chan); + struct fh_dma_slave *fhs = chan->private; + struct fh_cyclic_desc *cdesc; + struct fh_cyclic_desc *retval = NULL; + struct fh_desc *desc; + struct fh_desc *last = NULL; + unsigned long was_cyclic; + unsigned int reg_width; + unsigned int periods; + unsigned int i; + unsigned long flags; + + spin_lock_irqsave(&fhc->lock, flags); + if (fhc->nollp) { + spin_unlock_irqrestore(&fhc->lock, flags); + dev_dbg(chan2dev(&fhc->chan), + "channel doesn't support LLP transfers\n"); + return ERR_PTR(-EINVAL); + } + + if (!list_empty(&fhc->queue) || !list_empty(&fhc->active_list)) { + spin_unlock_irqrestore(&fhc->lock, flags); + dev_dbg(chan2dev(&fhc->chan), + "queue and/or active list are not empty\n"); + return ERR_PTR(-EBUSY); + } + + was_cyclic = test_and_set_bit(FH_DMA_IS_CYCLIC, &fhc->flags); + spin_unlock_irqrestore(&fhc->lock, flags); + if (was_cyclic) { + dev_dbg(chan2dev(&fhc->chan), + "channel already prepared for cyclic DMA\n"); + return ERR_PTR(-EBUSY); + } + + retval = ERR_PTR(-EINVAL); + + reg_width = fhs->reg_width; + + if (unlikely(!is_slave_direction(direction))) + goto out_err; + + fhc->direction = direction; + + periods = buf_len / period_len; + + /* Check for too big/unaligned periods and unaligned DMA buffer. */ + if (period_len > (fhc->block_size << reg_width)) + goto out_err; + if (unlikely(period_len & ((1 << reg_width) - 1))) + goto out_err; + if (unlikely(buf_addr & ((1 << reg_width) - 1))) + goto out_err; + + retval = ERR_PTR(-ENOMEM); + + if (periods > NR_DESCS_PER_CHANNEL) + goto out_err; + + cdesc = kzalloc(sizeof(struct fh_cyclic_desc), GFP_KERNEL); + if (!cdesc) + goto out_err; + + cdesc->desc = kzalloc(sizeof(struct fh_desc *) * periods, GFP_KERNEL); + if (!cdesc->desc) + goto out_err_alloc; + + for (i = 0; i < periods; i++) { + desc = fhc_desc_get(fhc); + if (!desc) + goto out_err_desc_get; + + switch (direction) { + case DMA_MEM_TO_DEV: + desc->lli.dar = fhs->tx_reg; + desc->lli.sar = buf_addr + (period_len * i); + desc->lli.ctllo = (FHC_DEFAULT_CTLLO_OLD(chan->private) + | FHC_CTLL_DST_WIDTH(reg_width) + | FHC_CTLL_SRC_WIDTH(reg_width) + | FHC_CTLL_DST_FIX + | FHC_CTLL_SRC_INC + | FHC_CTLL_FC(fhs->fc) + | FHC_CTLL_INT_EN); + + break; + case DMA_DEV_TO_MEM: + desc->lli.dar = buf_addr + (period_len * i); + desc->lli.sar = fhs->rx_reg; + desc->lli.ctllo = (FHC_DEFAULT_CTLLO_OLD(chan->private) + | FHC_CTLL_SRC_WIDTH(reg_width) + | FHC_CTLL_DST_WIDTH(reg_width) + | FHC_CTLL_DST_INC + | FHC_CTLL_SRC_FIX + | FHC_CTLL_FC(fhs->fc) + | FHC_CTLL_INT_EN); + + + break; + default: + break; + } + + desc->lli.ctlhi = (period_len >> reg_width); + cdesc->desc[i] = desc; + + if (last) + { + last->lli.llp = desc->txd.phys; + dma_sync_single_for_device(chan2parent(chan), + last->txd.phys, + sizeof(last->lli), + DMA_TO_DEVICE); + } + + last = desc; + } + + /* Let's make a cyclic list */ + last->lli.llp = cdesc->desc[0]->txd.phys; + dma_sync_single_for_device(chan2parent(chan), last->txd.phys, + sizeof(last->lli), DMA_TO_DEVICE); + + dev_dbg(chan2dev(&fhc->chan), "cyclic prepared buf 0x%llx len %zu " + "period %zu periods %d\n", (unsigned long long)buf_addr, + buf_len, period_len, periods); + + cdesc->periods = periods; + fhc->cdesc = cdesc; + + return cdesc; + +out_err_desc_get: + while (i--) + fhc_desc_put(fhc, cdesc->desc[i]); +out_err_alloc: + kfree(cdesc); +out_err: + clear_bit(FH_DMA_IS_CYCLIC, &fhc->flags); + return (struct fh_cyclic_desc *)retval; +} +EXPORT_SYMBOL(fh_dma_cyclic_prep); + +/** + * fh_dma_cyclic_free - free a prepared cyclic DMA transfer + * @chan: the DMA channel to free + */ +void fh_dma_cyclic_free(struct dma_chan *chan) +{ + struct fh_dma_chan *fhc = to_fh_dma_chan(chan); + struct fh_dma *fhd = to_fh_dma(fhc->chan.device); + struct fh_cyclic_desc *cdesc = fhc->cdesc; + int i; + unsigned long flags; + + dev_dbg(chan2dev(&fhc->chan), "%s\n", __func__); + + if (!cdesc) + return; + + spin_lock_irqsave(&fhc->lock, flags); + + fhc_chan_disable(fhd, fhc); + + dma_writel(fhd, CLEAR.ERROR, fhc->mask); + dma_writel(fhd, CLEAR.XFER, fhc->mask); + dma_writel(fhd, CLEAR.BLOCK, fhc->mask); + + spin_unlock_irqrestore(&fhc->lock, flags); + + for (i = 0; i < cdesc->periods; i++) + fhc_desc_put(fhc, cdesc->desc[i]); + + kfree(cdesc->desc); + kfree(cdesc); + + clear_bit(FH_DMA_IS_CYCLIC, &fhc->flags); +} +EXPORT_SYMBOL(fh_dma_cyclic_free); + +/*----------------------------------------------------------------------*/ + +static void fh_dma_off(struct fh_dma *fhd) +{ + int i; + + dma_writel(fhd, CFG, 0); + + channel_clear_bit(fhd, MASK.XFER, fhd->all_chan_mask); + channel_clear_bit(fhd, MASK.BLOCK, fhd->all_chan_mask); + channel_clear_bit(fhd, MASK.SRC_TRAN, fhd->all_chan_mask); + channel_clear_bit(fhd, MASK.DST_TRAN, fhd->all_chan_mask); + channel_clear_bit(fhd, MASK.ERROR, fhd->all_chan_mask); + + while (dma_readl(fhd, CFG) & FH_CFG_DMA_EN) + cpu_relax(); + + for (i = 0; i < fhd->dma.chancnt; i++) + fhd->chan[i].initialized = false; +} + +static int fh_dma_probe(struct platform_device *pdev) +{ + struct fh_dma_platform_data *pdata; + struct device_node *np = pdev->dev.of_node; + struct fh_dma *fhd; + size_t size; + void __iomem *regs; + bool autocfg; + unsigned int fh_params; + unsigned int nr_channels; + unsigned int max_blk_size = 0; + int irq; + int err; + int i; + struct resource *res; + + if (np && !IS_ERR(np)) { + regs = of_iomap(np, 0); + if (!regs) { + err = -ENOMEM; + goto err_release_r; + } + irq = irq_of_parse_and_map(np, 0); + } else { + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "can't fetch device resource info\n"); + goto err_release_r; + } + regs = ioremap(res->start, resource_size(res)); + if (regs == NULL) { + dev_err(&pdev->dev, "ioremap resource error\n"); + goto err_release_r; + } + irq = platform_get_irq(pdev, 0); + irq = irq_create_mapping(NULL, irq); + } + + /* Apply default dma_mask if needed */ + if (!pdev->dev.dma_mask) { + pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; + pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); + } + + fh_params = dma_read_byaddr(regs, FH_PARAMS); + autocfg = fh_params >> FH_PARAMS_EN & 0x1; + dev_dbg(&pdev->dev, "FH_PARAMS: 0x%08x\n", fh_params); + pdata = dev_get_platdata(&pdev->dev); + if (!pdata && autocfg) { + pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + + /* Fill platform data with the default values */ + pdata->is_private = true; + pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; + pdata->chan_priority = CHAN_PRIORITY_ASCENDING; + } else if (!pdata || pdata->nr_channels > FH_DMA_MAX_NR_CHANNELS) + return -EINVAL; + + if (autocfg) + nr_channels = (fh_params >> FH_PARAMS_NR_CHAN & 0x7) + 1; + else + nr_channels = pdata->nr_channels; + + size = sizeof(struct fh_dma) + nr_channels * sizeof(struct fh_dma_chan); + fhd = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); + fhd->regs = regs; + if (!fhd) + return -ENOMEM; + + if (np && !IS_ERR(np)) + fhd->clk = of_clk_get(np, 0); + else + fhd->clk = clk_get(&pdev->dev, pdata->clk_name); + if (IS_ERR(fhd->clk)) { + devm_kfree(&pdev->dev, fhd); + return EINVAL; + } + clk_prepare_enable(fhd->clk); + /* Get hardware configuration parameters */ + if (autocfg) { + max_blk_size = dma_readl(fhd, MAX_BLK_SIZE); + + fhd->nr_masters = (fh_params >> FH_PARAMS_NR_MASTER & 3) + 1; + for (i = 0; i < fhd->nr_masters; i++) { + fhd->data_width[i] = + (fh_params >> FH_PARAMS_DATA_WIDTH(i) & 3) + 2; + } + } else { + fhd->nr_masters = pdata->nr_masters; + memcpy(fhd->data_width, pdata->data_width, 4); + } + + /* Calculate all channel mask before DMA setup */ + fhd->all_chan_mask = (1 << nr_channels) - 1; + + /* Force dma off, just in case */ + fh_dma_off(fhd); + + /* Disable BLOCK interrupts as well */ + channel_clear_bit(fhd, MASK.BLOCK, fhd->all_chan_mask); + + err = devm_request_irq(&pdev->dev, irq, fh_dma_interrupt, 0, + "fh-dmac", fhd); + + if (err) + return err; + + platform_set_drvdata(pdev, fhd); +#ifndef CONFIG_CHANNEL_ALLOC_MEM_CLASSICS + /* Create a pool of consistent memory blocks for hardware descriptors */ + fhd->desc_pool = dmam_pool_create("fh_dmac_desc_pool", &pdev->dev, + sizeof(struct fh_desc), 4, 0); + if (!fhd->desc_pool) { + dev_err(&pdev->dev, "No memory for descriptors dma pool\n"); + return -ENOMEM; + } +#endif + tasklet_init(&fhd->tasklet, fh_dma_tasklet, (unsigned long)fhd); + + INIT_LIST_HEAD(&fhd->dma.channels); + for (i = 0; i < nr_channels; i++) { + struct fh_dma_chan *fhc = &fhd->chan[i]; + int r = nr_channels - i - 1; + + fhc->chan.device = &fhd->dma; + dma_cookie_init(&fhc->chan); + if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) + list_add_tail(&fhc->chan.device_node, + &fhd->dma.channels); + else + list_add(&fhc->chan.device_node, &fhd->dma.channels); + + /* 7 is highest priority & 0 is lowest. */ + if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) + fhc->priority = r; + else + fhc->priority = i; + + fhc->ch_regs = &__fh_regs(fhd)->CHAN[i]; + spin_lock_init(&fhc->lock); + fhc->mask = 1 << i; + + INIT_LIST_HEAD(&fhc->active_list); + INIT_LIST_HEAD(&fhc->queue); + INIT_LIST_HEAD(&fhc->free_list); + + channel_clear_bit(fhd, CH_EN, fhc->mask); + + fhc->direction = DMA_TRANS_NONE; + fhc->request_line = ~0; + + /* Hardware configuration */ + if (autocfg) { + unsigned int fhc_params; + + fhc_params = dma_read_byaddr(regs + r * sizeof(u32), + FHC_PARAMS); + + dev_dbg(&pdev->dev, "FHC_PARAMS[%d]: 0x%08x\n", i, + fhc_params); + + /* Decode maximum block size for given channel. The + * stored 4 bit value represents blocks from 0x00 for 3 + * up to 0x0a for 4095. */ + fhc->block_size = + (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1; + fhc->nollp = + (fhc_params >> FHC_PARAMS_MBLK_EN & 0x1) == 0; + } else { + fhc->block_size = pdata->block_size; + + /* Check if channel supports multi block transfer */ + channel_writel(fhc, LLP, 0xfffffffc); + fhc->nollp = + (channel_readl(fhc, LLP) & 0xfffffffc) == 0; + channel_writel(fhc, LLP, 0); + } + } + + /* Clear all interrupts on all channels. */ + dma_writel(fhd, CLEAR.XFER, fhd->all_chan_mask); + dma_writel(fhd, CLEAR.BLOCK, fhd->all_chan_mask); + dma_writel(fhd, CLEAR.SRC_TRAN, fhd->all_chan_mask); + dma_writel(fhd, CLEAR.DST_TRAN, fhd->all_chan_mask); + dma_writel(fhd, CLEAR.ERROR, fhd->all_chan_mask); + + dma_cap_set(DMA_MEMCPY, fhd->dma.cap_mask); + dma_cap_set(DMA_SLAVE, fhd->dma.cap_mask); + if (pdata->is_private) + dma_cap_set(DMA_PRIVATE, fhd->dma.cap_mask); + fhd->dma.dev = &pdev->dev; + fhd->dma.device_alloc_chan_resources = fhc_alloc_chan_resources; + fhd->dma.device_free_chan_resources = fhc_free_chan_resources; + + fhd->dma.device_prep_dma_memcpy = fhc_prep_dma_memcpy; + + fhd->dma.device_prep_slave_sg = fhc_prep_slave_sg; + + fhd->dma.device_config = fhc_device_config; + fhd->dma.device_pause = fhc_device_pause; + fhd->dma.device_resume = fhc_device_resume; + fhd->dma.device_terminate_all = fhc_device_terminate_all; + + fhd->dma.device_tx_status = fhc_tx_status; + fhd->dma.device_issue_pending = fhc_issue_pending; + + dma_writel(fhd, CFG, FH_CFG_DMA_EN); + + err = dma_async_device_register(&fhd->dma); + + if (err) + pr_err("dma register failed, ret %d\n", err); + + dev_info(&pdev->dev, "FH DMA Controller, %d channels\n", nr_channels); + + return 0; + +err_release_r: + return err; +} + +static int fh_dma_remove(struct platform_device *pdev) +{ + struct fh_dma *fhd = platform_get_drvdata(pdev); + struct fh_dma_chan *fhc, *_fhc; + + fh_dma_off(fhd); + dma_async_device_unregister(&fhd->dma); + + tasklet_kill(&fhd->tasklet); + + list_for_each_entry_safe(fhc, _fhc, &fhd->dma.channels, + chan.device_node) { + list_del(&fhc->chan.device_node); + channel_clear_bit(fhd, CH_EN, fhc->mask); + } + + return 0; +} + +static void fh_dma_shutdown(struct platform_device *pdev) +{ + struct fh_dma *fhd = platform_get_drvdata(pdev); + + fh_dma_off(fhd); + clk_disable_unprepare(fhd->clk); +} + +static int fh_dma_suspend_noirq(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct fh_dma *fhd = platform_get_drvdata(pdev); + + fh_dma_off(fhd); + clk_disable_unprepare(fhd->clk); + + return 0; +} + +static int fh_dma_resume_noirq(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct fh_dma *fhd = platform_get_drvdata(pdev); + + clk_prepare_enable(fhd->clk); + dma_writel(fhd, CFG, FH_CFG_DMA_EN); + + return 0; +} + +static const struct of_device_id fh_dma_of_id_table[] = { + { .compatible = "fh,fh-dma" }, + {} +}; + +static const struct dev_pm_ops fh_dma_dev_pm_ops = { + .suspend_noirq = fh_dma_suspend_noirq, + .resume_noirq = fh_dma_resume_noirq, + .freeze_noirq = fh_dma_suspend_noirq, + .thaw_noirq = fh_dma_resume_noirq, + .restore_noirq = fh_dma_resume_noirq, + .poweroff_noirq = fh_dma_suspend_noirq, +}; + +static struct platform_driver fh_dma_driver = { + .probe = fh_dma_probe, + .remove = fh_dma_remove, + .shutdown = fh_dma_shutdown, + .driver = { + .name = "fh_dmac", + .pm = &fh_dma_dev_pm_ops, + .of_match_table = of_match_ptr(fh_dma_of_id_table), + }, +}; + +static int __init fh_dma_init(void) +{ + return platform_driver_register(&fh_dma_driver); +} +subsys_initcall(fh_dma_init); + +static void __exit fh_dma_exit(void) +{ + platform_driver_unregister(&fh_dma_driver); +} +module_exit(fh_dma_exit); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("fullhan AHB-DMA devive driver"); diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 12d417a4..7bff612d 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -150,6 +150,12 @@ config GPIO_CLPS711X help Say yes here to support GPIO on CLPS711X SoCs. +config GPIO_FH + tristate "FH GPIO support" + depends on ARCH_FULLHAN + help + Say yes here to support GPIO functionality of FH. + config GPIO_DAVINCI bool "TI Davinci/Keystone GPIO support" default y if ARCH_DAVINCI diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index d074c229..4cfe26e4 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -141,3 +141,4 @@ obj-$(CONFIG_GPIO_ZEVIO) += gpio-zevio.o obj-$(CONFIG_GPIO_ZYNQ) += gpio-zynq.o obj-$(CONFIG_GPIO_ZX) += gpio-zx.o obj-$(CONFIG_GPIO_LOONGSON1) += gpio-loongson1.o +obj-$(CONFIG_GPIO_FH) += fh_gpio.o \ No newline at end of file diff --git a/drivers/gpio/fh_gpio.c b/drivers/gpio/fh_gpio.c new file mode 100644 index 00000000..90fd50b1 --- /dev/null +++ b/drivers/gpio/fh_gpio.c @@ -0,0 +1,889 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * GPIO Direction + */ +#define GPIO_DIR_INPUT 0 +#define GPIO_DIR_OUTPUT 1 + +/* + * GPIO interrupt type + */ +#define GPIO_INT_TYPE_LEVEL 0 +#define GPIO_INT_TYPE_EDGE 1 + +/* + * GPIO interrupt polarity + */ +#define GPIO_INT_POL_LOW 0 +#define GPIO_INT_POL_HIGH 1 + +#define OFFSET_GPIO_SWPORTA_DR (0x0000) +#define OFFSET_GPIO_SWPORTA_DDR (0x0004) +#define OFFSET_GPIO_PORTA_CTL (0x0008) +#define OFFSET_GPIO_SWPORTB_DR (0x000C) +#define OFFSET_GPIO_SWPORTB_DDR (0x0010) +#define OFFSET_GPIO_PORTB_CTL (0x0014) +#define OFFSET_GPIO_INTEN (0x0030) +#define OFFSET_GPIO_INTMASK (0x0034) +#define OFFSET_GPIO_INTTYPE_LEVEL (0x0038) +#define OFFSET_GPIO_INT_POLARITY (0x003C) +#define OFFSET_GPIO_INTSTATUS (0x0040) +#define OFFSET_GPIO_RAWINTSTATUS (0x0044) +#define OFFSET_GPIO_DEBOUNCE (0x0048) +#define OFFSET_GPIO_PORTA_EOI (0x004C) +#define OFFSET_GPIO_EXT_PORTA (0x0050) +#define OFFSET_GPIO_EXT_PORTB (0x0054) +#define OFFSET_GPIO_INT_BOTH (0x0068) + +struct fh_gpio_chip *fh_gpio0, *fh_gpio1, *fh_gpio2, *fh_gpio3; + +static inline void FH_GPIO_SetValue(void __iomem *base, int bit, int val) +{ + unsigned int reg; + + reg = readl(base + OFFSET_GPIO_SWPORTA_DR); + reg = val ? (reg | (1 << bit)) : (reg & ~(1 << bit)); + writel(reg, base + OFFSET_GPIO_SWPORTA_DR); +} + +static inline int FH_GPIO_GetValue(void __iomem *base, int bit) +{ + return (readl(base + OFFSET_GPIO_EXT_PORTA) >> bit) & 0x1; +} + +static inline void FH_GPIO_SetDirection(void __iomem *base, int bit, int dir) +{ + unsigned int reg; + + reg = readl(base + OFFSET_GPIO_SWPORTA_DDR); + reg = dir ? reg | (1 << bit) : reg & ~(1 << bit); + writel(reg, base + OFFSET_GPIO_SWPORTA_DDR); +} + +static inline int FH_GPIO_GetDirection(void __iomem *base, int bit) +{ + return (readl(base + OFFSET_GPIO_SWPORTA_DDR) >> bit) & 0x1; +} + +static inline void FH_GPIOB_SetValue(void __iomem *base, int bit, int val) +{ + unsigned int reg; + + reg = readl(base + OFFSET_GPIO_SWPORTB_DR); + reg = val ? (reg | (1 << bit)) : (reg & ~(1 << bit)); + writel(reg, base + OFFSET_GPIO_SWPORTB_DR); +} + +static inline int FH_GPIOB_GetValue(void __iomem *base, int bit) +{ + return (readl(base + OFFSET_GPIO_EXT_PORTB) >> bit) & 0x1; +} + +static inline void FH_GPIOB_SetDirection(void __iomem *base, int bit, int dir) +{ + unsigned int reg; + + reg = readl(base + OFFSET_GPIO_SWPORTB_DDR); + reg = dir ? reg | (1 << bit) : reg & ~(1 << bit); + writel(reg, base + OFFSET_GPIO_SWPORTB_DDR); +} + +static inline int FH_GPIOB_GetDirection(void __iomem *base, int bit) +{ + return (readl(base + OFFSET_GPIO_SWPORTB_DDR) >> bit) & 0x1; +} + +static inline void FH_GPIO_EnableDebounce(void __iomem *base, int bit, int bool) +{ + unsigned int reg; + + reg = readl(base + OFFSET_GPIO_DEBOUNCE); + reg = bool ? reg | (1 << bit) : reg & ~(1 << bit); + writel(reg, base + OFFSET_GPIO_DEBOUNCE); +} + +static inline void FH_GPIO_SetInterruptType(void __iomem *base, int bit, + int type) +{ + unsigned int reg; + + reg = readl(base + OFFSET_GPIO_INTTYPE_LEVEL); + reg = type ? reg | (1 << bit) : reg & ~(1 << bit); + writel(reg, base + OFFSET_GPIO_INTTYPE_LEVEL); +} + +static inline void FH_GPIO_SetInterruptPolarity(void __iomem *base, int bit, + int pol) +{ + unsigned int reg; + + reg = readl(base + OFFSET_GPIO_INT_POLARITY); + reg = pol ? reg | (1 << bit) : reg & ~(1 << bit); + writel(reg, base + OFFSET_GPIO_INT_POLARITY); +} + +static inline void FH_GPIO_Set_BothInterrupt_enable(void __iomem *base, int bit) +{ + unsigned int reg; + + reg = readl(base + OFFSET_GPIO_INT_BOTH); + reg |= (1 << bit); + writel(reg, base + OFFSET_GPIO_INT_BOTH); +} + +static inline void FH_GPIO_Set_BothInterrupt_disable(void __iomem *base, + int bit) +{ + unsigned int reg; + + reg = readl(base + OFFSET_GPIO_INT_BOTH); + reg &= ~(1 << bit); + writel(reg, base + OFFSET_GPIO_INT_BOTH); +} + +static inline void FH_GPIO_EnableInterruptMask(void __iomem *base, int bit, + int bool) +{ + unsigned int reg; + + reg = readl(base + OFFSET_GPIO_INTMASK); + reg = bool ? reg | (1 << bit) : reg & ~(1 << bit); + writel(reg, base + OFFSET_GPIO_INTMASK); +} + +static inline void FH_GPIO_EnableInterrupt(void __iomem *base, int bit, int bool) +{ + unsigned int reg; + + reg = readl(base + OFFSET_GPIO_INTEN); + reg = bool ? reg | (1 << bit) : reg & ~(1 << bit); + writel(reg, base + OFFSET_GPIO_INTEN); +} + +static inline void FH_GPIO_SetEnableInterrupts(void __iomem *base, + unsigned int val) +{ + writel(val, base + OFFSET_GPIO_INTEN); +} + +static inline unsigned int FH_GPIO_GetEnableInterrupts(void __iomem *base) +{ + return readl(base + OFFSET_GPIO_INTEN); +} + +static inline unsigned int FH_GPIO_GetInterruptStatus(void __iomem *base) +{ + return readl(base + OFFSET_GPIO_INTSTATUS); +} + +static inline void FH_GPIO_ClearInterrupt(void __iomem *base, int bit) +{ + unsigned int reg; + + reg = readl(base + OFFSET_GPIO_PORTA_EOI); + reg |= (1 << bit); + writel(reg, base + OFFSET_GPIO_PORTA_EOI); +} + + +static inline void __iomem *gpio_to_base(unsigned int gpio) +{ + void __iomem *base; + gpio = gpio / 32; + + switch (gpio) { + case 0: + base = fh_gpio0->base; + break; + case 1: + base = fh_gpio1->base; + break; + case 2: + base = fh_gpio2->base; + break; + case 3: + base = fh_gpio3->base; + break; + default: + pr_err("ERROR: incorrect GPIO num\n"); + base = NULL; + break; + } + + return base; +} + +static int _set_gpio_irq_type(unsigned int gpio, unsigned int type) +{ + u32 int_type, int_polarity; + u32 bit = gpio % 32; + void __iomem *base; + struct fh_gpio_chip *fh_gpio = NULL; + + switch (gpio / 32) { + case 0: + fh_gpio = fh_gpio0; + break; + case 1: + fh_gpio = fh_gpio1; + break; + case 2: + fh_gpio = fh_gpio2; + break; + case 3: + fh_gpio = fh_gpio3; + break; + default: + return -EINVAL; + } + + base = gpio_to_base(gpio); + switch (type & IRQF_TRIGGER_MASK) { + case IRQ_TYPE_EDGE_BOTH: + if (!fh_gpio->type) { + int_type = GPIO_INT_TYPE_EDGE; + /* toggle trigger */ + if (FH_GPIO_GetValue(base, bit)) + int_polarity = GPIO_INT_POL_LOW; + else + int_polarity = GPIO_INT_POL_HIGH; + } + break; + case IRQ_TYPE_EDGE_RISING: + int_type = GPIO_INT_TYPE_EDGE; + int_polarity = GPIO_INT_POL_HIGH; + break; + case IRQ_TYPE_EDGE_FALLING: + int_type = GPIO_INT_TYPE_EDGE; + int_polarity = GPIO_INT_POL_LOW; + break; + case IRQ_TYPE_LEVEL_HIGH: + int_type = GPIO_INT_TYPE_LEVEL; + int_polarity = GPIO_INT_POL_HIGH; + break; + case IRQ_TYPE_LEVEL_LOW: + int_type = GPIO_INT_TYPE_LEVEL; + int_polarity = GPIO_INT_POL_LOW; + break; + case IRQ_TYPE_NONE: + return 0; + default: + return -EINVAL; + } + + if ((type & IRQF_TRIGGER_MASK) == IRQ_TYPE_EDGE_BOTH) { + if (fh_gpio->type) + FH_GPIO_Set_BothInterrupt_enable(base, bit); + else { + FH_GPIO_SetInterruptType(base, bit, int_type); + FH_GPIO_SetInterruptPolarity(base, bit, int_polarity); + } + } else { + FH_GPIO_Set_BothInterrupt_disable(base, bit); + FH_GPIO_SetInterruptType(base, bit, int_type); + FH_GPIO_SetInterruptPolarity(base, bit, int_polarity); + } + + return 0; +} + +int fh_set_gpio_irq(struct gpio_irq_info *info) +{ + void __iomem *base; + + base = gpio_to_base(info->irq_gpio); + return _set_gpio_irq_type(info->irq_gpio, info->irq_type); +} +EXPORT_SYMBOL(fh_set_gpio_irq); + +void fh_irq_enable(unsigned int gpio) +{ + void __iomem *base; + int gpio_num = gpio % 32; + + base = gpio_to_base(gpio); + + FH_GPIO_EnableInterrupt(base, gpio_num, 1); +} +EXPORT_SYMBOL(fh_irq_enable); + +void fh_irq_disable(unsigned int gpio) +{ + void __iomem *base; + int gpio_num = gpio % 32; + + base = gpio_to_base(gpio); + FH_GPIO_EnableInterrupt(base, gpio_num, 0); +} +EXPORT_SYMBOL(fh_irq_disable); + +void fh_clear_gpio_irq(int gpio_id) +{ + void __iomem *base; + int gpio_num = gpio_id % 32; + + base = gpio_to_base(gpio_id); + FH_GPIO_ClearInterrupt(base, gpio_num); +} +EXPORT_SYMBOL(fh_clear_gpio_irq); + +static inline void __iomem *irq_to_controller(struct irq_data *d) +{ + struct fh_gpio_chip *fh_gpio = irq_data_get_irq_chip_data(d); + + return fh_gpio->base; +} + +static void gpio_irq_ack(struct irq_data *d) +{ + void __iomem *base; + + unsigned int gpio_bit = d->hwirq; + /* struct fh_gpio_chip *fh_gpio = irq_data_get_irq_chip_data(d); */ + + base = irq_to_controller(d); + FH_GPIO_ClearInterrupt(base, gpio_bit); +} + +static void gpio_irq_enable(struct irq_data *d) +{ + void __iomem *base; + + unsigned gpio_bit = d->hwirq; + /* struct fh_gpio_chip *fh_gpio = irq_data_get_irq_chip_data(d); */ + + base = irq_to_controller(d); + FH_GPIO_EnableInterrupt(base, gpio_bit, 1); +} + +static void gpio_irq_disable(struct irq_data *d) +{ + void __iomem *base; + + unsigned gpio_bit = d->hwirq; + /* struct fh_gpio_chip *fh_gpio = irq_data_get_irq_chip_data(d); */ + + base = irq_to_controller(d); + FH_GPIO_EnableInterrupt(base, gpio_bit, 0); +} + +static void gpio_irq_mask(struct irq_data *d) +{ + void __iomem *base; + + unsigned gpio_bit = d->hwirq; + /* struct fh_gpio_chip *fh_gpio = irq_data_get_irq_chip_data(d); */ + + base = irq_to_controller(d); + FH_GPIO_EnableInterruptMask(base, gpio_bit, 1); +} + +static void gpio_irq_unmask(struct irq_data *d) +{ + void __iomem *base; + + unsigned int gpio_bit = d->hwirq; + /* struct fh_gpio_chip *fh_gpio = irq_data_get_irq_chip_data(d); */ + + base = irq_to_controller(d); + FH_GPIO_EnableInterruptMask(base, gpio_bit, 0); +} + +static int gpio_irq_type(struct irq_data *d, unsigned int type) +{ + void __iomem *base; + unsigned int gpio; + + unsigned gpio_bit = d->hwirq; + struct fh_gpio_chip *fh_gpio = irq_data_get_irq_chip_data(d); + + base = irq_to_controller(d); + gpio = gpio_bit + fh_gpio->chip.base; + return _set_gpio_irq_type(gpio, type); +} + +#ifdef CONFIG_PM + +static int gpio_irq_set_wake(struct irq_data *d, unsigned value) +{ + int gpio = d->hwirq; + struct fh_gpio_chip *fh_gpio = irq_data_get_irq_chip_data(d); + + if (value) + fh_gpio->gpio_wakeups |= (1 << gpio); + else + fh_gpio->gpio_wakeups &= ~(1 << gpio); + + return 0; +} + +void fh_gpio_irq_suspend(void) +{ + fh_gpio0->gpio_backups = FH_GPIO_GetEnableInterrupts(fh_gpio0->base); + fh_gpio1->gpio_backups = FH_GPIO_GetEnableInterrupts(fh_gpio1->base); + + FH_GPIO_SetEnableInterrupts(fh_gpio0->base, fh_gpio0->gpio_wakeups); + FH_GPIO_SetEnableInterrupts(fh_gpio1->base, fh_gpio1->gpio_wakeups); +} + +void fh_gpio_irq_resume(void) +{ + FH_GPIO_SetEnableInterrupts(fh_gpio0->base, fh_gpio0->gpio_backups); + FH_GPIO_SetEnableInterrupts(fh_gpio1->base, fh_gpio1->gpio_backups); +} + +#else +#define gpio_irq_set_wake NULL +#endif + +static struct irq_chip gpio_irqchip = { + .name = "FH_GPIO_INTC", + .irq_ack = gpio_irq_ack, + .irq_enable = gpio_irq_enable, + .irq_disable = gpio_irq_disable, + .irq_mask = gpio_irq_mask, + .irq_unmask = gpio_irq_unmask, + .irq_set_type = gpio_irq_type, + .irq_set_wake = gpio_irq_set_wake, +}; + +static void gpio_toggle_trigger(unsigned int gpio, unsigned int offs) +{ + u32 int_polarity; + int gpio_num = gpio % 32; + void __iomem *base = gpio_to_base(gpio); + + if (FH_GPIO_GetValue(base, offs)) + int_polarity = GPIO_INT_POL_LOW; + else + int_polarity = GPIO_INT_POL_HIGH; + + FH_GPIO_SetInterruptPolarity(base, gpio_num, int_polarity); +} + +static void gpio_irq_handler(struct irq_desc *desc) +{ + struct irq_data *irqdata = irq_desc_get_irq_data(desc); + struct irq_chip *irqchip = irq_data_get_irq_chip(irqdata); + struct fh_gpio_chip *fh_gpio = irq_desc_get_handler_data(desc); + u32 irq_status; + int gpio_num; + + chained_irq_enter(irqchip, desc); + irq_status = FH_GPIO_GetInterruptStatus(fh_gpio->base); + + if (unlikely(irq_status == 0)) { + pr_err("gpio irq status is zero.\n"); + return; + } + + /* temporarily mask (level sensitive) parent IRQ */ + irqchip->irq_mask(irqdata); + + gpio_num = fls(irq_status) - 1; + + FH_GPIO_ClearInterrupt(fh_gpio->base, gpio_num); + + generic_handle_irq(irq_find_mapping(fh_gpio->irq_domain, gpio_num)); + + if ((irq_get_trigger_type(irq_find_mapping(fh_gpio->irq_domain, gpio_num)) & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) + if (!fh_gpio->type) + gpio_toggle_trigger((fh_gpio->chip.base + gpio_num), gpio_num); + + irqchip->irq_unmask(irqdata); + + chained_irq_exit(irqchip, desc); + /* now it may re-trigger */ +} + +/* +* This lock class tells lockdep that GPIO irqs are in a different +* category than their parents, so it won't report 0 recursion. +*/ +static struct lock_class_key gpio_lock_class; + +static int fh_gpio_irq_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) +{ + int ret; + + ret = irq_set_chip_data(irq, d->host_data); + if (ret < 0) + return ret; + irq_set_lockdep_class(irq, &gpio_lock_class); + irq_set_chip_and_handler(irq, &gpio_irqchip, handle_simple_irq); + irq_set_noprobe(irq); + + return 0; + +} + +static void fh_gpio_irq_unmap(struct irq_domain *d, unsigned int irq) +{ + irq_set_chip_and_handler(irq, NULL, NULL); + irq_set_chip_data(irq, NULL); +} + +static struct irq_domain_ops fh_gpio_irq_ops = { + .map = fh_gpio_irq_map, + .unmap = fh_gpio_irq_unmap, + .xlate = irq_domain_xlate_twocell, +}; + +static int fh_gpio_irq_create_domain(struct gpio_chip *c, unsigned offset) +{ + struct fh_gpio_chip *chip; + + chip = container_of(c, struct fh_gpio_chip, chip); + return irq_create_mapping(chip->irq_domain, offset); +} + +static int chip_to_irq(struct gpio_chip *c, unsigned offset) +{ + struct fh_gpio_chip *chip; + + chip = container_of(c, struct fh_gpio_chip, chip); + if (offset > chip->chip.ngpio) + return -ENXIO; + return irq_find_mapping(chip->irq_domain, offset); +} + +static int chip_gpio_get(struct gpio_chip *c, unsigned offset) +{ + u32 bit = offset % 32; + struct fh_gpio_chip *chip; + + chip = container_of(c, struct fh_gpio_chip, chip); + if (offset / 32) + return FH_GPIOB_GetValue(chip->base, bit); + else + return FH_GPIO_GetValue(chip->base, bit); +} + +static void chip_gpio_set(struct gpio_chip *c, unsigned int offset, int val) +{ + u32 bit = offset % 32; + struct fh_gpio_chip *chip; + + chip = container_of(c, struct fh_gpio_chip, chip); + if (offset / 32) + FH_GPIOB_SetValue(chip->base, bit, val); + else + FH_GPIO_SetValue(chip->base, bit, val); +} + +static int chip_direction_input(struct gpio_chip *c, unsigned offset) +{ + u32 bit = offset % 32; + unsigned long flags; + struct fh_gpio_chip *chip; + + chip = container_of(c, struct fh_gpio_chip, chip); + spin_lock_irqsave(&chip->lock, flags); + if (offset / 32) + FH_GPIOB_SetDirection(chip->base, bit, GPIO_DIR_INPUT); + else + FH_GPIO_SetDirection(chip->base, bit, GPIO_DIR_INPUT); + spin_unlock_irqrestore(&chip->lock, flags); + + return 0; +} + +static int chip_direction_output(struct gpio_chip *c, unsigned offset, int val) +{ + u32 bit = offset % 32; + unsigned long flags; + struct fh_gpio_chip *chip; + + chip = container_of(c, struct fh_gpio_chip, chip); + spin_lock_irqsave(&chip->lock, flags); + if (offset / 32) { + FH_GPIOB_SetDirection(chip->base, bit, GPIO_DIR_OUTPUT); + FH_GPIOB_SetValue(chip->base, bit, val); + } else { + FH_GPIO_SetDirection(chip->base, bit, GPIO_DIR_OUTPUT); + FH_GPIO_SetValue(chip->base, bit, val); + } + spin_unlock_irqrestore(&chip->lock, flags); + + return 0; +} + +static int chip_gpio_set_debounce(struct gpio_chip *c, unsigned offset, + unsigned int debounce) +{ + u32 bit = offset % 32; + unsigned long flags; + char db_clk_name[16] = {0}; + struct clk *gpio_clk = NULL; + int ret = 0; + struct fh_gpio_chip *chip; + bool enabled = !!debounce; + unsigned int clk_rate = 0; + + sprintf(db_clk_name, "gpio%d_gbclk", (offset / 32)); + gpio_clk = clk_get(NULL, db_clk_name); + if (IS_ERR(gpio_clk)) + return PTR_ERR(gpio_clk); + + clk_rate = 1000000UL / debounce; + + ret = clk_set_rate(gpio_clk, clk_rate); + if (ret) { + pr_err("Set GPIO Debounce Clk fail\n"); + return ret; + } + + ret = clk_prepare_enable(gpio_clk); + if (ret) { + pr_err("Set GPIO Debounce Clk fail\n"); + return ret; + } + + chip = container_of(c, struct fh_gpio_chip, chip); + spin_lock_irqsave(&chip->lock, flags); + FH_GPIO_EnableDebounce(chip->base, bit, enabled); + spin_unlock_irqrestore(&chip->lock, flags); + + return 0; +} + +void fh_gpio_set(int gpio_id, int value) +{ + __gpio_set_value(gpio_id, value); +} +EXPORT_SYMBOL(fh_gpio_set); + +int fh_gpio_get(int gpio_id, int *value) +{ + *value = __gpio_get_value(gpio_id); + return 0; +} +EXPORT_SYMBOL(fh_gpio_get); + +int fh_gpio_reset(int gpio_id) +{ + return 0; +} +EXPORT_SYMBOL(fh_gpio_reset); + +static void fh_gpio_irq_init(struct platform_device *pdev) +{ + int i, gpio_irq; + struct fh_gpio_chip *plat_data; + + plat_data = pdev->dev.platform_data; + + for (i = 0; i < 32; i++) { + gpio_irq = fh_gpio_irq_create_domain(&plat_data->chip, i); + irq_set_lockdep_class(gpio_irq, &gpio_lock_class); + irq_set_chip_and_handler(gpio_irq, &gpio_irqchip, handle_simple_irq); + irq_set_chip_data(gpio_irq, plat_data); + } + + irq_set_chained_handler_and_data(plat_data->irq, gpio_irq_handler, plat_data); +} + +static struct of_device_id const fh_gpio_of_match[] = { + { .compatible = "fh,fh-gpio" }, + {} +}; +MODULE_DEVICE_TABLE(of, fh_gpio_of_match); + +static int fh_gpio_probe(struct platform_device *pdev) +{ + int err = -EIO; + int id; + struct fh_gpio_chip *plat_data; +#ifdef CONFIG_OF + int ngpio; + const struct of_device_id *match; + struct device_node *np = pdev->dev.of_node; +#else + struct resource *res; +#endif + +#ifdef CONFIG_OF + match = of_match_device(fh_gpio_of_match, &pdev->dev); + if (!match) { + pr_info("Failed to find gpio controller\n"); + return -ENODEV; + } + + plat_data = devm_kzalloc(&pdev->dev, sizeof(*plat_data), GFP_KERNEL); + if (!plat_data) + return -ENOMEM; + + plat_data->chip.of_node = np; + /* set up the driver-specific struct */ + of_property_read_u32(np, "ngpio", &ngpio); + plat_data->chip.ngpio = ngpio; + of_property_read_u32(np, "base", &plat_data->chip.base); + of_property_read_u32(np, "id", &id); + of_property_read_u32(np, "trigger-type", &plat_data->type); + + plat_data->irq = irq_of_parse_and_map(np, 0); + if (plat_data->irq < 0) { + dev_err(&pdev->dev, "gpio interrupt is not available.\n"); + return plat_data->irq; + } + + plat_data->base = of_iomap(np, 0); + if (plat_data->base == NULL) { + err = -ENXIO; + goto release_irq; + } + + plat_data->irq_domain = irq_domain_add_linear(np, plat_data->chip.ngpio, &fh_gpio_irq_ops, plat_data); + + if (!plat_data->irq_domain) { + dev_err(&pdev->dev, "Couldn't allocate IRQ domain\n"); + err = -ENXIO; + goto release_io; + } +#else + plat_data = pdev->dev.platform_data; + + id = pdev->id; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "can't fetch device resource info\n"); + return err; + } + + plat_data->irq = irq_create_mapping(NULL, platform_get_irq(pdev, 0)); + if (plat_data->irq < 0) { + dev_err(&pdev->dev, "gpio interrupt is not available.\n"); + return plat_data->irq; + } + + plat_data->base = ioremap(res->start, resource_size(res)); + if (plat_data->base == NULL) { + err = -ENXIO; + goto release_irq; + } + + plat_data->irq_domain = irq_domain_add_linear(NULL, + plat_data->chip.ngpio, &fh_gpio_irq_ops, plat_data); + + if (!plat_data->irq_domain) { + dev_err(&pdev->dev, "Couldn't allocate IRQ domain\n"); + err = -ENXIO; + goto release_io; + } +#endif + + plat_data->chip.direction_input = chip_direction_input; + plat_data->chip.direction_output = chip_direction_output; + plat_data->chip.get = chip_gpio_get; + plat_data->chip.set = chip_gpio_set; + plat_data->chip.to_irq = chip_to_irq; + plat_data->chip.set_debounce = chip_gpio_set_debounce; + + switch (id) { + case 0: + fh_gpio0 = plat_data; + plat_data->chip.names = NULL; + break; + case 1: + fh_gpio1 = plat_data; + plat_data->chip.names = NULL; + break; + case 2: + fh_gpio2 = plat_data; + plat_data->chip.names = NULL; + break; + case 3: + fh_gpio3 = plat_data; + plat_data->chip.names = NULL; + break; + default: + dev_err(&pdev->dev, "Unknown GPIO Controller\n"); + err = -ENXIO; + goto release_domain; + } + + plat_data->pdev = pdev; + spin_lock_init(&plat_data->lock); + pdev->dev.platform_data = plat_data; + /* finally, register with the generic GPIO API */ + err = gpiochip_add(&plat_data->chip); + if (err) { + pr_err("GPIO support load fail.\n"); + goto release_domain; + } + + fh_gpio_irq_init(pdev); + pr_debug("GPIO support successfully loaded.\n\tBase Addr: 0x%p\n", + plat_data->base); + + return 0; + +release_domain: + irq_domain_remove(plat_data->irq_domain); +release_io: + iounmap(plat_data->base); +release_irq: + irq_dispose_mapping(plat_data->irq); + free_irq(plat_data->irq, plat_data); + + return err; +} + +static int fh_gpio_remove(struct platform_device *pdev) +{ + struct fh_gpio_chip *plat_data; + + plat_data = pdev->dev.platform_data; + + gpiochip_remove(&plat_data->chip); + irq_domain_remove(plat_data->irq_domain); + iounmap(plat_data->base); + + return 0; +} + +static struct platform_driver fh_gpio_driver = { + .driver = { + .name = GPIO_NAME, + .owner = THIS_MODULE, + .of_match_table = fh_gpio_of_match, + }, + .probe = fh_gpio_probe, + .remove = fh_gpio_remove, +}; + +static int __init fh_gpio_init(void) +{ + return platform_driver_register(&fh_gpio_driver); +} + +static void __exit fh_gpio_exit(void) +{ + platform_driver_unregister(&fh_gpio_driver); +} + +module_init(fh_gpio_init); +module_exit(fh_gpio_exit); + +MODULE_AUTHOR("QIN"); +MODULE_DESCRIPTION("Fullhan GPIO device driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform: FH"); diff --git a/drivers/gpio/gpiolib-sysfs.c b/drivers/gpio/gpiolib-sysfs.c index 4b44dd97..435ca2e6 100644 --- a/drivers/gpio/gpiolib-sysfs.c +++ b/drivers/gpio/gpiolib-sysfs.c @@ -609,7 +609,7 @@ int gpiod_export(struct gpio_desc *desc, bool direction_may_change) dev = device_create_with_groups(&gpio_class, &gdev->dev, MKDEV(0, 0), data, gpio_groups, - ioname ? ioname : "gpio%u", + ioname ? ioname : "GPIO%u", desc_to_gpio(desc)); if (IS_ERR(dev)) { status = PTR_ERR(dev); diff --git a/drivers/hid/Makefile b/drivers/hid/Makefile index 86b2b578..b126285c 100644 --- a/drivers/hid/Makefile +++ b/drivers/hid/Makefile @@ -1,7 +1,7 @@ # # Makefile for the HID driver # -hid-y := hid-core.o hid-input.o +hid-$(CONFIG_HID) := hid-core.o hid-input.o hid-$(CONFIG_DEBUG_FS) += hid-debug.o obj-$(CONFIG_HID) += hid.o diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index d252276f..83e148c1 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -343,6 +343,16 @@ config I2C_AT91 the latency to fill the transmission register is too long. If you are facing this situation, use the i2c-gpio driver. +config I2C_FH_INTERRUPT + tristate "FH I2C Driver with Interrupt" + help + This supports the use of the I2C interface on Fullhan + processors. + + Only master mode is supported. + + This driver can also be built as a module. If so, the module + will be called config I2C_AU1550 tristate "Au1550/Au1200/Au1300 SMBus interface" depends on MIPS_ALCHEMY diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 29764cc2..fe3c73e8 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -121,5 +121,6 @@ obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o obj-$(CONFIG_I2C_XGENE_SLIMPRO) += i2c-xgene-slimpro.o obj-$(CONFIG_SCx200_ACB) += scx200_acb.o +obj-$(CONFIG_I2C_FH_INTERRUPT) += i2c_fh_interrupt.o ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG diff --git a/drivers/i2c/busses/i2c_fh_interrupt.c b/drivers/i2c/busses/i2c_fh_interrupt.c new file mode 100644 index 00000000..ee0b620c --- /dev/null +++ b/drivers/i2c/busses/i2c_fh_interrupt.c @@ -0,0 +1,1072 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* #define FH_I2C_DEBUG */ + +#ifdef FH_I2C_DEBUG +#define PRINT_DBG(fmt, args...) printk(fmt, ## args) +#else +#define PRINT_DBG(fmt, args...) do { } while (0) +#endif + +/* + * Registers offset + */ +/*I2C*/ +#define REG_I2C_CON (0x0000) +#define REG_I2C_TAR (0x0004) +#define REG_I2C_SAR (0x0008) +#define REG_I2C_HS_MADDR (0x000C) +#define REG_I2C_DATA_CMD (0x0010) +#define REG_I2C_SS_SCL_HCNT (0x0014) +#define REG_I2C_SS_SCL_LCNT (0x0018) +#define REG_I2C_FS_SCL_HCNT (0x001C) +#define REG_I2C_FS_SCL_LCNT (0x0020) +#define REG_I2C_HS_SCL_HCNT (0x0024) +#define REG_I2C_HS_SCL_LCNT (0x0028) +#define REG_I2C_INTR_STAT (0x002c) +#define REG_I2C_INTR_MASK (0x0030) +#define REG_I2C_RAW_INTR_STAT (0x0034) +#define REG_I2C_RX_TL (0x0038) +#define REG_I2C_TX_TL (0x003c) +#define REG_I2C_CLR_INTR (0x0040) +#define REG_I2C_ENABLE (0x006c) +#define REG_I2C_STATUS (0x0070) +#define REG_I2C_TXFLR (0x0074) +#define REG_I2C_RXFLR (0x0078) +#define REG_I2C_DMA_CR (0x0088) +#define REG_I2C_DMA_TDLR (0x008c) +#define REG_I2C_DMA_RDLR (0x0090) + +#define DW_IC_INTR_NONE 0x0 + +#define DW_IC_CON 0x0 +#define DW_IC_TAR 0x4 +#define DW_IC_DATA_CMD 0x10 +#define DW_IC_SS_SCL_HCNT 0x14 +#define DW_IC_SS_SCL_LCNT 0x18 +#define DW_IC_FS_SCL_HCNT 0x1c +#define DW_IC_FS_SCL_LCNT 0x20 +#define DW_IC_INTR_STAT 0x2c +#define DW_IC_INTR_MASK 0x30 +#define DW_IC_RAW_INTR_STAT 0x34 +#define DW_IC_RX_TL 0x38 +#define DW_IC_TX_TL 0x3c +#define DW_IC_CLR_INTR 0x40 +#define DW_IC_CLR_RX_UNDER 0x44 +#define DW_IC_CLR_RX_OVER 0x48 +#define DW_IC_CLR_TX_OVER 0x4c +#define DW_IC_CLR_RD_REQ 0x50 +#define DW_IC_CLR_TX_ABRT 0x54 +#define DW_IC_CLR_RX_DONE 0x58 +#define DW_IC_CLR_ACTIVITY 0x5c +#define DW_IC_CLR_STOP_DET 0x60 +#define DW_IC_CLR_START_DET 0x64 +#define DW_IC_CLR_GEN_CALL 0x68 +#define DW_IC_ENABLE 0x6c +#define DW_IC_STATUS 0x70 +#define DW_IC_TXFLR 0x74 +#define DW_IC_RXFLR 0x78 +#define DW_IC_COMP_PARAM_1 0xf4 +#define DW_IC_TX_ABRT_SOURCE 0x80 + +#define DW_IC_CON_MASTER 0x1 +#define DW_IC_CON_SPEED_STD 0x2 +#define DW_IC_CON_SPEED_FAST 0x4 +#define DW_IC_CON_10BITADDR_MASTER 0x10 +#define DW_IC_CON_RESTART_EN 0x20 +#define DW_IC_CON_SLAVE_DISABLE 0x40 + +#define DW_IC_INTR_RX_UNDER 0x001 +#define DW_IC_INTR_RX_OVER 0x002 +#define DW_IC_INTR_RX_FULL 0x004 +#define DW_IC_INTR_TX_OVER 0x008 +#define DW_IC_INTR_TX_EMPTY 0x010 +#define DW_IC_INTR_RD_REQ 0x020 +#define DW_IC_INTR_TX_ABRT 0x040 +#define DW_IC_INTR_RX_DONE 0x080 +#define DW_IC_INTR_ACTIVITY 0x100 +#define DW_IC_INTR_STOP_DET 0x200 +#define DW_IC_INTR_START_DET 0x400 +#define DW_IC_INTR_GEN_CALL 0x800 + +#define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \ + DW_IC_INTR_TX_EMPTY | \ + DW_IC_INTR_TX_ABRT | \ + DW_IC_INTR_STOP_DET) + +#define DW_IC_STATUS_ACTIVITY 0x1 +#define DW_IC_STATUS_MASTER_ACTIVITY 0x20 + +#define DW_IC_ERR_TX_ABRT 0x1 + +/* + * status codes + */ +#define STATUS_IDLE 0x0 +#define STATUS_WRITE_IN_PROGRESS 0x1 +#define STATUS_READ_IN_PROGRESS 0x2 + +#define TIMEOUT 20 /* ms */ + +/* + * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register + * + * only expected abort codes are listed here + * refer to the datasheet for the full list + */ +#define ABRT_7B_ADDR_NOACK 0 +#define ABRT_10ADDR1_NOACK 1 +#define ABRT_10ADDR2_NOACK 2 +#define ABRT_TXDATA_NOACK 3 +#define ABRT_GCALL_NOACK 4 +#define ABRT_GCALL_READ 5 +#define ABRT_SBYTE_ACKDET 7 +#define ABRT_SBYTE_NORSTRT 9 +#define ABRT_10B_RD_NORSTRT 10 +#define ABRT_MASTER_DIS 11 +#define ARB_LOST 12 + +#define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK) +#define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK) +#define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK) +#define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK) +#define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK) +#define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ) +#define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET) +#define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT) +#define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT) +#define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS) +#define DW_IC_TX_ARB_LOST (1UL << ARB_LOST) + +#define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \ + DW_IC_TX_ABRT_10ADDR1_NOACK | \ + DW_IC_TX_ABRT_10ADDR2_NOACK | \ + DW_IC_TX_ABRT_TXDATA_NOACK | \ + DW_IC_TX_ABRT_GCALL_NOACK) + +static char *abort_sources[] = { + [ABRT_7B_ADDR_NOACK] = + "slave address not acknowledged (7bit mode)", + [ABRT_10ADDR1_NOACK] = + "first address byte not acknowledged (10bit mode)", + [ABRT_10ADDR2_NOACK] = + "second address byte not acknowledged (10bit mode)", + [ABRT_TXDATA_NOACK] = + "data not acknowledged", + [ABRT_GCALL_NOACK] = + "no acknowledgement for a general call", + [ABRT_GCALL_READ] = + "read after general call", + [ABRT_SBYTE_ACKDET] = + "start byte acknowledged", + [ABRT_SBYTE_NORSTRT] = + "trying to send start byte when restart is disabled", + [ABRT_10B_RD_NORSTRT] = + "trying to read when restart is disabled (10bit mode)", + [ABRT_MASTER_DIS] = + "trying to use disabled adapter", + [ARB_LOST] = + "lost arbitration", +}; + +enum BUS_STATUS { + I2C_BUSY, + I2C_IDLE +}; +enum RESULT { + SUCCESS, + FAILURE +}; +enum ENABLE_SET { + DISABLE, + ENABLE +}; +enum SPEED_MODE { + SSPEED = 1, + FSPEED = 2, + HSPEED = 3, +}; + +/* function Macro */ +#define I2C_GetTransmitFifoLevel(base_addr) (readl(base_addr + \ + REG_I2C_TXFLR)) + +#define I2c_GetTxFifoDepth(base_addr) (((readl(base_addr + \ + DW_IC_COMP_PARAM_1)>>16) & 0xff) + 1) + +#define I2c_GetRxFifoDepth(base_addr) (((readl(base_addr + \ + DW_IC_COMP_PARAM_1)>>8) & 0xff) + 1) + +#define I2c_SetDeviceId(base_addr, deviceID) writel(deviceID,\ + base_addr + REG_I2C_TAR) /* set IIC slave address */ + +#define I2c_Read(base_addr) (readl(base_addr + REG_I2C_DATA_CMD)&0xff) + +#define I2c_SetSsHcnt(base_addr, hcnt) writel(hcnt,\ + base_addr + DW_IC_SS_SCL_HCNT) + +#define I2c_SetSsLcnt(base_addr, lcnt) writel(lcnt,\ + base_addr + DW_IC_SS_SCL_LCNT) + +#define I2c_SetFsHcnt(base_addr, hcnt) writel(hcnt,\ + base_addr + DW_IC_FS_SCL_HCNT) + +#define I2c_SetFsLcnt(base_addr, lcnt) writel(lcnt,\ + base_addr + DW_IC_FS_SCL_LCNT) + +#define I2c_DisEnable(base_addr) writel(DISABLE, base_addr + REG_I2C_ENABLE) + +#define I2c_Enable(base_addr) writel(ENABLE, base_addr + REG_I2C_ENABLE) + +#define I2c_Write(base_addr, data) writel(data, base_addr + REG_I2C_DATA_CMD) + +#define I2c_GetTxTl(base_addr) (readl(base_addr + REG_I2C_TX_TL)&0xff) + +#define I2c_GetRxTl(base_addr) (readl(base_addr + REG_I2C_RX_TL)&0xff) + +#define I2c_GetRxFLR(base_addr) (readl(base_addr + DW_IC_RXFLR)&0xff) + +#define I2c_GetTxFLR(base_addr) (readl(base_addr + DW_IC_TXFLR)&0xff) + +#define I2c_SetTxRxTl(base_addr, txtl, rxtl) do {\ + writel(txtl, base_addr + REG_I2C_TX_TL); \ + writel(rxtl, base_addr + REG_I2C_RX_TL); \ + } while (0) + +#define I2c_IsActiveMst(base_addr) (readl(base_addr + REG_I2C_STATUS)>>5 & 1) + +#define I2c_SetCon(base_addr, config) writel(config, base_addr + REG_I2C_CON) + +#define I2c_GetCon(base_addr) readl(base_addr + REG_I2C_CON) + +#define I2c_Status(base_addr) readl(base_addr + REG_I2C_STATUS) + +#define I2c_SetTar(base_addr, id) writel(id, base_addr + REG_I2C_TAR) + +#define I2c_SetIntrMask(base_addr, mask) writel(mask,\ + base_addr + REG_I2C_INTR_MASK) + +#define I2c_ClrIntr(base_addr, mask) readl(base_addr + mask) + +#define I2c_GetTxAbrtSource(base_addr) readl(base_addr + DW_IC_TX_ABRT_SOURCE) + +#define I2c_TxEmpty(base_addr) (readl(base_addr +\ + REG_I2C_RAW_INTR_STAT) & M_TX_EMPTY) + +#define I2c_RxFull(base_addr) (readl(base_addr +\ + REG_I2C_RAW_INTR_STAT) & M_RX_FULL) + +#define I2c_RxEmpty(base_addr) (readl(base_addr +\ + REG_I2C_RAW_INTR_STAT) & M_RX_OVER) + +/* register define */ +union { + struct { + unsigned int MASTER_MODE : 1; + unsigned int SPEED : 2; + unsigned int IC_10BITADDR_SLAVE : 1; + unsigned int IC_10BITADDR_MASTER : 1; + unsigned int IC_RESTART_EN : 1; + unsigned int IC_SLAVE_DISABLE : 1; + unsigned int reserved_31_7 : 25; + } x; + unsigned int dw; +} Reg_I2c_Con; + +/** + * struct fh_i2c_dev - private i2c-designware data + * @dev: driver model device node + * @base: IO registers pointer + * @cmd_complete: tx completion indicator + * @lock: protect this struct and IO registers + * @clk: input reference clock + * @cmd_err: run time hadware error code + * @msgs: points to an array of messages currently being transferred + * @msgs_num: the number of elements in msgs + * @msg_write_idx: the element index of the current tx message in the msgs + * array + * @tx_buf_len: the length of the current tx buffer + * @tx_buf: the current tx buffer + * @msg_read_idx: the element index of the current rx message in the msgs + * array + * @rx_buf_len: the length of the current rx buffer + * @rx_buf: the current rx buffer + * @msg_err: error status of the current transfer + * @status: i2c master status, one of STATUS_* + * @abort_source: copy of the TX_ABRT_SOURCE register + * @irq: interrupt number for the i2c master + * @adapter: i2c subsystem adapter node + * @tx_fifo_depth: depth of the hardware tx fifo + * @rx_fifo_depth: depth of the hardware rx fifo + */ +struct fh_i2c_dev { + struct device *dev; + void __iomem *base; + struct completion cmd_complete; + struct mutex lock; + struct clk *clk; + int cmd_err; + struct i2c_msg *msgs; + int msgs_num; + int msg_write_idx; + u32 tx_buf_len; + u8 *tx_buf; + int msg_read_idx; + u32 rx_buf_len; + u8 *rx_buf; + int msg_err; + unsigned int status; + u32 abort_source; + int irq; + struct i2c_adapter adapter; + unsigned int tx_fifo_depth; + unsigned int rx_fifo_depth; + char isrname[24]; +}; + + +static int i2c_fh_wait_master_not_active(struct fh_i2c_dev *dev) +{ + int timeout = 200; /* 2000 us */ + + while (I2c_IsActiveMst(dev->base)) { + if (timeout <= 0) { + dev_warn(dev->dev, "timeout waiting for master not active\n"); + return -ETIMEDOUT; + } + timeout--; + udelay(10); + } + + return 0; +} + +static u32 +i2c_fh_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset) +{ + /* + * DesignWare I2C core doesn't seem to have solid strategy to meet + * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec + * will result in violation of the tHD;STA spec. + */ + u32 ret = 0; + + if (cond) + /* + * Conditional expression: + * + * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH + * + * This is based on the DW manuals, and represents an ideal + * configuration. The resulting I2C bus speed will be + * faster than any of the others. + * + * If your hardware is free from tHD;STA issue, try this one. + */ + ret = (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset; + else + /* + * Conditional expression: + * + * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf) + * + * This is just experimental rule; the tHD;STA period turned + * out to be proportinal to (_HCNT + 3). With this setting, + * we could meet both tHIGH and tHD;STA timing specs. + * + * If unsure, you'd better to take this alternative. + * + * The reason why we need to take into account "tf" here, + * is the same as described in i2c_fh_scl_lcnt(). + */ + ret = (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset; + return ret; +} + +static u32 i2c_fh_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset) +{ + /* + * Conditional expression: + * + * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf) + * + * DW I2C core starts counting the SCL CNTs for the LOW period + * of the SCL clock (tLOW) as soon as it pulls the SCL line. + * In order to meet the tLOW timing spec, we need to take into + * account the fall time of SCL signal (tf). Default tf value + * should be 0.3 us, for safety. + */ + return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset; +} + +/** + * i2c_fh_init() - initialize the designware i2c master hardware + * @dev: device private data + * + * This functions configures and enables the I2C master. + * This function is called during I2C init function, and in case of timeout at + * run time. + */ +static void i2c_fh_init(struct fh_i2c_dev *dev) +{ + u32 input_clock_khz = clk_get_rate(dev->clk) / 1000; + u32 ic_con, hcnt, lcnt; + + /* Disable the adapter */ + i2c_fh_wait_master_not_active(dev); + I2c_DisEnable(dev->base); + + /* set standard and fast speed deviders for high/low periods */ + + /* Standard-mode */ + + hcnt = i2c_fh_scl_hcnt(input_clock_khz, + 40, /* tHD;STA = tHIGH = 4.0 us */ + 3, /* tf = 0.3 us */ + 0, /* 0: DW default, 1: Ideal */ + 0); /* No offset */ + lcnt = i2c_fh_scl_lcnt(input_clock_khz, + 47, /* tLOW = 4.7 us */ + 3, /* tf = 0.3 us */ + 0); /* No offset */ + I2c_SetSsHcnt(dev->base, hcnt); + I2c_SetSsLcnt(dev->base, lcnt); + /* pr_info("\tClock: %dkhz, Standard-mode HCNT:LCNT = %d:%d\n", */ + /* input_clock_khz, hcnt, lcnt); */ + + /* Fast-mode */ + hcnt = i2c_fh_scl_hcnt(input_clock_khz, + 6, /* tHD;STA = tHIGH = 0.6 us */ + 3, /* tf = 0.3 us */ + 0, /* 0: DW default, 1: Ideal */ + 0); /* No offset */ + lcnt = i2c_fh_scl_lcnt(input_clock_khz, + 13, /* tLOW = 1.3 us */ + 3, /* tf = 0.3 us */ + 0); /* No offset */ + I2c_SetFsHcnt(dev->base, hcnt); + I2c_SetFsLcnt(dev->base, lcnt); + /* dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); */ + + /* Configure Tx/Rx FIFO threshold levels */ + + I2c_SetTxRxTl(dev->base, dev->tx_fifo_depth - 1, 0); + /* configure the i2c master */ + ic_con = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | + DW_IC_CON_RESTART_EN | DW_IC_CON_SPEED_FAST; + I2c_SetCon(dev->base, ic_con); + +} + +/* + * Waiting for bus not busy + */ +static int i2c_fh_wait_bus_not_busy(struct fh_i2c_dev *dev) +{ + int timeout = TIMEOUT; + + while (I2c_IsActiveMst(dev->base)) { + if (timeout <= 0) { + dev_warn(dev->dev, "timeout waiting for bus ready\n"); + return -ETIMEDOUT; + } + timeout--; + /* msleep(1); */ + usleep_range(100, 1000); + } + + return 0; +} + +static void i2c_fh_xfer_init(struct fh_i2c_dev *dev) +{ + struct i2c_msg *msgs = dev->msgs; + u32 ic_con; + + /* Disable the adapter */ + i2c_fh_wait_master_not_active(dev); + I2c_DisEnable(dev->base); + + /* set the slave (target) address */ + I2c_SetDeviceId(dev->base, msgs[dev->msg_write_idx].addr); + + /* if the slave address is ten bit address, enable 10BITADDR */ + ic_con = I2c_GetCon(dev->base); + if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) + ic_con |= DW_IC_CON_10BITADDR_MASTER; + else + ic_con &= ~DW_IC_CON_10BITADDR_MASTER; + I2c_SetCon(dev->base, ic_con); + + /* Enable the adapter */ + I2c_Enable(dev->base); + + /* Enable interrupts */ + I2c_SetIntrMask(dev->base, DW_IC_INTR_DEFAULT_MASK); + +} + +/* + * Initiate (and continue) low level master read/write transaction. + * This function is only called from i2c_fh_isr, and pumping i2c_msg + * messages into the tx buffer. Even if the size of i2c_msg data is + * longer than the size of the tx buffer, it handles everything. + */ +static void +i2c_fh_xfer_msg(struct fh_i2c_dev *dev) +{ + struct i2c_msg *msgs = dev->msgs; + u32 intr_mask, cmd; + int tx_limit, rx_limit; + u32 addr = msgs[dev->msg_write_idx].addr; + u32 buf_len = dev->tx_buf_len; + u8 *buf = dev->tx_buf; + + PRINT_DBG("i2c_fh_xfer_msg start, dev->msgs_num: %d\n", dev->msgs_num); + + intr_mask = DW_IC_INTR_DEFAULT_MASK; + + for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { + /* + * if target address has changed, we need to + * reprogram the target address in the i2c + * adapter when we are done with this transfer + */ + if (msgs[dev->msg_write_idx].addr != addr) { + dev_err(dev->dev, + "%s: invalid target address\n", __func__); + dev->msg_err = -EINVAL; + break; + } + + if (msgs[dev->msg_write_idx].len == 0) { + dev_err(dev->dev, + "%s: invalid message length\n", __func__); + dev->msg_err = -EINVAL; + break; + } + + if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { + /* new i2c_msg */ + buf = msgs[dev->msg_write_idx].buf; + buf_len = msgs[dev->msg_write_idx].len; + + PRINT_DBG("new msg: len: %d, buf: 0x%x\n", + buf_len, buf[0]); + } + + tx_limit = dev->tx_fifo_depth - I2c_GetTxTl(dev->base); + rx_limit = dev->rx_fifo_depth - I2c_GetRxTl(dev->base); + + while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) { + if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { + cmd = 0x100; + rx_limit--; + } else { + cmd = *buf++; + } + + tx_limit--; buf_len--; + + if (!buf_len && + ((dev->msg_write_idx == dev->msgs_num - 1) || + (msgs[dev->msg_write_idx].flags & + I2C_M_STOP))) { + /* 2015-11-8 ar0130 bug fixed */ + /* 20*1000 about 2 *0.1 ms */ + /* (for i2c send one byte @ 100KHz) */ + /* fixme: define MACRO get timeout value; */ + unsigned int _timeout = 20000; + + while (I2C_GetTransmitFifoLevel(dev->base) && + _timeout--) + ; + cmd |= 0x200; + } + + I2c_Write(dev->base, cmd); + } + PRINT_DBG("\n"); + + dev->tx_buf = buf; + dev->tx_buf_len = buf_len; + + if (buf_len == 0) { + dev->status &= ~STATUS_WRITE_IN_PROGRESS; + } else { + /* more bytes to be written */ + dev->status |= STATUS_WRITE_IN_PROGRESS; + break; + } + } + + /* + * If i2c_msg index search is completed, we don't need TX_EMPTY + * interrupt any more. + */ + + if (dev->msg_write_idx == dev->msgs_num) + intr_mask &= ~DW_IC_INTR_TX_EMPTY; + + if (dev->msg_err) + intr_mask = 0; + + I2c_SetIntrMask(dev->base, intr_mask); + +} + +static void +i2c_fh_read(struct fh_i2c_dev *dev) +{ + struct i2c_msg *msgs = dev->msgs; + int rx_valid; + + for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { + u32 len; + u8 *buf; + + if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) + continue; + + if (!(dev->status & STATUS_READ_IN_PROGRESS)) { + len = msgs[dev->msg_read_idx].len; + buf = msgs[dev->msg_read_idx].buf; + } else { + PRINT_DBG("STATUS_READ_IN_PROGRESS\n"); + len = dev->rx_buf_len; + buf = dev->rx_buf; + } + + rx_valid = I2c_GetRxFLR(dev->base); + + if (rx_valid == 0) + PRINT_DBG("rx_valid == 0\n"); + + for (; len > 0 && rx_valid > 0; len--, rx_valid--) + *buf++ = I2c_Read(dev->base); + + PRINT_DBG("i2c_fh_read, len: %d, buf[0]: 0x%x\n", + msgs[dev->msg_read_idx].len, + msgs[dev->msg_read_idx].buf[0]); + + if (len == 0) { + dev->status &= ~STATUS_READ_IN_PROGRESS; + } else { + PRINT_DBG("len > 0\n"); + dev->status |= STATUS_READ_IN_PROGRESS; + dev->rx_buf_len = len; + dev->rx_buf = buf; + return; + } + } +} + +static int i2c_fh_handle_tx_abort(struct fh_i2c_dev *dev) +{ + unsigned long abort_source = dev->abort_source; + int i; + + if (abort_source & DW_IC_TX_ABRT_NOACK) { + for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) { + pr_err( + "%s: %s\n", __func__, abort_sources[i]); + } + return -EREMOTEIO; + } + + for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) + pr_err("%s: %s\n", __func__, abort_sources[i]); + + if (abort_source & DW_IC_TX_ARB_LOST) + return -EAGAIN; + else if (abort_source & DW_IC_TX_ABRT_GCALL_READ) + return -EINVAL; /* wrong msgs[] data */ + else + return -EIO; +} + +/* + * Prepare controller for a transaction and call i2c_fh_xfer_msg + */ +static int +i2c_fh_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) +{ + struct fh_i2c_dev *dev = i2c_get_adapdata(adap); + int ret; + + PRINT_DBG("-------i2c, %s: msgs: %d\n", __func__, num); + + mutex_lock(&dev->lock); + + reinit_completion(&dev->cmd_complete); + dev->msgs = msgs; + dev->msgs_num = num; + dev->cmd_err = 0; + dev->msg_write_idx = 0; + dev->msg_read_idx = 0; + dev->msg_err = 0; + dev->status = STATUS_IDLE; + dev->abort_source = 0; + + ret = i2c_fh_wait_bus_not_busy(dev); + if (ret < 0) + goto done; + + + /* start the transfers */ + i2c_fh_xfer_init(dev); + + /* wait for tx to complete */ + ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, HZ); + + if (ret == 0) { + dev_err(dev->dev, "controller timed out\n"); + i2c_fh_init(dev); + ret = -ETIMEDOUT; + goto done; + } else if (ret < 0) + goto done; + + if (dev->msg_err) { + PRINT_DBG("dev->msg_err\n"); + ret = dev->msg_err; + goto done; + } + + /* no error */ + if (likely(!dev->cmd_err)) { + /* Disable the adapter */ + i2c_fh_wait_master_not_active(dev); + I2c_DisEnable(dev->base); + ret = num; + goto done; + } + + /* We have an error */ + if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { + PRINT_DBG("dev->cmd_err == DW_IC_ERR_TX_ABRT\n"); + ret = i2c_fh_handle_tx_abort(dev); + goto done; + } + + ret = -EIO; + +done: + PRINT_DBG("buf: 0x%x\n", dev->msgs[num - 1].buf[0]); + mutex_unlock(&dev->lock); + + return ret; +} + +static u32 i2c_fh_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | + I2C_FUNC_SMBUS_BYTE | + I2C_FUNC_SMBUS_BYTE_DATA | + I2C_FUNC_SMBUS_WORD_DATA | + I2C_FUNC_SMBUS_I2C_BLOCK; +} + +static u32 i2c_fh_read_clear_intrbits(struct fh_i2c_dev *dev) +{ + u32 stat; + + /* + * The IC_INTR_STAT register just indicates "enabled" interrupts. + * Ths unmasked raw version of interrupt status bits are available + * in the IC_RAW_INTR_STAT register. + * + * That is, + * stat = readl(IC_INTR_STAT); + * equals to, + * stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK); + * + * The raw version might be useful for debugging purposes. + */ + stat = readl(dev->base + DW_IC_INTR_STAT); + + /* + * Do not use the IC_CLR_INTR register to clear interrupts, or + * you'll miss some interrupts, triggered during the period from + * readl(IC_INTR_STAT) to readl(IC_CLR_INTR). + * + * Instead, use the separately-prepared IC_CLR_* registers. + */ + if (stat & DW_IC_INTR_RX_UNDER) + I2c_ClrIntr(dev->base, DW_IC_CLR_RX_UNDER); + if (stat & DW_IC_INTR_RX_OVER) + I2c_ClrIntr(dev->base, DW_IC_CLR_RX_OVER); + if (stat & DW_IC_INTR_TX_OVER) + I2c_ClrIntr(dev->base, DW_IC_CLR_TX_OVER); + if (stat & DW_IC_INTR_RD_REQ) + I2c_ClrIntr(dev->base, DW_IC_CLR_RD_REQ); + if (stat & DW_IC_INTR_TX_ABRT) { + /* + * The IC_TX_ABRT_SOURCE register is cleared whenever + * the IC_CLR_TX_ABRT is read. Preserve it beforehand. + */ + dev->abort_source = readl(dev->base + DW_IC_TX_ABRT_SOURCE); + I2c_ClrIntr(dev->base, DW_IC_CLR_TX_ABRT); + } + if (stat & DW_IC_INTR_RX_DONE) + I2c_ClrIntr(dev->base, DW_IC_CLR_RX_DONE); + if (stat & DW_IC_INTR_ACTIVITY) + I2c_ClrIntr(dev->base, DW_IC_CLR_ACTIVITY); + if (stat & DW_IC_INTR_STOP_DET) + I2c_ClrIntr(dev->base, DW_IC_CLR_STOP_DET); + if (stat & DW_IC_INTR_START_DET) + I2c_ClrIntr(dev->base, DW_IC_CLR_START_DET); + if (stat & DW_IC_INTR_GEN_CALL) + I2c_ClrIntr(dev->base, DW_IC_CLR_GEN_CALL); + + return stat; +} + +/* + * Interrupt service routine. This gets called whenever an I2C interrupt + * occurs. + */ +static irqreturn_t i2c_fh_isr(int this_irq, void *dev_id) +{ + struct fh_i2c_dev *dev = dev_id; + u32 stat; + + stat = i2c_fh_read_clear_intrbits(dev); + PRINT_DBG("-----------i2c, %s: stat=0x%x\n", __func__, stat); + if (stat & DW_IC_INTR_TX_ABRT) { + PRINT_DBG("DW_IC_INTR_TX_ABRT\n"); + dev->cmd_err |= DW_IC_ERR_TX_ABRT; + dev->status = STATUS_IDLE; + + /* + * Anytime TX_ABRT is set, the contents of the tx/rx + * buffers are flushed. Make sure to skip them. + */ + I2c_SetIntrMask(dev->base, DW_IC_INTR_NONE); + goto tx_aborted; + } + + if (stat & DW_IC_INTR_RX_FULL) { + PRINT_DBG("i2c_fh_read\n"); + i2c_fh_read(dev); + } + + if (stat & DW_IC_INTR_TX_EMPTY) { + PRINT_DBG("i2c_fh_xfer_msg\n"); + i2c_fh_xfer_msg(dev); + } + + /* + * No need to modify or disable the interrupt mask here. + * i2c_fh_xfer_msg() will take care of it according to + * the current transmit status. + */ + +tx_aborted: + if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) + complete(&dev->cmd_complete); + + return IRQ_HANDLED; +} + +static struct i2c_algorithm i2c_fh_algo = { + .master_xfer = i2c_fh_xfer, + .functionality = i2c_fh_func, +}; + + +static int __init fh_i2c_probe(struct platform_device *pdev) +{ + struct fh_i2c_dev *dev; + struct i2c_adapter *adap; + int r; +#ifdef CONFIG_USE_OF + struct device_node *np = pdev->dev.of_node; +#else + struct resource *mem; +#endif + + int id = 0; + char clkname[24] = {0}; + int err = 0; + + + pr_info("I2C driver:\n\tplatform registration... "); + + + /* NOTE: driver uses the static register mapping */ + dev = kzalloc(sizeof(struct fh_i2c_dev), GFP_KERNEL); + if (!dev) { + r = -ENOMEM; + goto err_return; + } +#ifdef CONFIG_USE_OF + id = of_alias_get_id(pdev->dev.of_node, "i2c"); +#else + id = pdev->id; +#endif + + snprintf(clkname, sizeof(clkname), "i2c%d_clk", id); + dev->clk = clk_get(NULL, clkname); + snprintf(dev->isrname, sizeof(dev->isrname), "i2c-%d", id); + + if (IS_ERR(dev->clk)) { + r = -ENODEV; + goto err_free_mem; + } + clk_prepare_enable(dev->clk); + + init_completion(&dev->cmd_complete); + mutex_init(&dev->lock); + dev->dev = get_device(&pdev->dev); + platform_set_drvdata(pdev, dev); + +#ifdef CONFIG_USE_OF + dev->base = of_iomap(np, 0); + dev->irq = irq_of_parse_and_map(np, 0); +#else + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!mem) { + dev_err(&pdev->dev, "no mem resource?\n"); + r = -EINVAL; + goto err_unuse_clocks; + } + dev->irq = irq_create_mapping(NULL, platform_get_irq(pdev, 0)); + dev->base = ioremap(mem->start, resource_size(mem)); +#endif + + + if (dev->base == NULL) { + dev_err(&pdev->dev, "failure mapping io resources\n"); + r = -ENOMEM; + goto err_unuse_clocks; + } + { + dev->tx_fifo_depth = I2c_GetTxFifoDepth(dev->base); + dev->rx_fifo_depth = I2c_GetRxFifoDepth(dev->base); + } + i2c_fh_init(dev); + + pr_info("\ttx fifo depth: %d, rx fifo depth: %d\n", + dev->tx_fifo_depth, dev->rx_fifo_depth); + + I2c_SetIntrMask(dev->base, DW_IC_INTR_NONE); /* disable IRQ */ + + if (dev->irq < 0) { + dev_err(&pdev->dev, "no irq resource?\n"); + r = -ENXIO; + goto err_iounmap; + } + + err = request_irq(dev->irq, i2c_fh_isr, + IRQF_SHARED, dev->isrname, dev); + + if (err) { + dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq); + r = -ENXIO; + goto err_iounmap; + } + + adap = &dev->adapter; + i2c_set_adapdata(adap, dev); + adap->owner = THIS_MODULE; + adap->class = I2C_CLASS_HWMON; + strlcpy(adap->name, "FH I2C adapter", + sizeof(adap->name)); + adap->algo = &i2c_fh_algo; + adap->dev.parent = &pdev->dev; + + adap->nr = id; +#ifdef CONFIG_USE_OF + adap->dev.of_node = np; +#endif + r = i2c_add_numbered_adapter(adap); + if (r) { + dev_err(&pdev->dev, "failure adding adapter\n"); + goto err_free_irq; + } + + pr_info("\t%s - (dev. name: %s id: %d, IRQ #%d\n" + "\t\tIO base addr: 0x%p)\n", "I2C", pdev->name, + id, dev->irq, dev->base); + + return 0; + +err_free_irq: + free_irq(dev->irq, dev); +err_iounmap: + iounmap(dev->base); +err_unuse_clocks: + clk_disable_unprepare(dev->clk); + clk_put(dev->clk); + dev->clk = NULL; +err_free_mem: + put_device(&pdev->dev); + kfree(dev); +err_return: + return r; +} + +static int __exit fh_i2c_remove(struct platform_device *pdev) +{ + struct fh_i2c_dev *dev = platform_get_drvdata(pdev); + + i2c_del_adapter(&dev->adapter); + put_device(&pdev->dev); + + clk_disable_unprepare(dev->clk); + clk_put(dev->clk); + + dev->clk = NULL; + i2c_fh_wait_master_not_active(dev); + writel(0, dev->base + DW_IC_ENABLE); + free_irq(dev->irq, dev); + kfree(dev); + + return 0; +} +static const struct of_device_id fh_i2c_of_match[] = { + {.compatible = "fh,fh-i2c",}, + {}, +}; + +static struct platform_driver fh_i2c_driver = { + .remove = __exit_p(fh_i2c_remove), + .driver = { + .name = "fh_i2c", + .owner = THIS_MODULE, + .of_match_table = fh_i2c_of_match, + + }, +}; + +static int __init fh_i2c_init_driver(void) +{ + return platform_driver_probe(&fh_i2c_driver, fh_i2c_probe); +} +module_init(fh_i2c_init_driver); + +static void __exit fh_i2c_exit_driver(void) +{ + platform_driver_unregister(&fh_i2c_driver); +} +module_exit(fh_i2c_exit_driver); + +MODULE_AUTHOR("QIN"); +MODULE_ALIAS("platform:fh"); +MODULE_DESCRIPTION("fullhan i2c driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 910cb5e2..8fde663f 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -115,6 +115,13 @@ config DW_APB_ICTL select GENERIC_IRQ_CHIP select IRQ_DOMAIN +config FULLHAN_INTC + bool + select IRQ_DOMAIN + select SPARSE_IRQ + select MULTI_IRQ_HANDLER + + config HISILICON_IRQ_MBIGEN bool select ARM_GIC_V3 diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index e4dbfc85..45583527 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_IRQ_MXS) += irq-mxs.o obj-$(CONFIG_ARCH_TEGRA) += irq-tegra.o obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o +obj-$(CONFIG_FULLHAN_INTC) += irq-fh.o obj-$(CONFIG_METAG) += irq-metag-ext.o obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o obj-$(CONFIG_ARCH_MOXART) += irq-moxart.o diff --git a/drivers/irqchip/irq-fh.c b/drivers/irqchip/irq-fh.c new file mode 100644 index 00000000..abade53d --- /dev/null +++ b/drivers/irqchip/irq-fh.c @@ -0,0 +1,218 @@ +/* + * FH irq subsystem + * + * Copyright (C) 2014 Fullhan Microelectronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define OFFSET_IRQ_EN_LOW (0x0000) +#define OFFSET_IRQ_EN_HIGH (0x0004) +#define OFFSET_IRQ_IRQMASK_LOW (0x0008) +#define OFFSET_IRQ_IRQMASK_HIGH (0x000C) +#define OFFSET_IRQ_IRQFORCE_LOW (0x0010) +#define OFFSET_IRQ_IRQFORCE_HIGH (0x0014) +#define OFFSET_IRQ_RAWSTATUS_LOW (0x0018) +#define OFFSET_IRQ_RAWSTATUS_HIGH (0x001C) +#define OFFSET_IRQ_STATUS_LOW (0x0020) +#define OFFSET_IRQ_STATUS_HIGH (0x0024) +#define OFFSET_IRQ_MASKSTATUS_LOW (0x0028) +#define OFFSET_IRQ_MASKSTATUS_HIGH (0x002C) +#define OFFSET_IRQ_FINSTATUS_LOW (0x0030) +#define OFFSET_IRQ_FINSTATUS_HIGH (0x0034) +#define OFFSET_FIQ_EN_LOW (0x02C0) +#define OFFSET_FIQ_EN_HIGH (0x02C4) +#define OFFSET_FIQ_FIQMASK_LOW (0x02C8) +#define OFFSET_FIQ_FIQMASK_HIGH (0x02CC) +#define OFFSET_FIQ_FIQFORCE_LOW (0x02D0) +#define OFFSET_FIQ_FIQFORCE_HIGH (0x02D4) +#define OFFSET_FIQ_RAWSTATUS_LOW (0x02D8) +#define OFFSET_FIQ_RAWSTATUS_HIGH (0x02DC) +#define OFFSET_FIQ_STATUS_LOW (0x02E0) +#define OFFSET_FIQ_STATUS_HIGH (0x02E4) +#define OFFSET_FIQ_FINSTATUS_LOW (0x02E8) +#define OFFSET_FIQ_FINSTATUS_HIGH (0x02EC) + +#define FH_INTC_NUM_IRQS 64 + +static void __iomem *fh_intc_base; +static struct irq_domain *fh_intc_domain; + +static int fh_intc_set_type(struct irq_data *d, unsigned int type) +{ + // only support level high + irqd_set_trigger_type(d, IRQF_TRIGGER_HIGH); + return 0; +} + +static void fh_intc_enable_irq(struct irq_data *d) +{ + u32 reg; + + if (d->hwirq > 31) { + reg = __raw_readl(fh_intc_base + OFFSET_IRQ_EN_HIGH); + reg |= 1 << (d->hwirq - 32); + __raw_writel(reg, fh_intc_base + OFFSET_IRQ_EN_HIGH); + + } else { + reg = __raw_readl(fh_intc_base + OFFSET_IRQ_EN_LOW); + reg |= 1 << d->hwirq; + __raw_writel(reg, fh_intc_base + OFFSET_IRQ_EN_LOW); + } +} + +static void fh_intc_disable_irq(struct irq_data *d) +{ + u32 reg; + + if (d->hwirq > 31) { + reg = __raw_readl(fh_intc_base + OFFSET_IRQ_EN_HIGH); + reg &= ~(1 << (d->hwirq - 32)); + __raw_writel(reg, fh_intc_base + OFFSET_IRQ_EN_HIGH); + + } else { + reg = __raw_readl(fh_intc_base + OFFSET_IRQ_EN_LOW); + reg &= ~(1 << d->hwirq); + __raw_writel(reg, fh_intc_base + OFFSET_IRQ_EN_LOW); + } +} + +static void fh_intc_mask_irq(struct irq_data *d) +{ + u32 reg; + + if (d->hwirq > 31) { + reg = __raw_readl(fh_intc_base + OFFSET_IRQ_IRQMASK_HIGH); + reg |= 1 << (d->hwirq - 32); + __raw_writel(reg, fh_intc_base + OFFSET_IRQ_IRQMASK_HIGH); + + } else { + reg = __raw_readl(fh_intc_base + OFFSET_IRQ_IRQMASK_LOW); + reg |= 1 << d->hwirq; + __raw_writel(reg, fh_intc_base + OFFSET_IRQ_IRQMASK_LOW); + } +} + +static void fh_intc_unmask_irq(struct irq_data *d) +{ + u32 reg; + + if (d->hwirq > 31) { + reg = __raw_readl(fh_intc_base + OFFSET_IRQ_IRQMASK_HIGH); + reg &= ~(1 << (d->hwirq - 32)); + __raw_writel(reg, fh_intc_base + OFFSET_IRQ_IRQMASK_HIGH); + + } else { + reg = __raw_readl(fh_intc_base + OFFSET_IRQ_IRQMASK_LOW); + reg &= ~(1 << d->hwirq); + __raw_writel(reg, fh_intc_base + OFFSET_IRQ_IRQMASK_LOW); + } +} + +static struct irq_chip fh_intc_chip = { + .irq_mask = fh_intc_mask_irq, + .irq_unmask = fh_intc_unmask_irq, + .irq_enable = fh_intc_enable_irq, + .irq_disable = fh_intc_disable_irq, + .irq_set_type = fh_intc_set_type, + +}; + +asmlinkage void __exception_irq_entry fh_intc_handle_irq(struct pt_regs *regs) +{ + u32 irqnr; + + irqnr = find_first_bit(fh_intc_base + OFFSET_IRQ_FINSTATUS_LOW, 64); + + handle_domain_irq(fh_intc_domain, irqnr, regs); + +} + +static int fh_irq_domain_map(struct irq_domain *d, unsigned int virq, + irq_hw_number_t hw) +{ + struct irq_data *data; + + + irq_set_chip_and_handler(virq, &fh_intc_chip, handle_level_irq); + /* give a default trigger type */ + data = irq_domain_get_irq_data(d, virq); + irqd_set_trigger_type(data, IRQF_TRIGGER_HIGH); + + return 0; +} + +static struct irq_domain_ops fh_irq_domain_ops = { + .map = fh_irq_domain_map, + .xlate = irq_domain_xlate_onecell, +}; +static void fh_intc_hw_init(void) +{ + WARN_ON(!fh_intc_base); + + __raw_writel(0, fh_intc_base + OFFSET_IRQ_EN_LOW); + __raw_writel(0, fh_intc_base + OFFSET_IRQ_EN_HIGH); +} + +static void fh_intc_create_default_handler(void) +{ + irq_set_default_host(fh_intc_domain); + set_handle_irq(fh_intc_handle_irq); +} + +static int __init fh_intc_of_init(struct device_node *np, + struct device_node *interrupt_parent) +{ + fh_intc_base = of_iomap(np, 0); + + fh_intc_hw_init(); + + fh_intc_domain = irq_domain_add_linear(np, FH_INTC_NUM_IRQS, + &fh_irq_domain_ops, NULL); + + fh_intc_create_default_handler(); + + return fh_intc_domain ? 0 : -ENODEV; +} +IRQCHIP_DECLARE(fh, "fh,fh-intc", fh_intc_of_init); + + +#ifndef CONFIG_USE_OF +void __init fh_intc_init_no_of(unsigned int iovbase) +{ + int irq_base; + + fh_intc_base = (void *)iovbase; + + fh_intc_hw_init(); + + irq_base = irq_alloc_descs(-1, 0, FH_INTC_NUM_IRQS, 0); + + if (irq_base < 0) + irq_base = 0; + + + /* create a legacy host */ + fh_intc_domain = irq_domain_add_legacy(NULL, FH_INTC_NUM_IRQS, + irq_base, 0, &fh_irq_domain_ops, NULL); + + + fh_intc_create_default_handler(); +} +#endif diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index d6c404b3..3b26d4e6 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -290,15 +290,14 @@ static int gic_irq_get_irqchip_state(struct irq_data *d, return 0; } + static int gic_set_type(struct irq_data *d, unsigned int type) { void __iomem *base = gic_dist_base(d); unsigned int gicirq = gic_irq(d); - /* Interrupt configuration for SGIs can't be changed */ if (gicirq < 16) return -EINVAL; - /* SPIs have restrictions on the supported types */ if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) @@ -956,6 +955,9 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) { struct gic_chip_data *gic = d->host_data; +#ifdef CONFIG_ARCH_FULLHAN + struct irq_data *data; +#endif if (hw < 32) { irq_set_percpu_devid(irq); @@ -967,6 +969,13 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, handle_fasteoi_irq, NULL, NULL); irq_set_probe(irq); } + +#ifdef CONFIG_ARCH_FULLHAN + /* give a default trigger type */ + data = irq_domain_get_irq_data(d, irq); + irqd_set_trigger_type(data, IRQF_TRIGGER_HIGH); +#endif + return 0; } @@ -1034,6 +1043,8 @@ static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, } static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = { + .map = gic_irq_domain_map, + .unmap = gic_irq_domain_unmap, .translate = gic_irq_domain_translate, .alloc = gic_irq_domain_alloc, .free = irq_domain_free_irqs_top, @@ -1149,6 +1160,8 @@ static int gic_init_bases(struct gic_chip_data *gic, int irq_start, goto error; } + irq_set_default_host(gic->domain); + gic_dist_init(gic); ret = gic_cpu_init(gic); if (ret) diff --git a/drivers/media/usb/dvb-usb/technisat-usb2.c b/drivers/media/usb/dvb-usb/technisat-usb2.c index 4706628a..f3ea8555 100644 --- a/drivers/media/usb/dvb-usb/technisat-usb2.c +++ b/drivers/media/usb/dvb-usb/technisat-usb2.c @@ -612,10 +612,9 @@ static int technisat_usb2_frontend_attach(struct dvb_usb_adapter *a) static int technisat_usb2_get_ir(struct dvb_usb_device *d) { struct technisat_usb2_state *state = d->priv; - u8 *buf = state->buf; - u8 *b; - int ret; struct ir_raw_event ev; + u8 *buf = state->buf; + int i, ret; buf[0] = GET_IR_DATA_VENDOR_REQUEST; buf[1] = 0x08; @@ -651,27 +650,26 @@ static int technisat_usb2_get_ir(struct dvb_usb_device *d) return 0; /* no key pressed */ /* decoding */ - b = buf+1; #if 0 deb_rc("RC: %d ", ret); debug_dump(b, ret, deb_rc); + debug_dump(buf + 1, ret, deb_rc); #endif ev.pulse = 0; - while (1) { - ev.pulse = !ev.pulse; - ev.duration = (*b * FIRMWARE_CLOCK_DIVISOR * FIRMWARE_CLOCK_TICK) / 1000; - ir_raw_event_store(d->rc_dev, &ev); - - b++; - if (*b == 0xff) { + for (i = 1; i < ARRAY_SIZE(state->buf); i++) { + if (buf[i] == 0xff) { ev.pulse = 0; ev.duration = 888888*2; ir_raw_event_store(d->rc_dev, &ev); break; } - } + + ev.pulse = !ev.pulse; + ev.duration = (buf[i] * FIRMWARE_CLOCK_DIVISOR * + FIRMWARE_CLOCK_TICK) / 1000; + ir_raw_event_store(d->rc_dev, &ev); ir_raw_event_handle(d->rc_dev); @@ -736,7 +734,7 @@ static struct dvb_usb_device_properties technisat_usb2_devices = { } } }, - }}, + } }, .size_of_priv = 0, }, }, diff --git a/drivers/media/v4l2-core/videobuf2-core.c b/drivers/media/v4l2-core/videobuf2-core.c index f7ca1fab..de8051d9 100644 --- a/drivers/media/v4l2-core/videobuf2-core.c +++ b/drivers/media/v4l2-core/videobuf2-core.c @@ -2065,8 +2065,8 @@ unsigned int vb2_core_poll(struct vb2_queue *q, struct file *file, * error flag is set. */ if (!vb2_is_streaming(q) || q->error) - return POLLERR; - + /* return POLLERR; */ + return 0; /* mengqx */ /* * If this quirk is set and QBUF hasn't been called yet then * return POLLERR as well. This only affects capture queues, output @@ -2324,7 +2324,7 @@ static size_t __vb2_perform_fileio(struct vb2_queue *q, char __user *data, size_ * else is able to provide this information with the write() operation. */ bool copy_timestamp = !read && q->copy_timestamp; - unsigned index; + unsigned int index; int ret; dprintk(3, "mode %s, offset %ld, count %zd, %sblocking\n", diff --git a/drivers/media/v4l2-core/videobuf2-v4l2.c b/drivers/media/v4l2-core/videobuf2-v4l2.c index 52ef8833..e7899b05 100644 --- a/drivers/media/v4l2-core/videobuf2-v4l2.c +++ b/drivers/media/v4l2-core/videobuf2-v4l2.c @@ -683,6 +683,8 @@ unsigned int vb2_poll(struct vb2_queue *q, struct file *file, poll_table *wait) res = POLLPRI; else if (req_events & POLLPRI) poll_wait(file, &fh->wait, wait); + if (v4l2_event_pending(fh)) + res = POLLPRI; } return res | vb2_core_poll(q, file, wait); diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 64971baf..a29e9746 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -4,6 +4,117 @@ menu "Misc devices" +config FH_DW_I2S + tristate "FH DW I2S(master) support" + default n + help + FH DW I2S driver, as the MASTER, generate BICK & LRCLK for slave + +config FH_ACW + tristate "FH ACW(slave) support" + default n + help + FH ACW I2S driver, as the SLAVE, external clk input is required + +config AUDIO_DMA_BUFFER_KB + int "Audio DMA buffer size in KB" + depends on FH_DW_I2S || FH_ACW + default 32 + help + Audio DMA buffer size in KB + 16KHz --> 16KB + 48KHz --> 32KB + +config FH_STEPMOTOR + depends on (ARCH_FH865x || ARCH_FH8636 || ARCH_FH8852V101) + tristate "FH STEPMOTOR Suppport" + default y + +config FH_SADC_V1 + depends on (MACH_FH8856 || MACH_FH8852) + tristate "FH SADC support(v1 version)" + help + To compile this driver as a module, choose M here: the module will + be called fh_sadc. + + HW para:10bits precision, 8 channels, 5M clk in. + one conversion need almost (12/5M *1)second + +config FH_SADC_V2 + depends on (MACH_FH8626V100) + tristate "FH SADC support(v2 version)" + help + To compile this driver as a module, choose M here: the module will + be called fh_sadc. + + HW para:12bits precision, 8 channels, 5M clk in. + one conversion need almost (12/5M *1)second + +config FH_SADC_V21 + depends on (MACH_FH8626V100) + tristate "FH SADC support(v21 version)" + default n + +config FH_SADC_V3 + depends on (ARCH_FH885xV200 || ARCH_FH865x || ARCH_FH8636 || ARCH_FH8852V101) + tristate "FH SADC support(v3 version)" + help + FH885xV200 or later soc version use SADC_V3 version. + + HW para:12bits precision, 8 channels, 5M clk in. + one conversion need almost (12/5M *1)second +choice + bool "FH EFUSE driver select" + default FH_EFUSE + +config FH_EFUSE_TEE + tristate "FH EFUSE driver for tee" + depends on TEE + +config FH_EFUSE + tristate "FH EFUSE driver original" + help + To compile this driver as a module, choose M here: the module will + be called fh_efuse. + + HW para:60 bytes could be programmed. +endchoice + +config FH_L2MEM + tristate "FH L2MEM allocator" + default n + +config FH_PINCTRL_MISC_DEV + tristate "FH Pinctrl misc device support" + default n + depends on ! PINCTRL_FULLHAN + help + To compile this driver as a module, choose M here: the module will + be called. + +config FH_CLK_MISC + tristate "FH clk miscdev support" + default n + help + To compile this driver as a module, choose M here: the module will + be called. + +if ARCH_FH885xV200 || ARCH_FH865x || ARCH_FH8636 || ARCH_FH8852V101 +config FH_PERF_MON + tristate "FH performance monitor" + default y + help + fh performance monitor +endif + +config FH_TSENSOR + depends on !(MACH_FH8856 || MACH_FH8852) && RTC_DRV_FH + tristate "FH TSENSOR suppport" + default n + help + fullhan tsensor driver, used to get the chip temperature + + config SENSORS_LIS3LV02D tristate depends on INPUT diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 2bf79ba4..92d953f8 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -53,6 +53,22 @@ obj-$(CONFIG_ECHO) += echo/ obj-$(CONFIG_VEXPRESS_SYSCFG) += vexpress-syscfg.o obj-$(CONFIG_CXL_BASE) += cxl/ obj-$(CONFIG_PANEL) += panel.o +ccflags-y += -I$(srctree)/drivers/tee/tee_api + +obj-$(CONFIG_FH_DMAC_MISC) += fh_dma_miscdev.o +obj-$(CONFIG_FH_ACW) += fh_acw.o +obj-$(CONFIG_FH_DW_I2S) += fh_dw_i2s.o +obj-$(CONFIG_FH_SADC_V1) += fh_sadc.o +obj-$(CONFIG_FH_SADC_V2) += fh_sadc_v2.o +obj-$(CONFIG_FH_SADC_V3) += fh_sadc_v3.o +obj-$(CONFIG_FH_EFUSE) += fh_efuse.o +obj-$(CONFIG_FH_EFUSE_TEE) += fh_efuse_tee.o +obj-$(CONFIG_FH_PINCTRL_MISC_DEV) += fh_pinctrl_dev.o +obj-$(CONFIG_FH_CLK_MISC) += fh_clk_miscdev.o +obj-$(CONFIG_FH_PERF_MON) += fh_perf_mon.o +obj-$(CONFIG_FH_STEPMOTOR) += fh_stepmotor.o fh_stepmotor_hw.o +obj-$(CONFIG_FH_TSENSOR) += fh_tsensor.o + lkdtm-$(CONFIG_LKDTM) += lkdtm_core.o lkdtm-$(CONFIG_LKDTM) += lkdtm_bugs.o diff --git a/drivers/misc/fh_acw.c b/drivers/misc/fh_acw.c new file mode 100644 index 00000000..ffe4accb --- /dev/null +++ b/drivers/misc/fh_acw.c @@ -0,0 +1,1422 @@ +/**@file + * @Copyright (c) 2016 Shanghai Fullhan Microelectronics Co., Ltd. + * @brief + * + * @author fullhan + * @date 2016-7-15 + * @version V1.0 + * @version V1.1 modify code style + * @note: misc audio driver for fh8830 embedded audio codec. + * @note History: + * @note