diff -drupN a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
--- a/arch/mips/kernel/cpu-probe.c	2017-10-21 18:09:07.000000000 +0300
+++ b/arch/mips/kernel/cpu-probe.c	2022-06-09 05:02:27.000000000 +0300
@@ -17,6 +17,7 @@
 #include <linux/smp.h>
 #include <linux/stddef.h>
 #include <linux/export.h>
+#include <linux/kallsyms.h>
 
 #include <asm/bugs.h>
 #include <asm/cpu.h>
@@ -414,6 +415,7 @@ static inline unsigned int decode_config
 
 	config0 = read_c0_config();
 
+
 	/*
 	 * Look for Standard TLB or Dual VTLB and FTLB
 	 */
@@ -471,6 +473,8 @@ static inline unsigned int decode_config
 
 	config1 = read_c0_config1();
 
+        if (config1 & MIPS_CONF1_C2)
+                c->ases |= MIPS_ASE_CU2;
 	if (config1 & MIPS_CONF1_MD)
 		c->ases |= MIPS_ASE_MDMX;
 	if (config1 & MIPS_CONF1_WR)
@@ -1332,18 +1336,65 @@ platform:
 	}
 }
 
+#ifdef CONFIG_XBURST_MXUV2
+extern int soc_support_mxuv2(void);
+#endif
 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
 {
+	unsigned int errorpc;
+	static unsigned int showerrorpc[NR_CPUS];
+	unsigned int config1;
+
+	if(showerrorpc[cpu] == 0) {
+		__asm__ __volatile__ (
+				"mfc0  %0, $30,  0   \n\t"
+				"nop                  \n\t"
+				:"=r"(errorpc)
+				:);
+
+		printk("CPU%d RESET ERROR PC:%08X\n", cpu,errorpc);
+		if(kernel_text_address(errorpc))
+			print_ip_sym(errorpc);
+		showerrorpc[cpu] = 1;
+	}
+
 	decode_configs(c);
 	/* JZRISC does not implement the CP0 counter. */
+	/* INGENIC RISC does not implement the CP0 counter. */
 	c->options &= ~MIPS_CPU_COUNTER;
 	BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
-	switch (c->processor_id & PRID_IMP_MASK) {
-	case PRID_IMP_JZRISC:
+
+	switch (c->processor_id & PRID_IMP_PROCESSOR_ID_MSK) {
+	case PRID_IMP_XBURST:
+	{
+		unsigned int config7;
 		c->cputype = CPU_JZRISC;
 		c->writecombine = _CACHE_UNCACHED_ACCELERATED;
-		__cpu_name[cpu] = "Ingenic JZRISC";
+		__cpu_name[cpu] = "Xburst";
+		/*
+		 * When CPU enters the long cycle, it will reduce the CPU speed to save power.
+		 * Set cp0 config7 bit 4 to disable this feature
+		 * This feature will cause bogoMips and loops_per_jiffy calculate in error
+		 */
+		config7 = read_c0_config7();
+		config7 |= (1 << 4);
+		write_c0_config7(config7);
+
+		config1 = read_c0_config1();
+#ifdef CONFIG_XBURST_MXUV2
+		if(soc_support_mxuv2()) {
+			c->ases |= MIPS_ASE_XBURSTMXUV2;
+		} else
+#endif
+		//c->ases |= MIPS_ASE_XBURSTMXU;
+	}
+		break;
+	case PRID_IMP_XBURST2:
+	{
+		c->cputype = CPU_JZRISC;
+		__cpu_name[cpu] = "Ingenic XBurst@II";
 		break;
+	}
 	default:
 		panic("Unknown Ingenic Processor ID!");
 		break;
@@ -1444,6 +1495,7 @@ void cpu_probe(void)
 {
 	struct cpuinfo_mips *c = &current_cpu_data;
 	unsigned int cpu = smp_processor_id();
+        //unsigned long fpu_csr31 = 0;
 
 	c->processor_id = PRID_IMP_UNKNOWN;
 	c->fpu_id	= FPIR_IMP_NONE;
@@ -1482,6 +1534,7 @@ void cpu_probe(void)
 	case PRID_COMP_INGENIC_D0:
 	case PRID_COMP_INGENIC_D1:
 	case PRID_COMP_INGENIC_E1:
+	case PRID_COMP_INGENIC_13:
 		cpu_probe_ingenic(c, cpu);
 		break;
 	case PRID_COMP_NETLOGIC:
@@ -1512,7 +1565,20 @@ void cpu_probe(void)
 	}
 
 	if (c->options & MIPS_CPU_FPU)
+        {
+                //fpu_fcr31 = cpu_test_fpu_csr31(FPU_CSR_DEFAULT);
 		cpu_set_fpu_opts(c);
+                #if 0
+                if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
+                                   MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
+                      if (c->fpu_id & MIPS_FPIR_3D)
+                               c->ases |= MIPS_ASE_MIPS3D;
+                       if (c->fpu_id & MIPS_FPIR_HAS2008)
+                               fpu_fcr31 = cpu_test_fpu_csr31(FPU_CSR_DEFAULT|FPU_CSR_MAC2008|FPU_CSR_ABS2008|FPU_CSR_NAN2008);
+               }
+               #endif
+
+        }
 	else
 		cpu_set_nofpu_opts(c);