From e81a81116296fcc2a2b675a20f416de79ff15e67 Mon Sep 17 00:00:00 2001 From: Dmitry Ilyin Date: Sun, 25 Apr 2021 20:34:56 +0300 Subject: [PATCH] Add jxf37 config (tested on Ruision RS-H649F-A0) --- README.md | 2 +- .../sensor/config/jxf37_i2c_1080p_line.ini | 298 ++++++++++++++++++ 2 files changed, 299 insertions(+), 1 deletion(-) create mode 100644 br-ext-chip-hisilicon/package/hisilicon-osdrv4/files/sensor/config/jxf37_i2c_1080p_line.ini diff --git a/README.md b/README.md index d91fa2b4..19de6eef 100644 --- a/README.md +++ b/README.md @@ -33,4 +33,4 @@ If you like our work, please consider supporting us on [Opencollective](https:// |![Image](https://github.com/OpenIPC/openipc-2.1/actions/workflows/hi3516ev300_images.yml/badge.svg)|Hi3516Ev300|[uImage + rootfs.squashfs](https://github.com/OpenIPC/openipc-2.1/releases/download/latest/openipc.hi3516ev300-br.tgz)|[zigfisher](https://github.com/ZigFisher), [widgetii](https://github.com/widgetii)| OK | |![Image](https://github.com/OpenIPC/openipc-2.1/actions/workflows/hi3518ev300_images.yml/badge.svg)|Hi3518Ev300|[uImage + rootfs.squashfs](https://github.com/OpenIPC/openipc-2.1/releases/download/latest/openipc.hi3518ev300-br.tgz)|[zigfisher](https://github.com/ZigFisher), [widgetii](https://github.com/widgetii)| OK | |![Image](https://github.com/OpenIPC/openipc-2.1/actions/workflows/ssc335_images.yml/badge.svg)|SSC335|[-](https://github.com/OpenIPC/openipc-2.1/releases/download/latest/openipc.ssc335-br.tgz)|[zigfisher](https://github.com/ZigFisher)|in progress| -|![Image](https://github.com/OpenIPC/openipc-2.1/actions/workflows/xm530_images.yml/badge.svg)|XM530|[uImage + rootfs.squashfs](https://github.com/OpenIPC/openipc-2.1/releases/download/latest/openipc.xm530-br.tgz)|[zigfisher](https://github.com/ZigFisher)|no video | +|![Image](https://github.com/OpenIPC/openipc-2.1/actions/workflows/xm530_images.yml/badge.svg)|XM530/XM550|[uImage + rootfs.squashfs](https://github.com/OpenIPC/openipc-2.1/releases/download/latest/openipc.xm530-br.tgz)|[zigfisher](https://github.com/ZigFisher)|no video | diff --git a/br-ext-chip-hisilicon/package/hisilicon-osdrv4/files/sensor/config/jxf37_i2c_1080p_line.ini b/br-ext-chip-hisilicon/package/hisilicon-osdrv4/files/sensor/config/jxf37_i2c_1080p_line.ini new file mode 100644 index 00000000..342812ef --- /dev/null +++ b/br-ext-chip-hisilicon/package/hisilicon-osdrv4/files/sensor/config/jxf37_i2c_1080p_line.ini @@ -0,0 +1,298 @@ +[sensor] +Sensor_type =stSnsSoiF37Obj ;sensor name +Mode =0 ;WDR_MODE_NONE = 0 + ;WDR_MODE_BUILT_IN = 1 + ;WDR_MODE_QUDRA = 2 + ;WDR_MODE_2To1_LINE = 3 + ;WDR_MODE_2To1_FRAME = 4 + ;WDR_MODE_2To1_FRAME_FULL_RATE = 5 + ;WDR_MODE_3To1_LINE = 6 + ;WDR_MODE_3To1_FRAME = 7 + ;WDR_MODE_3To1_FRAME_FULL_RATE = 8 + ;WDR_MODE_4To1_LINE = 9 + ;WDR_MODE_4To1_FRAME = 10 + ;WDR_MODE_4To1_FRAME_FULL_RATE = 11 +DllFile = /usr/lib/sensors/libsns_f37.so ;sensor lib path + + +[mode] +input_mode =0 ;INPUT_MODE_MIPI = 0 + ;INPUT_MODE_SUBLVDS = 1 + ;INPUT_MODE_LVDS = 2 ...etc + +dev_attr = 2 ;mipi_dev_attr_t = 0 + ;lvds_dev_attr_t = 1 + ;NULL =2 +raw_bitness = 12 + +[mipi] +;----------only for mipi_dev--------- +data_type = 2 ;raw data type: 8/10/12/14 bit + ;DATA_TYPE_RAW_8BIT = 0, + ;DATA_TYPE_RAW_10BIT, + ;DATA_TYPE_RAW_12BIT, + ;DATA_TYPE_RAW_14BIT, + ;DATA_TYPE_RAW_16BIT, + ;DATA_TYPE_YUV420_8BIT_NORMAL, + ;DATA_TYPE_YUV420_8BIT_LEGACY, + ;DATA_TYPE_YUV422_8BIT, +lane_id = 0|2|-1|-1|-1|-1|-1|-1| ;lane_id: -1 - disable + +[lvds] +;----------only for lvds_dev--------- +img_size_w = -1 ;oringnal sensor input image size W +img_size_h = -1 ;oringnal sensor input image size H +wdr_mode = -1 ;HI_WDR_MODE_NONE =0 + ;HI_WDR_MODE_2F = 1 + ;HI_WDR_MODE_3F = 2 + ;HI_WDR_MODE_4F =3 +sync_mode = -1 ;LVDS_SYNC_MODE_SOL = 0 + ;LVDS_SYNC_MODE_SAV = 1 +raw_data_type = -1 ;RAW_DATA_8BIT = 0 + ;RAW_DATA_10BIT = 1 + ;RAW_DATA_12BIT = 2 + ;RAW_DATA_14BIT = 3 +data_endian = -1 ;LVDS_ENDIAN_LITTLE = 0 + ;LVDS_ENDIAN_BIG = 1 +sync_code_endian =-1 ;LVDS_ENDIAN_LITTLE = 0 + ;LVDS_ENDIAN_BIG = 1 +lane_id = -1|-1|-1|-1|-1|-1|-1|-1| ;lane_id: -1 - disable +lvds_lane_num = -1 ;LVDS_LANE_NUM +wdr_vc_num = -1 ;WDR_VC_NUM +sync_code_num = -1 ;SYNC_CODE_NUM +sync_code_0 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1| +sync_code_1 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1| +sync_code_2 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1| +sync_code_3 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1| +sync_code_4 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1| +sync_code_5 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1| +sync_code_6 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1| +sync_code_7 = -1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1|-1| + +[isp_image] +Isp_x =0 +Isp_y =0 +Isp_W =1920 +Isp_H =1080 +Isp_FrameRate=30 +Isp_Bayer =0 ;BAYER_RGGB=0, BAYER_GRBG=1, BAYER_GBRG=2, BAYER_BGGR=3 + + +[vi_dev] +Input_mod = 6 + ; VI_MODE_BT656 = 0, /* ITU-R BT.656 YUV4:2:2 */ + ; VI_MODE_BT656_PACKED_YUV, /* ITU-R BT.656 packed YUV4:2:2 */ + ; VI_MODE_BT601, /* ITU-R BT.601 YUV4:2:2 */ + ; VI_MODE_DIGITAL_CAMERA, /* digatal camera mode */ + ; VI_MODE_BT1120_STANDARD, /* BT.1120 progressive mode */ + ; VI_MODE_BT1120_INTERLEAVED, /* BT.1120 interstage mode */ + ; VI_MODE_MIPI, /* MIPI RAW mode */ + ; VI_MODE_MIPI_YUV420_NORMAL, /* MIPI YUV420 normal mode */ + ; VI_MODE_MIPI_YUV420_LEGACY, /* MIPI YUV420 legacy mode */ + ; VI_MODE_MIPI_YUV422, /* MIPI YUV422 mode */ + ; VI_MODE_LVDS, /* LVDS mode */ + ; VI_MODE_HISPI, /* HiSPi mode */ + ; VI_MODE_SLVS, /* SLVS mode */ +Work_mod =0 ;VI_WORK_MODE_1Multiplex = 0 + ;VI_WORK_MODE_2Multiplex, + ;VI_WORK_MODE_4Multiplex +Combine_mode =0 ;Y/C composite or separation mode + ;VI_COMBINE_COMPOSITE = 0 /*Composite mode */ + ;VI_COMBINE_SEPARATE, /*Separate mode */ +Comp_mode =0 ;Component mode (single-component or dual-component) + ;VI_COMP_MODE_SINGLE = 0, /*single component mode */ + ;VI_COMP_MODE_DOUBLE = 1, /*double component mode */ +Clock_edge =1 ;Clock edge mode (sampling on the rising or falling edge) + ;VI_CLK_EDGE_SINGLE_UP=0, /*rising edge */ + ;VI_CLK_EDGE_SINGLE_DOWN, /*falling edge */ +Mask_num =2 ;Component mask +Mask_0 =0xFFF00000 +Mask_1 =0x0 +Scan_mode = 1;VI_SCAN_INTERLACED = 0 + ;VI_SCAN_PROGRESSIVE, +Data_seq =2 ;data sequence (ONLY for YUV format) + ;----2th component U/V sequence in bt1120 + ; VI_INPUT_DATA_VUVU = 0, + ; VI_INPUT_DATA_UVUV, + ;----input sequence for yuv + ; VI_INPUT_DATA_UYVY = 0, + ; VI_INPUT_DATA_VYUY, + ; VI_INPUT_DATA_YUYV, + ; VI_INPUT_DATA_YVYU + +Vsync =1 ; vertical synchronization signal + ;VI_VSYNC_FIELD = 0, + ;VI_VSYNC_PULSE, +VsyncNeg=1 ;Polarity of the vertical synchronization signal + ;VI_VSYNC_NEG_HIGH = 0, + ;VI_VSYNC_NEG_LOW /*if VIU_VSYNC_E +Hsync =0 ;Attribute of the horizontal synchronization signal + ;VI_HSYNC_VALID_SINGNAL = 0, + ;VI_HSYNC_PULSE, +HsyncNeg =0 ;Polarity of the horizontal synchronization signal + ;VI_HSYNC_NEG_HIGH = 0, + ;VI_HSYNC_NEG_LOW +VsyncValid =1 ;Attribute of the valid vertical synchronization signal + ;VI_VSYNC_NORM_PULSE = 0, + ;VI_VSYNC_VALID_SINGAL, +VsyncValidNeg =0;Polarity of the valid vertical synchronization signal + ;VI_VSYNC_VALID_NEG_HIGH = 0, + ;VI_VSYNC_VALID_NEG_LOW +Timingblank_HsyncHfb =0 ;Horizontal front blanking width +Timingblank_HsyncAct =1920 ;Horizontal effetive width +Timingblank_HsyncHbb =0 ;Horizontal back blanking width +Timingblank_VsyncVfb =0 ;Vertical front blanking height +Timingblank_VsyncVact =1080 ;Vertical effetive width +Timingblank_VsyncVbb=0 ;Vertical back blanking height +Timingblank_VsyncVbfb =0 ;Even-field vertical front blanking height(interlace, invalid progressive) +Timingblank_VsyncVbact=0 ;Even-field vertical effetive width(interlace, invalid progressive) +Timingblank_VsyncVbbb =0 ;Even-field vertical back blanking height(interlace, invalid progressive) + +;----- only for bt656 ---------- +FixCode =0 ;BT656_FIXCODE_1 = 0, + ;BT656_FIXCODE_0 +FieldPolar=0 ;BT656_FIELD_POLAR_STD = 0 + ;BT656_FIELD_POLAR_NSTD +DataPath =1 ;ISP enable or bypass + ;VI_PATH_BYPASS = 0,/* ISP bypass */ + ;VI_PATH_ISP = 1,/* ISP enable */ + ;VI_PATH_RAW = 2,/* Capture raw data, for debug */ +InputDataType=1 ;VI_DATA_TYPE_YUV = 0,VI_DATA_TYPE_RGB = 1, +DataRev =FALSE ;Data reverse. FALSE = 0; TRUE = 1 +DevRect_x=200 ; +DevRect_y=20 ; +DevRect_w=1920 ; +DevRect_h=1080 ; + +[vi_chn] +CapRect_X =0 +CapRect_Y =0 +CapRect_Width=1920 +CapRect_Height=1080 +DestSize_Width=1920 +DestSize_Height=1080 +CapSel =2 ;Frame/field select. ONLY used in interlaced mode + ;VI_CAPSEL_TOP = 0, /* top field */ + ;VI_CAPSEL_BOTTOM, /* bottom field */ + ;VI_CAPSEL_BOTH, /* top and bottom field */ + +PixFormat =26;PIXEL_FORMAT_YVU_SEMIPLANAR_420 = 26 ...etc +CompressMode =0 ;COMPRESS_MODE_NONE = 0 + ;COMPRESS_MODE_SEG =1 ...etc + +SrcFrameRate=-1 ;Source frame rate. -1: not controll +FrameRate =-1 ;Target frame rate. -1: not controll + +[vpss_group] +Vpss_DciEn =FALSE +Vpss_IeEn =FALSE +Vpss_NrEn =TRUE +Vpss_HistEn =FALSE +Vpss_DieMode=1 ;Define de-interlace mode + ;VPSS_DIE_MODE_AUTO = 0, + ;VPSS_DIE_MODE_NODIE = 1, + ;VPSS_DIE_MODE_DIE = 2, + +[vpss_corp] +Crop_enable =FALSE +Coordinate =1 ;VPSS_CROP_RATIO_COOR = 0, /*Ratio coordinate*/ + ;VPSS_CROP_ABS_COOR = 1 /*Absolute coordinate*/ +Crop_X =128 +Crop_Y =128 +Crop_W =1158 +Crop_H =562 + +[vpss_chn] +Vpss_W =1920 +Vpss_H =1080 +CompressMode=0 ;COMPRESS_MODE_NONE = 0 + ;COMPRESS_MODE_SEG =1 ...etc +Mirror =FALSE;Whether to mirror +Flip =FALSE;Whether to flip + +[vb_conf] +VbCnt=10 +vbTimes=15 ;when raw=8bit vbTimes = 10 + ;when raw=10/12 bit vbTimes = 15 + ;when raw=14/16 bit vbTimes = 20 +[venc_comm] +venc_chn =1 ;create venc chn number;(0,2] +BufCnt = 1 ;network meida-trans bufcnt + +[venc_0] +PicWidth =1920 +PicHeight =1080 +Profile =2 +RcMode =VENC_RC_MODE_H264CBR + +Gop =50 +StatTime =2 +ViFrmRate =30 +TargetFrmRate=30 +;----- only for VENC_RC_MODE_H264CBR ---------- +BitRate=4096 +FluctuateLevel=0 +;----- only for VENC_RC_MODE_H264VBR ---------- +MaxBitRate =10000 + +MaxQp=32 +MinQp=24 +;----- only for VENC_RC_MODE_H264FIXQP ---------- +IQp=45 + +PQp=40 +;-------- for REF_EX IsliceEnable------ +IsliceEnable = FALSE ;IsliceEnable and ViEnable is mutual exclusion +IsRefreshEnable = FALSE ;IsliceEnable and bRefreshEnable both TRUE is effective +RefreshLineNum = 12 ;PicHeight/16/6 6 is empirical value,ask Fuyang +ReqIQp = 30 +;-------- for REF_EX ViEnable------ +ViEnable = TRUE +ViInterval = 50 ; 2s +ViQpDelta = 2 + +[venc_1] +PicWidth =1920 +PicHeight =1080 +Profile =2 +RcMode =VENC_RC_MODE_H264CBR + +Gop =50 +StatTime =2 +ViFrmRate =30 +TargetFrmRate=30 +;----- only for VENC_RC_MODE_H264CBR ---------- +BitRate=4096 +FluctuateLevel=0 +;----- only for VENC_RC_MODE_H264VBR ---------- +MaxBitRate =10000 + +MaxQp=32 + +MinQp=24 +;----- only for VENC_RC_MODE_H264FIXQP ---------- +IQp=40 + +PQp=45 +;-------- for REF_EX IsliceEnable------ +IsliceEnable = FALSE ;IsliceEnable and ViEnable is mutual exclusion +IsRefreshEnable = FALSE ;IsliceEnable and bRefreshEnable both TRUE is effective +RefreshLineNum = 12 ;PicHeight/16/6 6 is empirical value,ask Fuyang +ReqIQp = 30 +;-------- for REF_EX ViEnable------ +ViEnable = TRUE +ViInterval = 50 ; 2s +ViQpDelta = 2 + +[bind] +ViDev =0 +ViChn =0 +VpssGrp =0 +VpssChn = 0 +VoDev =0 +VoChn =0 +ViSnapChn =0 +VpssSnapGrp=0 +VpssSnapChn=1 +VencSnapGrp=1 +VencSnapChn=3