OpenIPC
/
firmware
mirror of https://github.com/OpenIPC/firmware.git
1
0
Fork 0
Code Activity

Fix SigmaStar troubles and remove unused files

pull/65/head
Igor Zalatov (from Citadel PC) 2021-11-02 23:15:07 +03:00
parent f176dd2d64
commit dd7b469799
100 changed files with 201 additions and 20725 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
general/package/hisilicon-osdrv-hi3516cv100/Config.in 100644
View File

@ -0,0 +1,6 @@
config BR2_PACKAGE_HISILICON_OSDRV_HI3516CV100
bool "hisilicon-osdrv-hi3516cv100"
help
hisilicon-osdrv-hi3516cv100 - Hisilicon kernel modules and libs
https://openipc.org

BIN
general/package/hisilicon-osdrv-hi3516cv100/files/fonts/fonts.bin 100644
View File

Binary file not shown.

0
general/package/hisilicon-osdrv-hi3516cv100/files/kmod/.dot 100644
View File

0
general/package/hisilicon-osdrv-hi3516cv100/files/lib/.dot 100644
View File

68
general/package/hisilicon-osdrv-hi3516cv100/files/script/S99hisilicon 100755
View File

@ -0,0 +1,68 @@
#!/bin/sh
DAEMON="majestic"
PIDFILE="/var/run/$DAEMON.pid"
DAEMON_ARGS=""
# shellcheck source=/dev/null
[ -r "/etc/default/$DAEMON" ] && . "/etc/default/$DAEMON"
# The daemon does not create a pidfile, and use "-m" to instruct start-stop-daemon to create one.
start() {
logger -s -p daemon.info -t hisilicon "Check MAC for Xiongmai devices"
if [ "$(fw_printenv -n ethaddr)" = "00:00:23:34:45:66" ]; then
logger -s -p daemon.info -t hisilicon "The eth0 interface has a lousy MAC, let's try to change it.."
XMMAC="$(ipcinfo --xm_mac)" && [ -n "${XMMAC}" ] && fw_setenv ethaddr ${XMMAC} && ifconfig eth0 hw ether ${XMMAC} && logger -s -p daemon.info -t hisilicon "The eth0 interface have new MAC - ${XMMAC}" && reboot -f
else
logger -s -p daemon.info -t hisilicon "The eth0 interface has a correct MAC - $(fw_printenv -n ethaddr)"
fi
#
logger -s -p daemon.info -t hisilicon "Loading of kernel modules and initialization of the video system has started"
export TZ=$(cat /etc/TZ)
load_hisilicon -i
#
printf 'Starting %s: ' "$DAEMON"
[ -f /usr/bin/$DAEMON ] || echo -en "DISABLED, "
# shellcheck disable=SC2086 # we need the word splitting
start-stop-daemon -b -m -S -q -p "$PIDFILE" -x "/usr/bin/$DAEMON" \
-- $DAEMON_ARGS
status=$?
if [ "$status" -eq 0 ]; then
echo "OK"
else
echo "FAIL"
fi
return "$status"
}
stop() {
printf 'Stopping %s: ' "$DAEMON"
[ -f /usr/sbin/$DAEMON ] || echo -en "DISABLED, "
start-stop-daemon -K -q -p "$PIDFILE"
status=$?
if [ "$status" -eq 0 ]; then
rm -f "$PIDFILE"
echo "OK"
else
echo "FAIL"
fi
return "$status"
}
restart() {
stop
sleep 1
start
}
case "$1" in
start|stop|restart)
"$1";;
reload)
# Restart, since there is no true "reload" feature.
restart;;
*)
echo "Usage: $0 {start|stop|restart|reload}"
exit 1
esac

87
general/package/hisilicon-osdrv-hi3516cv100/files/script/ircut_demo 100644
View File

@ -0,0 +1,87 @@
#!/bin/sh
# on EV200:
# GPIO1_0 -> GPIO8 (1*8+0 = 8)
# GPIO1_1 -> GPIO9 (1*8+1 = 9)
# on EV300:
# GPIO1_3 -> GPIO11
# GPIO1_2 -> GPIO10
#(normal mode)
ir_cut_enable() {
# pin_mux
echo "$gpio_0" >/sys/class/gpio/unexport
echo "$gpio_1" >/sys/class/gpio/unexport
echo "$gpio_0" >/sys/class/gpio/export
echo "$gpio_1" >/sys/class/gpio/export
# dir
echo "out" >/sys/class/gpio/gpio$gpio_0/direction
echo "out" >/sys/class/gpio/gpio$gpio_1/direction
# data, gpio_1: 0, gpio_0: 1 (normal mode)
echo "1" >/sys/class/gpio/gpio$gpio_0/value
echo "0" >/sys/class/gpio/gpio$gpio_1/value
#sleep 1s
sleep 1
# back to original
echo "0" >/sys/class/gpio/gpio$gpio_0/value
echo "0" >/sys/class/gpio/gpio$gpio_1/value
}
# (ir mode)
ir_cut_disable() {
# pin_mux
echo "$gpio_0" >/sys/class/gpio/unexport
echo "$gpio_1" >/sys/class/gpio/unexport
echo "$gpio_0" >/sys/class/gpio/export
echo "$gpio_1" >/sys/class/gpio/export
# dir
echo "out" >/sys/class/gpio/gpio$gpio_0/direction
echo "out" >/sys/class/gpio/gpio$gpio_1/direction
# data, gpio_1: 1, gpio_0: 0 (ir mode)
echo "0" >/sys/class/gpio/gpio$gpio_0/value
echo "1" >/sys/class/gpio/gpio$gpio_1/value
#sleep 1s
sleep 1
# back to original
echo "0" >/sys/class/gpio/gpio$gpio_0/value
echo "0" >/sys/class/gpio/gpio$gpio_1/value
}
gpio_0=0
gpio_1=0
if [ $# -lt 2 ]; then
echo "usage : ./ircut_demo <chip> <mode>"
echo "for example:"
echo "ir mode : ./ircut_demo hi3516ev200 1"
else
if [ $1 = "hi3516ev200" ]; then
gpio_0=8
gpio_1=9
elif [ $1 = "hi3516ev300" ]; then
gpio_0=11
gpio_1=10
else
echo "wrong chipid: $1, please select: hi3516ev200 or hi3516ev300."
exit
fi
if [ $2 -eq 0 ]; then
echo "normal mode, ir_cut on"
ir_cut_enable >/dev/null
elif [ $2 -eq 1 ]; then
echo "ir mode, ir_cut off"
ir_cut_disable >/dev/null
else
echo "invalid mode, please slect 0 or 1."
fi
fi

1
general/package/hisilicon-osdrv-hi3516cv100/files/script/load_hisilicon 100755
View File

@ -0,0 +1 @@
#

0
general/package/hisilicon-osdrv-hi3516cv100/files/sensor/config/.dot 100644
View File

39
general/package/hisilicon-osdrv-hi3516cv100/hisilicon-osdrv-hi3516cv100.mk 100644
View File

@ -0,0 +1,39 @@
################################################################################
#
# hisilicon-osdrv-hi3516cv100
#
################################################################################
HISILICON_OSDRV_HI3516CV100_VERSION =
HISILICON_OSDRV_HI3516CV100_SITE =
HISILICON_OSDRV_HI3516CV100_LICENSE = MIT
HISILICON_OSDRV_HI3516CV100_LICENSE_FILES = LICENSE
define HISILICON_OSDRV_HI3516CV100_INSTALL_TARGET_CMDS
$(INSTALL) -m 755 -d $(TARGET_DIR)/etc/init.d
$(INSTALL) -m 755 -t $(TARGET_DIR)/etc/init.d $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3516cv100/files/script/S99hisilicon
$(INSTALL) -m 755 -d $(TARGET_DIR)/etc/sensors
# $(INSTALL) -m 644 -t $(TARGET_DIR)/etc/sensors $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3516cv100/files/sensor/config/*.ini
$(INSTALL) -m 755 -d $(TARGET_DIR)/lib/modules/4.9.37/hisilicon
# $(INSTALL) -m 644 -t $(TARGET_DIR)/lib/modules/4.9.37/hisilicon $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3516cv100/files/kmod/*.ko
# $(INSTALL) -m 644 -t $(TARGET_DIR)/lib/modules/4.9.37/hisilicon $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3516cv100/files/kmod/xxx.ko
$(INSTALL) -m 755 -d $(TARGET_DIR)/usr/bin
$(INSTALL) -m 755 -t $(TARGET_DIR)/usr/bin $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3516cv100/files/script/load_hisilicon
$(INSTALL) -m 755 -t $(TARGET_DIR)/usr/bin $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3516cv100/files/script/ircut_demo
$(INSTALL) -m 755 -d $(TARGET_DIR)/usr/lib/fonts
$(INSTALL) -m 644 -t $(TARGET_DIR)/usr/lib/fonts $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3516cv100/files/fonts/*.bin
$(INSTALL) -m 755 -d $(TARGET_DIR)/usr/lib/sensors
# $(INSTALL) -m 644 -t $(TARGET_DIR)/usr/lib/sensors $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3516cv100/files/sensor/*.so
$(INSTALL) -m 755 -d $(TARGET_DIR)/usr/lib
# $(INSTALL) -m 644 -t $(TARGET_DIR)/usr/lib/ $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3516cv100/files/lib/*.so
# $(INSTALL) -m 644 -t $(TARGET_DIR)/usr/lib/ $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3516cv100/files/lib/xxx.so
endef
$(eval $(generic-package))

16
general/package/hisilicon-osdrv-hi3516cv500/hisilicon-osdrv-hi3516cv500.mk
View File

@ -8,22 +8,6 @@ HISILICON_OSDRV_HI3516CV500_VERSION =
HISILICON_OSDRV_HI3516CV500_SITE =
HISILICON_OSDRV_HI3516CV500_LICENSE = MIT
HISILICON_OSDRV_HI3516CV500_LICENSE_FILES = LICENSE
HISILICON_OSDRV_HI3516CV500_INSTALL_STAGING = YES
define HISILICON_OSDRV_HI3516CV500_INSTALL_STAGING_CMDS
$(INSTALL) -m 755 -d $(STAGING_DIR)/usr/include/hisilicon
# $(INSTALL) -m 644 -t $(STAGING_DIR)/usr/include/hisilicon $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3516cv500/files/include/*
# $(INSTALL) -m 755 -d $(BUILD_DIR)/hisilicon-osdrv-hi3516cv500/include
# $(INSTALL) -m 644 -t $(BUILD_DIR)/hisilicon-osdrv-hi3516cv500/include $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3516cv500/files/include/*
# $(INSTALL) -m 755 -d $(BUILD_DIR)/hisilicon-osdrv-hi3516cv500/kmod
# $(INSTALL) -m 644 -t $(BUILD_DIR)/hisilicon-osdrv-hi3516cv500/kmod $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3516cv500/files/kmod/*.ko
# $(INSTALL) -m 755 -d $(BUILD_DIR)/hisilicon-osdrv-hi3516cv500/lib
# $(INSTALL) -m 644 -t $(BUILD_DIR)/hisilicon-osdrv-hi3516cv500/lib $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3516cv500/files/lib/*.so
endef
define HISILICON_OSDRV_HI3516CV500_INSTALL_TARGET_CMDS

16
general/package/hisilicon-osdrv-hi3516ev300/hisilicon-osdrv-hi3516ev300.mk
View File

@ -8,22 +8,6 @@ HISILICON_OSDRV_HI3516EV300_VERSION =
HISILICON_OSDRV_HI3516EV300_SITE =
HISILICON_OSDRV_HI3516EV300_LICENSE = MIT
HISILICON_OSDRV_HI3516EV300_LICENSE_FILES = LICENSE
HISILICON_OSDRV_HI3516EV300_INSTALL_STAGING = YES
define HISILICON_OSDRV_HI3516EV300_INSTALL_STAGING_CMDS
$(INSTALL) -m 755 -d $(STAGING_DIR)/usr/include/hisilicon
$(INSTALL) -m 644 -t $(STAGING_DIR)/usr/include/hisilicon $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3516ev300/files/include/*
# $(INSTALL) -m 755 -d $(BUILD_DIR)/hisilicon-osdrv-hi3516ev300/include
# $(INSTALL) -m 644 -t $(BUILD_DIR)/hisilicon-osdrv-hi3516ev300/include $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3516ev300/files/include/*
# $(INSTALL) -m 755 -d $(BUILD_DIR)/hisilicon-osdrv-hi3516ev300/kmod
# $(INSTALL) -m 644 -t $(BUILD_DIR)/hisilicon-osdrv-hi3516ev300/kmod $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3516ev300/files/kmod/*.ko
# $(INSTALL) -m 755 -d $(BUILD_DIR)/hisilicon-osdrv-hi3516ev300/lib
# $(INSTALL) -m 644 -t $(BUILD_DIR)/hisilicon-osdrv-hi3516ev300/lib $(BR2_EXTERNAL_HISILICON_PATH)/package/hisilicon-osdrv-hi3516ev300/files/lib/*.so
endef
define HISILICON_OSDRV_HI3516EV300_INSTALL_TARGET_CMDS

41
general/package/sigmastar-osdrv-ssc335/sigmastar-osdrv-ssc335.mk
View File

@ -8,47 +8,6 @@ SIGMASTAR_OSDRV_SSC335_VERSION =
SIGMASTAR_OSDRV_SSC335_SITE =
SIGMASTAR_OSDRV_SSC335_LICENSE = MIT
SIGMASTAR_OSDRV_SSC335_LICENSE_FILES = LICENSE
SIGMASTAR_OSDRV_SSC335_INSTALL_STAGING = YES
define SIGMASTAR_OSDRV_SSC335_INSTALL_STAGING_CMDS
$(INSTALL) -m 755 -d $(STAGING_DIR)/usr/include/sigmastar
$(INSTALL) -m 644 -t $(STAGING_DIR)/usr/include/sigmastar $(BR2_EXTERNAL_SIGMASTAR_PATH)/package/sigmastar-osdrv-ssc335/files/include/*.h
$(INSTALL) -m 755 -d $(STAGING_DIR)/usr/include/sigmastar/drivers/sensorif
$(INSTALL) -m 644 -t $(STAGING_DIR)/usr/include/sigmastar/drivers/sensorif $(BR2_EXTERNAL_SIGMASTAR_PATH)/package/sigmastar-osdrv-ssc335/files/include/drivers/sensorif/*.h
$(INSTALL) -m 755 -d $(STAGING_DIR)/usr/include/sigmastar/isp/ispahan
$(INSTALL) -m 644 -t $(STAGING_DIR)/usr/include/sigmastar/isp/ispahan $(BR2_EXTERNAL_SIGMASTAR_PATH)/package/sigmastar-osdrv-ssc335/files/include/isp/ispahan/*.h
$(INSTALL) -m 755 -d $(STAGING_DIR)/usr/include/sigmastar/isp/macaron
$(INSTALL) -m 644 -t $(STAGING_DIR)/usr/include/sigmastar/isp/macaron $(BR2_EXTERNAL_SIGMASTAR_PATH)/package/sigmastar-osdrv-ssc335/files/include/isp/macaron/*.h
$(INSTALL) -m 755 -d $(STAGING_DIR)/usr/include/sigmastar/isp/pudding
$(INSTALL) -m 644 -t $(STAGING_DIR)/usr/include/sigmastar/isp/pudding $(BR2_EXTERNAL_SIGMASTAR_PATH)/package/sigmastar-osdrv-ssc335/files/include/isp/pudding/*.h
# $(INSTALL) -m 755 -d $(BUILD_DIR)/usr/include/sigmastar
# $(INSTALL) -m 644 -t $(BUILD_DIR)/usr/include/sigmastar $(BR2_EXTERNAL_SIGMASTAR_PATH)/package/sigmastar-osdrv-ssc335/files/include/*.h
# $(INSTALL) -m 755 -d $(BUILD_DIR)/usr/include/sigmastar/drivers/sensorif
# $(INSTALL) -m 644 -t $(BUILD_DIR)/usr/include/sigmastar/drivers/sensorif $(BR2_EXTERNAL_SIGMASTAR_PATH)/package/sigmastar-osdrv-ssc335/files/include/drivers/sensorif/*.h
# $(INSTALL) -m 755 -d $(BUILD_DIR)/usr/include/sigmastar/isp/ispahan
# $(INSTALL) -m 644 -t $(BUILD_DIR)/usr/include/sigmastar/isp/ispahan $(BR2_EXTERNAL_SIGMASTAR_PATH)/package/sigmastar-osdrv-ssc335/files/include/isp/ispahan/*.h
# $(INSTALL) -m 755 -d $(BUILD_DIR)/usr/include/sigmastar/isp/macaron
# $(INSTALL) -m 644 -t $(BUILD_DIR)/usr/include/sigmastar/isp/macaron $(BR2_EXTERNAL_SIGMASTAR_PATH)/package/sigmastar-osdrv-ssc335/files/include/isp/macaron/*.h
# $(INSTALL) -m 755 -d $(BUILD_DIR)/usr/include/sigmastar/isp/pudding
# $(INSTALL) -m 644 -t $(BUILD_DIR)/usr/include/sigmastar/isp/pudding $(BR2_EXTERNAL_SIGMASTAR_PATH)/package/sigmastar-osdrv-ssc335/files/include/isp/pudding/*.h
# $(INSTALL) -m 755 -d $(BUILD_DIR)/sigmastar-osdrv-ssc335/kmod
# $(INSTALL) -m 644 -t $(BUILD_DIR)/sigmastar-osdrv-ssc335/kmod $(BR2_EXTERNAL_SIGMASTAR_PATH)/package/sigmastar-osdrv-ssc335/files/kmod/*.ko
# $(INSTALL) -m 755 -d $(BUILD_DIR)/sigmastar-osdrv-ssc335/lib
# $(INSTALL) -m 644 -t $(BUILD_DIR)/sigmastar-osdrv-ssc335/lib $(BR2_EXTERNAL_SIGMASTAR_PATH)/package/sigmastar-osdrv-ssc335/files/lib/*.so
endef
define SIGMASTAR_OSDRV_SSC335_INSTALL_TARGET_CMDS

16
general/package/xiongmai-osdrv-xm510/xiongmai-osdrv-xm510.mk
View File

@ -8,22 +8,6 @@ XIONGMAI_OSDRV_XM510_VERSION =
XIONGMAI_OSDRV_XM510_SITE =
XIONGMAI_OSDRV_XM510_LICENSE = MIT
XIONGMAI_OSDRV_XM510_LICENSE_FILES = LICENSE
XIONGMAI_OSDRV_XM510_INSTALL_STAGING = YES
define XIONGMAI_OSDRV_XM510_INSTALL_STAGING_CMDS
$(INSTALL) -m 755 -d $(STAGING_DIR)/usr/include/xiongmai
# $(INSTALL) -m 644 -t $(STAGING_DIR)/usr/include/xiongmai $(BR2_EXTERNAL_XIONGMAI_PATH)/package/xiongmai-osdrv-xm510/files/include/*
# $(INSTALL) -m 755 -d $(BUILD_DIR)/xiongmai-osdrv-xm510/include
# $(INSTALL) -m 644 -t $(BUILD_DIR)/xiongmai-osdrv-xm510/include $(BR2_EXTERNAL_XIONGMAI_PATH)/package/xiongmai-osdrv-xm510/files/include/*
# $(INSTALL) -m 755 -d $(BUILD_DIR)/xiongmai-osdrv-xm510/kmod
# $(INSTALL) -m 644 -t $(BUILD_DIR)/xiongmai-osdrv-xm510/kmod $(BR2_EXTERNAL_XIONGMAI_PATH)/package/xiongmai-osdrv-xm510/files/kmod/*.ko
# $(INSTALL) -m 755 -d $(BUILD_DIR)/xiongmai-osdrv-xm510/lib
# $(INSTALL) -m 644 -t $(BUILD_DIR)/xiongmai-osdrv-xm510/lib $(BR2_EXTERNAL_XIONGMAI_PATH)/package/xiongmai-osdrv-xm510/files/lib/*.so
endef
define XIONGMAI_OSDRV_XM510_INSTALL_TARGET_CMDS

70
general/package/xiongmai-osdrv-xm530/files/include/isp/mpi_ae.h
View File

@ -1,70 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : mpi_ae.h
Version : Initial Draft
Author : XM Isp software group
Created : 2015/6/27
Description : The common data type defination
Function List :
History :
1.Date : 2015/6/27
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef __MPI_AE_H__
#define __MPI_AE_H__
#include "xm_comm_isp.h"
#include "xm_comm_3a.h"
#include "xm_ae_comm.h"
/* The interface of ae lib register to isp. */
XM_S32 XM_MPI_AE_Register(ISP_DEV IspDev, ALG_LIB_S *pstAeLib);
XM_S32 XM_MPI_AE_UnRegister(ISP_DEV IspDev, ALG_LIB_S *pstAeLib);
/* The callback function of sensor register to ae lib. */
XM_S32 XM_MPI_ISP_AELibRegCallBack(ISP_DEV IspDev, ALG_LIB_S *pstAeLib, ISP_AE_REGISTER_S *pstRegister);
XM_S32 XM_MPI_ISP_AELibUnRegCallBack(ISP_DEV IspDev, ALG_LIB_S *pstAeLib);
XM_S32 XM_MPI_AE_SensorRegCallBack(ISP_DEV IspDev, ALG_LIB_S *pstAeLib, SENSOR_ID SensorId,
AE_SENSOR_REGISTER_S *pstRegister);
XM_S32 XM_MPI_AE_SensorUnRegCallBack(ISP_DEV IspDev, ALG_LIB_S *pstAeLib, SENSOR_ID SensorId);
XM_S32 XM_MPI_ISP_SetExposureAttr(ISP_DEV IspDev, const ISP_EXPOSURE_ATTR_S *pstExpAttr);
XM_S32 XM_MPI_ISP_GetExposureAttr(ISP_DEV IspDev, ISP_EXPOSURE_ATTR_S *pstExpAttr);
XM_S32 XM_MPI_ISP_SetAERouteAttr(ISP_DEV IspDev, const ISP_AE_ROUTE_S *pstAERouteAttr);
XM_S32 XM_MPI_ISP_GetAERouteAttr(ISP_DEV IspDev, ISP_AE_ROUTE_S *pstAERouteAttr);
XM_S32 XM_MPI_ISP_QueryInnerStateInfo(ISP_DEV IspDev, ISP_INNER_STATE_INFO_S *pstInnerStateInfo);
XM_S32 XM_MPI_ISP_SetAICalibrate(ISP_DEV IspDev, const ISP_AI_CALIBRATE_S *pstAICalibrate);
XM_S32 XM_MPI_ISP_GetAICalibrate(ISP_DEV IspDev, ISP_AI_CALIBRATE_S *pstAICalibrate);
XM_S32 XM_MPI_ISP_SetIrisAttr(ISP_DEV IspDev, const ISP_IRIS_ATTR_S *pstIrisAttr);
XM_S32 XM_MPI_ISP_GetIrisAttr(ISP_DEV IspDev, ISP_IRIS_ATTR_S *pstIrisAttr);
XM_S32 XM_MPI_ISP_SetExpStaInfo(ISP_DEV IspDev, ISP_EXP_STA_INFO_S *pstExpStatistic);
XM_S32 XM_MPI_ISP_GetExpStaInfo(ISP_DEV IspDev, ISP_EXP_STA_INFO_S *pstExpStatistic);
XM_S32 XM_MPI_ISP_SetSlowFrameRate(ISP_DEV IspDev, XM_U8 u8Value);
XM_S32 XM_MPI_ISP_GetSlowFrameRate(ISP_DEV IspDev, XM_U8 *pu8Value);
XM_S32 XM_MPI_ISP_GetStatisticsAE(ISP_DEV IspDev, ISP_AE_STAT_S *pstAeStat);
XM_S32 XM_MPI_ISP_GetStatisticsAEV2(ISP_DEV IspDev, ISP_AE_STAT_3_S *pstAeStatV2);
XM_S32 XM_MPI_AE_SetFrameRate(ISP_DEV IspDev, XM_U8 u8Fps);
//¿Éµ÷½Ú¹â²¹¹âLED
XM_S32 XM_MPI_AE_SetVarLEDAttr(ISP_DEV IspDev,const ISP_AE_VARLED_REGISTER_S *pstVarLED);
XM_S32 XM_MPI_AE_GetVarLEDAttr(ISP_DEV IspDev, ISP_AE_VARLED_REGISTER_S *pstVarLED);
#endif

53
general/package/xiongmai-osdrv-xm530/files/include/isp/mpi_awb.h
View File

@ -1,53 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : mpi_awb.h
Version : Initial Draft
Author : XM Isp software group
Created : 2015/6/27
Description : The common data type defination
Function List :
History :
1.Date : 2015/6/27
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef __MPI_AWB_H__
#define __MPI_AWB_H__
#include "xm_comm_isp.h"
#include "xm_comm_3a.h"
#include "xm_awb_comm.h"
/* The interface of awb lib register to isp. */
XM_S32 XM_MPI_AWB_Register(ALG_LIB_S *pstAwbLib);
XM_S32 XM_MPI_AWB_UnRegister(ALG_LIB_S *pstAwbLib);
/* The callback function of sensor register to awb lib. */
XM_S32 XM_MPI_AWB_SensorRegCallBack(ALG_LIB_S *pstAwbLib, SENSOR_ID SensorId,
AWB_SENSOR_REGISTER_S *pstRegister);
XM_S32 XM_MPI_AWB_SensorUnRegCallBack(ALG_LIB_S *pstAwbLib, SENSOR_ID SensorId);
XM_S32 XM_MPI_ISP_AWBLibRegCallBack(ALG_LIB_S *pstAWBLib,
ISP_AWB_REGISTER_S *pstRegister);
XM_S32 XM_MPI_ISP_SetWBAttr(const ISP_WB_ATTR_S *pstWBAttr);
XM_S32 XM_MPI_ISP_GetWBAttr(ISP_WB_ATTR_S *pstWBAttr);
XM_S32 XM_MPI_ISP_SetCCMAttr(const ISP_COLORMATRIX_ATTR_S *pstCCMAttr);
XM_S32 XM_MPI_ISP_GetCCMAttr(ISP_COLORMATRIX_ATTR_S *pstCCMAttr);
XM_S32 XM_MPI_ISP_QueryWBInfo(ISP_WB_INFO_S *pstWBInfo);
XM_S32 XM_MPI_ISP_QueryWBInfo2(ISP_WB_INFO_S_V2 *pstWBInfo);
XM_S32 XM_MPI_AWB_GetStatistics(ISP_DEV IspDev, ISP_WB_BAYER_STATISTICS_S *pstStat);
XM_S32 XM_MPI_ISP_SetWBCalAttr(const ISP_AWB_CALIBRATION_V2_S *pstWBCalAttr);
XM_S32 XM_MPI_ISP_GetWBCalAttr(ISP_AWB_CALIBRATION_V2_S *pstWBCalAttr);
#endif

180
general/package/xiongmai-osdrv-xm530/files/include/isp/mpi_isp.h
View File

@ -1,180 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : mpi_isp.h
Version : Initial Draft
Author : XM Isp software group
Created : 2015/6/27
Description : The common data type defination
Function List :
History :
1.Date : 2015/6/27
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef __MPI_ISP_H__
#define __MPI_ISP_H__
#include "xm_comm_isp.h"
#include "xm_comm_sns.h"
#include "xm_comm_3a.h"
#include "xm_comm_video.h"
/* Firmware Main Operation */
XM_S32 XM_MPI_ISP_Init(ISP_DEV IspDev);
XM_S32 XM_MPI_ISP_MemInit(ISP_DEV IspDev);
XM_S32 XM_MPI_ISP_Run(ISP_DEV IspDev);
XM_S32 XM_MPI_ISP_Exit(ISP_DEV IspDev);
/*******************************************************************************************
函数名称: XM_MPI_ISP_SetVsyncIntEn
函数功能: 设置输入场中断使能
输入参数: IspDev: IspDev
u8Mode:
0:Disable(强制)
1:Enable(强制)
2:恢复(强制关 之前的状态)
输出参数: 无
返回参数: -1: 失败
0: 成功
*******************************************************************************************/
XM_S32 XM_MPI_ISP_SetVsyncIntEn(ISP_DEV IspDev, XM_U8 u8Mode);
XM_S32 XM_MPI_ISP_GetChnAttr(ISP_CHN_ATTR_S *pstChnAttr);
XM_S32 XM_MPI_ISP_SetChnAttr(ISP_CHN_ATTR_S *pstChnAttr);
XM_S32 XM_MPI_ISP_GetFrame(VIDEO_FRAME_INFO_S *pstFrameInfo);
XM_S32 XM_MPI_ISP_ReleaseFrame(VIDEO_FRAME_INFO_S *pstFrameInfo);
XM_S32 XM_MPI_ISP_SensorRegCallBack(SENSOR_ID SensorId, const ISP_SENSOR_REGISTER_S *pstRegister);
XM_S32 XM_MPI_ISP_SensorUnRegCallBack(SENSOR_ID SensorId);
XM_S32 XM_MPI_ISP_SetModuleControl(const ISP_MODULE_CTRL_U *punModCtrl);
XM_S32 XM_MPI_ISP_GetModuleControl(ISP_MODULE_CTRL_U *punModCtrl);
XM_S32 XM_MPI_ISP_SetGammaAttr(const ISP_GAMMA_ATTR_S *pstGammaAttr);
XM_S32 XM_MPI_ISP_GetGammaAttr(ISP_GAMMA_ATTR_S *pstGammaAttr);
XM_S32 XM_MPI_ISP_SetBlackLevelAttr(const ISP_BLACKLVL_ATTR_S *pstBlackLevel);
XM_S32 XM_MPI_ISP_GetBlackLevelAttr(ISP_BLACKLVL_ATTR_S *pstBlackLevel);
/*******************************************************************************************
函数名称: XM_MPI_ISP_SetRegister
函数功能: 配置寄存器为指定值
输入参数: u32Addr: 需要操作的地址
u32Value: 该地址需要配置的值
输出参数: 无
返回参数: -1: 失败
0: 成功
注：
如带系统，会重新映射
*******************************************************************************************/
XM_S32 XM_MPI_ISP_SetRegister(XM_U32 u32Addr, XM_U32 u32Value);
/*******************************************************************************************
函数名称: XM_MPI_ISP_GetRegister
函数功能: 获取寄存器的值
输入参数: u32Addr: 需要操作的地址
pu32Value: 存放读取到的值
输出参数: 无
返回参数: -1: 失败
0: 成功
注：
如带系统，会重新映射
*******************************************************************************************/
XM_S32 XM_MPI_ISP_GetRegister(XM_U32 u32Addr, XM_U32 *pu32Value);
XM_S32 XM_MPI_ISP_SetPubAttr(ISP_DEV IspDev, const ISP_PUB_ATTR_S *pstPubAttr);
XM_S32 XM_MPI_ISP_GetPubAttr(ISP_DEV IspDev, ISP_PUB_ATTR_S *pstPubAttr);
XM_S32 XM_MPI_ISP_SetSaturationAttr(const ISP_SATURATION_ATTR_S *pstSatAttr);
XM_S32 XM_MPI_ISP_GetSaturationAttr(ISP_SATURATION_ATTR_S *pstSatAttr);
// DPC
XM_S32 XM_MPI_ISP_SetStDefectPixelAttr(ISP_STDPC_ATTR_S *pstStDPAttr);
XM_S32 XM_MPI_ISP_GetStDefectPixelAttr(ISP_STDPC_ATTR_S *pstStDPAttr);
XM_S32 XM_MPI_ISP_SetDyDefectPixelAttr(ISP_DYDPC_ATTR_S *pstDyDPAttr);
XM_S32 XM_MPI_ISP_GetDyDefectPixelAttr(ISP_DYDPC_ATTR_S *pstDyDPAttr);
XM_S32 XM_MPI_ISP_SetSharpenAttr(const ISP_SHARPEN_ATTR_S *pstSharpenAttr);
XM_S32 XM_MPI_ISP_GetSharpenAttr(ISP_SHARPEN_ATTR_S *pstSharpenAttr);
XM_S32 XM_MPI_ISP_GetSharpenV2Attr(ISP_SHARPENV2_ATTR_S *pstSharpenAttr);
XM_S32 XM_MPI_ISP_SetSharpenV2Attr(const ISP_SHARPENV2_ATTR_S *pstSharpenAttr);
XM_S32 XM_MPI_ISP_SetNRAttr(const ISP_2DNR_ATTR_S *pstNRAttr);
XM_S32 XM_MPI_ISP_GetNRAttr(ISP_2DNR_ATTR_S *pstNRAttr);
XM_S32 XM_MPI_ISP_Set3DNrAttr(const ISP_3DNR_ATTR_S *pstNRAttr);
XM_S32 XM_MPI_ISP_Get3DNrAttr(ISP_3DNR_ATTR_S *pstNRAttr);
XM_S32 XM_MPI_ISP_Set3DNrV2Attr(const ISP_3DNRV2_ATTR_S *pstNRAttr);
XM_S32 XM_MPI_ISP_Get3DNrV2Attr(ISP_3DNRV2_ATTR_S *pstNRAttr);
XM_S32 XM_MPI_ISP_GetNrInfo(ISP_NR_INFO_S *pstNRInfo);
XM_S32 XM_MPI_ISP_SetCSCAttr(const ISP_CSC_ATTR_S *pstCSCAttr);
XM_S32 XM_MPI_ISP_GetCSCAttr(ISP_CSC_ATTR_S *pstCSCAttr);
// 去伪彩
XM_S32 XM_MPI_ISP_SetAntiFalseColorAttr(const ISP_ANTI_FALSECOLOR_S *pstAntiFC);
XM_S32 XM_MPI_ISP_GetAntiFalseColorAttr(ISP_ANTI_FALSECOLOR_S *pstAntiFC);
XM_S32 XM_MPI_ISP_SetChromaAttr(ISP_CHROMA_ATTR_S *pstChromaAttr);
XM_S32 XM_MPI_ISP_GetChromaAttr(ISP_CHROMA_ATTR_S *pstChromaAttr);
XM_S32 XM_MPI_ISP_FpnInit(XM_U8 u8Mode);
XM_S32 XM_MPI_ISP_AWB_REFRESH(ISP_DEV IspDev);
//*pu32AeErr: err*64
XM_S32 XM_MPI_ISP_StabStats(XM_U32 *pu32AeErr);
XM_S32 XM_MPI_ISP_SetDRCAttr(ISP_DEV IspDev, const ISP_DRC_ATTR_S *pstDRC);
XM_S32 XM_MPI_ISP_GetDRCAttr(ISP_DEV IspDev, ISP_DRC_ATTR_S *pstDRC);
XM_S32 XM_MPI_ISP_SetDeFogAttr(ISP_DEV IspDev, const ISP_DEFOG_ATTR_S *pstDefogAttr);
XM_S32 XM_MPI_ISP_GetDeFogAttr(ISP_DEV IspDev, ISP_DEFOG_ATTR_S *pstDefogAttr);
// 注册场中断触发的回调函数
XM_S32 XM_MPI_ISP_SetVsyncCallback(ISP_DEV IspDev, ISP_VSYNC_CALBAK_S *pstVsyncCalBak);
XM_S32 XM_MPI_ISP_GetVsyncCallback(ISP_DEV IspDev, ISP_VSYNC_CALBAK_S *pstVsyncCalBak);
/*******************************************************************************************
函数名称: XM_MPI_ISP_Memncpy
函数功能: 内存拷贝（指定字节数）
输入参数: pSrc: 原始数据内存地址
u32Num: 数据的大小（字节）
输出参数: pDst: 拷贝的目标地址
返回参数: -1: 失败
0: 成功
*******************************************************************************************/
XM_S32 XM_MPI_ISP_Memncpy(XM_U8 *pDst, XM_U8 *pSrc, XM_U32 u32Num);
/*******************************************************************************************
函数名称: XM_MPI_ISP_Memset
函数功能: 指定内存，指定大小，配置成指定值
输入参数: pu8Addr: 需要操作的数据地址
u8Ch: 指定内存需要配置成的值
u32Num: 地址大小
输出参数: 无
返回参数: -1: 失败
0: 成功
*******************************************************************************************/
XM_VOID XM_MPI_ISP_Memset(XM_U8 *pu8Addr,XM_U8 u8Ch, XM_U32 u32Num);
XM_S32 XM_MPI_ISP_GetDCIAttr(ISP_DEV IspDev, ISP_DCI_ATTR_S *pstDciAttr);
XM_S32 XM_MPI_ISP_SetDCIAttr(ISP_DEV IspDev, ISP_DCI_ATTR_S *pstDciAttr);
#endif /*__MPI_ISP_H__ */

90
general/package/xiongmai-osdrv-xm530/files/include/isp/mpi_phyvi.h
View File

@ -1,90 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : mpi_mipi.h
Version : Initial Draft
Author : XM Isp software group
Created : 2015/6/27
Description : The common data type defination
Function List :
History :
1.Date : 2015/6/27
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef __MPI_MIPI_H__
#define __MPI_MIPI_H__
#include "xm_defines.h"
#include "xm_common.h"
typedef struct _mipi_dev_attr_s
{
XM_MIPI_LANE lane; /* MIPI lane num */
XM_SENSOR_BWIDE depth; /* Depth: 8/10/12/ bit */
XM_U32 snsMpInclk; //送给sensor的mclk时钟
XM_U32 snsMpOutclk; //sensor输出的mipi时钟
XM_U32 snsAllLine; //sensor输出总行数
XM_U32 snsAllPixs; //sensor输出总点数
XM_U32 snsActiveLine; //sensor输出有效行数
XM_U32 snsActivePixs; //sensor输出有效点数
XM_U32 bMpDvpclk; //芯片内部并行取点时钟
XM_U32 bAllPixs; //芯片内部并行取点总点数
XM_U32 delay; //mipi内部delay
XM_U32 MipiCtrl; //[23:16]:ctrl_dly(检测 sot时间 delay:ctrl_dly*2);[7:0]:sot_data(B8);[8]:clk_ctrl(0:CKp;1:CKn) [15:9]:保留
}MIPI_DEV_ATTR_S;
typedef struct _combo_dev_attr_s
{
XM_SENSOR_CONT input_mode;
MIPI_DEV_ATTR_S mipi_attr;
}COMBO_DEV_ATTR_S;
typedef enum xm_mipi_cmd
{
MIPI_SET_DEV_ATTR = 0,
MIPI_SET_OUTPUT_CLK_EDGE = 1,
MIPI_RESET_MIPI = 2,
MIPI_UNRESET_MIPI = 3,
MIPI_SET_RUN = 4,
// MIPI_RESET_SENSOR = 5,
// MIPI_UNRESET_SENSOR = 6,
MIPI_BUTT
}MIPI_CMD;
typedef struct _xm_mipi_ck_s
{
unsigned int mipi_ck_div;
unsigned int mipi_ck_count;
unsigned int mipi_ck_all_v;
unsigned int mipi_ck_all_h;
unsigned int mipi_ck_en;
}MIPI_CK_CMD;
XM_S32 XM_MPI_MIPI_GetDevAttr(ISP_DEV IspDev, COMBO_DEV_ATTR_S *pstComboDevAttr);
XM_S32 XM_MPI_MIPI_SetDevAttr(ISP_DEV IspDev, MIPI_CMD enCmd, const COMBO_DEV_ATTR_S *pstComboDevAttr);
/*****************************************************************************************************
鍑芥暟鍚嶇О: XM_MPI_MIPI_RefreshFV
鍑芥暟鍔熻兘: MIPI寮哄埗鍒锋柊琛屽満淇″彿
杈撳叆鍙傛暟: u32DelayMs:鍒锋柊鏃堕棿(ms)
>0: 閰嶇疆鐨勬椂闂<EFBFBD>
0: 鍐呴儴鑷<EFBFBD>姩鍐冲畾
u32TotalSizeV
>0: 鎬昏<EFBFBD>鏁<EFBFBD>
=0: 浠呭埛鏂颁俊鍙<EFBFBD>
杈撳嚭鍙傛暟: 鏃<EFBFBD>
杩斿洖鍙傛暟: 0: 鎴愬姛
-1: 澶辫触
*****************************************************************************************************/
XM_S32 XM_MPI_MIPI_RefreshFV(XM_U32 u32DelayMs, XM_U32 u32TotalSizeV);
#endif /*__MPI_ISP_H__ */

43
general/package/xiongmai-osdrv-xm530/files/include/isp/mpi_vda.h
View File

@ -1,43 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : mpi_vda.h
Version : Initial Draft
Author : XM Isp software group
Created : 2015/6/27
Description : The common data type defination
Function List :
History :
1.Date : 2015/6/27
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef __MPI_VDA_H__
#define __MPI_VDA_H__
#include "xm_comm_vda.h"
XM_S32 XM_MPI_VDA_CreateChn(VDA_CHN VdaChn, const VDA_CHN_ATTR_S *pstAttr);
XM_S32 XM_MPI_VDA_DestroyChn(VDA_CHN VdaChn);
XM_S32 XM_MPI_VDA_GetChnAttr(VDA_CHN VdaChn, VDA_CHN_ATTR_S *pstAttr);
XM_S32 XM_MPI_VDA_SetChnAttr(VDA_CHN VdaChn, const VDA_CHN_ATTR_S *pstAttr);
XM_S32 XM_MPI_VDA_StartRecvPic(VDA_CHN VdaChn);
XM_S32 XM_MPI_VDA_StopRecvPic(VDA_CHN VdaChn);
XM_S32 XM_MPI_VDA_GetData(VDA_CHN VdaChn, VDA_DATA_S *pstVdaData, XM_S32 s32MilliSec);
XM_S32 XM_MPI_VDA_ReleaseData(VDA_CHN VdaChn, const VDA_DATA_S* pstVdaData);
XM_S32 XM_MPI_VDA_Query(VDA_CHN VdaChn, VDA_CHN_STAT_S *pstChnStat);
XM_S32 XM_MPI_VDA_UpdateRef(VDA_CHN VdaChn, const VIDEO_FRAME_INFO_S *pstRefFrame);
#endif /* End of #ifndef __MPI_VDA_H__ */

37
general/package/xiongmai-osdrv-xm530/files/include/isp/mpi_vdam.h
View File

@ -1,37 +0,0 @@
#ifndef _MPI_VDAM_H_
#define _MPI_VDAM_H_
#include "xm_comm_vdam.h"
//#include "ispMsg.h"
#define TOTAL_VI_CHN_NUM 1
void XM_MPI_VDA_Setmovblefalg(XM_U8 channel,XM_U8 enble);
void XM_MPI_VDA_Getmovblefalg(XM_U8 channel,XM_U8 *enble);
void XM_MPI_VDA_SetMovMark(XM_U8 channel,VDA_MOTION_MOVE_RESULT *pstInfo);
void XM_MPI_VDA_GetMovMark(XM_U8 channel,VDA_MOTION_MOVE_RESULT *rstInfo);
void XM_MPI_VDA_Setshbleflag(XM_U8 channel,XM_U8 enble);
void XM_MPI_VDA_Getshbleflag(XM_U8 channel,XM_U8 *enble);
void XM_MPI_VDA_SetShdMark(XM_U8 channel,XM_U8 *shmark);
void XM_MPI_VDA_GetShdMark(XM_U8 channel,XM_U8 *shdmark);
int XM_MPI_VDA_SetMovAttr(XM_U8 channel,VDA_MOTION_MOVE_INIT *pstApInfo);
void XM_MPI_VDA_GetMovAttr(XM_U8 channel,VDA_MOTION_MOVE_INIT* gstApInfo);
void XM_MPI_VDA_CreatChn(XM_U8 VdaChn);
void XM_MPI_VDA_DestroyChn(XM_U8 VdaChn);
int XM_MPI_VDA_SetShAttr(XM_U8 channel,VDA_MOTION_SHELTER_INIT* pstApInfo);
int XM_MPI_VDA_GetShAttr(XM_U8 channel,VDA_MOTION_SHELTER_INIT* pstApInfo);
int XM_MPI_VDA_GetMovData(XM_U8 channel,VDA_MOTION_MOVE_RESULT* pstApInfo);
void XM_MPI_VDA_AfApinit(void);
int XM_MPI_VDA_Afgetdata(XM_U32 *rData);
int XM_MPI_VDA_VdaApInit(XM_U8 channel);
XM_U32 XM_MPI_VDA_VdaMovCmd(XM_U8 channel,VDA_MOTION_MOVE_RECDATA *pstApInfo);
int XM_MPI_VDA_VdaShCmd(XM_U8 channel,VDA_MOTION_SHELTER_RECDATA *pstApInfo);
int XM_MPI_VDA_VdaApiCmd(XM_U8 channel,ISP_AE_STAT_2_S* pstApInfo);
#endif

81
general/package/xiongmai-osdrv-xm530/files/include/isp/mpi_venctx.h
View File

@ -1,81 +0,0 @@
#ifndef __MPI_VENCTX_H__
#define __MPI_VENCTX_H__
#include "xm_type.h"
#include "xm_common.h"
typedef enum {
PCLK_36M = 0,
PCLK_74x25M = 1,
PCLK_117M = 2,
PCLK_148x5M = 3,
PCLK_42M = 4,
PCLK_144M = 5,
PCLK_37x125M = 6,
} VENC_PCLK;
typedef struct xm_VENC_SCALER_ATTR {
XM_U8 u8EnableH;
XM_U8 u8EnableV;
XM_U16 u16RatioH; // 1024:1 >1024:Up <1024:Dn
XM_U16 u16RatioV; // 1024:1 >1024:Up <1024:Dn(XM350 just Dn)
SIZE_S stDestSize;
VENC_PCLK enPclk;
}VENC_SCALER_ATTR;
typedef struct xm_VENC_TX_ATTR {
XM_U32 u32TestMode;
XM_U32 u32BlankVal_P;
XM_U32 u32SyncVal_P;
XM_U32 u32CSyncVal_P;
XM_U32 u32SubCarrierPar_P;
XM_U32 u32YColorGain_P;
XM_U32 u32BlankVal_N;
XM_U32 u32SyncVal_N;
XM_U32 u32CSyncVal_N;
XM_U32 u32SubCarrierPar_N;
XM_U32 u32YColorGain_N;
}VENC_TX_ATTR;
typedef struct xm_VENC_TX_FUN {
XM_S32 (*pFun_AHD)(XM_U8 u8StdMode);
XM_S32 (*pFun_CVI)(XM_U8 u8StdMode);
XM_S32 (*pFun_TVI)(XM_U8 u8StdMode);
XM_S32 (*pFun_CVBS)(XM_U8 u8StdMode);
}VENC_TX_FUN;
XM_S32 XM_MPI_VENC_SetScaler(const VENC_SCALER_ATTR *pstVenAttr);
XM_S32 XM_MPI_VENC_GetScaler(VENC_SCALER_ATTR *pstVenAttr);
/**********************************************************************
函数功能: 配置色同步
输入参数: u8BurstMode: 0 No CSync
1 have CSync
u8ColorMode: 0 BW
1 Color
输出参数: 无
返回参数: 0: Success
-1: Failure
**********************************************************************/
XM_S32 XM_MPI_VENC_SetColor(XM_U8 u8BurstMode, XM_U8 u8ColorMode);
/***************************************************************************
函数功能: 编码模式(Tx) 配置
输入参数: u8VencMode: 0:AHD 1:CVI 2:TVI
u8VstdType: 1:PAL 2:NTSC
u8RsltType: 0: 720P 1:1080P 2:960P 3:3M ...
输出参数: 无
返回参数: 0: 成功
-1: 出错
Note: Lycai
****************************************************************************/
XM_S32 XM_MPI_VENCTX_SetMode(XM_U8 u8VencMode, XM_U8 u8VstdType, XM_U8 u8RsltType);
#endif

185
general/package/xiongmai-osdrv-xm530/files/include/isp/mpi_xmisp.h
View File

@ -1,185 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm_type.h
Version : Initial Draft
Author : XM Isp software group
Created : 2017/04/07
Description : The common data type defination
Function List :
History :
1.Date : 2017/04/07
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef __MPI_XMISP_H__
#define __MPI_XMISP_H__
typedef struct xmIR_DNC_ATTR_s
{
int s32ColorExp; // <s32ColorExp: to Color Mode
int s32ColorDlt;
int s32ColorDlt2;
int s32BwExp; // >s32BwExp: to BW Mode
}IR_DNC_ATTR_S;
typedef struct xmIR_DNC_INFO_s
{
#if(defined SOC_NONE) || (defined CHIPID_XM530)
int s32Data[16];
#else
int s32Data[6];
#endif
}IR_DNC_INFO_S;
typedef enum {
tFALSE = 0,
tTRUE = 1,
} tBOOL;
typedef struct xmIR_FUNC_S
{
/**************************************
函数功能: 控制灯板光源
输入参数: u8Mode
0: 关闭
1: 打开
返回参数: -1: 出错
0: 操作完成
1: 操作无效
**************************************/
int(*pfn_led_ctrl)(unsigned char u8Mode);
/**************************************
函数功能: 获取灯板状态
输入参数: 无
输出参数: *ps32Mode: 0:Auto 1:Manual
* ps32State: 0:Close 1:Open
返回参数: -1: 出错
0: 成功
**************************************/
int(*pfn_led_get)(int *ps32Mode, int* ps32State);
/**************************************
函数功能: 日夜状态获取
输入参数: *ps32State: 0: Day 1:Night
输出参数: 无
返回参数: -1: 出错
0: 成功
**************************************/
int(*pfn_dnStatusExt_get)(int* ps32State);
} IR_FUNC_S;
typedef struct xmIR_CTRL_ATTR_S
{
unsigned char u8Delay2Color; // (s)
unsigned char u8Delay2Bw; // (s)
unsigned char u8DelayLedReOpen; // (s)
unsigned char u8Mode; // 0: No PhotoR 1: Have PhotoR 2: No PhotoR_V2 3: Have PhotoR_V2
unsigned short u16PeriodMs; // 调用周期(ms)
} IR_CTRL_ATTR_S;
/*********************************************************************************
函数功能: 获取日夜状态
输入参数: u8DnNow: 当前日夜模式(实际生效)
0: 彩色
1: 黑白
pstIrDncAttr
s32ColorExp: <=该值进入彩色模式
s32ColorDlt: >=该值进入彩色模式
s32ColorDlt2: >=该值进入彩色模式(Example: 50)
s32BwExp: >=该值进入黑白模式
输出参数: 无
返回参数: -1: 出错
0: 彩色
1: 黑白
*********************************************************************************/
int XM_MPI_IR_GetDNCStatus(unsigned char u8DnNow, IR_DNC_ATTR_S* pstIrDncAttr);
/*********************************************************************************
函数功能: 获取统计信息
输入参数: 无
输出参数: pstDncInfo: 统计信息
返回参数: -1: 出错
0: 彩色
1: 黑白
*********************************************************************************/
int XM_MPI_IR_GetInfo(IR_DNC_INFO_S *pstDncInfo);
/*********************************************************************************
函数功能: 注册灯板控制接口
输入参数: pstRegister: 指向接口地址
输出参数: 无
返回参数: -1: 出错
0: 成功
*********************************************************************************/
int XM_MPI_IR_FunCallBack(IR_FUNC_S *pstRegister);
/*********************************************************************************
函数功能: 配置控制参数
输入参数: pstCtrlAttr: 指向参数属性
输出参数: 无
返回参数: -1: 出错
0: 成功
*********************************************************************************/
int XM_MPI_IR_SetCtrlAttr(IR_CTRL_ATTR_S *pstCtrlAttr);
/*********************************************************************************
函数功能: 获取控制参数
输入参数: 无
输出参数: pstCtrlAttr: 指向参数属性
返回参数: -1: 出错
0: 成功
*********************************************************************************/
int XM_MPI_IR_GetCtrlAttr(IR_CTRL_ATTR_S *pstCtrlAttr);
/*********************************************************************************
函数功能: 切换模式
输入参数: u8Mode:
0: IR
1: WL
输出参数: 无
返回参数: -1: 出错
0: 成功
*********************************************************************************/
XM_S32 XM_MPI_IR_SwitchMode(XM_U8 u8Mode);
/*************************************************************************
函数功能: OSD 调试打印使能
输入参数: bEnable:
0: Close
1: Open
输出参数: 无
返回参数: 0: 成功
其他: 出错
*************************************************************************/
int XM_MPI_DBG_En(tBOOL bEnable);
/*************************************************************************
函数功能: OSD 调试打印
输入参数: u8Num: 打印数据个数
*pu32Data: 指向打印数据
依次在第1,2,3...u8Num行
输出参数: 无
返回参数: 0: 成功
其他: 出错
*************************************************************************/
int XM_MPI_DBG_Task(unsigned char u8Num, unsigned int *pu32Data);
/*************************************************************************
函数功能: OSD 调试释放内存
输入参数: 无
输出参数: 无
返回参数: 无
*************************************************************************/
int XM_MPI_DBG_Release(XM_VOID);
#endif /* __MPI_XMISP_H__ */

298
general/package/xiongmai-osdrv-xm530/files/include/isp/xm_ae_comm.h
View File

@ -1,298 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm_ae_common.h
Version : Initial Draft
Author : XM Isp software group
Created : 2015/6/27
Description : The common data type defination
Function List :
History :
1.Date : 2015/6/27
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef __XM_AE_COMM_H__
#define __XM_AE_COMM_H__
#include "xm_type.h"
#define XM_AE_LIB_NAME "xm_ae_lib"
#define XM_AWB_LIB_NAME "xm_awb_lib"
/************************** ae ctrl cmd **************************************/
typedef enum xm_AE_CTRL_CMD_E
{
AE_DEBUG_ATTR_SET,
AE_DEBUG_ATTR_GET,
AE_CTRL_BUTT,
} AE_CTRL_CMD_E;
typedef struct xm_AE_DBG_ATTR_S
{
XM_BOOL bAeBypass;
XM_BOOL bFrameEndUpdateMode;
XM_U32 u32MaxAgain;
XM_U32 u32MinAgin;
XM_U32 u32MaxDgain;
XM_U32 u32MinDgain;
XM_U32 u32MaxIspDgain;
XM_U32 u32MinIspDgain;
XM_U32 u32MaxIntTime;
XM_U32 u32MinIntTime;
XM_U32 u32Compensation;
#if 0
XM_U32 BlackLevel_R;
XM_U32 BlackLevel_Gr;
XM_U32 BlackLevel_Gb;
XM_U32 BlackLevel_B;
#endif
XM_U32 u32Hist01;
XM_U32 u32Hist12;
XM_U32 u32Hist34;
XM_U32 u32Hist45;
XM_BOOL bManualExposureEn;
XM_BOOL bManualAgainEn;
XM_BOOL bManualDgainEn;
XM_BOOL bManualIspDgainEn;
XM_U32 u32ManualExposureLines;
XM_U32 u32ManualAgain;
XM_U32 u32ManualDgain;
XM_U32 u32ManualIspDgain;
XM_U32 au32AeWeights[255];
}AE_DBG_ATTR_S;
typedef struct xm_AE_DBG_STATUS_S
{
XM_U32 u32FrmNumBgn;
XM_U32 u32FullLines;
XM_U32 u32IntTime;
XM_U32 u32Again;
XM_U32 u32AgainShift;
XM_U32 u32Dgain;
XM_U32 u32DgainShift;
XM_U32 u32IspDgain;
XM_U32 u32IspDgainShift;
XM_U32 u32Exposure;
XM_U32 u32Increment;
XM_U32 u32HistBalance;
XM_S32 u32HistError;
XM_U32 u32ExpoureStep;
XM_U32 u32FrmNumEnd;
}AE_DBG_STATUS_S;
/************************** sensor's interface to ae *********************/
/* eg: 0.35db, enAccuType=AE_ACCURACY_DB, f32Accuracy=0.35
* and the multiply of 0.35db is power(10, (0.35/20))
* eg: 1/16, 2/16, 3/16 multiplies, enAccuType=AE_ACCURACY_LINEAR, f32Accuracy=0.0625
* eg: 1,2,4,8,16 multiplies, enAccuType=AE_ACCURACY_DB, f32Accuracy=6
*/
typedef enum xm_AE_ACCURACY_E
{
AE_ACCURACY_DB = 0,
AE_ACCURACY_LINEAR,
AE_ACCURACY_TABLE,
AE_ACCURACY_BUTT,
} AE_ACCURACY_E;
typedef struct xm_AE_ACCURACY_S
{
AE_ACCURACY_E enAccuType;
float f32Accuracy;
} AE_ACCURACY_S;
typedef struct xm_AE_SENSOR_DEFAULT_S
{
XM_U8 u8AeCompensation;
XM_U8 u8UpdateMode; // 0: Old 1:New(sns_regs)
XM_U32 u32LinesPer500ms;
XM_U32 u32FlickerFreq;
XM_U32 u32FullLinesStd;
XM_U32 u32MaxIntTime; /* unit is line */
XM_U32 u32MinIntTime;
XM_U32 u32MaxIntTimeTarget;
XM_U32 u32MinIntTimeTarget;
XM_U32 u32MaxAgain;
XM_U32 u32MinAgain;
XM_U32 u32MaxAgainTarget;
XM_U32 u32MinAgainTarget;
AE_ACCURACY_S stAgainAccu;
XM_U32 u32MaxDgain;
XM_U32 u32MinDgain;
XM_U32 u32MaxDgainTarget;
XM_U32 u32MinDgainTarget;
AE_ACCURACY_S stDgainAccu;
XM_U32 u32MaxISPDgain;
XM_U32 u32MinISPDgain;
XM_U32 u32MaxISPDgainTarget;
XM_U32 u32MinISPDgainTarget;
XM_U32 u32ISPDgainShift;
/****** 新增加部分*****/
XM_U32 u32LinePixel; // 1行像素个数
XM_U32 u32TimeFinePoint; // < u32TimeFinePoint考虑细调
/********************************
u32UpdateCfg:
bit[0~7] period
bit[8~15] shut
bit[16~23] snsGain
bit[24~31] ispGain
********************************/
XM_U32 u32UpdateCfg;
XM_U32 u32MaxAllgain;
XM_U32 u32InitExp[4];
/********************************
u16AlgMode:
0x00: fix V1
0x01: first V1, after stab bypass AE
0x10: fix V2
0x11: first V2, after stab bypass AE
0x20: first V2, after stab V1
********************************/
XM_U16 u16AlgMode;
XM_BOOL bDelayCfg;
} AE_SENSOR_DEFAULT_S;
typedef struct xm_AE_SENSOR_DEFAULT_V2_S
{
XM_U32 u32MinIntTime;
XM_U32 u32MaxIntTime; /* unit is line */
XM_U32 u32MinAgain;
XM_U32 u32MaxAgain;
XM_U32 u32MinDgain;
XM_U32 u32MaxDgain;
XM_U32 u32MaxISPDgain;
/********************************
u32UpdateCfg:
bit[0~7] period
bit[8~15] shut
bit[16~23] snsGain
bit[24~31] ispGain
********************************/
XM_U32 u32UpdateCfg;
XM_U32 u32InitExp[4];
/********************************
u16AlgMode:
0x00: fix V1
0x01: first V1, after stab bypass AE
0x10: fix V2
0x11: first V2, after stab bypass AE
0x20: first V2, after stab V1
********************************/
XM_U16 u16AlgMode;
} AE_SENSOR_DEFAULT_V2_S;
typedef struct xm_AE_SENSOR_GAININFO_S
{
XM_U32 u32SnsTimes; //10bit precision
XM_U32 u32GainDb; // gain step in db
} AE_SENSOR_GAININFO_S;
typedef struct xm_AE_SENSOR_SHUTINFO_S
{
XM_U64 u64Exp; //10bit precision
XM_U32 u32Ofst; //10bit precision
XM_U32 u32ShutDb;
} AE_SENSOR_SHUTINFO_S;
typedef enum xm_ISP_SNS_TYPE_E
{
ISP_SNS_I2C_TYPE = 0,
ISP_SNS_SSP_TYPE,
ISP_SNS_TYPE_BUTT,
} ISP_SNS_TYPE_E;
typedef struct hiISP_I2C_DATA_S
{
XM_BOOL bUpdate;
XM_U8 u8DelayFrmNum;
XM_U8 u8IntPos;
XM_U32 u32RegAddr;
XM_U32 u32Data;
} ISP_I2C_DATA_S;
typedef struct hiISP_SSP_DATA_S
{
XM_BOOL bUpdate;
XM_U8 u8DelayFrmNum;
XM_U8 u8IntPos;
XM_U32 u32DevAddr;
XM_U32 u32DevAddrByteNum;
XM_U32 u32RegAddr;
XM_U32 u32RegAddrByteNum;
XM_U32 u32Data;
XM_U32 u32DataByteNum;
} ISP_SSP_DATA_S;
typedef struct xm_ISP_SNS_REGS_INFO_S
{
ISP_SNS_TYPE_E enSnsType;
XM_U32 u32RegNum;
XM_U8 u8Cfg2ValidDelayMax;
union
{
ISP_I2C_DATA_S *pstI2CData;
ISP_SSP_DATA_S *pstSspData;
};
} ISP_SNS_REGS_INFO_S;
typedef struct xm_AE_SENSOR_EXP_FUNC_S
{
XM_S32(*pfn_cmos_get_ae_default)(AE_SENSOR_DEFAULT_S *pstAeSnsDft);
/* the function of sensor set fps */
XM_VOID(*pfn_cmos_fps_set)(XM_U8 u8Fps, AE_SENSOR_DEFAULT_S *pstAeSnsDft);
XM_S32(*pfn_cmos_fps_get)(XM_U8 *pu8Fps);
XM_VOID(*pfn_cmos_slow_framerate_set)(XM_U16 u16SlowFrameRate, AE_SENSOR_DEFAULT_S *pstAeSnsDft);
/* while isp notify ae to update sensor regs, ae call these funcs. */
XM_VOID(*pfn_cmos_inttime_update)(XM_U32 u32IntTime);
XM_VOID(*pfn_cmos_gains_update)(XM_U32 u32Again, XM_U32 u32Dgain);
XM_VOID(*pfn_cmos_shut_calc_table)(XM_S32 s32IntTime,AE_SENSOR_SHUTINFO_S *pstAeSnsShutInfo);
XM_VOID(*pfn_cmos_gains_update2)(XM_S32 s32DGain,const AE_SENSOR_DEFAULT_S *pstAeSnsDft);
XM_VOID (*pfn_cmos_again_calc_table)(XM_U32 u32InTimes, AE_SENSOR_GAININFO_S *pstAeSnsGainInfo);
XM_VOID (*pfn_cmos_dgain_calc_table)(XM_U32 u32InTimes, AE_SENSOR_GAININFO_S *pstAeSnsGainInfo);
XM_S32(*pfn_cmos_get_sns_reg_info)(ISP_SNS_REGS_INFO_S *pstSnsRegsInfo);
XM_S32(*pfn_cmos_write_register)(XM_U32 addr, XM_U32 data);
XM_S32(*pfn_cmos_read_register)(XM_U32 addr);
} AE_SENSOR_EXP_FUNC_S;
typedef struct xm_AE_SENSOR_REGISTER_S
{
AE_SENSOR_EXP_FUNC_S stSnsExp;
} AE_SENSOR_REGISTER_S;
typedef struct xm_ISP_AE_VARLED_REGISTER_S
{
XM_BOOL bEnable;
ISP_OP_TYPE_E enOpType;
XM_U32 u32ManualLvl;
XM_U32 u32LvlNow; //RO
XM_U32 u32AutoSpeed; //0~255(default:128)
XM_U32 u32MaxLvl;
XM_U32 u32MinLvl;
XM_U32 u32ExpThreshold_1; // <: weaken
XM_U32 u32ExpThreshold_2; // >: enhance
XM_S32(*pfn_varLED_init)(XM_VOID);
XM_VOID(*pfn_varLED_update)(XM_U32 u32Lvl);
XM_VOID(*pfn_varLED_calc_table)(XM_U32 u32InTimes, AE_SENSOR_GAININFO_S *pstAeSnsGainInfo);
}ISP_AE_VARLED_REGISTER_S;
#endif

179
general/package/xiongmai-osdrv-xm530/files/include/isp/xm_awb_comm.h
View File

@ -1,179 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm_awb_common.h
Version : Initial Draft
Author : XM Isp software group
Created : 2015/6/27
Description : The common data type defination
Function List :
History :
1.Date : 2015/6/27
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef __XM_AWB_COMM_H__
#define __XM_AWB_COMM_H__
#include "xm_type.h"
#include "xm_comm_isp.h"
#ifdef __cplusplus
#if __cplusplus
extern "C"{
#endif
#endif /* End of #ifdef __cplusplus */
#define XM_AWB_LIB_NAME "xm_awb_lib"
/************************** isp ctrl cmd *************************************/
typedef enum xmAWB_CTRL_CMD_E
{
AWB_SATURATION_SET,
AWB_SATURATION_GET,
AWB_DEBUG_ATTR_SET,
AWB_DEBUG_ATTR_GET,
AWB_CTRL_BUTT,
} AWB_CTRL_CMD_E;
typedef struct xmAWB_DBG_ATTR_S
{
XM_U16 u16WhiteLevel;
XM_U16 u16BlackLevel;
XM_U16 u16CrMax;
XM_U16 u16CrMin;
XM_U16 u16CbMax;
XM_U16 u16CbMin;
XM_U16 u16CrHigh;
XM_U16 u16CrLow;
XM_U16 u16CbHigh;
XM_U16 u16CbLow;
XM_U16 u16RawWhiteLevel;
XM_U16 u16RawBlackLevel;
XM_U16 u16RawCrMax;
XM_U16 u16RawCrMin;
XM_U16 u16RawCbMax;
XM_U16 u16RawCbMin;
XM_U16 u16RawCrHigh;
XM_U16 u16RawCrLow;
XM_U16 u16RawCbHigh;
XM_U16 u16RawCbLow;
XM_U16 u16WDRMode;
XM_U16 u16Enable;
XM_U16 u16ManualEnable;
XM_U16 u16Zone;
XM_U16 u16HighTemp;
XM_U16 u16LowTemp;
XM_U16 u16RefTemp;
XM_U16 u16RgainBase;
XM_U16 u16GgainBase;
XM_U16 u16BgainBase;
XM_S32 s32p1;
XM_S32 s32p2;
XM_S32 s32q;
XM_S32 s32a;
XM_S32 s32c;
XM_U16 u16ManSatEnable;
XM_U16 u16SatTarget;
} AWB_DBG_ATTR_S;
typedef struct xmAWB_ZONE_DBG_S
{
XM_U16 u16Sum;
XM_U16 u16Rg;
XM_U16 u16Bg;
XM_U16 u16CountAll;
XM_U16 u16CountMin;
XM_U16 u16CountMax;
XM_U16 u16RawRAvg;
XM_U16 u16RawGAvg;
XM_U16 u16RawBAvg;
XM_U16 u16TK;
XM_U16 u16Weight;
XM_S16 s16Shift;
}AWB_ZONE_DBG_S;
typedef struct xmAWB_DBG_STATUS_S
{
XM_U32 u32FrmNumBgn;
XM_U32 u32GlobalSum;
XM_U16 u16GlobalRgSta;
XM_U16 u16GlobalBgSta;
XM_U16 u16GlobalCountAll;
XM_U16 u16GlobalCountMin;
XM_U16 u16GlobalCountMax;
XM_U16 u16GlobalRAvg;
XM_U16 u16GlobalGAvg;
XM_U16 u16GlobalBAvg;
XM_U16 u16TK;
XM_U16 u16Rgain;
XM_U16 u16Ggain;
XM_U16 u16Bgain;
XM_U16 au16CCM[9];
XM_U32 au32HistInfo[256];
AWB_ZONE_DBG_S astZoneDebug[255];
XM_U32 u32FrmNumEnd;
} AWB_DBG_STATUS_S;
/************************** sensor's interface to awb *********************/
typedef struct xmAWB_AGC_TABLE_S
{
XM_BOOL bValid;
XM_U8 au8Saturation[16]; /* adjust saturation, different iso with different saturation */
} AWB_AGC_TABLE_S;
typedef struct xmAWB_COEF_TABLE_S
{
XM_U16 u16R;
XM_U16 u16B;
} AWB_COEF_TABLE_S;
typedef struct xmISP_AWB_CALIBRATION_V2_S
{
XM_S16 A[8];
XM_S16 B[8];
XM_S16 C[8];
XM_U16 key;
XM_U16 ini_x;
XM_U16 ini_y;
XM_U16 dis_min;
XM_U16 dis_max;
XM_U16 dis[16];
XM_U16 val[16];
XM_U16 init_gain[4];
}ISP_AWB_CALIBRATION_V2_S;
typedef struct xmAWB_SENSOR_DEFAULT_S
{
ISP_COLORMATRIX_AUTO_S stCcm;
ISP_AWB_CALIBRATION_S stAwbCal;
const AWB_COEF_TABLE_S* pstRbTable; // Number Must is 161
} AWB_SENSOR_DEFAULT_S;
typedef struct xmAWB_SENSOR_EXP_FUNC_S
{
XM_S32(*pfn_cmos_get_awb_default)(AWB_SENSOR_DEFAULT_S *pstAwbSnsDft);
} AWB_SENSOR_EXP_FUNC_S;
typedef struct xmAWB_SENSOR_REGISTER_S
{
AWB_SENSOR_EXP_FUNC_S stSnsExp;
} AWB_SENSOR_REGISTER_S;
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif

343
general/package/xiongmai-osdrv-xm530/files/include/isp/xm_comm_3a.h
View File

@ -1,343 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm_common_3a.h
Version : Initial Draft
Author : XM Isp software group
Created : 2015/6/27
Description : The common data type defination
Function List :
History :
1.Date : 2015/6/27
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef __XM_COMM_3A_H__
#define __XM_COMM_3A_H__
#include "xm_common.h"
#include "xm_comm_isp.h"
#define MAX_REGISTER_ALG_LIB_NUM 2
typedef enum xm_ISP_ALG_MOD_E
{
ISP_ALG_AE = 0,
ISP_ALG_AF,
ISP_ALG_AWB,
ISP_ALG_ANTIFOG,
ISP_ALG_BLC,
ISP_ALG_DP,
ISP_ALG_DRC,
ISP_ALG_DEMOSAIC,
ISP_ALG_GAMMA,
ISP_ALG_GAMMAFE,
ISP_ALG_GE,
ISP_ALG_NEW_ANTIFOG,
ISP_ALG_NR,
ISP_ALG_SHARPEN,
ISP_ALG_SHADING,
ISP_ALG_BUTT,
} ISP_ALG_MOD_E;
typedef enum xm_ISP_CTRL_CMD_E
{
ISP_WDR_MODE_SET = 8000,
ISP_PROC_WRITE,
ISP_AE_FPS_BASE_SET,
ISP_AWB_ISO_SET, /* set iso, change saturation when iso change */
ISP_AE_INTTIME_GET,
ISP_AWB_INTTIME_SET,
ISP_CHANGE_IMAGE_MODE_SET,
ISP_CTRL_CMD_BUTT,
} ISP_CTRL_CMD_E;
typedef struct xm_ISP_CTRL_PROC_WRITE_S
{
XM_CHAR *pcProcBuff;
XM_U32 u32BuffLen;
XM_U32 u32WriteLen; /* The len count should contain '\0'. */
} ISP_CTRL_PROC_WRITE_S;
/******************************** AE *************************************/
/* the init param of ae alg */
typedef struct xm_ISP_AE_PARAM_S
{
SENSOR_ID SensorId;
XM_U32 u32MaxIspDgain;
XM_U32 u32MinIspDgain;
XM_U32 u32IspDgainShift;
XM_U8 u8FrameRate;
} ISP_AE_PARAM_S;
/* the statistics of ae alg */
typedef struct xm_ISP_AE_STAT_1_S
{
XM_U32 au32MeteringHist[16];
} ISP_AE_STAT_1_S;
typedef struct xm_ISP_AE_STAT_2_S
{
XM_U32 au32MeteringWin[AE_ZONE_ROW][AE_ZONE_COLUMN]; // Y_avg << 8
} ISP_AE_STAT_2_S;
typedef struct xm_ISP_AE_STAT_3_S
{
XM_U16 au16MeteringWinV2[ISP_V2_ZONE_ROW][ISP_V2_ZONE_COLUMN];
} ISP_AE_STAT_3_S;
typedef struct xm_ISP_AE_STAT_S
{
XM_U8 u8FrameRate;
XM_U32 u32FrameCnt;
XM_U32 au32MeteringWin[AE_ZONE_ROW][AE_ZONE_COLUMN]; // Y_avg << 8
} ISP_AE_STAT_S;
typedef struct xm_ISP_AE_INFO_S
{
XM_U32 u32FrameCnt; /* the counting of frame */
XM_U8 u8FrameRate;
ISP_AE_STAT_1_S stAeStat1;
ISP_AE_STAT_2_S stAeStat2;
ISP_AE_STAT_3_S stAeStat3;
} ISP_AE_INFO_S;
/* the final calculate of ae alg */
typedef struct xm_ISP_AE_RESULT_S
{
XM_U32 u32IspDgain;
XM_U32 u32IspDgainShift;
XM_U32 u32Iso;
XM_U32 u32Rsv;
/********************************
u32UpdateCfg:
bit[0~7] period
bit[8~15] shut
bit[16~23] snsGain
bit[24~31] ispGain
********************************/
XM_U32 u32UpdateCfg;
} ISP_AE_RESULT_S;
typedef struct xm_ISP_AE_EXP_FUNC_S
{
XM_S32 (*pfn_ae_init)(ISP_DEV IspDev, XM_S32 s32Handle, const ISP_AE_PARAM_S *pstAeParam);
XM_S32 (*pfn_ae_run)(ISP_DEV IspDev, XM_S32 s32Handle,
const ISP_AE_INFO_S *pstAeInfo,
ISP_AE_RESULT_S *pstAeResult,
XM_S32 s32Rsv
);
XM_S32 (*pfn_ae_ctrl)(ISP_DEV IspDev, XM_S32 s32Handle, XM_U32 u32Cmd, XM_VOID *pValue);
XM_S32 (*pfn_ae_exit)(ISP_DEV IspDev, XM_S32 s32Handle);
} ISP_AE_EXP_FUNC_S;
typedef struct xm_ISP_AE_REGISTER_S
{
ISP_AE_EXP_FUNC_S stAeExpFunc;
} ISP_AE_REGISTER_S;
/******************************** AWB *************************************/
/* the statistics of awb alg */
typedef struct xm_ISP_AWB_STAT_ZONE_S
{
XM_U32 u32Data1; // Wp
XM_U32 u32Data2; // Cb
XM_U32 u32Data3; // Cr
} ISP_AWB_STAT_ZONE_S;
typedef struct xm_ISP_AWB_STAT_1_S
{
ISP_AWB_STAT_ZONE_S stStat1[4][4]; // 4:Chn // 4:Zone
} ISP_AWB_STAT_1_S;
typedef struct xm_ISP_AWB_STAT_2_S
{
;
} ISP_AWB_STAT_2_S;
typedef struct xm_ISP_AWB_INFO_S
{
XM_U32 u32FrameCnt;
XM_U32 u32Rsv;
ISP_AWB_STAT_1_S *pstAwbStat1;
ISP_AWB_STAT_2_S *pstAwbStat2;
} ISP_AWB_INFO_S;
/* the statistics's attr of awb alg */
typedef struct xm_ISP_AWB_FT_L_ATTR_S
{
XM_BOOL bChange;
XM_U32 u32Lh;
XM_U32 u32Lv;
XM_U32 u32L45;
XM_U32 u32L135;
} ISP_AWB_FT_L_ATTR_S;
typedef struct xm_ISP_AWB_FT_K_ATTR_S
{
XM_BOOL bChange;
XM_U32 u32KCbCr1;
XM_U32 u32KCbCr2;
XM_U32 u32KCbCr3;
XM_U32 u32KCbCr4;
} ISP_AWB_FT_K_ATTR_S;
typedef struct xm_ISP_AWB_WDW_ATTR_S
{
XM_BOOL bChange;
XM_U8 u8Mode;
XM_U32 u32VBegin;
XM_U32 u32VEnd;
XM_U32 u32HBegin;
XM_U32 u32HEnd;
} ISP_AWB_WDW_ATTR_S;
typedef struct xm_ISP_AWB_BG_ATTR_S
{
XM_BOOL bChange;
XM_U32 u32R_Ch[4];
XM_U32 u32B_Ch[4];
} ISP_AWB_BG_ATTR_S;
typedef struct xm_ISP_AWB_RESULT_BK_S
{
ISP_AWB_FT_L_ATTR_S stFtL;
ISP_AWB_FT_K_ATTR_S stFtK;
ISP_AWB_WDW_ATTR_S stWin;
ISP_AWB_BG_ATTR_S stBg;
} ISP_AWB_RESULT_BK_S;
typedef struct xm_ISP_AWB_RESULT_GAIN_S
{
XM_BOOL bChange;
XM_U32 au32WhiteBalanceGain[3];
} ISP_AWB_RESULT_GAIN_S;
typedef struct xm_ISP_AWB_RESULT_CC_S
{
XM_BOOL bChange;
XM_U16 au16ColorMatrix[12];
} ISP_AWB_RESULT_CC_S;
/* the final calculate of awb alg */
typedef struct xm_ISP_AWB_RESULT_S
{
ISP_AWB_RESULT_GAIN_S *pstRlt_Gain;
ISP_AWB_RESULT_CC_S *pstRlt_Cc;
ISP_AWB_RESULT_BK_S *pstRlt_Bk;
XM_U16 *pstRlt_RGB;
} ISP_AWB_RESULT_S;
typedef struct xm_ISP_AWB_EXP_FUNC_S
{
XM_S32 (*pfn_awb_init)(XM_S32 s32Handle, ISP_AWB_RESULT_BK_S* const pstAwbParam,XM_U32 Width,XM_U32 Height);
XM_S32 (*pfn_awb_run)(XM_S32 s32Handle,
const ISP_AWB_INFO_S *pstAwbInfo,
ISP_AWB_RESULT_S *pstAwbResult,
XM_S32 s32Rsv
);
XM_S32 (*pfn_awb_ctrl)(XM_S32 s32Handle, XM_U32 u32Cmd, XM_VOID *pValue);
XM_S32 (*pfn_awb_exit)(XM_S32 s32Handle);
} ISP_AWB_EXP_FUNC_S;
typedef struct xm_ISP_AWB_REGISTER_S
{
ISP_AWB_EXP_FUNC_S stAwbExpFunc;
} ISP_AWB_REGISTER_S;
/******************************** AF *************************************/
/* the init param of af alg */
typedef struct xm_ISP_AF_PARAM_S
{
SENSOR_ID SensorId;
XM_S32 s32Rsv;
} ISP_AF_PARAM_S;
/* the statistics of af alg */
typedef struct xm_ISP_AF_STAT_S
{
XM_U16 u16FocusMetrics; /* The integrated and normalized measure of contrast*/
XM_U16 u16ThresholdRead; /* The ISP recommend value of AF threshold*/
XM_U16 u16ThresholdWrite; /* The user defined value of AF threshold (or 0 to use threshold from previous frame)*/
XM_U16 u16FocusIntensity; /* The average brightness*/
XM_U8 u8MetricsShift; /* Metrics scaling factor:the bigger value for this register means all zones metrics go higher,0x03 is the default, Range: [0x0, 0xF] */
XM_U8 u8NpOffset; /* The AF noise profile offset, Range: [0x0, 0xFF] */
XM_U16 au16ZoneMetrics[AE_ZONE_ROW][AE_ZONE_COLUMN]; /* The zoned measure of contrast*/
} ISP_AF_STAT_S;
typedef struct xm_ISP_AF_INFO_S
{
XM_U32 u32FrameCnt;
ISP_AF_STAT_S *pstStatistics;
} ISP_AF_INFO_S;
typedef struct xm_ISP_AF_STAT_ATTR_S
{
XM_BOOL bChange;
XM_U16 u16ThresholdWrite;
XM_U8 u8MetricsShift;
XM_U8 u8NpOffset;
} ISP_AF_STAT_ATTR_S;
/* the final calculate of af alg */
typedef struct xm_ISP_AF_RESULT_S
{
ISP_AF_STAT_ATTR_S stStatAttr;
XM_S32 s32Rsv;
} ISP_AF_RESULT_S;
typedef struct xm_ISP_AF_EXP_FUNC_S
{
XM_S32 (*pfn_af_init)(XM_S32 s32Handle, const ISP_AF_PARAM_S *pstAfParam);
XM_S32 (*pfn_af_run)(XM_S32 s32Handle,
const ISP_AF_INFO_S *pstAfInfo,
ISP_AF_RESULT_S *pstAfResult,
XM_S32 s32Rsv
);
XM_S32 (*pfn_af_ctrl)(XM_S32 s32Handle, XM_U32 u32Cmd, XM_VOID *pValue);
XM_S32 (*pfn_af_exit)(XM_S32 s32Handle);
} ISP_AF_EXP_FUNC_S;
typedef struct xm_ISP_AF_REGISTER_S
{
ISP_AF_EXP_FUNC_S stAfExpFunc;
} ISP_AF_REGISTER_S;
typedef struct xm_ALG_LIB_S
{
XM_S32 s32Id;
XM_CHAR acLibName[20];
} ALG_LIB_S;
typedef struct xm_ISP_BIND_ATTR_S
{
SENSOR_ID SensorId;
ALG_LIB_S stAeLib;
ALG_LIB_S stAfLib;
ALG_LIB_S stAwbLib;
} ISP_BIND_ATTR_S;
#endif /*__XM_COMM_SNS_H__ */

1360
general/package/xiongmai-osdrv-xm530/files/include/isp/xm_comm_isp.h
View File

File diff suppressed because it is too large Load Diff

214
general/package/xiongmai-osdrv-xm530/files/include/isp/xm_comm_sns.h
View File

@ -1,214 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm_comm_sns.h
Version : Initial Draft
Author : XM Isp software group
Created : 2015/7/6
Description : The common data type defination
Function List :
History :
1.Date : 2015/7/6
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef __XM_COMM_SNS_H__
#define __XM_COMM_SNS_H__
#include "xm_type.h"
#include "xm_comm_isp.h"
typedef struct xm_ISP_CMOS_AGC_TABLE_S
{
XM_BOOL bValid;
XM_U8 au8SharpenAltD[ISP_AUTO_STENGTH_NUM]; /* adjust image edge,different iso with different sharp strength */
XM_U8 au8SharpenAltUd[ISP_AUTO_STENGTH_NUM]; /* adjust image texture, different iso with different strength */
XM_U8 au8SharpenKd[ISP_AUTO_STENGTH_NUM];
XM_U8 au8SnrThresh[ISP_AUTO_STENGTH_NUM]; /* adjust 2Ddenoise strength, different iso with different strength */
XM_U8 au83DTfStrength[ISP_AUTO_STENGTH_NUM]; /* adjust 3Ddenoise strength, different iso with different strength */
XM_U8 au83DSfStrength[ISP_AUTO_STENGTH_NUM];
XM_U8 au8DyDpc[ISP_AUTO_STENGTH_NUM]; /* adjust DynamicDpc strength, different iso with different strength */
XM_U8 au8Saturation[ISP_AUTO_STENGTH_NUM];
XM_U16 au16Blc[ISP_AUTO_STENGTH_NUM]; /* adjust blackLevel,different iso with different sharp strength */
XM_U16 au16Ytrangamma[ISP_AUTO_STENGTH_NUM]; /*adjust Y_Tran gamma,iso with different sharp strength*/
} ISP_CMOS_AGC_TABLE_S;
typedef struct xm_ISP_CMOS_NOISE_TABLE_S
{
XM_BOOL bValid;
XM_U8 au8NoiseProfileWeightLut[128];
XM_U8 au8DemosaicWeightLut[128];
} ISP_CMOS_NOISE_TABLE_S;
typedef struct xm_ISP_CMOS_DEMOSAIC_S
{
XM_BOOL bValid;
XM_U8 u8VhSlope;
XM_U8 u8AaSlope;
XM_U8 u8VaSlope;
XM_U8 u8UuSlope;
XM_U8 u8SatSlope;
XM_U8 u8AcSlope;
XM_U16 u16VhThresh;
XM_U16 u16AaThresh;
XM_U16 u16VaThresh;
XM_U16 u16UuThresh;
XM_U16 u16SatThresh;
XM_U16 u16AcThresh;
} ISP_CMOS_DEMOSAIC_S;
typedef struct xm_ISP_CMOS_DRC_S
{
XM_U8 u8DrcBlack;
XM_U8 u8DrcVs; /* variance space */
XM_U8 u8DrcVi; /* variance intensity */
XM_U8 u8DrcSm; /* slope max */
XM_U16 u16DrcWl; /* white level */
} ISP_CMOS_DRC_S;
#define LUT_FACTOR (8)
#define GAMMA_FE_LUT_SIZE ((1<<LUT_FACTOR)+1)
typedef struct xm_ISP_CMOS_GAMMAFE_S
{
XM_BOOL bValid; /* wdr sensor should set */
XM_U16 au16Gammafe[GAMMA_FE_LUT_SIZE];
} ISP_CMOS_GAMMAFE_S;
typedef struct xm_ISP_CMOS_DENOISE_S
{
XM_U8 u8SinterThresh; /* sinter threshold */
XM_U8 u8NoiseProfile; /* two different noise profile */
XM_U16 u16Nr0; /* nr0 for noise profile 2 */
XM_U16 u16Nr1; /* nr1 for noise profile 2 */
} ISP_CMOS_DENOISE_S;
typedef struct xm_ISP_CMOS_COMM_S
{
XM_U8 u8Rggb; /* rggb start sequence */
XM_U8 u8BalanceFe;
} ISP_CMOS_COMM_S;
#define CMOS_SHADING_TABLE_NODE_NUMBER_MAX (129)
typedef struct xm_ISP_CMOS_SHADING_S
{
XM_BOOL bValid;
XM_U16 u16RCenterX;
XM_U16 u16RCenterY;
XM_U16 u16GCenterX;
XM_U16 u16GCenterY;
XM_U16 u16BCenterX;
XM_U16 u16BCenterY;
XM_U16 au16RShadingTbl[CMOS_SHADING_TABLE_NODE_NUMBER_MAX];
XM_U16 au16GShadingTbl[CMOS_SHADING_TABLE_NODE_NUMBER_MAX];
XM_U16 au16BShadingTbl[CMOS_SHADING_TABLE_NODE_NUMBER_MAX];
XM_U16 u16ROffCenter;
XM_U16 u16GOffCenter;
XM_U16 u16BOffCenter;
XM_U16 u16TblNodeNum;
} ISP_CMOS_SHADING_S;
#if (defined CHIPID_XM530)||(defined CHIPID_XM350)
#define GAMMA_NODE_NUMBER 97
#else
#define GAMMA_NODE_NUMBER 61
#endif
typedef struct xm_ISP_CMOS_GAMMA_S
{
XM_BOOL bValid;
XM_U16 au16Gamma[GAMMA_NODE_NUMBER];
} ISP_CMOS_GAMMA_S;
typedef struct xm_ISP_CMOS_DEFAULT_S
{
ISP_CMOS_COMM_S stComm;
ISP_CMOS_DENOISE_S stDenoise;
ISP_CMOS_DRC_S stDrc;
ISP_CMOS_AGC_TABLE_S stAgcTbl;
ISP_CMOS_NOISE_TABLE_S stNoiseTbl;
ISP_CMOS_DEMOSAIC_S stDemosaic;
ISP_CMOS_GAMMAFE_S stGammafe;
ISP_CMOS_GAMMA_S stGamma;
ISP_CMOS_SHADING_S stShading;
} ISP_CMOS_DEFAULT_S;
typedef enum xm_ISP_CMOS_MODE_E
{
ISP_CMOS_MODE_PIXEL_DETECT = 0,
ISP_CMOS_MODE_WDR,
ISP_CMOS_MODE_RESOLUTION,
ISP_CMOS_MODE_BUTT,
} ISP_CMOS_MODE_E;
typedef struct xm_ISP_CMOS_SENSOR_MAX_RESOLUTION_S
{
XM_U32 u32MaxWidth;
XM_U32 u32MaxHeight;
}ISP_CMOS_SENSOR_MAX_RESOLUTION;
typedef struct xm_ISP_CMOS_SENSOR_IMAGE_MODE_S
{
XM_U16 u16Width;
XM_U16 u16Height;
XM_U16 u16Fps;
}ISP_CMOS_SENSOR_IMAGE_MODE;
typedef struct xm_ISP_SENSOR_EXP_FUNC_S
{
XM_VOID(*pfn_cmos_sensor_init)(XM_VOID);
XM_VOID(*pfn_cmos_sensor_global_init)(XM_VOID);
XM_S32(*pfn_cmos_get_isp_default)(ISP_CMOS_DEFAULT_S *pstDef);
XM_S32(*pfn_cmos_get_sensor_max_resolution)(ISP_CMOS_SENSOR_MAX_RESOLUTION *pstSensorMaxResolution);
/* the function of sensor set pixel detect */
XM_VOID(*pfn_cmos_set_pixel_detect)(XM_BOOL bEnable);
XM_VOID(*pfn_cmos_set_wdr_mode)(XM_U8 u8Mode);
XM_VOID(*pfn_cmos_set_resolution)(XM_U32 u32ResolutionMode);
XM_S32(*pfn_cmos_set_image_mode)(ISP_CMOS_SENSOR_IMAGE_MODE *pstSensorImageMode);
XM_S32(*pfn_cmos_set_mirror_flip)(XM_U8 u8Mirror,XM_U8 u8Flip);
} ISP_SENSOR_EXP_FUNC_S;
typedef struct xm_ISP_SENSOR_REGISTER_S
{
ISP_SENSOR_EXP_FUNC_S stSnsExp;
} ISP_SENSOR_REGISTER_S;
/****** ERR_shift Noise_level*********/
#define SHIFTLEVEL_NUMBER 34
typedef struct xm_ISP_SENSOR_SHIFTLEVEL_S
{
XM_U8 u8Shift;
XM_U8 u8Level;
} ISP_SENSOR_SHIFTLEVEL_S;
typedef struct xm_ISP_CMOS_SNS_ATTR_S
{
XM_U8 u8InputMode; // 0:DVP 1:MIPI
XM_U8 u8Rsv[7];
XM_U32 u32Rsv[14];
} ISP_CMOS_SNS_ATTR_S;
#endif /*__XM_COMM_SNS_H__ */

232
general/package/xiongmai-osdrv-xm530/files/include/isp/xm_comm_vda.h
View File

@ -1,232 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm_comm_vda.h
Version : Initial Draft
Author : XM Isp software group
Created : 2015/6/27
Description : The common data type defination
Function List :
History :
1.Date : 2015/6/27
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef __XM_COMM_VDA_H__
#define __XM_COMM_VDA_H__
#include "xm_type.h"
#include "xm_debug.h"
#include "xm_comm_video.h"
#include "xm_common.h"
#include "xm_errno.h"
#include "xm_defines.h"
#if 0
/*Motion Region Data*/
typedef struct xmVDA_OBJ_S
{
XM_U16 u16Left;
XM_U16 u16Top;
XM_U16 u16Right;
XM_U16 u16Bottom;
}VDA_OBJ_S;
/*reference pictrue mode*/
typedef enum xmVDA_REF_MODE_E
{
VDA_REF_MODE_DYNAMIC = 0, /*reference pictrue dynamic*/
VDA_REF_MODE_STATIC, /*reference pictrue static*/
VDA_REF_MODE_USER, /*reference pictrue user*/
VDA_REF_MODE_BUTT /*reserve*/
}VDA_REF_MODE_E;
/*VDA algorithm*/
typedef enum xmVDA_ALG_E
{
VDA_ALG_REF, /*base on reference pictrue*/
VDA_ALG_BUTT
}VDA_ALG_E;
/*MB size*/
typedef enum xmVDA_MB_SIZE_E
{
VDA_MB_7PIXEL, /* 7*7 */
VDA_MB_BUTT
}VDA_MB_SIZE_E;
#endif
/*SAD bits*/
typedef enum xmVDA_MB_SADBITS_E
{
VDA_MB_SAD_8BIT = 0, /*SAD precision 8bits*/
VDA_MB_SAD_16BIT, /*SAD precision 16bits*/
VDA_MB_SAD_BUTT /*reserve*/
} VDA_MB_SADBITS_E;
/*MD attribute*/
typedef struct xmVDA_MD_ATTR_S
{
/*static attribute*/
//VDA_ALG_E enVdaAlg; /*arithmetic*/
//VDA_MB_SIZE_E enMbSize; /*MB size*/
VDA_MB_SADBITS_E enMbSadBits; /*MB SAD size*/
//VDA_REF_MODE_E enRefMode; /*reference picture mode*/
//XM_U32 u32MdBufNum; /*Result buffer number,range:[1,16]*/
/*dynamic attribute*/
//XM_U32 u32VdaIntvl; /*VDA interval,range:[0,256]*/
XM_U32 u32BgUpSrcWgt; // 更新权重
XM_U32 u32SadTh; // 报警阈值(0~255)<<8
XM_U32 u32ObjNumMax; // 最大运动区域的最大个数
}VDA_MD_ATTR_S;
#define VDA_OD_RGN_NUM_MAX 1
/*OD attribute*/
typedef struct xmVDA_OD_ATTR_S
{
XM_U32 u32SadTh; /*SAD threshold,range:[0,4080]*/
VDA_MB_SADBITS_E enMbSadBits; /*MB SAD size*/
}VDA_OD_ATTR_S;
/*work mode*/
typedef enum xmVDA_WORK_MODE_E
{
VDA_WORK_MODE_MD = 0, /*motion detection*/
VDA_WORK_MODE_OD, /*Occlusion detection*/
VDA_WORK_MODE_BUTT
}VDA_WORK_MODE_E;
/*work mode attribute*/
typedef union xmVDA_WORK_MODE_ATTR_U
{
VDA_MD_ATTR_S stMdAttr; /*MD attribute*/
VDA_OD_ATTR_S stOdAttr; /*OD attribute*/
}VDA_WORK_MODE_ATTR_U;
/*VDA CHN attribute*/
typedef struct xmVDA_CHN_ATTR_S
{
VDA_WORK_MODE_E enWorkMode; /*work mode*/
VDA_WORK_MODE_ATTR_U unAttr; /*work mode attribute*/
XM_U32 u32Width; /*the width of CHNL,[16,VDA_MAX_WIDTH]*/
XM_U32 u32Height; /*the height of CHNL,[16,VDA_MAX_HEIGHT]*/
XM_U16 u16VdaIntvl; /*VDA interval,[0,65535]*/ // 视频间隔
}VDA_CHN_ATTR_S;
// 宏块部分信息
typedef struct xmVDA_SAD_DATA_S
{
XM_BOOL bSadValid; /*SAD data is valid?*/
XM_VOID *pAddr; // 宏块统计信息
XM_U32 u32Stride; // 宏块数据以字节为单位的内存行宽度
XM_U32 u32TotalCnt; // 宏块总个数
}VDA_SAD_DATA_S;
/*MD data*/
typedef struct xmVDA_MD_DATA_S
{
// 运动部分信息
XM_BOOL bMdValid; // MD结果是否有效
XM_VOID *pAddr; // 结果地址
XM_U32 u32Stride; // 结果数据以字节为单位的内存行宽度
XM_U32 u32TotalCnt; // 宏块总个数
XM_U32 u32AlarmCnt; // 报警个数
}VDA_MD_DATA_S;
/*OD data*/
typedef struct xmVDA_OD_DATA_S
{
XM_BOOL bOdAlram; /*XM_TRUE:alarm*/
}VDA_OD_DATA_S;
typedef union xmVDA_DATA_U
{
VDA_SAD_DATA_S stSadData;
VDA_MD_DATA_S stMdData; /*MD data*/
VDA_OD_DATA_S stOdData; /*OD data*/
}VDA_DATA_U;
/*VDA data*/
typedef struct xmVDA_DATA_S
{
VDA_WORK_MODE_E enWorkMode; /*work mode*/
VDA_DATA_U unData; /*VDA data*/
XM_U32 u32MbWidth; /*VDA channle width in MB*/
XM_U32 u32MbHeight; /*VDA channle height in MB*/
XM_U64 u64Pts; /*time*/
}VDA_DATA_S;
/*chnnel state*/
typedef struct xmVDA_CHN_STAT_S
{
XM_BOOL bStartRecvPic; /*start receive picture*/
XM_U32 u32BufPcNow; // 现在指向的buffer位置
XM_U32 u32StatusFlag; // 现在状态(0:NotOpen 1:InitOk 2:Get1Buffer 3:GetAllBuffer)
}VDA_CHN_STAT_S;
/* invlalid device ID */
#define XM_ERR_VDA_INVALID_DEVID XM_DEF_ERR(XM_ID_VDA, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_DEVID)
/* invlalid channel ID */
#define XM_ERR_VDA_INVALID_CHNID XM_DEF_ERR(XM_ID_VDA, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_CHNID)
/* at lease one parameter is illagal ,eg, an illegal enumeration value */
#define XM_ERR_VDA_ILLEGAL_PARAM XM_DEF_ERR(XM_ID_VDA, EN_ERR_LEVEL_ERROR, EN_ERR_ILLEGAL_PARAM)
/* channel exists */
#define XM_ERR_VDA_EXIST XM_DEF_ERR(XM_ID_VDA, EN_ERR_LEVEL_ERROR, EN_ERR_EXIST)
/*UN exist*/
#define XM_ERR_VDA_UNEXIST XM_DEF_ERR(XM_ID_VDA, EN_ERR_LEVEL_ERROR, EN_ERR_UNEXIST)
/* using a NULL point */
#define XM_ERR_VDA_NULL_PTR XM_DEF_ERR(XM_ID_VDA, EN_ERR_LEVEL_ERROR, EN_ERR_NULL_PTR)
/* try to enable or initialize system,device or channel, before configing attribute */
#define XM_ERR_VDA_NOT_CONFIG XM_DEF_ERR(XM_ID_VDA, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_CONFIG)
/* operation is not supported by NOW */
#define XM_ERR_VDA_NOT_SUPPORT XM_DEF_ERR(XM_ID_VDA, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_SUPPORT)
/* operation is not permitted ,eg, try to change stati attribute */
#define XM_ERR_VDA_NOT_PERM XM_DEF_ERR(XM_ID_VDA, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_PERM)
/* failure caused by malloc memory */
#define XM_ERR_VDA_NOMEM XM_DEF_ERR(XM_ID_VDA, EN_ERR_LEVEL_ERROR, EN_ERR_NOMEM)
/* failure caused by malloc buffer */
#define XM_ERR_VDA_NOBUF XM_DEF_ERR(XM_ID_VDA, EN_ERR_LEVEL_ERROR, EN_ERR_NOBUF)
/* no data in buffer */
#define XM_ERR_VDA_BUF_EMPTY XM_DEF_ERR(XM_ID_VDA, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_EMPTY)
/* no buffer for new data */
#define XM_ERR_VDA_BUF_FULL XM_DEF_ERR(XM_ID_VDA, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_FULL)
/* bad address, eg. used for copy_from_user & copy_to_user */
#define XM_ERR_VDA_BADADDR XM_DEF_ERR(XM_ID_VDA, EN_ERR_LEVEL_ERROR, EN_ERR_BADADDR)
/* resource is busy, eg. destroy a venc chn without unregistering it */
#define XM_ERR_VDA_BUSY XM_DEF_ERR(XM_ID_VDA, EN_ERR_LEVEL_ERROR, EN_ERR_BUSY)
/* System is not ready,maybe not initialed or loaded.
* Returning the error code when opening a device file failed.
*/
#define XM_ERR_VDA_NOTREADY XM_DEF_ERR(XM_ID_VDA, EN_ERR_LEVEL_ERROR, EN_ERR_SYS_NOTREADY)
#endif /* End of #ifndef __XM_COMM_VDA_H__ */

115
general/package/xiongmai-osdrv-xm530/files/include/isp/xm_comm_vdam.h
View File

@ -1,115 +0,0 @@
#ifndef _XM_COMM_VDAM_H_
#define _XM_COMM_VDAM_H_
#include "xm_type.h"
#include "xm_errno.h"
#include "xm_defines.h"
#include "xm_comm_isp.h"
#include "xm_comm_3a.h"
#define VDAMOWIN 18
typedef struct tagVDA_MOTION_SHELTER_INIT
{
XM_U32 ShAlarmU; //过曝报警阈值
XM_U32 ShAlarmD; //遮挡报警阈值1(遮挡预警值)
XM_U32 ShAlarmAf; //遮挡报警阈值2(对焦值预警)
XM_U8 ShRatio; //遮挡比例
XM_U8 ShDframe; //遮挡间隔帧
XM_U8 ShLevel;
XM_U8 ShEnble;
}VDA_MOTION_SHELTER_INIT;
typedef struct tagVDA_MOTION_SHELTER_RECDATA
{
XM_U32 ShChvall;
}VDA_MOTION_SHELTER_RECDATA;
typedef struct tagVDA_MOTION_SHELTER_RESULT
{
XM_U8 ShReflag;
}VDA_MOTION_SHELTER_RESULT;
typedef struct tagVDA_MOTION_MOVE_INIT
{
XM_U8 u8RatioThresh; // [0,100]
XM_U8 MoRatio;
XM_U8 MoDframe;
XM_U8 MoEnble;
XM_U32 MoSentiven;
XM_U32 MoGridLine;
XM_U32 MoGridRows;
XM_U32 MoWinset[18];
}VDA_MOTION_MOVE_INIT;
typedef struct tagVDA_MOTION_MOVE_RECDATA
{
XM_U32 MoChvall[AE_ZONE_ROW][AE_ZONE_COLUMN]; //存取值
}VDA_MOTION_MOVE_RECDATA;
typedef struct tagVDA_MOTION_MOVE_RESULT
{
XM_U32 MoVdaBmark[AE_ZONE_ROW]; //移动标志位，每行占四个byte
XM_U16 MoReflag;
XM_U16 MoVdaCount;
}VDA_MOTION_MOVE_RESULT;
typedef struct tagVDA_MOTION_MOVE_S
{
VDA_MOTION_MOVE_INIT ModInit;
VDA_MOTION_MOVE_RECDATA MoRatival;
VDA_MOTION_MOVE_RESULT Modmark;
}VDA_MOTION_MOVE_S;
typedef struct tagVDA_MOTION_SHELTER_S
{
VDA_MOTION_SHELTER_RECDATA ShRaival;
VDA_MOTION_SHELTER_INIT ShdInit;
VDA_MOTION_SHELTER_RESULT Shdmark;
}VDA_MOTION_SHELTER_S;
typedef struct tagVDA_MOTION_CHANNEL
{
XM_U8 VdaCreate;
VDA_MOTION_MOVE_S MoveReslt;
VDA_MOTION_SHELTER_S ShelReslt;
}VDA_MOTION_CHANNEL;
typedef enum
{
XM_VDA_LEV1 =1,
XM_VDA_LEV2 =2 ,
XM_VDA_LEV3 =3 ,
XM_VDA_LEV4 =4 ,
XM_VDA_LEV5 =5 ,
XM_VDA_LEV6 =6 ,
}VDA_MOTION_Level;
typedef enum
{
VDA_SHL_RAT1=2,
VDA_SHL_RAT2=4,
VDA_SHL_RAT3=6,
VDA_SHL_RAT4=8,
VDA_SHL_RAT5=10,
VDA_SHL_RAT6=16
}VDA_MOTION_SHELTER_RATIO;
typedef enum
{
VDA_MOV_RAT1=2,
VDA_MOV_RAT2=4,
VDA_MOV_RAT3=6,
VDA_MOV_RAT4=8,
VDA_MOV_RAT5=10,
VDA_MOV_RAT6=12
}VDA_MOTION_MOVE_RATIO;
#endif

317
general/package/xiongmai-osdrv-xm530/files/include/isp/xm_comm_video.h
View File

@ -1,317 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm_common_video.h
Version : Initial Draft
Author : XM Isp software group
Created : 2015/6/27
Description : The common data type defination
Function List :
History :
1.Date : 2015/6/27
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef __XM_COMM_VIDEO_H__
#define __XM_COMM_VIDEO_H__
#include "xm_type.h"
#include "xm_common.h"
typedef enum xm_PIC_SIZE_E
{
PIC_QCIF = 0,
PIC_CIF,
PIC_2CIF,
PIC_HD1,
PIC_D1,
PIC_960H,
PIC_QVGA, /* 320 * 240 */
PIC_VGA, /* 640 * 480 */
PIC_XGA, /* 1024 * 768 */
PIC_SXGA, /* 1400 * 1050 */
PIC_UXGA, /* 1600 * 1200 */
PIC_QXGA, /* 2048 * 1536 */
PIC_WVGA, /* 854 * 480 */
PIC_WSXGA, /* 1680 * 1050 */
PIC_WUXGA, /* 1920 * 1200 */
PIC_WQXGA, /* 2560 * 1600 */
PIC_HD720, /* 1280 * 720 */
PIC_HD1080, /* 1920 * 1080 */
PIC_BUTT
}PIC_SIZE_E;
typedef enum xm_VIDEO_NORM_E
{
VIDEO_ENCODING_MODE_PAL=0,
VIDEO_ENCODING_MODE_NTSC,
VIDEO_ENCODING_MODE_AUTO,
VIDEO_ENCODING_MODE_BUTT
} VIDEO_NORM_E;
typedef enum xm_VIDEO_CONTROL_MODE_E
{
VIDEO_CONTROL_MODE_SLAVER=0,
VIDEO_CONTROL_MODE_MASTER,
VIDEO_CONTROL_MODE_BUTT
}VIDEO_CONTROL_MODE_E;
/* we ONLY define picture format used, all unused will be deleted!*/
typedef enum xm_PIXEL_FORMAT_E
{
PIXEL_FORMAT_RGB_1BPP = 0,
PIXEL_FORMAT_RGB_2BPP,
PIXEL_FORMAT_RGB_4BPP,
PIXEL_FORMAT_RGB_8BPP,
PIXEL_FORMAT_RGB_444,
PIXEL_FORMAT_RGB_4444,
PIXEL_FORMAT_RGB_555,
PIXEL_FORMAT_RGB_565,
PIXEL_FORMAT_RGB_1555,
/* 9 reserved */
PIXEL_FORMAT_RGB_888,
PIXEL_FORMAT_RGB_8888,
PIXEL_FORMAT_RGB_PLANAR_888,
PIXEL_FORMAT_RGB_BAYER,
PIXEL_FORMAT_YUV_A422,
PIXEL_FORMAT_YUV_A444,
PIXEL_FORMAT_YUV_PLANAR_422,
PIXEL_FORMAT_YUV_PLANAR_420,
PIXEL_FORMAT_YUV_PLANAR_444,
PIXEL_FORMAT_YUV_SEMIPLANAR_422,
PIXEL_FORMAT_YUV_SEMIPLANAR_420,
PIXEL_FORMAT_YUV_SEMIPLANAR_444,
PIXEL_FORMAT_UYVY_PACKAGE_422,
PIXEL_FORMAT_YUYV_PACKAGE_422,
PIXEL_FORMAT_VYUY_PACKAGE_422,
PIXEL_FORMAT_YCbCr_PLANAR,
PIXEL_FORMAT_RGB_422,
PIXEL_FORMAT_RGB_420,
PIXEL_FORMAT_BUTT
} PIXEL_FORMAT_E;
typedef struct xm_VIDEO_VBI_INFO_S
{
XM_U32 au32Data[VIU_MAX_VBI_LEN];
XM_U32 u32Len;
}VIDEO_VBI_INFO_S;
typedef enum xm_VIDEO_FIELD_E
{
VIDEO_FIELD_TOP = 0x01, /* even field */
VIDEO_FIELD_BOTTOM = 0x02, /* odd field */
VIDEO_FIELD_INTERLACED = 0x03, /* two interlaced fields */
VIDEO_FIELD_FRAME = 0x04, /* frame */
VIDEO_FIELD_BUTT
} VIDEO_FIELD_E;
typedef struct xm_VIDEO_FRAME_S
{
XM_U32 u32Width;
XM_U32 u32Height;
VIDEO_FIELD_E u32Field;
PIXEL_FORMAT_E enPixelFormat;
XM_U32 u32PhyAddr[3];
XM_VOID *pVirAddr[3];
XM_U32 u32Stride[3];
/*********************************************************
u32Stride:
--- u32Stride[0]: YSize
--- u32Stride[2]: ErrSize(bit0~bit15: SizeH bit16~bit31:SizeV)
*********************************************************/
XM_U16 u16OffsetTop; /* top offset of show area */
XM_U16 u16OffsetBottom; /* bottom offset of show area */
XM_U16 u16OffsetLeft; /* left offset of show area */
XM_U16 u16OffsetRight; /* right offset of show area */
XM_U64 u64pts;
XM_U32 u32TimeRef;
XM_U32 u32PrivateData;
//VIDEO_VBI_INFO_S astVbiInfo[VIU_MAX_VBI_NUM];
}VIDEO_FRAME_S;
typedef struct xm_VIDEO_FRAME_INFO_S
{
VIDEO_FRAME_S stVFrame;
XM_U32 u32PoolId;
} VIDEO_FRAME_INFO_S;
typedef struct xmBITMAP_S
{
XM_U32 u32Handle;
XM_U32 u32Width;
XM_U32 u32Height;
XM_U32 u32Format;
XM_VOID *pData;
} BITMAP_S;
typedef struct XM_VPP_CFG_S
{
XM_BOOL bVppEn;
XM_BOOL bIeEn;
XM_BOOL bDnEn;
XM_BOOL bSpEn;
XM_BOOL bIencEn;
XM_S32 s32IeSth; /* IE Strength [0,10] */
XM_S32 s32SpSth; /* SP Strength [-4,5] */
XM_S32 s32DnSfCosSth; /* coarse DN sf Strength [0,3] */
XM_S32 s32DnSfIncSth; /* Inching of DN sf Strength [0,255] */
XM_S32 s32DnTfSth; /* DN tf Strength [0,4] */
} VPP_CFG_S;
typedef struct xm_SCALE_CFG_S
{
XM_BOOL bScaleEn;
XM_S32 s32DstWidth; /* the dest width after scale */
XM_S32 s32DstHeight; /* the dest height after scale */
} SCALE_CFG_S;
/* Ie */
typedef struct XM_VPP_IE_EX_S
{
XM_U32 u32RefRange;//
XM_U32 u32IeStrength;//
XM_U32 u32Black;
XM_U32 u32White;
} VPP_IE_EX_S;
/*dn*/
typedef struct
{
XM_U16 saMask[2];
XM_U16 weight[2];
} tVppCalcWnd;
typedef struct
{
XM_U8 wWndX, hWndX;
XM_U8 wWndY, hWndY;
XM_U8 wWndC, hWndC;
XM_U8 wWndD, hWndD; //
XM_U16 sfyMask[2];
XM_U8 sfyRange[2]; //
XM_U8 sfyStrength; //
XM_U8 sfyLimitedFlag; //
XM_U8 MADpExDirectSub : 1;
XM_U8 MADpExMask : 4;
XM_U8 _reserved_ : 3;
XM_U8 sfcStrength;
XM_U8 sfyMADpThresh, sfyMADpRate;/**/
XM_U16 sfyMSEiThresh[8];
XM_U8 rsfyThresh, rsfyRate, rsfyStrength, tfyStrength;
XM_U8 rsfcThresh, rsfcRate, rsfcStrength, tfcStrength;/**/
XM_U8 tfyMADpThresh, tfyMADpRate;
XM_U8 tfySNRpThresh, tfySNRpRate;
XM_U16 tfyMSEiThresh[8];
XM_U16 tfyMSEpThresh[8];
XM_U8 tfyMaxStrength;//
XM_U8 tfcMaxStrength;/**/
XM_U8 tfcMADpThresh, tfcMADpRate;
XM_U16 tfcMSEiThresh[8];
XM_U16 diyMSEiThresh[8];
XM_U8 tfyLimit;
XM_U8 noiseMADpThresh;
XM_U16 noiseMSDpThresh;
XM_U8 log2hStepMADp, log2hStepMSEi;
XM_U8 histMinMADp, histMaxMADp;
XM_U16 histMinMSEi, histMaxMSEi;
/*---------------------------------------------*/
tVppCalcWnd yWnd[2];
tVppCalcWnd cWnd[2];
} tVppDnCfg;
typedef tVppDnCfg VPP_DN_EX_S;
/* Sp */
typedef struct
{
XM_U8 strength;//
XM_U8 limit;//
XM_U8 black;
XM_U8 white;
} tVppSharpenCfg;
typedef tVppSharpenCfg VPP_SP_EX_S;
typedef struct xm_VPP_CFG_EX_S
{
VPP_IE_EX_S stIE_Ex;
VPP_DN_EX_S stDN_Ex;
VPP_SP_EX_S stSP_Ex;
} VPP_CFG_EX_S;
/* VI Mix-Capture info. */
typedef struct xm_VI_MIXCAP_STAT_S
{
XM_BOOL bMixCapMode; /* In mix-capture mode or not. */
XM_BOOL bHasDownScale; /* VI Frame is downscaled or not. */
} VI_MIXCAP_STAT_S;
/* VI output frame info. */
typedef struct xm_VI_FRAME_INFO_S
{
VI_MIXCAP_STAT_S stMixCapState; /* VI Mix-Capture info. */
VIDEO_FRAME_INFO_S stViFrmInfo; /* Video frame info. */
XM_BOOL bFlashed; /* Flashed Video frame or not. */
}VI_FRAME_INFO_S;
typedef enum xm_LDC_VIEW_TYPE_E
{
LDC_VIEW_TYPE_ALL = 0, /* View scale all but x and y independtly, this will keep both x and y axis ,but corner maybe lost*/
LDC_VIEW_TYPE_CROP, /* Not use view scale, this will lost some side and corner */
LDC_VIEW_TYPE_BUTT,
} LDC_VIEW_TYPE_E;
typedef struct xm_LDC_ATTR_S
{
LDC_VIEW_TYPE_E enViewType;
XM_S32 s32CenterXOffset; /* Horizontal offset of the image distortion center relative to image center. [-28,28]. */
XM_S32 s32CenterYOffset; /* Vertical offset of the image distortion center relative to image center. [-14,14]. */
XM_S32 s32Ratio; /* Distortion ratio. [0, 511]. */
} LDC_ATTR_S;
#endif /* _XM_COMM_VIDEO_H_ */

431
general/package/xiongmai-osdrv-xm530/files/include/isp/xm_common.h
View File

@ -1,431 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm_ae_common.h
Version : Initial Draft
Author : XM Isp software group
Created : 2015/6/27
Description : The common data type defination
Function List :
History :
1.Date : 2015/6/27
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef __XM_COMMON_H__
#define __XM_COMMON_H__
#include "xm_type.h"
#include "xm_defines.h"
#include "xm_comm_video.h"
#ifndef VER_X
#define VER_X 1
#endif
#ifndef VER_Y
#define VER_Y 0
#endif
#ifndef VER_Z
#define VER_Z 0
#endif
#ifndef VER_P
#define VER_P 0
#endif
#ifdef XM_DEBUG
#define VER_D " "
#else
#define VER_D " Release"
#endif
#define __MK_VERSION(x,y,z,p) #x"."#y"."#z"."#p
#define MK_VERSION(x,y,z,p) __MK_VERSION(x,y,z,p)
#define MPP_VERSION CHIP_NAME MPP_VER_PRIX MK_VERSION(VER_X,VER_Y,VER_Z,VER_P) VER_D
#define COM_VERSION MPP_VER_PRIX MK_VERSION(VER_X,VER_Y,VER_Z,VER_P) VER_D
#define VERSION_NAME_MAXLEN 64
typedef struct xm_MPP_VERSION_S
{
XM_CHAR aVersion[VERSION_NAME_MAXLEN];
}MPP_VERSION_S;
typedef struct xm_POINT_S
{
XM_S32 s32X;
XM_S32 s32Y;
}POINT_S;
typedef struct xm_SIZE_S
{
XM_U32 u32Width;
XM_U32 u32Height;
} SIZE_S;
typedef struct xm_RECT_S
{
XM_S32 s32X;
XM_S32 s32Y;
XM_U32 u32Width;
XM_U32 u32Height;
}RECT_S;
typedef enum xm_ROTATE_E
{
ROTATE_NONE = 0,
ROTATE_90 = 1,
ROTATE_180 = 2,
ROTATE_270 = 3,
ROTATE_BUTT
} ROTATE_E;
typedef XM_S32 AI_CHN;
typedef XM_S32 AO_CHN;
typedef XM_S32 AENC_CHN;
typedef XM_S32 ADEC_CHN;
typedef XM_S32 AUDIO_DEV;
typedef XM_S32 AVENC_CHN;
typedef XM_S32 VI_DEV;
typedef XM_S32 VI_WAY;
typedef XM_S32 VI_CHN;
typedef XM_S32 VO_DEV;
typedef XM_S32 VO_LAYER;
typedef XM_S32 VO_CHN;
typedef XM_S32 VENC_CHN;
typedef XM_S32 VDEC_CHN;
typedef XM_S32 VENC_GRP;
typedef XM_S32 VO_GRP;
typedef XM_S32 VDA_CHN;
typedef XM_S32 IVE_HANDLE;
typedef XM_S32 ISP_DEV;
typedef XM_S32 SENSOR_ID;
#define XM_INVALID_CHN (-1)
#define XM_INVALID_WAY (-1)
#define XM_INVALID_LAYER (-1)
#define XM_INVALID_DEV (-1)
#define XM_INVALID_HANDLE (-1)
#define XM_INVALID_VALUE (-1)
#define XM_INVALID_TYPE (-1)
typedef enum xm_MOD_ID_E
{
XM_ID_CMPI = 0,
XM_ID_VB = 1,
XM_ID_SYS = 2,
XM_ID_VALG = 3,
#if 1
/*
VDEC内部会创建VB Pool, VDEC销毁的时候销毁VB Pool,
但是如果其他模块使用了这个图像, 销毁的时候VB--会报错;
所以VDEC模块要等其他模块销毁之后再销毁 f65132注
ctrl+c退出时如果先销毁CHNL再退出VDEC,则VDEC退出时会unregister CHNL，
因此时CHNL已被销毁，所以unregister不成功，打印出错信息。
为解决这个问题，需要把CHNL和VDEC的id顺序互换
*/
XM_ID_CHNL = 4,
XM_ID_VDEC = 5,
XM_ID_GROUP = 6,
XM_ID_VENC = 7,
XM_ID_VPSS = 8,
XM_ID_VDA = 9,
XM_ID_H264E = 10,
XM_ID_JPEGE = 11,
XM_ID_MPEG4E = 12,
#else
XM_ID_CHNL = 4,
XM_ID_GROUP = 5,
XM_ID_VENC = 6,
XM_ID_VPSS = 7,
XM_ID_VDA = 8,
XM_ID_H264E = 9,
XM_ID_JPEGE = 10,
XM_ID_MPEG4E = 11,
XM_ID_VDEC = 12,
#endif
XM_ID_H264D = 13,
XM_ID_JPEGD = 14,
XM_ID_VOU = 15,
XM_ID_VIU = 16,
XM_ID_DSU = 17,
XM_ID_RGN = 18,
XM_ID_RC = 19,
XM_ID_SIO = 20,
XM_ID_AI = 21,
XM_ID_AO = 22,
XM_ID_AENC = 23,
XM_ID_ADEC = 24,
XM_ID_AVENC = 25,
XM_ID_PCIV = 26,
XM_ID_PCIVFMW = 27,
XM_ID_ISP = 28,
XM_ID_IVE = 29,
/* there is a hole */
XM_ID_DCCM = 31,
XM_ID_DCCS = 32,
XM_ID_PROC = 33,
XM_ID_LOG = 34,
XM_ID_MST_LOG = 35,
XM_ID_VD = 36,
XM_ID_VCMP = 38,
XM_ID_FB = 39,
XM_ID_HDMI = 40,
XM_ID_VOIE = 41,
XM_ID_TDE = 42,
XM_ID_USR = 43,
XM_ID_VEDU = 44,
XM_ID_BUTT,
} MOD_ID_E;
typedef struct xm_MPP_CHN_S
{
MOD_ID_E enModId;
XM_S32 s32DevId;
XM_S32 s32ChnId;
} MPP_CHN_S;
#define MPP_MOD_VIU "vi"
#define MPP_MOD_VOU "vo"
#define MPP_MOD_HDMI "hdmi"
#define MPP_MOD_DSU "dsu"
#define MPP_MOD_CHNL "chnl"
#define MPP_MOD_VENC "venc"
#define MPP_MOD_GRP "grp"
#define MPP_MOD_VDA "vda"
#define MPP_MOD_VPSS "vpss"
#define MPP_MOD_RGN "rgn"
#define MPP_MOD_IVE "ive"
#define MPP_MOD_H264E "h264e"
#define MPP_MOD_JPEGE "jpege"
#define MPP_MOD_MPEG4E "mpeg4e"
#define MPP_MOD_VDEC "vdec"
#define MPP_MOD_H264D "h264d"
#define MPP_MOD_JPEGD "jpegd"
#define MPP_MOD_AI "ai"
#define MPP_MOD_AO "ao"
#define MPP_MOD_AENC "aenc"
#define MPP_MOD_ADEC "adec"
#define MPP_MOD_SIO "sio"
#define MPP_MOD_VB "vb"
#define MPP_MOD_SYS "sys"
#define MPP_MOD_CMPI "cmpi"
#define MPP_MOD_PCIV "pciv"
#define MPP_MOD_PCIVFMW "pcivfmw"
#define MPP_MOD_PROC "proc"
#define MPP_MOD_LOG "logmpp"
#define MPP_MOD_MST_LOG "mstlog"
#define MPP_MOD_DCCM "dccm"
#define MPP_MOD_DCCS "dccs"
#define MPP_MOD_VCMP "vcmp"
#define MPP_MOD_FB "fb"
#define MPP_MOD_RC "rc"
#define MPP_MOD_VOIE "voie"
#define MPP_MOD_TDE "tde"
#define MPP_MOD_ISP "isp"
#define MPP_MOD_ACODEC "acodec"
/* We just coyp this value of payload type from RTP/RTSP definition */
typedef enum
{
PT_PCMU = 0,
PT_1016 = 1,
PT_G721 = 2,
PT_GSM = 3,
PT_G723 = 4,
PT_DVI4_8K = 5,
PT_DVI4_16K = 6,
PT_LPC = 7,
PT_PCMA = 8,
PT_G722 = 9,
PT_S16BE_STEREO = 10,
PT_S16BE_MONO = 11,
PT_QCELP = 12,
PT_CN = 13,
PT_MPEGAUDIO = 14,
PT_G728 = 15,
PT_DVI4_3 = 16,
PT_DVI4_4 = 17,
PT_G729 = 18,
PT_G711A = 19,
PT_G711U = 20,
PT_G726 = 21,
PT_G729A = 22,
PT_LPCM = 23,
PT_CelB = 25,
PT_JPEG = 26,
PT_CUSM = 27,
PT_NV = 28,
PT_PICW = 29,
PT_CPV = 30,
PT_H261 = 31,
PT_MPEGVIDEO = 32,
PT_MPEG2TS = 33,
PT_H263 = 34,
PT_SPEG = 35,
PT_MPEG2VIDEO = 36,
PT_AAC = 37,
PT_WMA9STD = 38,
PT_HEAAC = 39,
PT_PCM_VOICE = 40,
PT_PCM_AUDIO = 41,
PT_AACLC = 42,
PT_MP3 = 43,
PT_ADPCMA = 49,
PT_AEC = 50,
PT_X_LD = 95,
PT_H264 = 96,
PT_D_GSM_HR = 200,
PT_D_GSM_EFR = 201,
PT_D_L8 = 202,
PT_D_RED = 203,
PT_D_VDVI = 204,
PT_D_BT656 = 220,
PT_D_H263_1998 = 221,
PT_D_MP1S = 222,
PT_D_MP2P = 223,
PT_D_BMPEG = 224,
PT_MP4VIDEO = 230,
PT_MP4AUDIO = 237,
PT_VC1 = 238,
PT_JVC_ASF = 255,
PT_D_AVI = 256,
PT_DIVX3 = 257,
PT_AVS = 258,
PT_REAL8 = 259,
PT_REAL9 = 260,
PT_VP6 = 261,
PT_VP6F = 262,
PT_VP6A = 263,
PT_SORENSON =264,
PT_MAX = 265,
/* add by xm_silicon */
PT_AMR = 1001,
PT_MJPEG = 1002,
PT_AMRWB = 1003,
PT_BUTT
}PAYLOAD_TYPE_E;
typedef enum xm_VOU_WHO_SENDPIC_E
{
VOU_WHO_SENDPIC_VIU = 0,
VOU_WHO_SENDPIC_VDEC = 1,
VOU_WHO_SENDPIC_PCIV = 2,
VOU_WHO_SENDPIC_VPP = 3,
VOU_WHO_SENDPIC_USR = 4,
VOU_WHO_SENDPIC_BUTT
} VOU_WHO_SENDPIC_E;
#if 1
//滤波系数的定义可能与芯片有关，具体实现时再考虑放在哪里
/* horizontal scale filter coefficient of dsu
** which affect image quality of encoding and preview.
** normally the filter can be set be DSU_HSCALE_FILTER_DEFAULT
** which means sdk will choose filter automatically.Otherwise,
** you can choose other filter
** Notes:65M means 6.5
*/
typedef enum xm_DSU_HSCALE_FILTER_E
{
DSU_HSCALE_FILTER_DEFAULT = 0,
DSU_HSCALE_FILTER_C_65M,
DSU_HSCALE_FILTER_CG_56M,
DSU_HSCALE_FILTER_LC_45M,
DSU_HSCALE_FILTER_CG_3M,
DSU_HSCALE_FILTER_CG_2M,
DSU_HSCALE_FILTER_CG_1M,
DSU_HSCALE_FILTER_BUTT
}DSU_HSCALE_FILTER_E;
/* vertical scale filter coefficient of dsu
** which affect image quality of encoding and preview.
** normally the filter can be set be DSU_VSCALE_FILTER_DEFAULT
** which means sdk will choose filter automatically.Otherwise,
** you can choose other filter
** Notes:38M means 3.8
*/
typedef enum xm_DSU_VSCALE_FILTER_E
{
DSU_VSCALE_FILTER_DEFAULT = 0,
DSU_VSCALE_FILTER_S_6M,
DSU_VSCALE_FILTER_S_5M,
DSU_VSCALE_FILTER_S_4M,
DSU_VSCALE_FILTER_S_38M,
DSU_VSCALE_FILTER_S_37M,
DSU_VSCALE_FILTER_S_36M,
DSU_VSCALE_FILTER_S_25M,
DSU_VSCALE_FILTER_S_2M,
DSU_VSCALE_FILTER_S_15M,
DSU_VSCALE_FILTER_S_12M,
DSU_VSCALE_FILTER_S_11M,
DSU_VSCALE_FILTER_S_1M,
DSU_VSCALE_FILTER_BUTT
}DSU_VSCALE_FILTER_E;
/*DSU filter param type*/
typedef enum xm_DSU_FILTER_PARAM_TYPE
{
FILTER_PARAM_TYPE_NORM = 0,
FILTER_PARAM_TYPE_EX,
FILTER_PARAM_TYPE_EX2,
FILTER_PARAM_TYPE_USER1,
FILTER_PARAM_TYPE_USER2,
FILTER_PARAM_TYPE_BUTT
}DSU_FILTER_PARAM_TYPE;
#define DSU_HFILTER_PARAM_NUM 792
#define DSU_VFILTER_PARAM_NUM 480
typedef struct xm_DSU_FILTER_PARAM_S
{
DSU_FILTER_PARAM_TYPE enFiltType;
XM_U8 au8HParamTable[DSU_HFILTER_PARAM_NUM];
XM_U8 au8VParamTable[DSU_VFILTER_PARAM_NUM];
}DSU_FILTER_PARAM_S;
#endif
#endif /* _XM_COMMON_H_ */

111
general/package/xiongmai-osdrv-xm530/files/include/isp/xm_debug.h
View File

@ -1,111 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm_debug.h
Version : Initial Draft
Author : XM Isp software group
Created : 2015/6/27
Description : The common data type defination
Function List :
History :
1.Date : 2015/6/27
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef __XM_DEBUG_H__
#define __XM_DEBUG_H__
#include "xm_type.h"
#include "xm_common.h"
#define _EX__FILE_LINE(fxx,lxx) "[File]:"fxx"\n[Line]:"#lxx"\n[Info]:"
#define EX__FILE_LINE(fxx,lxx) _EX__FILE_LINE(fxx,lxx)
#define __FILE_LINE__ EX__FILE_LINE(__FILE__, __LINE__)
#define XM_DBG_EMERG 0 /* system is unusable */
#define XM_DBG_ALERT 1 /* action must be taken immediately */
#define XM_DBG_CRIT 2 /* critical conditions */
#define XM_DBG_ERR 3 /* error conditions */
#define XM_DBG_WARN 4 /* warning conditions */
#define XM_DBG_NOTICE 5 /* normal but significant condition */
#define XM_DBG_INFO 6 /* informational */
#define XM_DBG_DEBUG 7 /* debug-level messages */
typedef struct xm_LOG_LEVEL_CONF_S
{
MOD_ID_E enModId;
XM_S32 s32Level;
XM_CHAR cModName[16];
} LOG_LEVEL_CONF_S;
#ifndef __KERNEL__
/******************************************************************************
** For User Mode : XM_PRINT, XM_ASSERT, XM_TRACE
******************************************************************************/
#define XM_PRINT printf
#ifdef XM_DEBUG
/* Using samples: XM_ASSERT(x>y); */
#define XM_ASSERT(expr) \
do{ \
if (!(expr)) { \
printf("\nASSERT failed at:\n"\
" >File name: %s\n" \
" >Function : %s\n" \
" >Line No. : %d\n" \
" >Condition: %s\n", \
__FILE__,__FUNCTION__, __LINE__, #expr);\
_exit(-1);\
} \
}while(0)
/* Using samples:
** XM_TRACE(XM_DBG_DEBUG, XM_ID_CMPI, "Test %d, %s\n", 12, "Test");
**/
#define XM_TRACE(level, enModId, fmt...) fprintf(stderr,##fmt)
#else
#define XM_ASSERT(expr)
#define XM_TRACE(level, enModId, fmt...)
#endif
#else
/******************************************************************************
** For Linux Kernel : XM_PRINT, XM_ASSERT, XM_TRACE
******************************************************************************/
#define XM_PRINT printk
extern XM_S32 XM_ChkLogLevel(XM_S32 s32Levle, MOD_ID_E enModId);
asmlinkage int XM_LOG(XM_S32 level, MOD_ID_E enModId,const char *fmt, ...);
#ifdef XM_DEBUG
/* Using samples: XM_ASSERT(x>y); */
#define XM_ASSERT(expr) \
do{ \
if (!(expr)) { \
panic("\nASSERT failed at:\n" \
" >File name: %s\n" \
" >Function : %s\n" \
" >Line No. : %d\n" \
" >Condition: %s\n", \
__FILE__,__FUNCTION__, __LINE__, #expr);\
} \
}while(0)
/* Using samples:
** XM_TRACE(XM_DBG_DEBUG, XM_ID_CMPI, "Test %d, %s\n", 12, "Test");
**/
#define XM_TRACE XM_LOG
#else
#define XM_ASSERT(expr)
#define XM_TRACE(level, enModId, fmt...)
#endif
#endif /* end of __KERNEL__ */
#endif /* __XM_DEBUG_H__ */

363
general/package/xiongmai-osdrv-xm530/files/include/isp/xm_defines.h
View File

@ -1,363 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm_defines.h
Version : Initial Draft
Author : XM Isp software group
Created : 2015/6/27
Description : The common data type defination
Function List :
History :
1.Date : 2015/6/27
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef __XM_DEFINES_H__
#define __XM_DEFINES_H__
#include "xm_type.h"
#define LINE_LEN_BIT 5
#define LINE_LEN (1<<LINE_LEN_BIT)
#define LINE_BASE_MASK (~(LINE_LEN-1))
typedef enum {
DSP_XM510 = 0x100,
DSP_XM530,
DSP_XM580,
DSP_XM320,
DSP_XM322,
DSP_XM350,
DSP_XM380,
DSP_XM310 = 0x110, // 提供给PQ_Tool
DSP_XM310V300 = 0x113, // 提供给PQ_Tool
DSP_XM330V200 = 0x122, // 提供给PQ_Tool
DSP_XM550 = 0x155,
NR_DSPCHIP
}XM_DSP_CHIP;
typedef enum {
SENSORCLK_18M = 0,
SENSORCLK_24M = 1,
SENSORCLK_27M = 2,
SENSORCLK_37x125M = 3,
SENSORCLK_24M_42M = 4,
SENSORCLK_18x5625M = 5,
}XM_SENSOR_CLK;
typedef enum {
SNSIO_12V = 0,
SNSIO_15V,
SNSIO_18V,
SNSIO_28V,
SNSIO_33V,
}XM_SENSOR_IO;
typedef enum {
MIPI_8BIT = 0,
MIPI_10BIT,
MIPI_12BIT,
}XM_MIPI_DEPTH;
typedef enum {
MIPI_1LANE = 0,
MIPI_2LANE,
MIPI_4LANE,
}XM_MIPI_LANE;
typedef enum xm_XM_SENSOR_BWIDE
{
SENSBWIDE_8BIT = 0,
SENSBWIDE_10BIT ,
SENSBWIDE_12BIT ,
}XM_SENSOR_BWIDE;
typedef enum xm_XM_SENSOR_CONT
{
SENSCONT_DVP = 0,
SENSCONT_MIPI = 1,
SENSCONT_BUTT = 0xFF,
}XM_SENSOR_CONT;
typedef enum xm_XM_FUNEXT
{
FUNBIT_XVI_MASK = 0,
FUNBIT_AF_MASK = 1,
FUNBIT_BUTT
}XM_FUNEXT;
typedef enum xm_PROFILE
{
P720_ = 0,
P1080_ ,
P960_ ,
P1536_ ,
P4M_ ,
P5M_ ,
P4K_ ,
PCVBS_=100,
P1080_S1 = 101, // 1080*1080
P1080_S2 = 102, // 1280*1080
PNULL ,
}PROFILE ;
typedef enum xm_VSTD
{
VSTDNULL = 0,
PALS ,
NTSCS ,
NRT15 ,
NRT12p5 ,
}VSTD;
typedef enum xm_txvenc_type
{
TXVENC_AHD = 0,
TXVENC_CVI = 1,
TXVENC_TVI = 2,
TXVENC_CVBS = 3,
TXVENC_AHD_15FPS = 4,
//TXVENC_TVI_V1 = 7,
TXVENC_BUTT
}TXVENC_TYPE;
typedef enum xm_ipcvenc_type
{
IPC_Hx264 = 0,
IPC_Hx265 = 1,
IPCVENC_BUTT
}IPCVENC_TYPE;
typedef struct xm_UPSCALER_CFG
{
PROFILE VPIXEL; // 0:720P 1:1080P 2:960P 3:NULL
VSTD VSTDB; // 0:NULL 1:PAL 2:NTSC
}UPSCALER_CFG;
typedef struct xm_SENSOR_IO_V
{
XM_U8 SsDvdd;
XM_U8 SsAvdd;
XM_U8 SsDovdd;
}XM_SENSOR_IO_V;
typedef struct xm_SENSOR_MIPI
{
XM_U8 MpDepth;
XM_U8 MpLane;
}XM_SENSOR_MIPI;
typedef struct xm_product_info
{
XM_U32 u32ProductType;
XM_U32 u32DSPType;
XM_U32 u32SensorType;
XM_U8 u8SensorClk;
XM_U8 u8SnsCommMode; // 0:I2C 1:SPI
XM_SENSOR_IO_V stSnsIO; // 1.8v/3.3v
XM_U8 u8StdType; //0: unknow 1:PAL 2:NTSC
PROFILE u8RsltType; // 0: 720P 1:1080P 2:960P 3:1536P 101:P1080_S1 102:P1080_S2
XM_BOOL bHsyncRecEn; // 0:Disable 1:Enable
XM_SENSOR_BWIDE SnsBwide; //0:8bit 1:10bit 2:12bit
XM_SENSOR_CONT SnsConnect; //0:DVP 1:MIPI
XM_SENSOR_MIPI SnsMipi;
XM_U8 u8FunExt; // XM_FUNEXT
XM_U8 u8SnsHDRmark; //0:normal 1:build-in 2:wdr
XM_U8 u8Encoder; //0:AHD 1:CVI 2:TVI 3;CVBS
/****************************
u8IRLed:
bit0:
0 普通模式（红外同步/自动同步... (硬件控制红外灯)）
1 软件控制灯
bit4:
0 软光敏
1 硬光敏
****************************/
XM_U8 u8IRLed;
}XM_PRODUCT_INFO;
typedef enum xm_oem
{
General = 0,
JvFeng,
XMJP,
}OEM;
#if 0
inline void InvalidateDcache(unsigned long addr, unsigned long len)
{
unsigned long end;
//TODO: cache刷新需要重写
return ;
addr &= LINE_BASE_MASK;
len >>= LINE_LEN_BIT;
end = addr + len*LINE_LEN;
while(addr != end)
{
asm("mcr p15, 0, %0, c7, c6, 1"::"r"(addr));
addr += LINE_LEN;
}
return;
}
inline void FlushDcache(unsigned long addr, unsigned long len)
{
unsigned long end;
//TODO: cache刷新需要重写
return ;
addr &= LINE_BASE_MASK;
len >>= LINE_LEN_BIT;
end = addr + len*LINE_LEN;
while(addr != end)
{
asm("mcr p15, 0, %0, c7, c10, 1"::"r"(addr));
addr += LINE_LEN;
}
return;
}
#endif
/* For Sys */
#define DEFAULT_ALIGN 16
#define MAX_MMZ_NAME_LEN 16
#define MAX_NODE_NUM 16
/* For VDA */
#define VDA_MAX_NODE_NUM 32
#define VDA_MAX_INTERNAL 256
#define VDA_CHN_NUM_MAX 32
#define VDA_MAX_WIDTH 960
#define VDA_MAX_HEIGHT 576
/* For VENC */
#define VENC_MAX_NAME_LEN 16
#define VENC_MAX_CHN_NUM 64
#define VENC_MAX_GRP_NUM 64
#define H264E_MAX_WIDTH 1920
#define H264E_MAX_HEIGHT 2048
#define H264E_MIN_WIDTH 160
#define H264E_MIN_HEIGHT 64
#define JPEGE_MAX_WIDTH 8192
#define JPEGE_MAX_HEIGHT 8192
#define JPEGE_MIN_WIDTH 64
#define JPEGE_MIN_HEIGHT 64
#define VENC_MAX_ROI_NUM 8 /* 最大支持8个ROI区域 */
#define H264E_MIN_HW_INDEX 0
#define H264E_MAX_HW_INDEX 5
#define H264E_MIN_VW_INDEX 0
#define H264E_MAX_VW_INDEX 2
/* For VDEC, hi3518 not support */
#define VDEC_MAX_CHN_NUM 0
/* For Region */
#define RGN_HANDLE_MAX 1024
#define OVERLAY_MAX_NUM 8
#define COVEREX_MAX_NUM 16
#define COVER_MAX_NUM 4
#define OVERLAYEX_MAX_NUM 0
/* number of channle and device on video input unit of chip
* Note! VIU_MAX_CHN_NUM is NOT equal to VIU_MAX_DEV_NUM
* multiplied by VIU_MAX_CHN_NUM, because all VI devices
* can't work at mode of 4 channles at the same time.
*/
#define VIU_MAX_DEV_NUM 1
#define VIU_MAX_WAY_NUM_PER_DEV 1
#define VIU_MAX_CHN_NUM_PER_DEV 1
#define VIU_MAX_PHYCHN_NUM 1
#define VIU_EXT_CHN_START VIU_MAX_PHYCHN_NUM
#define VIU_MAX_EXT_CHN_NUM 16
#define VIU_MAX_EXTCHN_BIND_PER_CHN 8
#define VIU_MAX_CHN_NUM (VIU_MAX_PHYCHN_NUM + VIU_MAX_EXT_CHN_NUM)
#define VIU_CHNID_DEV_FACTOR 2
/* 3518本不支持级联，这里宏定义这些信息，只是为了编译通过 */
#define VIU_MAX_CAS_CHN_NUM 2
#define VIU_SUB_CHN_START 16 /* 定义次通道起始宏*/
#define VIU_CAS_CHN_START 32 /* 定义级联通道起始宏*/
/* max number of VBI region*/
#define VIU_MAX_VBI_NUM 2
/* max length of one VBI region (by word)*/
#define VIU_MAX_VBI_LEN 8
#define VO_MIN_CHN_WIDTH 32 /* channel minimal width */
#define VO_MIN_CHN_HEIGHT 32 /* channel minimal height */
#define VO_MAX_ZOOM_RATIO 1000 /* max zoom ratio, 1000 means 100% scale */
#define VO_MAX_DEV_NUM 1 /* max dev num */
#define VO_MAX_LAYER_NUM 1 /* max layer num */
#define VO_MAX_CHN_NUM 32 /* mac chn num */
#define PIP_MAX_CHN_NUM 0
#define VHD_MAX_CHN_NUM 0 /* max VHD chn num */
#define VO_MAX_LAYER_IN_DEV 2 /* max layer num of each dev */
#define VO_CAS_MAX_PAT 128 /* cascade pattern max number */
#define VO_CAS_MAX_POS_32RGN 32 /* cascade position max number */
#define VO_CAS_MAX_POS_64RGN 64 /* cascade position max number */
#define VO_MAX_VIRT_DEV_NUM 4 /* max virtual dev num*/
#define VO_VIRT_DEV_0 3 /* virtual display device 1 */
#define VO_VIRT_DEV_1 4 /* virtual display device 2 */
#define VO_VIRT_DEV_2 5 /* virtual display device 3 */
#define VO_VIRT_DEV_3 6 /* virtual display device 4 */
#define VO_MAX_GFX_LAYER_PER_DEV 1
#define VOU_GRAPHICS_LAYER_NUM 1
#define VO_MIN_TOLERATE 1 /* min play toleration 1ms */
#define VO_MAX_TOLERATE 100000 /* max play toleration 100s */
#define AIO_MAX_CHN_NUM 2
#define AENC_MAX_CHN_NUM 32
#define ADEC_MAX_CHN_NUM 32
#define AI_DEV_MAX_NUM 1
#define AO_DEV_MIN_NUM 0
#define AO_DEV_MAX_NUM 1
#define SIO_MAX_NUM 1
#define VPSS_MAX_GRP_NUM 128
#define VPSS_MAX_PHY_CHN_NUM 2
#define VPSS_MAX_EXT_CHN_NUM 5
#define VPSS_MAX_CHN_NUM (VPSS_MAX_PHY_CHN_NUM + VPSS_MAX_EXT_CHN_NUM + 1)
#define VPSS_BSTR_CHN 0
#define VPSS_LSTR_CHN 1
#define VPSS_BYPASS_CHN 2
#define PCIV_MAX_CHN_NUM 0 /* max pciv channel number in each pciv device */
#define RC_MAD_HIST_SIZE 64
#define RC_MSE_HIST_SIZE 128
#define RC_MAX_BLINK_QP 35
#ifdef CHIPID_XM580
#define ISP_NUM_MAX (2) //(2)
#else
#define ISP_NUM_MAX (1) //(2)
#endif
#endif /* __XM_DEFINES_H__ */

100
general/package/xiongmai-osdrv-xm530/files/include/isp/xm_errno.h
View File

@ -1,100 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm_errno.h
Version : Initial Draft
Author : XM Isp software group
Created : 2015/6/27
Description : The common data type defination
Function List :
History :
1.Date : 2015/6/27
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef __XM_ERRNO_H__
#define __XM_ERRNO_H__
#include "xm_debug.h"
#define XM_ERR_APPID (0x80000000L + 0x20000000L)
typedef enum xm_ERR_LEVEL_E
{
EN_ERR_LEVEL_DEBUG = 0, /* debug-level */
EN_ERR_LEVEL_INFO, /* informational */
EN_ERR_LEVEL_NOTICE, /* normal but significant condition */
EN_ERR_LEVEL_WARNING, /* warning conditions */
EN_ERR_LEVEL_ERROR, /* error conditions */
EN_ERR_LEVEL_CRIT, /* critical conditions */
EN_ERR_LEVEL_ALERT, /* action must be taken immediately */
EN_ERR_LEVEL_FATAL, /* just for compatibility with previous version */
EN_ERR_LEVEL_BUTT
}ERR_LEVEL_E;
/******************************************************************************
|----------------------------------------------------------------|
| 1 | APP_ID | MOD_ID | ERR_LEVEL | ERR_ID |
|----------------------------------------------------------------|
|<--><--7bits----><----8bits---><--3bits---><------13bits------->|
******************************************************************************/
#define XM_DEF_ERR( module, level, errid) \
((XM_S32)( (XM_ERR_APPID) | ((module) << 16 ) | ((level)<<13) | (errid) ))
/* NOTE! the following defined all common error code,
** all module must reserved 0~63 for their common error code
*/
typedef enum xm_EN_ERR_CODE_E
{
EN_ERR_INVALID_DEVID = 1, /* invlalid device ID */
EN_ERR_INVALID_CHNID = 2, /* invlalid channel ID */
EN_ERR_ILLEGAL_PARAM = 3, /* at lease one parameter is illagal
* eg, an illegal enumeration value */
EN_ERR_EXIST = 4, /* resource exists */
EN_ERR_UNEXIST = 5, /* resource unexists */
EN_ERR_NULL_PTR = 6, /* using a NULL point */
EN_ERR_NOT_CONFIG = 7, /* try to enable or initialize system, device
** or channel, before configing attribute */
EN_ERR_NOT_SUPPORT = 8, /* operation or type is not supported by NOW */
EN_ERR_NOT_PERM = 9, /* operation is not permitted
** eg, try to change attribute */
EN_ERR_NOMEM = 12,/* failure caused by malloc memory */
EN_ERR_NOBUF = 13,/* failure caused by malloc buffer */
EN_ERR_BUF_EMPTY = 14,/* no data in buffer */
EN_ERR_BUF_FULL = 15,/* no buffer for new data */
EN_ERR_SYS_NOTREADY = 16,/* System is not ready,maybe not initialed or
** loaded. Returning the error code when opening
** a device file failed. */
EN_ERR_BADADDR = 17,/* bad address,
** eg. used for copy_from_user & copy_to_user */
EN_ERR_BUSY = 18,/* resource is busy,
** eg. destroy a venc chn without unregister it */
EN_ERR_BUTT = 63,/* maxium code, private error code of all modules
** must be greater than it */
}EN_ERR_CODE_E;
/*
** following is an example for defining error code of VDA module
** #define XM_ERR_MD_INVALID_CHNID XM_DEF_ERR(XM_ID_VDA, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_CHNID)
**
*/
#endif /* __XM_ERRNO_H__ */

103
general/package/xiongmai-osdrv-xm530/files/include/isp/xm_i2c.h
View File

@ -1,103 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm_i2c.h
Version : Initial Draft
Author : XM Isp software group
Created : 2015/6/27
Description : The common data type defination
Function List :
History :
1.Date : 2015/6/27
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef __XM_I2C_H__
#define __XM_I2C_H__
typedef struct I2C_DATA_S
{
unsigned char dev_addr;
unsigned int reg_addr;
unsigned int addr_byte_num;
unsigned int data;
unsigned int data_byte_num;
}I2C_DATA_S ;
typedef struct I2C_DATA_STR_
{
unsigned char dev_addr;
// unsigned int reg_addr;
unsigned char *data;
unsigned char addr_byte_num;
unsigned char data_byte_num;
}I2C_DATA_STR ;
#define READ_OPERATION (1)
#define WRITE_OPERATION 0xfe
#define CMD_I2C_WRITE 0x01
#define CMD_I2C_READ 0x03
/* I2C_CTRL_REG */
#define I2C_ENABLE (1 << 8)
#define I2C_UNMASK_TOTAL (1 << 7)
#define I2C_UNMASK_START (1 << 6)
#define I2C_UNMASK_END (1 << 5)
#define I2C_UNMASK_SEND (1 << 4)
#define I2C_UNMASK_RECEIVE (1 << 3)
#define I2C_UNMASK_ACK (1 << 2)
#define I2C_UNMASK_ARBITRATE (1<< 1)
#define I2C_UNMASK_OVER (1 << 0)
#define I2C_UNMASK_ALL (I2C_UNMASK_START | I2C_UNMASK_END | \
I2C_UNMASK_SEND | I2C_UNMASK_RECEIVE | \
I2C_UNMASK_ACK | I2C_UNMASK_ARBITRATE | \
I2C_UNMASK_OVER)
/* I2C_COM_REB */
#define I2C_SEND_ACK (~(1 << 4))
#define I2C_START (1 << 3)
#define I2C_READ (1 << 2)
#define I2C_WRITE (1 << 1)
#define I2C_STOP (1 << 0)
/* I2C_ICR_REG */
#define I2C_CLEAR_START (1 << 6)
#define I2C_CLEAR_END (1 << 5)
#define I2C_CLEAR_SEND (1 << 4)
#define I2C_CLEAR_RECEIVE (1 << 3)
#define I2C_CLEAR_ACK (1 << 2)
#define I2C_CLEAR_ARBITRATE (1 << 1)
#define I2C_CLEAR_OVER (1 << 0)
#define I2C_CLEAR_ALL (I2C_CLEAR_START | I2C_CLEAR_END | \
I2C_CLEAR_SEND | I2C_CLEAR_RECEIVE | \
I2C_CLEAR_ACK | I2C_CLEAR_ARBITRATE | \
I2C_CLEAR_OVER)
/* I2C_SR_REG */
#define I2C_BUSY (1 << 7)
#define I2C_START_INTR (1 << 6)
#define I2C_END_INTR (1 << 5)
#define I2C_SEND_INTR (1 << 4)
#define I2C_RECEIVE_INTR (1 << 3)
#define I2C_ACK_INTR (1 << 2)
#define I2C_ARBITRATE_INTR (1 << 1)
#define I2C_OVER_INTR (1 << 0)
int XM_I2C_WriteConfig(unsigned char dev_addr);
int XM_I2C_Write(unsigned char dev_addr, unsigned int reg_addr, unsigned int addr_byte_num, unsigned int data, unsigned int data_byte_num);
int XM_I2C_Read (unsigned char dev_addr, unsigned int reg_addr, unsigned int addr_byte_num, unsigned int data_byte_num);
#endif

41
general/package/xiongmai-osdrv-xm530/files/include/isp/xm_isp_debug.h
View File

@ -1,41 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm_isp_debug.h
Version : Initial Draft
Author : XM Isp software group
Created : 2015/6/27
Description : The common data type defination
Function List :
History :
1.Date : 2015/6/27
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef __XM_ISP_DEBUG_H__
#define __XM_ISP_DEBUG_H__
#include "xm_debug.h"
#if 0
#define PRINT_DEBUG_INFO
#endif
#if 0
#define PRINT_INFO_2FILE
#endif
#define ISP_TRACE(level, fmt...)\
do{ \
XM_TRACE(level,XM_ID_ISP,"[Func]:%s [Line]:%d [Info]:",__FUNCTION__, __LINE__);\
XM_TRACE(level,XM_ID_ISP,##fmt);\
}while(0)
/* To avoid divide-0 exception in code. */
#define DIV_0_TO_1(a) ( (0 == (a)) ? 1 : (a) )
#endif /* __XM_ISP_DEBUG_H__ */

276
general/package/xiongmai-osdrv-xm530/files/include/isp/xm_math.h
View File

@ -1,276 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm_math.h
Version : Initial Draft
Author : XM Isp software group
Created : 2015/6/27
Description : The common data type defination
Function List :
History :
1.Date : 2015/6/27
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef __XM_MATH_H__
#define __XM_MATH_H__
#include "xm_type.h"
/******************************************************************************
** ABS(x) absolute value of x
** SIGN(x) sign of x
** CMP(x,y) 0 if x==y; 1 if x>y; -1 if x<y
******************************************************************************/
#define ABS(x) ( (x) >= 0 ? (x) : (-(x)) )
#define SIGN(x) ( (x) >= 0 ? 1 : -1 )
#define CMP(x,y) (((x) == (y)) ? 0 : (((x) > (y)) ? 1 : -1))
/******************************************************************************
** MAX2(x,y) maximum of x and y
** MIN2(x,y) minimum of x and y
** MAX3(x,y,z) maximum of x, y and z
** MIN3(x,y,z) minimun of x, y and z
** MEDIAN(x,y,z) median of x,y,z
** MEAN2(x,y) mean of x,y
******************************************************************************/
#define MAX2(x,y) ( (x)>(y) ? (x):(y) )
#define MIN2(x,y) ( (x)<(y) ? (x):(y) )
#define MAX3(x,y,z) ( (x)>(y) ? MAX2(x,z) : MAX2(y,z) )
#define MIN3(x,y,z) ( (x)<(y) ? MIN2(x,z) : MIN2(y,z) )
#define MEDIAN(x,y,z) (((x)+(y)+(z) - MAX3(x,y,z)) - MIN3(x,y,z) )
#define MEAN2(x,y) (((x)+(y)) >> 1 )
/******************************************************************************
** CLIP3(x,min,max) clip x within [min,max]
** WRAP_MAX(x,max,min) wrap to min if x equal max
** WRAP_MIN(x,min,max) wrap to max if x equal min
** VALUE_BETWEEN(x,min.max) True if x is between [min,max] inclusively.
******************************************************************************/
#define CLIP3(x,min,max) ( (x)< (min) ? (min) : ((x)>(max)?(max):(x)) )
#define WRAP_MAX(x,max,min) ( (x)>=(max) ? (min) : (x) )
#define WRAP_MIN(x,min,max) ( (x)<=(min) ? (max) : (x) )
#define VALUE_BETWEEN(x,min,max) (((x)>=(min)) && ((x) <= (max)))
/******************************************************************************
** MULTI_OF_2_POWER(x,a) whether x is multiple of a(a must be power of 2)
** CEILING_2_POWER(x,a) ceiling x to multiple of a(a must be power of 2)
** FLOOR_2_POWER(x,a) floor x to multiple of a(a must be power of 2)
** HIALIGN(x, a) align x to multiple of a
**
** Example:
** CEILING_2_POWER(5,4) = 8
** FLOOR_2_POWER(5,4) = 4
******************************************************************************/
#define MULTI_OF_2_POWER(x,a) (!((x) & ((a) - 1) ) )
#define CEILING_2_POWER(x,a) ( ((x) + ((a) - 1) ) & ( ~((a) - 1) ) )
#define FLOOR_2_POWER(x,a) ( (x) & (~((a) - 1) ) )
#define HIALIGN(x, a) ((a) * (((x) + (a) - 1) / (a)))
#define HICEILING(x, a) (((x)+(a)-1)/(a))
/******************************************************************************
** Get the span between two unsinged number, such as
** SPAN(XM_U32, 100, 200) is 200 - 100 = 100
** SPAN(XM_U32, 200, 100) is 0xFFFFFFFF - 200 + 100
** SPAN(XM_U64, 200, 100) is 0xFFFFFFFFFFFFFFFF - 200 + 100
******************************************************************************/
#define SPAN(type, begin, end)\
({ \
type b = (begin); \
type e = (end); \
(type)((b >= e) ? (b - e) : (b + ((~((type)0))-e))); \
})
/******************************************************************************
** ENDIAN32(x,y) little endian <---> big endian
** IS_LITTLE_END() whether the system is little end mode
******************************************************************************/
#define ENDIAN32( x ) \
( ( (x) << 24 ) | \
( ( (x) & 0x0000ff00 ) << 8 ) | \
( ( (x) & 0x00ff0000 ) >> 8 ) | \
( ( (x) >> 24 ) & 0x000000ff ) )
#if 0
__inline XM_BOOL IS_LITTLE_END(void)
{
union unEND_TEST_U
{
XM_CHAR cTest[4];
XM_U32 u32Test;
} unEndTest;
unEndTest.cTest[0] = 0x01;
unEndTest.cTest[1] = 0x02;
unEndTest.cTest[2] = 0x03;
unEndTest.cTest[3] = 0x04;
return (unEndTest.u32Test > 0x01020304) ? (XM_TRUE) : (XM_FALSE);
}
#endif
/******************************************************************************
** FRACTION32(de,nu) fraction: nu(minator) / de(nominator).
** NUMERATOR32(x) of x(x is fraction)
** DENOMINATOR32(x) Denominator of x(x is fraction)
** represent fraction in 32 bit. LSB 16 is numerator, MSB 16 is denominator
** It is integer if denominator is 0.
******************************************************************************/
#define FRACTION32(de,nu) ( ((de) << 16) | (nu) )
#define NUMERATOR32(x) ( (x) & 0xffff)
#define DENOMINATOR32(x) ( (x) >> 16 )
/******************************************************************************
** RGB(r,g,b) assemble the r,g,b to 24bit color
** RGB_R(c) get RED from 24bit color
** RGB_G(c) get GREEN from 24bit color
** RGB_B(c) get BLUE from 24bit color
******************************************************************************/
#define RGB(r,g,b) ((((r) & 0xff) << 16) | (((g) & 0xff) << 8) | ((b) & 0xff))
#define RGB_R(c) ( ((c) & 0xff0000) >> 16)
#define RGB_G(c) ( ((c) & 0xff00) >> 8)
#define RGB_B(c) ( (c) & 0xff)
/******************************************************************************
** YUV(y,u,v) assemble the y,u,v to 24bit color
** YUV_Y(c) get Y from 24bit color
** YUV_U(c) get U from 24bit color
** YUV_V(c) get V from 24bit color
******************************************************************************/
#define YUV(y,u,v) ((((y) & 0xff) << 16) | (((u) & 0xff) << 8) | ((v) & 0xff))
#define YUV_Y(c) ( ((c) & 0xff0000) >> 16)
#define YUV_U(c) ( ((c) & 0xff00) >> 8)
#define YUV_V(c) ( (c) & 0xff)
/******************************************************************************
** Rgb2Yc(r, g, b, *y, *u, *u) convert r,g,b to y,u,v
** Rgb2Yuv(rgb, *yuv) convert rgb to yuv
******************************************************************************/
#if 0
__inline XM_VOID Rgb2Yc(XM_U8 r, XM_U8 g, XM_U8 b, XM_U8 * py, XM_U8 * pcb, XM_U8 * pcr)
{
/* Y */
*py = (XM_U8)(((r*66+g*129+b*25) >> 8) + 16);
/* Cb */
*pcb = (XM_U8)((((b*112-r*38)-g*74) >> 8) + 128);
/* Cr */
*pcr = (XM_U8)((((r*112-g*94)-b*18) >> 8) + 128);
}
__inline XM_U32 Rgb2Yuv(XM_U32 u32Rgb)
{
XM_U8 y,u,v;
Rgb2Yc(RGB_R(u32Rgb), RGB_G(u32Rgb), RGB_B(u32Rgb), &y, &u, &v);
return YUV(y,u,v);
}
/******************************************************************************
** GetYCFromRGB(rgb, *y, *cbcr) convert rgb to yyyy, uvuv,
******************************************************************************/
__inline XM_VOID GetYCFromRGB(XM_U32 rgb, XM_U32 * pY, XM_U32 * pC)
{
XM_U8 y, cb, cr;
XM_U32 color_y, color_c, tmp;
Rgb2Yc(RGB_R(rgb), RGB_G(rgb), RGB_B(rgb), &y, &cb, &cr);
tmp = y & 0xFF;
color_y = (tmp<<24) + (tmp<<16) + (tmp<<8) + tmp;
tmp = cb & 0xFF;
color_c = (tmp<<24) + (tmp<<8);
tmp = cr & 0xFF;
color_c = color_c + (tmp<<16) + tmp;
*pY = color_y;
*pC = color_c;
}
#endif
/*******************************************************************************
** FpsControl Useing Sample:
** FPS_CTRL_S g_stFpsCtrl;
**
** Take 12 frame uniform in 25.
** InitFps(&g_stFpsCtrl, 25, 12);
**
** {
** if(FpsControl(&g_stFpsCtrl)) printf("Yes, this frmae should be token");
** }
**
*******************************************************************************/
typedef struct hiFPS_CTRL_S
{
XM_U32 u32Ffps; /* Full frame rate */
XM_U32 u32Tfps; /* Target frame rate */
XM_U32 u32FrmKey; /* update key frame */
} FPS_CTRL_S;
#if 0
__inline XM_VOID InitFps(FPS_CTRL_S *pFrmCtrl, XM_U32 u32FullFps,
XM_U32 u32TagFps)
{
pFrmCtrl->u32Ffps = u32FullFps;
pFrmCtrl->u32Tfps = u32TagFps;
pFrmCtrl->u32FrmKey = 0;
}
__inline XM_BOOL FpsControl(FPS_CTRL_S *pFrmCtrl)
{
XM_BOOL bReturn = XM_FALSE;
pFrmCtrl->u32FrmKey += pFrmCtrl->u32Tfps;
if (pFrmCtrl->u32FrmKey >= pFrmCtrl->u32Ffps)
{
pFrmCtrl->u32FrmKey -= pFrmCtrl->u32Ffps;
bReturn = XM_TRUE;
}
return bReturn;
}
#endif
#if 0
/*******************************************************************************
** GetSysTimeBySec
** GetSysTimeByUsec
*******************************************************************************/
#ifdef __KERNEL__
#include <linux/time.h>
#else
#include <sys/time.h>
#endif
__inline XM_U32 GetSysTimeBySec(void)
{
struct timeval stTime;
#ifdef __KERNEL__
do_gettimeofday(&stTime);
#else
gettimeofday(&stTime, NULL);
#endif
return stTime.tv_sec;
}
__inline XM_U64 GetSysTimeByUsec(void)
{
struct timeval stTime;
#ifdef __KERNEL__
do_gettimeofday(&stTime);
#else
gettimeofday(&stTime, NULL);
#endif
return (stTime.tv_sec * 1000000LLU) + stTime.tv_usec;
}
#endif
#endif /* __XM_MATH_H__ */

73
general/package/xiongmai-osdrv-xm530/files/include/isp/xm_print.h
View File

@ -1,73 +0,0 @@
#ifndef _XM_PRINT_H_
#define _XM_PRINT_H_
#include "xm530_tmp.h"
#if (defined SOC_SYSTEM) ||(defined SOC_ALIOS)
#include <stdio.h>
#endif
#define NONE "\033[m"
#define RED "\033[0;32;31m"
#define LIGHT_RED "\033[1;31m"
#define GREEN "\033[0;32;32m"
#define LIGHT_GREEN "\033[1;32m"
#define BLUE "\033[0;32;34m"
#define LIGHT_BLUE "\033[1;34m"
#define DARY_GRAY "\033[1;30m"
#define CYAN "\033[0;36m"
#define LIGHT_CYAN "\033[1;36m"
#define PURPLE "\033[0;35m"
#define LIGHT_PURPLE "\033[1;35m"
#define BROWN "\033[0;33m"
#define YELLOW "\033[1;33m"
#define LIGHT_GRAY "\033[0;37m"
#define WHITE "\033[1;37m"
#ifdef SOC_SYSTEM // have system lib
#if 1
#define ERR(fmt, args ... ) fprintf(stderr, RED "ERR: " fmt NONE, ## args)
#define DEBUG(fmt, args ... ) fprintf(stderr, GREEN "DEBUG: " fmt NONE,## args)
#define DBG(fmt, args ... ) printf(fmt,## args)
#define ENTER() printf("\n")
#else
#define DBG(fmt)
#define ENTER()
#define DEBUG(fmt)
#define ERR(fmt)
#endif
#elif (defined SOC_ALIOS)
#define ERR(fmt, args ... ) fprintf(stderr, RED "ERR: " fmt NONE, ## args)
#define DEBUG(fmt, args ... ) fprintf(stderr, GREEN "DEBUG: " fmt NONE,## args)
#define DBG(fmt, args ... ) fprintf(stderr, fmt,## args)
#define ENTER() fprintf(stderr, "\n\r")
#else
//#ifdef SOC_NONE // have no system lib
typedef enum
{
_DWORD = 8,
_WORD =4 ,
_BYTE =2 ,
}HEX_STR;
extern unsigned char putstr(unsigned char u8UartNum, char const *str);
extern int puthex_str(unsigned char uart_NO,HEX_STR style,void *Word);
#if 1
#define DBG(fmt) putstr(0, fmt)
#define ENTER() putstr(0, "\n\r")
#define DEBUG(fmt) putstr(0,"DBG:" fmt "\r")
#define ERR(fmt) putstr(0,"ERR:" fmt "\r")
#else
#define DBG(fmt)
#define ENTER()
#define DEBUG(fmt)
#define ERR(fmt)
#endif
#endif
#endif // _XM_PRINT_H_

63
general/package/xiongmai-osdrv-xm530/files/include/isp/xm_sns_ctrl.h
View File

@ -1,63 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm_sns_ctrl.h
Version : Initial Draft
Author : XM Isp software group
Created : 2015/7/6
Description : The common data type defination
Function List :
History :
1.Date : 2015/7/6
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef __XM_SNS_CTRL_H__
#define __XM_SNS_CTRL_H__
#include "xm_type.h"
#include "xm_comm_sns.h"
#include "xm_ae_comm.h"
#include "xm_i2c.h"
#include "xm_defines.h"
#include "mpi_phyvi.h"
#define HD720P_LINES (750)
#define HD1080P_LINES (1125)
#define CVBS1080_60P_LINES 572
#define CVBS1080_50P_LINES 840
#define CVBS720_60P_LINES 780
#define CVBS720_50P_LINES 750
void sensor_init();
void sensor_init_boot();
void sensor_prog(int *rom);
XM_S32 sensor_write_register(XM_U32 addr, XM_U32 data);
XM_S32 sensor_read_register(XM_U32 addr);
XM_S32 sensor_write_register_sch(XM_U8,XM_U32 addr, XM_U32 data);
XM_S32 sensor_read_register_sch(XM_U8,XM_U32 addr);
int sensor_write_register_bit(int addr, int data, int mask);
int sensor_register_callback(ISP_DEV IspDev);
int sensor_unregister_callback(ISP_DEV IspDev);
int sensor_get_chip(I2C_DATA_S *pstI2CData);
void sensor_set_chip(XM_S32 s32SnsChip);
int sensor_mode_set(XM_U8 u8Mode);
int sensor_mode_get();
int sensor_get_temp(XM_S16 *ps16Temp);
void sensor_set_dnMode(XM_U8 u8Mode);
int sensor_set_encoderinfo(XM_U8 *u8pDta);
void sensor_set_fps(XM_U8 channel , XM_U8 frame);
void sensor_set_isp_para(XM_U8 u8Mode);
void sensor_set_ioAbility(XM_U8 u8Level);
void sensor_set_VicutByNickname(XM_U32 u32Nickname);
XM_S32 sensor_set_reslotionType(PROFILE enResType);
void sensor_restart(XM_U8 u8Mode);
XM_S32 cmos_set_sns_attr(ISP_CMOS_SNS_ATTR_S *pstSnsAttr);
XM_S32 cmos_get_sns_attr(ISP_CMOS_SNS_ATTR_S *pstSnsAttr);
#endif /* __XM_SNS_CTRL_H__ */

28
general/package/xiongmai-osdrv-xm530/files/include/isp/xm_ssp.h
View File

@ -1,28 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm_ssp.h
Version : Initial Draft
Author : XM Isp software group
Created : 2015/6/27
Description : The common data type defination
Function List :
History :
1.Date : 2015/6/27
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef _XM_SSP_
#define _XM_SSP_
#define SSP_READ_ALT 0x1
#define SSP_WRITE_ALT 0X3
#endif

56
general/package/xiongmai-osdrv-xm530/files/include/isp/xm_type.h
View File

@ -1,56 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm_type.h
Version : Initial Draft
Author : XM Isp software group
Created : 2015/6/27
Description : The common data type defination
Function List :
History :
1.Date : 2015/6/27
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef __XM_TYPE_H__
#define __XM_TYPE_H__
/*----------------------------------------------*
* The common data type, will be used in the whole project.*
*----------------------------------------------*/
typedef unsigned char XM_U8;
typedef unsigned short XM_U16;
typedef unsigned int XM_U32;
typedef char XM_S8;
typedef short XM_S16;
typedef int XM_S32;
typedef unsigned long long XM_U64;
typedef long long XM_S64;
typedef char XM_CHAR;
#define XM_VOID void
/*----------------------------------------------*
* const defination *
*----------------------------------------------*/
typedef enum {
XM_FALSE = 0,
XM_TRUE = 1,
} XM_BOOL;
#ifndef NULL
#define NULL 0L
#endif
#define XM_NULL 0L
#define XM_SUCCESS 0
#define XM_FAILURE (-1)
#endif /* __XM_TYPE_H__ */

59
general/package/xiongmai-osdrv-xm530/files/include/mpi/interrupt.h
View File

@ -1,59 +0,0 @@
#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__
/*
* COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
*
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
void aos_hw_interrupt_clear(int vector);
/*
* Interrupt handler definition
*/
#define MAX_HANDLERS IRQ_XM510_END
#define INTERRUPT_NAME_MAX 16
typedef void (*rt_isr_handler_t)(int vector, void *param);
struct rt_irq_desc
{
rt_isr_handler_t handler;
void *param;
char name[INTERRUPT_NAME_MAX];
uint32_t counter;
};
/*
* Interrupt interfaces
*/
#if 0
void rt_hw_interrupt_init(void);
void rt_hw_interrupt_mask(int vector);
void rt_hw_interrupt_umask(int vector);
rt_isr_handler_t rt_hw_interrupt_install(int vector,
rt_isr_handler_t handler,
void *param,
char *name);
#else
typedef void (*irq_hdlr_t)(int irq, void *param);
void os_hw_interrupt_enable(int irq);
irq_hdlr_t os_hw_interrupt_create(int irq, irq_hdlr_t irq_handler,void *param, char *name);
#endif
#endif /* end of include guard: __INTERRUPT_H__ */

52
general/package/xiongmai-osdrv-xm530/files/include/mpi/mpi_ai.h
View File

@ -1,52 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2025, XM Tech. Co., Ltd.
******************************************************************************
File Name : mpi_ai.h
Version : Initial Draft
Author : XM multimedia software group
Created : 2015/9/17
Description :
******************************************************************************/
#ifndef _MPI_AI_H__
#define _MPI_AI_H__
#include "xm_type.h"
#include "xm_common.h"
#include "xm_comm_aio.h"
#ifdef __cplusplus
#if __cplusplus
extern "C"
{
#endif
#endif /* __cplusplus */
#define FRAME_SIZE 160
XM_S32 XM_MPI_AI_SetVqeAttr(AUDIO_DEV AiDevId, AI_CHN AiChn, AUDIO_DEV AoDevId, AO_CHN AoChn, AI_VQE_CONFIG_S *pstVqeConfig);
XM_S32 XM_MPI_AI_GetVqeAttr(AUDIO_DEV AiDevId, AI_CHN AiChn, AI_VQE_CONFIG_S *pstVqeConfig);
XM_S32 XM_MPI_AI_SetVolume(AUDIO_DEV AudioDevId, XM_S32 s32VolumeDb);
XM_S32 XM_MPI_AI_GetVolume(AUDIO_DEV AudioDevId, XM_S32 *ps32VolumeDb);
XM_S32 XM_MPI_AUDIO_Init(void);
XM_S32 XM_MPI_AI_SetPubAttr(AUDIO_DEV AudioDevId, const AIO_ATTR_S *pstAttr);
XM_S32 XM_MPI_AI_GetPubAttr(AUDIO_DEV AudioDevId, AIO_ATTR_S *pstAttr);
XM_S32 XM_MPI_AI_Enable(AUDIO_DEV AudioDevId);
XM_S32 XM_MPI_AI_Disable(AUDIO_DEV AudioDevId);
XM_S32 XM_MPI_AI_GetFrame(AUDIO_DEV AudioDevId, AI_CHN AiChn,
AUDIO_FRAME_S *pstFrm, AEC_FRAME_S *pstAecFrm, XM_BOOL bBlock);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif

72
general/package/xiongmai-osdrv-xm530/files/include/mpi/mpi_sys.h
View File

@ -1,72 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2025, XM Tech. Co., Ltd.
******************************************************************************
File Name : mpi_sys.h
Version : Initial Draft
Author : XM multimedia software group
Created : 2015/9/17
Description :
******************************************************************************/
#ifndef __MPI_SYS_H__
#define __MPI_SYS_H__
/******************************************/
#ifdef __cplusplus
#if __cplusplus
extern "C"
{
#endif
#endif /* __cplusplus */
#include "xm_common.h"
#include "xm_comm_sys.h"
XM_S32 XM_MPI_SYS_Init(XM_VOID);
/*
** u64Base is the global PTS of the system.
** ADVICE:
** 1. Bester to call XM_MPI_SYS_GetCurPts on the host board to get the u64Base.
** 2. When the linux start up, call XM_MPI_SYS_InitPtsBase to set the init pts.
** 3. When media bussines is running, synchronize the PTS one time per minute.
** And should call XM_MPI_SYS_SyncPts.
*/
/* alloc mmz memory in user context */
XM_S32 XM_MPI_SYS_MmzAlloc(XM_U32 *pu32PhyAddr, XM_VOID **ppVirtAddr,
const XM_CHAR *strMmb, const XM_CHAR *strZone, XM_U32 u32Len);
XM_S32 XM_MPI_SYS_MmzAlloc_Cached(XM_U32 *pu32PhyAddr, void **ppVitAddr,
const XM_CHAR *pstrMmb, const XM_CHAR *pstrZone, XM_U32 u32Len);
/* free mmz memory in user context */
XM_S32 XM_MPI_SYS_MmzFree(XM_U32 u32PhyAddr, XM_VOID *pVirtAddr);
XM_S32 XM_MPI_SYS_MmzFlushCache(XM_U32 u32PhyAddr, XM_VOID *pVirAddr,
XM_U32 u32Size);
/* fulsh cache */
XM_S32 XM_MPI_SYS_MmzFlushCache(XM_U32 u32PhyAddr, XM_VOID *pVirAddr,
XM_U32 u32Size);
/*
** Call the mmap function to map physical address to virtual address
** The system function mmap is too complicated, so we packge it.
*/
XM_VOID * XM_MPI_SYS_Mmap(XM_U32 u32PhyAddr, XM_U32 u32Size);
XM_S32 XM_MPI_SYS_Munmap(XM_VOID* pVirAddr, XM_U32 u32Size);
XM_S32 XM_MPI_SYS_MmzReset(void);
XM_S32 XM_MPI_SYS_Bind(MPP_CHN_S *pstSrcChn, MPP_CHN_S *pstDestChn);
XM_S32 XM_MPI_SYS_UnBind(MPP_CHN_S *pstSrcChn, MPP_CHN_S *pstDestChn);
/******************************************/
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
/******************************************/
#endif /*__MPI_SYS_H__ */

51
general/package/xiongmai-osdrv-xm530/files/include/mpi/mpi_vi.h
View File

@ -1,51 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2025, XM Tech. Co., Ltd.
******************************************************************************
File Name : mpi_vi.h
Version : Initial Draft
Author : XM multimedia software group
Created : 2015/9/17
Description :
******************************************************************************/
#ifndef __MPI_VI_H__
#define __MPI_VI_H__
#ifdef __cplusplus
#if __cplusplus
extern "C"
{
#endif
#endif /* __cplusplus */
#include "xm_comm_vi.h"
XM_S32 XM_MPI_VI_Init(void);
XM_S32 XM_MPI_VI_SetChnAttr(VI_CHN ViChn, const VI_CHN_ATTR_S *pstAttr);
XM_S32 XM_MPI_VI_GetChnAttr(VI_CHN ViChn, VI_CHN_ATTR_S *pstAttr);
XM_S32 XM_MPI_VI_EnableChn(VI_CHN ViChn);
XM_S32 XM_MPI_VI_DisableChn(VI_CHN ViChn);
XM_S32 XM_MPI_VI_GetFrame(VI_CHN ViChn, VIDEO_FRAME_INFO_S *pstFrameInfo);
XM_S32 XM_MPI_VI_ReleaseFrame(VI_CHN ViChn, VIDEO_FRAME_INFO_S *pstFrameInfo);
XM_S32 XM_MPI_VI_SetExtChnAttr(VI_CHN ViChn, const VI_EXT_CHN_ATTR_S *pstExtChnAttr);
XM_S32 XM_MPI_VI_GetExtChnAttr(VI_CHN ViChn, VI_EXT_CHN_ATTR_S *pstExtChnAttr);
XM_S32 XM_MPI_VI_SetFrmRate(VI_CHN ViChn, XM_U32 srcFrmRate,XM_U32 dstFrmRate);
XM_S32 XM_MPI_VI_Bind(VI_CHN ViChn, MPP_CHN_S *pstDestChn);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /*__MPI_VI_H__ */

99
general/package/xiongmai-osdrv-xm530/files/include/mpi/mpi_vo.h
View File

@ -1,99 +0,0 @@
#ifndef __MPI_VO_H__
#define __MPI_VO_H__
#include "xm_comm_vo.h"
#ifdef __cplusplus
#if __cplusplus
extern "C"
{
#endif
#endif /* __cplusplus */
/* Device Settings */
XM_S32 XM_MPI_VO_Init(void);
XM_S32 XM_MPI_VO_SetPubAttr(VO_DEV VoDev, const VO_PUB_ATTR_S *pstPubAttr);
XM_S32 XM_MPI_VO_GetPubAttr(VO_DEV VoDev, VO_PUB_ATTR_S *pstPubAttr);
XM_S32 XM_MPI_VO_Enable (VO_DEV VoDev);
XM_S32 XM_MPI_VO_Disable(VO_DEV VoDev);
/*XM_S32 XM_MPI_VO_CloseFd(XM_VOID);*/
/* General Operation of Channel */
XM_S32 XM_MPI_VO_EnableChn (VO_LAYER VoLayer, VO_CHN VoChn);
XM_S32 XM_MPI_VO_DisableChn(VO_LAYER VoLayer, VO_CHN VoChn);
XM_S32 XM_MPI_VO_SetChnAttr(VO_LAYER VoLayer, VO_CHN VoChn, const VO_CHN_ATTR_S *pstChnAttr);
XM_S32 XM_MPI_VO_GetChnAttr(VO_LAYER VoLayer, VO_CHN VoChn, VO_CHN_ATTR_S *pstChnAttr);
XM_S32 XM_MPI_VO_GetChnFrame(VO_LAYER VoLayer, VO_CHN VoChn, VIDEO_FRAME_INFO_S *pstFrame, XM_S32 s32MilliSec);
XM_S32 XM_MPI_VO_ReleaseChnFrame(VO_LAYER VoLayer, VO_CHN VoChn, const VIDEO_FRAME_INFO_S *pstFrame);
/*XM_S32 XM_MPI_VO_PauseChn (VO_LAYER VoLayer, VO_CHN VoChn);*/
/*XM_S32 XM_MPI_VO_ResumeChn(VO_LAYER VoLayer, VO_CHN VoChn);*/
/*XM_S32 XM_MPI_VO_StepChn(VO_LAYER VoLayer, VO_CHN VoChn);*/
/*XM_S32 XM_MPI_VO_RefreshChn( VO_LAYER VoLayer, VO_CHN VoChn);*/
/*XM_S32 XM_MPI_VO_ShowChn(VO_LAYER VoLayer, VO_CHN VoChn);*/
/*XM_S32 XM_MPI_VO_HideChn(VO_LAYER VoLayer, VO_CHN VoChn);*/
/*XM_S32 XM_MPI_VO_SendFrame(VO_LAYER VoLayer, VO_CHN VoChn, VIDEO_FRAME_INFO_S *pstVFrame, XM_S32 s32MilliSec);*/
/*XM_S32 XM_MPI_VO_ClearChnBuffer(VO_LAYER VoLayer, VO_CHN VoChn, XM_BOOL bClrAll);*/
/*XM_S32 XM_MPI_VO_GetChnRegionLuma(VO_LAYER VoLayer, VO_CHN VoChn, VO_REGION_INFO_S *pstRegionInfo,*/
/*XM_U32 *pu32LumaData, XM_S32 s32MilliSec);*/
/* Cascade setting */
/*XM_S32 XM_MPI_VO_SetCascadeAttr(const VO_CAS_ATTR_S *pstCasAttr);*/
/*XM_S32 XM_MPI_VO_GetCascadeAttr(VO_CAS_ATTR_S *pstCasAttr);*/
/*XM_S32 XM_MPI_VO_EnableCascadeDev (VO_DEV VoCasDev);*/
/*XM_S32 XM_MPI_VO_DisableCascadeDev(VO_DEV VoCasDev);*/
/*XM_S32 XM_MPI_VO_SetCascadePattern(VO_DEV VoCasDev, XM_U32 u32Pattern);*/
/*XM_S32 XM_MPI_VO_GetCascadePattern(VO_DEV VoCasDev, XM_U32 *pu32Pattern);*/
/*XM_S32 XM_MPI_VO_CascadePosBindChn(XM_U32 u32Pos, VO_DEV VoCasDev, VO_CHN VoChn);*/
/*XM_S32 XM_MPI_VO_CascadePosUnBindChn(XM_U32 u32Pos, VO_DEV VoCasDev, VO_CHN VoChn);*/
/*XM_S32 XM_MPI_VO_EnableCascade (XM_VOID);*/
/*XM_S32 XM_MPI_VO_DisableCascade(XM_VOID);*/
/* VGA setting */
/*XM_S32 XM_MPI_VO_GetVgaParam(VO_DEV VoDev, VO_VGA_PARAM_S *pstVgaParam);*/
/*XM_S32 XM_MPI_VO_SetVgaParam(VO_DEV VoDev, VO_VGA_PARAM_S *pstVgaParam);*/
/*XM_S32 XM_MPI_VO_SetDevFrameRate(VO_DEV VoDev, XM_U32 u32FrameRate);*/
/*XM_S32 XM_MPI_VO_GetDevFrameRate(VO_DEV VoDev, XM_U32 *pu32FrameRate);*/
/*XM_S32 XM_MPI_VO_EnableRecvFrameRateMatch (VO_LAYER VoLayer, VO_CHN VoChn);*/
/*XM_S32 XM_MPI_VO_DisableRecvFrameRateMatch (VO_LAYER VoLayer, VO_CHN VoChn);*/
/* HDMI setting */
/*XM_S32 XM_MPI_VO_GetHdmiParam(VO_DEV VoDev, VO_HDMI_PARAM_S *pstHdmiParam);*/
/*XM_S32 XM_MPI_VO_SetHdmiParam(VO_DEV VoDev, VO_HDMI_PARAM_S *pstHdmiParam);*/
/*XM_S32 XM_MPI_VO_SetVtth(VO_DEV VoDev, XM_U32 u32Vtth);*/
/*XM_S32 XM_MPI_VO_GetVtth(VO_DEV VoDev, XM_U32* pu32Vtth);*/
XM_S32 XM_MPI_VO_SetImageLayerAttr(VO_LAYER VoLayer, const VO_IMAGE_LAYER_ATTR_S *pstLayerAttr);
XM_S32 XM_MPI_VO_GetImageLayerAttr(VO_LAYER VoLayer, const VO_IMAGE_LAYER_ATTR_S *pstLayerAttr);
XM_S32 XM_MPI_VO_EnableImageLayer(VO_LAYER VoLayer);
XM_S32 XM_MPI_VO_DisableImageLayer(VO_LAYER VoLayer);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /*__MPI_VO_H__ */

388
general/package/xiongmai-osdrv-xm530/files/include/mpi/xm_comm_aio.h
View File

@ -1,388 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2025, XM Tech. Co., Ltd.
******************************************************************************
File Name : xm_comm_aio.h
Version : Initial Draft
Author : XM multimedia software group
Created : 2015/9/17
Description :
******************************************************************************/
#ifndef __XM_COMM_AIO_H__
#define __XM_COMM_AIO_H__
#include "xm_common.h"
#include "xm_errno.h"
#ifdef __cplusplus
#if __cplusplus
extern "C"{
#endif
#endif /* End of #ifdef __cplusplus */
#define MAX_AUDIO_FRAME_NUM 50 /*max count of audio frame in Buffer */
#define MAX_AUDIO_POINT_BYTES 4 /*max bytes of one sample point(now 32bit max)*/
#define MAX_VOICE_POINT_NUM 480 /*max sample per frame for voice encode */
#define MAX_AUDIO_POINT_NUM 2048 /*max sample per frame for all encoder(aacplus:2048)*/
#define MAX_AO_POINT_NUM 4096 /*31/21 AO support 4096 framelen*/
#define MIN_AUDIO_POINT_NUM 80 /*min sample per frame*/
/*max length of audio frame by bytes, one frame contain many sample point */
#define MAX_AUDIO_FRAME_LEN (MAX_AUDIO_POINT_BYTES*MAX_AO_POINT_NUM)
/*max length of audio stream by bytes */
#define MAX_AUDIO_STREAM_LEN MAX_AUDIO_FRAME_LEN
#define MAX_AI_USRFRM_DEPTH 30 /*max depth of user frame buf */
typedef enum xmAUDIO_SAMPLE_RATE_E
{
AUDIO_SAMPLE_RATE_8000 = 8000, /* 8K samplerate*/
AUDIO_SAMPLE_RATE_12000 = 12000, /* 12K samplerate*/
AUDIO_SAMPLE_RATE_11025 = 11025, /* 11.025K samplerate*/
AUDIO_SAMPLE_RATE_16000 = 16000, /* 16K samplerate*/
AUDIO_SAMPLE_RATE_22050 = 22050, /* 22.050K samplerate*/
AUDIO_SAMPLE_RATE_24000 = 24000, /* 24K samplerate*/
AUDIO_SAMPLE_RATE_32000 = 32000, /* 32K samplerate*/
AUDIO_SAMPLE_RATE_44100 = 44100, /* 44.1K samplerate*/
AUDIO_SAMPLE_RATE_48000 = 48000, /* 48K samplerate*/
AUDIO_SAMPLE_RATE_BUTT,
} AUDIO_SAMPLE_RATE_E;
typedef enum xmAUDIO_BIT_WIDTH_E
{
AUDIO_BIT_WIDTH_8 = 0, /* 8bit width */
AUDIO_BIT_WIDTH_16 = 1, /* 16bit width*/
AUDIO_BIT_WIDTH_32 = 2, /* 32bit width*/
AUDIO_BIT_WIDTH_BUTT,
} AUDIO_BIT_WIDTH_E;
typedef enum xmAIO_MODE_E
{
AIO_MODE_I2S_MASTER = 0, /* SIO I2S master mode */
AIO_MODE_I2S_SLAVE, /* SIO I2S slave mode */
AIO_MODE_PCM_SLAVE_STD, /* SIO PCM slave standard mode */
AIO_MODE_PCM_SLAVE_NSTD, /* SIO PCM slave non-standard mode */
AIO_MODE_PCM_MASTER_STD, /* SIO PCM master standard mode */
AIO_MODE_PCM_MASTER_NSTD, /* SIO PCM master non-standard mode */
AIO_MODE_BUTT
} AIO_MODE_E;
typedef enum xmAIO_SOUND_MODE_E
{
AUDIO_SOUND_MODE_MONO =0,/*mono*/
AUDIO_SOUND_MODE_STEREO =1,/*stereo*/
AUDIO_SOUND_MODE_BUTT
} AUDIO_SOUND_MODE_E;
/*
An example of the packing scheme for G726-32 codewords is as shown, and bit A3 is the least significant bit of the first codeword:
RTP G726-32:
0 1
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-
|B B B B|A A A A|D D D D|C C C C| ...
|0 1 2 3|0 1 2 3|0 1 2 3|0 1 2 3|
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-
MEDIA G726-32:
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-
|A A A A|B B B B|C C C C|D D D D| ...
|3 2 1 0|3 2 1 0|3 2 1 0|3 2 1 0|
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-
*/
typedef enum xmG726_BPS_E
{
G726_16K = 0, /* G726 16kbps, see RFC3551.txt 4.5.4 G726-16 */
G726_24K, /* G726 24kbps, see RFC3551.txt 4.5.4 G726-24 */
G726_32K, /* G726 32kbps, see RFC3551.txt 4.5.4 G726-32 */
G726_40K, /* G726 40kbps, see RFC3551.txt 4.5.4 G726-40 */
MEDIA_G726_16K, /* G726 16kbps for ASF ... */
MEDIA_G726_24K, /* G726 24kbps for ASF ... */
MEDIA_G726_32K, /* G726 32kbps for ASF ... */
MEDIA_G726_40K, /* G726 40kbps for ASF ... */
G726_BUTT,
} G726_BPS_E;
typedef enum xmADPCM_TYPE_E
{
/* see DVI4 diiffers in three respects from the IMA ADPCM at RFC3551.txt 4.5.1 DVI4 */
ADPCM_TYPE_DVI4 = 0, /* 32kbps ADPCM(DVI4) for RTP */
ADPCM_TYPE_IMA, /* 32kbps ADPCM(IMA),NOTICE:point num must be 161/241/321/481 */
ADPCM_TYPE_ORG_DVI4,
ADPCM_TYPE_BUTT,
} ADPCM_TYPE_E;
#define AI_EXPAND 0x01
typedef struct xmAIO_ATTR_S
{
AUDIO_SAMPLE_RATE_E enSamplerate; /* sample rate*/
AUDIO_BIT_WIDTH_E enBitwidth; /* bitwidth*/
AIO_MODE_E enWorkmode; /* master or slave mode*/
AUDIO_SOUND_MODE_E enSoundmode; /* momo or steror*/
XM_U32 u32EXFlag; /* expand 8bit to 16bit,use AI_EXPAND(only valid for AI 8bit) */
XM_U32 u32FrmNum; /* frame num in buf[2,MAX_AUDIO_FRAME_NUM]*/
XM_U32 u32PtNumPerFrm; /* point num per frame (80/160/240/320/480/1024/2048)
(ADPCM IMA should add 1 point, AMR only support 160)*/
XM_U32 u32ChnCnt; /* channle number on FS, valid value:2/4/8/16 */
XM_U32 u32ClkSel; /* clock select, meaning is diffrent when master and slave mode,
if sio slave mode:
0: AD and DA clock of codec is separate
1: AD and DA clock of codec is inseparate
else sio master mode:
0:ACKOUT clock is from sio 0
1:ACKOUT clock is from sio 1/2
*/
} AIO_ATTR_S;
typedef struct xmAI_CHN_PARAM_S
{
XM_U32 u32UsrFrmDepth;
XM_S32 s32Rev;
} AI_CHN_PARAM_S;
typedef struct xmAUDIO_FRAME_S
{
AUDIO_BIT_WIDTH_E enBitwidth; /*audio frame bitwidth*/
AUDIO_SOUND_MODE_E enSoundmode; /*audio frame momo or stereo mode*/
XM_VOID *pVirAddr[2];
XM_U32 u32PhyAddr[2];
XM_U64 u64TimeStamp; /*audio frame timestamp*/
XM_U32 u32Seq; /*audio frame seq*/
XM_U32 u32Len; /*data lenth per channel in frame*/
XM_U32 u32PoolId[2];
} AUDIO_FRAME_S;
typedef struct xmAEC_FRAME_S
{
AUDIO_FRAME_S stRefFrame; /* AEC reference audio frame */
XM_BOOL bValid; /* whether frame is valid */
XM_BOOL bSysBind; /* whether is sysbind */
} AEC_FRAME_S;
typedef struct xmAUDIO_FRAME_COMBINE_S
{
AUDIO_FRAME_S stFrm; /* audio frame */
AEC_FRAME_S stRefFrm; /* AEC reference audio frame */
} AUDIO_FRAME_COMBINE_S;
typedef struct xmAUDIO_FRAME_INFO_S
{
AUDIO_FRAME_S *pstFrame;/*frame ptr*/
XM_U32 u32Id; /*frame id*/
} AUDIO_FRAME_INFO_S;
typedef struct xmAUDIO_STREAM_S
{
XM_U8 *pStream; /* the virtual address of stream */
XM_U32 u32PhyAddr; /* the physics address of stream */
XM_U32 u32Len; /* stream lenth, by bytes */
XM_U64 u64TimeStamp; /* frame time stamp*/
XM_U32 u32Seq; /* frame seq,if stream is not a valid frame,u32Seq is 0*/
} AUDIO_STREAM_S;
typedef enum xmAUDIO_RESAMPLE_TYPE_E
{
AUDIO_RESAMPLE_1X2 = 0x1,
AUDIO_RESAMPLE_2X1 = 0x2,
AUDIO_RESAMPLE_1X4 = 0x3,
AUDIO_RESAMPLE_4X1 = 0x4,
AUDIO_RESAMPLE_1X6 = 0x5,
AUDIO_RESAMPLE_6X1 = 0x6,
AUDIO_RESAMPLE_BUTT
} AUDIO_RESAMPLE_TYPE_E;
typedef struct xmAUDIO_RESAMPLE_ATTR_S
{
XM_U32 u32InPointNum; /* input point number of frame */
AUDIO_SAMPLE_RATE_E enInSampleRate; /* input sample rate */
AUDIO_RESAMPLE_TYPE_E enReSampleType; /* resample type */
} AUDIO_RESAMPLE_ATTR_S;
typedef struct xmAUDIO_RESAMPLE_ATTR_EX_S
{
XM_U32 u32InPointNum; /* input point number of frame */
AUDIO_SAMPLE_RATE_E enInSampleRate; /* input sample rate */
AUDIO_SAMPLE_RATE_E enOutSampleRate; /* output sample rate */
} AUDIO_RESAMPLE_ATTR_EX_S;
typedef struct xmAO_CHN_STATE_S
{
XM_U32 u32ChnTotalNum; /* total number of channel buffer */
XM_U32 u32ChnFreeNum; /* free number of channel buffer */
XM_U32 u32ChnBusyNum; /* busy number of channel buffer */
} AO_CHN_STATE_S;
typedef struct xmAIO_RESMP_INFO_S
{
XM_BOOL bReSmpEnable; /* resample enable or disable */
XM_BOOL bReSmpEnableEx; /*advanced resample enable or disable */
AUDIO_RESAMPLE_ATTR_S stResmpAttr;
AUDIO_RESAMPLE_ATTR_EX_S stResmpAttrEx;
} AIO_RESMP_INFO_S;
typedef struct xmAI_ANR_INFO_S
{
XM_BOOL bAnrEnable; /* noise reduce enable or disable */
} AI_ANR_INFO_S;
typedef enum xmAUDIO_AEC_MODE_E
{
AUDIO_AEC_MODE_RECEIVER = 0,
AUDIO_AEC_MODE_SPEAKER = 1,
AUDIO_AEC_MODE_HEADPHONE = 2,
AUDIO_AEC_MODE_BUTT
} AUDIO_AEC_MODE_E;
/**Defines the configure parameters of ALC.*/
typedef struct xmAI_ALC_CONFIG_S
{
XM_S32 s32MaxLev; /*s32MaxLev：[-23dBm0, -4dBm0]。default: -4dBm0*/
XM_S32 s32MinLev; /*s32MinLev： [-23dBm0, -4dBm0]。default: -16dBm0*/
XM_U32 u32MaxGain; /*u32MaxGain：[3dB,12dB]。default: 12dB*/
} AI_ALC_CONFIG_S;
/**Defines the configure parameters of AEC.*/
typedef struct xmAI_AEC_CONFIG_S
{
AUDIO_AEC_MODE_E enAecMode; /* AEC mode, default is speaker, 0:receiver 1:speaker 2:headphone */
XM_S32 s32Reserved;
} AI_AEC_CONFIG_S;
/**Defines the configure parameters of ANR.*/
typedef struct xmAI_ANR_CONFIG_S
{
XM_S32 s32Reserved;
} AI_ANR_CONFIG_S;
/**Defines the configure parameters of VQE.*/
typedef struct xmAI_VQE_CONFIG_S
{
XM_S32 bAecOpen;
XM_S32 bAnrOpen;
XM_S32 bAgcOpen;
XM_S32 s32SampleRate; /* Sample Rate：8KHz/11.025K/12K/16KHz。default: 8KHz*/
XM_S32 s32FrameSample; /* VQE frame length：
sample rate 8KHz: VQE frame length: 80/160/240/320/400/480， default: 160;
sample rate 11.025K/12K/16KHz: VQE frame length: 160/320/480/960， default: 160 */
AI_AEC_CONFIG_S stAecCfg;
AI_ANR_CONFIG_S stAnrCfg;
AI_ALC_CONFIG_S stAlcCfg;
} AI_VQE_CONFIG_S;
typedef struct xmAI_VQE_INFO_S
{
AI_VQE_CONFIG_S stVqeConfig; /*vqe config*/
XM_BOOL bVqeEnable; /* vqe enable or disable */
} AI_VQE_INFO_S;
/**Defines the configure parameters of AI saving file.*/
typedef struct xmAUDIO_SAVE_FILE_INFO_S
{
XM_BOOL bCfg;
XM_CHAR aFilePath[256];
//AI_SAVE_FILE_COMMOND_E eSaveFileCommond;
XM_U32 u32FileSize; /*in KB*/
} AUDIO_SAVE_FILE_INFO_S;
typedef enum xmAUDIO_FADE_RATE_E
{
AUDIO_FADE_RATE_1 = 0,
AUDIO_FADE_RATE_2 = 1,
AUDIO_FADE_RATE_4 = 2,
AUDIO_FADE_RATE_8 = 3,
AUDIO_FADE_RATE_16 = 4,
AUDIO_FADE_RATE_32 = 5,
AUDIO_FADE_RATE_64 = 6,
AUDIO_FADE_RATE_128 = 7,
AUDIO_FADE_RATE_BUTT
} AUDIO_FADE_RATE_E;
typedef struct xmAUDIO_FADE_S
{
XM_BOOL bFade;
AUDIO_FADE_RATE_E enFadeInRate;
AUDIO_FADE_RATE_E enFadeOutRate;
} AUDIO_FADE_S;
#define XM_TRACE_AI(level, fmt...)
#define XM_TRACE_AO(level, fmt...)
/* invlalid device ID */
#define XM_ERR_AI_INVALID_DEVID XM_DEF_ERR(XM_ID_AI, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_DEVID)
/* invlalid channel ID */
#define XM_ERR_AI_INVALID_CHNID XM_DEF_ERR(XM_ID_AI, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_CHNID)
/* at lease one parameter is illagal ,eg, an illegal enumeration value */
#define XM_ERR_AI_ILLEGAL_PARAM XM_DEF_ERR(XM_ID_AI, EN_ERR_LEVEL_ERROR, EN_ERR_ILLEGAL_PARAM)
/* using a NULL point */
#define XM_ERR_AI_NULL_PTR XM_DEF_ERR(XM_ID_AI, EN_ERR_LEVEL_ERROR, EN_ERR_NULL_PTR)
/* try to enable or initialize system,device or channel, before configing attribute */
#define XM_ERR_AI_NOT_CONFIG XM_DEF_ERR(XM_ID_AI, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_CONFIG)
/* operation is not supported by NOW */
#define XM_ERR_AI_NOT_SUPPORT XM_DEF_ERR(XM_ID_AI, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_SUPPORT)
/* operation is not permitted ,eg, try to change stati attribute */
#define XM_ERR_AI_NOT_PERM XM_DEF_ERR(XM_ID_AI, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_PERM)
/* the devide is not enabled */
#define XM_ERR_AI_NOT_ENABLED XM_DEF_ERR(XM_ID_AI, EN_ERR_LEVEL_ERROR, EN_ERR_UNEXIST)
/* failure caused by malloc memory */
#define XM_ERR_AI_NOMEM XM_DEF_ERR(XM_ID_AI, EN_ERR_LEVEL_ERROR, EN_ERR_NOMEM)
/* failure caused by malloc buffer */
#define XM_ERR_AI_NOBUF XM_DEF_ERR(XM_ID_AI, EN_ERR_LEVEL_ERROR, EN_ERR_NOBUF)
/* no data in buffer */
#define XM_ERR_AI_BUF_EMPTY XM_DEF_ERR(XM_ID_AI, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_EMPTY)
/* no buffer for new data */
#define XM_ERR_AI_BUF_FULL XM_DEF_ERR(XM_ID_AI, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_FULL)
/* system is not ready,had not initialed or loaded*/
#define XM_ERR_AI_SYS_NOTREADY XM_DEF_ERR(XM_ID_AI, EN_ERR_LEVEL_ERROR, EN_ERR_SYS_NOTREADY)
#define XM_ERR_AI_BUSY XM_DEF_ERR(XM_ID_AI, EN_ERR_LEVEL_ERROR, EN_ERR_BUSY)
/* invlalid device ID */
#define XM_ERR_AO_INVALID_DEVID XM_DEF_ERR(XM_ID_AO, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_DEVID)
/* invlalid channel ID */
#define XM_ERR_AO_INVALID_CHNID XM_DEF_ERR(XM_ID_AO, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_CHNID)
/* at lease one parameter is illagal ,eg, an illegal enumeration value */
#define XM_ERR_AO_ILLEGAL_PARAM XM_DEF_ERR(XM_ID_AO, EN_ERR_LEVEL_ERROR, EN_ERR_ILLEGAL_PARAM)
/* using a NULL point */
#define XM_ERR_AO_NULL_PTR XM_DEF_ERR(XM_ID_AO, EN_ERR_LEVEL_ERROR, EN_ERR_NULL_PTR)
/* try to enable or initialize system,device or channel, before configing attribute */
#define XM_ERR_AO_NOT_CONFIG XM_DEF_ERR(XM_ID_AO, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_CONFIG)
/* operation is not supported by NOW */
#define XM_ERR_AO_NOT_SUPPORT XM_DEF_ERR(XM_ID_AO, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_SUPPORT)
/* operation is not permitted ,eg, try to change stati attribute */
#define XM_ERR_AO_NOT_PERM XM_DEF_ERR(XM_ID_AO, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_PERM)
/* the devide is not enabled */
#define XM_ERR_AO_NOT_ENABLED XM_DEF_ERR(XM_ID_AO, EN_ERR_LEVEL_ERROR, EN_ERR_UNEXIST)
/* failure caused by malloc memory */
#define XM_ERR_AO_NOMEM XM_DEF_ERR(XM_ID_AO, EN_ERR_LEVEL_ERROR, EN_ERR_NOMEM)
/* failure caused by malloc buffer */
#define XM_ERR_AO_NOBUF XM_DEF_ERR(XM_ID_AO, EN_ERR_LEVEL_ERROR, EN_ERR_NOBUF)
/* no data in buffer */
#define XM_ERR_AO_BUF_EMPTY XM_DEF_ERR(XM_ID_AO, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_EMPTY)
/* no buffer for new data */
#define XM_ERR_AO_BUF_FULL XM_DEF_ERR(XM_ID_AO, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_FULL)
/* system is not ready,had not initialed or loaded*/
#define XM_ERR_AO_SYS_NOTREADY XM_DEF_ERR(XM_ID_AO, EN_ERR_LEVEL_ERROR, EN_ERR_SYS_NOTREADY)
#define XM_ERR_AO_BUSY XM_DEF_ERR(XM_ID_AO, EN_ERR_LEVEL_ERROR, EN_ERR_BUSY)
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* End of #ifndef __XM_COMM_AI_H__ */

54
general/package/xiongmai-osdrv-xm530/files/include/mpi/xm_comm_sys.h
View File

@ -1,54 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2025, XM Tech. Co., Ltd.
******************************************************************************
File Name : xm_comm_sys.h
Version : Initial Draft
Author : XM multimedia software group
Created : 2015/9/17
Description :
******************************************************************************/
#ifndef __XM_COMM_SYS_H__
#define __XM_COMM_SYS_H__
#include "xm_type.h"
#include "xm_errno.h"
#include "xm_debug.h"
#ifdef __cplusplus
#if __cplusplus
extern "C"{
#endif
#endif /* End of #ifdef __cplusplus */
#define XM_TRACE_SYS(level, fmt...) XM_TRACE(level, XM_ID_SYS,##fmt)
typedef struct xmMPP_SYS_CONF_S
{
/* stride of picture buffer must be aligned with this value.
* you can choose a value from 1 to 1024, and it must be multiple of 16.
*/
XM_U32 u32AlignWidth;
}MPP_SYS_CONF_S;
#define XM_ERR_SYS_NULL_PTR XM_DEF_ERR(XM_ID_SYS, EN_ERR_LEVEL_ERROR, EN_ERR_NULL_PTR)
#define XM_ERR_SYS_NOTREADY XM_DEF_ERR(XM_ID_SYS, EN_ERR_LEVEL_ERROR, EN_ERR_SYS_NOTREADY)
#define XM_ERR_SYS_NOT_PERM XM_DEF_ERR(XM_ID_SYS, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_PERM)
#define XM_ERR_SYS_NOMEM XM_DEF_ERR(XM_ID_SYS, EN_ERR_LEVEL_ERROR, EN_ERR_NOMEM)
#define XM_ERR_SYS_ILLEGAL_PARAM XM_DEF_ERR(XM_ID_SYS, EN_ERR_LEVEL_ERROR, EN_ERR_ILLEGAL_PARAM)
#define XM_ERR_SYS_BUSY XM_DEF_ERR(XM_ID_SYS, EN_ERR_LEVEL_ERROR, EN_ERR_BUSY)
#define XM_ERR_SYS_NOT_SUPPORT XM_DEF_ERR(XM_ID_SYS, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_SUPPORT)
#define XM_ERR_SYS_UNEXIST XM_DEF_ERR(XM_ID_SYS, EN_ERR_LEVEL_ERROR, EN_ERR_UNEXIST)
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /* __XM_COMM_SYS_H__ */

484
general/package/xiongmai-osdrv-xm530/files/include/mpi/xm_comm_vi.h
View File

@ -1,484 +0,0 @@
/******************************************************************************
Copyright (C), 2004-2020, XM Tech. Co., Ltd.
******************************************************************************
File Name : xm_comm_vi.h
Version : Initial Draft
Author : XM multimedia software group
Created : 2015/9/17
Last Modified :
Description :
Function List :
******************************************************************************/
#ifndef __XM_COMM_VI_H__
#define __XM_COMM_VI_H__
#include "xm_common.h"
#include "xm_errno.h"
#include "xm_comm_video.h"
#ifdef __cplusplus
#if __cplusplus
extern "C"
{
#endif
#endif /* __cplusplus */
#define VI_INVALID_FRMRATE (-1UL)
#define VIU_MAX_USER_FRAME_DEPTH 8
/*get the subchn index by main chn */
#define SUBCHN(ViChn) (ViChn + 16)
/* define cascade chn */
#define VI_CAS_CHN_1 32
#define VI_CAS_CHN_2 33
#define XM_TRACE_VI(level, fmt...) XM_TRACE(level, XM_ID_VIU,##fmt)
#define XM_ERR_VI_INVALID_PARA XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, EN_ERR_ILLEGAL_PARAM)
#define XM_ERR_VI_INVALID_DEVID XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_DEVID)
#define XM_ERR_VI_INVALID_CHNID XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_CHNID)
#define XM_ERR_VI_INVALID_NULL_PTR XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, EN_ERR_NULL_PTR)
#define XM_ERR_VI_FAILED_NOTCONFIG XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_CONFIG)
#define XM_ERR_VI_SYS_NOTREADY XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, EN_ERR_SYS_NOTREADY)
#define XM_ERR_VI_BUF_EMPTY XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_EMPTY)
#define XM_ERR_VI_BUF_FULL XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_FULL)
#define XM_ERR_VI_NOMEM XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, EN_ERR_NOMEM)
#define XM_ERR_VI_NOT_SUPPORT XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_SUPPORT)
#define XM_ERR_VI_BUSY XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, EN_ERR_BUSY)
#define XM_ERR_VI_NOT_PERM XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_PERM)
#define XM_ERR_VI_FAILED_NOTENABLE XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, ERR_VI_FAILED_NOTENABLE)/* 0xA0108040*/
#define XM_ERR_VI_FAILED_NOTDISABLE XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, ERR_VI_FAILED_NOTDISABLE)/* 0xA0108041*/
#define XM_ERR_VI_FAILED_CHNOTDISABLE XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, ERR_VI_FAILED_CHNOTDISABLE)/* 0xA0108042*/
#define XM_ERR_VI_CFG_TIMEOUT XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, ERR_VI_CFG_TIMEOUT)/* 0xA0108043*/
#define XM_ERR_VI_NORM_UNMATCH XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, ERR_VI_NORM_UNMATCH)/* 0xA0108044*/
#define XM_ERR_VI_INVALID_WAYID XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, ERR_VI_INVALID_WAYID)/* 0xA0108045*/
#define XM_ERR_VI_INVALID_PHYCHNID XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, ERR_VI_INVALID_PHYCHNID)/* 0xA0108046*/
#define XM_ERR_VI_FAILED_NOTBIND XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, ERR_VI_FAILED_NOTBIND)/* 0xA0108047*/
#define XM_ERR_VI_FAILED_BINDED XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, ERR_VI_FAILED_BINDED)/* 0xA0108048*/
/* interface mode of video input */
typedef enum xmVI_INTF_MODE_E
{
VI_MODE_BT656 = 0, /* ITU-R BT.656 YUV4:2:2 */
VI_MODE_BT601, /* ITU-R BT.601 YUV4:2:2 */
VI_MODE_DIGITAL_CAMERA, /* digatal camera mode */
VI_MODE_BT1120_STANDARD, /* BT.1120 progressive mode */
VI_MODE_BT1120_INTERLEAVED, /* BT.1120 interstage mode */
VI_MODE_BUTT
} VI_INTF_MODE_E;
/* Input mode */
typedef enum xmVI_INPUT_MODE_E
{
VI_INPUT_MODE_BT656 = 0, /* ITU-R BT.656 YUV4:2:2 */
VI_INPUT_MODE_BT601, /* ITU-R BT.601 YUV4:2:2 */
VI_INPUT_MODE_DIGITAL_CAMERA, /* digatal camera mode */
VI_INPUT_MODE_INTERLEAVED,
VI_INPUT_MODE_BUTT
} VI_INPUT_MODE_E;
typedef enum xmVI_WORK_MODE_E
{
VI_WORK_MODE_1Multiplex = 0, /* 1 Multiplex mode */
VI_WORK_MODE_2Multiplex, /* 2 Multiplex mode */
VI_WORK_MODE_4Multiplex, /* 4 Multiplex mode */
VI_WORK_MODE_BUTT
} VI_WORK_MODE_E;
/* whether an input picture is interlaced or progressive */
typedef enum xmVI_SCAN_MODE_E
{
VI_SCAN_INTERLACED = 0,
VI_SCAN_PROGRESSIVE,
VI_SCAN_BUTT,
} VI_SCAN_MODE_E;
typedef enum xmVI_DATA_YUV_SEQ_E
{
/*The input sequence of the second component(only contains u and v) in BT.1120 mode */
VI_INPUT_DATA_VUVU = 0,
VI_INPUT_DATA_UVUV,
/* The input sequence for yuv */
VI_INPUT_DATA_UYVY = 0,
VI_INPUT_DATA_VYUY,
VI_INPUT_DATA_YUYV,
VI_INPUT_DATA_YVYU,
VI_DATA_YUV_BUTT
} VI_DATA_YUV_SEQ_E;
typedef enum xmVI_CLK_EDGE_E
{
VI_CLK_EDGE_SINGLE_UP = 0, /* single-edge mode and in rising edge */
VI_CLK_EDGE_SINGLE_DOWN, /* single-edge mode and in falling edge */
//VI_CLK_EDGE_DOUBLE , /* Double edge mode */
VI_CLK_EDGE_BUTT
} VI_CLK_EDGE_E;
typedef enum xmVI_COMP_MODE_E
{
VI_COMP_MODE_SINGLE = 0, /* in single component mode */
VI_COMP_MODE_DOUBLE = 1, /* in double component mode */
VI_COMP_MODE_BUTT,
}VI_COMP_MODE_E;
/* Y/C composite or separation mode */
typedef enum xmVI_COMBINE_MODE_E
{
VI_COMBINE_COMPOSITE = 0, /* Composite mode */
VI_COMBINE_SEPARATE, /* Separate mode */
VI_COMBINE_BUTT,
} VI_COMBINE_MODE_E;
/* Attribute of the vertical synchronization signal */
typedef enum xmVI_VSYNC_E
{
VI_VSYNC_FIELD = 0, /* Field/toggle mode:a signal reversal means a new frame or a field */
VI_VSYNC_PULSE, /* Pusle/effective mode:a pusle or an effective signal means a new frame or a field */
} VI_VSYNC_E;
/* Polarity of the vertical synchronization signal */
typedef enum xmVI_VSYNC_NEG_E
{
VI_VSYNC_NEG_HIGH = 0, /*if VIU_VSYNC_E = VIU_VSYNC_FIELD,then the vertical synchronization signal of even field is high-level,
if VIU_VSYNC_E = VIU_VSYNC_PULSE,then the vertical synchronization pulse is positive pulse.*/
VI_VSYNC_NEG_LOW /*if VIU_VSYNC_E = VIU_VSYNC_FIELD,then the vertical synchronization signal of even field is low-level,
if VIU_VSYNC_E = VIU_VSYNC_PULSE,then the vertical synchronization pulse is negative pulse.*/
} VI_VSYNC_NEG_E;
/* Attribute of the horizontal synchronization signal */
typedef enum xmVI_HSYNC_E
{
VI_HSYNC_VALID_SINGNAL = 0, /* the horizontal synchronization is valid signal mode */
VI_HSYNC_PULSE, /* the horizontal synchronization is pulse mode, a new pulse means the beginning of a new line */
} VI_HSYNC_E;
/* Polarity of the horizontal synchronization signal */
typedef enum xmVI_HSYNC_NEG_E
{
VI_HSYNC_NEG_HIGH = 0, /*if VI_HSYNC_E = VI_HSYNC_VALID_SINGNAL,then the valid horizontal synchronization signal is high-level;
if VI_HSYNC_E = VI_HSYNC_PULSE,then the horizontal synchronization pulse is positive pulse */
VI_HSYNC_NEG_LOW /*if VI_HSYNC_E = VI_HSYNC_VALID_SINGNAL,then the valid horizontal synchronization signal is low-level;
if VI_HSYNC_E = VI_HSYNC_PULSE,then the horizontal synchronization pulse is negative pulse */
} VI_HSYNC_NEG_E;
/* Attribute of the valid vertical synchronization signal */
typedef enum xmVI_VSYNC_VALID_E
{
VI_VSYNC_NORM_PULSE = 0, /* the vertical synchronization is pusle mode, a pusle means a new frame or field */
VI_VSYNC_VALID_SINGAL, /* the vertical synchronization is effective mode, a effective signal means a new frame or field */
} VI_VSYNC_VALID_E;
/* Polarity of the valid vertical synchronization signal */
typedef enum xmVI_VSYNC_VALID_NEG_E
{
VI_VSYNC_VALID_NEG_HIGH = 0, /*if VI_VSYNC_VALID_E = VI_VSYNC_NORM_PULSE,a positive pulse means vertical synchronization pulse;
if VI_VSYNC_VALID_E = VI_VSYNC_VALID_SINGAL,the valid vertical synchronization signal is high-level */
VI_VSYNC_VALID_NEG_LOW /*if VI_VSYNC_VALID_E = VI_VSYNC_NORM_PULSE,a negative pulse means vertical synchronization pulse;
if VI_VSYNC_VALID_E = VI_VSYNC_VALID_SINGAL,the valid vertical synchronization signal is low-level */
} VI_VSYNC_VALID_NEG_E;
/* Blank information of the input timing */
typedef struct xmVI_TIMING_BLANK_S
{
XM_U32 u32HsyncHfb ; /* Horizontal front blanking width */
XM_U32 u32HsyncAct ; /* Horizontal effetive width */
XM_U32 u32HsyncHbb ; /* Horizontal back blanking width */
XM_U32 u32VsyncVfb ; /* Vertical front blanking height of one frame or odd-field frame picture */
XM_U32 u32VsyncVact ; /* Vertical effetive width of one frame or odd-field frame picture */
XM_U32 u32VsyncVbb ; /* Vertical back blanking height of one frame or odd-field frame picture */
XM_U32 u32VsyncVbfb ; /* Even-field vertical front blanking height when input mode is interlace (invalid when progressive input mode) */
XM_U32 u32VsyncVbact ; /* Even-field vertical effetive width when input mode is interlace (invalid when progressive input mode) */
XM_U32 u32VsyncVbbb ; /* Even-field vertical back blanking height when input mode is interlace (invalid when progressive input mode) */
}VI_TIMING_BLANK_S;
/* synchronization information about the BT.601 or DC timing */
typedef struct xmVI_SYNC_CFG_S
{
VI_VSYNC_E enVsync;
VI_VSYNC_NEG_E enVsyncNeg;
VI_HSYNC_E enHsync;
VI_HSYNC_NEG_E enHsyncNeg;
VI_VSYNC_VALID_E enVsyncValid;
VI_VSYNC_VALID_NEG_E enVsyncValidNeg;
VI_TIMING_BLANK_S stTimingBlank;
} VI_SYNC_CFG_S;
/* the highest bit of the BT.656 timing reference code*/
typedef enum xmBT656_FIXCODE_E
{
BT656_FIXCODE_1 = 0, /* The highest bit of the EAV/SAV data over the BT.656 protocol is always 1.*/
BT656_FIXCODE_0 /* The highest bit of the EAV/SAV data over the BT.656 protocol is always 0.*/
}BT656_FIXCODE_E;
/* Polarity of the field indicator bit (F) of the BT.656 timing reference code */
typedef enum xmBT656_FIELD_POLAR_E
{
BT656_FIELD_POLAR_STD = 0, /* the standard BT.656 mode,the first filed F=0,the second filed F=1*/
BT656_FIELD_POLAR_NSTD /* the non-standard BT.656 mode,the first filed F=1,the second filed F=0*/
}BT656_FIELD_POLAR_E;
typedef struct xmVI_BT656_SYNC_CFG_S
{
BT656_FIXCODE_E enFixCode;
BT656_FIELD_POLAR_E enFieldPolar;
}VI_BT656_SYNC_CFG_S;
typedef enum xmVI_VBI_LOCAL_E
{
VI_VBI_LOCAL_ODD_FRONT = 0,
VI_VBI_LOCAL_ODD_END,
VI_VBI_LOCAL_EVEN_FRONT,
VI_VBI_LOCAL_EVEN_END,
VI_VBI_LOCAL_BUTT
} VI_VBI_LOCAL_E;
typedef struct xmVI_VBI_ATTR_S
{
VI_VBI_LOCAL_E enLocal; /* location of VBI */
XM_S32 s32X; /* horizontal original position of the VBI data */
XM_S32 s32Y; /* vertical original position of the VBI data */
XM_U32 u32Len; /* length of VBI data, by word(4 Bytes) */
} VI_VBI_ATTR_S;
typedef enum xmVI_DATA_TYPE_E
{
VI_DATA_TYPE_YUV = 0,
VI_DATA_TYPE_RGB = 1,
VI_DATA_TYPE_BUTT
} VI_DATA_TYPE_E;
typedef enum xmVI_DATA_PATH_E
{
VI_PATH_BYPASS = 0, /* ISP bypass */
VI_PATH_ISP = 1, /* ISP enable */
VI_PATH_RAW = 2, /* Capture raw data, for debug */
VI_PATH_BUTT
}VI_DATA_PATH_E;
/* the extended attributes of VI device */
typedef struct xmVI_DEV_ATTR_EX_S
{
VI_INPUT_MODE_E enInputMode; /* Input mode */
VI_WORK_MODE_E enWorkMode; /*1-, 2-, or 4-channel multiplexed work mode */
VI_COMBINE_MODE_E enCombineMode; /* Y/C composite or separation mode */
VI_COMP_MODE_E enCompMode; /* Component mode (single-component or dual-component) */
VI_CLK_EDGE_E enClkEdge; /* Clock edge mode (sampling on the rising or falling edge) */
XM_U32 au32CompMask[2]; /* Component mask */
VI_SCAN_MODE_E enScanMode; /* Input scanning mode (progressive or interlaced) */
XM_S32 s32AdChnId[4]; /* AD channel ID. Typically, the default value -1 is recommended */
VI_DATA_YUV_SEQ_E enDataSeq; /* Input data sequence (only the YUV format is supported) */
VI_SYNC_CFG_S stSynCfg; /* Sync timing. This member must be configured in BT.601 mode or DC mode */
VI_BT656_SYNC_CFG_S stBT656SynCfg; /* Sync timing. This member must be configured in BT.656 mode */
VI_DATA_PATH_E enDataPath; /* ISP enable or bypass */
VI_DATA_TYPE_E enInputDataType; /* RGB: CSC-709 or CSC-601, PT YUV444 disable; YUV: default yuv CSC coef PT YUV444 enable. */
XM_BOOL bDataRev; /* Data reverse */
} VI_DEV_ATTR_EX_S;
/* the attributes of a VI device */
typedef struct xmVI_DEV_ATTR_S
{
VI_INTF_MODE_E enIntfMode; /* Interface mode */
VI_WORK_MODE_E enWorkMode; /*1-, 2-, or 4-channel multiplexed work mode */
XM_U32 au32CompMask[2]; /* Component mask */
VI_SCAN_MODE_E enScanMode; /* Input scanning mode (progressive or interlaced) */
XM_S32 s32AdChnId[4]; /* AD channel ID. Typically, the default value -1 is recommended */
/* The below members must be configured in BT.601 mode or DC mode and are invalid in other modes */
VI_DATA_YUV_SEQ_E enDataSeq; /* Input data sequence (only the YUV format is supported) */
VI_SYNC_CFG_S stSynCfg; /* Sync timing. This member must be configured in BT.601 mode or DC mode */
VI_DATA_PATH_E enDataPath; /* ISP enable or bypass */
VI_DATA_TYPE_E enInputDataType; /* RGB: CSC-709 or CSC-601, PT YUV444 disable; YUV: default yuv CSC coef PT YUV444 enable. */
XM_BOOL bDataRev; /* Data reverse */
} VI_DEV_ATTR_S;
typedef struct xmVI_CHN_BIND_ATTR_S
{
VI_DEV ViDev;
VI_WAY ViWay;
} VI_CHN_BIND_ATTR_S;
/* the attributes of a VI way */
typedef struct xmVI_WAY_ATTR_S
{
XM_S32 s32AdChnId;
} VI_WAY_ATTR_S;
/* captrue selection of video input */
typedef enum xmVI_CAPSEL_E
{
VI_CAPSEL_TOP = 0, /* top field */
VI_CAPSEL_BOTTOM, /* bottom field */
VI_CAPSEL_BOTH, /* top and bottom field */
VI_CAPSEL_BUTT
} VI_CAPSEL_E;
/* the attributes of a VI channel */
typedef struct xmVI_CHN_ATTR_S
{
RECT_S stCapRect; /* the capture rect (corresponding to the size of the picture captured by a VI device).
For primary channels, the stCapRect's u32Width and u32Height are static attributes. That is,
the value of them can be changed only after primary and secondary channels are disabled.
For secondary channels, stCapRect is an invalid attribute */
SIZE_S stDestSize; /* Target picture size.
For primary channels, stDestSize must be equal to stCapRect's u32Width and u32Height,
because primary channel doesn't have scale capability. Additionally, it is a static
attribute, That is, the value of stDestSize can be changed only after primary and
secondary channels are disabled.
For secondary channels, stDestSize is a dynamic attribute */
VI_CAPSEL_E enCapSel; /* Frame/field select. It is used only in interlaced mode.
For primary channels, enCapSel is a static attribute */
PIXEL_FORMAT_E enPixFormat; /* Pixel storage format. Only the formats semi-planar420 and semi-planar422 are supported */
XM_BOOL bMirror; /* Whether to mirror */
XM_BOOL bFlip; /* Whether to flip */
XM_BOOL bChromaResample; /* Whether to perform chrominance resampling. It is valid only for primary channels */
XM_S32 s32SrcFrameRate; /* Source frame rate. The value -1 indicates that the frame rate is not controlled */
XM_S32 s32FrameRate; /* Target frame rate. The value -1 indicates that the frame rate is not controlled */
} VI_CHN_ATTR_S;
typedef struct xmVI_CHN_STAT_S
{
XM_BOOL bEnable; /* Whether this channel is enabled */
XM_U32 u32IntCnt; /* The video frame interrupt count */
XM_U32 u32FrmRate; /* current frame rate */
XM_U32 u32LostInt; /* The interrupt is received but nobody care */
XM_U32 u32VbFail; /* Video buffer malloc failure */
XM_U32 u32PicWidth; /* curren pic width */
XM_U32 u32PicHeight; /* current pic height */
XM_U32 u32AutoDisInt; /* auto disable interrupt count, when VIU detected too many interrupts */
} VI_CHN_STAT_S;
typedef enum xm_VI_USERPIC_MODE_E
{
VI_USERPIC_MODE_PIC = 0, /* YUV picture */
VI_USERPIC_MODE_BGC, /* Background picture only with a color */
VI_USERPIC_MODE_BUTT,
} VI_USERPIC_MODE_E;
typedef struct xmVI_USERPIC_BGC_S
{
XM_U32 u32BgColor;
} VI_USERPIC_BGC_S;
typedef struct xmVI_USERPIC_ATTR_S
{
XM_BOOL bPub; /* Whether the user picture information is shared by all VI devices and channels*/
VI_USERPIC_MODE_E enUsrPicMode; /* User picture mode */
union
{
VIDEO_FRAME_INFO_S stUsrPicFrm; /* Information about a YUV picture */
VI_USERPIC_BGC_S stUsrPicBg; /* Information about a background picture only with a color */
}unUsrPic;
} VI_USERPIC_ATTR_S;
typedef struct xmVI_USR_GET_FRM_TIMEOUT_S
{
VIDEO_FRAME_INFO_S *pstVFrame;
XM_U32 u32MilliSec;
} VI_USR_GET_FRM_TIMEOUT_S;
typedef enum xmVI_FLASH_MODE_E
{
VI_FLASH_ONCE = 0, /* Flash one time */
VI_FLASH_FREQ = 1, /* Flash frequently */
VI_FLASH_MODE_BUTT
}VI_FLASH_MODE_E;
typedef struct xmVI_FlASH_CONFIG_S
{
VI_FLASH_MODE_E enFlashMode; /* Flash one time, flash frequently*/
XM_U32 u32StartTime; /* Flash start time£¬unit: sensor pix clk.*/
XM_U32 u32Duration; /* Flash high duration, unit: sensor pix clk.*/
XM_U32 u32CapFrmIndex; /* Set which vframe will be bFlashed after flashing, default is 0. */
XM_U32 u32Interval; /* Flash frequently interval, unit: frame*/
}VI_FLASH_CONFIG_S;
typedef struct xmVI_EXT_CHN_ATTR_S
{
VI_CHN s32BindChn; /* The channel num which extend channel will bind to*/
SIZE_S stDestSize; /* Target size*/
XM_S32 s32SrcFrameRate; /* Source frame rate. The value -1 indicates that the frame rate is not controlled */
XM_S32 s32FrameRate; /* Target frame rate. The value -1 indicates that the frame rate is not controlled */
PIXEL_FORMAT_E enPixFormat; /* Pixel storage format. Only the formats semi-planar420 and semi-planar422 are supported */
}VI_EXT_CHN_ATTR_S;
typedef struct xmVI_LDC_ATTR_S
{
XM_BOOL bEnable; /* Whether LDC is enbale */
LDC_ATTR_S stAttr; /* LDC Attribute */
}VI_LDC_ATTR_S;
typedef struct xmVI_CHN_LUM_S
{
XM_U32 u32Lum; /* Luma sum of current frame */
XM_U64 u64Pts; /* PTS of current frame */
} VI_CHN_LUM_S;
typedef enum xmVI_CSC_TYPE_E
{
VI_CSC_TYPE_601 = 0, /* CSC Type: 601 */
VI_CSC_TYPE_709, /* CSC Type: 709 */
VI_CSC_TYPE_BUTT,
} VI_CSC_TYPE_E;
typedef struct xmVI_CSC_ATTR_S
{
VI_CSC_TYPE_E enViCscType; /* 601 or 709 */
XM_U32 u32LumaVal; /* Luminance: [0 ~ 100] */
XM_U32 u32ContrVal; /* Contrast: [0 ~ 100] */
XM_U32 u32HueVal; /* Hue: [0 ~ 100] */
XM_U32 u32SatuVal; /* Satuature: [0 ~ 100] */
} VI_CSC_ATTR_S;
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /* End of #ifndef__XM_COMM_VIDEO_IN_H__ */

465
general/package/xiongmai-osdrv-xm530/files/include/mpi/xm_comm_vo.h
View File

@ -1,465 +0,0 @@
#ifndef __XM_COMM_VO_H__
#define __XM_COMM_VO_H__
#include "xm_type.h"
#include "xm_common.h"
#include "xm_comm_video.h"
#include "xm_errno.h"
#define VO_DEF_CHN_BUF_LEN 8
#define VO_DEF_DISP_BUF_LEN 5
#define VO_DEF_VIRT_BUF_LEN 3
#define VO_DEF_WBC_DEPTH_LEN 8
#ifdef __cplusplus
#if __cplusplus
extern "C"{
#endif
#endif /* End of #ifdef __cplusplus */
typedef enum xmEN_VOU_ERR_CODE_E
{
EN_ERR_VO_DEV_NOT_CONFIG = 0x40,
EN_ERR_VO_DEV_NOT_ENABLE = 0x41,
EN_ERR_VO_DEV_HAS_ENABLED = 0x42,
EN_ERR_VO_DEV_HAS_BINDED = 0x43,
EN_ERR_VO_DEV_NOT_BINDED = 0x44,
ERR_VO_NOT_ENABLE = 0x45,
ERR_VO_NOT_DISABLE = 0x46,
ERR_VO_NOT_CONFIG = 0x47,
ERR_VO_CHN_NOT_DISABLE = 0x48,
ERR_VO_CHN_NOT_ENABLE = 0x49,
ERR_VO_CHN_NOT_CONFIG = 0x4a,
ERR_VO_CHN_NOT_ALLOC = 0x4b,
ERR_VO_CCD_INVALID_PAT = 0x4c,
ERR_VO_CCD_INVALID_POS = 0x4d,
ERR_VO_WAIT_TIMEOUT = 0x4e,
ERR_VO_INVALID_VFRAME = 0x4f,
ERR_VO_INVALID_RECT_PARA = 0x50,
ERR_VO_SETBEGIN_ALREADY = 0x51,
ERR_VO_SETBEGIN_NOTYET = 0x52,
ERR_VO_SETEND_ALREADY = 0x53,
ERR_VO_SETEND_NOTYET = 0x54,
ERR_VO_GRP_INVALID_ID = 0x55,
ERR_VO_GRP_NOT_CREATE = 0x56,
ERR_VO_GRP_HAS_CREATED = 0x57,
ERR_VO_GRP_NOT_DESTROY = 0x58,
ERR_VO_GRP_CHN_FULL = 0x59,
ERR_VO_GRP_CHN_EMPTY = 0x5a,
ERR_VO_GRP_CHN_NOT_EMPTY = 0x5b,
ERR_VO_GRP_INVALID_SYN_MODE = 0x5c,
ERR_VO_GRP_INVALID_BASE_PTS = 0x5d,
ERR_VO_GRP_NOT_START = 0x5e,
ERR_VO_GRP_NOT_STOP = 0x5f,
ERR_VO_GRP_INVALID_FRMRATE = 0x60,
ERR_VO_GRP_CHN_HAS_REG = 0x61,
ERR_VO_GRP_CHN_NOT_REG = 0x62,
ERR_VO_GRP_CHN_NOT_UNREG = 0x63,
ERR_VO_GRP_BASE_NOT_CFG = 0x64,
ERR_GFX_NOT_DISABLE = 0x65,
ERR_GFX_NOT_BIND = 0x66,
ERR_GFX_NOT_UNBIND = 0x67,
ERR_GFX_INVALID_ID = 0x68,
ERR_VO_WBC_NOT_DISABLE = 0x69,
ERR_VO_WBC_NOT_CONFIG = 0x6a,
ERR_VO_CHN_AREA_OVERLAP = 0x6b,
EN_ERR_INVALID_WBCID = 0x6c,
EN_ERR_INVALID_LAYERID = 0x6d,
EN_ERR_VO_VIDEO_HAS_BINDED = 0x6e,
EN_ERR_VO_VIDEO_NOT_BINDED = 0x6f,
ERR_VO_WBC_HAS_BIND = 0x70,
ERR_VO_WBC_HAS_CONFIG = 0x71,
ERR_VO_WBC_NOT_BIND = 0x72,
/* new added */
ERR_VO_BUTT
}EN_VOU_ERR_CODE_E;
#define XM_TRACE_VO(level, fmt...) XM_TRACE(level, XM_ID_VOU,##fmt)
/* System define error code */
#define XM_ERR_VO_BUSY XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_BUSY)
#define XM_ERR_VO_NO_MEM XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_NOMEM)
#define XM_ERR_VO_NULL_PTR XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_NULL_PTR)
#define XM_ERR_VO_SYS_NOTREADY XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_SYS_NOTREADY)
#define XM_ERR_VO_INVALID_DEVID XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_DEVID)
#define XM_ERR_VO_INVALID_CHNID XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_CHNID)
#define XM_ERR_VO_ILLEGAL_PARAM XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_ILLEGAL_PARAM)
#define XM_ERR_VO_NOT_SUPPORT XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_SUPPORT)
#define XM_ERR_VO_NOT_PERMIT XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_PERM)
#define XM_ERR_VO_INVALID_WBCID XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_WBCID)
#define XM_ERR_VO_INVALID_LAYERID XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_LAYERID)
/* device relative error code */
#define XM_ERR_VO_DEV_NOT_CONFIG XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_VO_DEV_NOT_CONFIG)
#define XM_ERR_VO_DEV_NOT_ENABLE XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_VO_DEV_NOT_ENABLE)
#define XM_ERR_VO_DEV_HAS_ENABLED XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_VO_DEV_HAS_ENABLED)
#define XM_ERR_VO_DEV_HAS_BINDED XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_VO_DEV_HAS_BINDED)
#define XM_ERR_VO_DEV_NOT_BINDED XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_VO_DEV_NOT_BINDED)
/* video relative error code */
#define XM_ERR_VO_VIDEO_NOT_ENABLE XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_NOT_ENABLE)
#define XM_ERR_VO_VIDEO_NOT_DISABLE XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_NOT_DISABLE)
#define XM_ERR_VO_VIDEO_NOT_CONFIG XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_NOT_CONFIG)
#define XM_ERR_VO_VIDEO_HAS_BINDED XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_VO_VIDEO_HAS_BINDED)
#define XM_ERR_VO_VIDEO_NOT_BINDED XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_VO_VIDEO_NOT_BINDED)
/*wbc error code*/
#define XM_ERR_VO_WBC_NOT_DISABLE XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_WBC_NOT_DISABLE)
#define XM_ERR_VO_WBC_NOT_CONFIG XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_WBC_NOT_CONFIG)
#define XM_ERR_VO_WBC_HAS_CONFIG XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_WBC_HAS_CONFIG)
#define XM_ERR_VO_WBC_NOT_BIND XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_WBC_NOT_BIND)
#define XM_ERR_VO_WBC_HAS_BIND XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_WBC_HAS_BIND)
/* channel relative error code */
#define XM_ERR_VO_CHN_NOT_DISABLE XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_CHN_NOT_DISABLE)
#define XM_ERR_VO_CHN_NOT_ENABLE XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_CHN_NOT_ENABLE)
#define XM_ERR_VO_CHN_NOT_CONFIG XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_CHN_NOT_CONFIG)
#define XM_ERR_VO_CHN_NOT_ALLOC XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_CHN_NOT_ALLOC)
#define XM_ERR_VO_CHN_AREA_OVERLAP XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_CHN_AREA_OVERLAP)
/* cascade relatvie error code */
#define XM_ERR_VO_INVALID_PATTERN XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_CCD_INVALID_PAT)
#define XM_ERR_VO_INVALID_POSITION XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_CCD_INVALID_POS)
/* misc */
#define XM_ERR_VO_WAIT_TIMEOUT XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_WAIT_TIMEOUT)
#define XM_ERR_VO_INVALID_VFRAME XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_INVALID_VFRAME)
#define XM_ERR_VO_INVALID_RECT_PARA XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_INVALID_RECT_PARA)
#define XM_ERR_VO_SETBEGIN_ALREADY XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_SETBEGIN_ALREADY)
#define XM_ERR_VO_SETBEGIN_NOTYET XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_SETBEGIN_NOTYET)
#define XM_ERR_VO_SETEND_ALREADY XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_SETEND_ALREADY)
#define XM_ERR_VO_SETEND_NOTYET XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_SETEND_NOTYET)
/* sync group relative error code */
#define XM_ERR_VO_GRP_INVALID_ID XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_INVALID_ID)
#define XM_ERR_VO_GRP_NOT_CREATE XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_NOT_CREATE)
#define XM_ERR_VO_GRP_HAS_CREATED XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_HAS_CREATED)
#define XM_ERR_VO_GRP_NOT_DESTROY XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_NOT_DESTROY)
#define XM_ERR_VO_GRP_CHN_FULL XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_CHN_FULL)
#define XM_ERR_VO_GRP_CHN_EMPTY XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_CHN_EMPTY)
#define XM_ERR_VO_GRP_CHN_NOT_EMPTY XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_CHN_NOT_EMPTY)
#define XM_ERR_VO_GRP_INVALID_SYN_MODE XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_INVALID_SYN_MODE)
#define XM_ERR_VO_GRP_INVALID_BASE_PTS XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_INVALID_BASE_PTS)
#define XM_ERR_VO_GRP_NOT_START XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_NOT_START)
#define XM_ERR_VO_GRP_NOT_STOP XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_NOT_STOP)
#define XM_ERR_VO_GRP_INVALID_FRMRATE XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_INVALID_FRMRATE)
#define XM_ERR_VO_GRP_CHN_HAS_REG XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_CHN_HAS_REG)
#define XM_ERR_VO_GRP_CHN_NOT_REG XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_CHN_NOT_REG)
#define XM_ERR_VO_GRP_CHN_NOT_UNREG XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_CHN_NOT_UNREG)
#define XM_ERR_VO_GRP_BASE_NOT_CFG XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_BASE_NOT_CFG)
/* graphics relative error code */
#define XM_ERR_VO_GFX_NOT_DISABLE XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_GFX_NOT_DISABLE)
#define XM_ERR_VO_GFX_NOT_BIND XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_GFX_NOT_BIND)
#define XM_ERR_VO_GFX_NOT_UNBIND XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_GFX_NOT_UNBIND)
#define XM_ERR_VO_GFX_INVALID_ID XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_GFX_INVALID_ID)
/* vo inteface type */
#define VO_INTF_CVBS (0x01L<<0)
#define VO_INTF_YPBPR (0x01L<<1)
#define VO_INTF_VGA (0x01L<<2)
#define VO_INTF_BT656 (0x01L<<3)
#define VO_INTF_BT1120 (0x01L<<4)
#define VO_INTF_HDMI (0x01L<<5)
#define VO_INTF_LCD (0x01L<<6)
#define VO_INTF_BT656_H (0x01L<<7)
#define VO_INTF_BT656_L (0x01L<<8)
/* WBC channel id*/
#define VO_WBC_CHN_ID (VO_MAX_CHN_NUM + 1)
#define VO_DEFAULT_CHN -1 /* use vo buffer as pip buffer */
/*****************************************************************************
* 3520 ADDed
*****************************************************************************/
typedef XM_S32 VO_INTF_TYPE_E;
//typedef XM_S32 VO_WBC_CHN;
typedef enum xmVO_INTF_SYNC_E
{
VO_OUTPUT_PAL = 0,
VO_OUTPUT_NTSC,
VO_OUTPUT_960H_PAL, /* ITU-R BT.1302 960 x 576 at 50 Hz (interlaced)*/
VO_OUTPUT_960H_NTSC, /* ITU-R BT.1302 960 x 480 at 60 Hz (interlaced)*/
VO_OUTPUT_1080P24,
VO_OUTPUT_1080P25,
VO_OUTPUT_1080P30,
VO_OUTPUT_720P50,
VO_OUTPUT_720P60,
VO_OUTPUT_1080I50,
VO_OUTPUT_1080I60,
VO_OUTPUT_1080P50,
VO_OUTPUT_1080P60,
VO_OUTPUT_576P50,
VO_OUTPUT_480P60,
VO_OUTPUT_640x480_60, /* VESA 640 x 480 at 60 Hz (non-interlaced) CVT */
VO_OUTPUT_800x600_60, /* VESA 800 x 600 at 60 Hz (non-interlaced) */
VO_OUTPUT_1024x768_60, /* VESA 1024 x 768 at 60 Hz (non-interlaced) */
VO_OUTPUT_1280x1024_60, /* VESA 1280 x 1024 at 60 Hz (non-interlaced) */
VO_OUTPUT_1366x768_60, /* VESA 1366 x 768 at 60 Hz (non-interlaced) */
VO_OUTPUT_1440x900_60, /* VESA 1440 x 900 at 60 Hz (non-interlaced) CVT Compliant */
VO_OUTPUT_1280x800_60, /* 1280*800@60Hz VGA@60Hz*/
VO_OUTPUT_1680x1050_60, /* VESA 1680 x 1050 at 60 Hz (non-interlaced) */
VO_OUTPUT_1920x2160_30, /* 1920x2160_30 */
VO_OUTPUT_1600x1200_60, /* VESA 1600 x 1200 at 60 Hz (non-interlaced) */
VO_OUTPUT_1920x1200_60, /* VESA 1920 x 1600 at 60 Hz (non-interlaced) CVT (Reduced Blanking)*/
VO_OUTPUT_2560x1440_30, /* 2560x1440_30 */
VO_OUTPUT_2560x1600_60, /* 2560x1600_60 */
VO_OUTPUT_3840x2160_30, /* 3840x2160_30 */
VO_OUTPUT_3840x2160_60, /* 3840x2160_60 */
VO_OUTPUT_480x272_60, /* 480x272_60*/
VO_OUTPUT_USER,
VO_OUTPUT_BUTT
} VO_INTF_SYNC_E;
typedef enum xmVO_DISPLAY_FIELD_E
{
VO_FIELD_TOP, /* top field*/
VO_FIELD_BOTTOM, /* bottom field*/
VO_FIELD_BOTH, /* top and bottom field*/
VO_FIELD_BUTT
} VO_DISPLAY_FIELD_E;
typedef enum xmVOU_ZOOM_IN_E
{
VOU_ZOOM_IN_RECT = 0, /* zoom in by rect */
VOU_ZOOM_IN_RATIO, /* zoom in by ratio */
VOU_ZOOM_IN_BUTT
} VOU_ZOOM_IN_E;
typedef enum xmVO_CSC_MATRIX_E
{
VO_CSC_MATRIX_IDENTITY = 0, /* do not change color space */
VO_CSC_MATRIX_BT601_TO_BT709, /* change color space from BT.601 to BT.709 */
VO_CSC_MATRIX_BT709_TO_BT601, /* change color space from BT.709 to BT.601 */
VO_CSC_MATRIX_BT601_TO_RGB_PC, /* change color space from BT.601 to RGB */
VO_CSC_MATRIX_BT709_TO_RGB_PC, /* change color space from BT.709 to RGB */
VO_CSC_MATRIX_RGB_TO_BT601_PC, /* change color space from RGB to BT.601 */
VO_CSC_MATRIX_RGB_TO_BT709_PC, /* change color space from RGB to BT.709 */
VO_CSC_MATRIX_BUTT
} VO_CSC_MATRIX_E;
typedef struct xmVO_CHN_ATTR_S
{
XM_U32 u32Priority; /* video out overlay pri sd */
RECT_S stRect; /* rect of video out chn */
XM_BOOL bDeflicker; /* deflicker or not sd */
}VO_CHN_ATTR_S;
typedef struct tagVO_SYNC_INFO_S
{
XM_BOOL bSynm; /* sync mode(0:timing,as BT.656; 1:signal,as LCD) */
XM_BOOL bIop; /* interlaced or progressive display(0:i; 1:p) */
XM_U8 u8Intfb; /* interlace bit width while output */
XM_U16 u16Vact ; /* vertical active area */
XM_U16 u16Vbb; /* vertical back blank porch */
XM_U16 u16Vfb; /* vertical front blank porch */
XM_U16 u16Hact; /* herizontal active area */
XM_U16 u16Hbb; /* herizontal back blank porch */
XM_U16 u16Hfb; /* herizontal front blank porch */
XM_U16 u16Hmid; /* bottom herizontal active area */
XM_U16 u16Bvact; /* bottom vertical active area */
XM_U16 u16Bvbb; /* bottom vertical back blank porch */
XM_U16 u16Bvfb; /* bottom vertical front blank porch */
XM_U16 u16Hpw; /* horizontal pulse width */
XM_U16 u16Vpw; /* vertical pulse width */
XM_BOOL bIdv; /* inverse data valid of output */
XM_BOOL bIhs; /* inverse horizontal synch signal */
XM_BOOL bIvs; /* inverse vertical synch signal */
} VO_SYNC_INFO_S;
typedef struct xmVO_PUB_ATTR_S
{
XM_U32 u32BgColor; /* Background color of a device, in RGB format. */
VO_INTF_TYPE_E enIntfType; /* Type of a VO interface */
VO_INTF_SYNC_E enIntfSync; /* Type of a VO interface timing */
VO_SYNC_INFO_S stSyncInfo; /* Information about VO interface timings */
} VO_PUB_ATTR_S;
typedef struct xmVO_WBC_ATTR_S
{
SIZE_S stTargetSize; /* WBC Zoom target size */
PIXEL_FORMAT_E enPixelFormat; /* the pixel format of WBC output */
XM_U32 u32FrameRate; /* frame rate control */
} VO_WBC_ATTR_S;
typedef enum xmVO_WBC_MODE_E
{
VO_WBC_MODE_NOMAL = 0, /* In this mode, wbc will capture frames according to dev frame rate
and wbc frame rate */
VO_WBC_MODE_DROP_REPEAT, /* In this mode, wbc will drop dev repeat frame, and capture the real frame
according to video layer's display rate and wbc frame rate */
VO_WBC_MODE_PROG_TO_INTL, /* In this mode, wbc will drop dev repeat frame which repeats more than 3 times,
and change two progressive frames to one interlace frame */
VO_WBC_MODE_BUTT,
} VO_WBC_MODE_E;
typedef enum xmVO_WBC_SOURCE_TYPE_E
{
VO_WBC_SOURCE_DEV = 0x0, /* WBC source is device */
VO_WBC_SOURCE_VIDEO = 0x1, /* WBC source is video layer */
VO_WBC_SOURCE_GRAPHIC = 0x2, /* WBC source is graphic layer, not support */
VO_WBC_SOURCE_BUTT
} VO_WBC_SOURCE_TYPE_E;
typedef struct xmVO_WBC_SOURCE_S
{
VO_WBC_SOURCE_TYPE_E enSourceType; /* the type of WBC source */
XM_U32 u32SourceId; /* the device, video layer or graphic layer */
} VO_WBC_SOURCE_S;
typedef enum xmVO_CAS_MODE_E
{
VO_CAS_MODE_SINGLE = 0, /* cascade mode is single */
VO_CAS_MODE_DUAL, /* cascade mode is dual */
VO_CAS_MODE_BUTT,
} VO_CAS_MODE_E;
typedef enum xmVO_CAS_DATA_TRAN_MODE_E
{
VO_CAS_DATA_SINGLE_TRAN_MODE = 0, /* single transition,clock rising edge or clock falling edge tigger transition */
VO_CAS_DATA_DOUBLE_TRAN_MODE, /* double transition,clock rising edge and clock falling edge tigger transition */
VO_CAS_DATA_MODE_BUTT,
} VO_CAS_DATA_TRAN_MODE_E;
typedef enum xmVO_CAS_RGN_E
{
VO_CAS_64_RGN = 0,
VO_CAS_32_RGN,
VO_CAS_RGN_BUTT,
} VO_CAS_RGN_E; /* cascade region number */
typedef struct xmVO_CAS_ATTR_S
{
XM_BOOL bSlave; /* XM_TRUE: slave mode, XM_FALSE: master mode */
VO_CAS_RGN_E enCasRgn; /* cascade region number */
VO_CAS_MODE_E enCasMode; /* cascade mode */
VO_CAS_DATA_TRAN_MODE_E enCasDataTranMode; /* cascade data transition mode */
} VO_CAS_ATTR_S;
typedef enum xmVO_PART_MODE_E
{
VO_PART_MODE_SINGLE = 0, /* single partition, which use software to make multi-picture in one hardware cell */
VO_PART_MODE_MULTI = 1, /* muliti partition, each partition is a hardware cell */
VO_PART_MODE_BUTT
} VO_PART_MODE_E;
typedef struct xmVO_COMPRESS_ATTR_S
{
XM_BOOL bSupportCompress; /* Whether to support compress */
}VO_COMPRESS_ATTR_S;
typedef struct xmVO_VIDEO_LAYER_ATTR_S
{
RECT_S stDispRect; /* Display resolution */
SIZE_S stImageSize; /* Canvas size of the video layer */
XM_U32 u32DispFrmRt; /* Display frame rate */
PIXEL_FORMAT_E enPixFormat; /* Pixel format of the video layer */
XM_BOOL bDoubleFrame; /* Whether to double frames */
XM_BOOL bClusterMode; /* Whether to take Cluster way to use memory*/
} VO_VIDEO_LAYER_ATTR_S;
typedef enum xmVOU_LAYER_DDR_E
{
VOU_LAYER_DDR0 = 0,
VOU_LAYER_DDR1 = 1,
VOU_LAYER_DDR_BUTT
}VOU_LAYER_DDR_E;
typedef struct xmVO_ZOOM_RATIO_S
{
XM_U32 u32XRatio;
XM_U32 u32YRatio;
XM_U32 u32WRatio;
XM_U32 u32HRatio;
} VO_ZOOM_RATIO_S;
typedef struct xmVO_ZOOM_ATTR_S
{
VOU_ZOOM_IN_E enZoomType; /* choose the type of zoom in */
union
{
RECT_S stZoomRect; /* zoom in by rect */
VO_ZOOM_RATIO_S stZoomRatio; /* zoom in by ratio */
};
} VO_ZOOM_ATTR_S;
typedef struct xmVO_CSC_S
{
VO_CSC_MATRIX_E enCscMatrix;
XM_U32 u32Luma; /* luminance: 0 ~ 100 default: 50 */
XM_U32 u32Contrast; /* contrast : 0 ~ 100 default: 50 */
XM_U32 u32Hue; /* hue : 0 ~ 100 default: 50 */
XM_U32 u32Saturation; /* saturation: 0 ~ 100 default: 50 */
} VO_CSC_S;
typedef struct xmVO_VGA_PARAM_S
{
VO_CSC_S stCSC; /* color space */
XM_U32 u32Gain; /* current gain of VGA signals. [0, 64). default:0x30 */
XM_S32 s32SharpenStrength; /* current sharpen strength of VGA signals. [0, 255]. default:0x80 */
} VO_VGA_PARAM_S;
typedef struct xmVO_HDMI_PARAM_S
{
VO_CSC_S stCSC; /* color space */
} VO_HDMI_PARAM_S;
typedef struct xmVO_REGION_INFO_S
{
RECT_S *pstRegion; /*region attribute*/
XM_U32 u32RegionNum; /*count of the region*/
}VO_REGION_INFO_S;
typedef struct xmVO_IMAGE_LAYER_ATTR_S
{
RECT_S stDispRect; /* Display resolution */
PIXEL_FORMAT_E enPixFormat; /* Pixel format of the video layer */
XM_U32 u32PhyAddr;
XM_U32 u32Effect; /*0-7 tran;8-15 tran0;16-23 tran1; 24-27 HUP;28-31VUP */
} VO_IMAGE_LAYER_ATTR_S;
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* End of #ifndef __XM_COMM_VO_H__ */

40
general/package/xiongmai-osdrv-xm530/files/include/mpi_adec.h
View File

@ -1,40 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2025, XM Tech. Co., Ltd.
******************************************************************************
File Name : mpi_adec.h
Version : Initial Draft
Author : XM multimedia software group
Created : 2015/9/17
Description :
******************************************************************************/
#ifndef _MPI_ADEC_H__
#define _MPI_ADEC_H__
#include "xm_common.h"
#include "xm_comm_aio.h"
#include "xm_comm_adec.h"
#ifdef __cplusplus
#if __cplusplus
extern "C"
{
#endif
#endif /* __cplusplus */
XM_S32 XM_MPI_ADEC_CreateChn(ADEC_CHN AdChn, ADEC_CHN_ATTR_S *pstAttr);
XM_S32 XM_MPI_ADEC_DestroyChn(ADEC_CHN AdChn);
XM_S32 XM_MPI_ADEC_SendStream(ADEC_CHN AdChn, const AUDIO_STREAM_S *pstStream, XM_BOOL bBlock);
XM_S32 XM_MPI_ADEC_ReleaseBuf(ADEC_CHN AdChn);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif

47
general/package/xiongmai-osdrv-xm530/files/include/mpi_aenc.h
View File

@ -1,47 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2025, XM Tech. Co., Ltd.
******************************************************************************
File Name : mpi_aenc.h
Version : Initial Draft
Author : XM multimedia software group
Created : 2015/9/17
Description :
******************************************************************************/
#ifndef _MPI_AENC_H__
#define _MPI_AENC_H__
#include "xm_common.h"
#include "xm_comm_aio.h"
#include "xm_comm_aenc.h"
#ifdef __cplusplus
#if __cplusplus
extern "C"
{
#endif
#endif /* __cplusplus */
#define AENC_ADAPT_MAGIC 0Xfcfcfcfc
XM_S32 XM_MPI_AENC_CreateChn(AENC_CHN AeChn, const AENC_CHN_ATTR_S *pstAttr);
XM_S32 XM_MPI_AENC_DestroyChn(AENC_CHN AeChn);
XM_S32 XM_MPI_AENC_SendFrame(AENC_CHN AeChn,
const AUDIO_FRAME_S *pstFrm, const AEC_FRAME_S *pstAecFrm);
XM_S32 XM_MPI_AENC_GetStream(AENC_CHN AeChn, AUDIO_STREAM_S *pstStream, XM_BOOL bBlock);
XM_S32 XM_MPI_AENC_ReleaseStream(AENC_CHN AeChn, const AUDIO_STREAM_S *pstStream);
XM_S32 XM_MPI_AENC_GetFd(AENC_CHN AeChn);
XM_S32 XM_MPI_AENC_ReleaseBuf(AENC_CHN AeChn);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif

54
general/package/xiongmai-osdrv-xm530/files/include/mpi_ai.h
View File

@ -1,54 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2025, XM Tech. Co., Ltd.
******************************************************************************
File Name : mpi_ai.h
Version : Initial Draft
Author : XM multimedia software group
Created : 2015/9/17
Description :
******************************************************************************/
#ifndef _MPI_AI_H__
#define _MPI_AI_H__
#include "xm_type.h"
#include "xm_common.h"
#include "xm_comm_aio.h"
#ifdef __cplusplus
#if __cplusplus
extern "C"
{
#endif
#endif /* __cplusplus */
#define FRAME_SIZE 160
XM_S32 XM_MPI_AI_SetVqeAttr(AUDIO_DEV AiDevId, AI_CHN AiChn, AUDIO_DEV AoDevId, AO_CHN AoChn, AI_VQE_CONFIG_S *pstVqeConfig);
XM_S32 XM_MPI_AI_GetVqeAttr(AUDIO_DEV AiDevId, AI_CHN AiChn, AI_VQE_CONFIG_S *pstVqeConfig);
XM_S32 XM_MPI_AI_SetVolume(AUDIO_DEV AudioDevId, XM_S32 s32VolumeDb);
XM_S32 XM_MPI_AI_GetVolume(AUDIO_DEV AudioDevId, XM_S32 *ps32VolumeDb);
XM_S32 XM_MPI_AUDIO_Init(void);
XM_S32 XM_MPI_AI_SetPubAttr(AUDIO_DEV AudioDevId, const AIO_ATTR_S *pstAttr);
XM_S32 XM_MPI_AI_GetPubAttr(AUDIO_DEV AudioDevId, AIO_ATTR_S *pstAttr);
XM_S32 XM_MPI_AI_Enable(AUDIO_DEV AudioDevId);
XM_S32 XM_MPI_AI_Disable(AUDIO_DEV AudioDevId);
XM_S32 XM_MPI_AI_GetFrame(AUDIO_DEV AudioDevId, AI_CHN AiChn,
AUDIO_FRAME_S *pstFrm, AEC_FRAME_S *pstAecFrm, XM_BOOL bBlock);
XM_S32 XM_MPI_AI_RegisterFunc(fAudioInPreCallBack func);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif

50
general/package/xiongmai-osdrv-xm530/files/include/mpi_ao.h
View File

@ -1,50 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2025, XM Tech. Co., Ltd.
******************************************************************************
File Name : mpi_ao.h
Version : Initial Draft
Author : XM multimedia software group
Created : 2015/9/17
Description :
******************************************************************************/
#ifndef _MPI_AO_H__
#define _MPI_AO_H__
#include "xm_type.h"
#include "xm_common.h"
#include "xm_comm_aio.h"
#ifdef __cplusplus
#if __cplusplus
extern "C"
{
#endif
#endif /* __cplusplus */
XM_S32 XM_MPI_AO_SetPubAttr(AUDIO_DEV AudioDevId, const AIO_ATTR_S *pstAttr);
XM_S32 XM_MPI_AO_GetPubAttr(AUDIO_DEV AudioDevId, AIO_ATTR_S *pstAttr);
XM_S32 XM_MPI_AO_Enable(AUDIO_DEV AudioDevId);
XM_S32 XM_MPI_AO_Disable(AUDIO_DEV AudioDevId);
XM_S32 XM_MPI_AO_GetFd(AUDIO_DEV AudioDevId);
XM_S32 XM_MPI_AO_SetVolume(AUDIO_DEV AudioDevId, XM_S32 s32VolumeDb);
XM_S32 XM_MPI_AO_GetVolume(AUDIO_DEV AudioDevId, XM_S32 *ps32VolumeDb);
XM_S32 XM_MPI_AO_SetMute(AUDIO_DEV AudioDevId, XM_BOOL bEnable, AUDIO_FADE_S *pstFade);
XM_S32 XM_MPI_AO_GetMute(AUDIO_DEV AudioDevId, XM_BOOL *pbEnable, AUDIO_FADE_S *pstFade);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif

46
general/package/xiongmai-osdrv-xm530/files/include/mpi_region.h
View File

@ -1,46 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2025, XM Tech. Co., Ltd.
******************************************************************************
File Name : mpi_region.h
Version : Initial Draft
Author : XM multimedia software group
Created : 2015/9/17
Description :
******************************************************************************/
#ifndef __MPI_REGION_H__
#define __MPI_REGION_H__
#ifdef __cplusplus
#if __cplusplus
extern "C"{
#endif
#endif /* End of #ifdef __cplusplus */
#include "xm_comm_region.h"
XM_S32 XM_MPI_RGN_Init(void);
XM_S32 XM_MPI_RGN_SetPallet(VI_CHN ViChn, const RGN_PALLET_S *pstPallet);
XM_S32 XM_MPI_RGN_Create(VI_CHN ViChn, const RGN_ATTR_S *pstRegion);
XM_S32 XM_MPI_RGN_Destroy(VI_CHN ViChn, const RGN_ATTR_S *pstRegion);
XM_S32 XM_MPI_RGN_GetAttr(VI_CHN ViChn,RGN_ATTR_S *pstRegion);
XM_S32 XM_MPI_RGN_SetAttr(VI_CHN ViChn, const RGN_ATTR_S *pstRegion);
XM_S32 XM_MPI_RGN_SetBitMap(VI_CHN ViChn, const BITMAP_S *pstBitmap);
XM_S32 XM_MPI_RGN_Enable(VI_CHN ViChn, XM_U32 Handle, RGN_TYPE_E enType);
XM_S32 XM_MPI_RGN_Disable(VI_CHN ViChn, XM_U32 Handle, RGN_TYPE_E enType);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* End of #ifndef __MPI_REGION_H__ */

72
general/package/xiongmai-osdrv-xm530/files/include/mpi_sys.h
View File

@ -1,72 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2025, XM Tech. Co., Ltd.
******************************************************************************
File Name : mpi_sys.h
Version : Initial Draft
Author : XM multimedia software group
Created : 2015/9/17
Description :
******************************************************************************/
#ifndef __MPI_SYS_H__
#define __MPI_SYS_H__
/******************************************/
#ifdef __cplusplus
#if __cplusplus
extern "C"
{
#endif
#endif /* __cplusplus */
#include "xm_common.h"
#include "xm_comm_sys.h"
XM_S32 XM_MPI_SYS_Init(XM_VOID);
/*
** u64Base is the global PTS of the system.
** ADVICE:
** 1. Bester to call XM_MPI_SYS_GetCurPts on the host board to get the u64Base.
** 2. When the linux start up, call XM_MPI_SYS_InitPtsBase to set the init pts.
** 3. When media bussines is running, synchronize the PTS one time per minute.
** And should call XM_MPI_SYS_SyncPts.
*/
/* alloc mmz memory in user context */
XM_S32 XM_MPI_SYS_MmzAlloc(XM_U32 *pu32PhyAddr, XM_VOID **ppVirtAddr,
const XM_CHAR *strMmb, const XM_CHAR *strZone, XM_U32 u32Len);
XM_S32 XM_MPI_SYS_MmzAlloc_Cached(XM_U32 *pu32PhyAddr, void **ppVitAddr,
const XM_CHAR *pstrMmb, const XM_CHAR *pstrZone, XM_U32 u32Len);
/* free mmz memory in user context */
XM_S32 XM_MPI_SYS_MmzFree(XM_U32 u32PhyAddr, XM_VOID *pVirtAddr);
XM_S32 XM_MPI_SYS_MmzFlushCache(XM_U32 u32PhyAddr, XM_VOID *pVirAddr,
XM_U32 u32Size);
/* fulsh cache */
XM_S32 XM_MPI_SYS_MmzFlushCache(XM_U32 u32PhyAddr, XM_VOID *pVirAddr,
XM_U32 u32Size);
/*
** Call the mmap function to map physical address to virtual address
** The system function mmap is too complicated, so we packge it.
*/
XM_VOID * XM_MPI_SYS_Mmap(XM_U32 u32PhyAddr, XM_U32 u32Size);
XM_S32 XM_MPI_SYS_Munmap(XM_VOID* pVirAddr, XM_U32 u32Size);
XM_S32 XM_MPI_SYS_MmzReset(void);
XM_S32 XM_MPI_SYS_Bind(MPP_CHN_S *pstSrcChn, MPP_CHN_S *pstDestChn);
XM_S32 XM_MPI_SYS_UnBind(MPP_CHN_S *pstSrcChn, MPP_CHN_S *pstDestChn);
/******************************************/
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
/******************************************/
#endif /*__MPI_SYS_H__ */

57
general/package/xiongmai-osdrv-xm530/files/include/mpi_vdec.h
View File

@ -1,57 +0,0 @@
/******************************************************************************
Copyright (C), 2018-2025, XM Tech. Co., Ltd.
******************************************************************************
File Name : mpi_vdec.h
Version : Initial Draft
Author : Xm MPP Team
Created : 2018/3/20
Last Modified :
Description : mpi functions declaration
Function List :
History :
******************************************************************************/
#ifndef __MPI_VENC_H__
#define __MPI_VENC_H__
#include "xm_type.h"
#include "xm_common.h"
#include "xm_comm_vdec.h"
#include "xm_comm_video.h"
#ifdef __cplusplus
#if __cplusplus
extern "C"{
#endif
#endif
XM_S32 XM_MPI_VDEC_GetFd(VDEC_CHN VdChn);
XM_S32 XM_MPI_VDEC_ResetChn(VDEC_CHN VdChn);
XM_S32 XM_MPI_VDEC_CreateChn(VDEC_CHN VdChn,VDEC_CHN_ATTR_S *pstAttr);
XM_S32 XM_MPI_VDEC_DestroyChn(VDEC_CHN VdChn);
XM_S32 XM_MPI_VDEC_StartRecvStream(VDEC_CHN VdChn);
XM_S32 XM_MPI_VDEC_StopRecvStream(VDEC_CHN VdChn);
XM_S32 XM_MPI_VDEC_Query(VDEC_CHN VdChn,VDEC_CHN_STAT_S *pstStat);
XM_S32 XM_MPI_VDEC_QueryData(VDEC_CHN VdChn,XM_U32 *pData);
XM_S32 XM_MPI_VDEC_GetChnAttr(VDEC_CHN VdChn,VDEC_CHN_ATTR_S *pstAttr);
XM_S32 XM_MPI_VDEC_SendStream(VDEC_CHN VdChn,VDEC_STREAM_S *pstStream,XM_S32 u32BlockFLag);
XM_S32 XM_MPI_VDEC_SendStream_TimeOut(VDEC_CHN VdChn,VDEC_STREAM_S *pstStream,XM_U32 u32MilliSec);
XM_S32 XM_MPI_VDEC_GetUserData(VDEC_CHN VdChn,VDEC_USERDATA_S *pstData,XM_S32 s32MilliSec);
XM_S32 XM_MPI_VDEC_GetUserData_TimeOut(VDEC_CHN VdChn, VDEC_USERDATA_S *pstData, XM_U32 u32MilliSec);
XM_S32 XM_MPI_VDEC_ReleaseUserData(VDEC_CHN VdChn, VDEC_USERDATA_S *pstData);
XM_S32 XM_MPI_VDEC_GetImage(VDEC_CHN VdChn,VIDEO_FRAME_S *pstFrameInfo,XM_S32 s32MilliSec);
XM_S32 XM_MPI_VDEC_GetImage_TimeOut(VDEC_CHN VdChn, VIDEO_FRAME_INFO_S *pstFrameInfo,XM_U32 u32MilliSec);
XM_S32 XM_MPI_VDEC_ReleaseImage(VDEC_CHN VdChn, VIDEO_FRAME_S *pstFrameInfo);
XM_S32 XM_MPI_VDEC_SetChnParam(VDEC_CHN VdChn, VDEC_CHN_PARAM_S *pstChnParam);
XM_S32 XM_MPI_VDEC_GetChnParam(VDEC_CHN VdChn, VDEC_CHN_PARAM_S *pstChnParam);
XM_S32 XM_MPI_VDEC_Bind(VDEC_CHN VdChn, MPP_CHN_S *pstDestChn);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif

75
general/package/xiongmai-osdrv-xm530/files/include/mpi_venc.h
View File

@ -1,75 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2025, XM Tech. Co., Ltd.
******************************************************************************
File Name : mpi_venc.h
Version : Initial Draft
Author : Xm MPP Team
Created : 2015/8/21
Last Modified :
Description : mpi functions declaration
Function List :
History :
******************************************************************************/
#ifndef __MPI_VENC_H__
#define __MPI_VENC_H__
#include "xm_common.h"
#include "xm_comm_video.h"
#include "xm_comm_venc.h"
#ifdef __cplusplus
#if __cplusplus
extern "C"{
#endif
#endif /* __cplusplus */
//XM_S32 XM_MPI_VENC_InitModule(void);
XM_S32 XM_MPI_VENC_CheckAttr(VENC_CHN VeChn);
XM_S32 XM_MPI_VENC_Init(void);
XM_S32 XM_MPI_VENC_CreateGroup(VENC_GRP VeGroup);
XM_S32 XM_MPI_VENC_DestroyGroup(VENC_GRP VeGroup);
XM_S32 XM_MPI_VENC_CreateChn(VENC_CHN VeChn, const VENC_CHN_ATTR_S *pstAttr);
XM_S32 XM_MPI_VENC_DestroyChn(VENC_CHN VeChn);
XM_S32 XM_MPI_VENC_RegisterChn(VENC_GRP VeGroup, VENC_CHN VeChn );
XM_S32 XM_MPI_VENC_UnRegisterChn(VENC_CHN VeChn);
XM_S32 XM_MPI_VENC_StartRecvPic(VENC_CHN VeChn);
XM_S32 XM_MPI_VENC_StartRecvPicEx(VENC_CHN VeChn, VENC_RECV_PIC_PARAM_S *pstRecvParam);
XM_S32 XM_MPI_VENC_StopRecvPic(VENC_CHN VeChn);
XM_S32 XM_MPI_VENC_Query(VENC_CHN VeChn, VENC_CHN_STAT_S *pstStat);
XM_S32 XM_MPI_VENC_SetChnAttr( VENC_CHN VeChn, const VENC_CHN_ATTR_S *pstAttr);
XM_S32 XM_MPI_VENC_GetChnAttr( VENC_CHN VeChn, VENC_CHN_ATTR_S *pstAttr);
XM_S32 XM_MPI_VENC_SetH264Param(VENC_CHN VeChn, const VENC_CHN_PARAM_S *pstParam);
XM_S32 XM_MPI_VENC_GetH264Param(VENC_CHN VeChn, VENC_CHN_PARAM_S *pstParam);
XM_S32 XM_MPI_VENC_GetStream(VENC_CHN VeChn, VENC_STREAM_S *pstStream, XM_BOOL bBlockFlag);
XM_S32 XM_MPI_VENC_ReleaseStream(VENC_CHN VeChn, VENC_STREAM_S *pstStream);
XM_S32 XM_MPI_VENC_GetFd(VENC_CHN VeChn);
XM_S32 XM_MPI_VENC_RequestIDR(VENC_CHN VeChn);
XM_S32 XM_MPI_VENC_GETRefParamEx(VENC_CHN VeChn,VENC_PARAM_REF_EX_S *pstRefParam);
XM_S32 XM_MPI_VENC_SetRefParamEx(VENC_CHN VeChn,VENC_PARAM_REF_EX_S *pstRefParam);
XM_S32 XM_MPI_VENC_SelectData(void);
XM_S32 XM_MPI_VENC_EncodeJpeg(VIDEO_FRAME_INFO_S const *pframe, JPEG_ENC_ATTR_S *pstAttr, VENC_STREAM_S *pstStream);
XM_S32 XM_MPI_VENC_SetJpegParam(VENC_CHN VeChn, const VENC_PARAM_JPEG_S *pstJpegParam);
XM_S32 XM_MPI_VENC_GetJpegParam(VENC_CHN VeChn, VENC_PARAM_JPEG_S *pstJpegParam);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /* __MPI_VENC_H__ */

51
general/package/xiongmai-osdrv-xm530/files/include/mpi_vi.h
View File

@ -1,51 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2025, XM Tech. Co., Ltd.
******************************************************************************
File Name : mpi_vi.h
Version : Initial Draft
Author : XM multimedia software group
Created : 2015/9/17
Description :
******************************************************************************/
#ifndef __MPI_VI_H__
#define __MPI_VI_H__
#ifdef __cplusplus
#if __cplusplus
extern "C"
{
#endif
#endif /* __cplusplus */
#include "xm_comm_vi.h"
XM_S32 XM_MPI_VI_Init(void);
XM_S32 XM_MPI_VI_SetChnAttr(VI_CHN ViChn, const VI_CHN_ATTR_S *pstAttr);
XM_S32 XM_MPI_VI_GetChnAttr(VI_CHN ViChn, VI_CHN_ATTR_S *pstAttr);
XM_S32 XM_MPI_VI_EnableChn(VI_CHN ViChn);
XM_S32 XM_MPI_VI_DisableChn(VI_CHN ViChn);
XM_S32 XM_MPI_VI_GetFrame(VI_CHN ViChn, VIDEO_FRAME_INFO_S *pstFrameInfo);
XM_S32 XM_MPI_VI_ReleaseFrame(VI_CHN ViChn, VIDEO_FRAME_INFO_S *pstFrameInfo);
XM_S32 XM_MPI_VI_SetExtChnAttr(VI_CHN ViChn, const VI_EXT_CHN_ATTR_S *pstExtChnAttr);
XM_S32 XM_MPI_VI_GetExtChnAttr(VI_CHN ViChn, VI_EXT_CHN_ATTR_S *pstExtChnAttr);
XM_S32 XM_MPI_VI_SetFrmRate(VI_CHN ViChn, XM_U32 srcFrmRate,XM_U32 dstFrmRate);
XM_S32 XM_MPI_VI_Bind(VI_CHN ViChn, MPP_CHN_S *pstDestChn);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /*__MPI_VI_H__ */

99
general/package/xiongmai-osdrv-xm530/files/include/mpi_vo.h
View File

@ -1,99 +0,0 @@
#ifndef __MPI_VO_H__
#define __MPI_VO_H__
#include "xm_comm_vo.h"
#ifdef __cplusplus
#if __cplusplus
extern "C"
{
#endif
#endif /* __cplusplus */
/* Device Settings */
XM_S32 XM_MPI_VO_Init(void);
XM_S32 XM_MPI_VO_SetPubAttr(VO_DEV VoDev, const VO_PUB_ATTR_S *pstPubAttr);
XM_S32 XM_MPI_VO_GetPubAttr(VO_DEV VoDev, VO_PUB_ATTR_S *pstPubAttr);
XM_S32 XM_MPI_VO_Enable (VO_DEV VoDev);
XM_S32 XM_MPI_VO_Disable(VO_DEV VoDev);
/*XM_S32 XM_MPI_VO_CloseFd(XM_VOID);*/
/* General Operation of Channel */
XM_S32 XM_MPI_VO_EnableChn (VO_LAYER VoLayer, VO_CHN VoChn);
XM_S32 XM_MPI_VO_DisableChn(VO_LAYER VoLayer, VO_CHN VoChn);
XM_S32 XM_MPI_VO_SetChnAttr(VO_LAYER VoLayer, VO_CHN VoChn, const VO_CHN_ATTR_S *pstChnAttr);
XM_S32 XM_MPI_VO_GetChnAttr(VO_LAYER VoLayer, VO_CHN VoChn, VO_CHN_ATTR_S *pstChnAttr);
XM_S32 XM_MPI_VO_GetChnFrame(VO_LAYER VoLayer, VO_CHN VoChn, VIDEO_FRAME_INFO_S *pstFrame, XM_S32 s32MilliSec);
XM_S32 XM_MPI_VO_ReleaseChnFrame(VO_LAYER VoLayer, VO_CHN VoChn, const VIDEO_FRAME_INFO_S *pstFrame);
/*XM_S32 XM_MPI_VO_PauseChn (VO_LAYER VoLayer, VO_CHN VoChn);*/
/*XM_S32 XM_MPI_VO_ResumeChn(VO_LAYER VoLayer, VO_CHN VoChn);*/
/*XM_S32 XM_MPI_VO_StepChn(VO_LAYER VoLayer, VO_CHN VoChn);*/
/*XM_S32 XM_MPI_VO_RefreshChn( VO_LAYER VoLayer, VO_CHN VoChn);*/
/*XM_S32 XM_MPI_VO_ShowChn(VO_LAYER VoLayer, VO_CHN VoChn);*/
/*XM_S32 XM_MPI_VO_HideChn(VO_LAYER VoLayer, VO_CHN VoChn);*/
/*XM_S32 XM_MPI_VO_SendFrame(VO_LAYER VoLayer, VO_CHN VoChn, VIDEO_FRAME_INFO_S *pstVFrame, XM_S32 s32MilliSec);*/
/*XM_S32 XM_MPI_VO_ClearChnBuffer(VO_LAYER VoLayer, VO_CHN VoChn, XM_BOOL bClrAll);*/
/*XM_S32 XM_MPI_VO_GetChnRegionLuma(VO_LAYER VoLayer, VO_CHN VoChn, VO_REGION_INFO_S *pstRegionInfo,*/
/*XM_U32 *pu32LumaData, XM_S32 s32MilliSec);*/
/* Cascade setting */
/*XM_S32 XM_MPI_VO_SetCascadeAttr(const VO_CAS_ATTR_S *pstCasAttr);*/
/*XM_S32 XM_MPI_VO_GetCascadeAttr(VO_CAS_ATTR_S *pstCasAttr);*/
/*XM_S32 XM_MPI_VO_EnableCascadeDev (VO_DEV VoCasDev);*/
/*XM_S32 XM_MPI_VO_DisableCascadeDev(VO_DEV VoCasDev);*/
/*XM_S32 XM_MPI_VO_SetCascadePattern(VO_DEV VoCasDev, XM_U32 u32Pattern);*/
/*XM_S32 XM_MPI_VO_GetCascadePattern(VO_DEV VoCasDev, XM_U32 *pu32Pattern);*/
/*XM_S32 XM_MPI_VO_CascadePosBindChn(XM_U32 u32Pos, VO_DEV VoCasDev, VO_CHN VoChn);*/
/*XM_S32 XM_MPI_VO_CascadePosUnBindChn(XM_U32 u32Pos, VO_DEV VoCasDev, VO_CHN VoChn);*/
/*XM_S32 XM_MPI_VO_EnableCascade (XM_VOID);*/
/*XM_S32 XM_MPI_VO_DisableCascade(XM_VOID);*/
/* VGA setting */
/*XM_S32 XM_MPI_VO_GetVgaParam(VO_DEV VoDev, VO_VGA_PARAM_S *pstVgaParam);*/
/*XM_S32 XM_MPI_VO_SetVgaParam(VO_DEV VoDev, VO_VGA_PARAM_S *pstVgaParam);*/
/*XM_S32 XM_MPI_VO_SetDevFrameRate(VO_DEV VoDev, XM_U32 u32FrameRate);*/
/*XM_S32 XM_MPI_VO_GetDevFrameRate(VO_DEV VoDev, XM_U32 *pu32FrameRate);*/
/*XM_S32 XM_MPI_VO_EnableRecvFrameRateMatch (VO_LAYER VoLayer, VO_CHN VoChn);*/
/*XM_S32 XM_MPI_VO_DisableRecvFrameRateMatch (VO_LAYER VoLayer, VO_CHN VoChn);*/
/* HDMI setting */
/*XM_S32 XM_MPI_VO_GetHdmiParam(VO_DEV VoDev, VO_HDMI_PARAM_S *pstHdmiParam);*/
/*XM_S32 XM_MPI_VO_SetHdmiParam(VO_DEV VoDev, VO_HDMI_PARAM_S *pstHdmiParam);*/
/*XM_S32 XM_MPI_VO_SetVtth(VO_DEV VoDev, XM_U32 u32Vtth);*/
/*XM_S32 XM_MPI_VO_GetVtth(VO_DEV VoDev, XM_U32* pu32Vtth);*/
XM_S32 XM_MPI_VO_SetImageLayerAttr(VO_LAYER VoLayer, const VO_IMAGE_LAYER_ATTR_S *pstLayerAttr);
XM_S32 XM_MPI_VO_GetImageLayerAttr(VO_LAYER VoLayer, const VO_IMAGE_LAYER_ATTR_S *pstLayerAttr);
XM_S32 XM_MPI_VO_EnableImageLayer(VO_LAYER VoLayer);
XM_S32 XM_MPI_VO_DisableImageLayer(VO_LAYER VoLayer);
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /*__MPI_VO_H__ */

98
general/package/xiongmai-osdrv-xm530/files/include/xm/BlindDetect.h
View File

@ -1,98 +0,0 @@
//
// "$Id: BlindDetect.h 4 2009-06-11 13:01:43Z liwj $"
//
// Copyright (c)2008-2008, ZheJiang JuFeng Technology Stock CO.LTD.
// All Rights Reserved.
//
// Description:
// Revisions: Year-Month-Day SVN-Author Modification
//
#ifndef __PAL_BLINDDETECT_H__
#define __PAL_BLINDDETECT_H__
#ifdef __cplusplus
extern "C" {
#endif
/// \defgroup BlindDetectAPI API Blind Detect
/// 全屏范围按灵敏度的遮挡检测接口。
/// \n 调用流程图:
/// \code
/// ===========================
/// |
/// *BlindDetectGetCaps
/// |
/// BlindDetectCreate
/// +-----------|
/// | BlindDetectGetState
/// | BlindDetectSetParameter
/// +-----------|
/// BlindDetectDestory
/// |
/// ===========================
/// \endcode
/// @{
/// 黑屏检测设备特性结构
typedef struct BLIND_DETECT_CAPS
{
unsigned int Enabled; ///< 置1表示支持黑屏检测，置0表示不支持黑屏检测。
}BLIND_DETECT_CAPS;
/// 黑屏检测参数
typedef struct BLIND_DETECT_PARAM
{
unsigned char Level; ///< 等级 0 - 3 // 0 - 30
int Enable; ///< 为1表示使能，为0时表示禁用
}BLIND_DETECT_PARAM;
/// 创建黑屏检测设备
///
/// \param 无
/// \retval <0 创建失败
/// \retval 0 创建成功
int BlindDetectCreate(void);
/// 销毁黑屏检测设备
///
/// \param 无
/// \retval <0 销毁失败
/// \retval 0 销毁成功
int BlindDetectDestory(void);
/// 执行黑屏检测。立即返回。
///
/// \param [out] pData 指向一个unsigned int值的指针，unsigned int值是各个报警输入通道电平状态的
/// 掩码。低通道在低位，高通道在高位。高电平置1，低电平置0，不存在的通道置0。
/// \retval 0 检测成功
/// \retval <0 检测失败
int BlindDetectGetState(unsigned int* pData);
/// 设置黑屏检测捕获的参数。
///
/// \param [in] channel 通道号。
/// \param [in] pParam 指向黑屏检测参数结构BLIND_DETECT_ Param的指针。
/// \retval 0 设置成功
/// \retval <0 设置失败
int BlindDetectSetParameter(int channel, BLIND_DETECT_PARAM *pParam);
/// 得到黑屏支持的特性。
///
/// \param [out] pCaps 指向黑屏特性结构BLIND_DETECT _CAPS的指针。
/// \retval 0 获取成功。
/// \retval <0 获取失败。
int BlindDetectGetCaps(BLIND_DETECT_CAPS * pCaps);
/// @} end of group
#ifdef __cplusplus
}
#endif
#endif

1085
general/package/xiongmai-osdrv-xm530/files/include/xm/Camera.h
View File

File diff suppressed because it is too large Load Diff

48
general/package/xiongmai-osdrv-xm530/files/include/xm/DVRAPI.h
View File

@ -1,48 +0,0 @@
#ifndef _DVRAPI_H_
#define _DVRAPI_H_
/// 捕获分辨率类型
/// \note更新下面这个结构时，要同步更新Record.cpp里验证编码能力
typedef enum capture_size_t {
CAPTURE_SIZE_D1, ///< 720*576(PAL) 720*480(NTSC)
CAPTURE_SIZE_HD1, ///< 352*576(PAL) 352*480(NTSC)
CAPTURE_SIZE_BCIF, ///< 720*288(PAL) 720*240(NTSC)
CAPTURE_SIZE_CIF, ///< 352*288(PAL) 352*240(NTSC)
CAPTURE_SIZE_QCIF, ///< 176*144(PAL) 176*120(NTSC)
CAPTURE_SIZE_VGA, ///< 640*480(PAL) 640*480(NTSC)
CAPTURE_SIZE_QVGA, ///< 320*240(PAL) 320*240(NTSC)
CAPTURE_SIZE_SVCD, ///< 480*480(PAL) 480*480(NTSC)
CAPTURE_SIZE_QQVGA, ///< 160*128(PAL) 160*128(NTSC)
CAPTURE_SIZE_NR = 9, ///< 等临时处理等底层一起修改
CAPTURE_SIZE_ND1 = 9, ///< 240*192
CAPTURE_SIZE_650TVL, ///< 928*576
CAPTURE_SIZE_720P, ///< 1280*720
CAPTURE_SIZE_1_3M, ///< 1280*960
CAPTURE_SIZE_UXGA , ///< 1600*1200
CAPTURE_SIZE_1080P, ///< 1920*1080
CAPTURE_SIZE_WUXGA, ///< 1920*1200
CAPTURE_SIZE_2_5M, ///< 1872*1408
CAPTURE_SIZE_3M, ///< 2048*1536
CAPTURE_SIZE_5M, ///< 3744*1408
CAPTURE_SIZE_EXT_NR =19, ///< 枚举的图形大小种类的数目。
CAPTURE_SIZE_1080N = 19, ///< 960*1080
CAPTURE_SIZE_4M, ///< 2592*1520
CAPTURE_SIZE_6M, ///< 3072×2048
CAPTURE_SIZE_8M, ///< 3264×2448
CAPTURE_SIZE_12M, ///< 4000*3000
CAPTURE_SIZE_4K, ///< 4096 * 2160通用/3840*2160海思
CAPTURE_SIZE_EXT_V2_NR=25, ///< 枚举的图形大小种类的数目。
CAPTURE_SIZE_720N = 25, // 640*720
CAPTURE_SIZE_RES1, // 0*0 冗余
CAPTRUE_SIZE_RES2, // 0*0
CAPTURE_SIZE_RES3, // 0*0
CAPTURE_SIZE_RES4, // 0*0
CAPTURE_SIZE_RES5, // 0*0
CAPTURE_SIZE_RES6, // 0*0
CAPTURE_SIZE_EXT_V3_NR,
}CAPTURE_SIZE_T;
#endif

1216
general/package/xiongmai-osdrv-xm530/files/include/xm/IspTools.h
View File

File diff suppressed because it is too large Load Diff

1095
general/package/xiongmai-osdrv-xm530/files/include/xm/IspToolsFlash.h
View File

File diff suppressed because it is too large Load Diff

148
general/package/xiongmai-osdrv-xm530/files/include/xm/MotionDetect.h
View File

@ -1,148 +0,0 @@
//
// "$Id: MotionDetect.h 4 2009-06-11 13:01:43Z liwj $"
//
// Copyright (c)2008-2008, ZheJiang JuFeng Technology Stock CO.LTD.
// All Rights Reserved.
//
// Description:
// Revisions: Year-Month-Day SVN-Author Modification
//
#ifndef __PAL_MOTIONDETECT_H__
#define __PAL_MOTIONDETECT_H__
#ifdef __cplusplus
extern "C" {
#endif
/// \defgroup MotionDetectAPI API Motion Detect
/// 按区域和灵敏度的动态检测接口。
/// \n 调用流程图:
/// \code
/// ============================
/// |
/// *MotionDetectGetCaps
/// |
/// MotionDetectCreate
/// +------------|
/// | MotionDetectGetState
/// | MotionDetectSetParameter
/// | MotionDetectGetResult
/// | MotionDetectShowHint
/// +------------|
/// MotionDetectDestory
/// |
/// ============================
/// \endcode
/// @{
/// 动态检测参数
typedef struct MOTION_DETECT_PARAM
{
/// 动态检测的敏感度档次
int iLevel;
/// 动态检测的区域，数据的每一位对应一个矩形区域块，置1表示需要在该区域块动
/// 态检测，置0表示不需要在该区域块动态检测。每一行用一个unsigned int表示，最左边的
/// 块对应最低位，从上到下的行对应的下标从0到17。支持的行列数之外对应的数据
/// 位无效。
unsigned int win[18];
/// 灵敏度的具体值
unsigned char sensitiveness;
/// 帧间隔
unsigned char fieldinterval;
/// 使能开关，是否使能，为1表示使能，为0时表示禁用，其他参数被忽略。
int enable;
}MOTION_DETECT_PARAM;
/// 动态检测结果
typedef struct MOTION_DETECT_RESULT
{
/// 有动态检测发生的区域，数据的每一位对应一个矩形区域块，置1表示在该区域块
/// 动态检测成功，置0表示该区域块动态检测失败。每一行用一个unsigned int表示，最左边
/// 的块在最高位，从上到下的行对应的下标从0到17。支持的行列数之外对应的数据
/// 位无效。
unsigned int win[18];
}MOTION_DETECT_RESULT;
/// 视频动态检测特性结构
typedef struct MOTION_DETECT_CAPS
{
unsigned int Enabled; ///< 置1表示支持动态检测，置0表示不支持动态检测。
unsigned int GridLines; ///< 动态检测的区域需要划分成的列数。
unsigned int GridRows; ///< 动态检测的区域需要划分成的行数。
unsigned char Result; ///< 是否能得到每块区域的检测结果。
unsigned char Hint; ///< 是否能在检测成功时给予提示。
}MOTION_DETECT_CAPS;
/// 创建动态检测设备
///
/// \param 无
/// \retval <0 创建失败
/// \retval 0 创建成功
int MotionDetectCreate(void);
/// 销毁动态检测设备
///
/// \param 无
/// \retval <0 销毁失败
/// \retval 0 销毁成功
int MotionDetectDestory(void);
/// 执行动态检测。立即返回。
///
/// \param [out] pData 指向一个unsigned int值的指针，unsigned int值是各个报警输入通道电平状态
/// 的掩码。低通道在低位，高通道在高位。高电平置1，低电平置0，不存在的通
/// 道置0。
/// \retval 0 检测成功
/// \retval <0 检测失败
int MotionDetectGetState(unsigned int* pData);
/// 动态检测捕获的详细结果。
///
/// \param [in] channel 通道号。
/// \param [in] pResult 指向动态检测参数结构MOTION_DETECT_RESULT的指针。
/// \retval 0 设置成功
/// \retval <0 设置失败
int MotionDetectGetResult(int channel, MOTION_DETECT_RESULT *pResult);
/// 设置是否在动态检测成功的区域给予提示。
///
/// \param [in] channel 通道号。
/// \param [in] enable 为1表示提示，为0时表示不提示。
/// \retval 0 设置成功
/// \retval <0 设置失败
int MotionDetectShowHint(int channel, int enable);
/// 执行动态检测。立即返回。
///
/// \param [in] channel 通道号。
/// \param [in] pParam 指向动态检测参数结构MOTION_DETECT_PARAM的指针。
/// \retval 0 设置成功
/// \retval <0 设置失败
int MotionDetectSetParameter(int channel, MOTION_DETECT_PARAM *pParam);
/// 得到动态检测支持的特性。
///
/// \param [out] pCaps 指向动态检测特性结构MOTION_DETECT_CAPS的指针。
/// \retval 0 获取成功。
/// \retval <0 获取失败。
int MotionDetectGetCaps(MOTION_DETECT_CAPS * pCaps);
/// @} end of group
#ifdef __cplusplus
}
#endif
#endif

29
general/package/xiongmai-osdrv-xm530/files/include/xm/Types.h
View File

@ -1,29 +0,0 @@
#ifndef _TYPES_H_
#define _TYPES_H_
#include "BlindDetect.h"
#include "MotionDetect.h"
#include "xm_type.h"
typedef struct _stvda_date_
{
// Motion
MOTION_DETECT_CAPS stMotionPar;
XM_U8 u8MotionStatus;
// Blind
BLIND_DETECT_PARAM stBlindPar;
XM_U8 u8BlindStatus;
}stVDA_DATE;
extern stVDA_DATE gstVdaDate;
extern int get_dvr_hwinfo(int info_cmd,void *val);
#define HWID_VGA_CHIP (0x59)
#endif

138
general/package/xiongmai-osdrv-xm530/files/include/xm/com.h
View File

@ -1,138 +0,0 @@
/*********************************************************************
Copyright (C), 2015-8-26, JuFeng.Tech. Co., Ltd.
File name: com.h
Author:
Versoin: 1.00
Data: 2015-08-26
Desc: 串口源文件，实现串口通信
Ohters: // 其他说明
Function List:
**********************************************************************/
#ifndef __COM_H__
#define __COM_H__
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#define uint8 unsigned char
#define uint32 unsigned int
#define uint16 unsigned short
#define ISP_USED (0)
#define UART_0 (0)
#define COM_TimeOut0 (0x00000001)
#define COM_TimeOut1 (0x00010000)
typedef enum {
E_RECV_OK,
E_RECV_TIMEOUT
}eCOMERR;
#define TRUE 1
#define FALSE 0
/**************************** 调用函数库声明 *******************************/
/*
指令定义
*/
#define COM_CMDLEN 13 //( AA BB CC CC CC CC DD DD DD DD xx xx xx)
// 串口处理模式
#define CMD_DEBUGMODE 0XFE
#define CMD_BOOTMODE 0x95
#define CMD_VISCAMIN_MODE 0x80
#define CMD_VISCAMAX_MODE 0x8F
/***** DEBUG 模式指令定义 *****/
#define CMD_DEBUG_REGWRTIE 0x05
#define CMD_DEBUG_REGREAD 0x06
#define CMD_SENSOR_WRITE 0x07
#define CMD_SENSOR_READ 0x08
#define CMD_MOTOR_WRITE 0x09
#define CMD_MOTOR_READ 0x0A
#define CMD_SPI_WRITE 0x0B
#define CMD_SPI_READ 0x0C
#define CMD_FLASH_WRITE 0x0F
#define CMD_FLASH_READ 0x10
#define CMD_DEBUG_FLASHWRTIE 0x0aa //0x
#define CMD_DEBUG_FLASHREAD 0x0ab
#define CMD_DEBUG_FLASHERASE 0x0ac
#define CMD_DEBUG_TIMEOUTPARA_SET 0x01A
#define CMD_DEBUG_FLASHPARA_SET 0x01B
#define CMD_DEBUG_BAUDRATE_SET 0x01C
#define CMD_DEBUG_BOOTMODE_EN_SET 0x0D
#define CMD_DEBUG_FLASHPRO_SET 0x0E
#define CMD_DEBUG_AHD 0x5a
/*
UART 调试：
1、REG 读写；
2、FLASH byte读写(带校验， 使能)；
3、FLASH BLOCK ERASE(带校验, 使能)；
4、各模块超时变量查询及设置(带校验)；
5、FLASH 类型设置（操作指令可设置）(带校验)；
6、波特率设置(带校验)（默认波特率9600）;
7、UART BootLoader模式使能；（上位机控制）(带校验)；
8、FLASH写保护功能（由上位机控制）(带校验)；
保护为chip protect;
分断电记忆和断电不记忆两种；
*/
/***** bootloader 模式定义 *****/
#define CMD_BOOT_FLASH_WRITE 0x22
#define CMD_BOOT_FLASH_READ 0x42
#define CMD_BOOT_FLASH_CHECKSUM 0x52
#define CMD_BOOT_FLASH_BLANKCHECK 0x62
#define CMD_BOOT_FLASH_ERASE 0x82
#define CMD_BOOT_CHIP_ERASE 0xA2
/******************变量声明**************************/
/******************函数声明**************************/
void Com_Debugprocess_Anomaly(uint8 uart_NO);
void Com_FlashProcess(uint8 uart_NO);
uint8 getbyte(uint32 timeout);
void ISR_UART0(void);
void putdword(unsigned char ComNum, unsigned int c);
#endif

440
general/package/xiongmai-osdrv-xm530/files/include/xm/extCfg.h
View File

@ -1,440 +0,0 @@
#ifndef _EXTCFG_H_
#define _EXTCFG_H_
#define DEBUG_ON (1)
//#define RES_960 (1)
#include "xm_type.h"
#include "xm_common.h"
#include "xm_comm_isp.h"
#define FUN_NUM (35)
#define BUFFER_START (0x800)
#define ROM_BASE (0x32000)
#define MARK_ID (0xA55A5AA5)
#define MARK_ID_TO_SYS (0xA55A5AB5)
// 公用模块地址
#define ROM_COM_MARK (0)
#define ROM_MD_VER (4)
#define ROM_MD_SNSNUM (7)
#define ROM_MD_SNSBASE (8)
#define COM_FUN_REG_F (0)
#define COM_FUN_REG_B (1)
#define COM_FUN_MENU (2)
// 模块内的地址偏移(基于每个sensor配置起始点) gau32SnsBaseAddr
#define ROM_OFST_SNSID (0)
#define ROM_OFST_FUNMASK (1)
#define ROM_OFST_SNSI2C (5)
#define ROM_OFST_ISPCUT (9)
#define ROM_OFST_SNSCHECK (21)
// Sensor I2C
#define I2C_OFST_RESOLUTION (3)
// ISP CUT
#define ISPCUT_OFST_X_PAL (0)
#define ISPCUT_OFST_Y_PAL (2)
#define ISPCUT_OFST_WIDHT (4)
#define ISPCUT_OFST_HEIGHT (6)
#define SUPPORT_NUM (8)
#define ROM_FUN_SNSI2C (0)
#define ROM_FUN_ISPCUT (1)
#define ROM_FUN_ISPINIT_FRONT (2)
#define ROM_FUN_SNSINIT (3)
#define ROM_FUN_FPS (4)
#define ROM_FUN_MF (5)
#define ROM_FUN_AEDEF (6)
#define ROM_FUN_TABAGAIN (7)
#define ROM_FUN_TABDGAIN (8)
#define ROM_FUN_UPDATEGAIN (9)
#define ROM_FUN_UPDATESHUT (10)
#define ROM_FUN_ISPINIT (11)
#define ROM_FUN_PN_ISPSET (12)
#define ROM_FUN_AWB (13)
#define ROM_FUN_CCM (14)
#define ROM_FUN_SHARP (15)
#define ROM_FUN_2DNR (16)
#define ROM_FUN_3DNR (17)
#define ROM_FUN_DYDPC (18)
#define ROM_FUN_BLC (19)
#define ROM_FUN_CON (20)
#define ROM_FUN_SAT (21)
#define ROM_FUN_CHROMA (22)
#define ROM_FUN_AFC (23)
#define ROM_FUN_NR3D (24)
#define ROM_FUN_GAMMATAB (25)
#define ROM_FUN_LUM (26)
#define ROM_FUN_OTHER (27)
#define ROM_FUN_GAINMODE (28)
#define ROM_FUN_VENC (29)
#define ROM_FUN_AEAWBINIT (30)
#define ROM_FUN_AEAWBINFO (31)
#define ROM_FUN_STABDEAL (32)
#define ROM_FUN_GAINLOGIC (33)
#define ROM_FUN_SHUTLOGIC (34)
typedef enum {
// SmartSns
SMS_LINE = 0x10,
SMS_TAB = 0x11, // 标准查表
SMS_TAB1 = 0x15, // +带高温逻辑
SMS_TAB2 = 0x19, // +带增益逻辑
SMS_TAB3 = 0x1D, // +带高温、增益逻辑
//晶像
SOI_TAB = 0x21, //
// Sony
SONY_TAB = 0x31, //
// Ov
OV_LINE = 0x40, // 线性
OV_TAB = 0x41, // 查表
// Ps
PS_LINE = 0x50,
} GAIN_MODE_TYPE;
typedef struct _gamma_data_dn_s
{
XM_U8 u8Num; // <= 3 gamma条数
XM_U8 au8Idx[3]; // =u8Num
XM_U32 au32Exp[2]; // =u8Num-1
XM_U32 u32ThrDlt;
}GAMMA_DATA_DN_S;
typedef struct _lum_data_dn_s
{
XM_U8 u8Num; // <= 4
XM_U8 au8Lum[3]; // =u8Num
XM_U32 au32Exp[3]; // =u8Num
}LUM_DATA_DN_S;
typedef struct _other_data_s
{
XM_U8 u8Size;
XM_U8 u8Gain50;
XM_U8 u8Gain100;
XM_U8 u8CscLum;
XM_U8 u8CscSat;
XM_U8 u8CscContrast;
XM_U8 u8CscHue;
XM_U8 u8FlipMirror;
XM_U8 u8VencVstd;
XM_U8 u8Rslt; // 0xFF: 由内部决定
XM_U8 u8Rsv[6];
}OHTER_DATA_S;
// 高温逻辑(和线性模式共用变量)
typedef struct _HT_LOGIC_DT
{
XM_U8 u8En;
XM_U8 u8MinGain;
XM_U16 u16Reg[2]; // L H
XM_U32 u32LimitUp;
XM_U32 u32LimitDn;
/************************************************
线性模式时
XM_U8 u8AgainSft; // Again cal中移位(高4位<；低4位>)
XM_U8 u8AgainMin; // 最小增益
XM_U16 u16Rsv[2]; // 无意义
XM_U32 u32Rsv1; // 无意义
XM_U32 u32Rsv2; // 无意义
************************************************/
}HT_LOGIC_DT;
typedef struct _OV_AE_DATA
{
XM_U32 u32Hold;
XM_U32 u32Again;
XM_U32 u32Dgain;
XM_U32 u32Blc;
}AE_OV_TAB_DT;
typedef struct _AE_LINEAR_DT
{
XM_U8 u8AgainSft; // Again cal中移位(高4位<；低4位>)
XM_U8 u8AgainMin; // 最小增益
}AE_LINEAR_DT;
typedef union _GAIN_MODE_DT_U
{
HT_LOGIC_DT stHtLgc; // SmartSns 高温逻辑
AE_LINEAR_DT stLinear; // 线性增益
AE_OV_TAB_DT stOvTab; // OV
}GAIN_MODE_DT;
typedef struct xm_AE_INIT_S
{
XM_U8 u8Speed;
XM_U8 u8Tolerance;
XM_U8 u8Speed_Stab;
XM_U8 u8Tolerance_Stab;
XM_U32 u32UpdateCfg_Stab;
XM_U8 u8AntiFlicker;
XM_U8 u8AntiFlicker_Freq;
XM_U8 u8BlackDelayFrame;
XM_U8 u8WhiteDelayFrame;
XM_U8 u8ExpMode; // 0: Auto 1:Manual
XM_U32 u32ExpManual;
XM_U32 u32MinAGain;
XM_U32 u32MaxAGain;
XM_U32 u32MinDGain;
XM_U32 u32MaxDGain;
XM_U32 u32MinIspDGain;
XM_U32 u32MaxIspDGain;
}AE_INIT_S;
typedef struct xm_AWB_INIT_S
{
XM_U8 u8HighColorTemp;
XM_U8 u8LowColorTemp;
}AWB_INIT_S;
typedef struct xm_NR3D_INIT_S
{
XM_U8 u8Size;
XM_U8 u8FrameCnt;
XM_U8 u8Ctrl;
XM_U16 u16Width;
XM_U16 u16Height;
XM_U16 u16ChangePoint;
XM_U32 u32PhyAddr;
XM_U32 u32BaseAddr[8];
XM_U32 u32YAddr;
XM_U32 u32ErrAddr;
}NR3D_INIT_S;
typedef struct xm_STABDEAL_S
{
XM_U8 u8Size;
XM_U8 u8DealAfterStab;
XM_U16 u16FmRunNum;
XM_U16 u16StabFmID;
XM_U8 u8IspRegNum;
XM_U32 u32IspAddrData;
}STABDEAL_S;
XM_S32 ExtCfg_BaseAddrGet(XM_U8 u8Sns, XM_U32 u32Module, XM_U32 *pu32Addr);
XM_S32 ExtCft_Init();
//返回值: 0: 匹配上了 -1: 没有匹配上
XM_S32 ExtCfg_IsLock();
/************************************************************************
函数功能: 根据SensorID 获取外部配置文件该sensor索引
输入参数: u8SnsID: 目标sensor ID
输出参数: *pu8SnsIdx 在配置文件中索引
返回参数: 0: 存在该sensor
-1: 不存在该sensor
************************************************************************/
XM_S32 ExtCft_GetSnsIdx(XM_U8 u8SnsID,XM_U8 *pu8SnsIdx);
// 设置sensor 的索引 (确认匹配上Sensor)
XM_S32 ExtCfg_SetSnsIdx(XM_U8 u8SnsIdx, XM_U8 u8SnsAdWidth,XM_U8 u8SnsDtWidth);
// 获取SensorID
XM_S32 ExtCft_GetSnsId(XM_U8 *pu8SnsId);
// 获取配置文件中的Sensor个数
XM_S32 ExtCft_GetSnsNum(XM_U8 *pu8Num);
/*********************************************************
函数功能: 获取ISP裁剪参数
输入参数: u8Fps: 帧率模式(25/30/50/60)
输出参数: pstRect:
ISP裁剪参数
返回参数: -1: 不支持
0: 支持
*********************************************************/
XM_S32 ExtCft_GetIspWndRect(XM_U8 u8Fps,RECT_S* pstRect);
//获取分辨率
XM_S32 ExtCft_GetSnsResolution(XM_U8 *pu8Res);
//u8Mode: 0: Common Funciton
// 1: Sensor Function
//验证是否支持该功能(功能是否使用外部配置)
XM_S32 ExtCfg_CheckFun(XM_U8 u8Mode, XM_U32 u32Fun);
XM_S32 ExtCfg_PN_IspSet(XM_U8 u8Encode, XM_U8 u8VstdMode);
//u8DnMode: 0: Color 1:BW
//u8XviEn: 0:Disable 1:Enable
XM_S32 ExtCfg_SetMode(XM_U8 u8XviEn, XM_U8 u8DnMode);
XM_S32 ExtCfg_IspInit();
/************************************************************************
函数功能: 获取Gamma 参数
输入参数: *pu8Mode: 0:Color 1:Bw
输出参数: *pu8Mode
0: 死区 1:过渡
*pstGamm:
对应模式(Color/Bw)的参数
注: 每个模式Gamma最大 3条
************************************************************************/
XM_S32 ExtCfg_Gamma_Get(XM_U8 *pu8Mode,GAMMA_DATA_DN_S*pstGamm);
/************************************************************************
函数功能: 获取GammaTable
输入参数: u8GmId: ID(第u8GmId - 0x40 条)
输出参数: *pu16Tab:
Gamma表
注:
u8GmId>= 0x40
************************************************************************/
XM_S32 ExtCfg_GammaTab_Get(XM_U8 u8GmId,XM_U16 *pu16Tab);
/************************************************************************
函数功能: 获取lum参数
输入参数: 无
输出参数: 无
返回参数: -1: 不支持
其他: 亮度值
************************************************************************/
XM_S32 ExtCfg_Lum_Get();
// 获取Other参数
XM_S32 ExtCfg_Other_Get(OHTER_DATA_S *pstData);
// 初始化ISP 寄存器
XM_S32 ExtCfg_IspRegInit(XM_U8 u8Mode);
//u8DnMode: 0: Color 1:BW
//u8XviEn: 0:Disable 1:Enable
XM_S32 ExtCfg_SetMode(XM_U8 u8XviEn, XM_U8 u8DnMode);
//从Flash/E2PROM中读取
XM_S32 ExtCfg_Read_V2(XM_U8 u8Bytes, XM_U32 u32Add,XM_U8 *pu8Data);
XM_S32 ExtCfg_Write_V2(XM_U16 u16Bytes, XM_U32 u32Add,XM_U8 *pu8Data);
//写入Flash/E2PROM
XM_S32 ExtCfg_Write(XM_U8 u8Bytes, XM_U32 u32Addr,XM_U8 *pu8Data);
//函数功能: 从配置文件读取数据 写入Isp寄存器
//u32Addr: 数据起始地址(配置文件)
//u8Num: 寄存器个数
//u8Mode: 0:Read From E2 1:Read From RAM
XM_S32 ExtCft_WriteIsp(XM_U8 u8Mode, XM_U32 u32Addr, XM_U16 u16Num);
/************************************************************************
函数功能: ExtCft_GainModeGet
输入参数: u8Mode:
0: 获取GainMode
1: 获取GainLogic地址
输出参数: *pu32Data:
GainMode (u8Mode == 0)
GainLogic BaseAddr (u8Mode == 1)
返回参数: -1: failed/ not exist
0: Ok/exit
************************************************************************/
XM_S32 ExtCft_GainModeGet(XM_U8 u8Mode, XM_U32 *pu32Data);
/***********************************************************************
函数名称: ExtCft_GetVersion
函数功能: 获取外部配置版本信息
输入参数: 无
输出参数: 指向3个字节的buffer 地址
年(1Byte)
月(1Byte)
日(1Byte)
返回参数: 0: 成功
-1: 出错
Note:Lycai
***********************************************************************/
XM_S32 ExtCft_GetVersion(XM_U8 *pau8Data);
/***********************************************************************
函数名称: ExtCfg_VencSet
函数功能: 不同编码、视频支持进行外部配置参数
输入参数: u8VencMode: 当前制式
bit0: AHD_PAL
bit1: AHD_NTSC
bit2: CVI_PAL
bit3: CVI_NTSC
bit4: TVI_PAL
bit5: TVI_NTSC
bit6: CVBS_PAL
bit7: CVBS_NTSC
输出参数: 无
返回参数: 0: 成功
-1: 出错
Note:Lycai
***********************************************************************/
XM_S32 ExtCfg_VencSet(XM_U8 u8VencMode);
XM_S32 ExtCfg_Read_RAM(XM_U8 u8Bytes, XM_U32 u32Add,XM_U8 *pu8Data);
XM_S32 ExtCfg_CCM_Set(ISP_COLORMATRIX_AUTO_S *pstCCM);
XM_S32 ExtCfg_IspDataInit(XM_U8 u8Venc, XM_U8 u8Std);
XM_S32 ExtCfg_Init(XM_U8 *pu8Buffer);
XM_S32 ExtCfg_Nr3DInit(NR3D_INIT_S *pstNr3D);
XM_S32 ExtCfg_StabDeal(STABDEAL_S *pstStabDeal);
XM_S32 ExtCfg_AeAwbInit(XM_U8 u8Mode, XM_U8 u8Vstd);
/***********************************************************************
函数名称: ExtCfg_GetExtCfgFlg
函数功能: 判断是否需要配置
输入参数: 无
输出参数: 无
返回参数: 0: 不用配置(前面(ROM)已配置过)
1: 需要配置(前面未配置过)
2: 需要配置(无配置表)
-1: 出错
Note:Lycai
ROM 和ISP不能重复配置部分配置前判断
***********************************************************************/
XM_S32 ExtCfg_GetExtCfgFlg();
void PrintInt(unsigned char u8Num,int u32Data);
void PrintHex(unsigned char u8Num,int u32Data);
#endif

190
general/package/xiongmai-osdrv-xm530/files/include/xm/ispMsg.h
View File

@ -1,190 +0,0 @@
/*
**********************************************************************************
**Camera.c
**XM510/XM540
**
**(c) Copyright HZXM
**All Rights Reserved
**
**File : ispMsg.h
**Description : API to application
**Modify : 2015-01 Lycai Create the file
**********************************************************************************
*/
#ifndef _ISP_MSG_H_
#define _ISP_MSG_H_
#ifdef SOC_SYSTEM
#include <sys/ipc.h>
#include <sys/shm.h>
#include <sys/msg.h>
#include <sys/types.h>
#endif
#include "xm_type.h"
typedef enum {
C_EXP_LEVEL = 0,
C_DN_MODE = 1,
C_BLC_MODE = 2,
C_SCENE_MODE = 3,
C_AE_TGT = 4,
C_DN_THR = 5,
C_DWDR = 6,
C_AE_SENS = 7,
C_DN_SENS = 8,
C_IMG_STYLE = 9,
C_AUTO_GAIN = 10,
C_EE_SHUTTER = 11,
C_IRMODE = 12,
C_NR_DAY = 13,
C_NR_NIGHT = 14,
C_DEBUG = 15,
C_SAVE = 16,
C_MIRROR = 17,
C_FLIP = 18,
C_DEFLIKER = 19,
C_IRSWAP = 20,
C_SETCOLOR = 21,
C_VSTD = 22,
C_IR_STATUS = 23,
E_FORMAT = 24,
C_LEDMODE = 25,
C_LEDTYPE = 26,
C_SNAP = 27,
C_AE_WEIGHT = 28, // 焦点（人形）防过曝使能
C_GPIO_SET = 29,
C_AUTO_IRIS = 30,
C_SOFTIR_LVL = 31,
C_DEFOG = 32,
C_INFRARED_SWAP = 33,
VDA_MDOD = 48,
VDAM_MDOD = 49,
BLIND_DETECT = 50,
E_LIGHT_CTRL = 51,
E_COORD = 52,
IAPED_INFO = 60,
IAPG_INFO = 61,
E_PRODUCT = 255,
} CAMERA_SETTINT;
typedef enum {
VDA_CREAT = 1,
VDA_DESTORY ,
VDA_GETSTATE,
VDA_SETPARAMETER,
VDA_GETCAPS,
}CAMERA_VDACMD_MODE;
typedef enum {
MSG_WRITE = 1,
MSG_READ = 2,
MSG_ACK = 3,
} CAMERA_SETTINT_MODE;
typedef struct _xm_msg_data_
{
XM_S32 s32Cmd;
XM_S32 s32Mode;
XM_S32 s32DataNum;
XM_S32 s32Data[32];
}XM_MSG_DATA;
typedef struct _xm_msg_
{
char as8Head[4];
XM_MSG_DATA stData;
char term_path[32]; //当前运行2asndmsg 命令的终端名
}XM_MSG;
//白天黑夜降噪等级
typedef struct _nf_lenvl
{
XM_S32 day_level;
XM_S32 night_level;
}sNF_LEVEL;
typedef struct exposure_paramer
{
XM_U32 u32TimeMode;
XM_U32 u32TimeMax;
XM_U32 u32TimeMin;
XM_U32 u32GainMode;
XM_U32 u32GainLevel;
XM_U8 u8ExposureMode; // 0:自动曝光 1: 手动曝光
}sEXPOSUREPARAMER;
typedef struct wdr_paramer
{
XM_U8 u8Enable;
XM_U8 u8Level;
}sWDRPARAMER;
typedef struct camera_paramer
{
XM_U8 u8StdType;
XM_U8 u8SceneMode;
XM_U8 u8CameraDnc;
XM_U8 u8LumTarget;
sEXPOSUREPARAMER sCameraExposurePrm;
XM_U8 u8Mirror;
XM_U8 u8Flip;
XM_U8 u8FlickerMode;
XM_U8 u8EShutterLevel;
XM_U8 u8DNCThreshold;
XM_U8 u8DNCMode;
XM_U8 u8DNCDelayLevel;
sNF_LEVEL sNFLevel;
XM_U8 u8IRCutDirectioin;
XM_U8 u8IRCutSyncMode;
sWDRPARAMER sWDRParamer;
XM_U8 u8StyleMode;
XM_U8 u8BlcMode;
XM_U8 u8AeSensitivity;
XM_U8 u8AtFalseColor;
XM_U8 u8sawtooth;
XM_U8 u8BwBurst;
XM_U8 u8LedMode;
XM_U8 u8LedType;
XM_U8 u8HlcMode;
XM_U8 u8AeWeight; // 焦点（人形）防过曝使能
XM_U8 u8SoftIrLvl; // 软光敏阈值
sWDRPARAMER stDefog;
XM_U8 u8InfraredSwap; //灯板输入信号反向 (0:默认 1: 反向)
}sCAMERA_PARAMER;
typedef struct _video_paramer
{
XM_U32 changed_flag; //改变标记
XM_U32 lum; //亮度
XM_U32 contrast; //对比度
XM_U32 saturation; //饱和度
XM_U32 hue; //饱和度
XM_U32 autance; //锐度
XM_S32 autogain_mode; //自动增益模式
XM_S32 autogain_level; //自动增益等级
}VIDEO_PARAMER;
#define FILE_AEWMSG "/tmp/ispmsg"
#define FILE_AEWMSG2 "/tmp/ispmsg2"
#endif

186
general/package/xiongmai-osdrv-xm530/files/include/xm/ispPrivate.h
View File

@ -1,186 +0,0 @@
#ifndef _ISP_PRIVATE_H_
#define _ISP_PRIVATE_H_
#include "xm_comm_3a.h"
#if (defined SOC_ALIOS) || (defined SOC_SYSTEM)
#include <pthread.h>
#endif
typedef struct _dpc_info_
{
XM_BOOL bEnableStatic;
XM_BOOL bEnableDetect;
ISP_STATIC_DP_TYPE_E enStaticDPType; /* Select static bright/dark defect-pixel calibration. */
ISP_TRIGGER_STATUS_E enTriggerStatus; /*status of bad pixel trigger*/
XM_U16 u16BadPixelThreshMin; /*RW, Range: [0, 0xFFF] */
XM_U16 u16BadPixelThreshMax; /*RW, Range: [0, 0xFFF] */
XM_U16 u16BadPixelThresh; /*R Range: [0, 0xFFF] */
XM_U16 u16BadPixelCountMax; /*RW, limit of max number of bad pixel, Range: [0, 0x3FF] */
XM_U16 u16BadPixelCount; /*RW, limit of min number of bad pixel, Range: [0, 0x3FF]*/
XM_U16 u16BadPixelTriggerTime; /*RW, time limit for bad pixel trigger, in frame number ,Range: [0x0, 0x640]*/
ISP_DYDPC_ATTR_S stDyDpc;
}ISP_DPC_INFO;
typedef struct _isp_frame
{
XM_U32 way;
}ISP_FRAME;
typedef struct _reg_data_
{
XM_U32 reg_addr;
XM_U32 reg_data;
ISP_FRAME isp_frame;
}REG_DATA_S;
typedef struct _mem_info_
{
XM_U32 u32PhyAddr;
XM_VOID *pVirAddr;
XM_U32 u32Size;
XM_U8 u8Id;
}MEM_INFO;
typedef struct xmISP_API_ATTR_S
{
ISP_PUB_ATTR_S stPubAttr;
ISP_CHN_ATTR_S stChnAttr;
XM_U8 u8StatusFlag;
ISP_GAMMA_ATTR_S stGamma;
ISP_BLACKLVL_ATTR_S stBlc;
ISP_SATURATION_ATTR_S stSat;
ISP_SHARPEN_ATTR_S stSharpen;
ISP_SHARPENV2_ATTR_S stSharpenV2;
ISP_2DNR_ATTR_S stNr2D;
ISP_3DNR_ATTR_S stNr3D;
ISP_3DNRV2_ATTR_S stNr3DV2;
ISP_ANTI_FALSECOLOR_S stAntiFalseColor;
// ISP_DP_ATTR_S stDpc;
ISP_DPC_INFO stDpc;
ISP_CSC_ATTR_S stCsc;
ISP_CHROMA_ATTR_S stChromaAttr;
ISP_DRC_ATTR_S stDrcAttr;
ISP_DEFOG_ATTR_S stDefogAttr;
ISP_DCI_ATTR_S stDciAttr;
ISP_MODULE_CTRL_U stModuleCtrl;
} ISP_API_ATTR_S;
#define ISPDEV_NAME "/dev/isp"
#define ISP_CMD 'I'
#define CMD_REG_WRITE _IOW(ISP_CMD,1,REG_DATA_S)
#define CMD_REG_READ _IOW(ISP_CMD,2,REG_DATA_S)
#define CMD_REG_READS _IOW(ISP_CMD,3,REG_DATA_S)
#define CMD_IRQ_READ _IOW(ISP_CMD,4,REG_DATA_S)
#define CMD_AUDIO_READ _IO(ISP_CMD,5)
#define CMD_MIPI_CHECK_INIT _IOW(ISP_CMD,6,MIPI_CK_CMD)
#define CMD_MIPI_CHECK_RUN _IO(ISP_CMD,7)
#define ISP_STATUS_UN 0
#define ISP_STATUS_PUBINIT 1
#define ISP_STATUS_INIT 2
#define ISP_STATUS_RUN 3
#define ISP_STATUS_EXIT 4
//ISP_MODULE_CTRL_U
#define ISP_MODULE_VIDEOTEST (1<<0)
#define ISP_MODULE_DPC (1<<1)
#define ISP_MODULE_BLC (1<<2)
#define ISP_MODULE_GAMMAFE (1<<3)
#define ISP_MODULE_SHANDING (1<<4)
#define ISP_MODULE_WBGAIN (1<<5)
#define ISP_MODULE_NR2D (1<<6)
#define ISP_MODULE_NR3D (1<<7)
#define ISP_MODULE_DRC (1<<8)
#define ISP_MODULE_CCM (1<<9)
#define ISP_MODULE_GAMMA (1<<10)
#define ISP_MODULE_DEMOIRE (1<<11)
#define ISP_MODULE_CC (1<<12)
#define ISP_MODULE_SHARPNESS (1<<13)
#define ISP_MODULE_RSV (1<<14)
#define ISP_MODULE_ALL (1<<31)
extern ISP_AE_REGISTER_S gAlgAeFun;
extern ISP_AWB_REGISTER_S gAlgAwbFun;
extern ISP_API_ATTR_S *pstIspApiAttr;
#ifdef SOC_SYSTEM
extern pthread_mutex_t gIspMutex;
extern pthread_mutex_t gIspMutex3;
extern pthread_mutex_t gIspMutex4;
extern XM_S32 gIspDevFd;
XM_S32 Open_IspDev(XM_VOID);
XM_S32 Close_IspDev(XM_VOID);
// Ðźųõʼ»¯
XM_S32 IspIrqSignal_Init();
XM_S32 IspPthradMutex_lock(pthread_mutex_t *mutex);
XM_S32 IspPthradMutex_unLock(pthread_mutex_t *mutex);
XM_S32 Write_IspReg(XM_U32 u32Addr, XM_U32 u32Value);
XM_S32 Read_IspReg(XM_U32 u32Addr);
#elif (defined SOC_ALIOS)
extern pthread_mutex_t gIspMutex;
extern pthread_mutex_t gIspMutex3;
extern pthread_mutex_t gIspMutex4;
XM_S32 IspIrqSignal_Init();
XM_S32 IspPthradMutex_lock(pthread_mutex_t *mutex);
XM_S32 IspPthradMutex_unLock(pthread_mutex_t *mutex);
XM_S32 Write_IspReg(XM_U32 u32Addr, XM_U32 u32Value);
XM_S32 Read_IspReg(XM_U32 u32Addr);
#elif (defined SOC_NONE)
extern XM_S32 gIspMutex;
extern XM_S32 gIspMutex4;
XM_S32 IspPthradMutex_lock(XM_S32 *mutex);
XM_S32 IspPthradMutex_unLock(XM_S32 *mutex);
#define Write_IspReg(u32Addr, u32Value) (*((volatile unsigned long *)(u32Addr)) = (u32Value))
#define Read_IspReg(u32Addr) (*((volatile unsigned long *)(u32Addr)))
#endif
XM_VOID* IspMmap(XM_U32 u32PhyAddr, XM_U32 u32Size);
XM_S32 IspMunmap(XM_VOID* pVirAddr, XM_U32 u32Size);
XM_S32 IspDPCScan(XM_U16 *pu16Addr,ISP_STDPC_ATTR_S *pstStDPAttr);
XM_VOID IspAutoScaneTask();
XM_S32 IspAePhyStatWinInit(XM_U16 u16TotalH, XM_U16 u16TotalV);
XM_S32 ispMemnCpy(XM_S8 *pSrc,XM_S8 *pDst, XM_U32 u32Num);
XM_S32 ispMemnSet(XM_S8 *pSrc,XM_S8 pDat, XM_U32 u32Num);
XM_S32 IspInit(XM_U32 u32SizeH, XM_U32 u32SizeV);
// Awb
XM_VOID IspAwbInit(ISP_AWB_WDW_ATTR_S *pstWinAttr);
XM_S32 IspAwbRsltSet(ISP_AWB_RESULT_S* const pstAwbRslt);
#endif

159
general/package/xiongmai-osdrv-xm530/files/include/xm/mpi_config.h
View File

@ -1,159 +0,0 @@
#ifndef _MPI_CONFIG_H
#define _MPI_CONFIG_H
#include "xm_type.h"
#include "xm_math.h"
#include "mpi_ae.h"
#include "mpi_awb.h"
#include "mpi_isp.h"
#include "IspToolsFlash.h"
//#include "xm540_isp.h"
#include "xm_print.h"
typedef struct _xm_menu_cfgfile_
{
XM_U8 u8MenuEn;
XM_U8 u8MenuExpMode;
XM_U8 u8MenuDncMode;
XM_U8 u8MenuBlcEn;
XM_U8 u8MenuAeTgt;
XM_U8 u8MenuDncThr;
XM_U8 u8MenuWdr;
XM_U8 u8MenuImgStyle;
XM_U8 u8MenuAgcEn;
XM_U8 u8MenuAgcMax;
XM_U8 u8MenuNrlvlCol;
XM_U8 u8MenuNrlvlBw;
XM_U8 u8MenuIrcutMode;
XM_U8 u8MenuWbRb;
XM_U8 u8MenuWbMg;
XM_U8 u8MenuMirror;
XM_U8 u8MenuFlip;
XM_U8 u8MenuAntiflicker;
XM_U8 u8MenuIrcutSwap;
XM_U8 u8MenuBrightness;
XM_U8 u8MenuContrast;
XM_U8 u8MenuSaturation;
XM_U8 u8MenuHue;
XM_U8 u8MenuAcutance;
XM_U8 u8MenuSawtooth;
XM_U8 u8MenuAntiFc;
XM_U8 u8MenuBurstBw;
XM_U8 u8MenuVStdType;
XM_U8 u8MenuVEncType;
XM_U8 u8MenuRsltType;
XM_U8 u8MenuEShutter; // 电子慢快门
XM_U8 u8MenuHLC; // 强光抑制
}XM_MENU_CFGFILE;
typedef enum {
MODE_USE_MENU = 0,
MODE_NO_MENU = 1, // DebugMode
} XM_MENU_MODE;
/**********************************************************************
函数功能: 配置模式(配置/读取)
输入参数: enMode:
0: 正常使用菜单文件
1: 无菜单(调试模式)
输出参数: penMode:
0: 正常使用菜单文件
1: 无菜单(调试模式)
返回参数: -1 : 失败
其他 : 成功
Note: Lycai
**********************************************************************/
XM_S32 XM_MPI_MENU_SetMode(XM_MENU_MODE enMode);
XM_S32 XM_MPI_MENU_GetMode(XM_MENU_MODE *penMode);
/**********************************************************************
函数功能: 保存菜单配置文件(=> NowConfigFile)
输入参数: u32Cmd:
0 : ALL
其他 : 单独某项
s32Data:
-1: 读取当前然后写入
>0: 直接写入指定值
输出参数: 无
返回参数: -1 : 失败
其他 : 成功
Note: Lycai
**********************************************************************/
XM_S32 XM_MPI_MENU_SaveCfg(XM_U32 u32Cmd, XM_S32 s32Data);
/****************************************************************************
函数功能: 保存配置(=> default ConfigFile)
输入参数: pu32Cmd: 命令集
pu16Data: 各命令值
u8Num: 命令个数
输出参数: 无
返回参数: 0: Success
-1: Failure
>0: WriteNum
Note: Lycai
****************************************************************************/
XM_S32 XM_MPI_MENU_SaveDefCfg(XM_U32 *pu32Cmd, XM_U16 *pu16Data, XM_U8 u8Num);
/**********************************************************************
函数功能: 保存菜单配置文件(=> NowConfiFile)
输入参数: u8Mode: 0 To NowCofnig(will Save to Falsh)
1 To DefaultConfig(will Save to Falsh)
0x10: To NowCofnig(Not Save)
u32Cmd: 指定(地址)
*pu32Data: 对应值
输出参数: 无
返回参数: -1 : 失败
其他 : 成功
Note: Lycai
**********************************************************************/
XM_S32 XM_MPI_MENU_SetCfg(XM_U8 u8Mode,
XM_U32 u32Cmd, XM_U32 *pu32Data);
/**********************************************************************
函数功能: 配置文件同步
输入参数: u8Mode
0: default configFile -> Config
1: const default data -> Config
2: Auto
**********************************************************************/
XM_S32 XM_MPI_MENU_CfgSync(XM_U8 u8Mode);
/**********************************************************************
函数功能: 加载菜单配置文件
输入参数: u32Cmd
0: ALL
其他: 单独某项
输出参数: 无
返回参数: -1 : 失败
其他 : 成功
Note: Lycai
**********************************************************************/
XM_S32 XM_MPI_MENU_LoadCfg(XM_U32 u32Cmd);
/**********************************************************************
函数功能: 配置文件同步
输入参数: u8Mode
0: default configFile -> Config
1: const default data -> Config
输出参数: 无
返回参数: 0: Success
-1: Failure
**********************************************************************/
XM_S32 XM_MPI_MENU_SetDefault(XM_U8 u8Mode);
#endif

53
general/package/xiongmai-osdrv-xm530/files/include/xm/mpi_smartVda.h
View File

@ -1,53 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : mpi_smartVda.h (libsmart.a mpi)
Version : Initial Draft
Author : XM Isp software group
Created : 2017/9/25
Description : The common data type defination
Function List :
History :
1.Date : 2017/9/25
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef _MPI_SMARTVDA_H_
#define _MPI_SMARTVDA_H_
#include "xm_type.h"
typedef struct stResult
{
XM_U32 uiFlag; /*1：有目标 0：无目标*/
XM_U8 reserved[16];
}Move_Detect_Result_S;
typedef struct xmMove_Detect_Para_S//移动侦测参数设置
{
XM_U8 Enable;//侦测使能 0:不使能 1:使能
XM_U8 Sensitivity;//灵敏度
XM_U8 reserved[16];
}Move_Detect_Para_S;
//灯泡移动侦测检测的接口
XM_S32 MoveDetect_Creat(int nChannel);
XM_S32 MoveDetect_SetParam(int nChannel,Move_Detect_Para_S *pstParam);
XM_S32 MoveDetect_GetResult(int nChannel,Move_Detect_Result_S *pstResult);//返回 1:有目标 0:无目标
XM_S32 MoveDetect_Destory(int nChannel);
#endif

33
general/package/xiongmai-osdrv-xm530/files/include/xm/smart_result.h
View File

@ -1,33 +0,0 @@
#ifndef __SMART_RESULT_H__
#define __SMART_RESULT_H__
#ifdef __cplusplus
#if __cplusplus
extern "C"
{
#endif
#endif /* __cplusplus */
typedef enum{
SMART_MOVE_DETECT = 0,
SMART_PRED,
}SMART_TYPE_E;
typedef struct stSmart_Result
{
unsigned int cmd;//查询命令，每bit代表一种算法(算法顺序与SMART_TYPE_E中顺序保持一致)
unsigned int uiFlag; //查询结果，每bit代表一种算法结果(算法顺序与SMART_TYPE_E中顺序保持一致)
unsigned int reserved[16];
}Smart_Result_S;
XM_S32 Smart_GetResult(int nChannel,Smart_Result_S *pstResult) __attribute__((weak));
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif

409
general/package/xiongmai-osdrv-xm530/files/include/xm/xm322_isp.h
View File

@ -1,409 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm322_isp.h
Version : Initial Draft
Author : XM Isp software group
Created : 2016/5/20
Description : The common data type defination
Function List :
History :
1.Date : 2015/6/27
Author : Ganwencao
Modification : creat
******************************************************************************/
#ifndef _XM322_REG_
#define _XM322_REG_
// VideoMain
#define FRONT_V_VIE_EN (0x00AF0010)
#define VIDEOMAIN_RGBIR (0x00AF0080)
//pre_video
#define VIDOEMODE_BASE 0x00A00000
#define VIDOEMODE_DECODE_SEL (VIDOEMODE_BASE+0x000)
#define VIDOEMODE_SLA_MAT_SEL (VIDOEMODE_BASE+0x004)
#define VIDOEMODE_DEC_DATA_SEL (VIDOEMODE_BASE+0x008)
// DPC
#define SDPC_BASE 0x00A03000
#define SDPC_CLK_SW (SDPC_BASE+0x000)
#define SDPC_SRAMADDR_CLR (SDPC_BASE+0x004)
#define SDPC_SRAMADDR_DAT (SDPC_BASE+0x008)
#define SDPC_TEST_ENABLE (SDPC_BASE+0x00C)
#define DDPC_BASE 0x00A23000
#define DDPC_MAX_THD (DDPC_BASE+0x000)
#define DDPC_MIN_THD (DDPC_BASE+0x004)
#define DDPC_DIFF_THD1 (DDPC_BASE+0x008)
#define DDPC_DIFF_THD2 (DDPC_BASE+0x00C)
// BlackLevel
#define BLACKLEVEL_BASE 0x00A04000
#define BLACKLEVEL_OFFSET_R (BLACKLEVEL_BASE+0x000)
#define BLACKLEVEL_OFFSET_G (BLACKLEVEL_BASE+0x004)
#define BLACKLEVEL_OFFSET_B (BLACKLEVEL_BASE+0x008)
#define BLACKLEVEL_RGB_MAX (BLACKLEVEL_BASE+0x00C)
#define BLACKLEVEL_RGB_MIN (BLACKLEVEL_BASE+0x010)
// DIGTAL_GAIN
#define DIGITAL_GAIN (0x00A05000+0x000)
//LSC
#define LSC_BASE 0x00A06000
#define LSC_CTRL (LSC_BASE+0x000)
//AWB
#define AWB_BASE (0x00A10000)
#define AWB_FRONTGAIN_R (AWB_BASE+0x0000)
#define AWB_FRONTGAIN_G (AWB_BASE+0x0004)
#define AWB_FRONTGAIN_B (AWB_BASE+0x0008)
#define AWB_RGBMAX_REG (AWB_BASE+0x000C)
#define AWB_RGBMIN_REG (AWB_BASE+0x0010)
#define AWB_WDW_PIXL0 (AWB_BASE+0x1000)
#define AWB_WDW_PIXL1 (AWB_BASE+0x1004)
#define AWB_WDW_PIXL2 (AWB_BASE+0x1008)
#define AWB_WDW_PIXL3 (AWB_BASE+0x100C)
#define AWB_WDW_PIXL4 (AWB_BASE+0x1010)
#define AWB_WDW_PIXL5 (AWB_BASE+0x1014)
#define AWB_WDW_PIXL6 (AWB_BASE+0x1018)
#define AWB_WDW_PIXL7 (AWB_BASE+0x101C)
#define AWB_WDW_PIXL8 (AWB_BASE+0x1020)
#define AWB_WDW_PIXL9 (AWB_BASE+0x1024)
#define AWB_WDW_PIXL10 (AWB_BASE+0x1028)
#define AWB_WDW_PIXL11 (AWB_BASE+0x102C)
#define AWB_WDW_PIXL12 (AWB_BASE+0x1030)
#define AWB_WDW_PIXL13 (AWB_BASE+0x1034)
#define AWB_WDW_PIXL14 (AWB_BASE+0x1038)
#define AWB_WDW_PIXL15 (AWB_BASE+0x103C)
#define AWB_WDW_PIXL16 (AWB_BASE+0x1040)
#define AWB_WDW_PIXL17 (AWB_BASE+0x1044)
#define AWB_WDW_PIXL18 (AWB_BASE+0x1048)
#define AWB_WDW_PIXL19 (AWB_BASE+0x104C)
#define AWB_WDW_PIXL20 (AWB_BASE+0x1050)
#define AWB_WDW_PIXL21 (AWB_BASE+0x1054)
#define AWB_WDW_PIXL22 (AWB_BASE+0x1058)
#define AWB_WDW_PIXL23 (AWB_BASE+0x105C)
#define AWB_WDW_PIXL24 (AWB_BASE+0x1060)
#define AWB_WDW_PIXL25 (AWB_BASE+0x1064)
#define AWB_WDW_PIXL26 (AWB_BASE+0x1068)
#define AWB_WDW_PIXL27 (AWB_BASE+0x106C)
#define AWB_WDW_PIXL28 (AWB_BASE+0x1070)
#define AWB_WDW_PIXL29 (AWB_BASE+0x1074)
#define AWB_WDW_PIXL30 (AWB_BASE+0x1078)
#define AWB_WDW_PIXL31 (AWB_BASE+0x107C)
#define AWB_WDW_PIXL32 (AWB_BASE+0x1080)
#define AWB_WDW_LINE0 (AWB_BASE+0x10C0)
#define AWB_WDW_LINE1 (AWB_BASE+0x10C4)
#define AWB_WDW_LINE2 (AWB_BASE+0x10C8)
#define AWB_WDW_LINE3 (AWB_BASE+0x10CC)
#define AWB_WDW_LINE4 (AWB_BASE+0x10D0)
#define AWB_WDW_LINE5 (AWB_BASE+0x10D4)
#define AWB_WDW_LINE6 (AWB_BASE+0x10D8)
#define AWB_WDW_LINE7 (AWB_BASE+0x10DC)
#define AWB_WDW_LINE8 (AWB_BASE+0x10E0)
#define AWB_WDW_LINE9 (AWB_BASE+0x10E4)
#define AWB_WDW_LINE10 (AWB_BASE+0x10E8)
#define AWB_WDW_LINE11 (AWB_BASE+0x10EC)
#define AWB_WDW_LINE12 (AWB_BASE+0x10F0)
#define AWB_WDW_LINE13 (AWB_BASE+0x10F4)
#define AWB_WDW_LINE14 (AWB_BASE+0x10F8)
#define AWB_WDW_LINE15 (AWB_BASE+0x10FC)
#define AWB_WDW_LINE16 (AWB_BASE+0x1100)
#define AWB_SRAM_ADDR_RC (AWB_BASE+0x1140)
#define AWB_SRAM_RD_EN (AWB_BASE+0x1144)
#define AWB_R_INTG (AWB_BASE+0x1148)
#define AWB_G_INTG (AWB_BASE+0x114C)
#define AWB_B_INTG (AWB_BASE+0x1150)
#define AWB_HIST_RGB_SEL (AWB_BASE+0x2000)
#define AWB_HIST_CNT0 (AWB_BASE+0x2040)
#define AWB_HIST_CNT1 (AWB_BASE+0x2044)
#define AWB_HIST_CNT2 (AWB_BASE+0x2048)
#define AWB_HIST_CNT3 (AWB_BASE+0x204C)
#define AWB_HIST_CNT4 (AWB_BASE+0x2050)
#define AWB_HIST_CNT5 (AWB_BASE+0x2054)
#define AWB_HIST_CNT6 (AWB_BASE+0x2058)
#define AWB_HIST_CNT7 (AWB_BASE+0x205C)
#define AWB_HIST_CNT8 (AWB_BASE+0x2060)
#define AWB_HIST_CNT9 (AWB_BASE+0x2064)
#define AWB_HIST_CNT10 (AWB_BASE+0x2068)
#define AWB_HIST_CNT11 (AWB_BASE+0x206C)
#define AWB_HIST_CNT12 (AWB_BASE+0x2070)
#define AWB_HIST_CNT13 (AWB_BASE+0x2074)
#define AWB_HIST_CNT14 (AWB_BASE+0x2078)
#define AWB_HIST_CNT15 (AWB_BASE+0x207C)
#define AWB_HIST_CNT16 (AWB_BASE+0x2080)
#define AWB_HIST_CNT17 (AWB_BASE+0x2084)
#define AWB_HIST_CNT18 (AWB_BASE+0x2088)
#define AWB_HIST_CNT19 (AWB_BASE+0x208C)
#define AWB_HIST_CNT20 (AWB_BASE+0x2090)
#define AWB_HIST_CNT21 (AWB_BASE+0x2094)
#define AWB_HIST_CNT22 (AWB_BASE+0x2098)
#define AWB_HIST_CNT23 (AWB_BASE+0x209C)
#define AWB_HIST_CNT24 (AWB_BASE+0x20A0)
#define AWB_HIST_CNT25 (AWB_BASE+0x20A4)
#define AWB_HIST_CNT26 (AWB_BASE+0x20A8)
#define AWB_HIST_CNT27 (AWB_BASE+0x20AC)
#define AWB_HIST_CNT28 (AWB_BASE+0x20B0)
#define AWB_HIST_CNT29 (AWB_BASE+0x20B4)
#define AWB_HIST_CNT30 (AWB_BASE+0x20B8)
#define AWB_HIST_CNT31 (AWB_BASE+0x20BC)
/*
//DPC
#define DPC_BASE 0x00A23000
#define DPC_MAX_THD (0x00A23000+0X000)
#define DPC_MIN_THD (0x00A23000+0X004)
#define DPC_DIFF_THD1 (0x00A23000+0X008)
#define DPC_DIFF_THD2 (0x00A23000+0X00C)
*/
//NR_2D
#define NR_2D_BASE 0x00A20000
#define NR_2D_THDL_REG (NR_2D_BASE + 0x000)
#define NR_2D_THDH_REG (NR_2D_BASE + 0x004)
#define NR_2D_COEF_REG (NR_2D_BASE + 0x008)
#define NR_2D_GMIN_REG (NR_2D_BASE + 0x00C)
#define NR_2D_DELTA_THD (NR_2D_BASE + 0x010)
#define NR_2D_G_COEF1 (NR_2D_BASE + 0x014)
#define NR_2D_G_COEF2 (NR_2D_BASE + 0x018)
#define NR_2D_G_COEF3 (NR_2D_BASE + 0x01C)
#define NR_2D_G_COEF4 (NR_2D_BASE + 0x020)
#define NR_2D_RB_COEF1 (NR_2D_BASE + 0x024)
#define NR_2D_RB_COEF2 (NR_2D_BASE + 0x028)
#define NR_2D_RB_COEF3 (NR_2D_BASE + 0x02C)
#define NR_2D_H_SEL (NR_2D_BASE + 0x030)
#define NR_2D_FLT_EN (NR_2D_BASE + 0x034)
//AF
#define AF_BASE 0x00A21000
#define AF_WDW0_VBEGIN (AF_BASE + 0x000)
#define AF_WDW0_VEND (AF_BASE + 0x004)
#define AF_WDW0_HBEGIN (AF_BASE + 0x008)
#define AF_WDW0_HEND (AF_BASE + 0x00C)
#define AF_WDW0_HZ (AF_BASE + 0x094)
//NIR
#define NIR_BASE 0x00A30000
#define NIR_HIR_COEF1 (NIR_BASE + 0x0018)
#define NIR_HIR_COEF2 (NIR_BASE + 0x001C)
#define NIR_HIR_COEF3 (NIR_BASE + 0x0020)
#define NIR_IR_INTG (NIR_BASE + 0x2000)
#define NIR_R_INTG (NIR_BASE + 0x2004)
#define NIR_G_INTG (NIR_BASE + 0x2008)
#define NIR_B_INTG (NIR_BASE + 0x200C)
#define NIR_RGB_INTG (NIR_BASE + 0x2010)
#define NIR_CC_MODE (NIR_BASE + 0x1000)
#define NIR_RS_RAT (NIR_BASE + 0x1004)
#define NIR_GS_RAT (NIR_BASE + 0x1008)
#define NIR_BS_RAT (NIR_BASE + 0x100C)
#define NIR_CC_COEF11 (NIR_BASE + 0x1040)
#define NIR_CC_COEF12 (NIR_BASE + 0x1044)
#define NIR_CC_COEF13 (NIR_BASE + 0x1048)
#define NIR_CC_COEF14 (NIR_BASE + 0x104C)
#define NIR_CC_COEF21 (NIR_BASE + 0x1050)
#define NIR_CC_COEF22 (NIR_BASE + 0x1054)
#define NIR_CC_COEF23 (NIR_BASE + 0x1058)
#define NIR_CC_COEF24 (NIR_BASE + 0x105C)
#define NIR_CC_COEF31 (NIR_BASE + 0x1060)
#define NIR_CC_COEF32 (NIR_BASE + 0x1064)
#define NIR_CC_COEF33 (NIR_BASE + 0x1068)
#define NIR_CC_COEF34 (NIR_BASE + 0x106C)
#define NIR_LUMLUT0 (NIR_BASE + 0x1080)
// Demosaic
#define DEMOSAIC_BASE 0x00A50000
#define DEMOSAIC_G_HOFST (DEMOSAIC_BASE + 0x000)
#define DEMOSAIC_DHV_OFST (DEMOSAIC_BASE + 0x004)
#define DEMOSAIC_DHV_K (DEMOSAIC_BASE + 0x008)
#define DEMOSAIC_GCALC_MODE (DEMOSAIC_BASE + 0x00C)
#define DEMOSAIC_THRMAIN (DEMOSAIC_BASE + 0x010)
#define DEMOSAIC_THRSUB (DEMOSAIC_BASE + 0x014)
#define DEMOSAIC_WT_G (DEMOSAIC_BASE + 0x01C)
#define DEMOSAIC_HV_OFST (DEMOSAIC_BASE + 0x020)
// CSM
#define CSM_BASE 0x00A60000
#define CSM_RGB_MAX (CSM_BASE+0x000)
#define CSM_RGB_MIN (CSM_BASE+0x004)
#define CSM_R_OFST_REG (CSM_BASE+0x040)
#define CSM_R1_COEF_REG (CSM_BASE+0x044)
#define CSM_R2_COEF_REG (CSM_BASE+0x048)
#define CSM_R3_COEF_REG (CSM_BASE+0x04C)
#define CSM_G_OFST_REG (CSM_BASE+0x050)
#define CSM_G1_COEF_REG (CSM_BASE+0x054)
#define CSM_G2_COEF_REG (CSM_BASE+0x058)
#define CSM_G3_COEF_REG (CSM_BASE+0x05C)
#define CSM_B_OFST_REG (CSM_BASE+0x060)
#define CSM_B1_COEF_REG (CSM_BASE+0x064)
#define CSM_B2_COEF_REG (CSM_BASE+0x068)
#define CSM_B3_COEF_REG (CSM_BASE+0x06C)
// Gamma60
#define GAMMA60_BASE 0x00A61000
#define GAMMA60_BUF_SW (GAMMA60_BASE+0x000)
#define GAMMA60_BUF_SW_STATE (GAMMA60_BASE+0x004)
#define GAMMA60_LINE0_DAT0 (GAMMA60_BASE+0x040)
#define GAMMA60_LINE1_DAT0 (GAMMA60_BASE+0x140)
// RGB2YC
#define RGB2YC_BASE 0x00A62000
// Demoire
#define DEMOIRE_BASE 0x00A63000
#define DEMOIRE_V_THD (DEMOIRE_BASE+0x000)
#define DEMOIRE_KV (DEMOIRE_BASE+0x004)
#define DEMOIRE_DF_THD_MAX (DEMOIRE_BASE+0x008)
#define DEMOIRE_DF_THD_MIN (DEMOIRE_BASE+0x00C)
#define DEMOIRE_GAIN_MIN (DEMOIRE_BASE+0x010)
#define DEMOIRE_KC (DEMOIRE_BASE+0x014)
#define DEMOIRE_BYPASS (DEMOIRE_BASE+0x018)
// Y_Gamma
#define YGAMMA_BASE 0x00A71000
#define YGAMMA_BUF_SW (YGAMMA_BASE+0x000)
#define YGAMMA_BUF_SW_STATE (YGAMMA_BASE+0x004)
#define YGAMMA_LINE0_DAT0 (YGAMMA_BASE+0x040)
#define YGAMMA_LINE1_DAT0 (YGAMMA_BASE+0x180)
//Y_hist
#define YHIST_BASE (0x00A72000)
#define YHIST_CNT0 (YHIST_BASE+0x000)
//C_tran
#define CTRAN_BASE 0x00A73000
#define CTRAN_BUF_SW (CTRAN_BASE+0x000)
#define CTRAN_BUF_SW_STATE (CTRAN_BASE+0x004)
#define TRAN_LINE0_DAT0 (CTRAN_BASE+0x040)
#define TRAN_LINE0_DAT7 (CTRAN_BASE+0x05C)
#define TRAN_LINE0_DAT8 (CTRAN_BASE+0x060)
#define TRAN_LINE1_DAT0 (CTRAN_BASE+0x080)
// Sharpness
#define SHARPEN_BASE 0x00A74000
#define SHARPEN_YMTH1 (SHARPEN_BASE+0x000)
#define SHARPEN_YMTH2 (SHARPEN_BASE+0x004)
#define SHARPEN_YM_K (SHARPEN_BASE+0x008)
#define SHARPEN_KM0 (SHARPEN_BASE+0x00C)
#define SHARPEN_WM0 (SHARPEN_BASE+0x010)
#define SHARPEN_WM1 (SHARPEN_BASE+0x014)
#define SHARPEN_WM2 (SHARPEN_BASE+0x018)
#define SHARPEN_WM3 (SHARPEN_BASE+0x01C)
#define SHARPEN_WM4 (SHARPEN_BASE+0x020)
#define SHARPEN_WM5 (SHARPEN_BASE+0x024)
#define SHARPEN_YMDTH1 (SHARPEN_BASE+0x040)
#define SHARPEN_YMDTH2 (SHARPEN_BASE+0x044)
#define SHARPEN_YMD_K (SHARPEN_BASE+0x048)
#define SHARPEN_KMD_MAX (SHARPEN_BASE+0x04C)
#define SHARPEN_WMD0 (SHARPEN_BASE+0x050)
#define SHARPEN_WMD1 (SHARPEN_BASE+0x054)
#define SHARPEN_WMD2 (SHARPEN_BASE+0x058)
#define SHARPEN_WMD3 (SHARPEN_BASE+0x05C)
#define SHARPEN_WMD4 (SHARPEN_BASE+0x060)
#define SHARPEN_WMD5 (SHARPEN_BASE+0x064)
#define SHARPEN_YHTH1 (SHARPEN_BASE+0x080)
#define SHARPEN_YHTH2 (SHARPEN_BASE+0x084)
#define SHARPEN_YH_K (SHARPEN_BASE+0x088)
#define SHARPEN_KH0 (SHARPEN_BASE+0x08C)
#define SHARPEN_WH0 (SHARPEN_BASE+0x090)
#define SHARPEN_WH1 (SHARPEN_BASE+0x094)
#define SHARPEN_WH2 (SHARPEN_BASE+0x098)
#define SHARPEN_WH3 (SHARPEN_BASE+0x09C)
#define SHARPEN_WH4 (SHARPEN_BASE+0x0A0)
#define SHARPEN_WH5 (SHARPEN_BASE+0x0A4)
#define SHARPEN_YHDTH1 (SHARPEN_BASE+0x0C0)
#define SHARPEN_YHDTH2 (SHARPEN_BASE+0x0C4)
#define SHARPEN_YHD_K (SHARPEN_BASE+0x0C8)
#define SHARPEN_KHD_MAX (SHARPEN_BASE+0x0CC)
#define SHARPEN_WHD0 (SHARPEN_BASE+0x0D0)
#define SHARPEN_WHD1 (SHARPEN_BASE+0x0D4)
#define SHARPEN_WHD2 (SHARPEN_BASE+0x0D8)
#define SHARPEN_WHD3 (SHARPEN_BASE+0x0DC)
#define SHARPEN_WHD4 (SHARPEN_BASE+0x0E0)
#define SHARPEN_WHD5 (SHARPEN_BASE+0x0E4)
#define SHARPEN_KH00 (SHARPEN_BASE+0x100)
#define SHARPEN_KH01 (SHARPEN_BASE+0x104)
#define SHARPEN_KL00 (SHARPEN_BASE+0x108)
#define SHARPEN_KL01 (SHARPEN_BASE+0x10C)
#define SHARPEN_KH1 (SHARPEN_BASE+0x110)
#define SHARPEN_KL1 (SHARPEN_BASE+0x114)
#define SHARPEN_DLTMAX (SHARPEN_BASE+0x118)
#define SHARPEN_DFKD (SHARPEN_BASE+0x11C)
#define SHARPEN_DFMAX (SHARPEN_BASE+0x120)
#define SHARPEN_ENH_STREN (SHARPEN_BASE+0x130)
#define SHARPEN_ENH_THR (SHARPEN_BASE+0x134)
#define SHARPEN_ENH_GMAX (SHARPEN_BASE+0x138)
#define SHARPEN_TRAN_DAT0 (SHARPEN_BASE+0x140)
#define SHARPEN_C_KR1 (SHARPEN_BASE+0x1C0)
#define SHARPEN_C_KR2 (SHARPEN_BASE+0x1C4)
#define SHARPEN_C_KG1 (SHARPEN_BASE+0x1C8)
#define SHARPEN_C_KG2 (SHARPEN_BASE+0x1CC)
#define SHARPEN_C_KB1 (SHARPEN_BASE+0x1D0)
#define SHARPEN_C_KB2 (SHARPEN_BASE+0x1D4)
#define SHARPEN_C_ZONE_EN (SHARPEN_BASE+0x1D8)
#define SHARPEN_C_COEF1 (SHARPEN_BASE+0x1DC)
#define SHARPEN_C_COEF2 (SHARPEN_BASE+0x1E0)
#define SHARPEN_C_COEF3 (SHARPEN_BASE+0x1E4)
#define SHARPEN_C_FLT_SEL (SHARPEN_BASE+0x1E8)
#define SHARPEN_C_SAT_DAT0 (SHARPEN_BASE+0x200)
#define SHARPEN_EN (SHARPEN_BASE+0x240)
// YC_Gain
#define YC_GAIN_BASE 0x00A75000
#define Y_GAIN (YC_GAIN_BASE+(0x000))
#define CB_GAIN (YC_GAIN_BASE+(0x004))
#define CR_GAIN (YC_GAIN_BASE+(0x008))
#define Y_OFST (YC_GAIN_BASE+(0x00C))
#define Y_MAX_THD (YC_GAIN_BASE+(0x010))
#define Y_MIN_THD (YC_GAIN_BASE+(0x014))
#endif

393
general/package/xiongmai-osdrv-xm530/files/include/xm/xm350_isp.h
View File

@ -1,393 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm322_isp.h
Version : Initial Draft
Author : XM Isp software group
Created : 2016/5/20
Description : The common data type defination
Function List :
History :
1.Date : 2017/5/31
Author : Ganwencao
Modification : creat
******************************************************************************/
#ifndef _XM350_REG_
#define _XM350_REG_
//
#define FRONT_V_VIE_EN (0x00AF0010)
//pre_video
#define VIDOEMODE_BASE 0x00A00000
#define VIDOEMODE_DECODE_SEL (VIDOEMODE_BASE+0x000)
#define VIDOEMODE_SLA_MAT_SEL (VIDOEMODE_BASE+0x004)
#define VIDOEMODE_DEC_DATA_SEL (VIDOEMODE_BASE+0x008)
// DPC
#define SDPC_BASE 0x00A01000
#define SDPC_CLK_SW_REG (SDPC_BASE+0x000)
#define SDPC_CPU_ADDR (SDPC_BASE+0x004)
#define SDPC_CPU_DATA (SDPC_BASE+0x008)
#define SDPC_TEST (SDPC_BASE+0x00c)
#define SDPC_HIGH_THR (SDPC_BASE+0x010)
#define SDPC_LOW_THR (SDPC_BASE+0x014)
#define SDPC_DET_MODE (SDPC_BASE+0x018)
#define SDPC_DET_READY (SDPC_BASE+0x01c)
#define SDPC_ACTIVE_PIX_NUM (SDPC_BASE+0x040)
#define SDPC_ACTIVE_LINE_NUM (SDPC_BASE+0x044)
#define SDPC_CPU_OP_SEL (SDPC_BASE+0x048)
#define SDPC_VD_OP_SEL (SDPC_BASE+0x04c)
#define SDPC_BAD_PIX_NUM (SDPC_BASE+0x050)
#define DDPC_BASE 0x00A21000
#define DDPC_MAX_THD (DDPC_BASE+0x000)
#define DDPC_MIN_THD (DDPC_BASE+0x004)
#define DDPC_DIFF_THD1 (DDPC_BASE+0x008)
#define DDPC_DIFF_THD2 (DDPC_BASE+0x00C)
//FPN
#define FPN_BASE 0x00A02000
#define FPN_CLK_SW_REG (FPN_BASE+0x000)
#define FPN_CPU_ADDR (FPN_BASE+0x004)
#define FPN_CPU_DATA (FPN_BASE+0x008)
#define FPN_CPU_RDSEL (FPN_BASE+0x00C)
#define FPN_STREN (FPN_BASE+0x010)
#define FPN_SEL (FPN_BASE+0x014)
#define FPN_DET_MODE (FPN_BASE+0x018)
#define FPN_DET_READY (FPN_BASE+0x01C)
// BlackLevel
#define BLACKLEVEL_BASE 0x00A04000
#define BLACKLEVEL_OFFSET_R (BLACKLEVEL_BASE+0x000)
#define BLACKLEVEL_OFFSET_G (BLACKLEVEL_BASE+0x004)
#define BLACKLEVEL_OFFSET_B (BLACKLEVEL_BASE+0x008)
#define BLACKLEVEL_RGB_MAX (BLACKLEVEL_BASE+0x00C)
#define BLACKLEVEL_RGB_MIN (BLACKLEVEL_BASE+0x010)
// DIGTAL_GAIN
#define DIGITAL_GAIN (0x00A05000+0x000)
//LSC
#define LSC_BASE 0x00A06000
#define LSC_CTRL (LSC_BASE+0x000)
//AWB
#define AWB_BASE (0x00A10000)
#define AWB_FRONTGAIN_R (AWB_BASE+0x0000)
#define AWB_FRONTGAIN_G (AWB_BASE+0x0004)
#define AWB_FRONTGAIN_B (AWB_BASE+0x0008)
#define AWB_RGBMAX_REG (AWB_BASE+0x000C)
#define AWB_RGBMIN_REG (AWB_BASE+0x0010)
#define AWB_WDW_PIXL0 (AWB_BASE+0x1000)
#define AWB_WDW_PIXL1 (AWB_BASE+0x1004)
#define AWB_WDW_PIXL2 (AWB_BASE+0x1008)
#define AWB_WDW_PIXL3 (AWB_BASE+0x100C)
#define AWB_WDW_PIXL4 (AWB_BASE+0x1010)
#define AWB_WDW_PIXL5 (AWB_BASE+0x1014)
#define AWB_WDW_PIXL6 (AWB_BASE+0x1018)
#define AWB_WDW_PIXL7 (AWB_BASE+0x101C)
#define AWB_WDW_PIXL8 (AWB_BASE+0x1020)
#define AWB_WDW_PIXL9 (AWB_BASE+0x1024)
#define AWB_WDW_PIXL10 (AWB_BASE+0x1028)
#define AWB_WDW_PIXL11 (AWB_BASE+0x102C)
#define AWB_WDW_PIXL12 (AWB_BASE+0x1030)
#define AWB_WDW_PIXL13 (AWB_BASE+0x1034)
#define AWB_WDW_PIXL14 (AWB_BASE+0x1038)
#define AWB_WDW_PIXL15 (AWB_BASE+0x103C)
#define AWB_WDW_PIXL16 (AWB_BASE+0x1040)
#define AWB_WDW_PIXL17 (AWB_BASE+0x1044)
#define AWB_WDW_PIXL18 (AWB_BASE+0x1048)
#define AWB_WDW_PIXL19 (AWB_BASE+0x104C)
#define AWB_WDW_PIXL20 (AWB_BASE+0x1050)
#define AWB_WDW_PIXL21 (AWB_BASE+0x1054)
#define AWB_WDW_PIXL22 (AWB_BASE+0x1058)
#define AWB_WDW_PIXL23 (AWB_BASE+0x105C)
#define AWB_WDW_PIXL24 (AWB_BASE+0x1060)
#define AWB_WDW_PIXL25 (AWB_BASE+0x1064)
#define AWB_WDW_PIXL26 (AWB_BASE+0x1068)
#define AWB_WDW_PIXL27 (AWB_BASE+0x106C)
#define AWB_WDW_PIXL28 (AWB_BASE+0x1070)
#define AWB_WDW_PIXL29 (AWB_BASE+0x1074)
#define AWB_WDW_PIXL30 (AWB_BASE+0x1078)
#define AWB_WDW_PIXL31 (AWB_BASE+0x107C)
#define AWB_WDW_PIXL32 (AWB_BASE+0x1080)
#define AWB_WDW_LINE0 (AWB_BASE+0x10C0)
#define AWB_WDW_LINE1 (AWB_BASE+0x10C4)
#define AWB_WDW_LINE2 (AWB_BASE+0x10C8)
#define AWB_WDW_LINE3 (AWB_BASE+0x10CC)
#define AWB_WDW_LINE4 (AWB_BASE+0x10D0)
#define AWB_WDW_LINE5 (AWB_BASE+0x10D4)
#define AWB_WDW_LINE6 (AWB_BASE+0x10D8)
#define AWB_WDW_LINE7 (AWB_BASE+0x10DC)
#define AWB_WDW_LINE8 (AWB_BASE+0x10E0)
#define AWB_WDW_LINE9 (AWB_BASE+0x10E4)
#define AWB_WDW_LINE10 (AWB_BASE+0x10E8)
#define AWB_WDW_LINE11 (AWB_BASE+0x10EC)
#define AWB_WDW_LINE12 (AWB_BASE+0x10F0)
#define AWB_WDW_LINE13 (AWB_BASE+0x10F4)
#define AWB_WDW_LINE14 (AWB_BASE+0x10F8)
#define AWB_WDW_LINE15 (AWB_BASE+0x10FC)
#define AWB_WDW_LINE16 (AWB_BASE+0x1100)
#define AWB_SRAM_ADDR_RC (AWB_BASE+0x1140)
#define AWB_SRAM_RD_EN (AWB_BASE+0x1144)
#define AWB_R_INTG (AWB_BASE+0x1148)
#define AWB_G_INTG (AWB_BASE+0x114C)
#define AWB_B_INTG (AWB_BASE+0x1150)
#define AWB_HIST_RGB_SEL (AWB_BASE+0x2000)
#define AWB_HIST_CNT0 (AWB_BASE+0x2040)
#define AWB_HIST_CNT1 (AWB_BASE+0x2044)
#define AWB_HIST_CNT2 (AWB_BASE+0x2048)
#define AWB_HIST_CNT3 (AWB_BASE+0x204C)
#define AWB_HIST_CNT4 (AWB_BASE+0x2050)
#define AWB_HIST_CNT5 (AWB_BASE+0x2054)
#define AWB_HIST_CNT6 (AWB_BASE+0x2058)
#define AWB_HIST_CNT7 (AWB_BASE+0x205C)
#define AWB_HIST_CNT8 (AWB_BASE+0x2060)
#define AWB_HIST_CNT9 (AWB_BASE+0x2064)
#define AWB_HIST_CNT10 (AWB_BASE+0x2068)
#define AWB_HIST_CNT11 (AWB_BASE+0x206C)
#define AWB_HIST_CNT12 (AWB_BASE+0x2070)
#define AWB_HIST_CNT13 (AWB_BASE+0x2074)
#define AWB_HIST_CNT14 (AWB_BASE+0x2078)
#define AWB_HIST_CNT15 (AWB_BASE+0x207C)
#define AWB_HIST_CNT16 (AWB_BASE+0x2080)
#define AWB_HIST_CNT17 (AWB_BASE+0x2084)
#define AWB_HIST_CNT18 (AWB_BASE+0x2088)
#define AWB_HIST_CNT19 (AWB_BASE+0x208C)
#define AWB_HIST_CNT20 (AWB_BASE+0x2090)
#define AWB_HIST_CNT21 (AWB_BASE+0x2094)
#define AWB_HIST_CNT22 (AWB_BASE+0x2098)
#define AWB_HIST_CNT23 (AWB_BASE+0x209C)
#define AWB_HIST_CNT24 (AWB_BASE+0x20A0)
#define AWB_HIST_CNT25 (AWB_BASE+0x20A4)
#define AWB_HIST_CNT26 (AWB_BASE+0x20A8)
#define AWB_HIST_CNT27 (AWB_BASE+0x20AC)
#define AWB_HIST_CNT28 (AWB_BASE+0x20B0)
#define AWB_HIST_CNT29 (AWB_BASE+0x20B4)
#define AWB_HIST_CNT30 (AWB_BASE+0x20B8)
#define AWB_HIST_CNT31 (AWB_BASE+0x20BC)
/*
//DPC
#define DPC_BASE 0x00A23000
#define DPC_MAX_THD (0x00A23000+0X000)
#define DPC_MIN_THD (0x00A23000+0X004)
#define DPC_DIFF_THD1 (0x00A23000+0X008)
#define DPC_DIFF_THD2 (0x00A23000+0X00C)
*/
//NR_2D
#define NR_2D_BASE 0x00A20000
#define NR_2D_THDL_REG (NR_2D_BASE + 0x000)
#define NR_2D_THDH_REG (NR_2D_BASE + 0x004)
#define NR_2D_COEF_REG (NR_2D_BASE + 0x008)
#define NR_2D_GMIN_REG (NR_2D_BASE + 0x00C)
#define NR_2D_DELTA_THD (NR_2D_BASE + 0x010)
#define NR_2D_G_COEF1 (NR_2D_BASE + 0x014)
#define NR_2D_G_COEF2 (NR_2D_BASE + 0x018)
#define NR_2D_G_COEF3 (NR_2D_BASE + 0x01C)
#define NR_2D_G_COEF4 (NR_2D_BASE + 0x020)
#define NR_2D_RB_COEF1 (NR_2D_BASE + 0x024)
#define NR_2D_RB_COEF2 (NR_2D_BASE + 0x028)
#define NR_2D_RB_COEF3 (NR_2D_BASE + 0x02C)
#define NR_2D_H_SEL (NR_2D_BASE + 0x030)
#define NR_2D_FLT_EN (NR_2D_BASE + 0x034)
// Demosaic
#define DEMOSAIC_BASE 0x00A50000
#define DEMOSAIC_G_HOFST (DEMOSAIC_BASE + 0x000)
#define DEMOSAIC_DHV_OFST (DEMOSAIC_BASE + 0x004)
#define DEMOSAIC_DHV_K (DEMOSAIC_BASE + 0x008)
#define DEMOSAIC_THRMAIN (DEMOSAIC_BASE + 0x010)
#define DEMOSAIC_THRSUB (DEMOSAIC_BASE + 0x014)
// CSM
#define CSM_BASE 0x00A60000
#define CSM_RGB_MAX (CSM_BASE+0x000)
#define CSM_RGB_MIN (CSM_BASE+0x004)
#define CSM_R_OFST_REG (CSM_BASE+0x040)
#define CSM_R1_COEF_REG (CSM_BASE+0x044)
#define CSM_R2_COEF_REG (CSM_BASE+0x048)
#define CSM_R3_COEF_REG (CSM_BASE+0x04C)
#define CSM_G_OFST_REG (CSM_BASE+0x050)
#define CSM_G1_COEF_REG (CSM_BASE+0x054)
#define CSM_G2_COEF_REG (CSM_BASE+0x058)
#define CSM_G3_COEF_REG (CSM_BASE+0x05C)
#define CSM_B_OFST_REG (CSM_BASE+0x060)
#define CSM_B1_COEF_REG (CSM_BASE+0x064)
#define CSM_B2_COEF_REG (CSM_BASE+0x068)
#define CSM_B3_COEF_REG (CSM_BASE+0x06C)
// Gamma96
#define GAMMA96_BASE 0x00A61000
#define GAMMA96_LINE0_DAT0 (GAMMA96_BASE+0x000)
// RGB2YC
#define RGB2YC_BASE 0x00A62000
// Demoire
#define DEMOIRE_BASE 0x00A63000
#define DEMOIRE_V_THD (DEMOIRE_BASE+0x000)
#define DEMOIRE_KV (DEMOIRE_BASE+0x004)
#define DEMOIRE_DF_THD_MAX (DEMOIRE_BASE+0x008)
#define DEMOIRE_DF_THD_MIN (DEMOIRE_BASE+0x00C)
#define DEMOIRE_GAIN_MIN (DEMOIRE_BASE+0x010)
#define DEMOIRE_KC (DEMOIRE_BASE+0x014)
#define DEMOIRE_BYPASS (DEMOIRE_BASE+0x018)
// CC
#define CC_BASE 0x00A70000
#define CC_EN_REG (CC_BASE+0x000)
#define CC_HUE_OFST (CC_BASE+0x018)
#define CC_YS_TRAN_DAT0 (CC_BASE+0x040)
#define CC_S_TRAN_DAT0 (CC_BASE+0x084)
#define CC_HS_TRAN_DAT0 (CC_BASE+0x0E4)
#define CC_HH_H1_SATRT (CC_BASE+0x200)
#define CC_HH_H1_END (CC_BASE+0x204)
#define CC_HH_H1_MAX1 (CC_BASE+0x208)
#define CC_HH_H1_MAX2 (CC_BASE+0x20C)
#define CC_HH_H1_DMAX (CC_BASE+0x210)
#define CC_HH_H1_K1 (CC_BASE+0x214)
#define CC_HH_H1_K2 (CC_BASE+0x218)
#define CC_HH_H2_SATRT (CC_BASE+0x21C)
#define CC_HH_H2_END (CC_BASE+0x220)
#define CC_HH_H2_MAX1 (CC_BASE+0x224)
#define CC_HH_H2_MAX2 (CC_BASE+0x228)
#define CC_HH_H2_DMAX (CC_BASE+0x22C)
#define CC_HH_H2_K1 (CC_BASE+0x230)
#define CC_HH_H2_K2 (CC_BASE+0x234)
#define CC_HH_H3_SATRT (CC_BASE+0x240)
#define CC_HH_H3_END (CC_BASE+0x244)
#define CC_HH_H3_MAX1 (CC_BASE+0x248)
#define CC_HH_H3_MAX2 (CC_BASE+0x24C)
#define CC_HH_H3_DMAX (CC_BASE+0x250)
#define CC_HH_H3_K1 (CC_BASE+0x254)
#define CC_HH_H3_K2 (CC_BASE+0x258)
// Y_Gamma
#define YGAMMA_BASE 0x00A71000
#define YGAMMA_LINE0_DAT0 (YGAMMA_BASE+0x000)
//Y_hist
#define YHIST_BASE 0x00A72000
#define YHIST_CNT0 (YHIST_BASE+0x000)
//C_tran
#define CTRAN_BASE 0x00A73000
#define CTRAN_BUF_SW (CTRAN_BASE+0x000)
#define TRAN_LINE0_DAT0 (CTRAN_BASE+0x000)
#define TRAN_LINE0_DAT7 (CTRAN_BASE+0x05C)
#define TRAN_LINE0_DAT8 (CTRAN_BASE+0x060)
// Sharpness
#define SHARPEN_BASE 0x00A74000
#define SHARPEN_YMTH1 (SHARPEN_BASE+0x000)
#define SHARPEN_YMTH2 (SHARPEN_BASE+0x004)
#define SHARPEN_YM_K (SHARPEN_BASE+0x008)
#define SHARPEN_KM0 (SHARPEN_BASE+0x00C)
#define SHARPEN_WM0 (SHARPEN_BASE+0x010)
#define SHARPEN_WM1 (SHARPEN_BASE+0x014)
#define SHARPEN_WM2 (SHARPEN_BASE+0x018)
#define SHARPEN_WM3 (SHARPEN_BASE+0x01C)
#define SHARPEN_WM4 (SHARPEN_BASE+0x020)
#define SHARPEN_WM5 (SHARPEN_BASE+0x024)
#define SHARPEN_YMDTH1 (SHARPEN_BASE+0x040)
#define SHARPEN_YMDTH2 (SHARPEN_BASE+0x044)
#define SHARPEN_YMD_K (SHARPEN_BASE+0x048)
#define SHARPEN_KMD_MAX (SHARPEN_BASE+0x04C)
#define SHARPEN_WMD0 (SHARPEN_BASE+0x050)
#define SHARPEN_WMD1 (SHARPEN_BASE+0x054)
#define SHARPEN_WMD2 (SHARPEN_BASE+0x058)
#define SHARPEN_WMD3 (SHARPEN_BASE+0x05C)
#define SHARPEN_WMD4 (SHARPEN_BASE+0x060)
#define SHARPEN_WMD5 (SHARPEN_BASE+0x064)
#define SHARPEN_YHTH1 (SHARPEN_BASE+0x080)
#define SHARPEN_YHTH2 (SHARPEN_BASE+0x084)
#define SHARPEN_YH_K (SHARPEN_BASE+0x088)
#define SHARPEN_KH0 (SHARPEN_BASE+0x08C)
#define SHARPEN_WH0 (SHARPEN_BASE+0x090)
#define SHARPEN_WH1 (SHARPEN_BASE+0x094)
#define SHARPEN_WH2 (SHARPEN_BASE+0x098)
#define SHARPEN_WH3 (SHARPEN_BASE+0x09C)
#define SHARPEN_WH4 (SHARPEN_BASE+0x0A0)
#define SHARPEN_WH5 (SHARPEN_BASE+0x0A4)
#define SHARPEN_YHDTH1 (SHARPEN_BASE+0x0C0)
#define SHARPEN_YHDTH2 (SHARPEN_BASE+0x0C4)
#define SHARPEN_YHD_K (SHARPEN_BASE+0x0C8)
#define SHARPEN_KHD_MAX (SHARPEN_BASE+0x0CC)
#define SHARPEN_WHD0 (SHARPEN_BASE+0x0D0)
#define SHARPEN_WHD1 (SHARPEN_BASE+0x0D4)
#define SHARPEN_WHD2 (SHARPEN_BASE+0x0D8)
#define SHARPEN_WHD3 (SHARPEN_BASE+0x0DC)
#define SHARPEN_WHD4 (SHARPEN_BASE+0x0E0)
#define SHARPEN_WHD5 (SHARPEN_BASE+0x0E4)
#define SHARPEN_KH00 (SHARPEN_BASE+0x100)
#define SHARPEN_KH01 (SHARPEN_BASE+0x104)
#define SHARPEN_KL00 (SHARPEN_BASE+0x108)
#define SHARPEN_KL01 (SHARPEN_BASE+0x10C)
#define SHARPEN_KH1 (SHARPEN_BASE+0x110)
#define SHARPEN_KL1 (SHARPEN_BASE+0x114)
#define SHARPEN_DLTMAX (SHARPEN_BASE+0x118)
#define SHARPEN_DFKD (SHARPEN_BASE+0x11C)
#define SHARPEN_DFMAX (SHARPEN_BASE+0x120)
#define SHARPEN_ENH_STREN (SHARPEN_BASE+0x130)
#define SHARPEN_ENH_THR (SHARPEN_BASE+0x134)
#define SHARPEN_ENH_GMAX (SHARPEN_BASE+0x138)
#define SHARPEN_TRAN_DAT0 (SHARPEN_BASE+0x140)
#define SHARPEN_C_COEF1 (SHARPEN_BASE+0x1C0)
#define SHARPEN_C_COEF2 (SHARPEN_BASE+0x1C4)
#define SHARPEN_C_COEF3 (SHARPEN_BASE+0x1C8)
#define SHARPEN_C_FLT_SEL (SHARPEN_BASE+0x1CC)
#define SHARPEN_EN (SHARPEN_BASE+0x240)
#define SHARPEN_DENOISE_EN (SHARPEN_BASE+0x248)
#define SHARPEN_NOISETHR (SHARPEN_BASE+0x250)
// YC_Gain
#define YC_GAIN_BASE 0x00A75000
#define Y_GAIN (YC_GAIN_BASE+(0x000))
#define CB_GAIN (YC_GAIN_BASE+(0x004))
#define CR_GAIN (YC_GAIN_BASE+(0x008))
#define Y_OFST (YC_GAIN_BASE+(0x00C))
#define Y_MAX_THD (YC_GAIN_BASE+(0x010))
#define Y_MIN_THD (YC_GAIN_BASE+(0x014))
#endif

563
general/package/xiongmai-osdrv-xm530/files/include/xm/xm510_isp.h
View File

@ -1,563 +0,0 @@
#ifndef _XM510_REG_
#define _XM510_REG_
#define DDR_BASE_ADDR (0x80000000)
#define VIDOEMODE_BASE 0x40000000
#define VIDOEMODE_DECODE_SEL (VIDOEMODE_BASE+0x000)
#define VI_VH_NUM (VIDOEMODE_BASE+0x090)
#define VI_VH_ALL (VIDOEMODE_BASE+0x094)
// DPC
#define SDPC_BASE 0x40003000
#define SDPC_CLK_SW (SDPC_BASE+0x000)
#define SDPC_SRAMADDR_CLR (SDPC_BASE+0x004)
#define SDPC_SRAMADDR_DAT (SDPC_BASE+0x008)
#define SDPC_TEST_ENABLE (SDPC_BASE+0x00C)
#define DDPC_BASE 0x40023000
#define DDPC_MAX_THD (DDPC_BASE+0x000)
#define DDPC_MIN_THD (DDPC_BASE+0x004)
#define DDPC_DIFF_THD (DDPC_BASE+0x008)
// BlackLevel
#define BLACKLEVEL_BASE 0x40004000
#define BLACKLEVEL_OFFSET_R (BLACKLEVEL_BASE+0x000)
#define BLACKLEVEL_OFFSET_G (BLACKLEVEL_BASE+0x004)
#define BLACKLEVEL_OFFSET_B (BLACKLEVEL_BASE+0x008)
// front Gamma
#define FRONTGAMMA_BASE 0x40005000
//LSC
#define LSC_BASE 0x40006000
#define LSC_CTRL (LSC_BASE+0x000)
//NR_2D
#define NR_2D_BASE 0x40020000
#define NR_2D_FLT_EN (NR_2D_BASE + 0x018)
#define NR_2D_THDL_REG (NR_2D_BASE + 0x000)
#define NR_2D_THDH_REG (NR_2D_BASE + 0x004)
#define NR_2D_COEF_REG (NR_2D_BASE + 0x008)
#define NR_2D_GMIN_REG (NR_2D_BASE + 0x00C)
#define NR_2D_COEF_SEL_REG (NR_2D_BASE + 0x010)
#define NR_2D_DELTA_THD (NR_2D_BASE + 0x014)
//NR_3D
#define NR_3D_BASE 0x40040000
#define NR_3D_DENOSIE_CTL (NR_3D_BASE + 0x000)
#define NR_3D_RAMP (NR_3D_BASE + 0x004)
#define NR_3D_G1AMP (NR_3D_BASE + 0x008)
#define NR_3D_G2AMP (NR_3D_BASE + 0x00C)
#define NR_3D_BAMP (NR_3D_BASE + 0x010)
#define NR_3D_ERR_SFT (NR_3D_BASE + 0x014)
#define NR_3D_NR_LEVEL (NR_3D_BASE + 0x018)
#define NR_3D_YFLD_SPACE (NR_3D_BASE + 0x030)
#define NR_3D_BFLD_SPACE (NR_3D_BASE + 0x034)
#define NR_3D_DFT_YSADDR0 (NR_3D_BASE + 0x038)
#define NR_3D_DFT_ESADDR0 (NR_3D_BASE + 0x03C)
#define NR_3D_DIG_E1 (NR_3D_BASE + 0x020)
#define NR_3D_DIG_E2 (NR_3D_BASE + 0x024)
#define NR_3D_DIG_E3 (NR_3D_BASE + 0x028)
#define NR_3D_ERR_PAR (NR_3D_BASE + 0x040)
#define NR_3D_BAYER_PAR (NR_3D_BASE + 0x050)
#define NR_3D_DDR_HNUM (NR_3D_BASE + 0x0D0)
#define NR_3D_ACTIVE_HNUM (NR_3D_BASE + 0x0D4)
#define NR_3D_YCTRL_ERR70 (NR_3D_BASE + 0x0D8)
#define NR_3D_YCTRL_ERRF8 (NR_3D_BASE + 0x0DC)
#define NR_3D_DFT_BSADDR0 (NR_3D_BASE + 0x0A0)
#define NR_3D_DFT_BSADDR1 (NR_3D_BASE + 0x0A4)
#define NR_3D_DFT_BSADDR2 (NR_3D_BASE + 0x0A8)
#define NR_3D_DFT_BSADDR3 (NR_3D_BASE + 0x0AC)
#define NR_3D_DFT_BSADDR4 (NR_3D_BASE + 0x0B0)
#define NR_3D_DFT_BSADDR5 (NR_3D_BASE + 0x0B4)
#define NR_3D_DFT_BSADDR6 (NR_3D_BASE + 0x0B8)
#define NR_3D_DFT_BSADDR7 (NR_3D_BASE + 0x0BC)
#define NR_3D_WINERR_HBEGIN (NR_3D_BASE + 0x120)
#define NR_3D_WINERR_HEND (NR_3D_BASE + 0x124)
#define NR_3D_WINERR_VBEGIN (NR_3D_BASE + 0x128)
#define NR_3D_WINERR_VEND (NR_3D_BASE + 0x12C)
#define NR_3D_WINERR_RSHIFT (NR_3D_BASE + 0x140)
#define NR_3D_WINERR_LEVEL (NR_3D_BASE + 0x144)
#define NR_3D_CHANGE_POINT (NR_3D_BASE + 0x148)
#define NR_3D_FLT2D_PAR (NR_3D_BASE + 0x14C)
//Bayer_Dec
#define BD_BASE 0x40050000
#define BD_PIC_ALL_PIXELS (BD_BASE+0x000)
#define BD_PIC_ALL_LINES (BD_BASE+0x004)
#define BD_PIC_HNUM (BD_BASE+0x008)
#define BD_PIC_VNUM (BD_BASE+0x00C)
#define BD_PASSTHROUGH_MODE1 (BD_BASE+0x010)
#define BD_PASSTHROUGH_MODE2 (BD_BASE+0x014)
//VideoFetch
#define VF_BASE 0x40051000
#define VF_BAYER_ADDR0 (VF_BASE+0x000)
#define VF_BAYER_ADDR1 (VF_BASE+0x004)
#define VF_BAYER_ADDR2 (VF_BASE+0x008)
#define VF_BAYER_ADDR3 (VF_BASE+0x00C)
#define VF_BAYER_ADDR4 (VF_BASE+0x010)
#define VF_BAYER_ADDR5 (VF_BASE+0x014)
#define VF_BAYER_ADDR6 (VF_BASE+0x018)
#define VF_BAYER_ADDR7 (VF_BASE+0x01C)
#define VF_BAYER_ADDR0_END (VF_BASE+0x020)
#define VF_BAYER_ADDR1_END (VF_BASE+0x024)
#define VF_BAYER_ADDR2_END (VF_BASE+0x028)
#define VF_BAYER_ADDR3_END (VF_BASE+0x02C)
#define VF_BAYER_ADDR4_END (VF_BASE+0x030)
#define VF_BAYER_ADDR5_END (VF_BASE+0x034)
#define VF_BAYER_ADDR6_END (VF_BASE+0x038)
#define VF_BAYER_ADDR7_END (VF_BASE+0x03C)
#define VF_LINE_ADDR_INC (VF_BASE+0x040)
#define VF_BAYER_INV (VF_BASE+0x044)
#define VF_TOTAL_FRAME_NUM (VF_BASE+0x048)
#define VF_LINE_NUM_PIX (VF_BASE+0x04C)
#define VF_ENABLE (VF_BASE+0x050)
//AWB
#define AWB_BASE 0x40010000
#define AWB_FRONTGAIN_R (AWB_BASE + 0x5000)
#define AWB_FRONTGAIN_G (AWB_BASE + 0x5004)
#define AWB_FRONTGAIN_B (AWB_BASE + 0x5008)
#define AWB_BACKGAIN_RGAIN_RR (AWB_BASE + 0x0000)
#define AWB_BACKGAIN_RGAIN_RG (AWB_BASE + 0x0004)
#define AWB_BACKGAIN_RGAIN_BG (AWB_BASE + 0x0008)
#define AWB_BACKGAIN_RGAIN_BB (AWB_BASE + 0x000C)
#define AWB_BACKGAIN_BGAIN_RR (AWB_BASE + 0x0010)
#define AWB_BACKGAIN_BGAIN_RG (AWB_BASE + 0x0014)
#define AWB_BACKGAIN_BGAIN_BG (AWB_BASE + 0x0018)
#define AWB_BACKGAIN_BGAIN_BB (AWB_BASE + 0x001C)
#define AWB_BACKGAIN_LIMITMAX (AWB_BASE + 0x0020)
#define AWB_BACKGAIN_LIMITMIN (AWB_BASE + 0x0024)
#define AWB_CSM_BUF_SW (AWB_BASE+0x1000)
#define AWB_CSM_BUF_SW_STATE (AWB_BASE+0x1004)
#define AWB_CSM_R_OFST_REG0 (AWB_BASE+0x1040)
#define AWB_CSM_R1_COEF_REG0 (AWB_BASE+0x1044)
#define AWB_CSM_R2_COEF_REG0 (AWB_BASE+0x1048)
#define AWB_CSM_R3_COEF_REG0 (AWB_BASE+0x104C)
#define AWB_CSM_G_OFST_REG0 (AWB_BASE+0x1050)
#define AWB_CSM_G1_COEF_REG0 (AWB_BASE+0x1054)
#define AWB_CSM_G2_COEF_REG0 (AWB_BASE+0x1058)
#define AWB_CSM_G3_COEF_REG0 (AWB_BASE+0x105C)
#define AWB_CSM_B_OFST_REG0 (AWB_BASE+0x1060)
#define AWB_CSM_B1_COEF_REG0 (AWB_BASE+0x1064)
#define AWB_CSM_B2_COEF_REG0 (AWB_BASE+0x1068)
#define AWB_CSM_B3_COEF_REG0 (AWB_BASE+0x106C)
#define AWB_CSM_R_OFST_REG1 (AWB_BASE+0x1080)
#define AWB_CSM_R1_COEF_REG1 (AWB_BASE+0x1084)
#define AWB_CSM_R2_COEF_REG1 (AWB_BASE+0x1088)
#define AWB_CSM_R3_COEF_REG1 (AWB_BASE+0x108C)
#define AWB_CSM_G_OFST_REG1 (AWB_BASE+0x1090)
#define AWB_CSM_G1_COEF_REG1 (AWB_BASE+0x1094)
#define AWB_CSM_G2_COEF_REG1 (AWB_BASE+0x1098)
#define AWB_CSM_G3_COEF_REG1 (AWB_BASE+0x109C)
#define AWB_CSM_B_OFST_REG1 (AWB_BASE+0x10A0)
#define AWB_CSM_B1_COEF_REG1 (AWB_BASE+0x10A4)
#define AWB_CSM_B2_COEF_REG1 (AWB_BASE+0x10A8)
#define AWB_CSM_B3_COEF_REG1 (AWB_BASE+0x10AC)
#define AWB_GAMMA30_BUF_SW (AWB_BASE + 0x2000)
#define AWB_GAMMA30_SW_STATE (AWB_BASE + 0x2004)
#define AWB_GAMMA30_LINE0_DAT0 (AWB_BASE + 0x2040)
#define AWB_GAMMA30_LINE1_DAT0 (AWB_BASE + 0x20C0)
#define AWB_RGBMAX_REG (AWB_BASE + 0x500C)
// AWB (RGB2YC)
#define AWB_RGB2YC_COEF_Y1 (AWB_BASE + 0x3000)
#define AWB_RGB2YC_COEF_Y2 (AWB_BASE + 0x3004)
#define AWB_RGB2YC_COEF_Y3 (AWB_BASE + 0x3008)
#define AWB_RGB2YC_COEF_CB1 (AWB_BASE + 0x300C)
#define AWB_RGB2YC_COEF_CB2 (AWB_BASE + 0x3010)
#define AWB_RGB2YC_COEF_CB3 (AWB_BASE + 0x3014)
#define AWB_RGB2YC_COEF_CR1 (AWB_BASE + 0x3018)
#define AWB_RGB2YC_COEF_CR2 (AWB_BASE + 0x301C)
#define AWB_RGB2YC_COEF_CR3 (AWB_BASE + 0x3020)
#define AWB_RGB2YC_OFST_Y (AWB_BASE + 0x3024)
#define AWB_RGB2YC_OFST_CB (AWB_BASE + 0x3028)
#define AWB_RGB2YC_OFST_CR (AWB_BASE + 0x302C)
#define AWB_WDW_VBEGIN (AWB_BASE + 0x4000)
#define AWB_WDW_VEND (AWB_BASE + 0x4004)
#define AWB_WDW_HBEGIN (AWB_BASE + 0x4008)
#define AWB_WDW_HEND (AWB_BASE + 0x400C)
#define AWB_FACT_LH (AWB_BASE + 0x4040)
#define AWB_FACT_LV (AWB_BASE + 0x4044)
#define AWB_FACT_L45 (AWB_BASE + 0x4048)
#define AWB_FACT_L135 (AWB_BASE + 0x404C)
#define AWB_FACT_RGBTHD (AWB_BASE + 0x4050)
#define AWB_FACT_YTHD (AWB_BASE + 0x4054)
#define AWB_FACT_KCBCR1 (AWB_BASE + 0x4058)
#define AWB_FACT_KCBCR2 (AWB_BASE + 0x405C)
#define AWB_FACT_KCBCR3 (AWB_BASE + 0x4060)
#define AWB_FACT_KCBCR4 (AWB_BASE + 0x4064)
#define AWB_CH1_M_WPCNT (AWB_BASE + 0x40C0)
#define AWB_CH1_M_CBSUM (AWB_BASE + 0x40C4)
#define AWB_CH1_M_CRSUM (AWB_BASE + 0x40C8)
#define AWB_CH2_M_WPCNT (AWB_BASE + 0x4100)
#define AWB_CH2_M_CBSUM (AWB_BASE + 0x4104)
#define AWB_CH2_M_CRSUM (AWB_BASE + 0x4108)
#define AWB_CH3_M_WPCNT (AWB_BASE + 0x4140)
#define AWB_CH3_M_CBSUM (AWB_BASE + 0x4144)
#define AWB_CH3_M_CRSUM (AWB_BASE + 0x4148)
#define AWB_CH4_M_WPCNT (AWB_BASE + 0x4180)
#define AWB_CH4_M_CBSUM (AWB_BASE + 0x4184)
#define AWB_CH4_M_CRSUM (AWB_BASE + 0x4188)
//AF
#define AF_BASE 0x40021000
#define AF_WDW0_VBEGIN (AF_BASE + 0x000)
#define AF_WDW0_VEND (AF_BASE + 0x004)
#define AF_WDW0_HBEGIN (AF_BASE + 0x008)
#define AF_WDW0_HEND (AF_BASE + 0x00C)
#define AF_WDW0_HZ (AF_BASE + 0x094)
//AE
#define AE_BASEADDR 0x40030000
#define AE_WINDOW_VSTART (AE_BASEADDR + 0x3000)
#define AE_WINDOW_HSTART (AE_BASEADDR + 0x3020)
#define AE_WINDOWY_ROW1 (AE_BASEADDR + 0x3100)
#define AE_WINDOWY_ROW2 (AE_BASEADDR + 0x311C)
#define AE_WINDOWY_ROW3 (AE_BASEADDR + 0x3140)
#define AE_WINDOWY_ROW4 (AE_BASEADDR + 0x315C)
#define AE_WINDOWY_ROW5 (AE_BASEADDR + 0x3180)
#define AE_WINDOWY_ROW6 (AE_BASEADDR + 0x319C)
#define AE_WINDOWY_ROW7 (AE_BASEADDR + 0x31C0)
#define AE_HIST_COUNT (AE_BASEADDR + 0x3080)
// Demosaic
#define DEMOSAIC_BASE 0x40052000
#define DEMOSAIC_G_HOFST (DEMOSAIC_BASE + 0x000)
#define DEMOSAIC_DHV_OFST (DEMOSAIC_BASE + 0x004)
#define DEMOSAIC_DHV_K (DEMOSAIC_BASE + 0x008)
// CSM
#define CSM_GAMMA_BYPASS 0x40060004
#define CSM_BASE 0x40061000
#define CSM_BUF_SW (CSM_BASE+0x000)
#define CSM_BUF_SW_STATE (CSM_BASE+0x004)
#define CSM_R_OFST_REG0 (CSM_BASE+0x040)
#define CSM_R1_COEF_REG0 (CSM_BASE+0x044)
#define CSM_R2_COEF_REG0 (CSM_BASE+0x048)
#define CSM_R3_COEF_REG0 (CSM_BASE+0x04C)
#define CSM_G_OFST_REG0 (CSM_BASE+0x050)
#define CSM_G1_COEF_REG0 (CSM_BASE+0x054)
#define CSM_G2_COEF_REG0 (CSM_BASE+0x058)
#define CSM_G3_COEF_REG0 (CSM_BASE+0x05C)
#define CSM_B_OFST_REG0 (CSM_BASE+0x060)
#define CSM_B1_COEF_REG0 (CSM_BASE+0x064)
#define CSM_B2_COEF_REG0 (CSM_BASE+0x068)
#define CSM_B3_COEF_REG0 (CSM_BASE+0x06C)
#define CSM_R_OFST_REG1 (CSM_BASE+0x080)
#define CSM_R1_COEF_REG1 (CSM_BASE+0x084)
#define CSM_R2_COEF_REG1 (CSM_BASE+0x088)
#define CSM_R3_COEF_REG1 (CSM_BASE+0x08C)
#define CSM_G_OFST_REG1 (CSM_BASE+0x090)
#define CSM_G1_COEF_REG1 (CSM_BASE+0x094)
#define CSM_G2_COEF_REG1 (CSM_BASE+0x098)
#define CSM_G3_COEF_REG1 (CSM_BASE+0x09C)
#define CSM_B_OFST_REG1 (CSM_BASE+0x0A0)
#define CSM_B1_COEF_REG1 (CSM_BASE+0x0A4)
#define CSM_B2_COEF_REG1 (CSM_BASE+0x0A8)
#define CSM_B3_COEF_REG1 (CSM_BASE+0x0AC)
// Gamma60
#define GAMMA60_BASE 0x40062000
#define GAMMA60_BUF_SW (GAMMA60_BASE+0x000)
#define GAMMA60_BUF_SW_STATE (GAMMA60_BASE+0x004)
#define GAMMA60_LINE0_DAT0 (GAMMA60_BASE+0x040)
#define GAMMA60_LINE1_DAT0 (GAMMA60_BASE+0x140)
// RGB2YC
#define RGB2YC_BASE 0x40065000
// Demoire
#define DEMOIRE_BASE 0x40067000
#define DEMOIRE_BYPASS (DEMOIRE_BASE+0x018)
#define DEMOIRE_V_THD (DEMOIRE_BASE+0x000)
#define DEMOIRE_KV (DEMOIRE_BASE+0x004)
#define DEMOIRE_DF_THD_MAX (DEMOIRE_BASE+0x008)
#define DEMOIRE_DF_THD_MIN (DEMOIRE_BASE+0x00C)
#define DEMOIRE_GAIN_MIN (DEMOIRE_BASE+0x010)
#define DEMOIRE_KC (DEMOIRE_BASE+0x014)
// Upscaler
#define UPSCALER_BASE 0x40070000
#define UPSCALER_XDELTA (UPSCALER_BASE+0x000)
#define UPSCALER_YDELTA (UPSCALER_BASE+0x004)
#define UPSCALER_XSTART0 (UPSCALER_BASE+0x008)
#define UPSCALER_YSTART0 (UPSCALER_BASE+0x00C)
#define UPSCALER_XPHI0 (UPSCALER_BASE+0x010)
#define UPSCALER_YPHI0 (UPSCALER_BASE+0x014)
#define UPSCALER_XPHI_OFFSET (UPSCALER_BASE+0x018)
#define UPSCALER_YPHI_OFFSET (UPSCALER_BASE+0x01C)
#define UPSCALER_XSTART_OFFSET (UPSCALER_BASE+0x020)
#define UPSCALER_YSTART_OFFSET (UPSCALER_BASE+0x024)
#define UPSCALER_TOTAL_HNUM (UPSCALER_BASE+0x030)
#define UPSCALER_TOTAL_VNUM (UPSCALER_BASE+0x034)
#define UPSCALER_ACTIVE_HNUM (UPSCALER_BASE+0x038)
#define UPSCALER_ACTIVE_VNUM (UPSCALER_BASE+0x03C)
// CC
#define CC_BASE 0x40071000
#define CC_EN_REG (CC_BASE+0x000)
#define CC_HUE_OFST (CC_BASE+0x018)
#define CC_HS_TRAN_DAT0 (CC_BASE+0x0E4)
#define CC_HS_TRAN_DAT1 (CC_BASE+0x0E8)
#define CC_HH_H1_SATRT (CC_BASE+0x200)
#define CC_HH_H1_END (CC_BASE+0x204)
#define CC_HH_H1_MAX1 (CC_BASE+0x208)
#define CC_HH_H1_MAX2 (CC_BASE+0x20C)
#define CC_HH_H1_DMAX (CC_BASE+0x210)
#define CC_HH_H1_K1 (CC_BASE+0x214)
#define CC_HH_H1_K2 (CC_BASE+0x218)
#define CC_HH_H2_SATRT (CC_BASE+0x21C)
#define CC_HH_H2_END (CC_BASE+0x220)
#define CC_HH_H2_MAX1 (CC_BASE+0x224)
#define CC_HH_H2_MAX2 (CC_BASE+0x228)
#define CC_HH_H2_DMAX (CC_BASE+0x22C)
#define CC_HH_H2_K1 (CC_BASE+0x230)
#define CC_HH_H2_K2 (CC_BASE+0x234)
#define CC_HH_H3_SATRT (CC_BASE+0x240)
#define CC_HH_H3_END (CC_BASE+0x244)
#define CC_HH_H3_MAX1 (CC_BASE+0x248)
#define CC_HH_H3_MAX2 (CC_BASE+0x24C)
#define CC_HH_H3_DMAX (CC_BASE+0x250)
#define CC_HH_H3_K1 (CC_BASE+0x254)
#define CC_HH_H3_K2 (CC_BASE+0x258)
#define CC_HH_H4_SATRT (CC_BASE+0x25C)
#define CC_HH_H4_END (CC_BASE+0x260)
#define CC_HH_H4_MAX1 (CC_BASE+0x264)
#define CC_HH_H4_MAX2 (CC_BASE+0x268)
#define CC_HH_H4_DMAX (CC_BASE+0x26C)
#define CC_HH_H4_K1 (CC_BASE+0x270)
#define CC_HH_H4_K2 (CC_BASE+0x274)
#define CC_HH_H5_SATRT (CC_BASE+0x280)
#define CC_HH_H5_END (CC_BASE+0x284)
#define CC_HH_H5_MAX1 (CC_BASE+0x288)
#define CC_HH_H5_MAX2 (CC_BASE+0x28C)
#define CC_HH_H5_DMAX (CC_BASE+0x290)
#define CC_HH_H5_K1 (CC_BASE+0x294)
#define CC_HH_H5_K2 (CC_BASE+0x298)
#define CC_HH_H6_SATRT (CC_BASE+0x29C)
#define CC_HH_H6_END (CC_BASE+0x2A0)
#define CC_HH_H6_MAX1 (CC_BASE+0x2A4)
#define CC_HH_H6_MAX2 (CC_BASE+0x2A8)
#define CC_HH_H6_DMAX (CC_BASE+0x2AC)
#define CC_HH_H6_K1 (CC_BASE+0x2B0)
#define CC_HH_H6_K2 (CC_BASE+0x2B4)
// Y_Gamma
#define YGAMMA_BASE 0x40072000
#define YGAMMA_BUF_SW (YGAMMA_BASE+0x000)
#define YGAMMA_BUF_SW_STATE (YGAMMA_BASE+0x004)
#define YGAMMA_LINE0_DAT0 (YGAMMA_BASE+0x040)
#define YGAMMA_LINE1_DAT0 (YGAMMA_BASE+0x180)
#define YHIST_BASE (0x40073000)
#define YHIST_CNT0 (YHIST_BASE+0x000)
#define CTRAN_BASE 0x40074000
// Sharpness
#define SHARPEN_BASE 0x40075000
#define SHARPEN_H00_SEL (SHARPEN_BASE+(0x04))
#define SHARPEN_KH1 (SHARPEN_BASE+(0x08))
#define SHARPEN_KL1 (SHARPEN_BASE+(0x0C))
#define SHARPEN_DMAX (SHARPEN_BASE+(0x010))
#define SHARPEN_KD (SHARPEN_BASE+(0x018))
#define SHARPEN_KD_MAX (SHARPEN_BASE+(0x01C))
#define SHARPEN_TRAN_DAT0 (SHARPEN_BASE+(0x020))
#define SHARPEN_YMTH1 (SHARPEN_BASE+(0x128))
#define SHARPEN_YMTH2 (SHARPEN_BASE+(0x12C))
#define SHARPEN_KKM (SHARPEN_BASE+(0x130))
#define SHARPEN_WM0 (SHARPEN_BASE+(0x134))
#define SHARPEN_WM1 (SHARPEN_BASE+(0x138))
#define SHARPEN_WM2 (SHARPEN_BASE+(0x13C))
#define SHARPEN_WM3 (SHARPEN_BASE+(0x140))
#define SHARPEN_WM4 (SHARPEN_BASE+(0x144))
#define SHARPEN_WM5 (SHARPEN_BASE+(0x148))
#define SHARPEN_KM0 (SHARPEN_BASE+(0x14c))
#define SHARPEN_YHTH1 (SHARPEN_BASE+(0x150))
#define SHARPEN_YHTH2 (SHARPEN_BASE+(0x154))
#define SHARPEN_KKH (SHARPEN_BASE+(0x158))
#define SHARPEN_WH0 (SHARPEN_BASE+(0x15C))
#define SHARPEN_WH1 (SHARPEN_BASE+(0x160))
#define SHARPEN_WH2 (SHARPEN_BASE+(0x164))
#define SHARPEN_WH3 (SHARPEN_BASE+(0x168))
#define SHARPEN_WH4 (SHARPEN_BASE+(0x16C))
#define SHARPEN_WH5 (SHARPEN_BASE+(0x170))
#define SHARPEN_KH0 (SHARPEN_BASE+(0x174))
#define SHARPEN_YMDTH1 (SHARPEN_BASE+(0x178))
#define SHARPEN_YMDTH2 (SHARPEN_BASE+(0x17C))
#define SHARPEN_KKMD (SHARPEN_BASE+(0x180))
#define SHARPEN_WMD0 (SHARPEN_BASE+(0x184))
#define SHARPEN_WMD1 (SHARPEN_BASE+(0x188))
#define SHARPEN_WMD2 (SHARPEN_BASE+(0x18C))
#define SHARPEN_WMD3 (SHARPEN_BASE+(0x190))
#define SHARPEN_WMD4 (SHARPEN_BASE+(0x194))
#define SHARPEN_WMD5 (SHARPEN_BASE+(0x198))
#define SHARPEN_KMD_MAX (SHARPEN_BASE+(0x19C))
#define SHARPEN_YHDTH1 (SHARPEN_BASE+(0x1A0))
#define SHARPEN_YHDTH2 (SHARPEN_BASE+(0x1A4))
#define SHARPEN_KKHD (SHARPEN_BASE+(0x1A8))
#define SHARPEN_WHD0 (SHARPEN_BASE+(0x1AC))
#define SHARPEN_WHD1 (SHARPEN_BASE+(0x1B0))
#define SHARPEN_WHD2 (SHARPEN_BASE+(0x1B4))
#define SHARPEN_WHD3 (SHARPEN_BASE+(0x1B8))
#define SHARPEN_WHD4 (SHARPEN_BASE+(0x1BC))
#define SHARPEN_WHD5 (SHARPEN_BASE+(0x1C0))
#define SHARPEN_KHD_MAX (SHARPEN_BASE+(0x1C4))
#define SHARPEN_KCMIN (SHARPEN_BASE+(0x1E8))
#define SHARPEN_ENABLE (SHARPEN_BASE+(0x204))
#define SHARPEN_CBCR_ENABLE (SHARPEN_BASE+(0x208))
// YC_Gain
#define YC_GAIN_BASE 0x40076000
#define Y_GAIN (YC_GAIN_BASE+(0x000))
#define CB_GAIN (YC_GAIN_BASE+(0x004))
#define CR_GAIN (YC_GAIN_BASE+(0x008))
// AWB2
#define AWB2_BASE (0x40016000)
#define AWB2_WDW_PIXL0 (AWB2_BASE+0x000)
#define AWB2_WDW_PIXL1 (AWB2_BASE+0x004)
#define AWB2_WDW_PIXL2 (AWB2_BASE+0x008)
#define AWB2_WDW_PIXL3 (AWB2_BASE+0x00C)
#define AWB2_WDW_PIXL4 (AWB2_BASE+0x010)
#define AWB2_WDW_PIXL5 (AWB2_BASE+0x014)
#define AWB2_WDW_PIXL6 (AWB2_BASE+0x018)
#define AWB2_WDW_PIXL7 (AWB2_BASE+0x01C)
#define AWB2_WDW_PIXL8 (AWB2_BASE+0x020)
#define AWB2_WDW_PIXL9 (AWB2_BASE+0x024)
#define AWB2_WDW_PIXL10 (AWB2_BASE+0x028)
#define AWB2_WDW_PIXL11 (AWB2_BASE+0x02C)
#define AWB2_WDW_PIXL12 (AWB2_BASE+0x030)
#define AWB2_WDW_PIXL13 (AWB2_BASE+0x034)
#define AWB2_WDW_PIXL14 (AWB2_BASE+0x038)
#define AWB2_WDW_PIXL15 (AWB2_BASE+0x03C)
#define AWB2_WDW_PIXL16 (AWB2_BASE+0x040)
#define AWB2_WDW_PIXL17 (AWB2_BASE+0x044)
#define AWB2_WDW_PIXL18 (AWB2_BASE+0x048)
#define AWB2_WDW_PIXL19 (AWB2_BASE+0x04C)
#define AWB2_WDW_PIXL20 (AWB2_BASE+0x050)
#define AWB2_WDW_PIXL21 (AWB2_BASE+0x054)
#define AWB2_WDW_PIXL22 (AWB2_BASE+0x058)
#define AWB2_WDW_PIXL23 (AWB2_BASE+0x05C)
#define AWB2_WDW_PIXL24 (AWB2_BASE+0x060)
#define AWB2_WDW_PIXL25 (AWB2_BASE+0x064)
#define AWB2_WDW_PIXL26 (AWB2_BASE+0x068)
#define AWB2_WDW_PIXL27 (AWB2_BASE+0x06C)
#define AWB2_WDW_PIXL28 (AWB2_BASE+0x070)
#define AWB2_WDW_PIXL29 (AWB2_BASE+0x074)
#define AWB2_WDW_PIXL30 (AWB2_BASE+0x078)
#define AWB2_WDW_PIXL31 (AWB2_BASE+0x07C)
#define AWB2_WDW_PIXL32 (AWB2_BASE+0x080)
#define AWB2_WDW_LINE0 (AWB2_BASE+0x0C0)
#define AWB2_WDW_LINE1 (AWB2_BASE+0x0C4)
#define AWB2_WDW_LINE2 (AWB2_BASE+0x0C8)
#define AWB2_WDW_LINE3 (AWB2_BASE+0x0CC)
#define AWB2_WDW_LINE4 (AWB2_BASE+0x0D0)
#define AWB2_WDW_LINE5 (AWB2_BASE+0x0D4)
#define AWB2_WDW_LINE6 (AWB2_BASE+0x0D8)
#define AWB2_WDW_LINE7 (AWB2_BASE+0x0DC)
#define AWB2_WDW_LINE8 (AWB2_BASE+0x0E0)
#define AWB2_WDW_LINE9 (AWB2_BASE+0x0E4)
#define AWB2_WDW_LINE10 (AWB2_BASE+0x0E8)
#define AWB2_WDW_LINE11 (AWB2_BASE+0x0EC)
#define AWB2_WDW_LINE12 (AWB2_BASE+0x0F0)
#define AWB2_WDW_LINE13 (AWB2_BASE+0x0F4)
#define AWB2_WDW_LINE14 (AWB2_BASE+0x0F8)
#define AWB2_WDW_LINE15 (AWB2_BASE+0x0FC)
#define AWB2_WDW_LINE16 (AWB2_BASE+0x100)
#define AWB2_SRAM_ADDR_RC (AWB2_BASE+0x140)
#define AWB2_SRAM_RD_EN (AWB2_BASE+0x144)
#define AWB2_R_INTG (AWB2_BASE+0x148)
#define AWB2_G_INTG (AWB2_BASE+0x14C)
#define AWB2_B_INTG (AWB2_BASE+0x150)
//PLL use to upscaler
#define PLL_BASE 0x20000000
#define PLL_SYSCTRLREG_LOCK (PLL_BASE+0x002C)
#define PLLB1_CTRL (PLL_BASE+0x000C)
#define PLLB2_CTRL (PLL_BASE+0x0010)
#define PLLB_CTRL (PLL_BASE+0x0014)
//Video Store
#define VSTORE_BASE 0x40080000
#define VSTORE_EN_CH1 (0x40080000+0x1034)
#define VSTORE_EN_CH2 (0x40080000+0x2034)
#define VSTORE_EN_CH3 (0x40080000+0x3034)
#endif

48
general/package/xiongmai-osdrv-xm530/files/include/xm/xm510_tmp.h
View File

@ -1,48 +0,0 @@
#ifndef _XM510_TMP_H_
#define _XM510_TMP_H_
#include "xm_type.h"
#include "xm_defines.h"
#ifdef SOC_SYSTEM
#include <stdio.h>
#endif
#define VI_BASE (0x30000000)
#define VI_H_BEGIN (VI_BASE+0x098)
#define VI_H_END (VI_BASE+0x09C)
#define VI_V_BEGIN (VI_BASE+0x0A0)
#define VI_V_END (VI_BASE+0x0A4)
/**For read the configinit */
#define FILENAME_NOTEXIST 0x02 /*配置文件名不存在*/
#define SECTIONNAME_NOTEXIST 0x03 /*节名不存在*/
#define KEYNAME_NOTEXIST 0x04 /*键名不存在*/
#define STRING_LENNOTEQUAL 0x05 /*两个字符串长度不同*/
#define STRING_NOTEQUAL 0x06 /*两个字符串内容不相同*/
#define STRING_EQUAL 0x00 /*两个字符串内容相同*/
#define KEYNUM 2
#define NCNUM 32
void SysDelay_ms(XM_S32 ms);
XM_S32 SysGetProductInfo(XM_PRODUCT_INFO *pstProductInfo);
#ifdef SOC_SYSTEM
int GetConfigIntValue(char *pInFileName,char *pInSectionName,const char (*pInKeyName)[NCNUM],char (*pOutKeyValue)[NCNUM]);
int GetConfigStringValue(char *pInFileName,char *pInSectionName,const char (*pInKeyName)[NCNUM],char (*pOutKeyValue)[NCNUM]);
int CompareString(char *pInStr1,char *pInStr2);
int GetKeyValue(FILE *fpConfig,const char (*pInKeyName)[NCNUM],char (*pOutKeyValue)[NCNUM]);
#endif
void CameraConfigInit(UPSCALER_CFG *gstvstdvp);
XM_U8 IrledConfigInit(void);
int string_get_value(const char *filename, const char *str, const char separate, char *value, char *raw);
XM_S32 VI_WinSet(XM_U8 u8Mode, XM_U8 u8Mirror, XM_U8 u8Flip,
XM_U16 u16ValH, XM_U16 u16ValV);
#endif

504
general/package/xiongmai-osdrv-xm530/files/include/xm/xm520_isp.h
View File

@ -1,504 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm520_isp.h
Version : Initial Draft
Author : XM Isp software group
Created : 2016/6/18
Description : The common data type defination
Function List :
History :
1.Date : 2016/6/18
Author : Ganwencao
Modification : creat
******************************************************************************/
#ifndef _XM520_REG_
#define _XM520_REG_
#define DDR_BASE_ADDR (0x80000000)
//pre_video
#define VIDOEMODE_BASE 0x40000000
#define VIDOEMODE_DECODE_SEL (VIDOEMODE_BASE+0x000)
#define VIDOEMODE_SLA_MAT_SEL (VIDOEMODE_BASE+0x004)
#define VIDOEMODE_DEC_DATA_SEL (VIDOEMODE_BASE+0x008)
// DPC
#define SDPC_BASE 0x40003000
#define SDPC_CLK_SW (SDPC_BASE+0x000)
#define SDPC_SRAMADDR_CLR (SDPC_BASE+0x004)
#define SDPC_SRAMADDR_DAT (SDPC_BASE+0x008)
#define SDPC_TEST_ENABLE (SDPC_BASE+0x00C)
#define DDPC_BASE 0x40023000
#define DDPC_MAX_THD (DDPC_BASE+0x000)
#define DDPC_MIN_THD (DDPC_BASE+0x004)
#define DDPC_DIFF_THD1 (DDPC_BASE+0x008)
#define DDPC_DIFF_THD2 (DDPC_BASE+0x00C)
// BlackLevel
#define BLACKLEVEL_BASE 0x40004000
#define BLACKLEVEL_OFFSET_R (BLACKLEVEL_BASE+0x000)
#define BLACKLEVEL_OFFSET_G (BLACKLEVEL_BASE+0x004)
#define BLACKLEVEL_OFFSET_B (BLACKLEVEL_BASE+0x008)
#define BLACKLEVEL_RGB_MAX (BLACKLEVEL_BASE+0x00C)
#define BLACKLEVEL_RGB_MIN (BLACKLEVEL_BASE+0x010)
// DIGTAL_GAIN
#define DIGITAL_GAIN (0x40005000+0x000)
//LSC
#define LSC_BASE 0x40006000
#define LSC_CTRL (LSC_BASE+0x000)
//AWB
#define AWB_BASE (0x40010000)
#define AWB_FRONTGAIN_R (AWB_BASE+0x0000)
#define AWB_FRONTGAIN_G (AWB_BASE+0x0004)
#define AWB_FRONTGAIN_B (AWB_BASE+0x0008)
#define AWB_RGBMAX_REG (AWB_BASE+0x000C)
#define AWB_RGBMIN_REG (AWB_BASE+0x0010)
#define AWB_WDW_PIXL0 (AWB_BASE+0x1000)
#define AWB_WDW_PIXL1 (AWB_BASE+0x1004)
#define AWB_WDW_PIXL2 (AWB_BASE+0x1008)
#define AWB_WDW_PIXL3 (AWB_BASE+0x100C)
#define AWB_WDW_PIXL4 (AWB_BASE+0x1010)
#define AWB_WDW_PIXL5 (AWB_BASE+0x1014)
#define AWB_WDW_PIXL6 (AWB_BASE+0x1018)
#define AWB_WDW_PIXL7 (AWB_BASE+0x101C)
#define AWB_WDW_PIXL8 (AWB_BASE+0x1020)
#define AWB_WDW_PIXL9 (AWB_BASE+0x1024)
#define AWB_WDW_PIXL10 (AWB_BASE+0x1028)
#define AWB_WDW_PIXL11 (AWB_BASE+0x102C)
#define AWB_WDW_PIXL12 (AWB_BASE+0x1030)
#define AWB_WDW_PIXL13 (AWB_BASE+0x1034)
#define AWB_WDW_PIXL14 (AWB_BASE+0x1038)
#define AWB_WDW_PIXL15 (AWB_BASE+0x103C)
#define AWB_WDW_PIXL16 (AWB_BASE+0x1040)
#define AWB_WDW_PIXL17 (AWB_BASE+0x1044)
#define AWB_WDW_PIXL18 (AWB_BASE+0x1048)
#define AWB_WDW_PIXL19 (AWB_BASE+0x104C)
#define AWB_WDW_PIXL20 (AWB_BASE+0x1050)
#define AWB_WDW_PIXL21 (AWB_BASE+0x1054)
#define AWB_WDW_PIXL22 (AWB_BASE+0x1058)
#define AWB_WDW_PIXL23 (AWB_BASE+0x105C)
#define AWB_WDW_PIXL24 (AWB_BASE+0x1060)
#define AWB_WDW_PIXL25 (AWB_BASE+0x1064)
#define AWB_WDW_PIXL26 (AWB_BASE+0x1068)
#define AWB_WDW_PIXL27 (AWB_BASE+0x106C)
#define AWB_WDW_PIXL28 (AWB_BASE+0x1070)
#define AWB_WDW_PIXL29 (AWB_BASE+0x1074)
#define AWB_WDW_PIXL30 (AWB_BASE+0x1078)
#define AWB_WDW_PIXL31 (AWB_BASE+0x107C)
#define AWB_WDW_PIXL32 (AWB_BASE+0x1080)
#define AWB_WDW_LINE0 (AWB_BASE+0x10C0)
#define AWB_WDW_LINE1 (AWB_BASE+0x10C4)
#define AWB_WDW_LINE2 (AWB_BASE+0x10C8)
#define AWB_WDW_LINE3 (AWB_BASE+0x10CC)
#define AWB_WDW_LINE4 (AWB_BASE+0x10D0)
#define AWB_WDW_LINE5 (AWB_BASE+0x10D4)
#define AWB_WDW_LINE6 (AWB_BASE+0x10D8)
#define AWB_WDW_LINE7 (AWB_BASE+0x10DC)
#define AWB_WDW_LINE8 (AWB_BASE+0x10E0)
#define AWB_WDW_LINE9 (AWB_BASE+0x10E4)
#define AWB_WDW_LINE10 (AWB_BASE+0x10E8)
#define AWB_WDW_LINE11 (AWB_BASE+0x10EC)
#define AWB_WDW_LINE12 (AWB_BASE+0x10F0)
#define AWB_WDW_LINE13 (AWB_BASE+0x10F4)
#define AWB_WDW_LINE14 (AWB_BASE+0x10F8)
#define AWB_WDW_LINE15 (AWB_BASE+0x10FC)
#define AWB_WDW_LINE16 (AWB_BASE+0x1100)
#define AWB_SRAM_ADDR_RC (AWB_BASE+0x1140)
#define AWB_SRAM_RD_EN (AWB_BASE+0x1144)
#define AWB_R_INTG (AWB_BASE+0x1148)
#define AWB_G_INTG (AWB_BASE+0x114C)
#define AWB_B_INTG (AWB_BASE+0x1150)
#define AWB_HIST_RGB_SEL (AWB_BASE+0x2000)
#define AWB_HIST_CNT0 (AWB_BASE+0x2040)
#define AWB_HIST_CNT1 (AWB_BASE+0x2044)
#define AWB_HIST_CNT2 (AWB_BASE+0x2048)
#define AWB_HIST_CNT3 (AWB_BASE+0x204C)
#define AWB_HIST_CNT4 (AWB_BASE+0x2050)
#define AWB_HIST_CNT5 (AWB_BASE+0x2054)
#define AWB_HIST_CNT6 (AWB_BASE+0x2058)
#define AWB_HIST_CNT7 (AWB_BASE+0x205C)
#define AWB_HIST_CNT8 (AWB_BASE+0x2060)
#define AWB_HIST_CNT9 (AWB_BASE+0x2064)
#define AWB_HIST_CNT10 (AWB_BASE+0x2068)
#define AWB_HIST_CNT11 (AWB_BASE+0x206C)
#define AWB_HIST_CNT12 (AWB_BASE+0x2070)
#define AWB_HIST_CNT13 (AWB_BASE+0x2074)
#define AWB_HIST_CNT14 (AWB_BASE+0x2078)
#define AWB_HIST_CNT15 (AWB_BASE+0x207C)
#define AWB_HIST_CNT16 (AWB_BASE+0x2080)
#define AWB_HIST_CNT17 (AWB_BASE+0x2084)
#define AWB_HIST_CNT18 (AWB_BASE+0x2088)
#define AWB_HIST_CNT19 (AWB_BASE+0x208C)
#define AWB_HIST_CNT20 (AWB_BASE+0x2090)
#define AWB_HIST_CNT21 (AWB_BASE+0x2094)
#define AWB_HIST_CNT22 (AWB_BASE+0x2098)
#define AWB_HIST_CNT23 (AWB_BASE+0x209C)
#define AWB_HIST_CNT24 (AWB_BASE+0x20A0)
#define AWB_HIST_CNT25 (AWB_BASE+0x20A4)
#define AWB_HIST_CNT26 (AWB_BASE+0x20A8)
#define AWB_HIST_CNT27 (AWB_BASE+0x20AC)
#define AWB_HIST_CNT28 (AWB_BASE+0x20B0)
#define AWB_HIST_CNT29 (AWB_BASE+0x20B4)
#define AWB_HIST_CNT30 (AWB_BASE+0x20B8)
#define AWB_HIST_CNT31 (AWB_BASE+0x20BC)
//NR_2D
#define NR_2D_BASE 0x40020000
#define NR_2D_THDL_REG (NR_2D_BASE + 0x000)
#define NR_2D_THDH_REG (NR_2D_BASE + 0x004)
#define NR_2D_COEF_REG (NR_2D_BASE + 0x008)
#define NR_2D_GMIN_REG (NR_2D_BASE + 0x00C)
#define NR_2D_DELTA_THD (NR_2D_BASE + 0x010)
#define NR_2D_G_COEF1 (NR_2D_BASE + 0x014)
#define NR_2D_G_COEF2 (NR_2D_BASE + 0x018)
#define NR_2D_G_COEF3 (NR_2D_BASE + 0x01C)
#define NR_2D_G_COEF4 (NR_2D_BASE + 0x020)
#define NR_2D_RB_COEF1 (NR_2D_BASE + 0x024)
#define NR_2D_RB_COEF2 (NR_2D_BASE + 0x028)
#define NR_2D_RB_COEF3 (NR_2D_BASE + 0x02C)
#define NR_2D_H_SEL (NR_2D_BASE + 0x030)
#define NR_2D_FLT_EN (NR_2D_BASE + 0x034)
//AF
#define AF_BASE 0x40021000
#define AF_WDW0_VBEGIN (AF_BASE + 0x000)
#define AF_WDW0_VEND (AF_BASE + 0x004)
#define AF_WDW0_HBEGIN (AF_BASE + 0x008)
#define AF_WDW0_HEND (AF_BASE + 0x00C)
#define AF_WDW0_HZ (AF_BASE + 0x094)
#if 1 //XM520
//NR_3D
#define NR_3D_BASE 0x40040000
#define NR_3D_DENOSIE_CTL (NR_3D_BASE + 0x000)
#define NR_3D_ERR_SFT (NR_3D_BASE + 0x014)
#define NR_3D_YFLD_SPACE (NR_3D_BASE + 0x030)
#define NR_3D_BFLD_SPACE (NR_3D_BASE + 0x034)
#define NR_3D_DFT_YSADDR0 (NR_3D_BASE + 0x038)
#define NR_3D_DFT_ESADDR0 (NR_3D_BASE + 0x03C)
#define NR_3D_DIG_E1 (NR_3D_BASE + 0x020)
#define NR_3D_DIG_E2 (NR_3D_BASE + 0x024)
#define NR_3D_DIG_E3 (NR_3D_BASE + 0x028)
#define NR_3D_ERR_PAR (NR_3D_BASE + 0x040)
#define NR_3D_BAYER_PAR (NR_3D_BASE + 0x050)
#define NR_3D_DFT_BSADDR0 (NR_3D_BASE + 0x0A0)
#define NR_3D_DFT_BSADDR1 (NR_3D_BASE + 0x0A4)
#define NR_3D_DFT_BSADDR2 (NR_3D_BASE + 0x0A8)
#define NR_3D_DFT_BSADDR3 (NR_3D_BASE + 0x0AC)
#define NR_3D_DFT_BSADDR4 (NR_3D_BASE + 0x0B0)
#define NR_3D_DFT_BSADDR5 (NR_3D_BASE + 0x0B4)
#define NR_3D_DFT_BSADDR6 (NR_3D_BASE + 0x0B8)
#define NR_3D_DFT_BSADDR7 (NR_3D_BASE + 0x0BC)
#define NR_3D_DDR_BHNUM (NR_3D_BASE + 0x0C8)
#define NR_3D_DDR_YHNUM (NR_3D_BASE + 0x0CC)
#define NR_3D_DDR_EHNUM (NR_3D_BASE + 0x0D0)
#define NR_3D_ACTIVE_HNUM (NR_3D_BASE + 0x0D4)
#define NR_3D_ACTIVE_VNUM (NR_3D_BASE + 0x0D8)
#define NR_3D_WINERR_HBEGIN (NR_3D_BASE + 0x120)
#define NR_3D_WINERR_HEND (NR_3D_BASE + 0x124)
#define NR_3D_WINERR_VBEGIN (NR_3D_BASE + 0x128)
#define NR_3D_WINERR_VEND (NR_3D_BASE + 0x12C)
#define NR_3D_WINERR_RSHIFT (NR_3D_BASE + 0x140)
#define NR_3D_WINERR_LEVEL (NR_3D_BASE + 0x144)
#define NR_3D_CHANGE_POINT (NR_3D_BASE + 0x148)
#define NR_3D_FLT2D_PAR (NR_3D_BASE + 0x14C)
#else// This is XM510 code,just for test
//NR_3D
#define NR_3D_BASE 0x40040000
#define NR_3D_DENOSIE_CTL (NR_3D_BASE + 0x000)
#define NR_3D_ERR_SFT (NR_3D_BASE + 0x014)
#define NR_3D_NR_LEVEL (NR_3D_BASE + 0x018)
#define NR_3D_YFLD_SPACE (NR_3D_BASE + 0x030)
#define NR_3D_BFLD_SPACE (NR_3D_BASE + 0x034)
#define NR_3D_DFT_YSADDR0 (NR_3D_BASE + 0x038)
#define NR_3D_DFT_ESADDR0 (NR_3D_BASE + 0x03C)
#define NR_3D_DIG_E1 (NR_3D_BASE + 0x020)
#define NR_3D_DIG_E2 (NR_3D_BASE + 0x024)
#define NR_3D_DIG_E3 (NR_3D_BASE + 0x028)
#define NR_3D_ERR_PAR (NR_3D_BASE + 0x040)
#define NR_3D_BAYER_PAR (NR_3D_BASE + 0x050)
#define NR_3D_DDR_HNUM (NR_3D_BASE + 0x0D0)
#define NR_3D_ACTIVE_HNUM (NR_3D_BASE + 0x0D4)
#define NR_3D_YCTRL_ERR70 (NR_3D_BASE + 0x0D8)
#define NR_3D_YCTRL_ERRF8 (NR_3D_BASE + 0x0DC)
#define NR_3D_DFT_BSADDR0 (NR_3D_BASE + 0x0A0)
#define NR_3D_DFT_BSADDR1 (NR_3D_BASE + 0x0A4)
#define NR_3D_DFT_BSADDR2 (NR_3D_BASE + 0x0A8)
#define NR_3D_DFT_BSADDR3 (NR_3D_BASE + 0x0AC)
#define NR_3D_DFT_BSADDR4 (NR_3D_BASE + 0x0B0)
#define NR_3D_DFT_BSADDR5 (NR_3D_BASE + 0x0B4)
#define NR_3D_DFT_BSADDR6 (NR_3D_BASE + 0x0B8)
#define NR_3D_DFT_BSADDR7 (NR_3D_BASE + 0x0BC)
#define NR_3D_WINERR_HBEGIN (NR_3D_BASE + 0x120)
#define NR_3D_WINERR_HEND (NR_3D_BASE + 0x124)
#define NR_3D_WINERR_VBEGIN (NR_3D_BASE + 0x128)
#define NR_3D_WINERR_VEND (NR_3D_BASE + 0x12C)
#define NR_3D_WINERR_RSHIFT (NR_3D_BASE + 0x140)
#define NR_3D_WINERR_LEVEL (NR_3D_BASE + 0x144)
#define NR_3D_CHANGE_POINT (NR_3D_BASE + 0x148)
#define NR_3D_FLT2D_PAR (NR_3D_BASE + 0x14C)
#endif
// Demosaic
#define DEMOSAIC_BASE 0x40052000
#define DEMOSAIC_G_HOFST (DEMOSAIC_BASE + 0x000)
#define DEMOSAIC_DHV_OFST (DEMOSAIC_BASE + 0x004)
#define DEMOSAIC_DHV_K (DEMOSAIC_BASE + 0x008)
// CSM
#define CSM_BASE 0x40060000
#define CSM_RGB_MAX (CSM_BASE+0x000)
#define CSM_RGB_MIN (CSM_BASE+0x004)
#define CSM_R_OFST_REG (CSM_BASE+0x040)
#define CSM_R1_COEF_REG (CSM_BASE+0x044)
#define CSM_R2_COEF_REG (CSM_BASE+0x048)
#define CSM_R3_COEF_REG (CSM_BASE+0x04C)
#define CSM_G_OFST_REG (CSM_BASE+0x050)
#define CSM_G1_COEF_REG (CSM_BASE+0x054)
#define CSM_G2_COEF_REG (CSM_BASE+0x058)
#define CSM_G3_COEF_REG (CSM_BASE+0x05C)
#define CSM_B_OFST_REG (CSM_BASE+0x060)
#define CSM_B1_COEF_REG (CSM_BASE+0x064)
#define CSM_B2_COEF_REG (CSM_BASE+0x068)
#define CSM_B3_COEF_REG (CSM_BASE+0x06C)
// Gamma60
#define GAMMA60_BASE 0x40061000
#define GAMMA60_BUF_SW (GAMMA60_BASE+0x000)
#define GAMMA60_BUF_SW_STATE (GAMMA60_BASE+0x004)
#define GAMMA60_LINE0_DAT0 (GAMMA60_BASE+0x040)
#define GAMMA60_LINE1_DAT0 (GAMMA60_BASE+0x140)
// RGB2YC
#define RGB2YC_BASE 0x00A62000
// Demoire
#define DEMOIRE_BASE 0x40063000
#define DEMOIRE_V_THD (DEMOIRE_BASE+0x000)
#define DEMOIRE_KV (DEMOIRE_BASE+0x004)
#define DEMOIRE_DF_THD_MAX (DEMOIRE_BASE+0x008)
#define DEMOIRE_DF_THD_MIN (DEMOIRE_BASE+0x00C)
#define DEMOIRE_GAIN_MIN (DEMOIRE_BASE+0x010)
#define DEMOIRE_KC (DEMOIRE_BASE+0x014)
#define DEMOIRE_BYPASS (DEMOIRE_BASE+0x018)
// CC
#define CC_BASE 0x40071000
#define CC_EN_REG (CC_BASE+0x000)
#define CC_HUE_OFST (CC_BASE+0x018)
#define CC_HS_TRAN_DAT0 (CC_BASE+0x0E4)
#define CC_HS_TRAN_DAT1 (CC_BASE+0x0E8)
#define CC_HH_H1_SATRT (CC_BASE+0x200)
#define CC_HH_H1_END (CC_BASE+0x204)
#define CC_HH_H1_MAX1 (CC_BASE+0x208)
#define CC_HH_H1_MAX2 (CC_BASE+0x20C)
#define CC_HH_H1_DMAX (CC_BASE+0x210)
#define CC_HH_H1_K1 (CC_BASE+0x214)
#define CC_HH_H1_K2 (CC_BASE+0x218)
#define CC_HH_H2_SATRT (CC_BASE+0x21C)
#define CC_HH_H2_END (CC_BASE+0x220)
#define CC_HH_H2_MAX1 (CC_BASE+0x224)
#define CC_HH_H2_MAX2 (CC_BASE+0x228)
#define CC_HH_H2_DMAX (CC_BASE+0x22C)
#define CC_HH_H2_K1 (CC_BASE+0x230)
#define CC_HH_H2_K2 (CC_BASE+0x234)
#define CC_HH_H3_SATRT (CC_BASE+0x240)
#define CC_HH_H3_END (CC_BASE+0x244)
#define CC_HH_H3_MAX1 (CC_BASE+0x248)
#define CC_HH_H3_MAX2 (CC_BASE+0x24C)
#define CC_HH_H3_DMAX (CC_BASE+0x250)
#define CC_HH_H3_K1 (CC_BASE+0x254)
#define CC_HH_H3_K2 (CC_BASE+0x258)
#define CC_HH_H4_SATRT (CC_BASE+0x25C)
#define CC_HH_H4_END (CC_BASE+0x260)
#define CC_HH_H4_MAX1 (CC_BASE+0x264)
#define CC_HH_H4_MAX2 (CC_BASE+0x268)
#define CC_HH_H4_DMAX (CC_BASE+0x26C)
#define CC_HH_H4_K1 (CC_BASE+0x270)
#define CC_HH_H4_K2 (CC_BASE+0x274)
#define CC_HH_H5_SATRT (CC_BASE+0x280)
#define CC_HH_H5_END (CC_BASE+0x284)
#define CC_HH_H5_MAX1 (CC_BASE+0x288)
#define CC_HH_H5_MAX2 (CC_BASE+0x28C)
#define CC_HH_H5_DMAX (CC_BASE+0x290)
#define CC_HH_H5_K1 (CC_BASE+0x294)
#define CC_HH_H5_K2 (CC_BASE+0x298)
#define CC_HH_H6_SATRT (CC_BASE+0x29C)
#define CC_HH_H6_END (CC_BASE+0x2A0)
#define CC_HH_H6_MAX1 (CC_BASE+0x2A4)
#define CC_HH_H6_MAX2 (CC_BASE+0x2A8)
#define CC_HH_H6_DMAX (CC_BASE+0x2AC)
#define CC_HH_H6_K1 (CC_BASE+0x2B0)
#define CC_HH_H6_K2 (CC_BASE+0x2B4)
// Y_Gamma
#define YGAMMA_BASE 0x40072000
#define YGAMMA_BUF_SW (YGAMMA_BASE+0x000)
#define YGAMMA_BUF_SW_STATE (YGAMMA_BASE+0x004)
#define YGAMMA_LINE0_DAT0 (YGAMMA_BASE+0x040)
#define YGAMMA_LINE1_DAT0 (YGAMMA_BASE+0x180)
//Y_hist
#define YHIST_BASE (0x40073000)
#define YHIST_CNT0 (YHIST_BASE+0x000)
//C_tran
#define CTRAN_BASE 0x40074000
#define CTRAN_BUF_SW (CTRAN_BASE+0x000)
#define CTRAN_BUF_SW_STATE (CTRAN_BASE+0x004)
#define TRAN_LINE0_DAT0 (CTRAN_BASE+0x040)
#define TRAN_LINE1_DAT0 (CTRAN_BASE+0x080)
// Sharpness
#define SHARPEN_BASE 0x40075000
#define SHARPEN_YMTH1 (SHARPEN_BASE+0x000)
#define SHARPEN_YMTH2 (SHARPEN_BASE+0x004)
#define SHARPEN_YM_K (SHARPEN_BASE+0x008)
#define SHARPEN_KM0 (SHARPEN_BASE+0x00C)
#define SHARPEN_WM0 (SHARPEN_BASE+0x010)
#define SHARPEN_WM1 (SHARPEN_BASE+0x014)
#define SHARPEN_WM2 (SHARPEN_BASE+0x018)
#define SHARPEN_WM3 (SHARPEN_BASE+0x01C)
#define SHARPEN_WM4 (SHARPEN_BASE+0x020)
#define SHARPEN_WM5 (SHARPEN_BASE+0x024)
#define SHARPEN_YMDTH1 (SHARPEN_BASE+0x040)
#define SHARPEN_YMDTH2 (SHARPEN_BASE+0x044)
#define SHARPEN_YMD_K (SHARPEN_BASE+0x048)
#define SHARPEN_KMD_MAX (SHARPEN_BASE+0x04C)
#define SHARPEN_WMD0 (SHARPEN_BASE+0x050)
#define SHARPEN_WMD1 (SHARPEN_BASE+0x054)
#define SHARPEN_WMD2 (SHARPEN_BASE+0x058)
#define SHARPEN_WMD3 (SHARPEN_BASE+0x05C)
#define SHARPEN_WMD4 (SHARPEN_BASE+0x060)
#define SHARPEN_WMD5 (SHARPEN_BASE+0x064)
#define SHARPEN_YHTH1 (SHARPEN_BASE+0x080)
#define SHARPEN_YHTH2 (SHARPEN_BASE+0x084)
#define SHARPEN_YH_K (SHARPEN_BASE+0x088)
#define SHARPEN_KH0 (SHARPEN_BASE+0x08C)
#define SHARPEN_WH0 (SHARPEN_BASE+0x090)
#define SHARPEN_WH1 (SHARPEN_BASE+0x094)
#define SHARPEN_WH2 (SHARPEN_BASE+0x098)
#define SHARPEN_WH3 (SHARPEN_BASE+0x09C)
#define SHARPEN_WH4 (SHARPEN_BASE+0x0A0)
#define SHARPEN_WH5 (SHARPEN_BASE+0x0A4)
#define SHARPEN_YHDTH1 (SHARPEN_BASE+0x0C0)
#define SHARPEN_YHDTH2 (SHARPEN_BASE+0x0C4)
#define SHARPEN_YHD_K (SHARPEN_BASE+0x0C8)
#define SHARPEN_KHD_MAX (SHARPEN_BASE+0x0CC)
#define SHARPEN_WHD0 (SHARPEN_BASE+0x0D0)
#define SHARPEN_WHD1 (SHARPEN_BASE+0x0D4)
#define SHARPEN_WHD2 (SHARPEN_BASE+0x0D8)
#define SHARPEN_WHD3 (SHARPEN_BASE+0x0DC)
#define SHARPEN_WHD4 (SHARPEN_BASE+0x0E0)
#define SHARPEN_WHD5 (SHARPEN_BASE+0x0E4)
#define SHARPEN_KH00 (SHARPEN_BASE+0x100)
#define SHARPEN_KH01 (SHARPEN_BASE+0x104)
#define SHARPEN_KL00 (SHARPEN_BASE+0x108)
#define SHARPEN_KL01 (SHARPEN_BASE+0x10C)
#define SHARPEN_KH1 (SHARPEN_BASE+0x110)
#define SHARPEN_KL1 (SHARPEN_BASE+0x114)
#define SHARPEN_DLTMAX (SHARPEN_BASE+0x118)
#define SHARPEN_DFKD (SHARPEN_BASE+0x11C)
#define SHARPEN_DFMAX (SHARPEN_BASE+0x120)
#define SHARPEN_ENH_STREN (SHARPEN_BASE+0x130)
#define SHARPEN_ENH_THR (SHARPEN_BASE+0x134)
#define SHARPEN_ENH_GMAX (SHARPEN_BASE+0x138)
#define SHARPEN_TRAN_DAT0 (SHARPEN_BASE+0x140)
//#define SHARPEN_C_KR1 (SHARPEN_BASE+0x1C0)
//#define SHARPEN_C_KR2 (SHARPEN_BASE+0x1C4)
//#define SHARPEN_C_KG1 (SHARPEN_BASE+0x1C8)
//#define SHARPEN_C_KG2 (SHARPEN_BASE+0x1CC)
//#define SHARPEN_C_KB1 (SHARPEN_BASE+0x1D0)
//#define SHARPEN_C_KB2 (SHARPEN_BASE+0x1D4)
//#define SHARPEN_C_ZONE_EN (SHARPEN_BASE+0x1D8)
//#define SHARPEN_C_COEF1 (SHARPEN_BASE+0x1DC)
//#define SHARPEN_C_COEF2 (SHARPEN_BASE+0x1E0)
//#define SHARPEN_C_COEF3 (SHARPEN_BASE+0x1E4)
//#define SHARPEN_C_SAT_DAT0 (SHARPEN_BASE+0x200)
#define SHARPEN_EN (SHARPEN_BASE+0x240)
// YC_Gain
#define YC_GAIN_BASE 0x40076000
#define Y_GAIN (YC_GAIN_BASE+(0x000))
#define CB_GAIN (YC_GAIN_BASE+(0x004))
#define CR_GAIN (YC_GAIN_BASE+(0x008))
#define Y_OFST (YC_GAIN_BASE+(0x00C))
#define Y_MAX_THD (YC_GAIN_BASE+(0x010))
#define Y_MIN_THD (YC_GAIN_BASE+(0x014))
//PLL use to upscaler
#define PLL_BASE 0x20000000
#define PLL_SYSCTRLREG_LOCK (PLL_BASE+0x002C)
#define PLLB1_CTRL (PLL_BASE+0x000C)
#define PLLB2_CTRL (PLL_BASE+0x0010)
#define PLLB_CTRL (PLL_BASE+0x0014)
#endif

716
general/package/xiongmai-osdrv-xm530/files/include/xm/xm530_isp.h
View File

@ -1,716 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm530_isp.h
Version : Initial Draft
Author : XM Isp software group
Created : 2017/5/11
Description : The common data type defination
Function List :
History :
1.Date : 2017/5/11
Author : Ganwencao
Modification : creat
******************************************************************************/
#ifndef _XM530_REG_
#define _XM530_REG_
#define DDR_BASE_ADDR (0x80000000)
#define ISP_BASE_ADDR 0x30000000
//GPIO
#define GPIO_BASE (0x10020000)
#define GPIO_POC_18_SEL (GPIO_BASE+0x3C0)
#define GPIO_SEN1_MCLK (GPIO_BASE+0x160)
#define GPIO_SEN1_PCLK (GPIO_BASE+0x0D4)
#define GPIO_SEN1_HSYNC (GPIO_BASE+0x0D8)
#define GPIO_SEN1_VSYNC (GPIO_BASE+0x0DC)
#define GPIO_SEN1_DATE0 (GPIO_BASE+0x0E0)
#define GPIO_SEN1_DATE1 (GPIO_BASE+0x0E4)
#define GPIO_SEN1_DATE2 (GPIO_BASE+0x0E8)
#define GPIO_SEN1_DATE3 (GPIO_BASE+0x0EC)
#define GPIO_SEN1_DATE4 (GPIO_BASE+0x0F0)
#define GPIO_SEN1_DATE5 (GPIO_BASE+0x0F4)
#define GPIO_SEN1_DATE6 (GPIO_BASE+0x0F8)
#define GPIO_SEN1_DATE7 (GPIO_BASE+0x0FC)
#define GPIO_I2C1_SCL (GPIO_BASE+0x014)
#define GPIO_I2C1_SDA (GPIO_BASE+0x01C)
#define GPIO_PIN5_4 (GPIO_BASE+0x0D8)
#define GPIO_I2C0_SDA (GPIO_BASE+0x104)
#define GPIO_I2C0_SCL (GPIO_BASE+0x10C)
#define GPIO_SEN0_MCLK (GPIO_BASE+0x110)
#define GPIO_SEN0_VSYNC (GPIO_BASE+0x114)
#define GPIO_SEN0_PCLK (GPIO_BASE+0x118)
#define GPIO_SEN0_HSYNC (GPIO_BASE+0x11C)
#define GPIO_SEN0_DATE0 (GPIO_BASE+0x120)
#define GPIO_SEN0_DATE1 (GPIO_BASE+0x124)
#define GPIO_SEN0_DATE2 (GPIO_BASE+0x128)
#define GPIO_SEN0_DATE3 (GPIO_BASE+0x12C)
#define GPIO_SEN0_DATE4 (GPIO_BASE+0x130)
#define GPIO_SEN0_DATE5 (GPIO_BASE+0x134)
#define GPIO_SEN0_DATE6 (GPIO_BASE+0x138)
#define GPIO_SEN0_DATE7 (GPIO_BASE+0x13C)
#define GPIO_SEN0_DATE8 (GPIO_BASE+0x140)
#define GPIO_SEN0_DATE9 (GPIO_BASE+0x144)
#define GPIO_SEN0_DATE10 (GPIO_BASE+0x148)
#define GPIO_SEN0_DATE11 (GPIO_BASE+0x14C)
/*************************************************************************************/
#define VIDEOMAIN_BASE (0x300F0000)
#define VIDEOMAIN_AWBMODE (0x300F0004)
#define VIDEOMAIN_RGBIR (0x300F0008)
#define HDR_BYPASS_MODE (0x300F000C)
#define FRONT_V_VIE_EN (0x300F0040)
#define LUMA_V_VIE_EN (0x300F0060)
#define ANALOG_CTRL (VIDEOMAIN_BASE+0x1C)
//pre_video
#define VIDOEMODE_BASE 0x30000000
#define VIDOEMODE_DECODE_SEL (VIDOEMODE_BASE+0x000)
#define VIDOEMODE_SLA_MAT_SEL (VIDOEMODE_BASE+0x004)
#define VIDOEMODE_DEC_DATA_SEL (VIDOEMODE_BASE+0x008)
#define VI_VH_NUM (VIDOEMODE_BASE+0x090)
#define VI_VH_ALL (VIDOEMODE_BASE+0x094)
#define VI_CUT_BEGIN_H (VIDOEMODE_BASE+0x098)
#define VI_CUT_END_H (VIDOEMODE_BASE+0x09C)
#define VI_CUT_BEGIN_V (VIDOEMODE_BASE+0x0A0)
#define VI_CUT_END_V (VIDOEMODE_BASE+0x0A4)
#define VI_SYNC_HVALID_RECV (VIDOEMODE_BASE+0x0C0)
#define VI_SYNC_HVALID_RECV_EN (VIDOEMODE_BASE+0x0C4)
// DPC
#define SDPC_BASE 0x30001000
#define SDPC_CLK_SW (SDPC_BASE+0x000)
#define SDPC_SRAMADDR_CLR (SDPC_BASE+0x004)
#define SDPC_SRAMADDR_DAT (SDPC_BASE+0x008)
#define SDPC_TEST_ENABLE (SDPC_BASE+0x00C)
#define DDPC_BASE 0x30035000
#define DDPC_MAX_THD (DDPC_BASE+0x000)
#define DDPC_MIN_THD (DDPC_BASE+0x004)
#define DDPC_DIFF_THD1 (DDPC_BASE+0x008)
#define DDPC_DIFF_THD2 (DDPC_BASE+0x00C)
#define DDPC_DIFF_DFTH1 (DDPC_BASE+0x010)
#define DDPC_DIFF_DFTH2 (DDPC_BASE+0x014)
//FPN
#define FPN_BASE 0x30002000
#define FPN_CLK_SW_REG (FPN_BASE+0x000)
#define FPN_CPU_ADDR (FPN_BASE+0x004)
#define FPN_CPU_DATA (FPN_BASE+0x008)
#define FPN_CPU_RDSEL (FPN_BASE+0x00C)
#define FPN_STREN (FPN_BASE+0x010)
#define FPN_SEL (FPN_BASE+0x014)
#define FPN_DET_MODE (FPN_BASE+0x018)
#define FPN_DET_READY (FPN_BASE+0x01C)
#define FPN_BYPASS (FPN_BASE+0x020)
// BlackLevel
#define BLACKLEVEL_BASE 0x30004000
#define BLACKLEVEL_OFFSET_R (BLACKLEVEL_BASE+0x000)
#define BLACKLEVEL_OFFSET_G (BLACKLEVEL_BASE+0x004)
#define BLACKLEVEL_OFFSET_B (BLACKLEVEL_BASE+0x008)
#define BLACKLEVEL_RGB_MAX (BLACKLEVEL_BASE+0x00C)
#define BLACKLEVEL_RGB_MIN (BLACKLEVEL_BASE+0x010)
// DIGTAL_GAIN
#define DIGITAL_GAIN (0x30005000+0x000)
#define DIGITAL_RGBMAX (0x30005000+0x004)
//LSC
#define LSC_BASE 0x30006000
#define LSC_CTRL (LSC_BASE+0x000)
//HDR_DEC
#define DEC_BASE 0x30003000
#define DEC_BYPASS (DEC_BASE+0x000)
#define DEC_X1 (DEC_BASE+0x004)
#define DEC_RGB_MAX (DEC_BASE+0x034)
#define DEC_RGB_MIN (DEC_BASE+0x038)
//HDR
#define HDR_BASE (ISP_BASE_ADDR+0x8000)
#define HDR_R_GAIN (HDR_BASE+0x0000)
#define HDR_G_GAIN (HDR_BASE+0x0004)
#define HDR_B_GAIN (HDR_BASE+0x0008)
#define HDR_RGB_MAX (HDR_BASE+0x000C)
#define HDR_RGB_MIN (HDR_BASE+0x0010)
#define HDR_CLIP_WT_MAX (HDR_BASE+0x1000)
#define HDR_CLIP_WT_MIN (HDR_BASE+0x1004)
#define HDR_MOTION_THR (HDR_BASE+0x1008)
#define HDR_V_MAX (HDR_BASE+0x100C)
#define HDR_LS_TIME_RATIO (HDR_BASE+0x1010)
#define HDR_LE_WT_MIN (HDR_BASE+0x1014)
#define HDR_SE_WT_RATIO (HDR_BASE+0x1018)
#define HDR_DCTTAB_DAT0 (HDR_BASE+0x2040)
#define HDR_DS_WIDE (HDR_BASE+0x3000)
#define HDR_DS_HEIGHT (HDR_BASE+0x3004)
#define HDR_WIDE_DIVTAB (HDR_BASE+0x3008)
#define HDR_HEIGHT_DIVTAB (HDR_BASE+0x300C)
#define HDR_AVG_DIVTAB1 (HDR_BASE+0x3010)
#define HDR_ADAWT (HDR_BASE+0x3020)
#define HDR_DEHZAA (HDR_BASE+0x3024)
#define HDR_USMINTENS (HDR_BASE+0x3028)
#define HDR_FUSWT (HDR_BASE+0x302C)
#define LTM_LUM_DARK00 (HDR_BASE+0x3200)
#define LTM_LUM_BRIG00 (HDR_BASE+0x3300)
//AWB
#define AWB_BASE (0x30010000)
#define AWB_FRONTGAIN_R (AWB_BASE+0x0000)
#define AWB_FRONTGAIN_G (AWB_BASE+0x0004)
#define AWB_FRONTGAIN_B (AWB_BASE+0x0008)
#define AWB_RGBMAX_REG (AWB_BASE+0x000C)
#define AWB_RGBMIN_REG (AWB_BASE+0x0010)
#define AWB_WDW_PIXL0 (AWB_BASE+0x1000)
#define AWB_WDW_PIXL1 (AWB_BASE+0x1004)
#define AWB_WDW_PIXL2 (AWB_BASE+0x1008)
#define AWB_WDW_PIXL3 (AWB_BASE+0x100C)
#define AWB_WDW_PIXL4 (AWB_BASE+0x1010)
#define AWB_WDW_PIXL5 (AWB_BASE+0x1014)
#define AWB_WDW_PIXL6 (AWB_BASE+0x1018)
#define AWB_WDW_PIXL7 (AWB_BASE+0x101C)
#define AWB_WDW_PIXL8 (AWB_BASE+0x1020)
#define AWB_WDW_PIXL9 (AWB_BASE+0x1024)
#define AWB_WDW_PIXL10 (AWB_BASE+0x1028)
#define AWB_WDW_PIXL11 (AWB_BASE+0x102C)
#define AWB_WDW_PIXL12 (AWB_BASE+0x1030)
#define AWB_WDW_PIXL13 (AWB_BASE+0x1034)
#define AWB_WDW_PIXL14 (AWB_BASE+0x1038)
#define AWB_WDW_PIXL15 (AWB_BASE+0x103C)
#define AWB_WDW_PIXL16 (AWB_BASE+0x1040)
#define AWB_WDW_PIXL17 (AWB_BASE+0x1044)
#define AWB_WDW_PIXL18 (AWB_BASE+0x1048)
#define AWB_WDW_PIXL19 (AWB_BASE+0x104C)
#define AWB_WDW_PIXL20 (AWB_BASE+0x1050)
#define AWB_WDW_PIXL21 (AWB_BASE+0x1054)
#define AWB_WDW_PIXL22 (AWB_BASE+0x1058)
#define AWB_WDW_PIXL23 (AWB_BASE+0x105C)
#define AWB_WDW_PIXL24 (AWB_BASE+0x1060)
#define AWB_WDW_PIXL25 (AWB_BASE+0x1064)
#define AWB_WDW_PIXL26 (AWB_BASE+0x1068)
#define AWB_WDW_PIXL27 (AWB_BASE+0x106C)
#define AWB_WDW_PIXL28 (AWB_BASE+0x1070)
#define AWB_WDW_PIXL29 (AWB_BASE+0x1074)
#define AWB_WDW_PIXL30 (AWB_BASE+0x1078)
#define AWB_WDW_PIXL31 (AWB_BASE+0x107C)
#define AWB_WDW_PIXL32 (AWB_BASE+0x1080)
#define AWB_WDW_LINE0 (AWB_BASE+0x10C0)
#define AWB_WDW_LINE1 (AWB_BASE+0x10C4)
#define AWB_WDW_LINE2 (AWB_BASE+0x10C8)
#define AWB_WDW_LINE3 (AWB_BASE+0x10CC)
#define AWB_WDW_LINE4 (AWB_BASE+0x10D0)
#define AWB_WDW_LINE5 (AWB_BASE+0x10D4)
#define AWB_WDW_LINE6 (AWB_BASE+0x10D8)
#define AWB_WDW_LINE7 (AWB_BASE+0x10DC)
#define AWB_WDW_LINE8 (AWB_BASE+0x10E0)
#define AWB_WDW_LINE9 (AWB_BASE+0x10E4)
#define AWB_WDW_LINE10 (AWB_BASE+0x10E8)
#define AWB_WDW_LINE11 (AWB_BASE+0x10EC)
#define AWB_WDW_LINE12 (AWB_BASE+0x10F0)
#define AWB_WDW_LINE13 (AWB_BASE+0x10F4)
#define AWB_WDW_LINE14 (AWB_BASE+0x10F8)
#define AWB_WDW_LINE15 (AWB_BASE+0x10FC)
#define AWB_WDW_LINE16 (AWB_BASE+0x1100)
#define AWB_SRAM_ADDR_RC (AWB_BASE+0x1140)
#define AWB_SRAM_RD_EN (AWB_BASE+0x1144)
#define AWB_R_INTG (AWB_BASE+0x1148)
#define AWB_G_INTG (AWB_BASE+0x114C)
#define AWB_B_INTG (AWB_BASE+0x1150)
#define AWB_HIST_RGB_SEL (AWB_BASE+0x2000)
#define AWB_HIST_CNT0 (AWB_BASE+0x2040)
#define AWB_HIST_CNT1 (AWB_BASE+0x2044)
#define AWB_HIST_CNT2 (AWB_BASE+0x2048)
#define AWB_HIST_CNT3 (AWB_BASE+0x204C)
#define AWB_HIST_CNT4 (AWB_BASE+0x2050)
#define AWB_HIST_CNT5 (AWB_BASE+0x2054)
#define AWB_HIST_CNT6 (AWB_BASE+0x2058)
#define AWB_HIST_CNT7 (AWB_BASE+0x205C)
#define AWB_HIST_CNT8 (AWB_BASE+0x2060)
#define AWB_HIST_CNT9 (AWB_BASE+0x2064)
#define AWB_HIST_CNT10 (AWB_BASE+0x2068)
#define AWB_HIST_CNT11 (AWB_BASE+0x206C)
#define AWB_HIST_CNT12 (AWB_BASE+0x2070)
#define AWB_HIST_CNT13 (AWB_BASE+0x2074)
#define AWB_HIST_CNT14 (AWB_BASE+0x2078)
#define AWB_HIST_CNT15 (AWB_BASE+0x207C)
#define AWB_HIST_CNT16 (AWB_BASE+0x2080)
#define AWB_HIST_CNT17 (AWB_BASE+0x2084)
#define AWB_HIST_CNT18 (AWB_BASE+0x2088)
#define AWB_HIST_CNT19 (AWB_BASE+0x208C)
#define AWB_HIST_CNT20 (AWB_BASE+0x2090)
#define AWB_HIST_CNT21 (AWB_BASE+0x2094)
#define AWB_HIST_CNT22 (AWB_BASE+0x2098)
#define AWB_HIST_CNT23 (AWB_BASE+0x209C)
#define AWB_HIST_CNT24 (AWB_BASE+0x20A0)
#define AWB_HIST_CNT25 (AWB_BASE+0x20A4)
#define AWB_HIST_CNT26 (AWB_BASE+0x20A8)
#define AWB_HIST_CNT27 (AWB_BASE+0x20AC)
#define AWB_HIST_CNT28 (AWB_BASE+0x20B0)
#define AWB_HIST_CNT29 (AWB_BASE+0x20B4)
#define AWB_HIST_CNT30 (AWB_BASE+0x20B8)
#define AWB_HIST_CNT31 (AWB_BASE+0x20BC)
//NIR
#define NIR_BASE (0x30030000)
#define NIR_HIR_COEF1 (NIR_BASE + 0x0018)
#define NIR_HIR_COEF2 (NIR_BASE + 0x001C)
#define NIR_HIR_COEF3 (NIR_BASE + 0x0020)
#define NIR_CC_MODE (NIR_BASE + 0x1000)
#define NIR_RS_RAT (NIR_BASE + 0x1004)
#define NIR_GS_RAT (NIR_BASE + 0x1008)
#define NIR_BS_RAT (NIR_BASE + 0x100C)
#define NIR_CC_COEF11 (NIR_BASE + 0x1040)
#define NIR_CC_COEF12 (NIR_BASE + 0x1044)
#define NIR_CC_COEF13 (NIR_BASE + 0x1048)
#define NIR_CC_COEF14 (NIR_BASE + 0x104C)
#define NIR_CC_COEF21 (NIR_BASE + 0x1050)
#define NIR_CC_COEF22 (NIR_BASE + 0x1054)
#define NIR_CC_COEF23 (NIR_BASE + 0x1058)
#define NIR_CC_COEF24 (NIR_BASE + 0x105C)
#define NIR_CC_COEF31 (NIR_BASE + 0x1060)
#define NIR_CC_COEF32 (NIR_BASE + 0x1064)
#define NIR_CC_COEF33 (NIR_BASE + 0x1068)
#define NIR_CC_COEF34 (NIR_BASE + 0x106C)
#define NIR_CRT_LUMLUT0 (NIR_BASE + 0x1080)
#define NIR_IR_INTG (NIR_BASE + 0x2000)
#define NIR_R_INTG (NIR_BASE + 0x2004)
#define NIR_G_INTG (NIR_BASE + 0x2008)
#define NIR_B_INTG (NIR_BASE + 0x200C)
#define NIR_RGB_INTG (NIR_BASE + 0x2010)
#define NIR_FUS_LUMLUT0 (NIR_BASE + 0x3080)
//NR_2D
#define NR_2D_BASE 0x30036000
#define NR_2D_THDL_REG (NR_2D_BASE + 0x000)
#define NR_2D_THDH_REG (NR_2D_BASE + 0x004)
#define NR_2D_COEF_REG (NR_2D_BASE + 0x008)
#define NR_2D_GMIN_REG (NR_2D_BASE + 0x00C)
#define NR_2D_DELTA_THD (NR_2D_BASE + 0x010)
#define NR_2D_G_COEF1 (NR_2D_BASE + 0x014)
#define NR_2D_G_COEF2 (NR_2D_BASE + 0x018)
#define NR_2D_G_COEF3 (NR_2D_BASE + 0x01C)
#define NR_2D_G_COEF4 (NR_2D_BASE + 0x020)
#define NR_2D_RB_COEF1 (NR_2D_BASE + 0x024)
#define NR_2D_RB_COEF2 (NR_2D_BASE + 0x028)
#define NR_2D_RB_COEF3 (NR_2D_BASE + 0x02C)
#define NR_2D_H_SEL (NR_2D_BASE + 0x030)
#define NR_2D_FLT_EN (NR_2D_BASE + 0x034)
//BAYER_GAIN
#define BAYER_GAIN_BASE 0x30037000
#define NIR_R_GAIN_REG (BAYER_GAIN_BASE+0x000)
#define NIR_G_GAIN_REG (BAYER_GAIN_BASE+0x004)
#define NIR_B_GAIN_REG (BAYER_GAIN_BASE+0x008)
#define NIR_RGBMAX_REG (BAYER_GAIN_BASE+0x00C)
#define NIR_RGBMIN_REG (BAYER_GAIN_BASE+0x010)
////AF
//#define AF_BASE 0x30021000
//#define AF_WDW0_VBEGIN (AF_BASE + 0x000)
//#define AF_WDW0_VEND (AF_BASE + 0x004)
//#define AF_WDW0_HBEGIN (AF_BASE + 0x008)
//#define AF_WDW0_HEND (AF_BASE + 0x00C)
//
//#define AF_WDW0_HZ (AF_BASE + 0x094)
#if 1 //XM530
//NR_3D
#define NR_3D_BASE 0x30040000
#define NR_3D_DENOSIE_CTL (NR_3D_BASE + 0x000)
#define NR_3D_ERR_SFT (NR_3D_BASE + 0x014)
#define NR_3D_RAMP (NR_3D_BASE + 0x004)
#define NR_3D_G1AMP (NR_3D_BASE + 0x008)
#define NR_3D_G2AMP (NR_3D_BASE + 0x00C)
#define NR_3D_BAMP (NR_3D_BASE + 0x010)
#define NR_3D_YFLD_SPACE (NR_3D_BASE + 0x030)
#define NR_3D_BFLD_SPACE (NR_3D_BASE + 0x034)
#define NR_3D_DFT_YSADDR0 (NR_3D_BASE + 0x038)
#define NR_3D_DFT_ESADDR0 (NR_3D_BASE + 0x03C)
#define NR_3D_DIG_E1 (NR_3D_BASE + 0x020)
#define NR_3D_DIG_E2 (NR_3D_BASE + 0x024)
#define NR_3D_DIG_E3 (NR_3D_BASE + 0x028)
#define NR_3D_ERR_PAR (NR_3D_BASE + 0x040)
#define NR_3D_BAYER_PAR (NR_3D_BASE + 0x050)
#define NR_3D_NOISE_REG (NR_3D_BASE + 0x060)
#define NR_3D_DFT_BSADDR0 (NR_3D_BASE + 0x0A0)
#define NR_3D_DFT_BSADDR1 (NR_3D_BASE + 0x0A4)
#define NR_3D_DFT_BSADDR2 (NR_3D_BASE + 0x0A8)
#define NR_3D_DFT_BSADDR3 (NR_3D_BASE + 0x0AC)
#define NR_3D_DFT_BSADDR4 (NR_3D_BASE + 0x0B0)
#define NR_3D_DFT_BSADDR5 (NR_3D_BASE + 0x0B4)
#define NR_3D_DFT_BSADDR6 (NR_3D_BASE + 0x0B8)
#define NR_3D_DFT_BSADDR7 (NR_3D_BASE + 0x0BC)
#define NR_3D_DDR_BHNUM (NR_3D_BASE + 0x0C8)
#define NR_3D_DDR_YHNUM (NR_3D_BASE + 0x0CC)
#define NR_3D_DDR_EHNUM (NR_3D_BASE + 0x0D0)
#define NR_3D_ACTIVE_HNUM (NR_3D_BASE + 0x0D4)
#define NR_3D_ACTIVE_VNUM (NR_3D_BASE + 0x0D8)
#define NR_3D_WINERR_HBEGIN (NR_3D_BASE + 0x120)
#define NR_3D_WINERR_HEND (NR_3D_BASE + 0x124)
#define NR_3D_WINERR_VBEGIN (NR_3D_BASE + 0x128)
#define NR_3D_WINERR_VEND (NR_3D_BASE + 0x12C)
#define NR_3D_2D_NOISE_THR (NR_3D_BASE + 0x130)
#define NR_3D_FIT2D2_WEIGHT1 (NR_3D_BASE + 0x134)
#define NR_3D_FIT2D2_WEIGHT2 (NR_3D_BASE + 0x138)
#define NR_3D_NOISE_MAP (NR_3D_BASE + 0x144)
#define NR_3D_CHANGE_POINT (NR_3D_BASE + 0x148)
#define NR_3D_FLT2D_PAR (NR_3D_BASE + 0x14C)
#else// This is XM510 code,just for test
//NR_3D
#define NR_3D_BASE 0x30040000
#define NR_3D_DENOSIE_CTL (NR_3D_BASE + 0x000)
#define NR_3D_ERR_SFT (NR_3D_BASE + 0x014)
#define NR_3D_NR_LEVEL (NR_3D_BASE + 0x018)
#define NR_3D_YFLD_SPACE (NR_3D_BASE + 0x030)
#define NR_3D_BFLD_SPACE (NR_3D_BASE + 0x034)
#define NR_3D_DFT_YSADDR0 (NR_3D_BASE + 0x038)
#define NR_3D_DFT_ESADDR0 (NR_3D_BASE + 0x03C)
#define NR_3D_DIG_E1 (NR_3D_BASE + 0x020)
#define NR_3D_DIG_E2 (NR_3D_BASE + 0x024)
#define NR_3D_DIG_E3 (NR_3D_BASE + 0x028)
#define NR_3D_ERR_PAR (NR_3D_BASE + 0x040)
#define NR_3D_BAYER_PAR (NR_3D_BASE + 0x050)
#define NR_3D_DDR_HNUM (NR_3D_BASE + 0x0D0)
#define NR_3D_ACTIVE_HNUM (NR_3D_BASE + 0x0D4)
#define NR_3D_YCTRL_ERR70 (NR_3D_BASE + 0x0D8)
#define NR_3D_YCTRL_ERRF8 (NR_3D_BASE + 0x0DC)
#define NR_3D_DFT_BSADDR0 (NR_3D_BASE + 0x0A0)
#define NR_3D_DFT_BSADDR1 (NR_3D_BASE + 0x0A4)
#define NR_3D_DFT_BSADDR2 (NR_3D_BASE + 0x0A8)
#define NR_3D_DFT_BSADDR3 (NR_3D_BASE + 0x0AC)
#define NR_3D_DFT_BSADDR4 (NR_3D_BASE + 0x0B0)
#define NR_3D_DFT_BSADDR5 (NR_3D_BASE + 0x0B4)
#define NR_3D_DFT_BSADDR6 (NR_3D_BASE + 0x0B8)
#define NR_3D_DFT_BSADDR7 (NR_3D_BASE + 0x0BC)
#define NR_3D_WINERR_HBEGIN (NR_3D_BASE + 0x120)
#define NR_3D_WINERR_HEND (NR_3D_BASE + 0x124)
#define NR_3D_WINERR_VBEGIN (NR_3D_BASE + 0x128)
#define NR_3D_WINERR_VEND (NR_3D_BASE + 0x12C)
#define NR_3D_WINERR_RSHIFT (NR_3D_BASE + 0x140)
#define NR_3D_WINERR_LEVEL (NR_3D_BASE + 0x144)
#define NR_3D_CHANGE_POINT (NR_3D_BASE + 0x148)
#define NR_3D_FLT2D_PAR (NR_3D_BASE + 0x14C)
#endif
// Demosaic_cut_f
#define DMSC_CUT 0x30051000
#define DMSC_CUT_H_BEGIN (DMSC_CUT+0x0)
#define DMSC_CUT_H_END (DMSC_CUT+0x4)
#define DMSC_CUT_V_BEGIN (DMSC_CUT+0x8)
#define DMSC_CUT_V_END (DMSC_CUT+0xC)
// Demosaic
#define DEMOSAIC_BASE 0x30050000
#define DEMOSAIC_G_HOFST (DEMOSAIC_BASE + 0x000)
#define DEMOSAIC_DHV_OFST (DEMOSAIC_BASE + 0x004)
#define DEMOSAIC_DHV_K (DEMOSAIC_BASE + 0x008)
#define DEMOSAIC_GCALC_MODE (DEMOSAIC_BASE + 0x00C)
#define DEMOSAIC_THRMAIN (DEMOSAIC_BASE + 0x010)
#define DEMOSAIC_THRSUB (DEMOSAIC_BASE + 0x014)
// CSM
#define CSM_BASE 0x30060000
#define CSM_RGB_MAX (CSM_BASE+0x000)
#define CSM_RGB_MIN (CSM_BASE+0x004)
#define CSM_R_OFST_REG (CSM_BASE+0x040)
#define CSM_R1_COEF_REG (CSM_BASE+0x044)
#define CSM_R2_COEF_REG (CSM_BASE+0x048)
#define CSM_R3_COEF_REG (CSM_BASE+0x04C)
#define CSM_G_OFST_REG (CSM_BASE+0x050)
#define CSM_G1_COEF_REG (CSM_BASE+0x054)
#define CSM_G2_COEF_REG (CSM_BASE+0x058)
#define CSM_G3_COEF_REG (CSM_BASE+0x05C)
#define CSM_B_OFST_REG (CSM_BASE+0x060)
#define CSM_B1_COEF_REG (CSM_BASE+0x064)
#define CSM_B2_COEF_REG (CSM_BASE+0x068)
#define CSM_B3_COEF_REG (CSM_BASE+0x06C)
// Gamma96
#define GAMMA96_BASE 0x30061000
#define GAMMA96_LINE0_DAT0 (GAMMA96_BASE+0x000)
// RGB2YC
#define RGB2YC_BASE 0x30062000
// Demoire
#define DEMOIRE_BASE 0x30063000
#define DEMOIRE_V_THD (DEMOIRE_BASE+0x000)
#define DEMOIRE_KV (DEMOIRE_BASE+0x004)
#define DEMOIRE_DF_THD_MAX (DEMOIRE_BASE+0x008)
#define DEMOIRE_DF_THD_MIN (DEMOIRE_BASE+0x00C)
#define DEMOIRE_GAIN_MIN (DEMOIRE_BASE+0x010)
#define DEMOIRE_KC (DEMOIRE_BASE+0x014)
#define DEMOIRE_BYPASS (DEMOIRE_BASE+0x018)
// CC
#define CC_BASE 0x30071000
#define CC_EN_REG (CC_BASE+0x000)
#define CC_HUE_OFST (CC_BASE+0x018)
#define CC_YS_TRAN_DAT0 (CC_BASE+0x040)
#define CC_S_TRAN_DAT0 (CC_BASE+0x084)
#define CC_HS_TRAN_DAT0 (CC_BASE+0x0E4)
#define CC_HH_H1_SATRT (CC_BASE+0x200)
#define CC_HH_H1_END (CC_BASE+0x204)
#define CC_HH_H1_MAX1 (CC_BASE+0x208)
#define CC_HH_H1_MAX2 (CC_BASE+0x20C)
#define CC_HH_H1_DMAX (CC_BASE+0x210)
#define CC_HH_H1_K1 (CC_BASE+0x214)
#define CC_HH_H1_K2 (CC_BASE+0x218)
#define CC_HH_H2_SATRT (CC_BASE+0x21C)
#define CC_HH_H2_END (CC_BASE+0x220)
#define CC_HH_H2_MAX1 (CC_BASE+0x224)
#define CC_HH_H2_MAX2 (CC_BASE+0x228)
#define CC_HH_H2_DMAX (CC_BASE+0x22C)
#define CC_HH_H2_K1 (CC_BASE+0x230)
#define CC_HH_H2_K2 (CC_BASE+0x234)
#define CC_HH_H3_SATRT (CC_BASE+0x240)
#define CC_HH_H3_END (CC_BASE+0x244)
#define CC_HH_H3_MAX1 (CC_BASE+0x248)
#define CC_HH_H3_MAX2 (CC_BASE+0x24C)
#define CC_HH_H3_DMAX (CC_BASE+0x250)
#define CC_HH_H3_K1 (CC_BASE+0x254)
#define CC_HH_H3_K2 (CC_BASE+0x258)
//#define CC_HH_H4_SATRT (CC_BASE+0x25C)
//#define CC_HH_H4_END (CC_BASE+0x260)
//#define CC_HH_H4_MAX1 (CC_BASE+0x264)
//#define CC_HH_H4_MAX2 (CC_BASE+0x268)
//#define CC_HH_H4_DMAX (CC_BASE+0x26C)
//#define CC_HH_H4_K1 (CC_BASE+0x270)
//#define CC_HH_H4_K2 (CC_BASE+0x274)
//
//#define CC_HH_H5_SATRT (CC_BASE+0x280)
//#define CC_HH_H5_END (CC_BASE+0x284)
//#define CC_HH_H5_MAX1 (CC_BASE+0x288)
//#define CC_HH_H5_MAX2 (CC_BASE+0x28C)
//#define CC_HH_H5_DMAX (CC_BASE+0x290)
//#define CC_HH_H5_K1 (CC_BASE+0x294)
//#define CC_HH_H5_K2 (CC_BASE+0x298)
//
//#define CC_HH_H6_SATRT (CC_BASE+0x29C)
//#define CC_HH_H6_END (CC_BASE+0x2A0)
//#define CC_HH_H6_MAX1 (CC_BASE+0x2A4)
//#define CC_HH_H6_MAX2 (CC_BASE+0x2A8)
//#define CC_HH_H6_DMAX (CC_BASE+0x2AC)
//#define CC_HH_H6_K1 (CC_BASE+0x2B0)
//#define CC_HH_H6_K2 (CC_BASE+0x2B4)
// Y_Gamma
#define YGAMMA_BASE 0x30072000
#define YGAMMA_LINE0_DAT0 (YGAMMA_BASE+0x000)
//Y_hist
#define YHIST_BASE 0x30073000
#define YHIST_CNT0 (YHIST_BASE+0x000)
//C_tran
#define CTRAN_BASE 0x30074000
#define TRAN_LINE0_DAT0 (CTRAN_BASE+0x000)
#define TRAN_LINE0_DAT7 (CTRAN_BASE+0x01C)
#define TRAN_LINE0_DAT8 (CTRAN_BASE+0x020)
// Sharpness
#define SHARPEN_BASE 0x30075000
#define SHARPEN_YMTH1 (SHARPEN_BASE+0x000)
#define SHARPEN_YMTH2 (SHARPEN_BASE+0x004)
#define SHARPEN_YM_K (SHARPEN_BASE+0x008)
#define SHARPEN_KM0 (SHARPEN_BASE+0x00C)
#define SHARPEN_WM0 (SHARPEN_BASE+0x010)
#define SHARPEN_WM1 (SHARPEN_BASE+0x014)
#define SHARPEN_WM2 (SHARPEN_BASE+0x018)
#define SHARPEN_WM3 (SHARPEN_BASE+0x01C)
#define SHARPEN_WM4 (SHARPEN_BASE+0x020)
#define SHARPEN_WM5 (SHARPEN_BASE+0x024)
#define SHARPEN_YMDTH1 (SHARPEN_BASE+0x040)
#define SHARPEN_YMDTH2 (SHARPEN_BASE+0x044)
#define SHARPEN_YMD_K (SHARPEN_BASE+0x048)
#define SHARPEN_KMD_MAX (SHARPEN_BASE+0x04C)
#define SHARPEN_WMD0 (SHARPEN_BASE+0x050)
#define SHARPEN_WMD1 (SHARPEN_BASE+0x054)
#define SHARPEN_WMD2 (SHARPEN_BASE+0x058)
#define SHARPEN_WMD3 (SHARPEN_BASE+0x05C)
#define SHARPEN_WMD4 (SHARPEN_BASE+0x060)
#define SHARPEN_WMD5 (SHARPEN_BASE+0x064)
#define SHARPEN_YHTH1 (SHARPEN_BASE+0x080)
#define SHARPEN_YHTH2 (SHARPEN_BASE+0x084)
#define SHARPEN_YH_K (SHARPEN_BASE+0x088)
#define SHARPEN_KH0 (SHARPEN_BASE+0x08C)
#define SHARPEN_WH0 (SHARPEN_BASE+0x090)
#define SHARPEN_WH1 (SHARPEN_BASE+0x094)
#define SHARPEN_WH2 (SHARPEN_BASE+0x098)
#define SHARPEN_WH3 (SHARPEN_BASE+0x09C)
#define SHARPEN_WH4 (SHARPEN_BASE+0x0A0)
#define SHARPEN_WH5 (SHARPEN_BASE+0x0A4)
#define SHARPEN_YHDTH1 (SHARPEN_BASE+0x0C0)
#define SHARPEN_YHDTH2 (SHARPEN_BASE+0x0C4)
#define SHARPEN_YHD_K (SHARPEN_BASE+0x0C8)
#define SHARPEN_KHD_MAX (SHARPEN_BASE+0x0CC)
#define SHARPEN_WHD0 (SHARPEN_BASE+0x0D0)
#define SHARPEN_WHD1 (SHARPEN_BASE+0x0D4)
#define SHARPEN_WHD2 (SHARPEN_BASE+0x0D8)
#define SHARPEN_WHD3 (SHARPEN_BASE+0x0DC)
#define SHARPEN_WHD4 (SHARPEN_BASE+0x0E0)
#define SHARPEN_WHD5 (SHARPEN_BASE+0x0E4)
#define SHARPEN_KH00 (SHARPEN_BASE+0x100)
#define SHARPEN_KH01 (SHARPEN_BASE+0x104)
#define SHARPEN_KL00 (SHARPEN_BASE+0x108)
#define SHARPEN_KL01 (SHARPEN_BASE+0x10C)
#define SHARPEN_KH1 (SHARPEN_BASE+0x110)
#define SHARPEN_KL1 (SHARPEN_BASE+0x114)
#define SHARPEN_DLTMAX (SHARPEN_BASE+0x118)
#define SHARPEN_DFKD (SHARPEN_BASE+0x11C)
#define SHARPEN_DFMAX (SHARPEN_BASE+0x120)
#define SHARPEN_ENH_STREN (SHARPEN_BASE+0x130)
#define SHARPEN_ENH_THR (SHARPEN_BASE+0x134)
#define SHARPEN_ENH_GMAX (SHARPEN_BASE+0x138)
#define SHARPEN_TRAN_DAT0 (SHARPEN_BASE+0x140)
#define SHARPEN_C_COEF1 (SHARPEN_BASE+0x1C0)
#define SHARPEN_C_COEF2 (SHARPEN_BASE+0x1C4)
#define SHARPEN_C_COEF3 (SHARPEN_BASE+0x1C8)
#define SHARPEN_C_FLT_SEL (SHARPEN_BASE+0x1CC)
//#define SHARPEN_C_KR1 (SHARPEN_BASE+0x1C0)
//#define SHARPEN_C_KR2 (SHARPEN_BASE+0x1C4)
//#define SHARPEN_C_KG1 (SHARPEN_BASE+0x1C8)
//#define SHARPEN_C_KG2 (SHARPEN_BASE+0x1CC)
//#define SHARPEN_C_KB1 (SHARPEN_BASE+0x1D0)
//#define SHARPEN_C_KB2 (SHARPEN_BASE+0x1D4)
//#define SHARPEN_C_ZONE_EN (SHARPEN_BASE+0x1D8)
//#define SHARPEN_C_COEF1 (SHARPEN_BASE+0x1DC)
//#define SHARPEN_C_COEF2 (SHARPEN_BASE+0x1E0)
//#define SHARPEN_C_COEF3 (SHARPEN_BASE+0x1E4)
//#define SHARPEN_C_SAT_DAT0 (SHARPEN_BASE+0x200)
#define SHARPEN_EN (SHARPEN_BASE+0x240)
#define SHARPEN_DENOISE_EN (SHARPEN_BASE+0x248)
#define SHARPEN_NOISETHR (SHARPEN_BASE+0x250)
// YC_Gain
#define YC_GAIN_BASE 0x30076000
#define Y_GAIN (YC_GAIN_BASE+(0x000))
#define CB_GAIN (YC_GAIN_BASE+(0x004))
#define CR_GAIN (YC_GAIN_BASE+(0x008))
#define Y_OFST (YC_GAIN_BASE+(0x00C))
#define Y_MAX_THD (YC_GAIN_BASE+(0x010))
#define Y_MIN_THD (YC_GAIN_BASE+(0x014))
//PLL use to upscaler
#define PLL_BASE 0x20000000
#define PLL_SYSCTRLREG_LOCK (PLL_BASE+0x0000)
#define PLLB1_CTRL (PLL_BASE+0x0010)
#define PLLB2_CTRL (PLL_BASE+0x0014)
#define PLL_SENCLK_CTRL (PLL_BASE+0x003C)
#define PLL_ISPCLK_CTRL (PLL_BASE+0x0040)
#define PLL_LCDCLK_CTRL (PLL_BASE+0x0044)
#define PLL_ISPBUSCLK_CTRL (PLL_BASE+0x0048)
#define PLL_VENCCLK_CTRL (PLL_BASE+0x004C)
//Luma(BT1120)
#define LUM_VI_BASE 0x300E0000
#define LUM_DEC_SYNC_CTRL (LUM_VI_BASE+0x00C)
#define LUM_DEC_HEAD_DAT1 (LUM_VI_BASE+0x010)
#define LUM_DEC_HEAD_MSK1 (LUM_VI_BASE+0x01C)
#define LUM_DEC_HEAD_MSK2 (LUM_VI_BASE+0x020)
#define LUM_DEC_HEAD_MSK3 (LUM_VI_BASE+0x024)
#define LUM_DEC_SOL_DAT (LUM_VI_BASE+0x028)
#define LUM_DEC_EOL_DAT (LUM_VI_BASE+0x02C)
#define LUM_DEC_SOF_DAT (LUM_VI_BASE+0x030)
#define LUM_DEC_EOF_DAT (LUM_VI_BASE+0x034)
#define LUM_DEC_SOL_MSK (LUM_VI_BASE+0x038)
#define LUM_DEC_EOL_MSK (LUM_VI_BASE+0x03C)
#define LUM_DEC_SOF_MSK (LUM_VI_BASE+0x040)
#define LUM_DEC_EOF_MSK (LUM_VI_BASE+0x044)
#define LUM_TST_TOTALSIZE_H (LUM_VI_BASE+0x080)
#define LUM_TST_TOTALSIZE_V (LUM_VI_BASE+0x084)
#define LUM_TST_ACTIVESIZE_H (LUM_VI_BASE+0x088)
#define LUM_TST_ACTIVESIZE_V (LUM_VI_BASE+0x08C)
#define LUM_CUT_BEGIN_H (LUM_VI_BASE+0x098)
#define LUM_CUT_END_H (LUM_VI_BASE+0x09C)
#define LUM_CUT_BEGIN_V (LUM_VI_BASE+0x0A0)
#define LUM_CUT_END_V (LUM_VI_BASE+0x0A4)
//Video Store
#define VSTORE_BASE 0x30084000
#define VSTORE_EN_CH0 (VSTORE_BASE+0x0034)
#define VSTORE_EN_CH1 (VSTORE_BASE+0x1034)
#define VSTORE_EN_CH2 (VSTORE_BASE+0x2034)
#define VSTORE_EN_CH3 (VSTORE_BASE+0x3034)
#endif

43
general/package/xiongmai-osdrv-xm530/files/include/xm/xm530_tmp.h
View File

@ -1,43 +0,0 @@
#ifndef _XM530_TMP_H_
#define _XM530_TMP_H_
#include "xm_type.h"
#include "xm_defines.h"
#include "xm_i2c.h"
#define VI_BASE (0x30000000)
#define VI_H_BEGIN (VI_BASE+0x098)
#define VI_H_END (VI_BASE+0x09C)
#define VI_V_BEGIN (VI_BASE+0x0A0)
#define VI_V_END (VI_BASE+0x0A4)
/**For read the configinit */
#define FILENAME_NOTEXIST 0x02 /*配置文件名不存在*/
#define SECTIONNAME_NOTEXIST 0x03 /*节名不存在*/
#define KEYNAME_NOTEXIST 0x04 /*键名不存在*/
#define STRING_LENNOTEQUAL 0x05 /*两个字符串长度不同*/
#define STRING_NOTEQUAL 0x06 /*两个字符串内容不相同*/
#define STRING_EQUAL 0x00 /*两个字符串内容相同*/
#define KEYNUM 2
#define NCNUM 32
XM_S32 Write_IspRegSys(XM_U32 u32Addr, XM_U32 u32Value);
XM_S32 Read_IspRegSys(XM_U32 u32Addr);
void SysDelay_ms(XM_S32 ms);
XM_S32 SysGetProductInfo(XM_PRODUCT_INFO *pstProductInfo);
XM_S32 SysSetProductInfo(XM_PRODUCT_INFO *pstProductInfo);
int XM_I2C_Ioctl(int cmd, I2C_DATA_S *pstI2CData);
XM_S32 VI_WinSet(XM_U8 u8Mode, XM_U8 u8Mirror, XM_U8 u8Flip,
XM_U16 u16ValH, XM_U16 u16ValV);
void PrintInt(unsigned char u8Num,int u32Data);
void PrintHex(unsigned char u8Num,int u32Data);
XM_U8 putstr(XM_U8 uart_NO, char const *str) ;
void SysFlagSet(XM_U32 u32Flag);
#endif

543
general/package/xiongmai-osdrv-xm530/files/include/xm/xm540_isp.h
View File

@ -1,543 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm540_isp.h
Version : Initial Draft
Author : XM Isp software group
Created : 2015/6/27
Description : The common data type defination
Function List :
History :
1.Date : 2015/6/27
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef _XM540_REG_
#define _XM540_REG_
#define VIDOEMODE_BASE 0x00A00000
#define VIDOEMODE_DECODE_SEL (VIDOEMODE_BASE+0x000)
// DPC
#define SDPC_BASE 0x00A03000
#define SDPC_CLK_SW (SDPC_BASE+0x000)
#define SDPC_SRAMADDR_CLR (SDPC_BASE+0x004)
#define SDPC_SRAMADDR_DAT (SDPC_BASE+0x008)
#define SDPC_TEST_ENABLE (SDPC_BASE+0x00C)
#define DDPC_BASE 0x00A23000
#define DDPC_MAX_THD (DDPC_BASE+0x000)
#define DDPC_MIN_THD (DDPC_BASE+0x004)
#define DDPC_DIFF_THD (DDPC_BASE+0x008)
// BlackLevel
#define BLACKLEVEL_BASE 0x00A04000
#define BLACKLEVEL_OFFSET_R (BLACKLEVEL_BASE+0x000)
#define BLACKLEVEL_OFFSET_G (BLACKLEVEL_BASE+0x004)
#define BLACKLEVEL_OFFSET_B (BLACKLEVEL_BASE+0x008)
// front Gamma
#define FRONTGAMMA_BASE 0x00A05000
//LSC
#define LSC_BASE 0x00A06000
#define LSC_CTRL (LSC_BASE+0x000)
//NR_2D
#define NR_2D_BASE 0x00A20000
#define NR_2D_FLT_EN (NR_2D_BASE + 0x018)
#define NR_2D_THDL_REG (NR_2D_BASE + 0x000)
#define NR_2D_THDH_REG (NR_2D_BASE + 0x004)
#define NR_2D_COEF_REG (NR_2D_BASE + 0x008)
#define NR_2D_GMIN_REG (NR_2D_BASE + 0x00C)
#define NR_2D_COEF_SEL_REG (NR_2D_BASE + 0x010)
#define NR_2D_DELTA_THD (NR_2D_BASE + 0x014)
//NR_3D
#define NR_3D_BASE 0x40040000
#define NR_3D_DENOSIE_CTL (NR_3D_BASE + 0x000)
#define NR_3D_ERR_PAR (NR_3D_BASE + 0x040)
#define NR_3D_BAYER_PAR (NR_3D_BASE + 0x050)
#define NR_3D_FLT2D_PAR (NR_3D_BASE + 0x14C)
//AWB
#define AWB_BASE 0x00A10000
#define AWB_FRONTGAIN_R (AWB_BASE + 0x5000)
#define AWB_FRONTGAIN_G (AWB_BASE + 0x5004)
#define AWB_FRONTGAIN_B (AWB_BASE + 0x5008)
#define AWB_RGBMAX_REG (AWB_BASE + 0x500C)
#define AWB_RGBMIN_REG (AWB_BASE + 0x5010)
#define AWB_BACKGAIN_RGAIN_RR (AWB_BASE + 0x0000)
#define AWB_BACKGAIN_RGAIN_RG (AWB_BASE + 0x0004)
#define AWB_BACKGAIN_RGAIN_BG (AWB_BASE + 0x0008)
#define AWB_BACKGAIN_RGAIN_BB (AWB_BASE + 0x000C)
#define AWB_BACKGAIN_BGAIN_RR (AWB_BASE + 0x0010)
#define AWB_BACKGAIN_BGAIN_RG (AWB_BASE + 0x0014)
#define AWB_BACKGAIN_BGAIN_BG (AWB_BASE + 0x0018)
#define AWB_BACKGAIN_BGAIN_BB (AWB_BASE + 0x001C)
#define AWB_BACKGAIN_LIMITMAX (AWB_BASE + 0x0020)
#define AWB_BACKGAIN_LIMITMIN (AWB_BASE + 0x0024)
#define AWB_CSM_BUF_SW (AWB_BASE+0x1000)
#define AWB_CSM_BUF_SW_STATE (AWB_BASE+0x1004)
#define AWB_CSM_R_OFST_REG0 (AWB_BASE+0x1040)
#define AWB_CSM_R1_COEF_REG0 (AWB_BASE+0x1044)
#define AWB_CSM_R2_COEF_REG0 (AWB_BASE+0x1048)
#define AWB_CSM_R3_COEF_REG0 (AWB_BASE+0x104C)
#define AWB_CSM_G_OFST_REG0 (AWB_BASE+0x1050)
#define AWB_CSM_G1_COEF_REG0 (AWB_BASE+0x1054)
#define AWB_CSM_G2_COEF_REG0 (AWB_BASE+0x1058)
#define AWB_CSM_G3_COEF_REG0 (AWB_BASE+0x105C)
#define AWB_CSM_B_OFST_REG0 (AWB_BASE+0x1060)
#define AWB_CSM_B1_COEF_REG0 (AWB_BASE+0x1064)
#define AWB_CSM_B2_COEF_REG0 (AWB_BASE+0x1068)
#define AWB_CSM_B3_COEF_REG0 (AWB_BASE+0x106C)
#define AWB_CSM_R_OFST_REG1 (AWB_BASE+0x1080)
#define AWB_CSM_R1_COEF_REG1 (AWB_BASE+0x1084)
#define AWB_CSM_R2_COEF_REG1 (AWB_BASE+0x1088)
#define AWB_CSM_R3_COEF_REG1 (AWB_BASE+0x108C)
#define AWB_CSM_G_OFST_REG1 (AWB_BASE+0x1090)
#define AWB_CSM_G1_COEF_REG1 (AWB_BASE+0x1094)
#define AWB_CSM_G2_COEF_REG1 (AWB_BASE+0x1098)
#define AWB_CSM_G3_COEF_REG1 (AWB_BASE+0x109C)
#define AWB_CSM_B_OFST_REG1 (AWB_BASE+0x10A0)
#define AWB_CSM_B1_COEF_REG1 (AWB_BASE+0x10A4)
#define AWB_CSM_B2_COEF_REG1 (AWB_BASE+0x10A8)
#define AWB_CSM_B3_COEF_REG1 (AWB_BASE+0x10AC)
#define AWB_GAMMA30_BUF_SW (AWB_BASE + 0x2000)
#define AWB_GAMMA30_SW_STATE (AWB_BASE + 0x2004)
#define AWB_GAMMA30_LINE0_DAT0 (AWB_BASE + 0x2040)
#define AWB_GAMMA30_LINE1_DAT0 (AWB_BASE + 0x20C0)
// AWB (RGB2YC)
#define AWB_RGB2YC_COEF_Y1 (AWB_BASE + 0x3000)
#define AWB_RGB2YC_COEF_Y2 (AWB_BASE + 0x3004)
#define AWB_RGB2YC_COEF_Y3 (AWB_BASE + 0x3008)
#define AWB_RGB2YC_COEF_CB1 (AWB_BASE + 0x300C)
#define AWB_RGB2YC_COEF_CB2 (AWB_BASE + 0x3010)
#define AWB_RGB2YC_COEF_CB3 (AWB_BASE + 0x3014)
#define AWB_RGB2YC_COEF_CR1 (AWB_BASE + 0x3018)
#define AWB_RGB2YC_COEF_CR2 (AWB_BASE + 0x301C)
#define AWB_RGB2YC_COEF_CR3 (AWB_BASE + 0x3020)
#define AWB_RGB2YC_OFST_Y (AWB_BASE + 0x3024)
#define AWB_RGB2YC_OFST_CB (AWB_BASE + 0x3028)
#define AWB_RGB2YC_OFST_CR (AWB_BASE + 0x302C)
#define AWB_WDW_VBEGIN (AWB_BASE + 0x4000)
#define AWB_WDW_VEND (AWB_BASE + 0x4004)
#define AWB_WDW_HBEGIN (AWB_BASE + 0x4008)
#define AWB_WDW_HEND (AWB_BASE + 0x400C)
#define AWB_FACT_LH (AWB_BASE + 0x4040)
#define AWB_FACT_LV (AWB_BASE + 0x4044)
#define AWB_FACT_L45 (AWB_BASE + 0x4048)
#define AWB_FACT_L135 (AWB_BASE + 0x404C)
#define AWB_FACT_RGBTHD (AWB_BASE + 0x4050)
#define AWB_FACT_YTHD (AWB_BASE + 0x4054)
#define AWB_FACT_KCBCR1 (AWB_BASE + 0x4058)
#define AWB_FACT_KCBCR2 (AWB_BASE + 0x405C)
#define AWB_FACT_KCBCR3 (AWB_BASE + 0x4060)
#define AWB_FACT_KCBCR4 (AWB_BASE + 0x4064)
#define AWB_CH1_M_WPCNT (AWB_BASE + 0x40C0)
#define AWB_CH1_M_CBSUM (AWB_BASE + 0x40C4)
#define AWB_CH1_M_CRSUM (AWB_BASE + 0x40C8)
#define AWB_CH2_M_WPCNT (AWB_BASE + 0x4100)
#define AWB_CH2_M_CBSUM (AWB_BASE + 0x4104)
#define AWB_CH2_M_CRSUM (AWB_BASE + 0x4108)
#define AWB_CH3_M_WPCNT (AWB_BASE + 0x4140)
#define AWB_CH3_M_CBSUM (AWB_BASE + 0x4144)
#define AWB_CH3_M_CRSUM (AWB_BASE + 0x4148)
#define AWB_CH4_M_WPCNT (AWB_BASE + 0x4180)
#define AWB_CH4_M_CBSUM (AWB_BASE + 0x4184)
#define AWB_CH4_M_CRSUM (AWB_BASE + 0x4188)
//AF
#define AF_BASE 0x00A21000
#define AF_WDW0_VBEGIN (AF_BASE + 0x000)
#define AF_WDW0_VEND (AF_BASE + 0x004)
#define AF_WDW0_HBEGIN (AF_BASE + 0x008)
#define AF_WDW0_HEND (AF_BASE + 0x00C)
#define AF_WDW0_HZ (AF_BASE + 0x094)
//AE
#define AE_BASEADDR 0x00A30000
#define AE_WINDOW_VSTART (AE_BASEADDR + 0x3000)
#define AE_WINDOW_HSTART (AE_BASEADDR + 0x3020)
#define AE_WINDOWY_ROW1 (AE_BASEADDR + 0x3100)
#define AE_WINDOWY_ROW2 (AE_BASEADDR + 0x311C)
#define AE_WINDOWY_ROW3 (AE_BASEADDR + 0x3140)
#define AE_WINDOWY_ROW4 (AE_BASEADDR + 0x315C)
#define AE_WINDOWY_ROW5 (AE_BASEADDR + 0x3180)
#define AE_WINDOWY_ROW6 (AE_BASEADDR + 0x319C)
#define AE_WINDOWY_ROW7 (AE_BASEADDR + 0x31C0)
#define AE_HIST_COUNT (AE_BASEADDR + 0x3080)
// Demosaic
#define DEMOSAIC_BASE 0x00A50000
#define DEMOSAIC_G_HOFST (DEMOSAIC_BASE + 0x000)
#define DEMOSAIC_DHV_OFST (DEMOSAIC_BASE + 0x004)
#define DEMOSAIC_DHV_K (DEMOSAIC_BASE + 0x008)
// CSM
#define CSM_BASE 0x00A60000
#define CSM_BUF_SW (CSM_BASE+0x000)
#define CSM_BUF_SW_STATE (CSM_BASE+0x004)
#define CSM_R_OFST_REG0 (CSM_BASE+0x040)
#define CSM_R1_COEF_REG0 (CSM_BASE+0x044)
#define CSM_R2_COEF_REG0 (CSM_BASE+0x048)
#define CSM_R3_COEF_REG0 (CSM_BASE+0x04C)
#define CSM_G_OFST_REG0 (CSM_BASE+0x050)
#define CSM_G1_COEF_REG0 (CSM_BASE+0x054)
#define CSM_G2_COEF_REG0 (CSM_BASE+0x058)
#define CSM_G3_COEF_REG0 (CSM_BASE+0x05C)
#define CSM_B_OFST_REG0 (CSM_BASE+0x060)
#define CSM_B1_COEF_REG0 (CSM_BASE+0x064)
#define CSM_B2_COEF_REG0 (CSM_BASE+0x068)
#define CSM_B3_COEF_REG0 (CSM_BASE+0x06C)
#define CSM_R_OFST_REG1 (CSM_BASE+0x080)
#define CSM_R1_COEF_REG1 (CSM_BASE+0x084)
#define CSM_R2_COEF_REG1 (CSM_BASE+0x088)
#define CSM_R3_COEF_REG1 (CSM_BASE+0x08C)
#define CSM_G_OFST_REG1 (CSM_BASE+0x090)
#define CSM_G1_COEF_REG1 (CSM_BASE+0x094)
#define CSM_G2_COEF_REG1 (CSM_BASE+0x098)
#define CSM_G3_COEF_REG1 (CSM_BASE+0x09C)
#define CSM_B_OFST_REG1 (CSM_BASE+0x0A0)
#define CSM_B1_COEF_REG1 (CSM_BASE+0x0A4)
#define CSM_B2_COEF_REG1 (CSM_BASE+0x0A8)
#define CSM_B3_COEF_REG1 (CSM_BASE+0x0AC)
// Gamma60
#define GAMMA60_BASE 0x00A61000
#define GAMMA60_BUF_SW (GAMMA60_BASE+0x000)
#define GAMMA60_BUF_SW_STATE (GAMMA60_BASE+0x004)
#define GAMMA60_LINE0_DAT0 (GAMMA60_BASE+0x040)
#define GAMMA60_LINE1_DAT0 (GAMMA60_BASE+0x140)
// RGB2YC
#define RGB2YC_BASE 0x00A63000
// Demoire
#define DEMOIRE_BASE 0x00A64000
#define DEMOIRE_BYPASS (DEMOIRE_BASE+0x018)
#define DEMOIRE_V_THD (DEMOIRE_BASE+0x000)
#define DEMOIRE_KV (DEMOIRE_BASE+0x004)
#define DEMOIRE_DF_THD_MAX (DEMOIRE_BASE+0x008)
#define DEMOIRE_DF_THD_MIN (DEMOIRE_BASE+0x00C)
#define DEMOIRE_GAIN_MIN (DEMOIRE_BASE+0x010)
#define DEMOIRE_KC (DEMOIRE_BASE+0x014)
// CC
#define CC_BASE 0x00A70000
#define CC_EN_REG (CC_BASE+0x000)
#define CC_HUE_OFST (CC_BASE+0x018)
#define CC_HS_TRAN_DAT0 (CC_BASE+0x0E4)
#define CC_HS_TRAN_DAT1 (CC_BASE+0x0E8)
#define CC_HH_H1_SATRT (CC_BASE+0x200)
#define CC_HH_H1_END (CC_BASE+0x204)
#define CC_HH_H1_MAX1 (CC_BASE+0x208)
#define CC_HH_H1_MAX2 (CC_BASE+0x20C)
#define CC_HH_H1_DMAX (CC_BASE+0x210)
#define CC_HH_H1_K1 (CC_BASE+0x214)
#define CC_HH_H1_K2 (CC_BASE+0x218)
#define CC_HH_H2_SATRT (CC_BASE+0x21C)
#define CC_HH_H2_END (CC_BASE+0x220)
#define CC_HH_H2_MAX1 (CC_BASE+0x224)
#define CC_HH_H2_MAX2 (CC_BASE+0x228)
#define CC_HH_H2_DMAX (CC_BASE+0x22C)
#define CC_HH_H2_K1 (CC_BASE+0x230)
#define CC_HH_H2_K2 (CC_BASE+0x234)
#define CC_HH_H3_SATRT (CC_BASE+0x240)
#define CC_HH_H3_END (CC_BASE+0x244)
#define CC_HH_H3_MAX1 (CC_BASE+0x248)
#define CC_HH_H3_MAX2 (CC_BASE+0x24C)
#define CC_HH_H3_DMAX (CC_BASE+0x250)
#define CC_HH_H3_K1 (CC_BASE+0x254)
#define CC_HH_H3_K2 (CC_BASE+0x258)
#define CC_HH_H4_SATRT (CC_BASE+0x25C)
#define CC_HH_H4_END (CC_BASE+0x260)
#define CC_HH_H4_MAX1 (CC_BASE+0x264)
#define CC_HH_H4_MAX2 (CC_BASE+0x268)
#define CC_HH_H4_DMAX (CC_BASE+0x26C)
#define CC_HH_H4_K1 (CC_BASE+0x270)
#define CC_HH_H4_K2 (CC_BASE+0x274)
#define CC_HH_H5_SATRT (CC_BASE+0x280)
#define CC_HH_H5_END (CC_BASE+0x284)
#define CC_HH_H5_MAX1 (CC_BASE+0x288)
#define CC_HH_H5_MAX2 (CC_BASE+0x28C)
#define CC_HH_H5_DMAX (CC_BASE+0x290)
#define CC_HH_H5_K1 (CC_BASE+0x294)
#define CC_HH_H5_K2 (CC_BASE+0x298)
#define CC_HH_H6_SATRT (CC_BASE+0x29C)
#define CC_HH_H6_END (CC_BASE+0x2A0)
#define CC_HH_H6_MAX1 (CC_BASE+0x2A4)
#define CC_HH_H6_MAX2 (CC_BASE+0x2A8)
#define CC_HH_H6_DMAX (CC_BASE+0x2AC)
#define CC_HH_H6_K1 (CC_BASE+0x2B0)
#define CC_HH_H6_K2 (CC_BASE+0x2B4)
// Y_Gamma
#define YGAMMA_BASE 0x00A71000
#define YGAMMA_BUF_SW (YGAMMA_BASE+0x000)
#define YGAMMA_BUF_SW_STATE (YGAMMA_BASE+0x004)
#define YGAMMA_LINE0_DAT0 (YGAMMA_BASE+0x040)
#define YGAMMA_LINE1_DAT0 (YGAMMA_BASE+0x180)
#define YHIST_BASE (0x00A72000)
#define YHIST_CNT0 (YHIST_BASE+0x000)
#define CTRAN_BASE 0x00A73000
// Sharpness
#define SHARPEN_BASE 0x00A74000
#define SHARPEN_H00_SEL (SHARPEN_BASE+(0x004))
#define SHARPEN_KH1 (SHARPEN_BASE+(0x008))
#define SHARPEN_KL1 (SHARPEN_BASE+(0x00C))
#define SHARPEN_DMAX (SHARPEN_BASE+(0x010))
#define SHARPEN_KD (SHARPEN_BASE+(0x018))
#define SHARPEN_KD_MAX (SHARPEN_BASE+(0x01C))
#define SHARPEN_TRAN_DAT0 (SHARPEN_BASE+(0x020))
#define SHARPEN_YMTH1 (SHARPEN_BASE+(0x128))
#define SHARPEN_YMTH2 (SHARPEN_BASE+(0x12C))
#define SHARPEN_KKM (SHARPEN_BASE+(0x130))
#define SHARPEN_WM0 (SHARPEN_BASE+(0x134))
#define SHARPEN_WM1 (SHARPEN_BASE+(0x138))
#define SHARPEN_WM2 (SHARPEN_BASE+(0x13C))
#define SHARPEN_WM3 (SHARPEN_BASE+(0x140))
#define SHARPEN_WM4 (SHARPEN_BASE+(0x144))
#define SHARPEN_WM5 (SHARPEN_BASE+(0x148))
#define SHARPEN_KM0 (SHARPEN_BASE+(0x14c))
#define SHARPEN_YHTH1 (SHARPEN_BASE+(0x150))
#define SHARPEN_YHTH2 (SHARPEN_BASE+(0x154))
#define SHARPEN_KKH (SHARPEN_BASE+(0x158))
#define SHARPEN_WH0 (SHARPEN_BASE+(0x15C))
#define SHARPEN_WH1 (SHARPEN_BASE+(0x160))
#define SHARPEN_WH2 (SHARPEN_BASE+(0x164))
#define SHARPEN_WH3 (SHARPEN_BASE+(0x168))
#define SHARPEN_WH4 (SHARPEN_BASE+(0x16C))
#define SHARPEN_WH5 (SHARPEN_BASE+(0x170))
#define SHARPEN_KH0 (SHARPEN_BASE+(0x174))
#define SHARPEN_YMDTH1 (SHARPEN_BASE+(0x178))
#define SHARPEN_YMDTH2 (SHARPEN_BASE+(0x17C))
#define SHARPEN_KKMD (SHARPEN_BASE+(0x180))
#define SHARPEN_WMD0 (SHARPEN_BASE+(0x184))
#define SHARPEN_WMD1 (SHARPEN_BASE+(0x188))
#define SHARPEN_WMD2 (SHARPEN_BASE+(0x18C))
#define SHARPEN_WMD3 (SHARPEN_BASE+(0x190))
#define SHARPEN_WMD4 (SHARPEN_BASE+(0x194))
#define SHARPEN_WMD5 (SHARPEN_BASE+(0x198))
#define SHARPEN_KMD_MAX (SHARPEN_BASE+(0x19C))
#define SHARPEN_YHDTH1 (SHARPEN_BASE+(0x1A0))
#define SHARPEN_YHDTH2 (SHARPEN_BASE+(0x1A4))
#define SHARPEN_KKHD (SHARPEN_BASE+(0x1A8))
#define SHARPEN_WHD0 (SHARPEN_BASE+(0x1AC))
#define SHARPEN_WHD1 (SHARPEN_BASE+(0x1B0))
#define SHARPEN_WHD2 (SHARPEN_BASE+(0x1B4))
#define SHARPEN_WHD3 (SHARPEN_BASE+(0x1B8))
#define SHARPEN_WHD4 (SHARPEN_BASE+(0x1BC))
#define SHARPEN_WHD5 (SHARPEN_BASE+(0x1C0))
#define SHARPEN_KHD_MAX (SHARPEN_BASE+(0x1C4))
#define SHARPEN_KCMIN (SHARPEN_BASE+(0x1E8))
#define SHARPEN_ENABLE (SHARPEN_BASE+(0x204))
#define SHARPEN_CBCR_ENABLE (SHARPEN_BASE+(0x208))
// Y_tran
#define Y_TRAN_BASE 0x00A71000
#define Y_TRAN_BUF_SW (Y_TRAN_BASE+(0x000))
#define Y_TRAN_BUF_STATE (Y_TRAN_BASE+(0x004))
#define Y_TRAN_LINE0_DAT0 (Y_TRAN_BASE+(0x040))
#define Y_TRAN_LINE1_DAT0 (Y_TRAN_BASE+(0x180))
// C_tran
#define C_TRAN_BASE 0x00A73000
#define C_TRAN_BUF_SW (Y_TRAN_BASE+(0x000))
#define C_TRAN_BUF_STATE (Y_TRAN_BASE+(0x004))
#define C_TRAN_LINE0_DAT0 (Y_TRAN_BASE+(0x040))
#define C_TRAN_LINE1_DAT0 (Y_TRAN_BASE+(0x080))
// YC_Gain
#define YC_GAIN_BASE 0x00A75000
#define Y_GAIN (YC_GAIN_BASE+(0x000))
#define CB_GAIN (YC_GAIN_BASE+(0x004))
#define CR_GAIN (YC_GAIN_BASE+(0x008))
//PLL
#define PLL_BASE (0xFFFF0000)
#define PLL1_CTRL (PLL_BASE + 0x18)
#define PLL1_SENSOR_POSTD (PLL_BASE + 0x20)
#define PLL1_AHD_POSTD (PLL_BASE + 0x24)
#define PLL2_PRED (PLL_BASE + 0x28)
#define PLL2_CTRL (PLL_BASE + 0x30)
#define PLL2_AHD_POSTD (PLL_BASE + 0x34)
#define PLL_BIAS_EN (PLL_BASE + 0x38)
// AWB2
#if 0
#define AWB2_BASE (0x00A10000)
#define AWB2_BACKGAIN_RGAIN_RR (AWB2_BASE+0x0000)
#define AWB2_BACKGAIN_GGAIN_RG (AWB2_BASE+0x0004)
#define AWB2_BACKGAIN_BGAIN_BG (AWB2_BASE+0x0008)
#define AWB2_BACKRGB_MAX_REG (AWB2_BASE+0x000C)
#define AWB2_BACKRGB_MIN_REG (AWB2_BASE+0x0010)
#define AWB2_WDW_PIXL0 (AWB2_BASE+0x1000)
#define AWB2_WDW_PIXL1 (AWB2_BASE+0x1004)
#define AWB2_WDW_PIXL2 (AWB2_BASE+0x1008)
#define AWB2_WDW_PIXL3 (AWB2_BASE+0x100C)
#define AWB2_WDW_PIXL4 (AWB2_BASE+0x1010)
#define AWB2_WDW_PIXL5 (AWB2_BASE+0x1014)
#define AWB2_WDW_PIXL6 (AWB2_BASE+0x1018)
#define AWB2_WDW_PIXL7 (AWB2_BASE+0x101C)
#define AWB2_WDW_PIXL8 (AWB2_BASE+0x1020)
#define AWB2_WDW_PIXL9 (AWB2_BASE+0x1024)
#define AWB2_WDW_PIXL10 (AWB2_BASE+0x1028)
#define AWB2_WDW_PIXL11 (AWB2_BASE+0x102C)
#define AWB2_WDW_PIXL12 (AWB2_BASE+0x1030)
#define AWB2_WDW_PIXL13 (AWB2_BASE+0x1034)
#define AWB2_WDW_PIXL14 (AWB2_BASE+0x1038)
#define AWB2_WDW_PIXL15 (AWB2_BASE+0x103C)
#define AWB2_WDW_PIXL16 (AWB2_BASE+0x1040)
#define AWB2_WDW_PIXL17 (AWB2_BASE+0x1044)
#define AWB2_WDW_PIXL18 (AWB2_BASE+0x1048)
#define AWB2_WDW_PIXL19 (AWB2_BASE+0x104C)
#define AWB2_WDW_PIXL20 (AWB2_BASE+0x1050)
#define AWB2_WDW_PIXL21 (AWB2_BASE+0x1054)
#define AWB2_WDW_PIXL22 (AWB2_BASE+0x1058)
#define AWB2_WDW_PIXL23 (AWB2_BASE+0x105C)
#define AWB2_WDW_PIXL24 (AWB2_BASE+0x1060)
#define AWB2_WDW_PIXL25 (AWB2_BASE+0x1064)
#define AWB2_WDW_PIXL26 (AWB2_BASE+0x1068)
#define AWB2_WDW_PIXL27 (AWB2_BASE+0x106C)
#define AWB2_WDW_PIXL28 (AWB2_BASE+0x1070)
#define AWB2_WDW_PIXL29 (AWB2_BASE+0x1074)
#define AWB2_WDW_PIXL30 (AWB2_BASE+0x1078)
#define AWB2_WDW_PIXL31 (AWB2_BASE+0x107C)
#define AWB2_WDW_PIXL32 (AWB2_BASE+0x1080)
#define AWB2_WDW_LINE0 (AWB2_BASE+0x10C0)
#define AWB2_WDW_LINE1 (AWB2_BASE+0x10C4)
#define AWB2_WDW_LINE2 (AWB2_BASE+0x10C8)
#define AWB2_WDW_LINE3 (AWB2_BASE+0x10CC)
#define AWB2_WDW_LINE4 (AWB2_BASE+0x10D0)
#define AWB2_WDW_LINE5 (AWB2_BASE+0x10D4)
#define AWB2_WDW_LINE6 (AWB2_BASE+0x10D8)
#define AWB2_WDW_LINE7 (AWB2_BASE+0x10DC)
#define AWB2_WDW_LINE8 (AWB2_BASE+0x10E0)
#define AWB2_WDW_LINE9 (AWB2_BASE+0x10E4)
#define AWB2_WDW_LINE10 (AWB2_BASE+0x10E8)
#define AWB2_WDW_LINE11 (AWB2_BASE+0x10EC)
#define AWB2_WDW_LINE12 (AWB2_BASE+0x10F0)
#define AWB2_WDW_LINE13 (AWB2_BASE+0x10F4)
#define AWB2_WDW_LINE14 (AWB2_BASE+0x10F8)
#define AWB2_WDW_LINE15 (AWB2_BASE+0x10FC)
#define AWB2_WDW_LINE16 (AWB2_BASE+0x1100)
#define AWB2_SRAM_ADDR_RC (AWB2_BASE+0x1140)
#define AWB2_SRAM_RD_EN (AWB2_BASE+0x1144)
#define AWB2_R_INTG (AWB2_BASE+0x1148)
#define AWB2_G_INTG (AWB2_BASE+0x114C)
#define AWB2_B_INTG (AWB2_BASE+0x1150)
#define AWB2_HIST_RGB_SEL (AWB2_BASE+0x2000)
#define AWB2_HIST_CNT0 (AWB2_BASE+0x2040)
#define AWB2_HIST_CNT1 (AWB2_BASE+0x2044)
#define AWB2_HIST_CNT2 (AWB2_BASE+0x2048)
#define AWB2_HIST_CNT3 (AWB2_BASE+0x204C)
#define AWB2_HIST_CNT4 (AWB2_BASE+0x2050)
#define AWB2_HIST_CNT5 (AWB2_BASE+0x2054)
#define AWB2_HIST_CNT6 (AWB2_BASE+0x2058)
#define AWB2_HIST_CNT7 (AWB2_BASE+0x205C)
#define AWB2_HIST_CNT8 (AWB2_BASE+0x2060)
#define AWB2_HIST_CNT9 (AWB2_BASE+0x2064)
#define AWB2_HIST_CNT10 (AWB2_BASE+0x2068)
#define AWB2_HIST_CNT11 (AWB2_BASE+0x206C)
#define AWB2_HIST_CNT12 (AWB2_BASE+0x2070)
#define AWB2_HIST_CNT13 (AWB2_BASE+0x2074)
#define AWB2_HIST_CNT14 (AWB2_BASE+0x2078)
#define AWB2_HIST_CNT15 (AWB2_BASE+0x207C)
#define AWB2_HIST_CNT16 (AWB2_BASE+0x2080)
#define AWB2_HIST_CNT17 (AWB2_BASE+0x2084)
#define AWB2_HIST_CNT18 (AWB2_BASE+0x2088)
#define AWB2_HIST_CNT19 (AWB2_BASE+0x208C)
#define AWB2_HIST_CNT20 (AWB2_BASE+0x2090)
#define AWB2_HIST_CNT21 (AWB2_BASE+0x2094)
#define AWB2_HIST_CNT22 (AWB2_BASE+0x2098)
#define AWB2_HIST_CNT23 (AWB2_BASE+0x209C)
#define AWB2_HIST_CNT24 (AWB2_BASE+0x20A0)
#define AWB2_HIST_CNT25 (AWB2_BASE+0x20A4)
#define AWB2_HIST_CNT26 (AWB2_BASE+0x20A8)
#define AWB2_HIST_CNT27 (AWB2_BASE+0x20AC)
#define AWB2_HIST_CNT28 (AWB2_BASE+0x20B0)
#define AWB2_HIST_CNT29 (AWB2_BASE+0x20B4)
#define AWB2_HIST_CNT30 (AWB2_BASE+0x20B8)
#define AWB2_HIST_CNT31 (AWB2_BASE+0x20BC)
#endif
#endif

94
general/package/xiongmai-osdrv-xm530/files/include/xm/xm540_tmp.h
View File

@ -1,94 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm540_tmp.h
Version : Initial Draft
Author : XM Isp software group
Created : 2015/6/27
Description : The common data type defination
Function List :
History :
1.Date : 2015/6/27
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef _XM540_TMP_H_
#define _XM540_TMP_H_
#include "xm_i2c.h"
#include "xm_ssp.h"
#include "xm_type.h"
#include "xm_ae_comm.h"
#include "xm_awb_comm.h"
#include "xm_comm_sns.h"
#include "xm_comm_3a.h"
#define VI_BASE (0x00A00000)
#define VI_H_BEGIN (VI_BASE+0x098)
#define VI_H_END (VI_BASE+0x09C)
#define VI_V_BEGIN (VI_BASE+0x0A0)
#define VI_V_END (VI_BASE+0x0A4)
/*************************************************************************
函数功能: 配置VI裁剪参数(H、V)
输出参数: u8Mode:
0: Real Data(实际值)
1: 基于标准值进行偏移
2: Refresh
u8Mirror:
1: Mirror
u8Flip:
1: Flip
u16ValH: 水平方向值(bit15:为符号) [0, 0xFFFE]
0~0x7FFF :
0x8000 ~ 0xFFFE : <0
u16ValV: 垂直方向值(bit15:为符号) [0, 0xFFFE]
0~0x7FFF :
0x8000 ~ 0xFFFE : <0
note:
u16ValH/u16ValV = 0xFFFF 时标准不写入
*************************************************************************/
XM_S32 VI_WinSet(XM_U8 u8Mode, XM_U8 u8Mirror, XM_U8 u8Flip,
XM_U16 u16ValH, XM_U16 u16ValV);
int XM_I2C_Ioctl(int cmd, I2C_DATA_S *pstI2CData);
int XM_SPI_Ioctl(int cmd, XM_U32* pu32Data);
void I2C_Write(XM_U32 addr, XM_U32 data);
void PrintHex(unsigned char u8Num, XM_U64 u64Data);
void PrintInt(unsigned char u8Num,int u32Data);
void SysDelay_ms(unsigned int nms);
XM_S32 SysGetProductInfo_Ptr(XM_PRODUCT_INFO **pstProductInfo);
/***********************************************************************
函数名称: SysReadFromFlash
函数功能: 读取FLash配置
输入参数: pu8Data: 缓存地址
u32Addr: 读取地址
u32Len: 读取长度
输出参数: 无
返回参数: 1: 成功
0: 出错
Note:Lycai
***********************************************************************/
XM_BOOL SysReadFromFlash(XM_U8 *pu8Data, XM_U32 u32Addr, XM_U32 u32Len);
/**********************************************************************
函数功能: 配置色同步
输入参数: u8BurstMode: 0 No CSync
1 have CSync
u8ColorMode: 0 BW
1 Color
输出参数: 无
返回参数: 0: Success
-1: Failure
**********************************************************************/
XM_S32 XM_MPI_VENC_SetColor(XM_U8 u8BurstMode, XM_U8 u8ColorMode);
#endif

674
general/package/xiongmai-osdrv-xm530/files/include/xm/xm550_isp.h
View File

@ -1,674 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm550_isp.h
Version : Initial Draft
Author : XM Isp software group
Created : 2016/11/26
Description : The common data type defination
Function List :
History :
1.Date : 2016/11/24
Author : Ganwencao
Modification : creat
******************************************************************************/
#ifndef _XM550_REG_
#define _XM550_REG_
#define DDR_BASE_ADDR (0x80000000)
#define ISP_BASE_ADDR 0x30000000
//video_main
#define VIDEOMAIN_RGBIR_SEL (0x300f000c)
//pre_video
//CH1
#define VIDEOMODE_BASE_CH1 (ISP_BASE_ADDR+0x0)
#define VIDEOMODE_DECODE_SEL_CH1 (VIDOEMODE_BASE_CH1+0x000)
#define VIDEOMODE_SLA_MAT_SEL_CH1 (VIDOEMODE_BASE_CH1+0x004)
#define VIDEOMODE_DEC_DATA_SEL_CH1 (VIDOEMODE_BASE_CH1+0x008)
//CH2
//#define VIDOEMODE_BASE_CH2 0x30001000
#define VIDEOMODE_BASE_CH2 (ISP_BASE_ADDR+0x1000)
#define VIDEO2MODE_DECODE_SEL_CH2 (VIDOEMODE_BASE_CH2+0x000)
#define VIDEO2MODE_SLA_MAT_SEL_CH2 (VIDOEMODE_BASE_CH2+0x004)
#define VIDEO2MODE_DEC_DATA_SEL_CH2 (VIDOEMODE_BASE_CH2+0x008)
// DPC
//#define SDPC_BASE 0x30003000
#define SDPC_BASE (ISP_BASE_ADDR+0x3000)
#define SDPC_CLK_SW (SDPC_BASE+0x000)
#define SDPC_SRAMADDR_CLR (SDPC_BASE+0x004)
#define SDPC_SRAMADDR_DAT (SDPC_BASE+0x008)
#define SDPC_TEST_ENABLE (SDPC_BASE+0x00C)
// BlackLevel
#define BLACKLEVEL_BASE (ISP_BASE_ADDR+0x4000)
#define BLACKLEVEL_OFFSET_R_CH1 (BLACKLEVEL_BASE+0x000)
#define BLACKLEVEL_OFFSET_G_CH1 (BLACKLEVEL_BASE+0x004)
#define BLACKLEVEL_OFFSET_B_CH1 (BLACKLEVEL_BASE+0x008)
#define BLACKLEVEL_RGB_MAX_CH1 (BLACKLEVEL_BASE+0x00C)
#define BLACKLEVEL_RGB_MIN_CH1 (BLACKLEVEL_BASE+0x010)
#define BLACKLEVEL_OFFSET_R_CH2 (BLACKLEVEL_BASE+0x040)
#define BLACKLEVEL_OFFSET_G_CH2 (BLACKLEVEL_BASE+0x044)
#define BLACKLEVEL_OFFSET_B_CH2 (BLACKLEVEL_BASE+0x048)
#define BLACKLEVEL_RGB_MAX_CH2 (BLACKLEVEL_BASE+0x04C)
#define BLACKLEVEL_RGB_MIN_CH2 (BLACKLEVEL_BASE+0x050)
// DIGTAL_GAIN
#define DIGITAL_GAIN_BASE (ISP_BASE_ADDR+0x5000)
#define DIGITAL_GAIN_CH1 (DIGITAL_GAIN_BASE+0x0)
#define DIGITAL_GAIN_CH2 (DIGITAL_GAIN_BASE+0x10)
//LSC
#define LSC_BASE (ISP_BASE_ADDR+0x6000)
#define LSC_CTRL (LSC_BASE+0x000)
//HDR
#define HDR_BASE (ISP_BASE_ADDR+0x0000)
#define HDR_R_GAIN (HDR_BASE+0x8000)
#define HDR_G_GAIN (HDR_BASE+0x8004)
#define HDR_B_GAIN (HDR_BASE+0x8008)
#define HDR_RGB_MAX (HDR_BASE+0x800C)
#define HDR_RGB_MIN (HDR_BASE+0x8010)
#define HDR_CLIP_WT_MAX (HDR_BASE+0x9000)
#define HDR_CLIP_WT_MIN (HDR_BASE+0x9004)
#define HDR_MOTION_THR (HDR_BASE+0x9008)
#define HDR_V_MAX (HDR_BASE+0x900C)
#define HDR_LS_TIME_RATIO (HDR_BASE+0x9010)
#define HDR_LE_WT_MIN (HDR_BASE+0x9014)
#define HDR_SE_WT_RATIO (HDR_BASE+0x9018)
#define HDR_DCTTAB_DAT0 (HDR_BASE+0xA040)
#define HDR_USMINTENS (HDR_BASE+0xB028)
#define HDR_FUSWT (HDR_BASE+0xB02C)
//NIR
#define NIR_BASE (ISP_BASE_ADDR+0x30000)
#define NIR_IR_INTG (NIR_BASE + 0x2000)
#define NIR_R_INTG (NIR_BASE + 0x2004)
#define NIR_G_INTG (NIR_BASE + 0x2008)
#define NIR_B_INTG (NIR_BASE + 0x200C)
#define NIR_RGB_INTG (NIR_BASE + 0x2010)
#define NIR_RS_RAT (NIR_BASE + 0x1004)
#define NIR_GS_RAT (NIR_BASE + 0x1008)
#define NIR_BS_RAT (NIR_BASE + 0x100C)
#define NIR_HIR_COEF1 (NIR_BASE + 0x0018)
#define NIR_HIR_COEF2 (NIR_BASE + 0x001C)
#define NIR_HIR_COEF3 (NIR_BASE + 0x0020)
#define NIR_LUMLUT0 (NIR_BASE + 0x1080)
//AWB
#define AWB_BASE (ISP_BASE_ADDR+0x10000)
#define AWB_FRONTGAIN_R_CH1 (AWB_BASE+0x0)
#define AWB_FRONTGAIN_G_CH1 (AWB_BASE+0x4)
#define AWB_FRONTGAIN_B_CH1 (AWB_BASE+0x8)
#define AWB_RGBMAX_REG_CH1 (AWB_BASE+0xC)
#define AWB_RGBMIN_REG_CH1 (AWB_BASE+0x10)
#define AWB_FRONTGAIN_R_CH2 (AWB_BASE+0x40)
#define AWB_FRONTGAIN_G_CH2 (AWB_BASE+0x44)
#define AWB_FRONTGAIN_B_CH2 (AWB_BASE+0x48)
#define AWB_RGBMAX_REG_CH2 (AWB_BASE+0x4C)
#define AWB_RGBMIN_REG_CH2 (AWB_BASE+0x50)
#define AWB_WDW_PIXL0 (AWB_BASE+0x1000)
#define AWB_WDW_PIXL1 (AWB_BASE+0x1004)
#define AWB_WDW_PIXL2 (AWB_BASE+0x1008)
#define AWB_WDW_PIXL3 (AWB_BASE+0x100C)
#define AWB_WDW_PIXL4 (AWB_BASE+0x1010)
#define AWB_WDW_PIXL5 (AWB_BASE+0x1014)
#define AWB_WDW_PIXL6 (AWB_BASE+0x1018)
#define AWB_WDW_PIXL7 (AWB_BASE+0x101C)
#define AWB_WDW_PIXL8 (AWB_BASE+0x1020)
#define AWB_WDW_PIXL9 (AWB_BASE+0x1024)
#define AWB_WDW_PIXL10 (AWB_BASE+0x1028)
#define AWB_WDW_PIXL11 (AWB_BASE+0x102C)
#define AWB_WDW_PIXL12 (AWB_BASE+0x1030)
#define AWB_WDW_PIXL13 (AWB_BASE+0x1034)
#define AWB_WDW_PIXL14 (AWB_BASE+0x1038)
#define AWB_WDW_PIXL15 (AWB_BASE+0x103C)
#define AWB_WDW_PIXL16 (AWB_BASE+0x1040)
#define AWB_WDW_PIXL17 (AWB_BASE+0x1044)
#define AWB_WDW_PIXL18 (AWB_BASE+0x1048)
#define AWB_WDW_PIXL19 (AWB_BASE+0x104C)
#define AWB_WDW_PIXL20 (AWB_BASE+0x1050)
#define AWB_WDW_PIXL21 (AWB_BASE+0x1054)
#define AWB_WDW_PIXL22 (AWB_BASE+0x1058)
#define AWB_WDW_PIXL23 (AWB_BASE+0x105C)
#define AWB_WDW_PIXL24 (AWB_BASE+0x1060)
#define AWB_WDW_PIXL25 (AWB_BASE+0x1064)
#define AWB_WDW_PIXL26 (AWB_BASE+0x1068)
#define AWB_WDW_PIXL27 (AWB_BASE+0x106C)
#define AWB_WDW_PIXL28 (AWB_BASE+0x1070)
#define AWB_WDW_PIXL29 (AWB_BASE+0x1074)
#define AWB_WDW_PIXL30 (AWB_BASE+0x1078)
#define AWB_WDW_PIXL31 (AWB_BASE+0x107C)
#define AWB_WDW_PIXL32 (AWB_BASE+0x1080)
#define AWB_WDW_LINE0 (AWB_BASE+0x10C0)
#define AWB_WDW_LINE1 (AWB_BASE+0x10C4)
#define AWB_WDW_LINE2 (AWB_BASE+0x10C8)
#define AWB_WDW_LINE3 (AWB_BASE+0x10CC)
#define AWB_WDW_LINE4 (AWB_BASE+0x10D0)
#define AWB_WDW_LINE5 (AWB_BASE+0x10D4)
#define AWB_WDW_LINE6 (AWB_BASE+0x10D8)
#define AWB_WDW_LINE7 (AWB_BASE+0x10DC)
#define AWB_WDW_LINE8 (AWB_BASE+0x10E0)
#define AWB_WDW_LINE9 (AWB_BASE+0x10E4)
#define AWB_WDW_LINE10 (AWB_BASE+0x10E8)
#define AWB_WDW_LINE11 (AWB_BASE+0x10EC)
#define AWB_WDW_LINE12 (AWB_BASE+0x10F0)
#define AWB_WDW_LINE13 (AWB_BASE+0x10F4)
#define AWB_WDW_LINE14 (AWB_BASE+0x10F8)
#define AWB_WDW_LINE15 (AWB_BASE+0x10FC)
#define AWB_WDW_LINE16 (AWB_BASE+0x1100)
#define AWB_SRAM_ADDR_RC (AWB_BASE+0x1140)
#define AWB_SRAM_RD_EN (AWB_BASE+0x1144)
#define AWB_R_INTG (AWB_BASE+0x1148)
#define AWB_G_INTG (AWB_BASE+0x114C)
#define AWB_B_INTG (AWB_BASE+0x1150)
#define AWB_HDR_LS_MODE (AWB_BASE+0x1180)
#define AWB_FRAME_CH_SEL (AWB_BASE+0x1184)
#define AWB_HIST_RGB_SEL (AWB_BASE+0x2000)
#define AWB_HIST_CNT0 (AWB_BASE+0x2040)
#define AWB_HIST_CNT1 (AWB_BASE+0x2044)
#define AWB_HIST_CNT2 (AWB_BASE+0x2048)
#define AWB_HIST_CNT3 (AWB_BASE+0x204C)
#define AWB_HIST_CNT4 (AWB_BASE+0x2050)
#define AWB_HIST_CNT5 (AWB_BASE+0x2054)
#define AWB_HIST_CNT6 (AWB_BASE+0x2058)
#define AWB_HIST_CNT7 (AWB_BASE+0x205C)
#define AWB_HIST_CNT8 (AWB_BASE+0x2060)
#define AWB_HIST_CNT9 (AWB_BASE+0x2064)
#define AWB_HIST_CNT10 (AWB_BASE+0x2068)
#define AWB_HIST_CNT11 (AWB_BASE+0x206C)
#define AWB_HIST_CNT12 (AWB_BASE+0x2070)
#define AWB_HIST_CNT13 (AWB_BASE+0x2074)
#define AWB_HIST_CNT14 (AWB_BASE+0x2078)
#define AWB_HIST_CNT15 (AWB_BASE+0x207C)
#define AWB_HIST_CNT16 (AWB_BASE+0x2080)
#define AWB_HIST_CNT17 (AWB_BASE+0x2084)
#define AWB_HIST_CNT18 (AWB_BASE+0x2088)
#define AWB_HIST_CNT19 (AWB_BASE+0x208C)
#define AWB_HIST_CNT20 (AWB_BASE+0x2090)
#define AWB_HIST_CNT21 (AWB_BASE+0x2094)
#define AWB_HIST_CNT22 (AWB_BASE+0x2098)
#define AWB_HIST_CNT23 (AWB_BASE+0x209C)
#define AWB_HIST_CNT24 (AWB_BASE+0x20A0)
#define AWB_HIST_CNT25 (AWB_BASE+0x20A4)
#define AWB_HIST_CNT26 (AWB_BASE+0x20A8)
#define AWB_HIST_CNT27 (AWB_BASE+0x20AC)
#define AWB_HIST_CNT28 (AWB_BASE+0x20B0)
#define AWB_HIST_CNT29 (AWB_BASE+0x20B4)
#define AWB_HIST_CNT30 (AWB_BASE+0x20B8)
#define AWB_HIST_CNT31 (AWB_BASE+0x20BC)
//AF
#define DDPC_BASE (ISP_BASE_ADDR+0x23000)
#define DDPC_MAX_THD (DDPC_BASE+0x000)
#define DDPC_MIN_THD (DDPC_BASE+0x004)
#define DDPC_DIFF_THD1 (DDPC_BASE+0x008)
#define DDPC_DIFF_THD2 (DDPC_BASE+0x00C)
//NR_2D
#define NR_2D_BASE (ISP_BASE_ADDR+0x20000)
#define NR_2D_THDL_REG_CH1 (NR_2D_BASE + 0x000)
#define NR_2D_THDH_REG_CH1 (NR_2D_BASE + 0x004)
#define NR_2D_COEF_REG_CH1 (NR_2D_BASE + 0x008)
#define NR_2D_GMIN_REG_CH1 (NR_2D_BASE + 0x00C)
#define NR_2D_DELTA_THD_CH1 (NR_2D_BASE + 0x010)
#define NR_2D_G_COEF1_CH1 (NR_2D_BASE + 0x014)
#define NR_2D_G_COEF2_CH1 (NR_2D_BASE + 0x018)
#define NR_2D_G_COEF3_CH1 (NR_2D_BASE + 0x01C)
#define NR_2D_G_COEF4_CH1 (NR_2D_BASE + 0x020)
#define NR_2D_RB_COEF1_CH1 (NR_2D_BASE + 0x024)
#define NR_2D_RB_COEF2_CH1 (NR_2D_BASE + 0x028)
#define NR_2D_RB_COEF3_CH1 (NR_2D_BASE + 0x02C)
#define NR_2D_H_SEL_CH1 (NR_2D_BASE + 0x030)
#define NR_2D_FLT_EN_CH1 (NR_2D_BASE + 0x034)
#define NR_2D_THDL_REG_CH2 (NR_2D_BASE + 0x040)
#define NR_2D_THDH_REG_CH2 (NR_2D_BASE + 0x044)
#define NR_2D_COEF_REG_CH2 (NR_2D_BASE + 0x048)
#define NR_2D_GMIN_REG_CH2 (NR_2D_BASE + 0x04C)
#define NR_2D_DELTA_THD_CH2 (NR_2D_BASE + 0x050)
#define NR_2D_G_COEF1_CH2 (NR_2D_BASE + 0x054)
#define NR_2D_G_COEF2_CH2 (NR_2D_BASE + 0x058)
#define NR_2D_G_COEF3_CH2 (NR_2D_BASE + 0x05C)
#define NR_2D_G_COEF4_CH2 (NR_2D_BASE + 0x060)
#define NR_2D_RB_COEF1_CH2 (NR_2D_BASE + 0x064)
#define NR_2D_RB_COEF2_CH2 (NR_2D_BASE + 0x068)
#define NR_2D_RB_COEF3_CH2 (NR_2D_BASE + 0x06C)
#define NR_2D_H_SEL_CH2 (NR_2D_BASE + 0x070)
#define NR_2D_FLT_EN_CH2 (NR_2D_BASE + 0x074)
//AF
#define AF_BASE (ISP_BASE_ADDR+0x21000)
#define AF_WDW0_VBEGIN (AF_BASE + 0x000)
#define AF_WDW0_VEND (AF_BASE + 0x004)
#define AF_WDW0_HBEGIN (AF_BASE + 0x008)
#define AF_WDW0_HEND (AF_BASE + 0x00C)
#define AF_WDW0_HZ (AF_BASE + 0x094)
#if 1
//NR_3D
#define NR_3D_BASE_CH1 (ISP_BASE_ADDR+0x40000)
#define NR_3D_DENOSIE_CTL_CH1 (NR_3D_BASE_CH1 + 0x000)
#define NR_3D_RAMP_CH1 (NR_3D_BASE_CH1 + 0x004)
#define NR_3D_G1AMP_CH1 (NR_3D_BASE_CH1 + 0x008)
#define NR_3D_G2AMP_CH1 (NR_3D_BASE_CH1 + 0x00c)
#define NR_3D_BAMP_CH1 (NR_3D_BASE_CH1 + 0x010)
#define NR_3D_ERR_SFT_CH1 (NR_3D_BASE_CH1 + 0x014)
#define NR_3D_DIG_E1_CH1 (NR_3D_BASE_CH1 + 0x020)
#define NR_3D_DIG_E2_CH1 (NR_3D_BASE_CH1 + 0x024)
#define NR_3D_DIG_E3_CH1 (NR_3D_BASE_CH1 + 0x028)
#define NR_3D_DIG_E4_CH1 (NR_3D_BASE_CH1 + 0x02c)
#define NR_3D_YFLD_SPACE_CH1 (NR_3D_BASE_CH1 + 0x030)
#define NR_3D_BFLD_SPACE_CH1 (NR_3D_BASE_CH1 + 0x034)
#define NR_3D_DFT_YSADDR0_CH1 (NR_3D_BASE_CH1 + 0x038)
#define NR_3D_DFT_ESADDR0_CH1 (NR_3D_BASE_CH1 + 0x03C)
#define NR_3D_ERR_PAR_CH1 (NR_3D_BASE_CH1 + 0x040)
#define NR_3D_BAYER_PAR_CH1 (NR_3D_BASE_CH1 + 0x050)
#define NR_3D_DFT_BSADDR0_CH1 (NR_3D_BASE_CH1 + 0x0A0)
#define NR_3D_DFT_BSADDR1_CH1 (NR_3D_BASE_CH1 + 0x0A4)
#define NR_3D_DFT_BSADDR2_CH1 (NR_3D_BASE_CH1 + 0x0A8)
#define NR_3D_DFT_BSADDR3_CH1 (NR_3D_BASE_CH1 + 0x0AC)
#define NR_3D_DFT_BSADDR4_CH1 (NR_3D_BASE_CH1 + 0x0B0)
#define NR_3D_DFT_BSADDR5_CH1 (NR_3D_BASE_CH1 + 0x0B4)
#define NR_3D_DFT_BSADDR6_CH1 (NR_3D_BASE_CH1 + 0x0B8)
#define NR_3D_DFT_BSADDR7_CH1 (NR_3D_BASE_CH1 + 0x0BC)
#define NR_3D_DDR_BHNUM_CH1 (NR_3D_BASE_CH1 + 0x0C8)
#define NR_3D_DDR_YHNUM_CH1 (NR_3D_BASE_CH1 + 0x0CC)
#define NR_3D_DDR_EHNUM_CH1 (NR_3D_BASE_CH1 + 0x0D0)
#define NR_3D_ACTIVE_HNUM_CH1 (NR_3D_BASE_CH1 + 0x0D4)
#define NR_3D_ACTIVE_VNUM_CH1 (NR_3D_BASE_CH1 + 0x0D8)
#define NR_3D_WINERR_HBEGIN_CH1 (NR_3D_BASE_CH1 + 0x120)
#define NR_3D_WINERR_HEND_CH1 (NR_3D_BASE_CH1 + 0x124)
#define NR_3D_WINERR_VBEGIN_CH1 (NR_3D_BASE_CH1 + 0x128)
#define NR_3D_WINERR_VEND_CH1 (NR_3D_BASE_CH1 + 0x12C)
#define NR_3D_WINERR_RSHIFT_CH1 (NR_3D_BASE_CH1 + 0x140)
#define NR_3D_WINERR_LEVEL_CH1 (NR_3D_BASE_CH1 + 0x144)
#define NR_3D_CHANGE_POINT_CH1 (NR_3D_BASE_CH1 + 0x148)
#define NR_3D_FLT2D_PAR_CH1 (NR_3D_BASE_CH1 + 0x14C)
#define NR_3D_BASE_CH2 (ISP_BASE_ADDR+0x40200)
#define NR_3D_DENOSIE_CTL_CH2 (NR_3D_BASE_CH2 + 0x000)
#define NR_3D_RAMP_CH2 (NR_3D_BASE_CH2 + 0x004)
#define NR_3D_G1AMP_CH2 (NR_3D_BASE_CH2 + 0x008)
#define NR_3D_G2AMP_CH2 (NR_3D_BASE_CH2 + 0x00c)
#define NR_3D_BAMP_CH2 (NR_3D_BASE_CH2 + 0x010)
#define NR_3D_ERR_SFT_CH2 (NR_3D_BASE_CH2 + 0x014)
#define NR_3D_DIG_E1_CH2 (NR_3D_BASE_CH2 + 0x020)
#define NR_3D_DIG_E2_CH2 (NR_3D_BASE_CH2 + 0x024)
#define NR_3D_DIG_E3_CH2 (NR_3D_BASE_CH2 + 0x028)
#define NR_3D_DIG_E4_CH2 (NR_3D_BASE_CH2 + 0x02c)
#define NR_3D_YFLD_SPACE_CH2 (NR_3D_BASE_CH2 + 0x030)
#define NR_3D_BFLD_SPACE_CH2 (NR_3D_BASE_CH2 + 0x034)
#define NR_3D_DFT_YSADDR0_CH2 (NR_3D_BASE_CH2 + 0x038)
#define NR_3D_DFT_ESADDR0_CH2 (NR_3D_BASE_CH2 + 0x03C)
#define NR_3D_ERR_PAR_CH2 (NR_3D_BASE_CH2 + 0x040)
#define NR_3D_BAYER_PAR_CH2 (NR_3D_BASE_CH2 + 0x050)
#define NR_3D_DFT_BSADDR0_CH2 (NR_3D_BASE_CH2 + 0x0A0)
#define NR_3D_DFT_BSADDR1_CH2 (NR_3D_BASE_CH2 + 0x0A4)
#define NR_3D_DFT_BSADDR2_CH2 (NR_3D_BASE_CH2 + 0x0A8)
#define NR_3D_DFT_BSADDR3_CH2 (NR_3D_BASE_CH2 + 0x0AC)
#define NR_3D_DFT_BSADDR4_CH2 (NR_3D_BASE_CH2 + 0x0B0)
#define NR_3D_DFT_BSADDR5_CH2 (NR_3D_BASE_CH2 + 0x0B4)
#define NR_3D_DFT_BSADDR6_CH2 (NR_3D_BASE_CH2 + 0x0B8)
#define NR_3D_DFT_BSADDR7_CH2 (NR_3D_BASE_CH2 + 0x0BC)
#define NR_3D_DDR_BHNUM_CH2 (NR_3D_BASE_CH2 + 0x0C8)
#define NR_3D_DDR_YHNUM_CH2 (NR_3D_BASE_CH2 + 0x0CC)
#define NR_3D_DDR_EHNUM_CH2 (NR_3D_BASE_CH2 + 0x0D0)
#define NR_3D_ACTIVE_HNUM_CH2 (NR_3D_BASE_CH2 + 0x0D4)
#define NR_3D_ACTIVE_VNUM_CH2 (NR_3D_BASE_CH2 + 0x0D8)
#define NR_3D_WINERR_HBEGIN_CH2 (NR_3D_BASE_CH2 + 0x120)
#define NR_3D_WINERR_HEND_CH2 (NR_3D_BASE_CH2 + 0x124)
#define NR_3D_WINERR_VBEGIN_CH2 (NR_3D_BASE_CH2 + 0x128)
#define NR_3D_WINERR_VEND_CH2 (NR_3D_BASE_CH2 + 0x12C)
#define NR_3D_WINERR_RSHIFT_CH2 (NR_3D_BASE_CH2 + 0x140)
#define NR_3D_WINERR_LEVEL_CH2 (NR_3D_BASE_CH2 + 0x144)
#define NR_3D_CHANGE_POINT_CH2 (NR_3D_BASE_CH2 + 0x148)
#define NR_3D_FLT2D_PAR_CH2 (NR_3D_BASE_CH2 + 0x14C)
#else// This is XM510 code,just for test
//NR_3D
#define NR_3D_BASE 0x30040000
#define NR_3D_DENOSIE_CTL (NR_3D_BASE + 0x000)
#define NR_3D_ERR_SFT (NR_3D_BASE + 0x014)
#define NR_3D_NR_LEVEL (NR_3D_BASE + 0x018)
#define NR_3D_YFLD_SPACE (NR_3D_BASE + 0x030)
#define NR_3D_BFLD_SPACE (NR_3D_BASE + 0x034)
#define NR_3D_DFT_YSADDR0 (NR_3D_BASE + 0x038)
#define NR_3D_DFT_ESADDR0 (NR_3D_BASE + 0x03C)
#define NR_3D_DIG_E1 (NR_3D_BASE + 0x020)
#define NR_3D_DIG_E2 (NR_3D_BASE + 0x024)
#define NR_3D_DIG_E3 (NR_3D_BASE + 0x028)
#define NR_3D_ERR_PAR (NR_3D_BASE + 0x040)
#define NR_3D_BAYER_PAR (NR_3D_BASE + 0x050)
#define NR_3D_DDR_HNUM (NR_3D_BASE + 0x0D0)
#define NR_3D_ACTIVE_HNUM (NR_3D_BASE + 0x0D4)
#define NR_3D_YCTRL_ERR70 (NR_3D_BASE + 0x0D8)
#define NR_3D_YCTRL_ERRF8 (NR_3D_BASE + 0x0DC)
#define NR_3D_DFT_BSADDR0 (NR_3D_BASE + 0x0A0)
#define NR_3D_DFT_BSADDR1 (NR_3D_BASE + 0x0A4)
#define NR_3D_DFT_BSADDR2 (NR_3D_BASE + 0x0A8)
#define NR_3D_DFT_BSADDR3 (NR_3D_BASE + 0x0AC)
#define NR_3D_DFT_BSADDR4 (NR_3D_BASE + 0x0B0)
#define NR_3D_DFT_BSADDR5 (NR_3D_BASE + 0x0B4)
#define NR_3D_DFT_BSADDR6 (NR_3D_BASE + 0x0B8)
#define NR_3D_DFT_BSADDR7 (NR_3D_BASE + 0x0BC)
#define NR_3D_WINERR_HBEGIN (NR_3D_BASE + 0x120)
#define NR_3D_WINERR_HEND (NR_3D_BASE + 0x124)
#define NR_3D_WINERR_VBEGIN (NR_3D_BASE + 0x128)
#define NR_3D_WINERR_VEND (NR_3D_BASE + 0x12C)
#define NR_3D_WINERR_RSHIFT (NR_3D_BASE + 0x140)
#define NR_3D_WINERR_LEVEL (NR_3D_BASE + 0x144)
#define NR_3D_CHANGE_POINT (NR_3D_BASE + 0x148)
#define NR_3D_FLT2D_PAR (NR_3D_BASE + 0x14C)
#endif
// Demosaic
#define DEMOSAIC_BASE (ISP_BASE_ADDR+0x52000)
#define DEMOSAIC_G_HOFST (DEMOSAIC_BASE + 0x000)
#define DEMOSAIC_DHV_OFST (DEMOSAIC_BASE + 0x004)
#define DEMOSAIC_DHV_K (DEMOSAIC_BASE + 0x008)
// CSM
#define CSM_BASE (ISP_BASE_ADDR+0x60000)
#define CSM_RGB_MAX_CH1 (CSM_BASE+0x000)
#define CSM_RGB_MIN_CH1 (CSM_BASE+0x004)
#define CSM_R_OFST_REG_CH1 (CSM_BASE+0x040)
#define CSM_R1_COEF_REG_CH1 (CSM_BASE+0x044)
#define CSM_R2_COEF_REG_CH1 (CSM_BASE+0x048)
#define CSM_R3_COEF_REG_CH1 (CSM_BASE+0x04C)
#define CSM_G_OFST_REG_CH1 (CSM_BASE+0x050)
#define CSM_G1_COEF_REG_CH1 (CSM_BASE+0x054)
#define CSM_G2_COEF_REG_CH1 (CSM_BASE+0x058)
#define CSM_G3_COEF_REG_CH1 (CSM_BASE+0x05C)
#define CSM_B_OFST_REG_CH1 (CSM_BASE+0x060)
#define CSM_B1_COEF_REG_CH1 (CSM_BASE+0x064)
#define CSM_B2_COEF_REG_CH1 (CSM_BASE+0x068)
#define CSM_B3_COEF_REG_CH1 (CSM_BASE+0x06C)
#define CSM_RGB_MAX_CH2 (CSM_BASE+0x080)
#define CSM_RGB_MIN_CH2 (CSM_BASE+0x084)
#define CSM_R_OFST_REG_CH2 (CSM_BASE+0x0C0)
#define CSM_R1_COEF_REG_CH2 (CSM_BASE+0x0C4)
#define CSM_R2_COEF_REG_CH2 (CSM_BASE+0x0C8)
#define CSM_R3_COEF_REG_CH2 (CSM_BASE+0x0CC)
#define CSM_G_OFST_REG_CH2 (CSM_BASE+0x0D0)
#define CSM_G1_COEF_REG_CH2 (CSM_BASE+0x0D4)
#define CSM_G2_COEF_REG_CH2 (CSM_BASE+0x0D8)
#define CSM_G3_COEF_REG_CH2 (CSM_BASE+0x0DC)
#define CSM_B_OFST_REG_CH2 (CSM_BASE+0x0E0)
#define CSM_B1_COEF_REG_CH2 (CSM_BASE+0x0E4)
#define CSM_B2_COEF_REG_CH2 (CSM_BASE+0x0E8)
#define CSM_B3_COEF_REG_CH2 (CSM_BASE+0x0EC)
// Gamma96
#define GAMMA96_BASE (ISP_BASE_ADDR+0x61000)
#define GAMMA96_LINE0_DAT0 (GAMMA96_BASE+0x0)
// RGB2YC
#define RGB2YC_BASE (ISP_BASE_ADDR+0x62000)
// Demoire
#define DEMOIRE_BASE (ISP_BASE_ADDR+0x63000)
#define DEMOIRE_V_THD (DEMOIRE_BASE+0x000)
#define DEMOIRE_KV (DEMOIRE_BASE+0x004)
#define DEMOIRE_DF_THD_MAX (DEMOIRE_BASE+0x008)
#define DEMOIRE_DF_THD_MIN (DEMOIRE_BASE+0x00C)
#define DEMOIRE_GAIN_MIN (DEMOIRE_BASE+0x010)
#define DEMOIRE_KC (DEMOIRE_BASE+0x014)
#define DEMOIRE_BYPASS (DEMOIRE_BASE+0x018)
// CC
#define CC_BASE (ISP_BASE_ADDR+0x71000)
#define CC_EN_REG (CC_BASE+0x000)
#define CC_HUE_OFST (CC_BASE+0x018)
#define CC_HS_TRAN_DAT0 (CC_BASE+0x0E4)
#define CC_HH_H1_SATRT (CC_BASE+0x200)
#define CC_HH_H1_END (CC_BASE+0x204)
#define CC_HH_H1_MAX1 (CC_BASE+0x208)
#define CC_HH_H1_MAX2 (CC_BASE+0x20C)
#define CC_HH_H1_DMAX (CC_BASE+0x210)
#define CC_HH_H1_K1 (CC_BASE+0x214)
#define CC_HH_H1_K2 (CC_BASE+0x218)
#define CC_HH_H2_SATRT (CC_BASE+0x21C)
#define CC_HH_H2_END (CC_BASE+0x220)
#define CC_HH_H2_MAX1 (CC_BASE+0x224)
#define CC_HH_H2_MAX2 (CC_BASE+0x228)
#define CC_HH_H2_DMAX (CC_BASE+0x22C)
#define CC_HH_H2_K1 (CC_BASE+0x230)
#define CC_HH_H2_K2 (CC_BASE+0x234)
#define CC_HH_H3_SATRT (CC_BASE+0x240)
#define CC_HH_H3_END (CC_BASE+0x244)
#define CC_HH_H3_MAX1 (CC_BASE+0x248)
#define CC_HH_H3_MAX2 (CC_BASE+0x24C)
#define CC_HH_H3_DMAX (CC_BASE+0x250)
#define CC_HH_H3_K1 (CC_BASE+0x254)
#define CC_HH_H3_K2 (CC_BASE+0x258)
#define CC_HH_H4_SATRT (CC_BASE+0x25C)
#define CC_HH_H4_END (CC_BASE+0x260)
#define CC_HH_H4_MAX1 (CC_BASE+0x264)
#define CC_HH_H4_MAX2 (CC_BASE+0x268)
#define CC_HH_H4_DMAX (CC_BASE+0x26C)
#define CC_HH_H4_K1 (CC_BASE+0x270)
#define CC_HH_H4_K2 (CC_BASE+0x274)
#define CC_HH_H5_SATRT (CC_BASE+0x280)
#define CC_HH_H5_END (CC_BASE+0x284)
#define CC_HH_H5_MAX1 (CC_BASE+0x288)
#define CC_HH_H5_MAX2 (CC_BASE+0x28C)
#define CC_HH_H5_DMAX (CC_BASE+0x290)
#define CC_HH_H5_K1 (CC_BASE+0x294)
#define CC_HH_H5_K2 (CC_BASE+0x298)
#define CC_HH_H6_SATRT (CC_BASE+0x29C)
#define CC_HH_H6_END (CC_BASE+0x2A0)
#define CC_HH_H6_MAX1 (CC_BASE+0x2A4)
#define CC_HH_H6_MAX2 (CC_BASE+0x2A8)
#define CC_HH_H6_DMAX (CC_BASE+0x2AC)
#define CC_HH_H6_K1 (CC_BASE+0x2B0)
#define CC_HH_H6_K2 (CC_BASE+0x2B4)
// Y_Gamma
#define YGAMMA_BASE (ISP_BASE_ADDR+0x72000)
#define YGAMMA_BUF_SW (YGAMMA_BASE+0x000)
#define YGAMMA_BUF_SW_STATE (YGAMMA_BASE+0x004)
#define YGAMMA_LINE0_DAT0 (YGAMMA_BASE+0x040)
#define YGAMMA_LINE1_DAT0 (YGAMMA_BASE+0x180)
//Y_hist
#define YHIST_BASE (ISP_BASE_ADDR+0x73000)
#define YHIST_CNT0 (YHIST_BASE+0x000)
//C_tran
#define CTRAN_BASE (ISP_BASE_ADDR+0x74000)
#define CTRAN_BUF_SW (CTRAN_BASE+0x000)
#define CTRAN_BUF_SW_STATE (CTRAN_BASE+0x004)
#define TRAN_LINE0_DAT0 (CTRAN_BASE+0x040)
#define TRAN_LINE1_DAT0 (CTRAN_BASE+0x080)
// Sharpness
#define SHARPEN_BASE (ISP_BASE_ADDR+0x75000)
#define SHARPEN_YMTH1 (SHARPEN_BASE+0x000)
#define SHARPEN_YMTH2 (SHARPEN_BASE+0x004)
#define SHARPEN_YM_K (SHARPEN_BASE+0x008)
#define SHARPEN_KM0 (SHARPEN_BASE+0x00C)
#define SHARPEN_WM0 (SHARPEN_BASE+0x010)
#define SHARPEN_WM1 (SHARPEN_BASE+0x014)
#define SHARPEN_WM2 (SHARPEN_BASE+0x018)
#define SHARPEN_WM3 (SHARPEN_BASE+0x01C)
#define SHARPEN_WM4 (SHARPEN_BASE+0x020)
#define SHARPEN_WM5 (SHARPEN_BASE+0x024)
#define SHARPEN_YMDTH1 (SHARPEN_BASE+0x040)
#define SHARPEN_YMDTH2 (SHARPEN_BASE+0x044)
#define SHARPEN_YMD_K (SHARPEN_BASE+0x048)
#define SHARPEN_KMD_MAX (SHARPEN_BASE+0x04C)
#define SHARPEN_WMD0 (SHARPEN_BASE+0x050)
#define SHARPEN_WMD1 (SHARPEN_BASE+0x054)
#define SHARPEN_WMD2 (SHARPEN_BASE+0x058)
#define SHARPEN_WMD3 (SHARPEN_BASE+0x05C)
#define SHARPEN_WMD4 (SHARPEN_BASE+0x060)
#define SHARPEN_WMD5 (SHARPEN_BASE+0x064)
#define SHARPEN_YHTH1 (SHARPEN_BASE+0x080)
#define SHARPEN_YHTH2 (SHARPEN_BASE+0x084)
#define SHARPEN_YH_K (SHARPEN_BASE+0x088)
#define SHARPEN_KH0 (SHARPEN_BASE+0x08C)
#define SHARPEN_WH0 (SHARPEN_BASE+0x090)
#define SHARPEN_WH1 (SHARPEN_BASE+0x094)
#define SHARPEN_WH2 (SHARPEN_BASE+0x098)
#define SHARPEN_WH3 (SHARPEN_BASE+0x09C)
#define SHARPEN_WH4 (SHARPEN_BASE+0x0A0)
#define SHARPEN_WH5 (SHARPEN_BASE+0x0A4)
#define SHARPEN_YHDTH1 (SHARPEN_BASE+0x0C0)
#define SHARPEN_YHDTH2 (SHARPEN_BASE+0x0C4)
#define SHARPEN_YHD_K (SHARPEN_BASE+0x0C8)
#define SHARPEN_KHD_MAX (SHARPEN_BASE+0x0CC)
#define SHARPEN_WHD0 (SHARPEN_BASE+0x0D0)
#define SHARPEN_WHD1 (SHARPEN_BASE+0x0D4)
#define SHARPEN_WHD2 (SHARPEN_BASE+0x0D8)
#define SHARPEN_WHD3 (SHARPEN_BASE+0x0DC)
#define SHARPEN_WHD4 (SHARPEN_BASE+0x0E0)
#define SHARPEN_WHD5 (SHARPEN_BASE+0x0E4)
#define SHARPEN_KH00 (SHARPEN_BASE+0x100)
#define SHARPEN_KH01 (SHARPEN_BASE+0x104)
#define SHARPEN_KL00 (SHARPEN_BASE+0x108)
#define SHARPEN_KL01 (SHARPEN_BASE+0x10C)
#define SHARPEN_KH1 (SHARPEN_BASE+0x110)
#define SHARPEN_KL1 (SHARPEN_BASE+0x114)
#define SHARPEN_DLTMAX (SHARPEN_BASE+0x118)
#define SHARPEN_DFKD (SHARPEN_BASE+0x11C)
#define SHARPEN_DFMAX (SHARPEN_BASE+0x120)
#define SHARPEN_ENH_STREN (SHARPEN_BASE+0x130)
#define SHARPEN_ENH_THR (SHARPEN_BASE+0x134)
#define SHARPEN_ENH_GMAX (SHARPEN_BASE+0x138)
#define SHARPEN_TRAN_DAT0 (SHARPEN_BASE+0x140)
#define SHARPEN_C_KR1 (SHARPEN_BASE+0x1C0)
#define SHARPEN_C_KR2 (SHARPEN_BASE+0x1C4)
#define SHARPEN_C_KG1 (SHARPEN_BASE+0x1C8)
#define SHARPEN_C_KG2 (SHARPEN_BASE+0x1CC)
#define SHARPEN_C_KB1 (SHARPEN_BASE+0x1D0)
#define SHARPEN_C_KB2 (SHARPEN_BASE+0x1D4)
#define SHARPEN_C_ZONE_EN (SHARPEN_BASE+0x1D8)
#define SHARPEN_C_COEF1 (SHARPEN_BASE+0x1DC)
#define SHARPEN_C_COEF2 (SHARPEN_BASE+0x1E0)
#define SHARPEN_C_COEF3 (SHARPEN_BASE+0x1E4)
#define SHARPEN_C_FLT_SEL (SHARPEN_BASE+0x1E8)
#define SHARPEN_C_SAT_DAT0 (SHARPEN_BASE+0x200)
// sharpen_ch2
#define SHARPEN_YMTH1_CH2 (SHARPEN_BASE+0x280)
#define SHARPEN_YMTH2_CH2 (SHARPEN_BASE+0x284)
#define SHARPEN_YM_K_CH2 (SHARPEN_BASE+0x288)
#define SHARPEN_KM0_CH2 (SHARPEN_BASE+0x28C)
#define SHARPEN_YMDTH1_CH2 (SHARPEN_BASE+0x290)
#define SHARPEN_YMDTH2_CH2 (SHARPEN_BASE+0x294)
#define SHARPEN_YMD_K_CH2 (SHARPEN_BASE+0x298)
#define SHARPEN_KMDMAX_CH2 (SHARPEN_BASE+0x29C)
#define SHARPEN_YHTH1_CH2 (SHARPEN_BASE+0x2a0)
#define SHARPEN_YHTH2_CH2 (SHARPEN_BASE+0x2a4)
#define SHARPEN_YH_K_CH2 (SHARPEN_BASE+0x2a8)
#define SHARPEN_KH0_CH2 (SHARPEN_BASE+0x2aC)
#define SHARPEN_YHDTH1_CH2 (SHARPEN_BASE+0x2b0)
#define SHARPEN_YHDTH2_CH2 (SHARPEN_BASE+0x2b4)
#define SHARPEN_YHD_K_CH2 (SHARPEN_BASE+0x2b8)
#define SHARPEN_KHDMAX_CH2 (SHARPEN_BASE+0x2bC)
#define SHARPEN_DFKD_CH2 (SHARPEN_BASE+0x2c0)
#define SHARPEN_DFMAX_CH2 (SHARPEN_BASE+0x2c4)
#define SHARPEN_EN_CH1 (SHARPEN_BASE+0x240)
#define SHARPEN_EN_CH2 (SHARPEN_BASE+0x244)
#define DENOISE_EN_CH1 (SHARPEN_BASE+0x248)
#define DENOISE_EN_CH2 (SHARPEN_BASE+0x24C)
#define NOISETHR_CH1 (SHARPEN_BASE+0x250)
#define NOISETHR_CH2 (SHARPEN_BASE+0x254)
// YC_Gain
#define YC_GAIN_BASE 0x30076000
#define Y_GAIN (YC_GAIN_BASE+(0x000))
#define CB_GAIN (YC_GAIN_BASE+(0x004))
#define CR_GAIN (YC_GAIN_BASE+(0x008))
#define Y_OFST (YC_GAIN_BASE+(0x00C))
#define Y_MAX_THD (YC_GAIN_BASE+(0x010))
#define Y_MIN_THD (YC_GAIN_BASE+(0x014))
//PLL use to upscaler
#define PLL_BASE 0x20000000
#define PLL_SYSCTRLREG_LOCK (PLL_BASE+0x002C)
#define PLLB1_CTRL (PLL_BASE+0x000C)
#define PLLB2_CTRL (PLL_BASE+0x0010)
#define PLLB_CTRL (PLL_BASE+0x0014)
#endif

163
general/package/xiongmai-osdrv-xm530/files/include/xm_comm_adec.h
View File

@ -1,163 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2025, XM Tech. Co., Ltd.
******************************************************************************
File Name : xm_comm_adec.h
Version : Initial Draft
Author : XM multimedia software group
Created : 2015/9/17
Last Modified :
Description :
******************************************************************************/
#ifndef __XM_COMM_ADEC_H__
#define __XM_COMM_ADEC_H__
#include "xm_type.h"
#include "xm_common.h"
#include "xm_comm_aio.h"
#ifdef __cplusplus
#if __cplusplus
extern "C"{
#endif
#endif /* End of #ifdef __cplusplus */
typedef struct xmADEC_ATTR_G711_S
{
XM_U32 resv;
}ADEC_ATTR_G711_S;
typedef struct xmADEC_ATTR_G726_S
{
G726_BPS_E enG726bps;
}ADEC_ATTR_G726_S;
typedef struct xmADEC_ATTR_ADPCM_S
{
ADPCM_TYPE_E enADPCMType;
}ADEC_ATTR_ADPCM_S;
typedef struct xmADEC_ATTR_LPCM_S
{
XM_U32 resv;
}ADEC_ATTR_LPCM_S;
typedef enum xmADEC_MODE_E
{
ADEC_MODE_PACK = 0,/*require input is valid dec pack(a
complete frame encode result),
e.g.the stream get from AENC is a
valid dec pack, the stream know actually
pack len from file is also a dec pack.
this mode is high-performative*/
ADEC_MODE_STREAM ,/*input is stream,low-performative,
if you couldn't find out whether a stream is
vaild dec pack,you could use
this mode*/
ADEC_MODE_BUTT
}ADEC_MODE_E;
typedef struct xmADEC_CH_ATTR_S
{
PAYLOAD_TYPE_E enType;
XM_U32 u32BufSize; /*buf size[2~MAX_AUDIO_FRAME_NUM]*/
ADEC_MODE_E enMode; /*decode mode*/
XM_VOID *pValue;
}ADEC_CHN_ATTR_S;
typedef struct xmADEC_DECODER_S
{
PAYLOAD_TYPE_E enType;
XM_CHAR aszName[16];
XM_S32 (*pfnOpenDecoder)(XM_VOID *pDecoderAttr, XM_VOID **ppDecoder); /*struct ppDecoder is packed by user,user malloc and free memory for this struct */
XM_S32 (*pfnDecodeFrm)(XM_VOID *pDecoder, XM_U8 **pu8Inbuf,XM_S32 *ps32LeftByte,
XM_U16 *pu16Outbuf,XM_U32 *pu32OutLen,XM_U32 *pu32Chns);
XM_S32 (*pfnGetFrmInfo)(XM_VOID *pDecoder, XM_VOID *pInfo);
XM_S32 (*pfnCloseDecoder)(XM_VOID *pDecoder);
} ADEC_DECODER_S;
typedef enum xmEN_ADEC_ERR_CODE_E
{
ADEC_ERR_DECODER_ERR = 64,
ADEC_ERR_BUF_LACK,
ADEC_ERR_VOICE_DEC_TYPE,
ADEC_ERR_VOICE_DEC_FRAMESIZE,
ADEC_ERR_VOICE_DEC_FRAMETYPE,
ADEC_ERR_VOICE_INVALID_DEVICE,
ADEC_ERR_VOICE_INVALID_INBUF,
ADEC_ERR_VOICE_INVALID_OUTBUF,
ADEC_ERR_VOICE_TRANS_DEVICE,
ADEC_ERR_VOICE_TRANS_TYPE,
} EN_ADEC_ERR_CODE_E;
typedef enum xm_ADEC_OUTPUT_MODE_E
{
ADEC_OUTPUT_MODE_BIND = 0,
ADEC_OUTPUT_MODE_MANUAL,
ADEC_OUTPUT_MODE_BUTTL
} ADEC_OUTPUT_MODE_E;
#define XM_TRACE_ADEC(level, fmt...) XM_TRACE(level, XM_ID_ADEC,##fmt)
/* invlalid device ID */
#define XM_ERR_ADEC_INVALID_DEVID XM_DEF_ERR(XM_ID_ADEC, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_DEVID)
/* invlalid channel ID */
#define XM_ERR_ADEC_INVALID_CHNID XM_DEF_ERR(XM_ID_ADEC, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_CHNID)
/* at lease one parameter is illagal ,eg, an illegal enumeration value */
#define XM_ERR_ADEC_ILLEGAL_PARAM XM_DEF_ERR(XM_ID_ADEC, EN_ERR_LEVEL_ERROR, EN_ERR_ILLEGAL_PARAM)
/* channel exists */
#define XM_ERR_ADEC_EXIST XM_DEF_ERR(XM_ID_ADEC, EN_ERR_LEVEL_ERROR, EN_ERR_EXIST)
/* channel unexists */
#define XM_ERR_ADEC_UNEXIST XM_DEF_ERR(XM_ID_ADEC, EN_ERR_LEVEL_ERROR, EN_ERR_UNEXIST)
/* using a NULL point */
#define XM_ERR_ADEC_NULL_PTR XM_DEF_ERR(XM_ID_ADEC, EN_ERR_LEVEL_ERROR, EN_ERR_NULL_PTR)
/* try to enable or initialize system,device or channel, before configing attribute */
#define XM_ERR_ADEC_NOT_CONFIG XM_DEF_ERR(XM_ID_ADEC, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_CONFIG)
/* operation is not supported by NOW */
#define XM_ERR_ADEC_NOT_SUPPORT XM_DEF_ERR(XM_ID_ADEC, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_SUPPORT)
/* operation is not permitted ,eg, try to change stati attribute */
#define XM_ERR_ADEC_NOT_PERM XM_DEF_ERR(XM_ID_ADEC, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_PERM)
/* failure caused by malloc memory */
#define XM_ERR_ADEC_NOMEM XM_DEF_ERR(XM_ID_ADEC, EN_ERR_LEVEL_ERROR, EN_ERR_NOMEM)
/* failure caused by malloc buffer */
#define XM_ERR_ADEC_NOBUF XM_DEF_ERR(XM_ID_ADEC, EN_ERR_LEVEL_ERROR, EN_ERR_NOBUF)
/* no data in buffer */
#define XM_ERR_ADEC_BUF_EMPTY XM_DEF_ERR(XM_ID_ADEC, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_EMPTY)
/* no buffer for new data */
#define XM_ERR_ADEC_BUF_FULL XM_DEF_ERR(XM_ID_ADEC, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_FULL)
/* system is not ready,had not initialed or loaded*/
#define XM_ERR_ADEC_SYS_NOTREADY XM_DEF_ERR(XM_ID_ADEC, EN_ERR_LEVEL_ERROR, EN_ERR_SYS_NOTREADY)
/* decoder internal err */
#define XM_ERR_ADEC_DECODER_ERR XM_DEF_ERR(XM_ID_ADEC, EN_ERR_LEVEL_ERROR, ADEC_ERR_DECODER_ERR)
/* input buffer not enough to decode one frame */
#define XM_ERR_ADEC_BUF_LACK XM_DEF_ERR(XM_ID_ADEC, EN_ERR_LEVEL_ERROR, ADEC_ERR_BUF_LACK)
#define XM_ERR_ADEC_DEC_TYPE XM_DEF_ERR(XM_ID_ADEC, EN_ERR_LEVEL_ERROR, ADEC_ERR_VOICE_DEC_TYPE)
#define XM_ERR_ADEC_DEC_FRAMESIZE XM_DEF_ERR(XM_ID_ADEC, EN_ERR_LEVEL_ERROR, ADEC_ERR_VOICE_DEC_FRAMESIZE)
#define XM_ERR_ADEC_DEC_FRAMETYPE XM_DEF_ERR(XM_ID_ADEC, EN_ERR_LEVEL_ERROR, ADEC_ERR_VOICE_DEC_FRAMETYPE)
#define XM_ERR_ADEC_INVALID_DEVICE XM_DEF_ERR(XM_ID_ADEC, EN_ERR_LEVEL_ERROR, ADEC_ERR_VOICE_INVALID_DEVICE)
#define XM_ERR_ADEC_INVALID_INBUF XM_DEF_ERR(XM_ID_ADEC, EN_ERR_LEVEL_ERROR, ADEC_ERR_VOICE_INVALID_INBUF)
#define XM_ERR_ADEC_INVALID_OUTBUF XM_DEF_ERR(XM_ID_ADEC, EN_ERR_LEVEL_ERROR, ADEC_ERR_VOICE_INVALID_OUTBUF)
#define XM_ERR_ADEC_TRANS_DEVICE XM_DEF_ERR(XM_ID_ADEC, EN_ERR_LEVEL_ERROR, ADEC_ERR_VOICE_TRANS_DEVICE)
#define XM_ERR_ADEC_TRANS_TYPE XM_DEF_ERR(XM_ID_ADEC, EN_ERR_LEVEL_ERROR, ADEC_ERR_VOICE_TRANS_TYPE)
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif/* End of #ifndef __XM_COMM_ADEC_H__*/

114
general/package/xiongmai-osdrv-xm530/files/include/xm_comm_aenc.h
View File

@ -1,114 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2025, XM Tech. Co., Ltd.
******************************************************************************
File Name : xm_comm_aenc.h
Version : Initial Draft
Author : XM multimedia software group
Created : 2015/9/17
Description :
******************************************************************************/
#ifndef __XM_COMM_AENC_H__
#define __XM_COMM_AENC_H__
#include "xm_type.h"
#include "xm_common.h"
#include "xm_comm_aio.h"
#ifdef __cplusplus
#if __cplusplus
extern "C"{
#endif
#endif /* End of #ifdef __cplusplus */
typedef struct xmAENC_ATTR_G711_S
{
XM_U32 resv; /*reserve item*/
}AENC_ATTR_G711_S;
typedef struct xmAENC_ATTR_G726_S
{
G726_BPS_E enG726bps;
}AENC_ATTR_G726_S;
typedef struct xmAENC_ATTR_ADPCM_S
{
ADPCM_TYPE_E enADPCMType;
}AENC_ATTR_ADPCM_S;
typedef struct xmAENC_ATTR_LPCM_S
{
XM_U32 resv; /*reserve item*/
}AENC_ATTR_LPCM_S;
typedef struct xmAENC_ENCODER_S
{
PAYLOAD_TYPE_E enType;
XM_U32 u32MaxFrmLen;
XM_CHAR aszName[16]; /* encoder type,be used to print proc information */
XM_S32 (*pfnOpenEncoder)(XM_VOID *pEncoderAttr, XM_VOID **ppEncoder); /* pEncoder is the handle to control the encoder */
XM_S32 (*pfnEncodeFrm)(XM_VOID *pEncoder, const AUDIO_FRAME_S *pstData,
XM_U8 *pu8Outbuf,XM_U32 *pu32OutLen);
XM_S32 (*pfnCloseEncoder)(XM_VOID *pEncoder);
} AENC_ENCODER_S;
typedef struct xmAENC_CHN_ATTR_S
{
PAYLOAD_TYPE_E enType; /*payload type ()*/
XM_U32 u32BufSize; /*buf size [2~MAX_AUDIO_FRAME_NUM]*/
XM_VOID *pValue; /*point to attribute of definite audio encoder*/
}AENC_CHN_ATTR_S;
typedef enum xmEN_AENC_ERR_CODE_E
{
ADEC_ERR_ENCODER_ERR = 64 ,
} EN_AENC_ERR_CODE_E;
#define XM_TRACE_AENC(level, fmt...) XM_TRACE(level, XM_ID_AENC,##fmt)
/* invlalid device ID */
#define XM_ERR_AENC_INVALID_DEVID XM_DEF_ERR(XM_ID_AENC, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_DEVID)
/* invlalid channel ID */
#define XM_ERR_AENC_INVALID_CHNID XM_DEF_ERR(XM_ID_AENC, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_CHNID)
/* at lease one parameter is illagal ,eg, an illegal enumeration value */
#define XM_ERR_AENC_ILLEGAL_PARAM XM_DEF_ERR(XM_ID_AENC, EN_ERR_LEVEL_ERROR, EN_ERR_ILLEGAL_PARAM)
/* channel exists */
#define XM_ERR_AENC_EXIST XM_DEF_ERR(XM_ID_AENC, EN_ERR_LEVEL_ERROR, EN_ERR_EXIST)
/* channel unexists */
#define XM_ERR_AENC_UNEXIST XM_DEF_ERR(XM_ID_AENC, EN_ERR_LEVEL_ERROR, EN_ERR_UNEXIST)
/* using a NULL point */
#define XM_ERR_AENC_NULL_PTR XM_DEF_ERR(XM_ID_AENC, EN_ERR_LEVEL_ERROR, EN_ERR_NULL_PTR)
/* try to enable or initialize system,device or channel, before configing attribute */
#define XM_ERR_AENC_NOT_CONFIG XM_DEF_ERR(XM_ID_AENC, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_CONFIG)
/* operation is not supported by NOW */
#define XM_ERR_AENC_NOT_SUPPORT XM_DEF_ERR(XM_ID_AENC, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_SUPPORT)
/* operation is not permitted ,eg, try to change static attribute */
#define XM_ERR_AENC_NOT_PERM XM_DEF_ERR(XM_ID_AENC, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_PERM)
/* failure caused by malloc memory */
#define XM_ERR_AENC_NOMEM XM_DEF_ERR(XM_ID_AENC, EN_ERR_LEVEL_ERROR, EN_ERR_NOMEM)
/* failure caused by malloc buffer */
#define XM_ERR_AENC_NOBUF XM_DEF_ERR(XM_ID_AENC, EN_ERR_LEVEL_ERROR, EN_ERR_NOBUF)
/* no data in buffer */
#define XM_ERR_AENC_BUF_EMPTY XM_DEF_ERR(XM_ID_AENC, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_EMPTY)
/* no buffer for new data */
#define XM_ERR_AENC_BUF_FULL XM_DEF_ERR(XM_ID_AENC, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_FULL)
/* system is not ready,had not initialed or loaded*/
#define XM_ERR_AENC_SYS_NOTREADY XM_DEF_ERR(XM_ID_AENC, EN_ERR_LEVEL_ERROR, EN_ERR_SYS_NOTREADY)
/* encoder internal err */
#define XM_ERR_AENC_ENCODER_ERR XM_DEF_ERR(XM_ID_AENC, EN_ERR_LEVEL_ERROR, ADEC_ERR_ENCODER_ERR)
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif/* End of #ifndef __XM_COMM_AENC_H__*/

390
general/package/xiongmai-osdrv-xm530/files/include/xm_comm_aio.h
View File

@ -1,390 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2025, XM Tech. Co., Ltd.
******************************************************************************
File Name : xm_comm_aio.h
Version : Initial Draft
Author : XM multimedia software group
Created : 2015/9/17
Description :
******************************************************************************/
#ifndef __XM_COMM_AIO_H__
#define __XM_COMM_AIO_H__
#include "xm_common.h"
#include "xm_errno.h"
#ifdef __cplusplus
#if __cplusplus
extern "C"{
#endif
#endif /* End of #ifdef __cplusplus */
#define MAX_AUDIO_FRAME_NUM 50 /*max count of audio frame in Buffer */
#define MAX_AUDIO_POINT_BYTES 4 /*max bytes of one sample point(now 32bit max)*/
#define MAX_VOICE_POINT_NUM 480 /*max sample per frame for voice encode */
#define MAX_AUDIO_POINT_NUM 2048 /*max sample per frame for all encoder(aacplus:2048)*/
#define MAX_AO_POINT_NUM 4096 /*31/21 AO support 4096 framelen*/
#define MIN_AUDIO_POINT_NUM 80 /*min sample per frame*/
/*max length of audio frame by bytes, one frame contain many sample point */
#define MAX_AUDIO_FRAME_LEN (MAX_AUDIO_POINT_BYTES*MAX_AO_POINT_NUM)
/*max length of audio stream by bytes */
#define MAX_AUDIO_STREAM_LEN MAX_AUDIO_FRAME_LEN
#define MAX_AI_USRFRM_DEPTH 30 /*max depth of user frame buf */
typedef enum xmAUDIO_SAMPLE_RATE_E
{
AUDIO_SAMPLE_RATE_8000 = 8000, /* 8K samplerate*/
AUDIO_SAMPLE_RATE_12000 = 12000, /* 12K samplerate*/
AUDIO_SAMPLE_RATE_11025 = 11025, /* 11.025K samplerate*/
AUDIO_SAMPLE_RATE_16000 = 16000, /* 16K samplerate*/
AUDIO_SAMPLE_RATE_22050 = 22050, /* 22.050K samplerate*/
AUDIO_SAMPLE_RATE_24000 = 24000, /* 24K samplerate*/
AUDIO_SAMPLE_RATE_32000 = 32000, /* 32K samplerate*/
AUDIO_SAMPLE_RATE_44100 = 44100, /* 44.1K samplerate*/
AUDIO_SAMPLE_RATE_48000 = 48000, /* 48K samplerate*/
AUDIO_SAMPLE_RATE_BUTT,
} AUDIO_SAMPLE_RATE_E;
typedef enum xmAUDIO_BIT_WIDTH_E
{
AUDIO_BIT_WIDTH_8 = 0, /* 8bit width */
AUDIO_BIT_WIDTH_16 = 1, /* 16bit width*/
AUDIO_BIT_WIDTH_32 = 2, /* 32bit width*/
AUDIO_BIT_WIDTH_BUTT,
} AUDIO_BIT_WIDTH_E;
typedef enum xmAIO_MODE_E
{
AIO_MODE_I2S_MASTER = 0, /* SIO I2S master mode */
AIO_MODE_I2S_SLAVE, /* SIO I2S slave mode */
AIO_MODE_PCM_SLAVE_STD, /* SIO PCM slave standard mode */
AIO_MODE_PCM_SLAVE_NSTD, /* SIO PCM slave non-standard mode */
AIO_MODE_PCM_MASTER_STD, /* SIO PCM master standard mode */
AIO_MODE_PCM_MASTER_NSTD, /* SIO PCM master non-standard mode */
AIO_MODE_BUTT
} AIO_MODE_E;
typedef enum xmAIO_SOUND_MODE_E
{
AUDIO_SOUND_MODE_MONO =0,/*mono*/
AUDIO_SOUND_MODE_STEREO =1,/*stereo*/
AUDIO_SOUND_MODE_BUTT
} AUDIO_SOUND_MODE_E;
/*
An example of the packing scheme for G726-32 codewords is as shown, and bit A3 is the least significant bit of the first codeword:
RTP G726-32:
0 1
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-
|B B B B|A A A A|D D D D|C C C C| ...
|0 1 2 3|0 1 2 3|0 1 2 3|0 1 2 3|
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-
MEDIA G726-32:
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-
|A A A A|B B B B|C C C C|D D D D| ...
|3 2 1 0|3 2 1 0|3 2 1 0|3 2 1 0|
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-
*/
typedef enum xmG726_BPS_E
{
G726_16K = 0, /* G726 16kbps, see RFC3551.txt 4.5.4 G726-16 */
G726_24K, /* G726 24kbps, see RFC3551.txt 4.5.4 G726-24 */
G726_32K, /* G726 32kbps, see RFC3551.txt 4.5.4 G726-32 */
G726_40K, /* G726 40kbps, see RFC3551.txt 4.5.4 G726-40 */
MEDIA_G726_16K, /* G726 16kbps for ASF ... */
MEDIA_G726_24K, /* G726 24kbps for ASF ... */
MEDIA_G726_32K, /* G726 32kbps for ASF ... */
MEDIA_G726_40K, /* G726 40kbps for ASF ... */
G726_BUTT,
} G726_BPS_E;
typedef enum xmADPCM_TYPE_E
{
/* see DVI4 diiffers in three respects from the IMA ADPCM at RFC3551.txt 4.5.1 DVI4 */
ADPCM_TYPE_DVI4 = 0, /* 32kbps ADPCM(DVI4) for RTP */
ADPCM_TYPE_IMA, /* 32kbps ADPCM(IMA),NOTICE:point num must be 161/241/321/481 */
ADPCM_TYPE_ORG_DVI4,
ADPCM_TYPE_BUTT,
} ADPCM_TYPE_E;
#define AI_EXPAND 0x01
typedef struct xmAIO_ATTR_S
{
AUDIO_SAMPLE_RATE_E enSamplerate; /* sample rate*/
AUDIO_BIT_WIDTH_E enBitwidth; /* bitwidth*/
AIO_MODE_E enWorkmode; /* master or slave mode*/
AUDIO_SOUND_MODE_E enSoundmode; /* momo or steror*/
XM_U32 u32EXFlag; /* expand 8bit to 16bit,use AI_EXPAND(only valid for AI 8bit) */
XM_U32 u32FrmNum; /* frame num in buf[2,MAX_AUDIO_FRAME_NUM]*/
XM_U32 u32PtNumPerFrm; /* point num per frame (80/160/240/320/480/1024/2048)
(ADPCM IMA should add 1 point, AMR only support 160)*/
XM_U32 u32ChnCnt; /* channle number on FS, valid value:2/4/8/16 */
XM_U32 u32ClkSel; /* clock select, meaning is diffrent when master and slave mode,
if sio slave mode:
0: AD and DA clock of codec is separate
1: AD and DA clock of codec is inseparate
else sio master mode:
0:ACKOUT clock is from sio 0
1:ACKOUT clock is from sio 1/2
*/
} AIO_ATTR_S;
typedef struct xmAI_CHN_PARAM_S
{
XM_U32 u32UsrFrmDepth;
XM_S32 s32Rev;
} AI_CHN_PARAM_S;
typedef struct xmAUDIO_FRAME_S
{
AUDIO_BIT_WIDTH_E enBitwidth; /*audio frame bitwidth*/
AUDIO_SOUND_MODE_E enSoundmode; /*audio frame momo or stereo mode*/
XM_VOID *pVirAddr[2];
XM_U32 u32PhyAddr[2];
XM_U64 u64TimeStamp; /*audio frame timestamp*/
XM_U32 u32Seq; /*audio frame seq*/
XM_U32 u32Len; /*data lenth per channel in frame*/
XM_U32 u32PoolId[2];
} AUDIO_FRAME_S;
typedef struct xmAEC_FRAME_S
{
AUDIO_FRAME_S stRefFrame; /* AEC reference audio frame */
XM_BOOL bValid; /* whether frame is valid */
XM_BOOL bSysBind; /* whether is sysbind */
} AEC_FRAME_S;
typedef struct xmAUDIO_FRAME_COMBINE_S
{
AUDIO_FRAME_S stFrm; /* audio frame */
AEC_FRAME_S stRefFrm; /* AEC reference audio frame */
} AUDIO_FRAME_COMBINE_S;
typedef struct xmAUDIO_FRAME_INFO_S
{
AUDIO_FRAME_S *pstFrame;/*frame ptr*/
XM_U32 u32Id; /*frame id*/
} AUDIO_FRAME_INFO_S;
typedef struct xmAUDIO_STREAM_S
{
XM_U8 *pStream; /* the virtual address of stream */
XM_U32 u32PhyAddr; /* the physics address of stream */
XM_U32 u32Len; /* stream lenth, by bytes */
XM_U64 u64TimeStamp; /* frame time stamp*/
XM_U32 u32Seq; /* frame seq,if stream is not a valid frame,u32Seq is 0*/
} AUDIO_STREAM_S;
typedef enum xmAUDIO_RESAMPLE_TYPE_E
{
AUDIO_RESAMPLE_1X2 = 0x1,
AUDIO_RESAMPLE_2X1 = 0x2,
AUDIO_RESAMPLE_1X4 = 0x3,
AUDIO_RESAMPLE_4X1 = 0x4,
AUDIO_RESAMPLE_1X6 = 0x5,
AUDIO_RESAMPLE_6X1 = 0x6,
AUDIO_RESAMPLE_BUTT
} AUDIO_RESAMPLE_TYPE_E;
typedef struct xmAUDIO_RESAMPLE_ATTR_S
{
XM_U32 u32InPointNum; /* input point number of frame */
AUDIO_SAMPLE_RATE_E enInSampleRate; /* input sample rate */
AUDIO_RESAMPLE_TYPE_E enReSampleType; /* resample type */
} AUDIO_RESAMPLE_ATTR_S;
typedef struct xmAUDIO_RESAMPLE_ATTR_EX_S
{
XM_U32 u32InPointNum; /* input point number of frame */
AUDIO_SAMPLE_RATE_E enInSampleRate; /* input sample rate */
AUDIO_SAMPLE_RATE_E enOutSampleRate; /* output sample rate */
} AUDIO_RESAMPLE_ATTR_EX_S;
typedef struct xmAO_CHN_STATE_S
{
XM_U32 u32ChnTotalNum; /* total number of channel buffer */
XM_U32 u32ChnFreeNum; /* free number of channel buffer */
XM_U32 u32ChnBusyNum; /* busy number of channel buffer */
} AO_CHN_STATE_S;
typedef struct xmAIO_RESMP_INFO_S
{
XM_BOOL bReSmpEnable; /* resample enable or disable */
XM_BOOL bReSmpEnableEx; /*advanced resample enable or disable */
AUDIO_RESAMPLE_ATTR_S stResmpAttr;
AUDIO_RESAMPLE_ATTR_EX_S stResmpAttrEx;
} AIO_RESMP_INFO_S;
typedef struct xmAI_ANR_INFO_S
{
XM_BOOL bAnrEnable; /* noise reduce enable or disable */
} AI_ANR_INFO_S;
typedef enum xmAUDIO_AEC_MODE_E
{
AUDIO_AEC_MODE_RECEIVER = 0,
AUDIO_AEC_MODE_SPEAKER = 1,
AUDIO_AEC_MODE_HEADPHONE = 2,
AUDIO_AEC_MODE_BUTT
} AUDIO_AEC_MODE_E;
/**Defines the configure parameters of ALC.*/
typedef struct xmAI_ALC_CONFIG_S
{
XM_S32 s32MaxLev; /*s32MaxLev：[-23dBm0, -4dBm0]。default: -4dBm0*/
XM_S32 s32MinLev; /*s32MinLev： [-23dBm0, -4dBm0]。default: -16dBm0*/
XM_U32 u32MaxGain; /*u32MaxGain：[3dB,12dB]。default: 12dB*/
} AI_ALC_CONFIG_S;
/**Defines the configure parameters of AEC.*/
typedef struct xmAI_AEC_CONFIG_S
{
AUDIO_AEC_MODE_E enAecMode; /* AEC mode, default is speaker, 0:receiver 1:speaker 2:headphone */
XM_S32 s32Reserved;
} AI_AEC_CONFIG_S;
/**Defines the configure parameters of ANR.*/
typedef struct xmAI_ANR_CONFIG_S
{
XM_S32 s32Reserved;
} AI_ANR_CONFIG_S;
/**Defines the configure parameters of VQE.*/
typedef struct xmAI_VQE_CONFIG_S
{
XM_S32 bAecOpen;
XM_S32 bAnrOpen;
XM_S32 bAgcOpen;
XM_S32 s32SampleRate; /* Sample Rate：8KHz/11.025K/12K/16KHz。default: 8KHz*/
XM_S32 s32FrameSample; /* VQE frame length：
sample rate 8KHz: VQE frame length: 80/160/240/320/400/480， default: 160;
sample rate 11.025K/12K/16KHz: VQE frame length: 160/320/480/960， default: 160 */
AI_AEC_CONFIG_S stAecCfg;
AI_ANR_CONFIG_S stAnrCfg;
AI_ALC_CONFIG_S stAlcCfg;
} AI_VQE_CONFIG_S;
typedef struct xmAI_VQE_INFO_S
{
AI_VQE_CONFIG_S stVqeConfig; /*vqe config*/
XM_BOOL bVqeEnable; /* vqe enable or disable */
} AI_VQE_INFO_S;
/**Defines the configure parameters of AI saving file.*/
typedef struct xmAUDIO_SAVE_FILE_INFO_S
{
XM_BOOL bCfg;
XM_CHAR aFilePath[256];
//AI_SAVE_FILE_COMMOND_E eSaveFileCommond;
XM_U32 u32FileSize; /*in KB*/
} AUDIO_SAVE_FILE_INFO_S;
typedef enum xmAUDIO_FADE_RATE_E
{
AUDIO_FADE_RATE_1 = 0,
AUDIO_FADE_RATE_2 = 1,
AUDIO_FADE_RATE_4 = 2,
AUDIO_FADE_RATE_8 = 3,
AUDIO_FADE_RATE_16 = 4,
AUDIO_FADE_RATE_32 = 5,
AUDIO_FADE_RATE_64 = 6,
AUDIO_FADE_RATE_128 = 7,
AUDIO_FADE_RATE_BUTT
} AUDIO_FADE_RATE_E;
typedef struct xmAUDIO_FADE_S
{
XM_BOOL bFade;
AUDIO_FADE_RATE_E enFadeInRate;
AUDIO_FADE_RATE_E enFadeOutRate;
} AUDIO_FADE_S;
typedef void(*fAudioInPreCallBack) (unsigned char *buf, unsigned int len);
#define XM_TRACE_AI(level, fmt...) XM_TRACE(level, XM_ID_AI,##fmt)
#define XM_TRACE_AO(level, fmt...) XM_TRACE(level, XM_ID_AO,##fmt)
/* invlalid device ID */
#define XM_ERR_AI_INVALID_DEVID XM_DEF_ERR(XM_ID_AI, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_DEVID)
/* invlalid channel ID */
#define XM_ERR_AI_INVALID_CHNID XM_DEF_ERR(XM_ID_AI, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_CHNID)
/* at lease one parameter is illagal ,eg, an illegal enumeration value */
#define XM_ERR_AI_ILLEGAL_PARAM XM_DEF_ERR(XM_ID_AI, EN_ERR_LEVEL_ERROR, EN_ERR_ILLEGAL_PARAM)
/* using a NULL point */
#define XM_ERR_AI_NULL_PTR XM_DEF_ERR(XM_ID_AI, EN_ERR_LEVEL_ERROR, EN_ERR_NULL_PTR)
/* try to enable or initialize system,device or channel, before configing attribute */
#define XM_ERR_AI_NOT_CONFIG XM_DEF_ERR(XM_ID_AI, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_CONFIG)
/* operation is not supported by NOW */
#define XM_ERR_AI_NOT_SUPPORT XM_DEF_ERR(XM_ID_AI, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_SUPPORT)
/* operation is not permitted ,eg, try to change stati attribute */
#define XM_ERR_AI_NOT_PERM XM_DEF_ERR(XM_ID_AI, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_PERM)
/* the devide is not enabled */
#define XM_ERR_AI_NOT_ENABLED XM_DEF_ERR(XM_ID_AI, EN_ERR_LEVEL_ERROR, EN_ERR_UNEXIST)
/* failure caused by malloc memory */
#define XM_ERR_AI_NOMEM XM_DEF_ERR(XM_ID_AI, EN_ERR_LEVEL_ERROR, EN_ERR_NOMEM)
/* failure caused by malloc buffer */
#define XM_ERR_AI_NOBUF XM_DEF_ERR(XM_ID_AI, EN_ERR_LEVEL_ERROR, EN_ERR_NOBUF)
/* no data in buffer */
#define XM_ERR_AI_BUF_EMPTY XM_DEF_ERR(XM_ID_AI, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_EMPTY)
/* no buffer for new data */
#define XM_ERR_AI_BUF_FULL XM_DEF_ERR(XM_ID_AI, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_FULL)
/* system is not ready,had not initialed or loaded*/
#define XM_ERR_AI_SYS_NOTREADY XM_DEF_ERR(XM_ID_AI, EN_ERR_LEVEL_ERROR, EN_ERR_SYS_NOTREADY)
#define XM_ERR_AI_BUSY XM_DEF_ERR(XM_ID_AI, EN_ERR_LEVEL_ERROR, EN_ERR_BUSY)
/* invlalid device ID */
#define XM_ERR_AO_INVALID_DEVID XM_DEF_ERR(XM_ID_AO, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_DEVID)
/* invlalid channel ID */
#define XM_ERR_AO_INVALID_CHNID XM_DEF_ERR(XM_ID_AO, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_CHNID)
/* at lease one parameter is illagal ,eg, an illegal enumeration value */
#define XM_ERR_AO_ILLEGAL_PARAM XM_DEF_ERR(XM_ID_AO, EN_ERR_LEVEL_ERROR, EN_ERR_ILLEGAL_PARAM)
/* using a NULL point */
#define XM_ERR_AO_NULL_PTR XM_DEF_ERR(XM_ID_AO, EN_ERR_LEVEL_ERROR, EN_ERR_NULL_PTR)
/* try to enable or initialize system,device or channel, before configing attribute */
#define XM_ERR_AO_NOT_CONFIG XM_DEF_ERR(XM_ID_AO, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_CONFIG)
/* operation is not supported by NOW */
#define XM_ERR_AO_NOT_SUPPORT XM_DEF_ERR(XM_ID_AO, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_SUPPORT)
/* operation is not permitted ,eg, try to change stati attribute */
#define XM_ERR_AO_NOT_PERM XM_DEF_ERR(XM_ID_AO, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_PERM)
/* the devide is not enabled */
#define XM_ERR_AO_NOT_ENABLED XM_DEF_ERR(XM_ID_AO, EN_ERR_LEVEL_ERROR, EN_ERR_UNEXIST)
/* failure caused by malloc memory */
#define XM_ERR_AO_NOMEM XM_DEF_ERR(XM_ID_AO, EN_ERR_LEVEL_ERROR, EN_ERR_NOMEM)
/* failure caused by malloc buffer */
#define XM_ERR_AO_NOBUF XM_DEF_ERR(XM_ID_AO, EN_ERR_LEVEL_ERROR, EN_ERR_NOBUF)
/* no data in buffer */
#define XM_ERR_AO_BUF_EMPTY XM_DEF_ERR(XM_ID_AO, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_EMPTY)
/* no buffer for new data */
#define XM_ERR_AO_BUF_FULL XM_DEF_ERR(XM_ID_AO, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_FULL)
/* system is not ready,had not initialed or loaded*/
#define XM_ERR_AO_SYS_NOTREADY XM_DEF_ERR(XM_ID_AO, EN_ERR_LEVEL_ERROR, EN_ERR_SYS_NOTREADY)
#define XM_ERR_AO_BUSY XM_DEF_ERR(XM_ID_AO, EN_ERR_LEVEL_ERROR, EN_ERR_BUSY)
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* End of #ifndef __XM_COMM_AI_H__ */

322
general/package/xiongmai-osdrv-xm530/files/include/xm_comm_rc.h
View File

@ -1,322 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2025, XM Tech. Co., Ltd.
******************************************************************************
File Name : xm_comm_rc.h
Version : Initial Draft
Author : XM multimedia software group
Created : 2015/9/17
Description :
******************************************************************************/
#ifndef __XM_COMM_RC_H__
#define __XM_COMM_RC_H__
#include "xm_defines.h"
#ifdef __cplusplus
#if __cplusplus
extern "C"{
#endif
#endif /* __cplusplus */
typedef XM_U32 XM_FR32;
typedef enum xmVENC_RC_MODE_E
{
VENC_RC_MODE_H264CBR = 1,
VENC_RC_MODE_H264VBR,
VENC_RC_MODE_H264ABR,
VENC_RC_MODE_H264FIXQP,
VENC_RC_MODE_MJPEGCBR,
VENC_RC_MODE_MJPEGVBR,
VENC_RC_MODE_MJPEGABR,
VENC_RC_MODE_MJPEGFIXQP,
VENC_RC_MODE_MPEG4CBR,
VENC_RC_MODE_MPEG4VBR,
VENC_RC_MODE_MPEG4ABR,
VENC_RC_MODE_MPEG4FIXQP,
VENC_RC_MODE_H265CBR,
VENC_RC_MODE_H265VBR,
VENC_RC_MODE_H265FIXQP,
VENC_RC_MODE_BUTT,
}VENC_RC_MODE_E;
typedef struct xmVENC_ATTR_H264_FIXQP_S
{
XM_U32 u32Gop; /*the interval of ISLICE. */
XM_U32 u32SrcFrmRate; /* the input frame rate of the venc chnnel */
XM_FR32 fr32DstFrmRate ; /* the target frame rate of the venc chnnel */
XM_U32 u32IQp; /* qp of the i frame */
XM_U32 u32PQp; /* qp of the p frame */
} VENC_ATTR_H264_FIXQP_S;
typedef struct xmVENC_ATTR_H264_CBR_S
{
XM_U32 u32Gop; /*the interval of ISLICE. */
XM_U32 u32StatTime; /* the rate statistic time, the unit is senconds(s) */
XM_U32 u32SrcFrmRate; /* the input frame rate of the venc chnnel */
XM_FR32 fr32DstFrmRate ; /* the target frame rate of the venc chnnel */
XM_U32 u32BitRate; /* average bitrate */
XM_U32 u32FluctuateLevel; /* level [0..5].scope of bitrate fluctuate. 1-5: 10%-50%. 0: SDK optimized, recommended; */
} VENC_ATTR_H264_CBR_S;
typedef struct xmVENC_ATTR_H264_VBR_S
{
XM_U32 u32Gop; /*the interval of ISLICE. */
XM_U32 u32StatTime; /* the rate statistic time, the unit is senconds(s) */
XM_U32 u32SrcFrmRate; /* the input frame rate of the venc chnnel */
XM_FR32 fr32DstFrmRate ; /* the target frame rate of the venc chnnel */
XM_U32 u32MaxBitRate; /* the max bitrate */
XM_U32 u32MaxQp; /* the max qp */
XM_U32 u32MinQp; /* the min qp */
}VENC_ATTR_H264_VBR_S;
typedef struct xmVENC_ATTR_H264_ABR_S
{
XM_U32 u32Gop; /*the interval of ISLICE. */
XM_U32 u32StatTime; /* the rate statistic time, the unit is senconds(s) */
XM_U32 u32SrcFrmRate; /* the input frame rate of the venc chnnel */
XM_FR32 fr32DstFrmRate ; /* the target frame rate of the venc chnnel */
XM_U32 u32AvgBitRate; /* average bitrate */
XM_U32 u32MaxBitRate; /* the max bitrate */
}VENC_ATTR_H264_ABR_S;
typedef struct xmVENC_ATTR_H264_CBR_S VENC_ATTR_H265_CBR_S;
typedef struct xmVENC_ATTR_H264_VBR_S VENC_ATTR_H265_VBR_S;
typedef struct xmVENC_ATTR_H264_FIXQP_S VENC_ATTR_H265_FIXQP_S;
typedef struct xmVENC_ATTR_MPEG4_FIXQP_S
{
XM_U32 u32Gop; /*the interval of ISLICE. */
XM_U32 u32SrcFrmRate; /* the input frame rate of the venc chnnel */
XM_FR32 fr32DstFrmRate ; /* the target frame rate of the venc chnnel */
XM_U32 u32IQp; /* qp of the i frame */
XM_U32 u32PQp; /* qp of the p frame */
}VENC_ATTR_MPEG4_FIXQP_S;
typedef struct xmVENC_ATTR_MPEG4_CBR_S
{
XM_U32 u32Gop; /*the interval of ISLICE. */
XM_U32 u32StatTime; /* the rate statistic time, the unit is senconds(s) */
XM_U32 u32SrcFrmRate; /* the input frame rate of the venc chnnel */
XM_FR32 fr32DstFrmRate ; /* the target frame rate of the venc chnnel */
XM_U32 u32BitRate; /* average bitrate */
XM_U32 u32FluctuateLevel; /* level [0..5].scope of bitrate fluctuate. 1-5: 10%-50%. 0: SDK optimized, recommended; */
}VENC_ATTR_MPEG4_CBR_S;
typedef struct xmVENC_ATTR_MPEG4_VBR_S
{
XM_U32 u32Gop; /* the interval of ISLICE. */
XM_U32 u32StatTime; /* the rate statistic time, the unit is senconds(s) */
XM_U32 u32SrcFrmRate; /* the input frame rate of the venc chnnel */
XM_FR32 fr32DstFrmRate ; /* the target frame rate of the venc chnnel */
XM_U32 u32MaxBitRate; /* the max bitrate */
XM_U32 u32MaxQp; /* the max qp */
XM_U32 u32MinQp; /* the min qp */
}VENC_ATTR_MPEG4_VBR_S;
typedef struct xmVENC_ATTR_MJPEG_FIXQP_S
{
XM_U32 u32SrcFrmRate; /* the input frame rate of the venc chnnel */
XM_FR32 fr32DstFrmRate; /* the target frame rate of the venc chnnel */
XM_U32 u32Qfactor; /* image quality :[1,99]*/
}VENC_ATTR_MJPEG_FIXQP_S;
typedef struct xmVENC_ATTR_MJPEG_CBR_S
{
XM_U32 u32StatTime; /* the rate statistic time, the unit is senconds(s) */
XM_U32 u32SrcFrmRate; /* the input frame rate of the venc chnnel */
XM_FR32 fr32DstFrmRate ; /* the target frame rate of the venc chnnel */
XM_U32 u32BitRate; /* average bitrate */
XM_U32 u32FluctuateLevel; /* level [0..5].scope of bitrate fluctuate. 1-5: 10%-50%. 0: SDK optimized, recommended; */
} VENC_ATTR_MJPEG_CBR_S;
typedef struct xmVENC_ATTR_MJPEG_VBR_S
{
XM_U32 u32StatTime; /* the rate statistic time, the unit is senconds(s) */
XM_U32 u32SrcFrmRate; /* the input frame rate of the venc chnnel */
XM_FR32 fr32DstFrmRate; /* the target frame rate of the venc chnnel */
XM_U32 u32MaxBitRate; /* max bitrate */
XM_U32 u32MaxQfactor; /* max image quailty allowed */
XM_U32 u32MinQfactor; /* min image quality allowed */
}VENC_ATTR_MJPEG_VBR_S;
typedef struct xmVENC_RC_ATTR_S
{
VENC_RC_MODE_E enRcMode; /*the type of rc*/
union
{
VENC_ATTR_H264_CBR_S stAttrH264Cbr;
VENC_ATTR_H264_VBR_S stAttrH264Vbr;
VENC_ATTR_H264_FIXQP_S stAttrH264FixQp;
VENC_ATTR_H264_ABR_S stAttrH264Abr;
VENC_ATTR_MPEG4_CBR_S stAttrMpeg4Cbr;
VENC_ATTR_MPEG4_FIXQP_S stAttrMpeg4FixQp;
VENC_ATTR_MPEG4_VBR_S stAttrMpeg4Vbr;
VENC_ATTR_MJPEG_CBR_S stAttrMjpegeCbr;
VENC_ATTR_MJPEG_FIXQP_S stAttrMjpegeFixQp;
VENC_ATTR_MJPEG_VBR_S stAttrMjpegeVbr;
VENC_ATTR_H265_CBR_S stAttrH265Cbr;
VENC_ATTR_H265_VBR_S stAttrH265Vbr;
VENC_ATTR_H265_FIXQP_S stAttrH265FixQp;
};
XM_VOID* pRcAttr ; /*the rc attribute which could be specified by user*/
}VENC_RC_ATTR_S;
typedef enum xmRC_SUPERFRM_MODE_E
{
SUPERFRM_NONE, /* sdk don't care super frame */
SUPERFRM_DISCARD, /* the super frame is discarded */
SUPERFRM_REENCODE, /* the super frame is re-encode */
SUPERFRM_BUTT
}VENC_SUPERFRM_MODE_E;
typedef struct xmVENC_PARAM_H264_CBR_S
{
XM_U32 u32MinIprop; /* the min ratio of i frame and p frame */
XM_U32 u32MaxIprop; /* the max ratio of i frame and p frame */
XM_U32 u32MaxQp; /* the max QP value */
XM_U32 u32MinQp; /* the min QP value */
XM_S32 s32IPQPDelta; /* the qp difference between the i frame and the before gop avarage qp; == Qp(P) - Qp(I) */
XM_S32 s32QualityLevel; /* quality of picture [1, 5] */
XM_S32 s32MaxReEncodeTimes; /* max number of re-encode times [0, 3]*/
XM_U32 u32MinIQp; /* min qp for i frame */
}VENC_PARAM_H264_CBR_S;
typedef struct xmVENC_PARAM_H264_VBR_S
{
XM_S32 s32IPQPDelta; /* the qp difference between the i frame and the before gop avarage qp; == Qp(P) - Qp(I) */
XM_S32 s32ChangePos; /* Indicates the ratio of the current bit rate to the maximum
bit rate when the QP value starts to be adjusted */
XM_U32 u32MinIprop; /* the min ratio of i frame and p frame */
XM_U32 u32MaxIprop; /* the max ratio of i frame and p frame */
XM_U32 u32MinIQP; /* min qp for i frame */
}VENC_PARAM_H264_VBR_S;
typedef struct xmVENC_PARAM_MJPEG_CBR_S
{
XM_U32 u32MaxQfactor; /* the max Qfactor value*/
XM_U32 u32MinQfactor; /* the min Qfactor value */
//XM_U32 u32RQRatio[RC_RQRATIO_SIZE]; /* the rate stabilization weight,
//100-u32RQRatio[i] is the sequence quality stabilization weight */
}VENC_PARAM_MJPEG_CBR_S;
typedef struct xmVENC_PARAM_MJPEG_VBR_S
{
XM_S32 s32DeltaQfactor; /* Indicates the maximum change of Qfactor values of frames
when the picture quality changes */
XM_S32 s32ChangePos; /* Indicates the ratio of the current bit rate to the maximum
bit rate when the Qfactor value starts to be adjusted */
}VENC_PARAM_MJPEG_VBR_S;
typedef struct xmVENC_PARAM_MPEG4_CBR_S
{
XM_U32 u32MinIprop; /* the min ratio of i frame and p frame*/
XM_U32 u32MaxIprop; /* the max ratio of i frame and p frame */
XM_U32 u32MaxQp; /* the max QP value*/
XM_U32 u32MinQp; /* the min QP value */
XM_U32 u32MaxPPDeltaQp; /* the max qp value difference between two successive P frame */
XM_U32 u32MaxIPDeltaQp; /* the max qp value difference between p frame and the next i frame */
XM_S32 s32IPQPDelta; /* the qp difference between the i frame and the before gop avarage qp*/
//XM_U32 u32RQRatio[RC_RQRATIO_SIZE]; /* the rate stabilization weight,
//100-u32RQRatio[i] is the sequence quality stabilization weight */
}VENC_PARAM_MPEG4_CBR_S;
typedef struct xmVENC_PARAM_MPEG4_VBR_S
{
XM_S32 s32IPQPDelta; /* the qp difference between the i frame and the before gop avarage qp*/
XM_S32 s32ChangePos; /* Indicates the ratio of the current bit rate to the maximum
bit rate when the QP value starts to be adjusted */
XM_U32 u32MinIprop; /* the min ratio of i frame and p frame */
XM_U32 u32MaxIprop; /* the max ratio of i frame and p frame */
}VENC_PARAM_MPEG4_VBR_S;
typedef struct xmVENC_PARAM_H264_CBR_S VENC_PARAM_H265_CBR_S;
typedef struct xmVENC_PARAM_H264_VBR_S VENC_PARAM_H265_VBR_S;
typedef struct xmVENC_RC_PARAM_S
{
//XM_U32 u32ThrdI[RC_TEXTURE_THR_SIZE]; /* just useful for h264/h265 and mpeg4 for now */
//XM_U32 u32ThrdP[RC_TEXTURE_THR_SIZE];
XM_U32 u32RowQpDelta;
union
{
VENC_PARAM_H264_CBR_S stParamH264Cbr;
VENC_PARAM_H264_VBR_S stParamH264VBR;
VENC_PARAM_MJPEG_CBR_S stParamMjpegCbr;
VENC_PARAM_MJPEG_VBR_S stParamMjpegVbr;
VENC_PARAM_MPEG4_CBR_S stParamMpeg4Cbr;
VENC_PARAM_MPEG4_VBR_S stParamMpeg4Vbr;
VENC_PARAM_H265_CBR_S stParamH265Cbr;
VENC_PARAM_H265_VBR_S stParamH265Vbr;
};
XM_VOID* pRcParam; /*RC parameter which could be specified by usrer*/
}VENC_RC_PARAM_S;
typedef enum xmVENC_FRAMELOST_MODE_E
{
FRMLOST_NORMAL, /*normal mode*/
FRMLOST_PSKIP, /*pskip*/
FRMLOST_BUTT,
}VENC_FRAMELOST_MODE_E;
typedef struct xmVENC_PARAM_FRAMELOST_S
{
XM_BOOL bFrmLostOpen; /* Indicates whether to discard frames to ensure
stable bit rate when the instant bit rate is exceeded */
XM_U32 u32FrmLostBpsThr; /* the instant bit rate threshold */
VENC_FRAMELOST_MODE_E enFrmLostMode; /*frame lost strategy*/
XM_U32 u32EncFrmGaps; /*the gap of frame lost*/
}VENC_PARAM_FRAMELOST_S;
typedef struct xmVENC_SUPERFRAME_CFG_S
{
VENC_SUPERFRM_MODE_E enSuperFrmMode; /* Indicates the mode of processing the super frame,[SUPERFRM_NONE,SUPERFRM_DISCARD,SUPERFRM_REENCODE]*/
XM_U32 u32SuperIFrmBitsThr; /* Indicate the threshold of the super I frame
for enabling the super frame processing mode */
XM_U32 u32SuperPFrmBitsThr; /* Indicate the threshold of the super P frame */
XM_U32 u32SuperBFrmBitsThr; /* Indicate the threshold of the super B frame */
}VENC_SUPERFRAME_CFG_S;
typedef enum xmVENC_RC_PRIORITY_E
{
VENC_RC_PRIORITY_BITRATE_FIRST = 1,
VENC_RC_PRIORITY_FRAMEBITS_FIRST,
VENC_RC_PRIORITY_BUTT,
} VENC_RC_PRIORITY_E;
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /* __XM_COMM_RC_H__ */

144
general/package/xiongmai-osdrv-xm530/files/include/xm_comm_region.h
View File

@ -1,144 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2025, XM Tech. Co., Ltd.
******************************************************************************
File Name : xm_comm_region.h
Version : Initial Draft
Author : XM multimedia software group
Created : 2015/9/17
Description :
******************************************************************************/
#ifndef __XM_COMM_REGION_H__
#define __XM_COMM_REGION_H__
#include "xm_common.h"
#include "xm_comm_video.h"
#include "xm_errno.h"
#include "xm_defines.h"
#ifdef __cplusplus
#if __cplusplus
extern "C"{
#endif
#endif /* End of #ifdef __cplusplus */
typedef XM_U32 RGN_HANDLE;
/* type of video regions */
typedef enum xmRGN_TYPE_E
{
OVERLAY_RGN = 0, /* video overlay region */
COVER_RGN,
COVEREX_RGN,
OVERLAYEX_RGN,
RGN_BUTT
} RGN_TYPE_E;
typedef struct xmOVERLAY_COMM_ATTR_S
{
XM_U32 u32ColorMap;//3-0:背景调色盘索引 7-4:字符调色盘索引0, bit 11-8:字符调色盘索引1,
XM_U32 u32Effect; //BIt0-3 背景透明度,4-7淡入淡出,8-11闪烁,12-15水平放大,16-19垂直放大,20-23字符透明度
XM_U32 u32Format;//字符色彩模式，1 代表单色彩，2 代表双色彩，4 代表15色彩
RECT_S stRect;
}OVERLAY_ATTR_S;
typedef struct xmCOVER_COMM_ATTR_S
{
XM_U32 u32Color;
XM_U32 u32Effect; //0边框 1实心
RECT_S stRect;
}COVER_ATTR_S;
typedef union xmRGN_ATTR_U
{
OVERLAY_ATTR_S stOverlay;
COVER_ATTR_S stCover;
} RGN_ATTR_U;
typedef struct xmRGN_PALLET_S
{
XM_U32 pallet[16];
}RGN_PALLET_S;
/* attribute of a region */
typedef struct xmRGN_ATTR_S
{
XM_U32 u32Handle;
RGN_TYPE_E enType;
RGN_ATTR_U unAttr;
} RGN_ATTR_S;
#define RGN_MAX_BMP_UPD_NUM 16
typedef struct xmRGN_BMP_UPD_S
{
POINT_S stPoint;
BITMAP_S stBmp;
XM_U32 u32Stride;
} RGN_BMP_UPD_S;
typedef struct xmRGN_BMP_UPD_CFG_S
{
XM_U32 u32BmpCnt;
RGN_BMP_UPD_S astBmpUpd[RGN_MAX_BMP_UPD_NUM];
} RGN_BMP_UPD_CFG_S;
#define XM_TRACE_RGN(level, fmt...) XM_TRACE(level, XM_ID_RGN,##fmt)
/* invlalid device ID */
#define XM_ERR_RGN_INVALID_DEVID XM_DEF_ERR(XM_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_DEVID)
/* invlalid channel ID */
#define XM_ERR_RGN_INVALID_CHNID XM_DEF_ERR(XM_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_CHNID)
/* at lease one parameter is illagal ,eg, an illegal enumeration value */
#define XM_ERR_RGN_ILLEGAL_PARAM XM_DEF_ERR(XM_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_ILLEGAL_PARAM)
/* channel exists */
#define XM_ERR_RGN_EXIST XM_DEF_ERR(XM_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_EXIST)
/*UN exist*/
#define XM_ERR_RGN_UNEXIST XM_DEF_ERR(XM_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_UNEXIST)
/* using a NULL point */
#define XM_ERR_RGN_NULL_PTR XM_DEF_ERR(XM_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_NULL_PTR)
/* try to enable or initialize system,device or channel, before configing attribute */
#define XM_ERR_RGN_NOT_CONFIG XM_DEF_ERR(XM_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_CONFIG)
/* operation is not supported by NOW */
#define XM_ERR_RGN_NOT_SUPPORT XM_DEF_ERR(XM_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_SUPPORT)
/* operation is not permitted ,eg, try to change stati attribute */
#define XM_ERR_RGN_NOT_PERM XM_DEF_ERR(XM_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_PERM)
/* failure caused by malloc memory */
#define XM_ERR_RGN_NOMEM XM_DEF_ERR(XM_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_NOMEM)
/* failure caused by malloc buffer */
#define XM_ERR_RGN_NOBUF XM_DEF_ERR(XM_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_NOBUF)
/* no data in buffer */
#define XM_ERR_RGN_BUF_EMPTY XM_DEF_ERR(XM_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_EMPTY)
/* no buffer for new data */
#define XM_ERR_RGN_BUF_FULL XM_DEF_ERR(XM_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_FULL)
/* bad address, eg. used for copy_from_user & copy_to_user */
#define XM_ERR_RGN_BADADDR XM_DEF_ERR(XM_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_BADADDR)
/* resource is busy, eg. destroy a venc chn without unregistering it */
#define XM_ERR_RGN_BUSY XM_DEF_ERR(XM_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_BUSY)
/* System is not ready,maybe not initialed or loaded.
* Returning the error code when opening a device file failed.
*/
#define XM_ERR_RGN_NOTREADY XM_DEF_ERR(XM_ID_RGN, EN_ERR_LEVEL_ERROR, EN_ERR_SYS_NOTREADY)
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /* __XM_COMM_REGION_H__ */

54
general/package/xiongmai-osdrv-xm530/files/include/xm_comm_sys.h
View File

@ -1,54 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2025, XM Tech. Co., Ltd.
******************************************************************************
File Name : xm_comm_sys.h
Version : Initial Draft
Author : XM multimedia software group
Created : 2015/9/17
Description :
******************************************************************************/
#ifndef __XM_COMM_SYS_H__
#define __XM_COMM_SYS_H__
#include "xm_type.h"
#include "xm_errno.h"
#include "xm_debug.h"
#ifdef __cplusplus
#if __cplusplus
extern "C"{
#endif
#endif /* End of #ifdef __cplusplus */
#define XM_TRACE_SYS(level, fmt...) XM_TRACE(level, XM_ID_SYS,##fmt)
typedef struct xmMPP_SYS_CONF_S
{
/* stride of picture buffer must be aligned with this value.
* you can choose a value from 1 to 1024, and it must be multiple of 16.
*/
XM_U32 u32AlignWidth;
}MPP_SYS_CONF_S;
#define XM_ERR_SYS_NULL_PTR XM_DEF_ERR(XM_ID_SYS, EN_ERR_LEVEL_ERROR, EN_ERR_NULL_PTR)
#define XM_ERR_SYS_NOTREADY XM_DEF_ERR(XM_ID_SYS, EN_ERR_LEVEL_ERROR, EN_ERR_SYS_NOTREADY)
#define XM_ERR_SYS_NOT_PERM XM_DEF_ERR(XM_ID_SYS, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_PERM)
#define XM_ERR_SYS_NOMEM XM_DEF_ERR(XM_ID_SYS, EN_ERR_LEVEL_ERROR, EN_ERR_NOMEM)
#define XM_ERR_SYS_ILLEGAL_PARAM XM_DEF_ERR(XM_ID_SYS, EN_ERR_LEVEL_ERROR, EN_ERR_ILLEGAL_PARAM)
#define XM_ERR_SYS_BUSY XM_DEF_ERR(XM_ID_SYS, EN_ERR_LEVEL_ERROR, EN_ERR_BUSY)
#define XM_ERR_SYS_NOT_SUPPORT XM_DEF_ERR(XM_ID_SYS, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_SUPPORT)
#define XM_ERR_SYS_UNEXIST XM_DEF_ERR(XM_ID_SYS, EN_ERR_LEVEL_ERROR, EN_ERR_UNEXIST)
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /* __XM_COMM_SYS_H__ */

147
general/package/xiongmai-osdrv-xm530/files/include/xm_comm_vdec.h
View File

@ -1,147 +0,0 @@
#ifndef __XM_COMM_VENC_H__
#define __XM_COMM_VENC_H__
#include "xm_type.h"
#include "xm_common.h"
#include "xm_errno.h"
#include "xm_comm_video.h"
#ifdef __cplusplus
#if __cplusplus
extern "C"{
#endif
#endif /* __cplusplus */
/* invlalid channel ID */
#define XM_ERR_VDEC_INVALID_CHNID XM_DEF_ERR(XM_ID_VDEC, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_CHNID)
/* at lease one parameter is illagal ,eg, an illegal enumeration value */
#define XM_ERR_VDEC_ILLEGAL_PARAM XM_DEF_ERR(XM_ID_VDEC, EN_ERR_LEVEL_ERROR, EN_ERR_ILLEGAL_PARAM)
/* channel exists */
#define XM_ERR_VDEC_EXIST XM_DEF_ERR(XM_ID_VDEC, EN_ERR_LEVEL_ERROR, EN_ERR_EXIST)
/* channel exists */
#define XM_ERR_VDEC_UNEXIST XM_DEF_ERR(XM_ID_VDEC, EN_ERR_LEVEL_ERROR, EN_ERR_UNEXIST)
/* using a NULL point */
#define XM_ERR_VDEC_NULL_PTR XM_DEF_ERR(XM_ID_VDEC, EN_ERR_LEVEL_ERROR, EN_ERR_NULL_PTR)
/* try to enable or initialize system,device or channel, before configing attribute */
#define XM_ERR_VDEC_NOT_CONFIG XM_DEF_ERR(XM_ID_VDEC, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_CONFIG)
/* operation is not supported by NOW */
#define XM_ERR_VDEC_NOT_SUPPORT XM_DEF_ERR(XM_ID_VDEC, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_SUPPORT)
/* operation is not permitted ,eg, try to change stati attribute */
#define XM_ERR_VDEC_NOT_PERM XM_DEF_ERR(XM_ID_VDEC, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_PERM)
/*encode one frame not finish,maybe bus error,timeout,sys reset and so on*/
#define XM_ERR_VDEC_NOT_FINISH XM_DEF_ERR(XM_ID_VDEC, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_FINISH)
/* insufficient resource*/
#define XM_ERR_VDEC_INSUFF_RES XM_DEF_ERR(XM_ID_VDEC, EN_ERR_LEVEL_ERROR, EN_ERR_INSUFF_RES)
/* failure caused by malloc memory */
#define XM_ERR_VDEC_NOMEM XM_DEF_ERR(XM_ID_VDEC, EN_ERR_LEVEL_ERROR, EN_ERR_NOMEM)
/* failure caused by malloc buffer */
#define XM_ERR_VDEC_NOBUF XM_DEF_ERR(XM_ID_VDEC, EN_ERR_LEVEL_ERROR, EN_ERR_NOBUF)
/* no data in buffer */
#define XM_ERR_VDEC_BUF_EMPTY XM_DEF_ERR(XM_ID_VDEC, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_EMPTY)
/* no buffer for new data */
#define XM_ERR_VDEC_BUF_FULL XM_DEF_ERR(XM_ID_VDEC, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_FULL)
/* system is not ready,had not initialed or loaded*/
#define XM_ERR_VDEC_SYS_NOTREADY XM_DEF_ERR(XM_ID_VDEC, EN_ERR_LEVEL_ERROR, EN_ERR_SYS_NOTREADY)
/*failure caused by hardware issue eg: hardware not init or config*/
#define XM_ERR_VDEC_HW_FAILED XM_DEF_ERR(XM_ID_VDEC, EN_ERR_LEVEL_ERROR, EN_ERR_HW_FAILED)
/* system is busy*/
#define XM_ERR_VDEC_BUSY XM_DEF_ERR(XM_ID_VDEC, EN_ERR_LEVEL_ERROR, EN_ERR_BUSY)
/* undefined error */
#define XM_ERR_VDEC_UND_ERROR XM_DEF_ERR(XM_ID_VDEC, EN_ERR_LEVEL_ERROR, EN_ERR_UND)
typedef enum xmVIDEO_MODE_E
{
VIDEO_MODE_STREAM = 0,
VIDEO_MODE_FRAME,
VIDEO_MODE_BUTT
}VIDEO_MODE_E;
typedef struct xmVDEC_STREAM_S
{
XM_U8 *pu8Addr;
XM_U32 u32Len;
XM_U64 u64PTS;
}VDEC_STREAM_S;
typedef struct xmVDEC_ATTR_JPEG_S
{
VIDEO_MODE_E enMode;
}VDEC_ATTR_JPEG_S;
typedef struct xmVDEC_ATTR_VIDEO_S
{
XM_U32 u32RefFrame;
VIDEO_MODE_E enMode;
XM_S32 s32SupportBFrame;
}VDEC_ATTR_VIDEO_S;
typedef struct xmVDEC_CHN_ATTR_S
{
PAYLOAD_TYPE_E enType;
XM_U32 u32BufSize;
XM_U32 u32Priority;
XM_U32 u32PicWidth;
XM_U32 u32PicHeight;
union
{
VDEC_ATTR_JPEG_S stVdecJpegAttr;
VDEC_ATTR_VIDEO_S stVdecVideoAtrr;
};
}VDEC_CHN_ATTR_S;
typedef struct xmVDEC_USERDATA_S
{
XM_U8 *pu8Addr;
XM_U32 u32PhyAddr;
XM_U32 u32Len;
XM_BOOL bValid;
}VDEC_USERDATA_S;
typedef struct xmVDEC_CHN_STAT_S
{
XM_U32 u32LeftStreamBytes;/*待解码byte数*/
XM_U32 u32LeftStreamFrames;/*待解码的frame数*/
XM_U32 u32LeftPics;/*待获取的pic数*/
XM_BOOL bStartRecvStream;/*是否允许接受码流*/
XM_U32 u32RecvStreamFrames;/*已接收的frame数*/
XM_U32 u32DecodeStreamFrames;/*已解码的frame数*/
}VDEC_CHN_STAT_S;
typedef union
{
struct
{
XM_S32 IsAdvProfile;
XM_S32 CodecVersion;
}Vc1Ext;
struct
{
XM_S32 bReversed;
}Vp6Ext;
}VDEC_STD_EXTENSION_U;
typedef struct xmVDEC_CHN_PARAM_S
{
VDEC_STD_EXTENSION_U StdExt;
XM_S32 s32ChanErrThr;
XM_S32 s32ChanStrmOfThr;
XM_S32 s32DecMode;
XM_S32 s32DecOrderOutput;
XM_S32 s32DnrTfEnable;
XM_S32 s32DnrDispOutEnable;
XM_U32 u32MaxFramesInDec;
}VDEC_CHN_PARAM_S;
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif

593
general/package/xiongmai-osdrv-xm530/files/include/xm_comm_venc.h
View File

@ -1,593 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2025, XM Tech. Co., Ltd.
******************************************************************************
File Name : xm_comm_venc.h
Version : Initial Draft
Author : XM multimedia software group
Created : 2015/9/17
Description :
******************************************************************************/
#ifndef __XM_COMM_VENC_H__
#define __XM_COMM_VENC_H__
#ifdef __cplusplus
#if __cplusplus
extern "C"{
#endif
#endif /* __cplusplus */
#include "xm_type.h"
#include "xm_common.h"
#include "xm_errno.h"
#include "xm_comm_video.h"
#include "xm_comm_rc.h"
#define XM_TRACE_VENC(level, fmt...) XM_TRACE(level, XM_ID_VENC,##fmt)
/* invlalid channel ID */
#define XM_ERR_VENC_INVALID_CHNID XM_DEF_ERR(XM_ID_VENC, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_CHNID)
/* at lease one parameter is illagal ,eg, an illegal enumeration value */
#define XM_ERR_VENC_ILLEGAL_PARAM XM_DEF_ERR(XM_ID_VENC, EN_ERR_LEVEL_ERROR, EN_ERR_ILLEGAL_PARAM)
/* channel exists */
#define XM_ERR_VENC_EXIST XM_DEF_ERR(XM_ID_VENC, EN_ERR_LEVEL_ERROR, EN_ERR_EXIST)
/* channel exists */
#define XM_ERR_VENC_UNEXIST XM_DEF_ERR(XM_ID_VENC, EN_ERR_LEVEL_ERROR, EN_ERR_UNEXIST)
/* using a NULL point */
#define XM_ERR_VENC_NULL_PTR XM_DEF_ERR(XM_ID_VENC, EN_ERR_LEVEL_ERROR, EN_ERR_NULL_PTR)
/* try to enable or initialize system,device or channel, before configing attribute */
#define XM_ERR_VENC_NOT_CONFIG XM_DEF_ERR(XM_ID_VENC, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_CONFIG)
/* operation is not supported by NOW */
#define XM_ERR_VENC_NOT_SUPPORT XM_DEF_ERR(XM_ID_VENC, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_SUPPORT)
/* operation is not permitted ,eg, try to change stati attribute */
#define XM_ERR_VENC_NOT_PERM XM_DEF_ERR(XM_ID_VENC, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_PERM)
/* encode one frame not finish,maybe bus error,timeout,sys reset and so on */
#define XM_ERR_VENC_NOT_FINISH XM_DEF_ERR(XM_ID_VENC, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_FINISH)
/* insufficient resource*/
#define XM_ERR_VENC_INSUFF_RES XM_DEF_ERR(XM_ID_VENC, EN_ERR_LEVEL_ERROR, EN_ERR_INSUFF_RES)
/* failure caused by malloc memory */
#define XM_ERR_VENC_NOMEM XM_DEF_ERR(XM_ID_VENC, EN_ERR_LEVEL_ERROR, EN_ERR_NOMEM)
/* failure caused by malloc buffer */
#define XM_ERR_VENC_NOBUF XM_DEF_ERR(XM_ID_VENC, EN_ERR_LEVEL_ERROR, EN_ERR_NOBUF)
/* no data in buffer */
#define XM_ERR_VENC_BUF_EMPTY XM_DEF_ERR(XM_ID_VENC, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_EMPTY)
/* no buffer for new data */
#define XM_ERR_VENC_BUF_FULL XM_DEF_ERR(XM_ID_VENC, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_FULL)
/* system is not ready,had not initialed or loaded*/
#define XM_ERR_VENC_SYS_NOTREADY XM_DEF_ERR(XM_ID_VENC, EN_ERR_LEVEL_ERROR, EN_ERR_SYS_NOTREADY)
/* encoder hardware init or config failed */
#define XM_ERR_VENC_HW_FAILED XM_DEF_ERR(XM_ID_VENC, EN_ERR_LEVEL_ERROR, EN_ERR_HW_FAILED)
/* system is busy*/
#define XM_ERR_VENC_BUSY XM_DEF_ERR(XM_ID_VENC, EN_ERR_LEVEL_ERROR, EN_ERR_BUSY)
/* undefined error */
#define XM_ERR_VENC_UND_ERROR XM_DEF_ERR(XM_ID_VENC, EN_ERR_LEVEL_ERROR, EN_ERR_UND)
/*the coding frame type for H265*/
typedef enum xmH265E_Coding_Type_E
{
H265ENC_INFO_FRAME = 0,
H265ENC_INTRA_FRAME = 1,
H265ENC_PERDICTED_FRAME = 2,
H265_NOTCODED_FRAME
}H265E_Coding_Type_E;
/*the nalu type of H264E*/
typedef enum xmH264E_NALU_TYPE_E
{
H264E_NALU_PSLICE = 1, /*PSLICE types*/
H264E_NALU_ISLICE = 5, /*ISLICE types*/
H264E_NALU_SEI = 6, /*SEI types*/
H264E_NALU_SPS = 7, /*SPS types*/
H264E_NALU_PPS = 8, /*PPS types*/
H264E_NALU_VIRP = 24, /*VISLICE types*/
H264E_NALU_BUTT
} H264E_NALU_TYPE_E;
/*the nalu type of H265E*/
typedef enum xmH265E_NALU_TYPE_E
{
H265E_NALU_PSLICE = 1, /*P SLICE types*/
H265E_NALU_ISLICE = 19, /*I SLICE types*/
H265E_NALU_VPS = 32, /*VPS types*/
H265E_NALU_SPS = 33, /*SPS types*/
H265E_NALU_PPS = 34, /*PPS types*/
H265E_NALU_SEI = 39, /*SEI types*/
H265E_NALU_BUTT
} H265E_NALU_TYPE_E;
/*the reference type of H264E slice*/
typedef enum xmH264E_REFSLICE_TYPE_E
{
H264E_REFSLICE_FOR_1X = 1, /*Reference slice for H264E_REF_MODE_1X*/
H264E_REFSLICE_FOR_2X = 2, /*Reference slice for H264E_REF_MODE_2X*/
H264E_REFSLICE_FOR_4X = 5, /*Reference slice for H264E_REF_MODE_4X*/
H264E_REFSLICE_FOR_BUTT /* slice not for reference*/
} H264E_REFSLICE_TYPE_E;
/*the pack type of JPEGE*/
typedef enum xmJPEGE_PACK_TYPE_E
{
JPEGE_PACK_ECS = 5, /*ECS types*/
JPEGE_PACK_APP = 6, /*APP types*/
JPEGE_PACK_VDO = 7, /*VDO types*/
JPEGE_PACK_PIC = 8, /*PIC types*/
JPEGE_PACK_BUTT
} JPEGE_PACK_TYPE_E;
/*the pack type of MPEG4*/
typedef enum xmMPEG4E_PACK_TYPE_E
{
MPEG4E_PACK_VOP_P = 1, /*P VOP packet types*/
MPEG4E_PACK_VOP_I = 5, /*I VOP packet types*/
MPEG4E_PACK_VOS = 6, /*VOS types*/
MPEG4E_PACK_VO = 7, /*VO types*/
MPEG4E_PACK_VOL = 8, /*VOL types*/
MPEG4E_PACK_GVOP = 9 /*GROUP of vop types */
} MPEG4E_PACK_TYPE_E;
/*the data type of VENC*/
typedef union xmVENC_DATA_TYPE_U
{
H264E_NALU_TYPE_E enH264EType; /*H264E NALU types*/
JPEGE_PACK_TYPE_E enJPEGEType; /*JPEGE pack types*/
MPEG4E_PACK_TYPE_E enMPEG4EType; /*MPEG4E pack types*/
H265E_NALU_TYPE_E enH265EType; /*H264E NALU types*/
}VENC_DATA_TYPE_U;
typedef struct xmVENC_PACK_INFO_S
{
VENC_DATA_TYPE_U u32PackType;
XM_U32 u32PackOffset;
XM_U32 u32PackLength;
}VENC_PACK_INFO_S;
typedef struct xmVENC_PACK_S
{
XM_U32 u32PhyAddr; /*the physics address of stream*/
XM_U8 *pu8Addr; /*the virtual address of stream*/
XM_U32 u32Len; /*the length of stream*/
XM_U64 u64PTS; /*PTS*/
XM_BOOL bFrameEnd; /*frame end？*/
VENC_DATA_TYPE_U DataType; /*the type of stream*/
}VENC_PACK_S;
typedef enum xmH264E_REF_TYPE_E
{
BASE_IDRSLICE = 0, //the Idr frame at Base layer
BASE_PSLICE_REFBYBASE, //the P frame at Base layer, referenced by other frames at Base layer
BASE_PSLICE_REFBYENHANCE, //the P frame at Base layer, referenced by other frames at Enhance layer
ENHANCE_PSLICE_REFBYENHANCE, //the P frame at Enhance layer, referenced by other frames at Enhance layer
ENHANCE_PSLICE_NOTFORREF, //the P frame at Enhance layer ,not referenced
ENHANCE_PSLICE_BUTT
} H264E_REF_TYPE_E;
typedef enum xmH264E_REF_TYPE_E H265E_REF_TYPE_E;
typedef struct xmVENC_STREAM_INFO_H264_S
{
XM_U32 u32PicBytesNum; /* the coded picture stream byte number */
XM_U32 u32PSkipMbNum; /* the skip macroblock num */
XM_U32 u32IpcmMbNum; /* the ipcm macroblock num */
XM_U32 u32Inter16x8MbNum; /* the inter16x8 macroblock num */
XM_U32 u32Inter16x16MbNum; /* the inter16x16 macroblock num */
XM_U32 u32Inter8x16MbNum; /* the inter8x16 macroblock num */
XM_U32 u32Inter8x8MbNum; /* the inter8x8 macroblock num */
XM_U32 u32Intra16MbNum; /* the intra16x16 macroblock num */
XM_U32 u32Intra8MbNum; /* the intra8x8 macroblock num */
XM_U32 u32Intra4MbNum; /* the inter4x4 macroblock num */
H264E_REFSLICE_TYPE_E enRefSliceType; /*the reference type of H264E slice*/
H264E_REF_TYPE_E enRefType; /*Type of encoded frames in advanced frame skipping reference mode*/
XM_U32 u32UpdateAttrCnt; /*Number of times that channel attributes or parameters (including RC parameters) are set*/
}VENC_STREAM_INFO_H264_S;
typedef struct xmVENC_STREAM_INFO_H265_S
{
XM_U32 u32PicBytesNum; /* the coded picture stream byte number */
XM_U32 u32Inter64x64CuNum; /* the num */
XM_U32 u32Inter32x32CuNum;
XM_U32 u32Inter16x16CuNum;
XM_U32 u32Inter8x8CuNum;
XM_U32 u32Intra32x32CuNum;
XM_U32 u32Intra16x16CuNum;
XM_U32 u32Intra8x8CuNum;
XM_U32 u32Intra4x4CuNum;
H265E_REF_TYPE_E enRefType; /*Type of encoded frames in advanced frame skipping reference mode*/
XM_U32 u32UpdateAttrCnt; /*Number of times that channel attributes or parameters (including RC parameters) are set*/
}VENC_STREAM_INFO_H265_S;
typedef struct xmVENC_STREAM_INFO_JPEG_S
{
XM_U32 u32PicBytesNum; /* the coded picture stream byte number */
XM_U32 u32UpdateAttrCnt; /*Number of times that channel attributes or parameters (including RC parameters) are set*/
XM_U32 u32Qfactor; /* image quality */
}VENC_STREAM_INFO_JPEG_S;
typedef struct xmVENC_STREAM_INFO_MPEG4_S
{
XM_U32 u32PicBytesNum; /* the coded picture stream byte number */
XM_U32 u32UpdateAttrCnt; /*Number of times that channel attributes or parameters (including RC parameters) are set*/
}VENC_STREAM_INFO_MPEG4_S;
typedef struct xmVENC_STREAM_S
{
VENC_PACK_S *pstPack; /*stream pack attribute*/
XM_U32 u32PackCount; /*the pack number of one frame stream*/
XM_U32 u32Seq; /*the list number of stream*/
}VENC_STREAM_S;
typedef struct xmVENC_ATTR_H264_S
{
XM_U32 u32MaxPicWidth; /*maximum width of a picture to be encoded, in pixel*/
XM_U32 u32MaxPicHeight; /*maximum height of a picture to be encoded, in pixel*/
XM_U32 u32BufSize; /*stream buffer size*/
XM_U32 u32Profile; /*0: baseline; 1:MP; 2:HP; 3: SVC-T [0,3]; */
XM_BOOL bByFrame; /*get stream mode is slice mode or frame mode*/
XM_U32 u32PicWidth; /*width of a picture to be encoded, in pixel*/
XM_U32 u32PicHeight; /*height of a picture to be encoded, in pixel*/
XM_U32 u32BFrameNum; /* 0: not support B frame; >=1: number of B frames */
XM_U32 u32RefNum; /* 0: default; number of refrence frame*/
}VENC_ATTR_H264_S;
typedef struct xmVENC_ATTR_H265_S
{
XM_U32 u32MaxPicWidth; /*maximum width of a picture to be encoded, in pixel*/
XM_U32 u32MaxPicHeight; /*maximum height of a picture to be encoded, in pixel*/
XM_U32 u32BufSize; /*stream buffer size*/
XM_U32 u32Profile; /*0: MP */
XM_BOOL bByFrame; /*get stream mode is slice mode or frame mode*/
XM_U32 u32PicWidth; /*width of a picture to be encoded, in pixel*/
XM_U32 u32PicHeight; /*height of a picture to be encoded, in pixel*/
XM_U32 u32BFrameNum; /* 0: not support B frame; >=1: number of B frames */
XM_U32 u32RefNum; /* 0: default; number of refrence frame*/
}VENC_ATTR_H265_S;
typedef struct xmVENC_ATTR_MJPEG_S
{
XM_U32 u32MaxPicWidth; /*maximum width of a picture to be encoded, in pixel*/
XM_U32 u32MaxPicHeight; /*maximum height of a picture to be encoded, in pixel*/
XM_U32 u32BufSize; /*stream buffer size*/
XM_BOOL bByFrame; /*get stream mode is field mode or frame mode*/
XM_U32 u32PicWidth; /*width of a picture to be encoded, in pixel*/
XM_U32 u32PicHeight; /*height of a picture to be encoded, in pixel*/
}VENC_ATTR_MJPEG_S;
typedef struct xmVENC_ATTR_JPEG_S
{
XM_U32 u32MaxPicWidth; /*maximum width of a picture to be encoded, in pixel*/
XM_U32 u32MaxPicHeight; /*maximum height of a picture to be encoded, in pixel*/
XM_U32 u32BufSize; /*stream buffer size*/
XM_BOOL bByFrame; /*get stream mode is field mode or frame mode*/
XM_U32 u32PicWidth; /*width of a picture to be encoded, in pixel*/
XM_U32 u32PicHeight; /*height of a picture to be encoded, in pixel*/
XM_BOOL bSupportDCF; /*support dcf*/
}VENC_ATTR_JPEG_S;
/* attribute of MPEG4*/
typedef struct xmVENC_ATTR_MPEG4_S
{
XM_U32 u32MaxPicWidth; /*maximum width of a picture to be encoded, in pixel*/
XM_U32 u32MaxPicHeight; /*maximum height of a picture to be encoded, in pixel*/
XM_U32 u32BufSize; /*buffer size*/
XM_BOOL bByFrame; /*get stream mode is pack or frame*/
XM_U32 u32PicWidth; /*width of a picture to be encoded, in pixel*/
XM_U32 u32PicHeight; /*height of a picture to be encoded, in pixel*/
}VENC_ATTR_MPEG4_S;
typedef struct xmVENC_ATTR_S
{
PAYLOAD_TYPE_E enType; /*the type of payload*/
union
{
VENC_ATTR_H264_S stAttrH264e; /*attributes of h264*/
VENC_ATTR_MJPEG_S stAttrMjpeg; /*attributes of mjpeg*/
VENC_ATTR_JPEG_S stAttrJpeg; /*attributes of jpeg*/
VENC_ATTR_MPEG4_S stAttrMpeg4; /*attributes of mpeg4*/
VENC_ATTR_H265_S stAttrH265e; /*attributes of h265*/
};
}VENC_ATTR_S;
typedef struct xmVENC_CHN_ATTR_S
{
VENC_ATTR_S stVeAttr; /*the attribute of video encoder*/
VENC_RC_ATTR_S stRcAttr; /*the attribute of rate ctrl*/
}VENC_CHN_ATTR_S;
typedef struct xmJPEG_ENC_ATTR_S
{
int lumWidthSrc;//16对齐
int lumHeightSrc;//2对齐
int horOffsetSrc;//2对齐
int verOffsetSrc;//2对齐
int dstWidth;//>=96 4对齐
int dstHeight;//>=32 2对齐
}JPEG_ENC_ATTR_S;
/*vbr mode*/
typedef struct xmVENC_PARAM_REF_EX_S
{
XM_U8 bVirtualEnable; /*virtual I frame enable/disable*/
XM_U32 u32VirtualIInterval; /*virtual I frame interval*/
}VENC_PARAM_REF_EX_S;
typedef struct xmVENC_CHN_STAT_S
{
XM_U32 u32LeftPics; /*left picture number */
XM_U32 u32LeftStreamBytes; /*left stream bytes*/
XM_U32 u32LeftStreamFrames; /*left stream frames*/
XM_U32 u32CurPacks; /*pack number of current frame*/
XM_U32 u32LeftRecvPics; /*Number of frames to be received. This member is valid after HI_MPI_VENC_StartRecvPicEx is called.*/
XM_U32 u32LeftEncPics; /*Number of frames to be encoded. This member is valid after HI_MPI_VENC_StartRecvPicEx is called.*/
}VENC_CHN_STAT_S;
typedef struct xmVENC_PARAM_H264_SLICE_SPLIT_S
{
XM_BOOL bSplitEnable; /*slice split enable, XM_TRUE:enable, HI_FALSE:diable, default value:HI_FALSE*/
XM_U32 u32SplitMode; /*0:bit number, 1:mb line number, >=2:no meaning*/
XM_U32 u32SliceSize; /*when the splitmode is 0, this value presents the bitsnum of one slice average,
when the splitmode is 1, this value presents the mb num of one slice*/
} VENC_PARAM_H264_SLICE_SPLIT_S;
typedef struct xmVENC_PARAM_H264_INTER_PRED_S
{
/* search window */
XM_U32 u32HWSize; /* size of horizontal search window.
default value: differ with the picture size */
XM_U32 u32VWSize; /* size of vertical search window.
default value: differ with the picture size */
/* inter pred, one of the following 4 kinds of inter prediction mode must be enable */
XM_BOOL bInter16x16PredEn; /*default: XM_TRUE, enable 16x16 prediction*/
XM_BOOL bInter16x8PredEn; /*default: XM_TRUE*/
XM_BOOL bInter8x16PredEn; /*default: XM_TRUE*/
XM_BOOL bInter8x8PredEn; /*default: XM_TRUE*/
XM_BOOL bExtedgeEn; /*default: XM_TRUE*/
} VENC_PARAM_H264_INTER_PRED_S;
typedef struct xmVENC_PARAM_H264_INTRA_PRED_S
{
/* intra pred, one of following 2 kinds of intra pred mode must be enable */
XM_BOOL bIntra16x16PredEn; /*default: XM_TRUE, enable 16x16 intra prediction*/
XM_BOOL bIntraNxNPredEn; /*default: XM_TRUE, enable 4x4 and/or 8x8 prediction
Notes: this value must work with IntraTransMode*/
XM_U32 constrained_intra_pred_flag; /*default: HI_FALSE, see the H.264 protocol*/
XM_BOOL bIpcmEn; /*default: XM_TRUE, enable ipcm*/
}VENC_PARAM_H264_INTRA_PRED_S;
typedef struct xmVENC_PARAM_H264_TRANS_S
{
XM_U32 u32IntraTransMode; /* 0: trans4x4, trans8x8; 1: trans4x4, 2: trans8x8 */
XM_U32 u32InterTransMode; /* 0: trans4x4, trans8x8; 1: trans4x4, 2: trans8x8 */
XM_BOOL bScalingListValid; /* default: HI_FALSE */
/* Notes: Enable IntraScalingList8X8 and InterScalingList8X8 while bScalingListValid is XM_TRUE */
XM_U8 InterScalingList8X8[64];
XM_U8 IntraScalingList8X8[64];
XM_S32 chroma_qp_index_offset; /* [-12,12],default value: 0*/
}VENC_PARAM_H264_TRANS_S;
typedef struct xmVENC_PARAM_H264_ENTROPY_S
{
XM_U32 u32EntropyEncModeI; /* 0:cavlc, 1:cabac */
XM_U32 u32EntropyEncModeP; /* 0:cavlc, 1:cabac */
XM_U32 cabac_stuff_en; /* default: 0*/
XM_U32 Cabac_init_idc; /* 0~2 */
}VENC_PARAM_H264_ENTROPY_S;
typedef struct xmVENC_PARAM_H264_POC_S
{
XM_U32 pic_order_cnt_type; /* default value: 2. {0,1,2} */
}VENC_PARAM_H264_POC_S;
typedef struct xmVENC_PARAM_H264_DBLK_S
{
XM_U32 disable_deblocking_filter_idc; /* default value: 0. {0,1,2} */
XM_S32 slice_alpha_c0_offset_div2; /* default value: 5. [-6,+6] */
XM_S32 slice_beta_offset_div2; /* default value: 5. [-6,+6] */
}VENC_PARAM_H264_DBLK_S;
typedef struct xmVENC_PARAM_H264_VUI_TIME_INFO_S
{
XM_U8 timing_info_present_flag; /* default value: 0. If 1, timing info belows will be encoded into vui. {0,1} */
XM_U8 fixed_frame_rate_flag; /* default value: n/a. {0,1} */
XM_U32 num_units_in_tick; /* default value: n/a. > 0. */
XM_U32 time_scale; /* default value: n/a. > 0. */
}VENC_PARAM_VUI_H264_TIME_INFO_S;
typedef struct xmVENC_PARAM_VUI_ASPECT_RATIO_S
{
XM_U8 aspect_ratio_info_present_flag; /* default value: 0. If 1, aspectratio info belows will be encoded into vui. {0,1} */
XM_U8 aspect_ratio_idc; /* default value: n/a. [0,255],17~254 is reserved. */
XM_U8 overscan_info_present_flag; /* default value: 0,just be 0.If 1, oversacan info belows will be encoded into vui. {0,1} */
XM_U8 overscan_appropriate_flag; /* default value: n/a. */
XM_U16 sar_width; /* default value: n/a. sar_width and sar_height shall be relatively prime. */
XM_U16 sar_height ; /* default value: n/a. */
}VENC_PARAM_VUI_ASPECT_RATIO_S;
typedef struct xmVENC_PARAM_VUI_VIDEO_SIGNAL_S
{
XM_U8 video_signal_type_present_flag ; /* default value: 0. If 1, video singnal info will be encoded into vui. {0,1} */
XM_U8 video_format ; /* default value: n/a. >= 0. */
XM_U8 video_full_range_flag; /* default value: n/a. {0,1}. */
XM_U8 colour_description_present_flag ; /* default value: n/a. {0,1} */
XM_U8 colour_primaries ; /* default value: n/a. [0,255],0/9~255 is reserved */
XM_U8 transfer_characteristics; /* default value: n/a. [0,255],0/13~255 is reserved */
XM_U8 matrix_coefficients; /* default value: n/a. [0,255],9~255 is reserved */
}VENC_PARAM_VUI_VIDEO_SIGNAL_S;
typedef struct xmVENC_PARAM_H264_VUI_S
{
VENC_PARAM_VUI_ASPECT_RATIO_S stVuiAspectRatio;
VENC_PARAM_VUI_H264_TIME_INFO_S stVuiTimeInfo;
VENC_PARAM_VUI_VIDEO_SIGNAL_S stVuiVideoSignal;
}VENC_PARAM_H264_VUI_S;
typedef struct xmVENC_PARAM_JPEG_S
{
XM_U32 u32Qfactor; /*image quality :[1,99]*/
XM_U8 u8YQt[64]; /* y qt value */
XM_U8 u8CbQt[64]; /* cb qt value */
XM_U8 u8CrQt[64]; /* cr qt value */
XM_U32 u32MCUPerECS; /*default value: 0, MCU number of one ECS*/
} VENC_PARAM_JPEG_S;
typedef struct xmVENC_PARAM_MJPEG_S
{
XM_U8 u8YQt[64]; /* y qt value */
XM_U8 u8CbQt[64]; /* cb qt value */
XM_U8 u8CrQt[64]; /* cr qt value */
XM_U32 u32MCUPerECS; /*default value: 0, MCU number of one ECS*/
} VENC_PARAM_MJPEG_S;
typedef struct xmVENC_PARAM_MPEG4_S
{
XM_BOOL bSplitEnable; /*slice split enable, XM_TRUE:enable, HI_FALSE:diable, default value:HI_FALSE*/
XM_U32 u32SplitMode; /*0:bit number, 1:mb line number, >=2:no meaning*/
XM_U32 u32PacketSize; /*when the splitmode is 0, this value presents the bitsnum of one packet average,
when the splitmode is 1, this value presents the mb num of one packet*/
/* search window */
XM_U32 u32HWSize; /* size of horizontal search window.
* default value: differ with the picture size
* 0000: [-16, +15]
* 0001: [-32, +31]
*/
XM_U32 u32VWSize; /* size of vertical search window.
* default value: differ with the picture size
* 000: [-16, +15]
* >000: no meaning.
*/
} VENC_PARAM_MPEG4_S;
/* ROI struct */
typedef struct xmVENC_ROI_CFG_S
{
XM_U32 u32Index; /* Index of an ROI. The system supports indexes ranging from 0 to 7 */
XM_BOOL bEnable; /* Whether to enable this ROI */
XM_BOOL bAbsQp; /* QP mode of an ROI.HI_FALSE: relative QP.HI_TURE: absolute QP.*/
XM_S32 s32Qp; /* QP value. */
RECT_S stRect; /* Region of an ROI*/
}VENC_ROI_CFG_S;
typedef struct xmVENC_ROIBG_FRAME_RATE_S
{
XM_S32 s32SrcFrmRate; /* Input frame rate of Roi backgroud*/
XM_S32 s32DstFrmRate; /* Output frame rate of Roi backgroud */
}VENC_ROIBG_FRAME_RATE_S;
typedef struct xmVENC_COLOR2GREY_S
{
XM_BOOL bColor2Grey; /* Whether to enable Color2Grey.*/
}VENC_COLOR2GREY_S;
typedef struct xmVENC_CROP_CFG_S
{
XM_BOOL bEnable; /* Crop region enable */
RECT_S stRect; /* Crop region, note: s32X must be multi of 16 */
}VENC_CROP_CFG_S;
typedef struct xmVENC_FRAME_RATE_S
{
XM_S32 s32SrcFrmRate; /* Input frame rate of a channel*/
XM_S32 s32DstFrmRate; /* Output frame rate of a channel*/
} VENC_FRAME_RATE_S;
typedef struct xmVENC_PARAM_REF_S
{
XM_U32 u32Base; /*Base layer period*/
XM_U32 u32Enhance; /*Enhance layer period*/
XM_BOOL bEnablePred; /*Whether some frames at the base layer are referenced by other frames at the base layer. When bEnablePred is HI_FALSE, all frames at the base layer reference IDR frames.*/
} VENC_PARAM_REF_S;
typedef enum xmH264E_IDR_PIC_ID_MODE_E
{
H264E_IDR_PIC_ID_MODE_AUTO = 0, /*auto mode */
H264E_IDR_PIC_ID_MODE_USR, /*user mode */
H264E_IDR_PIC_ID_MODE_BUTT,
}H264E_IDR_PIC_ID_MODE_E;
typedef struct xmVENC_H264_IDRPICID_CFG_S
{
H264E_IDR_PIC_ID_MODE_E enH264eIdrPicIdMode; /*the mode of idr_pic_id that is set*/
XM_U32 u32H264eIdrPicId; /*idr_pic_id value*/
} VENC_H264_IDRPICID_CFG_S;
/* Jpeg snap mode */
typedef enum xmVENC_JPEG_SNAP_MODE_E
{
JPEG_SNAP_ALL = 0, /* Jpeg channel snap all the pictures when started. */
JPEG_SNAP_FLASH = 1, /* Jpeg channel snap the flashed pictures when started. */
JPEG_SNAP_BUTT,
}VENC_JPEG_SNAP_MODE_E;
typedef struct xmVENC_RECV_PIC_PARAM_S
{
XM_S32 s32RecvPicNum; /*Number of frames received and encoded by the encoding channel*/
} VENC_RECV_PIC_PARAM_S;
typedef struct xmVENC_STREAM_BUF_INFO_S
{
XM_U32 u32PhyAddr;
XM_VOID *pUserAddr;
XM_U32 u32BufSize;
} VENC_STREAM_BUF_INFO_S;
typedef struct xmVENC_CHN_PARAM_S
{
XM_U32 u32QuarterPixelMv;
XM_U32 u32MinIQp;
}VENC_CHN_PARAM_S;
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /* __XM_COMM_VENC_H__ */

497
general/package/xiongmai-osdrv-xm530/files/include/xm_comm_vi.h
View File

@ -1,497 +0,0 @@
/******************************************************************************
Copyright (C), 2004-2020, XM Tech. Co., Ltd.
******************************************************************************
File Name : xm_comm_vi.h
Version : Initial Draft
Author : XM multimedia software group
Created : 2015/9/17
Last Modified :
Description :
Function List :
******************************************************************************/
#ifndef __XM_COMM_VI_H__
#define __XM_COMM_VI_H__
#include "xm_common.h"
#include "xm_errno.h"
#include "xm_comm_video.h"
#ifdef __cplusplus
#if __cplusplus
extern "C"
{
#endif
#endif /* __cplusplus */
#define VI_INVALID_FRMRATE (-1UL)
#define VIU_MAX_USER_FRAME_DEPTH 8
/*get the subchn index by main chn */
#define SUBCHN(ViChn) (ViChn + 16)
/* define cascade chn */
#define VI_CAS_CHN_1 32
#define VI_CAS_CHN_2 33
#define XM_TRACE_VI(level, fmt...) XM_TRACE(level, XM_ID_VIU,##fmt)
#define XM_ERR_VI_INVALID_PARA XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, EN_ERR_ILLEGAL_PARAM)
#define XM_ERR_VI_INVALID_DEVID XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_DEVID)
#define XM_ERR_VI_INVALID_CHNID XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_CHNID)
#define XM_ERR_VI_INVALID_NULL_PTR XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, EN_ERR_NULL_PTR)
#define XM_ERR_VI_FAILED_NOTCONFIG XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_CONFIG)
#define XM_ERR_VI_SYS_NOTREADY XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, EN_ERR_SYS_NOTREADY)
#define XM_ERR_VI_BUF_EMPTY XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_EMPTY)
#define XM_ERR_VI_BUF_FULL XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, EN_ERR_BUF_FULL)
#define XM_ERR_VI_NOMEM XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, EN_ERR_NOMEM)
#define XM_ERR_VI_NOT_SUPPORT XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_SUPPORT)
#define XM_ERR_VI_BUSY XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, EN_ERR_BUSY)
#define XM_ERR_VI_NOT_PERM XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_PERM)
enum
{
ERR_VI_FAILED_NOTENABLE = 0x40,
ERR_VI_FAILED_NOTDISABLE = 0x41,
ERR_VI_FAILED_CHNOTDISABLE = 0x42,
ERR_VI_CFG_TIMEOUT = 0x43,
ERR_VI_NORM_UNMATCH = 0x44,
ERR_VI_INVALID_WAYID = 0x45,
ERR_VI_INVALID_PHYCHNID = 0x46,
ERR_VI_FAILED_NOTBIND = 0x47,
ERR_VI_FAILED_BINDED = 0x48
};
#define XM_ERR_VI_FAILED_NOTENABLE XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, ERR_VI_FAILED_NOTENABLE)/* 0xA0108040*/
#define XM_ERR_VI_FAILED_NOTDISABLE XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, ERR_VI_FAILED_NOTDISABLE)/* 0xA0108041*/
#define XM_ERR_VI_FAILED_CHNOTDISABLE XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, ERR_VI_FAILED_CHNOTDISABLE)/* 0xA0108042*/
#define XM_ERR_VI_CFG_TIMEOUT XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, ERR_VI_CFG_TIMEOUT)/* 0xA0108043*/
#define XM_ERR_VI_NORM_UNMATCH XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, ERR_VI_NORM_UNMATCH)/* 0xA0108044*/
#define XM_ERR_VI_INVALID_WAYID XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, ERR_VI_INVALID_WAYID)/* 0xA0108045*/
#define XM_ERR_VI_INVALID_PHYCHNID XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, ERR_VI_INVALID_PHYCHNID)/* 0xA0108046*/
#define XM_ERR_VI_FAILED_NOTBIND XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, ERR_VI_FAILED_NOTBIND)/* 0xA0108047*/
#define XM_ERR_VI_FAILED_BINDED XM_DEF_ERR(XM_ID_VIU, EN_ERR_LEVEL_ERROR, ERR_VI_FAILED_BINDED)/* 0xA0108048*/
/* interface mode of video input */
typedef enum xmVI_INTF_MODE_E
{
VI_MODE_BT656 = 0, /* ITU-R BT.656 YUV4:2:2 */
VI_MODE_BT601, /* ITU-R BT.601 YUV4:2:2 */
VI_MODE_DIGITAL_CAMERA, /* digatal camera mode */
VI_MODE_BT1120_STANDARD, /* BT.1120 progressive mode */
VI_MODE_BT1120_INTERLEAVED, /* BT.1120 interstage mode */
VI_MODE_BUTT
} VI_INTF_MODE_E;
/* Input mode */
typedef enum xmVI_INPUT_MODE_E
{
VI_INPUT_MODE_BT656 = 0, /* ITU-R BT.656 YUV4:2:2 */
VI_INPUT_MODE_BT601, /* ITU-R BT.601 YUV4:2:2 */
VI_INPUT_MODE_DIGITAL_CAMERA, /* digatal camera mode */
VI_INPUT_MODE_INTERLEAVED,
VI_INPUT_MODE_BUTT
} VI_INPUT_MODE_E;
typedef enum xmVI_WORK_MODE_E
{
VI_WORK_MODE_1Multiplex = 0, /* 1 Multiplex mode */
VI_WORK_MODE_2Multiplex, /* 2 Multiplex mode */
VI_WORK_MODE_4Multiplex, /* 4 Multiplex mode */
VI_WORK_MODE_BUTT
} VI_WORK_MODE_E;
/* whether an input picture is interlaced or progressive */
typedef enum xmVI_SCAN_MODE_E
{
VI_SCAN_INTERLACED = 0,
VI_SCAN_PROGRESSIVE,
VI_SCAN_BUTT,
} VI_SCAN_MODE_E;
typedef enum xmVI_DATA_YUV_SEQ_E
{
/*The input sequence of the second component(only contains u and v) in BT.1120 mode */
VI_INPUT_DATA_VUVU = 0,
VI_INPUT_DATA_UVUV,
/* The input sequence for yuv */
VI_INPUT_DATA_UYVY = 0,
VI_INPUT_DATA_VYUY,
VI_INPUT_DATA_YUYV,
VI_INPUT_DATA_YVYU,
VI_DATA_YUV_BUTT
} VI_DATA_YUV_SEQ_E;
typedef enum xmVI_CLK_EDGE_E
{
VI_CLK_EDGE_SINGLE_UP = 0, /* single-edge mode and in rising edge */
VI_CLK_EDGE_SINGLE_DOWN, /* single-edge mode and in falling edge */
//VI_CLK_EDGE_DOUBLE , /* Double edge mode */
VI_CLK_EDGE_BUTT
} VI_CLK_EDGE_E;
typedef enum xmVI_COMP_MODE_E
{
VI_COMP_MODE_SINGLE = 0, /* in single component mode */
VI_COMP_MODE_DOUBLE = 1, /* in double component mode */
VI_COMP_MODE_BUTT,
}VI_COMP_MODE_E;
/* Y/C composite or separation mode */
typedef enum xmVI_COMBINE_MODE_E
{
VI_COMBINE_COMPOSITE = 0, /* Composite mode */
VI_COMBINE_SEPARATE, /* Separate mode */
VI_COMBINE_BUTT,
} VI_COMBINE_MODE_E;
/* Attribute of the vertical synchronization signal */
typedef enum xmVI_VSYNC_E
{
VI_VSYNC_FIELD = 0, /* Field/toggle mode:a signal reversal means a new frame or a field */
VI_VSYNC_PULSE, /* Pusle/effective mode:a pusle or an effective signal means a new frame or a field */
} VI_VSYNC_E;
/* Polarity of the vertical synchronization signal */
typedef enum xmVI_VSYNC_NEG_E
{
VI_VSYNC_NEG_HIGH = 0, /*if VIU_VSYNC_E = VIU_VSYNC_FIELD,then the vertical synchronization signal of even field is high-level,
if VIU_VSYNC_E = VIU_VSYNC_PULSE,then the vertical synchronization pulse is positive pulse.*/
VI_VSYNC_NEG_LOW /*if VIU_VSYNC_E = VIU_VSYNC_FIELD,then the vertical synchronization signal of even field is low-level,
if VIU_VSYNC_E = VIU_VSYNC_PULSE,then the vertical synchronization pulse is negative pulse.*/
} VI_VSYNC_NEG_E;
/* Attribute of the horizontal synchronization signal */
typedef enum xmVI_HSYNC_E
{
VI_HSYNC_VALID_SINGNAL = 0, /* the horizontal synchronization is valid signal mode */
VI_HSYNC_PULSE, /* the horizontal synchronization is pulse mode, a new pulse means the beginning of a new line */
} VI_HSYNC_E;
/* Polarity of the horizontal synchronization signal */
typedef enum xmVI_HSYNC_NEG_E
{
VI_HSYNC_NEG_HIGH = 0, /*if VI_HSYNC_E = VI_HSYNC_VALID_SINGNAL,then the valid horizontal synchronization signal is high-level;
if VI_HSYNC_E = VI_HSYNC_PULSE,then the horizontal synchronization pulse is positive pulse */
VI_HSYNC_NEG_LOW /*if VI_HSYNC_E = VI_HSYNC_VALID_SINGNAL,then the valid horizontal synchronization signal is low-level;
if VI_HSYNC_E = VI_HSYNC_PULSE,then the horizontal synchronization pulse is negative pulse */
} VI_HSYNC_NEG_E;
/* Attribute of the valid vertical synchronization signal */
typedef enum xmVI_VSYNC_VALID_E
{
VI_VSYNC_NORM_PULSE = 0, /* the vertical synchronization is pusle mode, a pusle means a new frame or field */
VI_VSYNC_VALID_SINGAL, /* the vertical synchronization is effective mode, a effective signal means a new frame or field */
} VI_VSYNC_VALID_E;
/* Polarity of the valid vertical synchronization signal */
typedef enum xmVI_VSYNC_VALID_NEG_E
{
VI_VSYNC_VALID_NEG_HIGH = 0, /*if VI_VSYNC_VALID_E = VI_VSYNC_NORM_PULSE,a positive pulse means vertical synchronization pulse;
if VI_VSYNC_VALID_E = VI_VSYNC_VALID_SINGAL,the valid vertical synchronization signal is high-level */
VI_VSYNC_VALID_NEG_LOW /*if VI_VSYNC_VALID_E = VI_VSYNC_NORM_PULSE,a negative pulse means vertical synchronization pulse;
if VI_VSYNC_VALID_E = VI_VSYNC_VALID_SINGAL,the valid vertical synchronization signal is low-level */
} VI_VSYNC_VALID_NEG_E;
/* Blank information of the input timing */
typedef struct xmVI_TIMING_BLANK_S
{
XM_U32 u32HsyncHfb ; /* Horizontal front blanking width */
XM_U32 u32HsyncAct ; /* Horizontal effetive width */
XM_U32 u32HsyncHbb ; /* Horizontal back blanking width */
XM_U32 u32VsyncVfb ; /* Vertical front blanking height of one frame or odd-field frame picture */
XM_U32 u32VsyncVact ; /* Vertical effetive width of one frame or odd-field frame picture */
XM_U32 u32VsyncVbb ; /* Vertical back blanking height of one frame or odd-field frame picture */
XM_U32 u32VsyncVbfb ; /* Even-field vertical front blanking height when input mode is interlace (invalid when progressive input mode) */
XM_U32 u32VsyncVbact ; /* Even-field vertical effetive width when input mode is interlace (invalid when progressive input mode) */
XM_U32 u32VsyncVbbb ; /* Even-field vertical back blanking height when input mode is interlace (invalid when progressive input mode) */
}VI_TIMING_BLANK_S;
/* synchronization information about the BT.601 or DC timing */
typedef struct xmVI_SYNC_CFG_S
{
VI_VSYNC_E enVsync;
VI_VSYNC_NEG_E enVsyncNeg;
VI_HSYNC_E enHsync;
VI_HSYNC_NEG_E enHsyncNeg;
VI_VSYNC_VALID_E enVsyncValid;
VI_VSYNC_VALID_NEG_E enVsyncValidNeg;
VI_TIMING_BLANK_S stTimingBlank;
} VI_SYNC_CFG_S;
/* the highest bit of the BT.656 timing reference code*/
typedef enum xmBT656_FIXCODE_E
{
BT656_FIXCODE_1 = 0, /* The highest bit of the EAV/SAV data over the BT.656 protocol is always 1.*/
BT656_FIXCODE_0 /* The highest bit of the EAV/SAV data over the BT.656 protocol is always 0.*/
}BT656_FIXCODE_E;
/* Polarity of the field indicator bit (F) of the BT.656 timing reference code */
typedef enum xmBT656_FIELD_POLAR_E
{
BT656_FIELD_POLAR_STD = 0, /* the standard BT.656 mode,the first filed F=0,the second filed F=1*/
BT656_FIELD_POLAR_NSTD /* the non-standard BT.656 mode,the first filed F=1,the second filed F=0*/
}BT656_FIELD_POLAR_E;
typedef struct xmVI_BT656_SYNC_CFG_S
{
BT656_FIXCODE_E enFixCode;
BT656_FIELD_POLAR_E enFieldPolar;
}VI_BT656_SYNC_CFG_S;
typedef enum xmVI_VBI_LOCAL_E
{
VI_VBI_LOCAL_ODD_FRONT = 0,
VI_VBI_LOCAL_ODD_END,
VI_VBI_LOCAL_EVEN_FRONT,
VI_VBI_LOCAL_EVEN_END,
VI_VBI_LOCAL_BUTT
} VI_VBI_LOCAL_E;
typedef struct xmVI_VBI_ATTR_S
{
VI_VBI_LOCAL_E enLocal; /* location of VBI */
XM_S32 s32X; /* horizontal original position of the VBI data */
XM_S32 s32Y; /* vertical original position of the VBI data */
XM_U32 u32Len; /* length of VBI data, by word(4 Bytes) */
} VI_VBI_ATTR_S;
typedef enum xmVI_DATA_TYPE_E
{
VI_DATA_TYPE_YUV = 0,
VI_DATA_TYPE_RGB = 1,
VI_DATA_TYPE_BUTT
} VI_DATA_TYPE_E;
typedef enum xmVI_DATA_PATH_E
{
VI_PATH_BYPASS = 0, /* ISP bypass */
VI_PATH_ISP = 1, /* ISP enable */
VI_PATH_RAW = 2, /* Capture raw data, for debug */
VI_PATH_BUTT
}VI_DATA_PATH_E;
/* the extended attributes of VI device */
typedef struct xmVI_DEV_ATTR_EX_S
{
VI_INPUT_MODE_E enInputMode; /* Input mode */
VI_WORK_MODE_E enWorkMode; /*1-, 2-, or 4-channel multiplexed work mode */
VI_COMBINE_MODE_E enCombineMode; /* Y/C composite or separation mode */
VI_COMP_MODE_E enCompMode; /* Component mode (single-component or dual-component) */
VI_CLK_EDGE_E enClkEdge; /* Clock edge mode (sampling on the rising or falling edge) */
XM_U32 au32CompMask[2]; /* Component mask */
VI_SCAN_MODE_E enScanMode; /* Input scanning mode (progressive or interlaced) */
XM_S32 s32AdChnId[4]; /* AD channel ID. Typically, the default value -1 is recommended */
VI_DATA_YUV_SEQ_E enDataSeq; /* Input data sequence (only the YUV format is supported) */
VI_SYNC_CFG_S stSynCfg; /* Sync timing. This member must be configured in BT.601 mode or DC mode */
VI_BT656_SYNC_CFG_S stBT656SynCfg; /* Sync timing. This member must be configured in BT.656 mode */
VI_DATA_PATH_E enDataPath; /* ISP enable or bypass */
VI_DATA_TYPE_E enInputDataType; /* RGB: CSC-709 or CSC-601, PT YUV444 disable; YUV: default yuv CSC coef PT YUV444 enable. */
XM_BOOL bDataRev; /* Data reverse */
} VI_DEV_ATTR_EX_S;
/* the attributes of a VI device */
typedef struct xmVI_DEV_ATTR_S
{
VI_INTF_MODE_E enIntfMode; /* Interface mode */
VI_WORK_MODE_E enWorkMode; /*1-, 2-, or 4-channel multiplexed work mode */
XM_U32 au32CompMask[2]; /* Component mask */
VI_SCAN_MODE_E enScanMode; /* Input scanning mode (progressive or interlaced) */
XM_S32 s32AdChnId[4]; /* AD channel ID. Typically, the default value -1 is recommended */
/* The below members must be configured in BT.601 mode or DC mode and are invalid in other modes */
VI_DATA_YUV_SEQ_E enDataSeq; /* Input data sequence (only the YUV format is supported) */
VI_SYNC_CFG_S stSynCfg; /* Sync timing. This member must be configured in BT.601 mode or DC mode */
VI_DATA_PATH_E enDataPath; /* ISP enable or bypass */
VI_DATA_TYPE_E enInputDataType; /* RGB: CSC-709 or CSC-601, PT YUV444 disable; YUV: default yuv CSC coef PT YUV444 enable. */
XM_BOOL bDataRev; /* Data reverse */
} VI_DEV_ATTR_S;
typedef struct xmVI_CHN_BIND_ATTR_S
{
VI_DEV ViDev;
VI_WAY ViWay;
} VI_CHN_BIND_ATTR_S;
/* the attributes of a VI way */
typedef struct xmVI_WAY_ATTR_S
{
XM_S32 s32AdChnId;
} VI_WAY_ATTR_S;
/* captrue selection of video input */
typedef enum xmVI_CAPSEL_E
{
VI_CAPSEL_TOP = 0, /* top field */
VI_CAPSEL_BOTTOM, /* bottom field */
VI_CAPSEL_BOTH, /* top and bottom field */
VI_CAPSEL_BUTT
} VI_CAPSEL_E;
/* the attributes of a VI channel */
typedef struct xmVI_CHN_ATTR_S
{
RECT_S stCapRect; /* the capture rect (corresponding to the size of the picture captured by a VI device).
For primary channels, the stCapRect's u32Width and u32Height are static attributes. That is,
the value of them can be changed only after primary and secondary channels are disabled.
For secondary channels, stCapRect is an invalid attribute */
SIZE_S stDestSize; /* Target picture size.
For primary channels, stDestSize must be equal to stCapRect's u32Width and u32Height,
because primary channel doesn't have scale capability. Additionally, it is a static
attribute, That is, the value of stDestSize can be changed only after primary and
secondary channels are disabled.
For secondary channels, stDestSize is a dynamic attribute */
VI_CAPSEL_E enCapSel; /* Frame/field select. It is used only in interlaced mode.
For primary channels, enCapSel is a static attribute */
PIXEL_FORMAT_E enPixFormat; /* Pixel storage format. Only the formats semi-planar420 and semi-planar422 are supported */
XM_BOOL bMirror; /* Whether to mirror */
XM_BOOL bFlip; /* Whether to flip */
XM_BOOL bChromaResample; /* Whether to perform chrominance resampling. It is valid only for primary channels */
XM_S32 s32SrcFrameRate; /* Source frame rate. The value -1 indicates that the frame rate is not controlled */
XM_S32 s32FrameRate; /* Target frame rate. The value -1 indicates that the frame rate is not controlled */
} VI_CHN_ATTR_S;
typedef struct xmVI_CHN_STAT_S
{
XM_BOOL bEnable; /* Whether this channel is enabled */
XM_U32 u32IntCnt; /* The video frame interrupt count */
XM_U32 u32FrmRate; /* current frame rate */
XM_U32 u32LostInt; /* The interrupt is received but nobody care */
XM_U32 u32VbFail; /* Video buffer malloc failure */
XM_U32 u32PicWidth; /* curren pic width */
XM_U32 u32PicHeight; /* current pic height */
XM_U32 u32AutoDisInt; /* auto disable interrupt count, when VIU detected too many interrupts */
} VI_CHN_STAT_S;
typedef enum xm_VI_USERPIC_MODE_E
{
VI_USERPIC_MODE_PIC = 0, /* YUV picture */
VI_USERPIC_MODE_BGC, /* Background picture only with a color */
VI_USERPIC_MODE_BUTT,
} VI_USERPIC_MODE_E;
typedef struct xmVI_USERPIC_BGC_S
{
XM_U32 u32BgColor;
} VI_USERPIC_BGC_S;
typedef struct xmVI_USERPIC_ATTR_S
{
XM_BOOL bPub; /* Whether the user picture information is shared by all VI devices and channels*/
VI_USERPIC_MODE_E enUsrPicMode; /* User picture mode */
union
{
VIDEO_FRAME_INFO_S stUsrPicFrm; /* Information about a YUV picture */
VI_USERPIC_BGC_S stUsrPicBg; /* Information about a background picture only with a color */
}unUsrPic;
} VI_USERPIC_ATTR_S;
typedef struct xmVI_USR_GET_FRM_TIMEOUT_S
{
VIDEO_FRAME_INFO_S *pstVFrame;
XM_U32 u32MilliSec;
} VI_USR_GET_FRM_TIMEOUT_S;
typedef enum xmVI_FLASH_MODE_E
{
VI_FLASH_ONCE = 0, /* Flash one time */
VI_FLASH_FREQ = 1, /* Flash frequently */
VI_FLASH_MODE_BUTT
}VI_FLASH_MODE_E;
typedef struct xmVI_FlASH_CONFIG_S
{
VI_FLASH_MODE_E enFlashMode; /* Flash one time, flash frequently*/
XM_U32 u32StartTime; /* Flash start time£¬unit: sensor pix clk.*/
XM_U32 u32Duration; /* Flash high duration, unit: sensor pix clk.*/
XM_U32 u32CapFrmIndex; /* Set which vframe will be bFlashed after flashing, default is 0. */
XM_U32 u32Interval; /* Flash frequently interval, unit: frame*/
}VI_FLASH_CONFIG_S;
typedef struct xmVI_EXT_CHN_ATTR_S
{
VI_CHN s32BindChn; /* The channel num which extend channel will bind to*/
SIZE_S stDestSize; /* Target size*/
XM_S32 s32SrcFrameRate; /* Source frame rate. The value -1 indicates that the frame rate is not controlled */
XM_S32 s32FrameRate; /* Target frame rate. The value -1 indicates that the frame rate is not controlled */
PIXEL_FORMAT_E enPixFormat; /* Pixel storage format. Only the formats semi-planar420 and semi-planar422 are supported */
}VI_EXT_CHN_ATTR_S;
typedef struct xmVI_LDC_ATTR_S
{
XM_BOOL bEnable; /* Whether LDC is enbale */
LDC_ATTR_S stAttr; /* LDC Attribute */
}VI_LDC_ATTR_S;
typedef struct xmVI_CHN_LUM_S
{
XM_U32 u32Lum; /* Luma sum of current frame */
XM_U64 u64Pts; /* PTS of current frame */
} VI_CHN_LUM_S;
typedef enum xmVI_CSC_TYPE_E
{
VI_CSC_TYPE_601 = 0, /* CSC Type: 601 */
VI_CSC_TYPE_709, /* CSC Type: 709 */
VI_CSC_TYPE_BUTT,
} VI_CSC_TYPE_E;
typedef struct xmVI_CSC_ATTR_S
{
VI_CSC_TYPE_E enViCscType; /* 601 or 709 */
XM_U32 u32LumaVal; /* Luminance: [0 ~ 100] */
XM_U32 u32ContrVal; /* Contrast: [0 ~ 100] */
XM_U32 u32HueVal; /* Hue: [0 ~ 100] */
XM_U32 u32SatuVal; /* Satuature: [0 ~ 100] */
} VI_CSC_ATTR_S;
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /* End of #ifndef__XM_COMM_VIDEO_IN_H__ */

308
general/package/xiongmai-osdrv-xm530/files/include/xm_comm_video.h
View File

@ -1,308 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm_common_video.h
Version : Initial Draft
Author : XM Isp software group
Created : 2015/6/27
Description : The common data type defination
Function List :
History :
1.Date : 2015/6/27
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef __XM_COMM_VIDEO_H__
#define __XM_COMM_VIDEO_H__
#include "xm_type.h"
#include "xm_common.h"
typedef enum xm_PIC_SIZE_E
{
PIC_QCIF = 0,
PIC_CIF,
PIC_2CIF,
PIC_HD1,
PIC_D1,
PIC_960H,
PIC_QVGA, /* 320 * 240 */
PIC_VGA, /* 640 * 480 */
PIC_XGA, /* 1024 * 768 */
PIC_SXGA, /* 1400 * 1050 */
PIC_UXGA, /* 1600 * 1200 */
PIC_QXGA, /* 2048 * 1536 */
PIC_WVGA, /* 854 * 480 */
PIC_WSXGA, /* 1680 * 1050 */
PIC_WUXGA, /* 1920 * 1200 */
PIC_WQXGA, /* 2560 * 1600 */
PIC_HD720, /* 1280 * 720 */
PIC_HD1080, /* 1920 * 1080 */
PIC_BUTT
}PIC_SIZE_E;
typedef enum xm_VIDEO_NORM_E
{
VIDEO_ENCODING_MODE_PAL=0,
VIDEO_ENCODING_MODE_NTSC,
VIDEO_ENCODING_MODE_AUTO,
VIDEO_ENCODING_MODE_BUTT
} VIDEO_NORM_E;
typedef enum xm_VIDEO_CONTROL_MODE_E
{
VIDEO_CONTROL_MODE_SLAVER=0,
VIDEO_CONTROL_MODE_MASTER,
VIDEO_CONTROL_MODE_BUTT
}VIDEO_CONTROL_MODE_E;
/* we ONLY define picture format used, all unused will be deleted!*/
typedef enum xm_PIXEL_FORMAT_E
{
PIXEL_FORMAT_RGB_1BPP = 0,
PIXEL_FORMAT_RGB_2BPP,
PIXEL_FORMAT_RGB_4BPP,
PIXEL_FORMAT_RGB_8BPP,
PIXEL_FORMAT_RGB_444,
PIXEL_FORMAT_RGB_4444,
PIXEL_FORMAT_RGB_555,
PIXEL_FORMAT_RGB_565,
PIXEL_FORMAT_RGB_1555,
/* 9 reserved */
PIXEL_FORMAT_RGB_888,
PIXEL_FORMAT_RGB_8888,
PIXEL_FORMAT_RGB_PLANAR_888,
PIXEL_FORMAT_RGB_BAYER,
PIXEL_FORMAT_YUV_A422,
PIXEL_FORMAT_YUV_A444,
PIXEL_FORMAT_YUV_PLANAR_422,
PIXEL_FORMAT_YUV_PLANAR_420,
PIXEL_FORMAT_YUV_PLANAR_444,
PIXEL_FORMAT_YUV_SEMIPLANAR_422,
PIXEL_FORMAT_YUV_SEMIPLANAR_420,
PIXEL_FORMAT_YUV_SEMIPLANAR_444,
PIXEL_FORMAT_UYVY_PACKAGE_422,
PIXEL_FORMAT_YUYV_PACKAGE_422,
PIXEL_FORMAT_VYUY_PACKAGE_422,
PIXEL_FORMAT_YCbCr_PLANAR,
PIXEL_FORMAT_RGB_422,
PIXEL_FORMAT_RGB_420,
PIXEL_FORMAT_BUTT
} PIXEL_FORMAT_E;
typedef enum xm_VIDEO_FIELD_E
{
VIDEO_FIELD_TOP = 0x01, /* even field */
VIDEO_FIELD_BOTTOM = 0x02, /* odd field */
VIDEO_FIELD_INTERLACED = 0x03, /* two interlaced fields */
VIDEO_FIELD_FRAME = 0x04, /* frame */
VIDEO_FIELD_BUTT
} VIDEO_FIELD_E;
typedef struct xm_VIDEO_FRAME_S
{
XM_U32 u32Width;
XM_U32 u32Height;
VIDEO_FIELD_E u32Field;
PIXEL_FORMAT_E enPixelFormat;
XM_U32 u32PhyAddr[3];
XM_VOID *pVirAddr[3];
XM_U32 u32Stride[3];
XM_U16 u16OffsetTop; /* top offset of show area */
XM_U16 u16OffsetBottom; /* bottom offset of show area */
XM_U16 u16OffsetLeft; /* left offset of show area */
XM_U16 u16OffsetRight; /* right offset of show area */
XM_U64 u64pts;
XM_U32 u32TimeRef;
XM_U32 u32PrivateData;
//VIDEO_VBI_INFO_S astVbiInfo[VIU_MAX_VBI_NUM];
}VIDEO_FRAME_S;
typedef struct xm_VIDEO_FRAME_INFO_S
{
VIDEO_FRAME_S stVFrame;
XM_U32 u32PoolId;
} VIDEO_FRAME_INFO_S;
typedef struct xmBITMAP_S
{
XM_U32 u32Handle;
XM_U32 u32Width;
XM_U32 u32Height;
XM_U32 u32Format;
XM_VOID *pData;
} BITMAP_S;
typedef struct XM_VPP_CFG_S
{
XM_BOOL bVppEn;
XM_BOOL bIeEn;
XM_BOOL bDnEn;
XM_BOOL bSpEn;
XM_BOOL bIencEn;
XM_S32 s32IeSth; /* IE Strength [0,10] */
XM_S32 s32SpSth; /* SP Strength [-4,5] */
XM_S32 s32DnSfCosSth; /* coarse DN sf Strength [0,3] */
XM_S32 s32DnSfIncSth; /* Inching of DN sf Strength [0,255] */
XM_S32 s32DnTfSth; /* DN tf Strength [0,4] */
} VPP_CFG_S;
typedef struct xm_SCALE_CFG_S
{
XM_BOOL bScaleEn;
XM_S32 s32DstWidth; /* the dest width after scale */
XM_S32 s32DstHeight; /* the dest height after scale */
} SCALE_CFG_S;
/* Ie */
typedef struct XM_VPP_IE_EX_S
{
XM_U32 u32RefRange;//
XM_U32 u32IeStrength;//
XM_U32 u32Black;
XM_U32 u32White;
} VPP_IE_EX_S;
/*dn*/
typedef struct
{
XM_U16 saMask[2];
XM_U16 weight[2];
} tVppCalcWnd;
typedef struct
{
XM_U8 wWndX, hWndX;
XM_U8 wWndY, hWndY;
XM_U8 wWndC, hWndC;
XM_U8 wWndD, hWndD; //
XM_U16 sfyMask[2];
XM_U8 sfyRange[2]; //
XM_U8 sfyStrength; //
XM_U8 sfyLimitedFlag; //
XM_U8 MADpExDirectSub : 1;
XM_U8 MADpExMask : 4;
XM_U8 _reserved_ : 3;
XM_U8 sfcStrength;
XM_U8 sfyMADpThresh, sfyMADpRate;/**/
XM_U16 sfyMSEiThresh[8];
XM_U8 rsfyThresh, rsfyRate, rsfyStrength, tfyStrength;
XM_U8 rsfcThresh, rsfcRate, rsfcStrength, tfcStrength;/**/
XM_U8 tfyMADpThresh, tfyMADpRate;
XM_U8 tfySNRpThresh, tfySNRpRate;
XM_U16 tfyMSEiThresh[8];
XM_U16 tfyMSEpThresh[8];
XM_U8 tfyMaxStrength;//
XM_U8 tfcMaxStrength;/**/
XM_U8 tfcMADpThresh, tfcMADpRate;
XM_U16 tfcMSEiThresh[8];
XM_U16 diyMSEiThresh[8];
XM_U8 tfyLimit;
XM_U8 noiseMADpThresh;
XM_U16 noiseMSDpThresh;
XM_U8 log2hStepMADp, log2hStepMSEi;
XM_U8 histMinMADp, histMaxMADp;
XM_U16 histMinMSEi, histMaxMSEi;
/*---------------------------------------------*/
tVppCalcWnd yWnd[2];
tVppCalcWnd cWnd[2];
} tVppDnCfg;
typedef tVppDnCfg VPP_DN_EX_S;
/* Sp */
typedef struct
{
XM_U8 strength;//
XM_U8 limit;//
XM_U8 black;
XM_U8 white;
} tVppSharpenCfg;
typedef tVppSharpenCfg VPP_SP_EX_S;
typedef struct xm_VPP_CFG_EX_S
{
VPP_IE_EX_S stIE_Ex;
VPP_DN_EX_S stDN_Ex;
VPP_SP_EX_S stSP_Ex;
} VPP_CFG_EX_S;
/* VI Mix-Capture info. */
typedef struct xm_VI_MIXCAP_STAT_S
{
XM_BOOL bMixCapMode; /* In mix-capture mode or not. */
XM_BOOL bHasDownScale; /* VI Frame is downscaled or not. */
} VI_MIXCAP_STAT_S;
/* VI output frame info. */
typedef struct xm_VI_FRAME_INFO_S
{
VI_MIXCAP_STAT_S stMixCapState; /* VI Mix-Capture info. */
VIDEO_FRAME_INFO_S stViFrmInfo; /* Video frame info. */
XM_BOOL bFlashed; /* Flashed Video frame or not. */
}VI_FRAME_INFO_S;
typedef enum xm_LDC_VIEW_TYPE_E
{
LDC_VIEW_TYPE_ALL = 0, /* View scale all but x and y independtly, this will keep both x and y axis ,but corner maybe lost*/
LDC_VIEW_TYPE_CROP, /* Not use view scale, this will lost some side and corner */
LDC_VIEW_TYPE_BUTT,
} LDC_VIEW_TYPE_E;
typedef struct xm_LDC_ATTR_S
{
LDC_VIEW_TYPE_E enViewType;
XM_S32 s32CenterXOffset; /* Horizontal offset of the image distortion center relative to image center. [-28,28]. */
XM_S32 s32CenterYOffset; /* Vertical offset of the image distortion center relative to image center. [-14,14]. */
XM_S32 s32Ratio; /* Distortion ratio. [0, 511]. */
} LDC_ATTR_S;
#endif /* _XM_COMM_VIDEO_H_ */

468
general/package/xiongmai-osdrv-xm530/files/include/xm_comm_vo.h
View File

@ -1,468 +0,0 @@
#ifndef __XM_COMM_VO_H__
#define __XM_COMM_VO_H__
#include "xm_type.h"
#include "xm_common.h"
#include "xm_comm_video.h"
#include "xm_errno.h"
#define VO_DEF_CHN_BUF_LEN 8
#define VO_DEF_DISP_BUF_LEN 5
#define VO_DEF_VIRT_BUF_LEN 3
#define VO_DEF_WBC_DEPTH_LEN 8
#ifdef __cplusplus
#if __cplusplus
extern "C"{
#endif
#endif /* End of #ifdef __cplusplus */
typedef enum xmEN_VOU_ERR_CODE_E
{
EN_ERR_VO_DEV_NOT_CONFIG = 0x40,
EN_ERR_VO_DEV_NOT_ENABLE = 0x41,
EN_ERR_VO_DEV_HAS_ENABLED = 0x42,
EN_ERR_VO_DEV_HAS_BINDED = 0x43,
EN_ERR_VO_DEV_NOT_BINDED = 0x44,
ERR_VO_NOT_ENABLE = 0x45,
ERR_VO_NOT_DISABLE = 0x46,
ERR_VO_NOT_CONFIG = 0x47,
ERR_VO_CHN_NOT_DISABLE = 0x48,
ERR_VO_CHN_NOT_ENABLE = 0x49,
ERR_VO_CHN_NOT_CONFIG = 0x4a,
ERR_VO_CHN_NOT_ALLOC = 0x4b,
ERR_VO_CCD_INVALID_PAT = 0x4c,
ERR_VO_CCD_INVALID_POS = 0x4d,
ERR_VO_WAIT_TIMEOUT = 0x4e,
ERR_VO_INVALID_VFRAME = 0x4f,
ERR_VO_INVALID_RECT_PARA = 0x50,
ERR_VO_SETBEGIN_ALREADY = 0x51,
ERR_VO_SETBEGIN_NOTYET = 0x52,
ERR_VO_SETEND_ALREADY = 0x53,
ERR_VO_SETEND_NOTYET = 0x54,
ERR_VO_GRP_INVALID_ID = 0x55,
ERR_VO_GRP_NOT_CREATE = 0x56,
ERR_VO_GRP_HAS_CREATED = 0x57,
ERR_VO_GRP_NOT_DESTROY = 0x58,
ERR_VO_GRP_CHN_FULL = 0x59,
ERR_VO_GRP_CHN_EMPTY = 0x5a,
ERR_VO_GRP_CHN_NOT_EMPTY = 0x5b,
ERR_VO_GRP_INVALID_SYN_MODE = 0x5c,
ERR_VO_GRP_INVALID_BASE_PTS = 0x5d,
ERR_VO_GRP_NOT_START = 0x5e,
ERR_VO_GRP_NOT_STOP = 0x5f,
ERR_VO_GRP_INVALID_FRMRATE = 0x60,
ERR_VO_GRP_CHN_HAS_REG = 0x61,
ERR_VO_GRP_CHN_NOT_REG = 0x62,
ERR_VO_GRP_CHN_NOT_UNREG = 0x63,
ERR_VO_GRP_BASE_NOT_CFG = 0x64,
ERR_GFX_NOT_DISABLE = 0x65,
ERR_GFX_NOT_BIND = 0x66,
ERR_GFX_NOT_UNBIND = 0x67,
ERR_GFX_INVALID_ID = 0x68,
ERR_VO_WBC_NOT_DISABLE = 0x69,
ERR_VO_WBC_NOT_CONFIG = 0x6a,
ERR_VO_CHN_AREA_OVERLAP = 0x6b,
EN_ERR_INVALID_WBCID = 0x6c,
EN_ERR_INVALID_LAYERID = 0x6d,
EN_ERR_VO_VIDEO_HAS_BINDED = 0x6e,
EN_ERR_VO_VIDEO_NOT_BINDED = 0x6f,
ERR_VO_WBC_HAS_BIND = 0x70,
ERR_VO_WBC_HAS_CONFIG = 0x71,
ERR_VO_WBC_NOT_BIND = 0x72,
/* new added */
ERR_VO_BUTT
}EN_VOU_ERR_CODE_E;
#define XM_TRACE_VO(level, fmt...) XM_TRACE(level, XM_ID_VOU,##fmt)
/* System define error code */
#define XM_ERR_VO_BUSY XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_BUSY)
#define XM_ERR_VO_NO_MEM XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_NOMEM)
#define XM_ERR_VO_NULL_PTR XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_NULL_PTR)
#define XM_ERR_VO_SYS_NOTREADY XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_SYS_NOTREADY)
#define XM_ERR_VO_INVALID_DEVID XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_DEVID)
#define XM_ERR_VO_INVALID_CHNID XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_CHNID)
#define XM_ERR_VO_ILLEGAL_PARAM XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_ILLEGAL_PARAM)
#define XM_ERR_VO_NOT_SUPPORT XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_SUPPORT)
#define XM_ERR_VO_NOT_PERMIT XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_NOT_PERM)
#define XM_ERR_VO_INVALID_WBCID XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_WBCID)
#define XM_ERR_VO_INVALID_LAYERID XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_LAYERID)
/* device relative error code */
#define XM_ERR_VO_DEV_NOT_CONFIG XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_VO_DEV_NOT_CONFIG)
#define XM_ERR_VO_DEV_NOT_ENABLE XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_VO_DEV_NOT_ENABLE)
#define XM_ERR_VO_DEV_HAS_ENABLED XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_VO_DEV_HAS_ENABLED)
#define XM_ERR_VO_DEV_HAS_BINDED XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_VO_DEV_HAS_BINDED)
#define XM_ERR_VO_DEV_NOT_BINDED XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_VO_DEV_NOT_BINDED)
/* video relative error code */
#define XM_ERR_VO_VIDEO_NOT_ENABLE XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_NOT_ENABLE)
#define XM_ERR_VO_VIDEO_NOT_DISABLE XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_NOT_DISABLE)
#define XM_ERR_VO_VIDEO_NOT_CONFIG XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_NOT_CONFIG)
#define XM_ERR_VO_VIDEO_HAS_BINDED XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_VO_VIDEO_HAS_BINDED)
#define XM_ERR_VO_VIDEO_NOT_BINDED XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, EN_ERR_VO_VIDEO_NOT_BINDED)
/*wbc error code*/
#define XM_ERR_VO_WBC_NOT_DISABLE XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_WBC_NOT_DISABLE)
#define XM_ERR_VO_WBC_NOT_CONFIG XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_WBC_NOT_CONFIG)
#define XM_ERR_VO_WBC_HAS_CONFIG XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_WBC_HAS_CONFIG)
#define XM_ERR_VO_WBC_NOT_BIND XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_WBC_NOT_BIND)
#define XM_ERR_VO_WBC_HAS_BIND XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_WBC_HAS_BIND)
/* channel relative error code */
#define XM_ERR_VO_CHN_NOT_DISABLE XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_CHN_NOT_DISABLE)
#define XM_ERR_VO_CHN_NOT_ENABLE XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_CHN_NOT_ENABLE)
#define XM_ERR_VO_CHN_NOT_CONFIG XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_CHN_NOT_CONFIG)
#define XM_ERR_VO_CHN_NOT_ALLOC XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_CHN_NOT_ALLOC)
#define XM_ERR_VO_CHN_AREA_OVERLAP XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_CHN_AREA_OVERLAP)
/* cascade relatvie error code */
#define XM_ERR_VO_INVALID_PATTERN XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_CCD_INVALID_PAT)
#define XM_ERR_VO_INVALID_POSITION XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_CCD_INVALID_POS)
/* misc */
#define XM_ERR_VO_WAIT_TIMEOUT XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_WAIT_TIMEOUT)
#define XM_ERR_VO_INVALID_VFRAME XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_INVALID_VFRAME)
#define XM_ERR_VO_INVALID_RECT_PARA XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_INVALID_RECT_PARA)
#define XM_ERR_VO_SETBEGIN_ALREADY XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_SETBEGIN_ALREADY)
#define XM_ERR_VO_SETBEGIN_NOTYET XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_SETBEGIN_NOTYET)
#define XM_ERR_VO_SETEND_ALREADY XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_SETEND_ALREADY)
#define XM_ERR_VO_SETEND_NOTYET XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_SETEND_NOTYET)
/* sync group relative error code */
#define XM_ERR_VO_GRP_INVALID_ID XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_INVALID_ID)
#define XM_ERR_VO_GRP_NOT_CREATE XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_NOT_CREATE)
#define XM_ERR_VO_GRP_HAS_CREATED XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_HAS_CREATED)
#define XM_ERR_VO_GRP_NOT_DESTROY XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_NOT_DESTROY)
#define XM_ERR_VO_GRP_CHN_FULL XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_CHN_FULL)
#define XM_ERR_VO_GRP_CHN_EMPTY XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_CHN_EMPTY)
#define XM_ERR_VO_GRP_CHN_NOT_EMPTY XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_CHN_NOT_EMPTY)
#define XM_ERR_VO_GRP_INVALID_SYN_MODE XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_INVALID_SYN_MODE)
#define XM_ERR_VO_GRP_INVALID_BASE_PTS XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_INVALID_BASE_PTS)
#define XM_ERR_VO_GRP_NOT_START XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_NOT_START)
#define XM_ERR_VO_GRP_NOT_STOP XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_NOT_STOP)
#define XM_ERR_VO_GRP_INVALID_FRMRATE XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_INVALID_FRMRATE)
#define XM_ERR_VO_GRP_CHN_HAS_REG XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_CHN_HAS_REG)
#define XM_ERR_VO_GRP_CHN_NOT_REG XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_CHN_NOT_REG)
#define XM_ERR_VO_GRP_CHN_NOT_UNREG XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_CHN_NOT_UNREG)
#define XM_ERR_VO_GRP_BASE_NOT_CFG XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_VO_GRP_BASE_NOT_CFG)
/* graphics relative error code */
#define XM_ERR_VO_GFX_NOT_DISABLE XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_GFX_NOT_DISABLE)
#define XM_ERR_VO_GFX_NOT_BIND XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_GFX_NOT_BIND)
#define XM_ERR_VO_GFX_NOT_UNBIND XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_GFX_NOT_UNBIND)
#define XM_ERR_VO_GFX_INVALID_ID XM_DEF_ERR(XM_ID_VOU, EN_ERR_LEVEL_ERROR, ERR_GFX_INVALID_ID)
/* vo inteface type */
#define VO_INTF_CVBS (0x01L<<0)
#define VO_INTF_YPBPR (0x01L<<1)
#define VO_INTF_VGA (0x01L<<2)
#define VO_INTF_BT656 (0x01L<<3)
#define VO_INTF_BT1120 (0x01L<<4)
#define VO_INTF_HDMI (0x01L<<5)
#define VO_INTF_LCD (0x01L<<6)
#define VO_INTF_BT656_H (0x01L<<7)
#define VO_INTF_BT656_L (0x01L<<8)
/* WBC channel id*/
#define VO_WBC_CHN_ID (VO_MAX_CHN_NUM + 1)
#define VO_DEFAULT_CHN -1 /* use vo buffer as pip buffer */
/*****************************************************************************
* 3520 ADDed
*****************************************************************************/
typedef XM_S32 VO_INTF_TYPE_E;
//typedef XM_S32 VO_WBC_CHN;
typedef enum xmVO_INTF_SYNC_E
{
VO_OUTPUT_PAL = 0,
VO_OUTPUT_NTSC,
VO_OUTPUT_960H_PAL, /* ITU-R BT.1302 960 x 576 at 50 Hz (interlaced)*/
VO_OUTPUT_960H_NTSC, /* ITU-R BT.1302 960 x 480 at 60 Hz (interlaced)*/
VO_OUTPUT_1080P24,
VO_OUTPUT_1080P25,
VO_OUTPUT_1080P30,
VO_OUTPUT_720P50,
VO_OUTPUT_720P60,
VO_OUTPUT_1080I50,
VO_OUTPUT_1080I60,
VO_OUTPUT_1080P50,
VO_OUTPUT_1080P60,
VO_OUTPUT_576P50,
VO_OUTPUT_480P60,
VO_OUTPUT_640x480_60, /* VESA 640 x 480 at 60 Hz (non-interlaced) CVT */
VO_OUTPUT_800x600_60, /* VESA 800 x 600 at 60 Hz (non-interlaced) */
VO_OUTPUT_1024x768_60, /* VESA 1024 x 768 at 60 Hz (non-interlaced) */
VO_OUTPUT_1280x1024_60, /* VESA 1280 x 1024 at 60 Hz (non-interlaced) */
VO_OUTPUT_1366x768_60, /* VESA 1366 x 768 at 60 Hz (non-interlaced) */
VO_OUTPUT_1440x900_60, /* VESA 1440 x 900 at 60 Hz (non-interlaced) CVT Compliant */
VO_OUTPUT_1280x800_60, /* 1280*800@60Hz VGA@60Hz*/
VO_OUTPUT_1680x1050_60, /* VESA 1680 x 1050 at 60 Hz (non-interlaced) */
VO_OUTPUT_1920x2160_30, /* 1920x2160_30 */
VO_OUTPUT_1600x1200_60, /* VESA 1600 x 1200 at 60 Hz (non-interlaced) */
VO_OUTPUT_1920x1200_60, /* VESA 1920 x 1600 at 60 Hz (non-interlaced) CVT (Reduced Blanking)*/
VO_OUTPUT_2560x1440_30, /* 2560x1440_30 */
VO_OUTPUT_2560x1600_60, /* 2560x1600_60 */
VO_OUTPUT_3840x2160_30, /* 3840x2160_30 */
VO_OUTPUT_480x272_60_S, /* 480x272_60 serial */
VO_OUTPUT_480x272_60, /* 480x272_60*/
VO_OUTPUT_800x480_60, /* 800x480_60*/
VO_OUTPUT_1024x600_60, /* 1024x600_60*/
VO_OUTPUT_480x320_60, /* 480x320_60*/
VO_OUTPUT_USER,
VO_OUTPUT_BUTT
} VO_INTF_SYNC_E;
typedef enum xmVO_DISPLAY_FIELD_E
{
VO_FIELD_TOP, /* top field*/
VO_FIELD_BOTTOM, /* bottom field*/
VO_FIELD_BOTH, /* top and bottom field*/
VO_FIELD_BUTT
} VO_DISPLAY_FIELD_E;
typedef enum xmVOU_ZOOM_IN_E
{
VOU_ZOOM_IN_RECT = 0, /* zoom in by rect */
VOU_ZOOM_IN_RATIO, /* zoom in by ratio */
VOU_ZOOM_IN_BUTT
} VOU_ZOOM_IN_E;
typedef enum xmVO_CSC_MATRIX_E
{
VO_CSC_MATRIX_IDENTITY = 0, /* do not change color space */
VO_CSC_MATRIX_BT601_TO_BT709, /* change color space from BT.601 to BT.709 */
VO_CSC_MATRIX_BT709_TO_BT601, /* change color space from BT.709 to BT.601 */
VO_CSC_MATRIX_BT601_TO_RGB_PC, /* change color space from BT.601 to RGB */
VO_CSC_MATRIX_BT709_TO_RGB_PC, /* change color space from BT.709 to RGB */
VO_CSC_MATRIX_RGB_TO_BT601_PC, /* change color space from RGB to BT.601 */
VO_CSC_MATRIX_RGB_TO_BT709_PC, /* change color space from RGB to BT.709 */
VO_CSC_MATRIX_BUTT
} VO_CSC_MATRIX_E;
typedef struct xmVO_CHN_ATTR_S
{
XM_U32 u32Priority; /* video out overlay pri sd */
RECT_S stRect; /* rect of video out chn */
XM_BOOL bDeflicker; /* deflicker or not sd */
}VO_CHN_ATTR_S;
typedef struct tagVO_SYNC_INFO_S
{
XM_BOOL bSynm; /* sync mode(0:timing,as BT.656; 1:signal,as LCD) */
XM_BOOL bIop; /* interlaced or progressive display(0:i; 1:p) */
XM_U8 u8Intfb; /* interlace bit width while output */
XM_U16 u16Vact ; /* vertical active area */
XM_U16 u16Vbb; /* vertical back blank porch */
XM_U16 u16Vfb; /* vertical front blank porch */
XM_U16 u16Hact; /* herizontal active area */
XM_U16 u16Hbb; /* herizontal back blank porch */
XM_U16 u16Hfb; /* herizontal front blank porch */
XM_U16 u16Hmid; /* bottom herizontal active area */
XM_U16 u16Bvact; /* bottom vertical active area */
XM_U16 u16Bvbb; /* bottom vertical back blank porch */
XM_U16 u16Bvfb; /* bottom vertical front blank porch */
XM_U16 u16Hpw; /* horizontal pulse width */
XM_U16 u16Vpw; /* vertical pulse width */
XM_BOOL bIdv; /* inverse data valid of output */
XM_BOOL bIhs; /* inverse horizontal synch signal */
XM_BOOL bIvs; /* inverse vertical synch signal */
} VO_SYNC_INFO_S;
typedef struct xmVO_PUB_ATTR_S
{
XM_U32 u32BgColor; /* Background color of a device, in RGB format. */
VO_INTF_TYPE_E enIntfType; /* Type of a VO interface */
VO_INTF_SYNC_E enIntfSync; /* Type of a VO interface timing */
VO_SYNC_INFO_S stSyncInfo; /* Information about VO interface timings */
} VO_PUB_ATTR_S;
typedef struct xmVO_WBC_ATTR_S
{
SIZE_S stTargetSize; /* WBC Zoom target size */
PIXEL_FORMAT_E enPixelFormat; /* the pixel format of WBC output */
XM_U32 u32FrameRate; /* frame rate control */
} VO_WBC_ATTR_S;
typedef enum xmVO_WBC_MODE_E
{
VO_WBC_MODE_NOMAL = 0, /* In this mode, wbc will capture frames according to dev frame rate
and wbc frame rate */
VO_WBC_MODE_DROP_REPEAT, /* In this mode, wbc will drop dev repeat frame, and capture the real frame
according to video layer's display rate and wbc frame rate */
VO_WBC_MODE_PROG_TO_INTL, /* In this mode, wbc will drop dev repeat frame which repeats more than 3 times,
and change two progressive frames to one interlace frame */
VO_WBC_MODE_BUTT,
} VO_WBC_MODE_E;
typedef enum xmVO_WBC_SOURCE_TYPE_E
{
VO_WBC_SOURCE_DEV = 0x0, /* WBC source is device */
VO_WBC_SOURCE_VIDEO = 0x1, /* WBC source is video layer */
VO_WBC_SOURCE_GRAPHIC = 0x2, /* WBC source is graphic layer, not support */
VO_WBC_SOURCE_BUTT
} VO_WBC_SOURCE_TYPE_E;
typedef struct xmVO_WBC_SOURCE_S
{
VO_WBC_SOURCE_TYPE_E enSourceType; /* the type of WBC source */
XM_U32 u32SourceId; /* the device, video layer or graphic layer */
} VO_WBC_SOURCE_S;
typedef enum xmVO_CAS_MODE_E
{
VO_CAS_MODE_SINGLE = 0, /* cascade mode is single */
VO_CAS_MODE_DUAL, /* cascade mode is dual */
VO_CAS_MODE_BUTT,
} VO_CAS_MODE_E;
typedef enum xmVO_CAS_DATA_TRAN_MODE_E
{
VO_CAS_DATA_SINGLE_TRAN_MODE = 0, /* single transition,clock rising edge or clock falling edge tigger transition */
VO_CAS_DATA_DOUBLE_TRAN_MODE, /* double transition,clock rising edge and clock falling edge tigger transition */
VO_CAS_DATA_MODE_BUTT,
} VO_CAS_DATA_TRAN_MODE_E;
typedef enum xmVO_CAS_RGN_E
{
VO_CAS_64_RGN = 0,
VO_CAS_32_RGN,
VO_CAS_RGN_BUTT,
} VO_CAS_RGN_E; /* cascade region number */
typedef struct xmVO_CAS_ATTR_S
{
XM_BOOL bSlave; /* XM_TRUE: slave mode, XM_FALSE: master mode */
VO_CAS_RGN_E enCasRgn; /* cascade region number */
VO_CAS_MODE_E enCasMode; /* cascade mode */
VO_CAS_DATA_TRAN_MODE_E enCasDataTranMode; /* cascade data transition mode */
} VO_CAS_ATTR_S;
typedef enum xmVO_PART_MODE_E
{
VO_PART_MODE_SINGLE = 0, /* single partition, which use software to make multi-picture in one hardware cell */
VO_PART_MODE_MULTI = 1, /* muliti partition, each partition is a hardware cell */
VO_PART_MODE_BUTT
} VO_PART_MODE_E;
typedef struct xmVO_COMPRESS_ATTR_S
{
XM_BOOL bSupportCompress; /* Whether to support compress */
}VO_COMPRESS_ATTR_S;
typedef struct xmVO_VIDEO_LAYER_ATTR_S
{
RECT_S stDispRect; /* Display resolution */
SIZE_S stImageSize; /* Canvas size of the video layer */
XM_U32 u32DispFrmRt; /* Display frame rate */
PIXEL_FORMAT_E enPixFormat; /* Pixel format of the video layer */
XM_BOOL bDoubleFrame; /* Whether to double frames */
XM_BOOL bClusterMode; /* Whether to take Cluster way to use memory*/
} VO_VIDEO_LAYER_ATTR_S;
typedef enum xmVOU_LAYER_DDR_E
{
VOU_LAYER_DDR0 = 0,
VOU_LAYER_DDR1 = 1,
VOU_LAYER_DDR_BUTT
}VOU_LAYER_DDR_E;
typedef struct xmVO_ZOOM_RATIO_S
{
XM_U32 u32XRatio;
XM_U32 u32YRatio;
XM_U32 u32WRatio;
XM_U32 u32HRatio;
} VO_ZOOM_RATIO_S;
typedef struct xmVO_ZOOM_ATTR_S
{
VOU_ZOOM_IN_E enZoomType; /* choose the type of zoom in */
union
{
RECT_S stZoomRect; /* zoom in by rect */
VO_ZOOM_RATIO_S stZoomRatio; /* zoom in by ratio */
};
} VO_ZOOM_ATTR_S;
typedef struct xmVO_CSC_S
{
VO_CSC_MATRIX_E enCscMatrix;
XM_U32 u32Luma; /* luminance: 0 ~ 100 default: 50 */
XM_U32 u32Contrast; /* contrast : 0 ~ 100 default: 50 */
XM_U32 u32Hue; /* hue : 0 ~ 100 default: 50 */
XM_U32 u32Saturation; /* saturation: 0 ~ 100 default: 50 */
} VO_CSC_S;
typedef struct xmVO_VGA_PARAM_S
{
VO_CSC_S stCSC; /* color space */
XM_U32 u32Gain; /* current gain of VGA signals. [0, 64). default:0x30 */
XM_S32 s32SharpenStrength; /* current sharpen strength of VGA signals. [0, 255]. default:0x80 */
} VO_VGA_PARAM_S;
typedef struct xmVO_HDMI_PARAM_S
{
VO_CSC_S stCSC; /* color space */
} VO_HDMI_PARAM_S;
typedef struct xmVO_REGION_INFO_S
{
RECT_S *pstRegion; /*region attribute*/
XM_U32 u32RegionNum; /*count of the region*/
}VO_REGION_INFO_S;
typedef struct xmVO_IMAGE_LAYER_ATTR_S
{
RECT_S stDispRect; /* Display resolution */
PIXEL_FORMAT_E enPixFormat; /* Pixel format of the video layer */
XM_U32 u32PhyAddr;
XM_U32 u32Effect; /*0-7 tran;8-15 tran0;16-23 tran1; 24-27 HUP;28-31VUP */
} VO_IMAGE_LAYER_ATTR_S;
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* End of #ifdef __cplusplus */
#endif /* End of #ifndef __XM_COMM_VO_H__ */

408
general/package/xiongmai-osdrv-xm530/files/include/xm_common.h
View File

@ -1,408 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm_ae_common.h
Version : Initial Draft
Author : XM Isp software group
Created : 2015/6/27
Description : The common data type defination
Function List :
History :
1.Date : 2015/6/27
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef __XM_COMMON_H__
#define __XM_COMMON_H__
#include "xm_type.h"
#include "xm_defines.h"
/*#include "xm_comm_video.h"*/
#ifndef VER_X
#define VER_X 1
#endif
#ifndef VER_Y
#define VER_Y 0
#endif
#ifndef VER_Z
#define VER_Z 0
#endif
#ifndef VER_P
#define VER_P 0
#endif
#ifdef XM_DEBUG
#define VER_D " "
#else
#define VER_D " Release"
#endif
#define __MK_VERSION(x,y,z,p) #x"."#y"."#z"."#p
#define MK_VERSION(x,y,z,p) __MK_VERSION(x,y,z,p)
#define MPP_VERSION CHIP_NAME MPP_VER_PRIX MK_VERSION(VER_X,VER_Y,VER_Z,VER_P) VER_D
#define COM_VERSION MPP_VER_PRIX MK_VERSION(VER_X,VER_Y,VER_Z,VER_P) VER_D
#define VERSION_NAME_MAXLEN 64
typedef struct xm_MPP_VERSION_S
{
XM_CHAR aVersion[VERSION_NAME_MAXLEN];
}MPP_VERSION_S;
typedef struct xm_POINT_S
{
XM_S32 s32X;
XM_S32 s32Y;
}POINT_S;
typedef struct xm_SIZE_S
{
XM_U32 u32Width;
XM_U32 u32Height;
} SIZE_S;
typedef struct xm_RECT_S
{
XM_S32 s32X;
XM_S32 s32Y;
XM_U32 u32Width;
XM_U32 u32Height;
}RECT_S;
typedef enum xm_ROTATE_E
{
ROTATE_NONE = 0,
ROTATE_90 = 1,
ROTATE_180 = 2,
ROTATE_270 = 3,
ROTATE_BUTT
} ROTATE_E;
typedef XM_S32 AI_CHN;
typedef XM_S32 AO_CHN;
typedef XM_S32 AENC_CHN;
typedef XM_S32 ADEC_CHN;
typedef XM_S32 AUDIO_DEV;
typedef XM_S32 AVENC_CHN;
typedef XM_S32 VI_DEV;
typedef XM_S32 VI_WAY;
typedef XM_S32 VI_CHN;
typedef XM_S32 VO_DEV;
typedef XM_S32 VO_LAYER;
typedef XM_S32 VO_CHN;
typedef XM_S32 VENC_CHN;
typedef XM_S32 VDEC_CHN;
typedef XM_S32 VENC_GRP;
typedef XM_S32 VO_GRP;
typedef XM_S32 VDA_CHN;
typedef XM_S32 IVE_HANDLE;
typedef XM_S32 ISP_DEV;
typedef XM_S32 SENSOR_ID;
#define XM_INVALID_CHN (-1)
#define XM_INVALID_WAY (-1)
#define XM_INVALID_LAYER (-1)
#define XM_INVALID_DEV (-1)
#define XM_INVALID_HANDLE (-1)
#define XM_INVALID_VALUE (-1)
#define XM_INVALID_TYPE (-1)
typedef enum xm_MOD_ID_E
{
XM_ID_CMPI = 0,
XM_ID_VB = 1,
XM_ID_SYS = 2,
XM_ID_VALG = 3,
XM_ID_CHNL = 4,
XM_ID_VDEC = 5,
XM_ID_GROUP = 6,
XM_ID_VENC = 7,
XM_ID_VPSS = 8,
XM_ID_VDA = 9,
XM_ID_H264E = 10,
XM_ID_JPEGE = 11,
XM_ID_MPEG4E = 12,
XM_ID_H264D = 13,
XM_ID_JPEGD = 14,
XM_ID_VOU = 15,
XM_ID_VIU = 16,
XM_ID_DSU = 17,
XM_ID_RGN = 18,
XM_ID_RC = 19,
XM_ID_SIO = 20,
XM_ID_AI = 21,
XM_ID_AO = 22,
XM_ID_AENC = 23,
XM_ID_ADEC = 24,
XM_ID_AVENC = 25,
XM_ID_PCIV = 26,
XM_ID_PCIVFMW = 27,
XM_ID_ISP = 28,
XM_ID_IVE = 29,
/* there is a hole */
XM_ID_DCCM = 31,
XM_ID_DCCS = 32,
XM_ID_PROC = 33,
XM_ID_LOG = 34,
XM_ID_MST_LOG = 35,
XM_ID_VD = 36,
XM_ID_VCMP = 38,
XM_ID_FB = 39,
XM_ID_HDMI = 40,
XM_ID_VOIE = 41,
XM_ID_TDE = 42,
XM_ID_USR = 43,
XM_ID_VEDU = 44,
XM_ID_BUTT,
} MOD_ID_E;
typedef struct xm_MPP_CHN_S
{
MOD_ID_E enModId;
XM_S32 s32DevId;
XM_S32 s32ChnId;
} MPP_CHN_S;
#define MPP_MOD_VIU "vi"
#define MPP_MOD_VOU "vo"
#define MPP_MOD_HDMI "hdmi"
#define MPP_MOD_DSU "dsu"
#define MPP_MOD_CHNL "chnl"
#define MPP_MOD_VENC "venc"
#define MPP_MOD_GRP "grp"
#define MPP_MOD_VDA "vda"
#define MPP_MOD_VPSS "vpss"
#define MPP_MOD_RGN "rgn"
#define MPP_MOD_IVE "ive"
#define MPP_MOD_H264E "h264e"
#define MPP_MOD_JPEGE "jpege"
#define MPP_MOD_MPEG4E "mpeg4e"
#define MPP_MOD_VDEC "vdec"
#define MPP_MOD_H264D "h264d"
#define MPP_MOD_JPEGD "jpegd"
#define MPP_MOD_AI "ai"
#define MPP_MOD_AO "ao"
#define MPP_MOD_AENC "aenc"
#define MPP_MOD_ADEC "adec"
#define MPP_MOD_SIO "sio"
#define MPP_MOD_VB "vb"
#define MPP_MOD_SYS "sys"
#define MPP_MOD_CMPI "cmpi"
#define MPP_MOD_PCIV "pciv"
#define MPP_MOD_PCIVFMW "pcivfmw"
#define MPP_MOD_PROC "proc"
#define MPP_MOD_LOG "logmpp"
#define MPP_MOD_MST_LOG "mstlog"
#define MPP_MOD_DCCM "dccm"
#define MPP_MOD_DCCS "dccs"
#define MPP_MOD_VCMP "vcmp"
#define MPP_MOD_FB "fb"
#define MPP_MOD_RC "rc"
#define MPP_MOD_VOIE "voie"
#define MPP_MOD_TDE "tde"
#define MPP_MOD_ISP "isp"
#define MPP_MOD_ACODEC "acodec"
/* We just coyp this value of payload type from RTP/RTSP definition */
typedef enum
{
PT_PCMU = 0,
PT_1016 = 1,
PT_G721 = 2,
PT_GSM = 3,
PT_G723 = 4,
PT_DVI4_8K = 5,
PT_DVI4_16K = 6,
PT_LPC = 7,
PT_PCMA = 8,
PT_G722 = 9,
PT_S16BE_STEREO = 10,
PT_S16BE_MONO = 11,
PT_QCELP = 12,
PT_CN = 13,
PT_MPEGAUDIO = 14,
PT_G728 = 15,
PT_DVI4_3 = 16,
PT_DVI4_4 = 17,
PT_G729 = 18,
PT_G711A = 19,
PT_G711U = 20,
PT_G726 = 21,
PT_G729A = 22,
PT_LPCM = 23,
PT_CelB = 25,
PT_JPEG = 26,
PT_CUSM = 27,
PT_NV = 28,
PT_PICW = 29,
PT_CPV = 30,
PT_H261 = 31,
PT_MPEGVIDEO = 32,
PT_MPEG2TS = 33,
PT_H263 = 34,
PT_SPEG = 35,
PT_MPEG2VIDEO = 36,
PT_AAC = 37,
PT_WMA9STD = 38,
PT_HEAAC = 39,
PT_PCM_VOICE = 40,
PT_PCM_AUDIO = 41,
PT_AACLC = 42,
PT_MP3 = 43,
PT_ADPCMA = 49,
PT_AEC = 50,
PT_X_LD = 95,
PT_H264 = 96,
PT_D_GSM_HR = 200,
PT_D_GSM_EFR = 201,
PT_D_L8 = 202,
PT_D_RED = 203,
PT_D_VDVI = 204,
PT_D_BT656 = 220,
PT_D_H263_1998 = 221,
PT_D_MP1S = 222,
PT_D_MP2P = 223,
PT_D_BMPEG = 224,
PT_MP4VIDEO = 230,
PT_MP4AUDIO = 237,
PT_VC1 = 238,
PT_JVC_ASF = 255,
PT_D_AVI = 256,
PT_DIVX3 = 257,
PT_AVS = 258,
PT_REAL8 = 259,
PT_REAL9 = 260,
PT_VP6 = 261,
PT_VP6F = 262,
PT_VP6A = 263,
PT_SORENSON =264,
PT_H265 = 265,
PT_MAX = 266,
/* add by xm_silicon */
PT_AMR = 1001,
PT_MJPEG = 1002,
PT_AMRWB = 1003,
PT_BUTT
}PAYLOAD_TYPE_E;
typedef enum xm_VOU_WHO_SENDPIC_E
{
VOU_WHO_SENDPIC_VIU = 0,
VOU_WHO_SENDPIC_VDEC = 1,
VOU_WHO_SENDPIC_PCIV = 2,
VOU_WHO_SENDPIC_VPP = 3,
VOU_WHO_SENDPIC_USR = 4,
VOU_WHO_SENDPIC_BUTT
} VOU_WHO_SENDPIC_E;
#if 1
//滤波系数的定义可能与芯片有关，具体实现时再考虑放在哪里
/* horizontal scale filter coefficient of dsu
** which affect image quality of encoding and preview.
** normally the filter can be set be DSU_HSCALE_FILTER_DEFAULT
** which means sdk will choose filter automatically.Otherwise,
** you can choose other filter
** Notes:65M means 6.5
*/
typedef enum xm_DSU_HSCALE_FILTER_E
{
DSU_HSCALE_FILTER_DEFAULT = 0,
DSU_HSCALE_FILTER_C_65M,
DSU_HSCALE_FILTER_CG_56M,
DSU_HSCALE_FILTER_LC_45M,
DSU_HSCALE_FILTER_CG_3M,
DSU_HSCALE_FILTER_CG_2M,
DSU_HSCALE_FILTER_CG_1M,
DSU_HSCALE_FILTER_BUTT
}DSU_HSCALE_FILTER_E;
/* vertical scale filter coefficient of dsu
** which affect image quality of encoding and preview.
** normally the filter can be set be DSU_VSCALE_FILTER_DEFAULT
** which means sdk will choose filter automatically.Otherwise,
** you can choose other filter
** Notes:38M means 3.8
*/
typedef enum xm_DSU_VSCALE_FILTER_E
{
DSU_VSCALE_FILTER_DEFAULT = 0,
DSU_VSCALE_FILTER_S_6M,
DSU_VSCALE_FILTER_S_5M,
DSU_VSCALE_FILTER_S_4M,
DSU_VSCALE_FILTER_S_38M,
DSU_VSCALE_FILTER_S_37M,
DSU_VSCALE_FILTER_S_36M,
DSU_VSCALE_FILTER_S_25M,
DSU_VSCALE_FILTER_S_2M,
DSU_VSCALE_FILTER_S_15M,
DSU_VSCALE_FILTER_S_12M,
DSU_VSCALE_FILTER_S_11M,
DSU_VSCALE_FILTER_S_1M,
DSU_VSCALE_FILTER_BUTT
}DSU_VSCALE_FILTER_E;
/*DSU filter param type*/
typedef enum xm_DSU_FILTER_PARAM_TYPE
{
FILTER_PARAM_TYPE_NORM = 0,
FILTER_PARAM_TYPE_EX,
FILTER_PARAM_TYPE_EX2,
FILTER_PARAM_TYPE_USER1,
FILTER_PARAM_TYPE_USER2,
FILTER_PARAM_TYPE_BUTT
}DSU_FILTER_PARAM_TYPE;
#define DSU_HFILTER_PARAM_NUM 792
#define DSU_VFILTER_PARAM_NUM 480
typedef struct xm_DSU_FILTER_PARAM_S
{
DSU_FILTER_PARAM_TYPE enFiltType;
XM_U8 au8HParamTable[DSU_HFILTER_PARAM_NUM];
XM_U8 au8VParamTable[DSU_VFILTER_PARAM_NUM];
}DSU_FILTER_PARAM_S;
#endif
#endif /* _XM_COMMON_H_ */

113
general/package/xiongmai-osdrv-xm530/files/include/xm_debug.h
View File

@ -1,113 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm_debug.h
Version : Initial Draft
Author : XM Isp software group
Created : 2015/6/27
Description : The common data type defination
Function List :
History :
1.Date : 2015/6/27
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef __XM_DEBUG_H__
#define __XM_DEBUG_H__
#include "xm_type.h"
#include "xm_common.h"
#define XM_DEBUG
#define _EX__FILE_LINE(fxx,lxx) "[File]:"fxx"\n[Line]:"#lxx"\n[Info]:"
#define EX__FILE_LINE(fxx,lxx) _EX__FILE_LINE(fxx,lxx)
#define __FILE_LINE__ EX__FILE_LINE(__FILE__, __LINE__)
#define XM_DBG_EMERG 0 /* system is unusable */
#define XM_DBG_ALERT 1 /* action must be taken immediately */
#define XM_DBG_CRIT 2 /* critical conditions */
#define XM_DBG_ERR 3 /* error conditions */
#define XM_DBG_WARN 4 /* warning conditions */
#define XM_DBG_NOTICE 5 /* normal but significant condition */
#define XM_DBG_INFO 6 /* informational */
#define XM_DBG_DEBUG 7 /* debug-level messages */
typedef struct xm_LOG_LEVEL_CONF_S
{
MOD_ID_E enModId;
XM_S32 s32Level;
XM_CHAR cModName[16];
} LOG_LEVEL_CONF_S;
#ifndef __KERNEL__
/******************************************************************************
** For User Mode : XM_PRINT, XM_ASSERT, XM_TRACE
******************************************************************************/
int XM_LOG(XM_S32 level, MOD_ID_E enModId,const char *fmt, ...);
#define XM_PRINT printf
#ifdef XM_DEBUG
/* Using samples: XM_ASSERT(x>y); */
#define XM_ASSERT(expr) \
do{ \
if (!(expr)) { \
printf("\nASSERT failed at:\n"\
" >File name: %s\n" \
" >Function : %s\n" \
" >Line No. : %d\n" \
" >Condition: %s\n", \
__FILE__,__FUNCTION__, __LINE__, #expr);\
_exit(-1);\
} \
}while(0)
/* Using samples:
** XM_TRACE(XM_DBG_DEBUG, XM_ID_CMPI, "Test %d, %s\n", 12, "Test");
**/
#define XM_TRACE XM_LOG
#else
#define XM_ASSERT(expr)
#define XM_TRACE(level, enModId, fmt...)
#endif
#else
/******************************************************************************
** For Linux Kernel : XM_PRINT, XM_ASSERT, XM_TRACE
******************************************************************************/
#define XM_PRINT printk
extern XM_S32 XM_ChkLogLevel(XM_S32 s32Levle, MOD_ID_E enModId);
asmlinkage int XM_LOG(XM_S32 level, MOD_ID_E enModId,const char *fmt, ...);
#ifdef XM_DEBUG
/* Using samples: XM_ASSERT(x>y); */
#define XM_ASSERT(expr) \
do{ \
if (!(expr)) { \
panic("\nASSERT failed at:\n" \
" >File name: %s\n" \
" >Function : %s\n" \
" >Line No. : %d\n" \
" >Condition: %s\n", \
__FILE__,__FUNCTION__, __LINE__, #expr);\
} \
}while(0)
/* Using samples:
** XM_TRACE(XM_DBG_DEBUG, XM_ID_CMPI, "Test %d, %s\n", 12, "Test");
**/
#define XM_TRACE XM_LOG
#else
#define XM_ASSERT(expr)
#define XM_TRACE(level, enModId, fmt...)
#endif
#endif /* end of __KERNEL__ */
#endif /* __XM_DEBUG_H__ */

66
general/package/xiongmai-osdrv-xm530/files/include/xm_defines.h
View File

@ -1,66 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm_defines.h
Version : Initial Draft
Author : XM Isp software group
Created : 2015/6/27
Description : The common data type defination
Function List :
History :
1.Date : 2015/6/27
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef __XM_DEFINES_H__
#define __XM_DEFINES_H__
#define BITMSK(bit) (XM_S32)(1 << (bit))
#define LINE_LEN_BIT 5
#define LINE_LEN (1<<LINE_LEN_BIT)
#define LINE_BASE_MASK (~(LINE_LEN-1))
/* For Sys */
#define DEFAULT_ALIGN 16
#define MAX_MMZ_NAME_LEN 16
#define MAX_NODE_NUM 16
/* For VDA */
#define VDA_MAX_NODE_NUM 32
#define VDA_MAX_INTERNAL 256
#define VDA_CHN_NUM_MAX 32
#define VDA_MAX_WIDTH 960
#define VDA_MAX_HEIGHT 576
/* For H264 H265 JPEG */
#define VENC_MAX_CHN_NUM 4
/* For Region */
#define OVERLAY_MAX_NUM 8
#define COVER_MAX_NUM 32
#define RGN_MAX_CHN_NUM 3
/* number of channle and device on video input unit of chip
* Note! VIU_MAX_CHN_NUM is NOT equal to VIU_MAX_DEV_NUM
* multiplied by VIU_MAX_CHN_NUM, because all VI devices
* can't work at mode of 4 channles at the same time.
*/
#define VIU_MAX_CHN_NUM 3
#define AIO_MAX_CHN_NUM 1
#define AENC_MAX_CHN_NUM 1
#define ADEC_MAX_CHN_NUM 1
#define AI_DEV_MAX_NUM 1
#define AO_DEV_MIN_NUM 0
#define AO_DEV_MAX_NUM 1
#endif /* __XM_DEFINES_H__ */

103
general/package/xiongmai-osdrv-xm530/files/include/xm_errno.h
View File

@ -1,103 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2020, XM. Co., Ltd.
******************************************************************************
File Name : xm_errno.h
Version : Initial Draft
Author : XM Isp software group
Created : 2015/6/27
Description : The common data type defination
Function List :
History :
1.Date : 2015/6/27
Author : Lycai
Modification : creat
******************************************************************************/
#ifndef __XM_ERRNO_H__
#define __XM_ERRNO_H__
#include "xm_debug.h"
#define XM_ERR_APPID (0x80000000L + 0x20000000L)
typedef enum xm_ERR_LEVEL_E
{
EN_ERR_LEVEL_DEBUG = 0, /* debug-level */
EN_ERR_LEVEL_INFO, /* informational */
EN_ERR_LEVEL_NOTICE, /* normal but significant condition */
EN_ERR_LEVEL_WARNING, /* warning conditions */
EN_ERR_LEVEL_ERROR, /* error conditions */
EN_ERR_LEVEL_CRIT, /* critical conditions */
EN_ERR_LEVEL_ALERT, /* action must be taken immediately */
EN_ERR_LEVEL_FATAL, /* just for compatibility with previous version */
EN_ERR_LEVEL_BUTT
}ERR_LEVEL_E;
/******************************************************************************
|----------------------------------------------------------------|
| 1 | APP_ID | MOD_ID | ERR_LEVEL | ERR_ID |
|----------------------------------------------------------------|
|<--><--7bits----><----8bits---><--3bits---><------13bits------->|
******************************************************************************/
#define XM_DEF_ERR( module, level, errid) \
((XM_S32)( (XM_ERR_APPID) | ((module) << 16 ) | ((level)<<13) | (errid) ))
/* NOTE! the following defined all common error code,
** all module must reserved 0~63 for their common error code
*/
typedef enum xm_EN_ERR_CODE_E
{
EN_ERR_INVALID_DEVID = 1, /* invlalid device ID */
EN_ERR_INVALID_CHNID = 2, /* invlalid channel ID */
EN_ERR_ILLEGAL_PARAM = 3, /* at lease one parameter is illagal
* eg, an illegal enumeration value */
EN_ERR_EXIST = 4, /* resource exists */
EN_ERR_UNEXIST = 5, /* resource unexists */
EN_ERR_NULL_PTR = 6, /* using a NULL point */
EN_ERR_NOT_CONFIG = 7, /* try to enable or initialize system, device
** or channel, before configing attribute */
EN_ERR_NOT_SUPPORT = 8, /* operation or type is not supported by NOW */
EN_ERR_NOT_PERM = 9, /* operation is not permitted
** eg, try to change attribute */
EN_ERR_NOT_FINISH = 10,/* encode one frame not finish,maybe bus error,timeout,sys reset and so on*/
EN_ERR_INSUFF_RES = 11,/* insufficient resource */
EN_ERR_NOMEM = 12,/* failure caused by malloc memory */
EN_ERR_NOBUF = 13,/* failure caused by malloc buffer */
EN_ERR_BUF_EMPTY = 14,/* no data in buffer */
EN_ERR_BUF_FULL = 15,/* no buffer for new data */
EN_ERR_SYS_NOTREADY = 16,/* System is not ready,maybe not initialed or
** loaded. Returning the error code when opening
** a device file failed. */
EN_ERR_BADADDR = 17,/* bad address,
** eg. used for copy_from_user & copy_to_user */
EN_ERR_BUSY = 18,/* resource is busy,
** eg. destroy a venc chn without unregister it */
EN_ERR_HW_FAILED = 19,/*encoder hardware failed*/
EN_ERR_UND = 20,/* undefined error */
EN_ERR_BUTT = 63,/* maxium code, private error code of all modules
** must be greater than it */
}EN_ERR_CODE_E;
/*
** following is an example for defining error code of VDA module
** #define XM_ERR_MD_INVALID_CHNID XM_DEF_ERR(XM_ID_VDA, EN_ERR_LEVEL_ERROR, EN_ERR_INVALID_CHNID)
**
*/
#endif /* __XM_ERRNO_H__ */

68
general/package/xiongmai-osdrv-xm530/files/include/xm_type.h
View File

@ -1,68 +0,0 @@
/******************************************************************************
Copyright (C), 2015-2025 XM Tech. Co., Ltd.
******************************************************************************
File Name : xm_type.h
Version : Initial Draft
Author : XM multimedia software group
Created : 2015/9/17
Last Modified :
Description : The common data type defination
******************************************************************************/
#ifndef __XM_TYPE_H__
#define __XM_TYPE_H__
#ifdef __cplusplus
#if __cplusplus
extern "C"{
#endif
#endif /* __cplusplus */
/*----------------------------------------------*
* The common data type, will be used in the whole project.*
*----------------------------------------------*/
typedef unsigned char XM_U8;
typedef unsigned short XM_U16;
typedef unsigned int XM_U32;
typedef signed char XM_S8;
typedef short XM_S16;
typedef int XM_S32;
#ifndef _M_IX86
typedef unsigned long long XM_U64;
typedef long long XM_S64;
#else
typedef __int64 XM_U64;
typedef __int64 XM_S64;
#endif
typedef char XM_CHAR;
#define XM_VOID void
/*----------------------------------------------*
* const defination *
*----------------------------------------------*/
typedef enum {
XM_FALSE = 0,
XM_TRUE = 1,
} XM_BOOL;
#ifndef NULL
#define NULL 0L
#endif
#define XM_NULL 0L
#define XM_SUCCESS 0
#define XM_FAILURE (-1)
#ifdef __cplusplus
#if __cplusplus
}
#endif
#endif /* __cplusplus */
#endif /* __XM_TYPE_H__ */

16
general/package/xiongmai-osdrv-xm530/xiongmai-osdrv-xm530.mk
View File

@ -8,22 +8,6 @@ XIONGMAI_OSDRV_XM530_VERSION =
XIONGMAI_OSDRV_XM530_SITE =
XIONGMAI_OSDRV_XM530_LICENSE = MIT
XIONGMAI_OSDRV_XM530_LICENSE_FILES = LICENSE
XIONGMAI_OSDRV_XM530_INSTALL_STAGING = YES
define XIONGMAI_OSDRV_XM530_INSTALL_STAGING_CMDS
$(INSTALL) -m 755 -d $(STAGING_DIR)/usr/include/xiongmai
# $(INSTALL) -m 644 -t $(STAGING_DIR)/usr/include/xiongmai $(BR2_EXTERNAL_XIONGMAI_PATH)/package/xiongmai-osdrv-xm530/files/include/*
# $(INSTALL) -m 755 -d $(BUILD_DIR)/xiongmai-osdrv-xm530/include
# $(INSTALL) -m 644 -t $(BUILD_DIR)/xiongmai-osdrv-xm530/include $(BR2_EXTERNAL_XIONGMAI_PATH)/package/xiongmai-osdrv-xm530/files/include/*
# $(INSTALL) -m 755 -d $(BUILD_DIR)/xiongmai-osdrv-xm530/kmod
# $(INSTALL) -m 644 -t $(BUILD_DIR)/xiongmai-osdrv-xm530/kmod $(BR2_EXTERNAL_XIONGMAI_PATH)/package/xiongmai-osdrv-xm530/files/kmod/*.ko
# $(INSTALL) -m 755 -d $(BUILD_DIR)/xiongmai-osdrv-xm530/lib
# $(INSTALL) -m 644 -t $(BUILD_DIR)/xiongmai-osdrv-xm530/lib $(BR2_EXTERNAL_XIONGMAI_PATH)/package/xiongmai-osdrv-xm530/files/lib/*.so
endef
define XIONGMAI_OSDRV_XM530_INSTALL_TARGET_CMDS