diff --git a/.github/workflows/ak3916ev300_images.yml b/.github/workflows/ak3916ev300_images.yml index d1aad31b..3838a6e4 100644 --- a/.github/workflows/ak3916ev300_images.yml +++ b/.github/workflows/ak3916ev300_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/ak3918ev200_images.yml b/.github/workflows/ak3918ev200_images.yml index 71278519..b8f21f60 100644 --- a/.github/workflows/ak3918ev200_images.yml +++ b/.github/workflows/ak3918ev200_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/ak3918ev300_images.yml b/.github/workflows/ak3918ev300_images.yml index 4dafb5f5..81656716 100644 --- a/.github/workflows/ak3918ev300_images.yml +++ b/.github/workflows/ak3918ev300_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/ambarella-s3l_images.yml b/.github/workflows/ambarella-s3l_images.yml index da35d584..7c2fa709 100644 --- a/.github/workflows/ambarella-s3l_images.yml +++ b/.github/workflows/ambarella-s3l_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/fh8833v100_images.yml b/.github/workflows/fh8833v100_images.yml index 17677c6a..ad0ed05f 100644 --- a/.github/workflows/fh8833v100_images.yml +++ b/.github/workflows/fh8833v100_images.yml @@ -28,6 +28,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/fh8852v100_images.yml b/.github/workflows/fh8852v100_images.yml index ed3480bb..bb708d2a 100644 --- a/.github/workflows/fh8852v100_images.yml +++ b/.github/workflows/fh8852v100_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/fh8852v200_images.yml b/.github/workflows/fh8852v200_images.yml index 6cc71137..922fd4d0 100644 --- a/.github/workflows/fh8852v200_images.yml +++ b/.github/workflows/fh8852v200_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/fh8852v210_images.yml b/.github/workflows/fh8852v210_images.yml index 308768f8..f6bf04e3 100644 --- a/.github/workflows/fh8852v210_images.yml +++ b/.github/workflows/fh8852v210_images.yml @@ -28,6 +28,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/fh8856v100_images.yml b/.github/workflows/fh8856v100_images.yml index 4e2782f3..fcc47f6c 100644 --- a/.github/workflows/fh8856v100_images.yml +++ b/.github/workflows/fh8856v100_images.yml @@ -28,6 +28,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/fh8856v200_images.yml b/.github/workflows/fh8856v200_images.yml index 34576716..4ba41a8f 100644 --- a/.github/workflows/fh8856v200_images.yml +++ b/.github/workflows/fh8856v200_images.yml @@ -28,6 +28,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/fh8856v210_images.yml b/.github/workflows/fh8856v210_images.yml index 27e91f87..9042a2f7 100644 --- a/.github/workflows/fh8856v210_images.yml +++ b/.github/workflows/fh8856v210_images.yml @@ -28,6 +28,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/fh8858v200_images.yml b/.github/workflows/fh8858v200_images.yml index 5c489f0a..80152770 100644 --- a/.github/workflows/fh8858v200_images.yml +++ b/.github/workflows/fh8858v200_images.yml @@ -28,6 +28,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/fh8858v210_images.yml b/.github/workflows/fh8858v210_images.yml index 6a94efe1..a512bc29 100644 --- a/.github/workflows/fh8858v210_images.yml +++ b/.github/workflows/fh8858v210_images.yml @@ -28,6 +28,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/gk7102_images.yml b/.github/workflows/gk7102_images.yml index 8a43d2d6..8ef151d0 100644 --- a/.github/workflows/gk7102_images.yml +++ b/.github/workflows/gk7102_images.yml @@ -23,6 +23,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/gk7102s_images.yml b/.github/workflows/gk7102s_images.yml index 0347ff80..61115bd9 100644 --- a/.github/workflows/gk7102s_images.yml +++ b/.github/workflows/gk7102s_images.yml @@ -23,6 +23,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/gk7202v300_images.yml b/.github/workflows/gk7202v300_images.yml index bdaaacee..1d772016 100644 --- a/.github/workflows/gk7202v300_images.yml +++ b/.github/workflows/gk7202v300_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/gk7205v200_fpv_images.yml b/.github/workflows/gk7205v200_fpv_images.yml index 5e857dcc..01832d87 100644 --- a/.github/workflows/gk7205v200_fpv_images.yml +++ b/.github/workflows/gk7205v200_fpv_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/gk7205v200_images.yml b/.github/workflows/gk7205v200_images.yml index e7afefc5..baa49d28 100644 --- a/.github/workflows/gk7205v200_images.yml +++ b/.github/workflows/gk7205v200_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/gk7205v200_ultimate_images.yml b/.github/workflows/gk7205v200_ultimate_images.yml index cc7e6657..99a752f7 100644 --- a/.github/workflows/gk7205v200_ultimate_images.yml +++ b/.github/workflows/gk7205v200_ultimate_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/gk7205v210_images.yml b/.github/workflows/gk7205v210_images.yml index 22c95b5c..1d2d41cb 100644 --- a/.github/workflows/gk7205v210_images.yml +++ b/.github/workflows/gk7205v210_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/gk7205v300_fpv_images.yml b/.github/workflows/gk7205v300_fpv_images.yml index b135bcbe..c8368288 100644 --- a/.github/workflows/gk7205v300_fpv_images.yml +++ b/.github/workflows/gk7205v300_fpv_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/gk7205v300_images.yml b/.github/workflows/gk7205v300_images.yml index 6307a763..9cdda8ba 100644 --- a/.github/workflows/gk7205v300_images.yml +++ b/.github/workflows/gk7205v300_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/gk7205v300_ultimate_images.yml b/.github/workflows/gk7205v300_ultimate_images.yml index 4c20fd9e..971b725f 100644 --- a/.github/workflows/gk7205v300_ultimate_images.yml +++ b/.github/workflows/gk7205v300_ultimate_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/gk7605v100_images.yml b/.github/workflows/gk7605v100_images.yml index c16c96dc..b8c6ed37 100644 --- a/.github/workflows/gk7605v100_images.yml +++ b/.github/workflows/gk7605v100_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/gm8136_images.yml b/.github/workflows/gm8136_images.yml index 94433fe5..e3aac55c 100644 --- a/.github/workflows/gm8136_images.yml +++ b/.github/workflows/gm8136_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/hi3516av100_images.yml b/.github/workflows/hi3516av100_images.yml index 1e8952f0..fe28b807 100644 --- a/.github/workflows/hi3516av100_images.yml +++ b/.github/workflows/hi3516av100_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/hi3516av100_ultimate_images.yml b/.github/workflows/hi3516av100_ultimate_images.yml index 851d499a..e9d90c6f 100644 --- a/.github/workflows/hi3516av100_ultimate_images.yml +++ b/.github/workflows/hi3516av100_ultimate_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/hi3516av200_images.yml b/.github/workflows/hi3516av200_images.yml index 98e2a395..0b70e3db 100644 --- a/.github/workflows/hi3516av200_images.yml +++ b/.github/workflows/hi3516av200_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/hi3516av200_ultimate_images.yml b/.github/workflows/hi3516av200_ultimate_images.yml index b2347350..63005618 100644 --- a/.github/workflows/hi3516av200_ultimate_images.yml +++ b/.github/workflows/hi3516av200_ultimate_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/hi3516av300_images.yml b/.github/workflows/hi3516av300_images.yml index ddd6796e..21eb3be1 100644 --- a/.github/workflows/hi3516av300_images.yml +++ b/.github/workflows/hi3516av300_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/hi3516cv100_images.yml b/.github/workflows/hi3516cv100_images.yml index a01d1025..d27c3307 100644 --- a/.github/workflows/hi3516cv100_images.yml +++ b/.github/workflows/hi3516cv100_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/hi3516cv200_images.yml b/.github/workflows/hi3516cv200_images.yml index dd8875e0..cfd38298 100644 --- a/.github/workflows/hi3516cv200_images.yml +++ b/.github/workflows/hi3516cv200_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/hi3516cv300_images.yml b/.github/workflows/hi3516cv300_images.yml index c295a0b5..632b6759 100644 --- a/.github/workflows/hi3516cv300_images.yml +++ b/.github/workflows/hi3516cv300_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/hi3516cv300_ultimate_images.yml b/.github/workflows/hi3516cv300_ultimate_images.yml index b03504cf..c41bd1c9 100644 --- a/.github/workflows/hi3516cv300_ultimate_images.yml +++ b/.github/workflows/hi3516cv300_ultimate_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/hi3516cv500_images.yml b/.github/workflows/hi3516cv500_images.yml index 45a2b952..00172912 100644 --- a/.github/workflows/hi3516cv500_images.yml +++ b/.github/workflows/hi3516cv500_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/hi3516dv100_images.yml b/.github/workflows/hi3516dv100_images.yml index 9702ad89..c40d7c98 100644 --- a/.github/workflows/hi3516dv100_images.yml +++ b/.github/workflows/hi3516dv100_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/hi3516dv100_ultimate_images.yml b/.github/workflows/hi3516dv100_ultimate_images.yml index 97e98d3a..6e9a027e 100644 --- a/.github/workflows/hi3516dv100_ultimate_images.yml +++ b/.github/workflows/hi3516dv100_ultimate_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/hi3516dv300_images.yml b/.github/workflows/hi3516dv300_images.yml index e14c8799..32d0803f 100644 --- a/.github/workflows/hi3516dv300_images.yml +++ b/.github/workflows/hi3516dv300_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/hi3516ev100_images.yml b/.github/workflows/hi3516ev100_images.yml index f450120a..6940e643 100644 --- a/.github/workflows/hi3516ev100_images.yml +++ b/.github/workflows/hi3516ev100_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/hi3516ev200_matrix.yml b/.github/workflows/hi3516ev200_matrix.yml index c4f340ad..6d7386d1 100644 --- a/.github/workflows/hi3516ev200_matrix.yml +++ b/.github/workflows/hi3516ev200_matrix.yml @@ -25,7 +25,7 @@ jobs: runs-on: ubuntu-latest env: - CHIP: hi3516ev200 + FAMILY: hi3516ev200 outputs: sdk-file: ${{ steps.build-sdk.outputs.sdk-file }} @@ -45,6 +45,9 @@ jobs: if [ ! -z "$ACT" ]; then apt install -y cpio rsync bc echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space @@ -59,7 +62,7 @@ jobs: run: | set -x make prepare - make BOARD=unknown_unknown_${CHIP}_openipc br-sdk + make BOARD=unknown_unknown_${FAMILY}_openipc br-sdk SDK_PATH=$(find output/images -name "*_sdk-buildroot.tar.gz") echo "SDK_PATH=$SDK_PATH" >> $GITHUB_ENV SDK_FILE=$(basename $SDK_PATH) @@ -97,9 +100,6 @@ jobs: - platform: hi3516dv200 release: ultimate - env: - HAS_NAND: ${{ matrix.release == 'ultimate' }} && (${{ matrix.platform == 'hi3516ev300' }} || ${{ matrix.platform == 'hi3516ev200' }}) - steps: - name: Checkout @@ -115,6 +115,9 @@ jobs: if [ ! -z "$ACT" ]; then apt install -y cpio rsync bc echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space @@ -144,7 +147,6 @@ jobs: echo "RELEASE_NAME=$RELEASE_NAME" >> $GITHUB_ENV echo "PRERELEASE=$PRERELEASE" >> $GITHUB_ENV echo "BRANCH=$BRANCH" >> $GITHUB_ENV - cd $GITHUB_WORKSPACE make prepare - uses: actions/download-artifact@v3 @@ -166,7 +168,6 @@ jobs: NORFW_FILE=$(basename $NORFW_PATH) echo "NORFW_FILE=$NORFW_FILE" >> $GITHUB_ENV - cd $GITHUB_WORKSPACE CONF_PATH=$(find . -name "${BOARD}_defconfig") echo Using ${{ needs.toolchain.outputs.sdk-file }} @@ -183,6 +184,9 @@ jobs: mkdir /tmp/extsdk tar xvf ${{ needs.toolchain.outputs.sdk-file }} --strip-components=1 -C /tmp/extsdk >/dev/null + HAS_NAND=$(make BOARD=${BOARD} has-nand) + echo "HAS_NAND=$HAS_NAND" >> $GITHUB_ENV + make BOARD=$BOARD all [[ $(stat --printf="%s" ${GITHUB_WORKSPACE}/output/images/uImage) -gt 3145728 ]] && echo "TG_NOTIFY=Warning, kernel size exceeded : $(stat --printf="%s" ${GITHUB_WORKSPACE}/output/images/uImage) ... ${{ matrix.platform }} (${{ matrix.release }})" >> $GITHUB_ENV && exit 1 @@ -194,8 +198,7 @@ jobs: md5sum uImage.${{ matrix.platform }} > uImage.${{ matrix.platform }}.md5sum tar -cvzf $NORFW_PATH uImage* *rootfs.squashfs.${{ matrix.platform }}* - # TODO: infer from configs - if [ "$HAS_NAND" == "true" ]; then + if [ "$HAS_NAND" == "y" ]; then NANDFW_PATH="${GITHUB_WORKSPACE}/output/images/openipc.${{ matrix.platform }}-nand-br.tgz" echo "NANDFW_PATH=$NANDFW_PATH" >> $GITHUB_ENV NANDFW_FILE=$(basename $NANDFW_PATH) @@ -223,7 +226,6 @@ jobs: - name: Create release if: ${{ !env.ACT && github.event_name != 'pull_request' }} uses: actions/create-release@v1 - continue-on-error: true env: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} with: @@ -235,7 +237,6 @@ jobs: - name: Upload NOR FW to release if: ${{ !env.ACT && github.event_name != 'pull_request' }} uses: svenstaro/upload-release-action@v2 - continue-on-error: true with: repo_token: ${{ secrets.GITHUB_TOKEN }} file: ${{ env.NORFW_PATH }} @@ -244,9 +245,8 @@ jobs: overwrite: true - name: Upload NAND FW to release - if: ${{ !env.ACT && github.event_name != 'pull_request' && env.HAS_NAND }} + if: ${{ !env.ACT && github.event_name != 'pull_request' && env.HAS_NAND == 'y' }} uses: svenstaro/upload-release-action@v2 - continue-on-error: true with: repo_token: ${{ secrets.GITHUB_TOKEN }} file: ${{ env.NANDFW_PATH }} diff --git a/.github/workflows/hi3518cv100_images.yml b/.github/workflows/hi3518cv100_images.yml index d7a0dc69..224a5f9e 100644 --- a/.github/workflows/hi3518cv100_images.yml +++ b/.github/workflows/hi3518cv100_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/hi3518ev100_images.yml b/.github/workflows/hi3518ev100_images.yml index a96fcb9a..9b7dd4cb 100644 --- a/.github/workflows/hi3518ev100_images.yml +++ b/.github/workflows/hi3518ev100_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/hi3518ev200_images.yml b/.github/workflows/hi3518ev200_images.yml index b1720bb2..e9e8e457 100644 --- a/.github/workflows/hi3518ev200_images.yml +++ b/.github/workflows/hi3518ev200_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/hi3518ev200_ultimate_images.yml b/.github/workflows/hi3518ev200_ultimate_images.yml index 71da0567..dd6918df 100644 --- a/.github/workflows/hi3518ev200_ultimate_images.yml +++ b/.github/workflows/hi3518ev200_ultimate_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/hi3519v101_images.yml b/.github/workflows/hi3519v101_images.yml index aef842dc..839c0c00 100644 --- a/.github/workflows/hi3519v101_images.yml +++ b/.github/workflows/hi3519v101_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/hi3536cv100_images.yml b/.github/workflows/hi3536cv100_images.yml index 8dd2ab8e..0f44a084 100644 --- a/.github/workflows/hi3536cv100_images.yml +++ b/.github/workflows/hi3536cv100_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/hi3536dv100_images.yml b/.github/workflows/hi3536dv100_images.yml index 3ff9545b..88965cf9 100644 --- a/.github/workflows/hi3536dv100_images.yml +++ b/.github/workflows/hi3536dv100_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/msc313e_images.yml b/.github/workflows/msc313e_images.yml index cbc927b6..4cb5f783 100644 --- a/.github/workflows/msc313e_images.yml +++ b/.github/workflows/msc313e_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/msc316dc_images.yml b/.github/workflows/msc316dc_images.yml index e0cacfa0..68790ca3 100644 --- a/.github/workflows/msc316dc_images.yml +++ b/.github/workflows/msc316dc_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/msc316dm_images.yml b/.github/workflows/msc316dm_images.yml index eb25c79c..1c9a1031 100644 --- a/.github/workflows/msc316dm_images.yml +++ b/.github/workflows/msc316dm_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/nt98562_images.yml b/.github/workflows/nt98562_images.yml index ac005a15..3b4a2c7f 100644 --- a/.github/workflows/nt98562_images.yml +++ b/.github/workflows/nt98562_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/nt98566_images.yml b/.github/workflows/nt98566_images.yml index 24978aea..57571a7f 100644 --- a/.github/workflows/nt98566_images.yml +++ b/.github/workflows/nt98566_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/rv1109_images.yml b/.github/workflows/rv1109_images.yml index 9636c7ee..2a670974 100644 --- a/.github/workflows/rv1109_images.yml +++ b/.github/workflows/rv1109_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/rv1126_images.yml b/.github/workflows/rv1126_images.yml index dfacd7dd..e1e0a836 100644 --- a/.github/workflows/rv1126_images.yml +++ b/.github/workflows/rv1126_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/ssc325_images.yml b/.github/workflows/ssc325_images.yml index dd80a47c..2e7417e1 100644 --- a/.github/workflows/ssc325_images.yml +++ b/.github/workflows/ssc325_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/ssc335_images.yml b/.github/workflows/ssc335_images.yml index 609ee90e..5fced6e6 100644 --- a/.github/workflows/ssc335_images.yml +++ b/.github/workflows/ssc335_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/ssc335de_images.yml b/.github/workflows/ssc335de_images.yml index f554ffa8..141d0970 100644 --- a/.github/workflows/ssc335de_images.yml +++ b/.github/workflows/ssc335de_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/ssc337_images.yml b/.github/workflows/ssc337_images.yml index 64aeaaa0..a17f6cbe 100644 --- a/.github/workflows/ssc337_images.yml +++ b/.github/workflows/ssc337_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/ssc337de_images.yml b/.github/workflows/ssc337de_images.yml index 8078397a..4635ff59 100644 --- a/.github/workflows/ssc337de_images.yml +++ b/.github/workflows/ssc337de_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/t10_images.yml b/.github/workflows/t10_images.yml index 599c068c..11f92026 100644 --- a/.github/workflows/t10_images.yml +++ b/.github/workflows/t10_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/t20_images.yml b/.github/workflows/t20_images.yml index e2204f9e..32203c90 100644 --- a/.github/workflows/t20_images.yml +++ b/.github/workflows/t20_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/t21_images.yml b/.github/workflows/t21_images.yml index 83f91c72..adaedc56 100644 --- a/.github/workflows/t21_images.yml +++ b/.github/workflows/t21_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/t31_images.yml b/.github/workflows/t31_images.yml index a8470931..df36c77c 100644 --- a/.github/workflows/t31_images.yml +++ b/.github/workflows/t31_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/xm510_images.yml b/.github/workflows/xm510_images.yml index 917953aa..43fbd032 100644 --- a/.github/workflows/xm510_images.yml +++ b/.github/workflows/xm510_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/xm530_images.yml b/.github/workflows/xm530_images.yml index 7d9f6db2..8e0d79b1 100644 --- a/.github/workflows/xm530_images.yml +++ b/.github/workflows/xm530_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/.github/workflows/xm550_images.yml b/.github/workflows/xm550_images.yml index 261262cc..cd9baee7 100644 --- a/.github/workflows/xm550_images.yml +++ b/.github/workflows/xm550_images.yml @@ -30,6 +30,9 @@ jobs: echo "FORCE_UNSAFE_CONFIGURE=1" >> $GITHUB_ENV # Mitigate #325 issue apt install -y pip && pip install cmake + else + # https://github.com/actions/runner-images/issues/2577 + echo "1.1.1.1 invisible-mirror.net" | sudo tee -a /etc/hosts fi - name: Free disk space diff --git a/Makefile b/Makefile index c673300e..7afa87dc 100644 --- a/Makefile +++ b/Makefile @@ -67,6 +67,8 @@ install-deps: $(eval CHIP := $(shell echo $@ | cut -d "_" -f 3)) @cat $(BR_EXT_DIR)/board/$(FAMILY)/$(CHIP).config +has-nand: + @sed -rn "s/^BR2_TARGET_ROOTFS_UBI=(y)/\1/p" $(FULL_PATH) list-configs: @echo diff --git a/br-ext-chip-hisilicon/configs/unknown_unknown_hi3516cv500_ltv_defconfig b/br-ext-chip-hisilicon/configs/unknown_unknown_hi3516cv500_ltv_defconfig deleted file mode 100644 index 2249fce1..00000000 --- a/br-ext-chip-hisilicon/configs/unknown_unknown_hi3516cv500_ltv_defconfig +++ /dev/null @@ -1,100 +0,0 @@ -# Architecture -BR2_arm=y -BR2_cortex_a7=y -BR2_ARM_EABI=y -BR2_ARM_FPU_NEON_VFPV4=y -BR2_ARM_INSTRUCTIONS_THUMB2=y -BR2_KERNEL_HEADERS_VERSION=y -BR2_DEFAULT_KERNEL_VERSION="4.9.37" -BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_9=y - -# Toolchain -BR2_PER_PACKAGE_DIRECTORIES=y -BR2_GCC_VERSION_8_X=y -BR2_TOOLCHAIN_USES_GLIBC=y -BR2_TOOLCHAIN_BUILDROOT_GLIBC=y -BR2_TOOLCHAIN_BUILDROOT_LIBC="glibc" -BR2_TOOLCHAIN_BUILDROOT_CXX=y -BR2_TOOLCHAIN_BUILDROOT_LOCALE=y -BR2_TOOLCHAIN_BUILDROOT_USE_SSP=y - -# Kernel -BR2_LINUX_KERNEL=y -BR2_LINUX_KERNEL_CUSTOM_VERSION=y -BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.9.37" -BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y -BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_HISILICON_PATH)/board/hi3516cv500/kernel/hi3516cv500.generic.config" -BR2_LINUX_KERNEL_UIMAGE=y -BR2_LINUX_KERNEL_XZ=y -BR2_LINUX_KERNEL_EXT_HISI_PATCHER=y -BR2_LINUX_KERNEL_EXT_HISI_PATCHER_LIST="$(BR2_EXTERNAL_HISILICON_PATH)/board/hi3516cv500/kernel/patches/ $(BR2_EXTERNAL_HISILICON_PATH)/board/hi3516cv500/kernel/overlay" - -# Filesystem -# BR2_TARGET_TZ_INFO is not set -BR2_TARGET_ROOTFS_CPIO=y -BR2_TARGET_ROOTFS_SQUASHFS=y -BR2_TARGET_ROOTFS_SQUASHFS4_XZ=y -BR2_ROOTFS_OVERLAY="$(TOPDIR)/../general/overlay" -BR2_ROOTFS_POST_BUILD_SCRIPT="$(TOPDIR)/../scripts/executing_commands_for_$(BR2_TOOLCHAIN_BUILDROOT_LIBC).sh" - -# OpenIPC configuration -BR2_TOOLCHAIN_BUILDROOT_VENDOR="openipc" -BR2_TARGET_GENERIC_ISSUE="Welcome to OpenIPC v2.2" -BR2_TARGET_GENERIC_HOSTNAME="openipc-hi3516cv500-ltv" -BR2_GLOBAL_PATCH_DIR="$(TOPDIR)/../general/package/all-patches" - -# OpenIPC packages -BR2_PACKAGE_BUSYBOX_CONFIG="$(TOPDIR)/../general/package/busybox/busybox.config" -BR2_PACKAGE_DROPBEAR_OPENIPC=y -BR2_PACKAGE_FDK_AAC_OPENIPC=y -BR2_PACKAGE_FWPRINTENV_OPENIPC=y -BR2_PACKAGE_HASERL=y -BR2_PACKAGE_HISI_GPIO is not set -BR2_PACKAGE_HISILICON_OSDRV_HI3516CV500=y -BR2_PACKAGE_IPCTOOL=y -BR2_PACKAGE_JSON_C=y -BR2_PACKAGE_LAME_OPENIPC=y -BR2_PACKAGE_LIBCURL_OPENIPC=y -BR2_PACKAGE_LIBCURL_OPENIPC_CURL=y -# BR2_PACKAGE_LIBCURL_OPENIPC_VERBOSE is not set -# BR2_PACKAGE_LIBCURL_OPENIPC_PROXY_SUPPORT is not set -# BR2_PACKAGE_LIBCURL_OPENIPC_COOKIES_SUPPORT is not set -# BR2_PACKAGE_LIBCURL_OPENIPC_EXTRA_PROTOCOLS_FEATURES is not set -BR2_PACKAGE_LIBCURL_OPENIPC_MBEDTLS=y -BR2_PACKAGE_LIBEVENT_OPENIPC=y -BR2_PACKAGE_LIBEVENT_OPENIPC_REMOVE_PYSCRIPT=y -BR2_PACKAGE_LIBOGG_OPENIPC=y -BR2_PACKAGE_LIBWEBSOCKETS_OPENIPC=y -BR2_PACKAGE_LIBYAML=y -BR2_PACKAGE_MAJESTIC_FONTS=y -BR2_PACKAGE_MAJESTIC=y -BR2_PACKAGE_MBEDTLS_OPENIPC=y -# BR2_PACKAGE_MBEDTLS_OPENIPC_PROGRAMS is not set -# BR2_PACKAGE_MBEDTLS_OPENIPC_COMPRESSION is not set -BR2_PACKAGE_MICROBE_WEB=y -# BR2_PACKAGE_MINI_SNMPD is not set -BR2_PACKAGE_MOTORS=y -BR2_PACKAGE_OPUS_OPENIPC=y -BR2_PACKAGE_OPUS_OPENIPC_FIXED_POINT=y -# BR2_PACKAGE_SSHPASS is not set -BR2_PACKAGE_UACME_OPENIPC=y -BR2_PACKAGE_VTUND_OPENIPC=y -BR2_PACKAGE_YAML_CLI=y - -# WiFi -BR2_PACKAGE_WIRELESS_TOOLS=y -BR2_PACKAGE_WPA_SUPPLICANT=y -BR2_PACKAGE_WPA_SUPPLICANT_CLI=y -BR2_PACKAGE_WPA_SUPPLICANT_NL80211=y -BR2_PACKAGE_WPA_SUPPLICANT_PASSPHRASE=y -BR2_PACKAGE_LINUX_FIRMWARE_OPENIPC=y -BR2_PACKAGE_LINUX_FIRMWARE_OPENIPC_MT7601U=y -# BR2_PACKAGE_RTL8188EU is not set - -# WIREGUARD -BR2_PACKAGE_WIREGUARD_LINUX_COMPAT=y -BR2_PACKAGE_WIREGUARD_TOOLS=y - -# DEBUG -BR2_PACKAGE_HOST_GDB=y -BR2_PACKAGE_GDB=y diff --git a/br-ext-chip-hisilicon/configs/unknown_unknown_hi3516ev200_dozor_defconfig b/br-ext-chip-hisilicon/configs/unknown_unknown_hi3516ev200_dozor_defconfig deleted file mode 100644 index 292c686f..00000000 --- a/br-ext-chip-hisilicon/configs/unknown_unknown_hi3516ev200_dozor_defconfig +++ /dev/null @@ -1,103 +0,0 @@ -# Architecture -BR2_arm=y -BR2_cortex_a7=y -BR2_ARM_EABI=y -BR2_ARM_FPU_NEON_VFPV4=y -BR2_ARM_INSTRUCTIONS_THUMB2=y -BR2_KERNEL_HEADERS_VERSION=y -BR2_DEFAULT_KERNEL_VERSION="4.9.37" -BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_9=y - -# Toolchain -BR2_PER_PACKAGE_DIRECTORIES=y -BR2_GCC_VERSION_8_X=y -# BR2_TOOLCHAIN_USES_UCLIBC is not set -# BR2_TOOLCHAIN_BUILDROOT_UCLIBC is not set -# BR2_TOOLCHAIN_BUILDROOT_LIBC="uclibc" -BR2_TOOLCHAIN_USES_MUSL=y -BR2_TOOLCHAIN_BUILDROOT_MUSL=y -BR2_TOOLCHAIN_BUILDROOT_LIBC="musl" -BR2_TOOLCHAIN_BUILDROOT_CXX=y -BR2_TOOLCHAIN_BUILDROOT_LOCALE=y -BR2_TOOLCHAIN_BUILDROOT_USE_SSP=y - -# Kernel -BR2_LINUX_KERNEL=y -BR2_LINUX_KERNEL_CUSTOM_VERSION=y -BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.9.37" -BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y -BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_HISILICON_PATH)/board/hi3516ev200/kernel/hi3516ev200.generic.config" -BR2_LINUX_KERNEL_UIMAGE=y -BR2_LINUX_KERNEL_XZ=y -BR2_LINUX_KERNEL_EXT_HISI_PATCHER=y -BR2_LINUX_KERNEL_EXT_HISI_PATCHER_LIST="$(BR2_EXTERNAL_HISILICON_PATH)/board/hi3516ev200/kernel/patches/ $(BR2_EXTERNAL_HISILICON_PATH)/board/hi3516ev200/kernel/overlay" - -# Filesystem -# BR2_TARGET_TZ_INFO is not set -BR2_TARGET_ROOTFS_CPIO=y -BR2_TARGET_ROOTFS_SQUASHFS=y -BR2_TARGET_ROOTFS_SQUASHFS4_XZ=y -BR2_ROOTFS_OVERLAY="$(TOPDIR)/../general/overlay" -BR2_ROOTFS_POST_BUILD_SCRIPT="$(TOPDIR)/../scripts/executing_commands_for_$(BR2_TOOLCHAIN_BUILDROOT_LIBC).sh" - -# OpenIPC configuration -BR2_TOOLCHAIN_BUILDROOT_VENDOR="openipc" -BR2_TARGET_GENERIC_ISSUE="Welcome to OpenIPC v2.2" -BR2_TARGET_GENERIC_HOSTNAME="openipc-hi3516ev200" -BR2_GLOBAL_PATCH_DIR="$(TOPDIR)/../general/package/all-patches" - -# OpenIPC packages -BR2_PACKAGE_BUSYBOX_CONFIG="$(TOPDIR)/../general/package/busybox/busybox.config" -BR2_PACKAGE_DROPBEAR_OPENIPC=y -# BR2_PACKAGE_FDK_AAC_OPENIPC is not set -BR2_PACKAGE_FWPRINTENV_OPENIPC=y -BR2_PACKAGE_HASERL=y -BR2_PACKAGE_HISI_GPIO is not set -BR2_PACKAGE_HISILICON_OSDRV_HI3516EV300=y -BR2_PACKAGE_IPCTOOL=y -BR2_PACKAGE_JSON_C=y -BR2_PACKAGE_LAME_OPENIPC=y -BR2_PACKAGE_LIBCURL_OPENIPC=y -BR2_PACKAGE_LIBCURL_OPENIPC_CURL=y -# BR2_PACKAGE_LIBCURL_OPENIPC_VERBOSE is not set -# BR2_PACKAGE_LIBCURL_OPENIPC_PROXY_SUPPORT is not set -# BR2_PACKAGE_LIBCURL_OPENIPC_COOKIES_SUPPORT is not set -# BR2_PACKAGE_LIBCURL_OPENIPC_EXTRA_PROTOCOLS_FEATURES is not set -BR2_PACKAGE_LIBCURL_OPENIPC_MBEDTLS=y -BR2_PACKAGE_LIBEVENT_OPENIPC=y -BR2_PACKAGE_LIBEVENT_OPENIPC_REMOVE_PYSCRIPT=y -BR2_PACKAGE_LIBOGG_OPENIPC=y -BR2_PACKAGE_LIBWEBSOCKETS_OPENIPC=y -BR2_PACKAGE_LIBYAML=y -BR2_PACKAGE_MAJESTIC_FONTS=y -BR2_PACKAGE_MAJESTIC=y -BR2_PACKAGE_MBEDTLS_OPENIPC=y -# BR2_PACKAGE_MBEDTLS_OPENIPC_PROGRAMS is not set -# BR2_PACKAGE_MBEDTLS_OPENIPC_COMPRESSION is not set -BR2_PACKAGE_MICROBE_WEB=y -# BR2_PACKAGE_MINI_SNMPD is not set -BR2_PACKAGE_MOTORS=y -BR2_PACKAGE_OPUS_OPENIPC=y -BR2_PACKAGE_OPUS_OPENIPC_FIXED_POINT=y -# BR2_PACKAGE_SSHPASS is not set -BR2_PACKAGE_UACME_OPENIPC=y -BR2_PACKAGE_VTUND_OPENIPC=y -BR2_PACKAGE_YAML_CLI=y - -# WiFi -BR2_PACKAGE_WIRELESS_TOOLS=y -BR2_PACKAGE_WPA_SUPPLICANT=y -BR2_PACKAGE_WPA_SUPPLICANT_CLI=y -BR2_PACKAGE_WPA_SUPPLICANT_NL80211=y -BR2_PACKAGE_WPA_SUPPLICANT_PASSPHRASE=y -BR2_PACKAGE_LINUX_FIRMWARE_OPENIPC=y -BR2_PACKAGE_LINUX_FIRMWARE_OPENIPC_MT7601U=y -# BR2_PACKAGE_RTL8188EU is not set - -# WIREGUARD -BR2_PACKAGE_WIREGUARD_LINUX_COMPAT=y -BR2_PACKAGE_WIREGUARD_TOOLS=y - -# DEBUG -BR2_PACKAGE_HOST_GDB=y -BR2_PACKAGE_GDB=y diff --git a/br-ext-chip-hisilicon/configs/unknown_unknown_hi3516ev200_ltv_defconfig b/br-ext-chip-hisilicon/configs/unknown_unknown_hi3516ev200_ltv_defconfig deleted file mode 100644 index cff58fac..00000000 --- a/br-ext-chip-hisilicon/configs/unknown_unknown_hi3516ev200_ltv_defconfig +++ /dev/null @@ -1,103 +0,0 @@ -# Architecture -BR2_arm=y -BR2_cortex_a7=y -BR2_ARM_EABI=y -BR2_ARM_FPU_NEON_VFPV4=y -BR2_ARM_INSTRUCTIONS_THUMB2=y -BR2_KERNEL_HEADERS_VERSION=y -BR2_DEFAULT_KERNEL_VERSION="4.9.37" -BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_9=y - -# Toolchain -BR2_PER_PACKAGE_DIRECTORIES=y -BR2_GCC_VERSION_8_X=y -# BR2_TOOLCHAIN_USES_UCLIBC is not set -# BR2_TOOLCHAIN_BUILDROOT_UCLIBC is not set -# BR2_TOOLCHAIN_BUILDROOT_LIBC="uclibc" -BR2_TOOLCHAIN_USES_MUSL=y -BR2_TOOLCHAIN_BUILDROOT_MUSL=y -BR2_TOOLCHAIN_BUILDROOT_LIBC="musl" -BR2_TOOLCHAIN_BUILDROOT_CXX=y -BR2_TOOLCHAIN_BUILDROOT_LOCALE=y -BR2_TOOLCHAIN_BUILDROOT_USE_SSP=y - -# Kernel -BR2_LINUX_KERNEL=y -BR2_LINUX_KERNEL_CUSTOM_VERSION=y -BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.9.37" -BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y -BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_HISILICON_PATH)/board/hi3516ev200/kernel/hi3516ev200.generic.config" -BR2_LINUX_KERNEL_UIMAGE=y -BR2_LINUX_KERNEL_XZ=y -BR2_LINUX_KERNEL_EXT_HISI_PATCHER=y -BR2_LINUX_KERNEL_EXT_HISI_PATCHER_LIST="$(BR2_EXTERNAL_HISILICON_PATH)/board/hi3516ev200/kernel/patches/ $(BR2_EXTERNAL_HISILICON_PATH)/board/hi3516ev200/kernel/overlay" - -# Filesystem -# BR2_TARGET_TZ_INFO is not set -BR2_TARGET_ROOTFS_CPIO=y -BR2_TARGET_ROOTFS_SQUASHFS=y -BR2_TARGET_ROOTFS_SQUASHFS4_XZ=y -BR2_ROOTFS_OVERLAY="$(TOPDIR)/../general/overlay" -BR2_ROOTFS_POST_BUILD_SCRIPT="$(TOPDIR)/../scripts/executing_commands_for_$(BR2_TOOLCHAIN_BUILDROOT_LIBC).sh" - -# OpenIPC configuration -BR2_TOOLCHAIN_BUILDROOT_VENDOR="openipc" -BR2_TARGET_GENERIC_ISSUE="Welcome to OpenIPC v2.2" -BR2_TARGET_GENERIC_HOSTNAME="openipc-hi3516ev200-ltv" -BR2_GLOBAL_PATCH_DIR="$(TOPDIR)/../general/package/all-patches" - -# OpenIPC packages -BR2_PACKAGE_BUSYBOX_CONFIG="$(TOPDIR)/../general/package/busybox/busybox.config" -BR2_PACKAGE_DROPBEAR_OPENIPC=y -# BR2_PACKAGE_FDK_AAC_OPENIPC is not set -BR2_PACKAGE_FWPRINTENV_OPENIPC=y -BR2_PACKAGE_HASERL=y -BR2_PACKAGE_HISI_GPIO is not set -BR2_PACKAGE_HISILICON_OSDRV_HI3516EV300=y -BR2_PACKAGE_IPCTOOL=y -BR2_PACKAGE_JSON_C=y -BR2_PACKAGE_LAME_OPENIPC=y -BR2_PACKAGE_LIBCURL_OPENIPC=y -BR2_PACKAGE_LIBCURL_OPENIPC_CURL=y -# BR2_PACKAGE_LIBCURL_OPENIPC_VERBOSE is not set -# BR2_PACKAGE_LIBCURL_OPENIPC_PROXY_SUPPORT is not set -# BR2_PACKAGE_LIBCURL_OPENIPC_COOKIES_SUPPORT is not set -# BR2_PACKAGE_LIBCURL_OPENIPC_EXTRA_PROTOCOLS_FEATURES is not set -BR2_PACKAGE_LIBCURL_OPENIPC_MBEDTLS=y -BR2_PACKAGE_LIBEVENT_OPENIPC=y -BR2_PACKAGE_LIBEVENT_OPENIPC_REMOVE_PYSCRIPT=y -BR2_PACKAGE_LIBOGG_OPENIPC=y -BR2_PACKAGE_LIBWEBSOCKETS_OPENIPC=y -BR2_PACKAGE_LIBYAML=y -BR2_PACKAGE_MAJESTIC_FONTS=y -BR2_PACKAGE_MAJESTIC=y -BR2_PACKAGE_MBEDTLS_OPENIPC=y -# BR2_PACKAGE_MBEDTLS_OPENIPC_PROGRAMS is not set -# BR2_PACKAGE_MBEDTLS_OPENIPC_COMPRESSION is not set -BR2_PACKAGE_MICROBE_WEB=y -# BR2_PACKAGE_MINI_SNMPD is not set -BR2_PACKAGE_MOTORS=y -BR2_PACKAGE_OPUS_OPENIPC=y -BR2_PACKAGE_OPUS_OPENIPC_FIXED_POINT=y -# BR2_PACKAGE_SSHPASS is not set -BR2_PACKAGE_UACME_OPENIPC=y -BR2_PACKAGE_VTUND_OPENIPC=y -BR2_PACKAGE_YAML_CLI=y - -# WiFi -BR2_PACKAGE_WIRELESS_TOOLS=y -BR2_PACKAGE_WPA_SUPPLICANT=y -BR2_PACKAGE_WPA_SUPPLICANT_CLI=y -BR2_PACKAGE_WPA_SUPPLICANT_NL80211=y -BR2_PACKAGE_WPA_SUPPLICANT_PASSPHRASE=y -BR2_PACKAGE_LINUX_FIRMWARE_OPENIPC=y -BR2_PACKAGE_LINUX_FIRMWARE_OPENIPC_MT7601U=y -# BR2_PACKAGE_RTL8188EU is not set - -# WIREGUARD -BR2_PACKAGE_WIREGUARD_LINUX_COMPAT=y -BR2_PACKAGE_WIREGUARD_TOOLS=y - -# DEBUG -BR2_PACKAGE_HOST_GDB=y -BR2_PACKAGE_GDB=y diff --git a/br-ext-chip-hisilicon/configs/unknown_unknown_hi3516ev200_vixand_defconfig b/br-ext-chip-hisilicon/configs/unknown_unknown_hi3516ev200_vixand_defconfig deleted file mode 100644 index 6b7f97f6..00000000 --- a/br-ext-chip-hisilicon/configs/unknown_unknown_hi3516ev200_vixand_defconfig +++ /dev/null @@ -1,110 +0,0 @@ -# Architecture -BR2_arm=y -BR2_cortex_a7=y -BR2_ARM_EABI=y -BR2_ARM_FPU_NEON_VFPV4=y -BR2_ARM_INSTRUCTIONS_THUMB2=y -BR2_KERNEL_HEADERS_VERSION=y -BR2_DEFAULT_KERNEL_VERSION="4.9.37" -BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_9=y - -# Toolchain -BR2_PER_PACKAGE_DIRECTORIES=y -BR2_GCC_VERSION_8_X=y -# BR2_TOOLCHAIN_USES_UCLIBC is not set -# BR2_TOOLCHAIN_BUILDROOT_UCLIBC is not set -# BR2_TOOLCHAIN_BUILDROOT_LIBC="uclibc" -BR2_TOOLCHAIN_USES_MUSL=y -BR2_TOOLCHAIN_BUILDROOT_MUSL=y -BR2_TOOLCHAIN_BUILDROOT_LIBC="musl" -BR2_TOOLCHAIN_BUILDROOT_CXX=y -BR2_TOOLCHAIN_BUILDROOT_LOCALE=y -BR2_TOOLCHAIN_BUILDROOT_USE_SSP=y - -# Kernel -BR2_LINUX_KERNEL=y -BR2_LINUX_KERNEL_CUSTOM_VERSION=y -BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.9.37" -BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y -BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_HISILICON_PATH)/board/hi3516ev200/kernel/hi3516ev200.generic.config" -BR2_LINUX_KERNEL_UIMAGE=y -BR2_LINUX_KERNEL_XZ=y -BR2_LINUX_KERNEL_EXT_HISI_PATCHER=y -BR2_LINUX_KERNEL_EXT_HISI_PATCHER_LIST="$(BR2_EXTERNAL_HISILICON_PATH)/board/hi3516ev200/kernel/patches/ $(BR2_EXTERNAL_HISILICON_PATH)/board/hi3516ev200/kernel/overlay" - -# Filesystem -# BR2_TARGET_TZ_INFO is not set -BR2_TARGET_ROOTFS_CPIO=y -BR2_TARGET_ROOTFS_SQUASHFS=y -BR2_TARGET_ROOTFS_SQUASHFS4_XZ=y -BR2_ROOTFS_OVERLAY="$(TOPDIR)/../general/overlay" -BR2_ROOTFS_POST_BUILD_SCRIPT="$(TOPDIR)/../scripts/executing_commands_for_$(BR2_TOOLCHAIN_BUILDROOT_LIBC).sh" - -# OpenIPC configuration -BR2_TOOLCHAIN_BUILDROOT_VENDOR="openipc" -BR2_TARGET_GENERIC_ISSUE="Welcome to OpenIPC v2.2" -BR2_TARGET_GENERIC_HOSTNAME="vixand-hi3516ev200" -BR2_GLOBAL_PATCH_DIR="$(TOPDIR)/../general/package/all-patches" - -# OpenIPC packages -BR2_PACKAGE_BUSYBOX_CONFIG="$(TOPDIR)/../general/package/busybox/busybox.config" -BR2_PACKAGE_DROPBEAR_OPENIPC=y -# BR2_PACKAGE_FDK_AAC_OPENIPC is not set -BR2_PACKAGE_FWPRINTENV_OPENIPC=y -BR2_PACKAGE_HASERL=y -BR2_PACKAGE_HISI_GPIO is not set -BR2_PACKAGE_HISILICON_OSDRV_HI3516EV300=y -BR2_PACKAGE_IPCTOOL=y -BR2_PACKAGE_JSON_C=y -BR2_PACKAGE_LAME_OPENIPC=y -BR2_PACKAGE_LIBCURL_OPENIPC=y -BR2_PACKAGE_LIBCURL_OPENIPC_CURL=y -# BR2_PACKAGE_LIBCURL_OPENIPC_VERBOSE is not set -# BR2_PACKAGE_LIBCURL_OPENIPC_PROXY_SUPPORT is not set -# BR2_PACKAGE_LIBCURL_OPENIPC_COOKIES_SUPPORT is not set -# BR2_PACKAGE_LIBCURL_OPENIPC_EXTRA_PROTOCOLS_FEATURES is not set -BR2_PACKAGE_LIBCURL_OPENIPC_MBEDTLS=y -BR2_PACKAGE_LIBEVENT_OPENIPC=y -BR2_PACKAGE_LIBEVENT_OPENIPC_REMOVE_PYSCRIPT=y -BR2_PACKAGE_LIBOGG_OPENIPC=y -BR2_PACKAGE_LIBWEBSOCKETS_OPENIPC=y -BR2_PACKAGE_LIBYAML=y -BR2_PACKAGE_MAJESTIC_FONTS=y -BR2_PACKAGE_MAJESTIC=y -BR2_PACKAGE_MBEDTLS_OPENIPC=y -# BR2_PACKAGE_MBEDTLS_OPENIPC_PROGRAMS is not set -# BR2_PACKAGE_MBEDTLS_OPENIPC_COMPRESSION is not set -BR2_PACKAGE_MICROBE_WEB=y -# BR2_PACKAGE_MINI_SNMPD is not set -BR2_PACKAGE_MOTORS=y -BR2_PACKAGE_OPUS_OPENIPC=y -BR2_PACKAGE_OPUS_OPENIPC_FIXED_POINT=y -# BR2_PACKAGE_SSHPASS is not set -BR2_PACKAGE_UACME_OPENIPC=y -BR2_PACKAGE_VTUND_OPENIPC=y -BR2_PACKAGE_YAML_CLI=y - -# WiFi -BR2_PACKAGE_WIRELESS_TOOLS=y -BR2_PACKAGE_WPA_SUPPLICANT=y -BR2_PACKAGE_WPA_SUPPLICANT_CLI=y -BR2_PACKAGE_WPA_SUPPLICANT_NL80211=y -BR2_PACKAGE_WPA_SUPPLICANT_PASSPHRASE=y -BR2_PACKAGE_LINUX_FIRMWARE_OPENIPC=y -BR2_PACKAGE_LINUX_FIRMWARE_OPENIPC_MT7601U=y -# BR2_PACKAGE_RTL8188EU is not set - -# WIREGUARD -BR2_PACKAGE_WIREGUARD_LINUX_COMPAT=y -BR2_PACKAGE_WIREGUARD_TOOLS=y - -# For Facilitator ONLY -BR2_PACKAGE_NGINX=y -BR2_PACKAGE_PHP=y -BR2_PACKAGE_PHP_EXT_JSON=y -BR2_PACKAGE_PHP_EXT_MBSTRING=y -BR2_PACKAGE_PHP_EXT_ZIP=y - -# DEBUG -BR2_PACKAGE_HOST_GDB=y -BR2_PACKAGE_GDB=y diff --git a/br-ext-chip-hisilicon/configs/unknown_unknown_hi3518ev200_domsip_defconfig b/br-ext-chip-hisilicon/configs/unknown_unknown_hi3518ev200_domsip_defconfig deleted file mode 100644 index 90da79b2..00000000 --- a/br-ext-chip-hisilicon/configs/unknown_unknown_hi3518ev200_domsip_defconfig +++ /dev/null @@ -1,103 +0,0 @@ -# Architecture -BR2_arm=y -BR2_arm926t=y -BR2_ARM_EABI=y -# BR2_ARM_INSTRUCTIONS_THUMB is not set -BR2_KERNEL_HEADERS_VERSION=y -BR2_DEFAULT_KERNEL_VERSION="4.9.37" -BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_9=y - -# Toolchain -BR2_PER_PACKAGE_DIRECTORIES=y -BR2_GCC_VERSION_8_X=y -# BR2_TOOLCHAIN_USES_UCLIBC is not set -# BR2_TOOLCHAIN_BUILDROOT_UCLIBC is not set -# BR2_TOOLCHAIN_BUILDROOT_LIBC="uclibc" -BR2_TOOLCHAIN_USES_MUSL=y -BR2_TOOLCHAIN_BUILDROOT_MUSL=y -BR2_TOOLCHAIN_BUILDROOT_LIBC="musl" -BR2_TOOLCHAIN_BUILDROOT_CXX=y -BR2_TOOLCHAIN_BUILDROOT_LOCALE=y -BR2_TOOLCHAIN_BUILDROOT_USE_SSP=y - -# Kernel -BR2_LINUX_KERNEL=y -BR2_LINUX_KERNEL_CUSTOM_VERSION=y -BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.9.37" -BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y -BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_HISILICON_PATH)/board/hi3516cv200/kernel/hi3518ev200.generic.config.no-himci" -BR2_LINUX_KERNEL_UIMAGE=y -BR2_LINUX_KERNEL_XZ=y -BR2_LINUX_KERNEL_EXT_HISI_PATCHER=y -BR2_LINUX_KERNEL_EXT_HISI_PATCHER_LIST="$(BR2_EXTERNAL_HISILICON_PATH)/board/hi3516cv200/kernel/patches/ $(BR2_EXTERNAL_HISILICON_PATH)/board/hi3516cv200/kernel/overlay" - -# Filesystem -# BR2_TARGET_TZ_INFO is not set -BR2_TARGET_ROOTFS_CPIO=y -BR2_TARGET_ROOTFS_SQUASHFS=y -BR2_TARGET_ROOTFS_SQUASHFS4_XZ=y -BR2_ROOTFS_OVERLAY="$(TOPDIR)/../general/overlay" -BR2_ROOTFS_POST_BUILD_SCRIPT="$(TOPDIR)/../scripts/executing_commands_for_$(BR2_TOOLCHAIN_BUILDROOT_LIBC).sh" - -# OpenIPC configuration -BR2_TOOLCHAIN_BUILDROOT_VENDOR="openipc" -BR2_TARGET_GENERIC_ISSUE="Welcome to OpenIPC v2.2" -BR2_TARGET_GENERIC_HOSTNAME="openipc-hi3518ev200" -BR2_GLOBAL_PATCH_DIR="$(TOPDIR)/../general/package/all-patches" - -# OpenIPC packages -BR2_PACKAGE_BUSYBOX_CONFIG="$(TOPDIR)/../general/package/busybox/busybox.config" -BR2_PACKAGE_DROPBEAR_OPENIPC=y -# BR2_PACKAGE_FDK_AAC_OPENIPC is not set -BR2_PACKAGE_FWPRINTENV_OPENIPC=y -BR2_PACKAGE_HASERL=y -BR2_PACKAGE_HISI_GPIO is not set -BR2_PACKAGE_HISILICON_OSDRV_HI3516CV200=y -BR2_PACKAGE_IPCTOOL=y -BR2_PACKAGE_JSON_C=y -BR2_PACKAGE_LAME_OPENIPC=y -BR2_PACKAGE_LIBCURL_OPENIPC=y -BR2_PACKAGE_LIBCURL_OPENIPC_CURL=y -# BR2_PACKAGE_LIBCURL_OPENIPC_VERBOSE is not set -# BR2_PACKAGE_LIBCURL_OPENIPC_PROXY_SUPPORT is not set -# BR2_PACKAGE_LIBCURL_OPENIPC_COOKIES_SUPPORT is not set -# BR2_PACKAGE_LIBCURL_OPENIPC_EXTRA_PROTOCOLS_FEATURES is not set -BR2_PACKAGE_LIBCURL_OPENIPC_MBEDTLS=y -BR2_PACKAGE_LIBEVENT_OPENIPC=y -BR2_PACKAGE_LIBEVENT_OPENIPC_REMOVE_PYSCRIPT=y -BR2_PACKAGE_LIBOGG_OPENIPC=y -BR2_PACKAGE_LIBWEBSOCKETS_OPENIPC=y -BR2_PACKAGE_LIBYAML=y -BR2_PACKAGE_MAJESTIC_FONTS=y -BR2_PACKAGE_MAJESTIC=y -BR2_PACKAGE_MBEDTLS_OPENIPC=y -# BR2_PACKAGE_MBEDTLS_OPENIPC_PROGRAMS is not set -# BR2_PACKAGE_MBEDTLS_OPENIPC_COMPRESSION is not set -BR2_PACKAGE_MICROBE_WEB=y -# BR2_PACKAGE_MINI_SNMPD is not set -BR2_PACKAGE_MOTORS=y -BR2_PACKAGE_OPUS_OPENIPC=y -BR2_PACKAGE_OPUS_OPENIPC_FIXED_POINT=y -# BR2_PACKAGE_SSHPASS is not set -BR2_PACKAGE_UACME_OPENIPC=y -BR2_PACKAGE_VTUND_OPENIPC=y -BR2_PACKAGE_YAML_CLI=y - -# WiFi -BR2_PACKAGE_WIRELESS_TOOLS=y -BR2_PACKAGE_WPA_SUPPLICANT=y -BR2_PACKAGE_WPA_SUPPLICANT_CLI=y -BR2_PACKAGE_WPA_SUPPLICANT_NL80211=y -BR2_PACKAGE_WPA_SUPPLICANT_PASSPHRASE=y -BR2_PACKAGE_LINUX_FIRMWARE_OPENIPC=y -BR2_PACKAGE_LINUX_FIRMWARE_OPENIPC_MT7601U=y -BR2_PACKAGE_LINUX_FIRMWARE_OPENIPC_RTL8188EU=y -# BR2_PACKAGE_RTL8188EU is not set - -# WIREGUARD -BR2_PACKAGE_WIREGUARD_LINUX_COMPAT=y -BR2_PACKAGE_WIREGUARD_TOOLS=y - -# DEBUG -BR2_PACKAGE_HOST_GDB=y -BR2_PACKAGE_GDB=y diff --git a/br-ext-chip-hisilicon/configs/unknown_unknown_hi3536dv100_vixand_defconfig b/br-ext-chip-hisilicon/configs/unknown_unknown_hi3536dv100_vixand_defconfig index 4bd9a6f6..623ba28f 100644 --- a/br-ext-chip-hisilicon/configs/unknown_unknown_hi3536dv100_vixand_defconfig +++ b/br-ext-chip-hisilicon/configs/unknown_unknown_hi3536dv100_vixand_defconfig @@ -97,7 +97,8 @@ BR2_PACKAGE_WIREGUARD_LINUX_COMPAT=y BR2_PACKAGE_WIREGUARD_TOOLS=y # For Facilitator "Vasiliy" ONLY -BR2_PACKAGE_PHPy +# BR2_PACKAGE_NGINX is not set +BR2_PACKAGE_PHP=y BR2_PACKAGE_PHP_EXT_JSON=y BR2_PACKAGE_PHP_EXT_ZIP=y BR2_PACKAGE_UHTTPD=y diff --git a/br-ext-chip-ingenic/board/t31/kernel/t31.generic.config b/br-ext-chip-ingenic/board/t31/kernel/t31.generic.config index 93c53b92..53515c62 100644 --- a/br-ext-chip-ingenic/board/t31/kernel/t31.generic.config +++ b/br-ext-chip-ingenic/board/t31/kernel/t31.generic.config @@ -858,7 +858,7 @@ CONFIG_RTL8192C_COMMON=m # CONFIG_BCM43341 is not set # CONFIG_BCMDHD_1_141_66 is not set # CONFIG_BCMDHD_AP6181 is not set -# CONFIG_MT7601_STA is not set +CONFIG_MT7601_STA=y # # Enable WiMAX (Networking options) to see the WiMAX drivers diff --git a/br-ext-chip-ingenic/configs/unknown_unknown_t31_vixand_defconfig.high b/br-ext-chip-ingenic/configs/unknown_unknown_t31_vixand_defconfig.high deleted file mode 100644 index 4c8bc587..00000000 --- a/br-ext-chip-ingenic/configs/unknown_unknown_t31_vixand_defconfig.high +++ /dev/null @@ -1,119 +0,0 @@ -# Architecture -BR2_mipsel=y -BR2_mips_xburst=y -# BR2_MIPS_SOFT_FLOAT is not set -BR2_MIPS_FP32_MODE_32=y -# BR2_MIPS_FP32_MODE_XX is not set -BR2_MIPS_NAN_LEGACY=y -BR2_MIPS_OABI32=y -BR2_KERNEL_HEADERS_VERSION=y -BR2_DEFAULT_KERNEL_VERSION="3.10.14" -BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_3_10=y - -# Toolchain -BR2_PER_PACKAGE_DIRECTORIES=y -BR2_GCC_VERSION_8_X=y -BR2_TOOLCHAIN_USES_UCLIBC=y -BR2_TOOLCHAIN_BUILDROOT_UCLIBC=y -BR2_TOOLCHAIN_BUILDROOT_LIBC="uclibc" -BR2_EXTRA_GCC_CONFIG_OPTIONS="--with-float=hard" -# BR2_TOOLCHAIN_USES_MUSL is not set -# BR2_TOOLCHAIN_BUILDROOT_MUSL is not set -# BR2_TOOLCHAIN_BUILDROOT_LIBC="musl" -BR2_TOOLCHAIN_BUILDROOT_CXX=y -BR2_TOOLCHAIN_BUILDROOT_LOCALE=y -BR2_TOOLCHAIN_BUILDROOT_USE_SSP=y - -# Kernel -BR2_LINUX_KERNEL=y -BR2_LINUX_KERNEL_CUSTOM_VERSION=y -BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="3.10.14" -BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y -BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_INGENIC_PATH)/board/t31/kernel/t31.generic.config.vixand" -BR2_LINUX_KERNEL_UIMAGE=y -BR2_LINUX_KERNEL_LZMA=y -BR2_LINUX_KERNEL_EXT_INGENIC_PATCHER=y -BR2_LINUX_KERNEL_EXT_INGENIC_PATCHER_LIST="$(BR2_EXTERNAL_INGENIC_PATH)/board/t31/kernel/patches/ $(BR2_EXTERNAL_INGENIC_PATH)/board/t31/kernel/overlay" - -# Filesystem -# BR2_TARGET_TZ_INFO is not set -BR2_TARGET_ROOTFS_CPIO=y -BR2_TARGET_ROOTFS_SQUASHFS=y -BR2_TARGET_ROOTFS_SQUASHFS4_XZ=y -BR2_ROOTFS_OVERLAY="$(TOPDIR)/../general/overlay" -BR2_ROOTFS_POST_BUILD_SCRIPT="$(TOPDIR)/../scripts/executing_commands_for_$(BR2_TOOLCHAIN_BUILDROOT_LIBC).sh" - -# OpenIPC configuration -BR2_TOOLCHAIN_BUILDROOT_VENDOR="openipc" -BR2_TARGET_GENERIC_ISSUE="Welcome to OpenIPC v2.2" -BR2_TARGET_GENERIC_HOSTNAME="vixand-t31" -BR2_GLOBAL_PATCH_DIR="$(TOPDIR)/../general/package/all-patches" - -# OpenIPC packages -BR2_PACKAGE_BUSYBOX_CONFIG="$(TOPDIR)/../general/package/busybox/busybox.config" -BR2_PACKAGE_DROPBEAR_OPENIPC=y -# BR2_PACKAGE_FDK_AAC_OPENIPC is not set -BR2_PACKAGE_FWPRINTENV_OPENIPC=y -BR2_PACKAGE_INGENIC_OSDRV_T31=y -BR2_PACKAGE_HASERL=y -# BR2_PACKAGE_HISI_GPIO is not set -BR2_PACKAGE_IPCTOOL=y -BR2_PACKAGE_JSON_C=y -BR2_PACKAGE_LAME_OPENIPC=y -BR2_PACKAGE_LIBCURL_OPENIPC=y -BR2_PACKAGE_LIBCURL_OPENIPC_CURL=y -# BR2_PACKAGE_LIBCURL_OPENIPC_VERBOSE is not set -# BR2_PACKAGE_LIBCURL_OPENIPC_PROXY_SUPPORT is not set -# BR2_PACKAGE_LIBCURL_OPENIPC_COOKIES_SUPPORT is not set -# BR2_PACKAGE_LIBCURL_OPENIPC_EXTRA_PROTOCOLS_FEATURES is not set -BR2_PACKAGE_LIBCURL_OPENIPC_MBEDTLS=y -BR2_PACKAGE_LIBEVENT_OPENIPC=y -BR2_PACKAGE_LIBEVENT_OPENIPC_REMOVE_PYSCRIPT=y -BR2_PACKAGE_LIBOGG_OPENIPC=y -BR2_PACKAGE_LIBWEBSOCKETS_OPENIPC=y -BR2_PACKAGE_LIBYAML=y -# BR2_PACKAGE_MAJESTIC_FONTS is not set -BR2_PACKAGE_MAJESTIC=y -BR2_PACKAGE_MBEDTLS_OPENIPC=y -# BR2_PACKAGE_MBEDTLS_OPENIPC_PROGRAMS is not set -# BR2_PACKAGE_MBEDTLS_OPENIPC_COMPRESSION is not set -BR2_PACKAGE_MICROBE_WEB=y -# BR2_PACKAGE_MINI_SNMPD is not set -# BR2_PACKAGE_MOTORS is not set -BR2_PACKAGE_OPUS_OPENIPC=y -BR2_PACKAGE_OPUS_OPENIPC_FIXED_POINT=y -# BR2_PACKAGE_SSHPASS is not set -BR2_PACKAGE_UACME_OPENIPC=y -BR2_PACKAGE_VTUND_OPENIPC=y -BR2_PACKAGE_YAML_CLI=y - -# WiFi -# BR2_PACKAGE_WIRELESS_TOOLS is not set -# BR2_PACKAGE_WPA_SUPPLICANT is not set -# BR2_PACKAGE_WPA_SUPPLICANT_CLI is not set -# BR2_PACKAGE_WPA_SUPPLICANT_NL80211 is not set -# BR2_PACKAGE_WPA_SUPPLICANT_PASSPHRASE is not set -# BR2_PACKAGE_LINUX_FIRMWARE_OPENIPC is not set -# BR2_PACKAGE_LINUX_FIRMWARE_OPENIPC_MT7601U is not set -# BR2_PACKAGE_RTL8188EU is not set - -# WIREGUARD -# BR2_PACKAGE_WIREGUARD_LINUX_COMPAT is not set -# BR2_PACKAGE_WIREGUARD_TOOLS is not set - -# MQTT -BR2_PACKAGE_MOSQUITTO=y -# BR2_PACKAGE_MOSQUITTO_BROKER is not set - -# For Facilitator "Vasiliy" ONLY -BR2_PACKAGE_PHP=y -BR2_PACKAGE_PHP_EXT_JSON=y -BR2_PACKAGE_PHP_EXT_ZIP=y -BR2_PACKAGE_UHTTPD=y - -# Optional packages -BR2_PACKAGE_PPPD=y - -# DEBUG -BR2_PACKAGE_HOST_GDB=y -BR2_PACKAGE_GDB=y diff --git a/br-ext-chip-sigmastar/board/infinity6b0/kernel/overlay/drivers/sstar/gpio/infinity6b0/mhal_pinmux.c b/br-ext-chip-sigmastar/board/infinity6b0/kernel/overlay/drivers/sstar/gpio/infinity6b0/mhal_pinmux.c new file mode 100644 index 00000000..c9a22007 --- /dev/null +++ b/br-ext-chip-sigmastar/board/infinity6b0/kernel/overlay/drivers/sstar/gpio/infinity6b0/mhal_pinmux.c @@ -0,0 +1,1359 @@ +/* +* mhal_pinmux.c- Sigmastar +* +* Copyright (C) 2018 Sigmastar Technology Corp. +* +* Author: karl.xiao +* +* This software is licensed under the terms of the GNU General Public +* License version 2, as published by the Free Software Foundation, and +* may be copied, distributed, and modified under those terms. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +*/ +#include "ms_platform.h" +#include "mdrv_types.h" +#include "mhal_gpio.h" +#include "padmux.h" +#include "gpio.h" + +//============================================================================== +// +// MACRO DEFINE +// +//============================================================================== + +#define BASE_RIU_PA 0xFD000000 +#define PMSLEEP_BANK 0x000E00 +#define SAR_BANK 0x001400 +#define ALBANY1_BANK 0x003200 +#define ALBANY2_BANK 0x003300 +#define CHIPTOP_BANK 0x101E00 +#define UTMI0_BANK 0x142100 + +#define _GPIO_W_WORD(addr,val) {(*(volatile u16*)(addr)) = (u16)(val);} +#define _GPIO_W_WORD_MASK(addr,val,mask) {(*(volatile u16*)(addr)) = ((*(volatile u16*)(addr)) & ~(mask)) | ((u16)(val) & (mask));} +#define _GPIO_R_BYTE(addr) (*(volatile u8*)(addr)) +#define _GPIO_R_WORD_MASK(addr,mask) ((*(volatile u16*)(addr)) & (mask)) + +#define GET_BASE_ADDR_BY_BANK(x, y) ((x) + ((y) << 1)) +#define _RIUA_8BIT(bank , offset) GET_BASE_ADDR_BY_BANK(BASE_RIU_PA, bank) + (((offset) & ~1)<<1) + ((offset) & 1) +#define _RIUA_16BIT(bank , offset) GET_BASE_ADDR_BY_BANK(BASE_RIU_PA, bank) + ((offset)<<2) + +/* Non PM Pad : CHIPTOP_BANK */ +#define REG_PWM5_MODE 0x02 + #define REG_PWM5_MODE_MASK BIT2|BIT1|BIT0 +#define REG_PWM6_MODE 0x02 + #define REG_PWM6_MODE_MASK BIT5|BIT4|BIT3 +#define REG_PWM7_MODE 0x02 + #define REG_PWM7_MODE_MASK BIT8|BIT7|BIT6 +#define REG_PWM8_MODE 0x02 + #define REG_PWM8_MODE_MASK BIT11|BIT10|BIT9 +#define REG_PWM9_MODE 0x02 + #define REG_PWM9_MODE_MASK BIT14|BIT13|BIT12 +#define REG_FUART_MODE 0x03 + #define REG_FUART_MODE_MASK BIT2|BIT1|BIT0 +#define REG_UART0_MODE 0x03 + #define REG_UART0_MODE_MASK BIT6|BIT5|BIT4 +#define REG_UART1_MODE 0x03 + #define REG_UART1_MODE_MASK BIT10|BIT9|BIT8 +#define REG_PWM10_MODE 0x04 + #define REG_PWM10_MODE_MASK BIT2|BIT1|BIT0 +#define REG_SR_MODE 0x06 + #define REG_SR_MODE_MASK BIT2|BIT1|BIT0 +#define REG_SR_I2C_MODE 0x06 + #define REG_SR_I2C_MODE_MASK BIT5|BIT4 +#define REG_SR_HVSYNC_MODE 0x06 + #define REG_SR_HVSYNC_MODE_MASK BIT6 +#define REG_SR_MCLK_MODE 0x06 + #define REG_SR_MCLK_MODE_MASK BIT7 +#define REG_SR_PCK_MODE 0x06 + #define REG_SR_PCK_MODE_MASK BIT8 +#define REG_SR_PDN_MODE 0x06 + #define REG_SR_PDN_MODE_MASK BIT10|BIT9 +#define REG_SR_RST_MODE 0x06 + #define REG_SR_RST_MODE_MASK BIT12|BIT11 +#define REG_PWM0_MODE 0x07 + #define REG_PWM0_MODE_MASK BIT2|BIT1|BIT0 +#define REG_PWM1_MODE 0x07 + #define REG_PWM1_MODE_MASK BIT5|BIT4|BIT3 +#define REG_PWM2_MODE 0x07 + #define REG_PWM2_MODE_MASK BIT8|BIT7|BIT6 +#define REG_PWM3_MODE 0x07 + #define REG_PWM3_MODE_MASK BIT11|BIT10|BIT9 +#define REG_PWM4_MODE 0x07 + #define REG_PWM4_MODE_MASK BIT14|BIT13|BIT12 +#define REG_NAND_MODE 0x08 + #define REG_NAND_MODE_MASK BIT0 +#define REG_SD_MODE 0x08 + #define REG_SD_MODE_MASK BIT3|BIT2 +#define REG_SDIO_MODE 0x08 + #define REG_SDIO_MODE_MASK BIT8 +#define REG_I2C0_MODE 0x09 + #define REG_I2C0_MODE_MASK BIT2|BIT1|BIT0 +#define REG_I2C1_MODE 0x09 + #define REG_I2C1_MODE_MASK BIT5|BIT4 +#define REG_SPI0_MODE 0x0c + #define REG_SPI0_MODE_MASK BIT2|BIT1|BIT0 +#define REG_SPI1_MODE 0x0c + #define REG_SPI1_MODE_MASK BIT6|BIT5|BIT4 +#define REG_EJ_MODE 0x0f + #define REG_EJ_MODE_MASK BIT1|BIT0 +#define REG_ETH_MODE 0x0f + #define REG_ETH_MODE_MASK BIT2 +#define REG_CCIR_MODE 0x0f + #define REG_CCIR_MODE_MASK BIT5|BIT4 +#define REG_TTL_MODE 0x0f + #define REG_TTL_MODE_MASK BIT7|BIT6 +#define REG_DMIC_MODE 0x0f + #define REG_DMIC_MODE_MASK BIT9|BIT8 +#define REG_I2S_MODE 0x0f + #define REG_I2S_MODE_MASK BIT11|BIT10 +#define REG_TEST_IN_MODE 0x12 + #define REG_TEST_IN_MODE_MASK BIT1|BIT0 +#define REG_TEST_OUT_MODE 0x12 + #define REG_TEST_OUT_MODE_MASK BIT5|BIT4 +#define REG_EMMC_MODE 0x13 + #define REG_EMMC_MODE_MASK BIT0 +#define REG_EMMC_RSTN_EN 0x13 + #define REG_EMMC_RSTN_EN_MASK BIT1 +#define REG_MIPI_PAD_IN 0x33 + #define REG_MIPI_PAD_IN_MASK BIT1|BIT0 +#define REG_ALLPAD_IN 0x50 + #define REG_ALLPAD_IN_MASK BIT15 + +/* PM Sleep : PMSLEEP_BANK */ +#define REG_PM_GPIO_PM_LOCK 0x12 + #define REG_PM_GPIO_PM_LOCK_MASK 0xFFFF +#define REG_PM_GPIO_PM4_INV 0x1c + #define REG_PM_GPIO_PM4_INV_MASK BIT1 +#define REG_PM_LINK_WKINT2GPIO4 0x1c + #define REG_PM_LINK_WKINT2GPIO4_MASK BIT3 +#define REG_PM_IR_IS_GPIO 0x1c + #define REG_PM_IR_IS_GPIO_MASK BIT4 +#define REG_PM_PWM0_MODE 0x28 + #define REG_PM_PWM0_MODE_MASK BIT1|BIT0 +#define REG_PM_PWM1_MODE 0x28 + #define REG_PM_PWM1_MODE_MASK BIT3|BIT2 +#define REG_PM_PWM2_MODE 0x28 + #define REG_PM_PWM2_MODE_MASK BIT7|BIT6 +#define REG_PM_PWM3_MODE 0x28 + #define REG_PM_PWM3_MODE_MASK BIT9|BIT8 +#define REG_PM_PWM4_MODE 0x27 + #define REG_PM_PWM4_MODE_MASK BIT0 +#define REG_PM_PWM5_MODE 0x27 + #define REG_PM_PWM5_MODE_MASK BIT1 +#define REG_PM_PWM8_MODE 0x27 + #define REG_PM_PWM8_MODE_MASK BIT2 +#define REG_PM_PWM9_MODE 0x27 + #define REG_PM_PWM9_MODE_MASK BIT3 +#define REG_PM_PWM10_MODE 0x27 + #define REG_PM_PWM10_MODE_MASK BIT4 +#define REG_PM_UART1_MODE 0x27 + #define REG_PM_UART1_MODE_MASK BIT8 +#define REG_PM_LED_MODE 0x28 + #define REG_PM_LED_MODE_MASK BIT5|BIT4 + +#define REG_PM_VID_MODE 0x28 + #define REG_PM_VID_MODE_MASK BIT13|BIT12 +#define REG_PM_SD_CDZ_MODE 0x28 + #define REG_PM_SD_CDZ_MODE_MASK BIT14 +#define REG_PM_SPI_IS_GPIO 0x35 + #define REG_PM_SPI_IS_GPIO_MASK BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0 + #define REG_PM_SPI_GPIO_MASK BIT0 + #define REG_PM_SPICSZ1_GPIO_MASK BIT2 + #define REG_PM_SPICSZ2_GPIO_MASK BIT3 + #define REG_PM_SPIWPN_GPIO_MASK BIT4 + #define REG_PM_SPIHOLDN_MODE_MASK BIT6 | BIT7 +#define REG_PM_SPICSZ1_GPIO REG_PM_SPI_IS_GPIO +#define REG_PM_SPICSZ2_GPIO REG_PM_SPI_IS_GPIO +#define REG_PM_SPI_GPIO REG_PM_SPI_IS_GPIO +#define REG_PM_SPIWPN_GPIO REG_PM_SPI_IS_GPIO +#define REG_PM_SPIHOLDN_MODE REG_PM_SPI_IS_GPIO + +#define REG_PM_UART_IS_GPIO 0x35 + #define REG_PM_UART_IS_GPIO_MASK BIT11|BIT10|BIT9|BIT8 + +/* SAR : SAR_BANK, R/W 8-bits */ +#define REG_SAR_AISEL_8BIT 0x11*2 + #define REG_SAR_CH0_AISEL BIT0 + #define REG_SAR_CH1_AISEL BIT1 + #define REG_SAR_CH2_AISEL BIT2 + #define REG_SAR_CH3_AISEL BIT3 + +/* EMAC : ALBANY1_BANK */ +#define REG_ATOP_RX_INOFF 0x69 + #define REG_ATOP_RX_INOFF_MASK BIT15|BIT14 + +/* EMAC : ALBANY2_BANK */ +#define REG_ETH_GPIO_EN 0x71 + #define REG_ETH_GPIO_EN_MASK BIT3|BIT2|BIT1|BIT0 + +/* UTMI0 : UTMI0_BANK */ +#define REG_UTMI0_FL_XVR_PDN 0x0 + #define REG_UTMI0_FL_XVR_PDN_MASK BIT12 +#define REG_UTMI0_REG_PDN 0x0 + #define REG_UTMI0_REG_PDN_MASK BIT15 // 1: power doen 0: enable +#define REG_UTMI0_CLK_EXTRA0_EN 0x4 + #define REG_UTMI0_CLK_EXTRA0_EN_MASK BIT7 // 1: power down 0: enable +#define REG_UTMI0_GPIO_EN 0x1f + #define REG_UTMI0_GPIO_EN_MASK BIT14 + +//-------------------- configuration ----------------- +#define ENABLE_CHECK_ALL_PAD_CONFLICT 0 + +//============================================================================== +// +// STRUCTURE +// +//============================================================================== + +typedef struct stPadMux +{ + U16 padID; + U32 base; + U16 offset; + U16 mask; + U16 val; + U16 mode; +} ST_PadMuxInfo; + +typedef struct stPadMode +{ + U8 u8PadName[16]; + U32 u32ModeRIU; + U32 u32ModeMask; +} ST_PadModeInfo; + +//============================================================================== +// +// VARIABLES +// +//============================================================================== + +const ST_PadMuxInfo m_stPadMuxTbl[] = +{ + {PAD_GPIO0, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, + {PAD_GPIO0, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, + {PAD_GPIO0, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6, PINMUX_FOR_SPI1_MODE_4}, + {PAD_GPIO0, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1, PINMUX_FOR_FUART_MODE_2}, + {PAD_GPIO0, CHIPTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT2, PINMUX_FOR_PWM0_MODE_4}, + {PAD_GPIO0, CHIPTOP_BANK, REG_PWM8_MODE, REG_PWM8_MODE_MASK, BIT9, PINMUX_FOR_PWM8_MODE_1}, + {PAD_GPIO0, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT10, PINMUX_FOR_I2S_MODE_1}, + {PAD_GPIO0, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, + {PAD_GPIO0, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, + + {PAD_GPIO1, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, + {PAD_GPIO1, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, + {PAD_GPIO1, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6, PINMUX_FOR_SPI1_MODE_4}, + {PAD_GPIO1, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1, PINMUX_FOR_FUART_MODE_2}, + {PAD_GPIO1, CHIPTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT5, PINMUX_FOR_PWM1_MODE_4}, + {PAD_GPIO1, CHIPTOP_BANK, REG_PWM9_MODE, REG_PWM9_MODE_MASK, BIT12, PINMUX_FOR_PWM9_MODE_1}, + {PAD_GPIO1, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT10, PINMUX_FOR_I2S_MODE_1}, + {PAD_GPIO1, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, + {PAD_GPIO1, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, + + {PAD_GPIO2, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, + {PAD_GPIO2, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, + {PAD_GPIO2, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6, PINMUX_FOR_SPI1_MODE_4}, + {PAD_GPIO2, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1, PINMUX_FOR_FUART_MODE_2}, + {PAD_GPIO2, CHIPTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT8, PINMUX_FOR_PWM2_MODE_4}, + {PAD_GPIO2, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT10, PINMUX_FOR_I2S_MODE_1}, + {PAD_GPIO2, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, + {PAD_GPIO2, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, + + {PAD_GPIO3, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, + {PAD_GPIO3, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, + {PAD_GPIO3, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT6, PINMUX_FOR_SPI1_MODE_4}, + {PAD_GPIO3, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1, PINMUX_FOR_FUART_MODE_2}, + {PAD_GPIO3, CHIPTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT11, PINMUX_FOR_PWM3_MODE_4}, + {PAD_GPIO3, CHIPTOP_BANK, REG_PWM10_MODE, REG_PWM10_MODE_MASK, BIT0, PINMUX_FOR_PWM10_MODE_1}, + {PAD_GPIO3, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT10, PINMUX_FOR_I2S_MODE_1}, + {PAD_GPIO3, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, + {PAD_GPIO3, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, + + {PAD_GPIO4, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, + {PAD_GPIO4, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, + {PAD_GPIO4, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1, PINMUX_FOR_SPI0_MODE_2}, + {PAD_GPIO4, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT5|BIT4, PINMUX_FOR_UART0_MODE_3}, + {PAD_GPIO4, CHIPTOP_BANK, REG_PWM4_MODE, REG_PWM4_MODE_MASK, BIT13|BIT12, PINMUX_FOR_PWM4_MODE_3}, + {PAD_GPIO4, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, + {PAD_GPIO4, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT8, PINMUX_FOR_DMIC_MODE_1}, + {PAD_GPIO4, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, + {PAD_GPIO4, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, + + {PAD_GPIO5, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, + {PAD_GPIO5, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, + {PAD_GPIO5, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1, PINMUX_FOR_SPI0_MODE_2}, + {PAD_GPIO5, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT5|BIT4, PINMUX_FOR_UART0_MODE_3}, + {PAD_GPIO5, CHIPTOP_BANK, REG_PWM5_MODE, REG_PWM5_MODE_MASK, BIT1|BIT0, PINMUX_FOR_PWM5_MODE_3}, + {PAD_GPIO5, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, + {PAD_GPIO5, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT8, PINMUX_FOR_DMIC_MODE_1}, + {PAD_GPIO5, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, + {PAD_GPIO5, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, + + {PAD_GPIO6, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, + {PAD_GPIO6, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, + {PAD_GPIO6, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1, PINMUX_FOR_SPI0_MODE_2}, + {PAD_GPIO6, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT9|BIT8, PINMUX_FOR_UART1_MODE_3}, + {PAD_GPIO6, CHIPTOP_BANK, REG_PWM6_MODE, REG_PWM6_MODE_MASK, BIT4|BIT3, PINMUX_FOR_PWM6_MODE_3}, + {PAD_GPIO6, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, + {PAD_GPIO6, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT8, PINMUX_FOR_DMIC_MODE_1}, + {PAD_GPIO6, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, + {PAD_GPIO6, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, + + {PAD_GPIO7, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, + {PAD_GPIO7, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, + {PAD_GPIO7, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1, PINMUX_FOR_SPI0_MODE_2}, + {PAD_GPIO7, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT9|BIT8, PINMUX_FOR_UART1_MODE_3}, + {PAD_GPIO7, CHIPTOP_BANK, REG_PWM7_MODE, REG_PWM7_MODE_MASK, BIT7|BIT6, PINMUX_FOR_PWM7_MODE_3}, + {PAD_GPIO7, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, + {PAD_GPIO7, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, + {PAD_GPIO7, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, + + {PAD_GPIO8, CHIPTOP_BANK, REG_PWM8_MODE, REG_PWM8_MODE_MASK, BIT10, PINMUX_FOR_PWM8_MODE_2}, + {PAD_GPIO8, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, + + {PAD_GPIO9, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, + + {PAD_GPIO12, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5, PINMUX_FOR_SPI1_MODE_2}, + {PAD_GPIO12, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT10, PINMUX_FOR_UART1_MODE_4}, + {PAD_GPIO12, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, + + {PAD_GPIO13, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5, PINMUX_FOR_SPI1_MODE_2}, + {PAD_GPIO13, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT10, PINMUX_FOR_UART1_MODE_4}, + {PAD_GPIO13, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, + + {PAD_GPIO14, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5, PINMUX_FOR_SPI1_MODE_2}, + {PAD_GPIO14, CHIPTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT1, PINMUX_FOR_PWM0_MODE_2}, + {PAD_GPIO14, CHIPTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT6, PINMUX_FOR_PWM2_MODE_1}, + {PAD_GPIO14, CHIPTOP_BANK, REG_PWM9_MODE, REG_PWM9_MODE_MASK, BIT13|BIT12, PINMUX_FOR_PWM9_MODE_3}, + {PAD_GPIO14, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, + {PAD_GPIO14, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, + {PAD_GPIO14, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, + + {PAD_GPIO15, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5, PINMUX_FOR_SPI1_MODE_2}, + {PAD_GPIO15, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1|BIT0, PINMUX_FOR_FUART_MODE_3}, + {PAD_GPIO15, CHIPTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT4, PINMUX_FOR_PWM1_MODE_2}, + {PAD_GPIO15, CHIPTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT9, PINMUX_FOR_PWM3_MODE_1}, + {PAD_GPIO15, CHIPTOP_BANK, REG_PWM10_MODE, REG_PWM10_MODE_MASK, BIT1|BIT0, PINMUX_FOR_PWM10_MODE_3}, + {PAD_GPIO15, CHIPTOP_BANK, REG_ETH_MODE, REG_ETH_MODE_MASK, BIT2, PINMUX_FOR_ETH_MODE}, + {PAD_GPIO15, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, + {PAD_GPIO15, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, + + {PAD_FUART_RX, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT0, PINMUX_FOR_EJ_MODE_1}, + {PAD_FUART_RX, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, + {PAD_FUART_RX, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, + {PAD_FUART_RX, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SPI0_MODE_3}, + {PAD_FUART_RX, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT0, PINMUX_FOR_FUART_MODE_1}, + {PAD_FUART_RX, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1|BIT0, PINMUX_FOR_FUART_MODE_3}, + {PAD_FUART_RX, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2|BIT0, PINMUX_FOR_FUART_MODE_5}, + {PAD_FUART_RX, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT5, PINMUX_FOR_UART0_MODE_2}, + {PAD_FUART_RX, CHIPTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_PWM0_MODE_3}, + {PAD_FUART_RX, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, + {PAD_FUART_RX, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, + + {PAD_FUART_TX, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT0, PINMUX_FOR_EJ_MODE_1}, + {PAD_FUART_TX, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, + {PAD_FUART_TX, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, + {PAD_FUART_TX, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SPI0_MODE_3}, + {PAD_FUART_TX, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT0, PINMUX_FOR_FUART_MODE_1}, + {PAD_FUART_TX, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1|BIT0, PINMUX_FOR_FUART_MODE_3}, + {PAD_FUART_TX, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2|BIT0, PINMUX_FOR_FUART_MODE_5}, + {PAD_FUART_TX, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT5, PINMUX_FOR_UART0_MODE_2}, + {PAD_FUART_TX, CHIPTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT4|BIT3, PINMUX_FOR_PWM1_MODE_3}, + {PAD_FUART_TX, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, + {PAD_FUART_TX, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, + + {PAD_FUART_CTS, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT0, PINMUX_FOR_EJ_MODE_1}, + {PAD_FUART_CTS, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, + {PAD_FUART_CTS, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, + {PAD_FUART_CTS, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SPI0_MODE_3}, + {PAD_FUART_CTS, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT0, PINMUX_FOR_FUART_MODE_1}, + {PAD_FUART_CTS, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT1|BIT0, PINMUX_FOR_FUART_MODE_3}, + {PAD_FUART_CTS, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT9, PINMUX_FOR_UART1_MODE_2}, + {PAD_FUART_CTS, CHIPTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT7, PINMUX_FOR_PWM2_MODE_2}, + {PAD_FUART_CTS, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, + {PAD_FUART_CTS, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, + + {PAD_FUART_RTS, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT0, PINMUX_FOR_EJ_MODE_1}, + {PAD_FUART_RTS, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, + {PAD_FUART_RTS, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, + {PAD_FUART_RTS, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SPI0_MODE_3}, + {PAD_FUART_RTS, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT0, PINMUX_FOR_FUART_MODE_1}, + {PAD_FUART_RTS, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT9, PINMUX_FOR_UART1_MODE_2}, + {PAD_FUART_RTS, CHIPTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT10, PINMUX_FOR_PWM3_MODE_2}, + + {PAD_I2C0_SCL, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, + {PAD_I2C0_SCL, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, + {PAD_I2C0_SCL, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT0, PINMUX_FOR_I2C0_MODE_1}, + {PAD_I2C0_SCL, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, + {PAD_I2C0_SCL, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, + + {PAD_I2C0_SDA, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, + {PAD_I2C0_SDA, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, + {PAD_I2C0_SDA, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT0, PINMUX_FOR_I2C0_MODE_1}, + {PAD_I2C0_SDA, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, + {PAD_I2C0_SDA, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, + + {PAD_I2C1_SCL, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, + {PAD_I2C1_SCL, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, + {PAD_I2C1_SCL, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT4, PINMUX_FOR_I2C1_MODE_1}, + + {PAD_I2C1_SDA, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, + {PAD_I2C1_SDA, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, + {PAD_I2C1_SDA, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT4, PINMUX_FOR_I2C1_MODE_1}, + + {PAD_SR_IO00, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, + {PAD_SR_IO00, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, + {PAD_SR_IO00, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, + {PAD_SR_IO00, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, + {PAD_SR_IO00, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, + + {PAD_SR_IO01, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, + {PAD_SR_IO01, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1|BIT0, PINMUX_FOR_MIPI_PAD_IN_3}, + {PAD_SR_IO01, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, + {PAD_SR_IO01, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, + {PAD_SR_IO01, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_I2C0_MODE_3}, + {PAD_SR_IO01, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_I2C1_MODE_3}, + {PAD_SR_IO01, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, + {PAD_SR_IO01, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, + {PAD_SR_IO01, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, + + {PAD_SR_IO02, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, + {PAD_SR_IO02, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1|BIT0, PINMUX_FOR_MIPI_PAD_IN_3}, + {PAD_SR_IO02, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, + {PAD_SR_IO02, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, + {PAD_SR_IO02, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT1|BIT0, PINMUX_FOR_I2C0_MODE_3}, + {PAD_SR_IO02, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_I2C1_MODE_3}, + {PAD_SR_IO02, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, + {PAD_SR_IO02, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, + {PAD_SR_IO02, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, + {PAD_SR_IO02, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, + {PAD_SR_IO02, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, + {PAD_SR_IO02, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, + {PAD_SR_IO02, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, + + {PAD_SR_IO03, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, + {PAD_SR_IO03, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1, PINMUX_FOR_MIPI_PAD_IN_2}, + {PAD_SR_IO03, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1|BIT0, PINMUX_FOR_MIPI_PAD_IN_3}, + {PAD_SR_IO03, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, + {PAD_SR_IO03, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, + {PAD_SR_IO03, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, + {PAD_SR_IO03, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, + {PAD_SR_IO03, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, + {PAD_SR_IO03, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, + {PAD_SR_IO03, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, + {PAD_SR_IO03, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, + {PAD_SR_IO03, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, + + {PAD_SR_IO04, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, + {PAD_SR_IO04, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1, PINMUX_FOR_MIPI_PAD_IN_2}, + {PAD_SR_IO04, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1|BIT0, PINMUX_FOR_MIPI_PAD_IN_3}, + {PAD_SR_IO04, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, + {PAD_SR_IO04, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, + {PAD_SR_IO04, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, + {PAD_SR_IO04, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, + {PAD_SR_IO04, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, + {PAD_SR_IO04, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, + {PAD_SR_IO04, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, + {PAD_SR_IO04, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, + {PAD_SR_IO04, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, + + {PAD_SR_IO05, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, + {PAD_SR_IO05, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1, PINMUX_FOR_MIPI_PAD_IN_2}, + {PAD_SR_IO05, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1|BIT0, PINMUX_FOR_MIPI_PAD_IN_3}, + {PAD_SR_IO05, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, + {PAD_SR_IO05, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, + {PAD_SR_IO05, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, + {PAD_SR_IO05, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, + {PAD_SR_IO05, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, + {PAD_SR_IO05, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, + {PAD_SR_IO05, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, + {PAD_SR_IO05, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, + {PAD_SR_IO05, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, + + {PAD_SR_IO06, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, + {PAD_SR_IO06, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1, PINMUX_FOR_MIPI_PAD_IN_2}, + {PAD_SR_IO06, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1|BIT0, PINMUX_FOR_MIPI_PAD_IN_3}, + {PAD_SR_IO06, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, + {PAD_SR_IO06, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, + {PAD_SR_IO06, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, + {PAD_SR_IO06, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, + {PAD_SR_IO06, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, + {PAD_SR_IO06, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, + {PAD_SR_IO06, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, + {PAD_SR_IO06, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, + {PAD_SR_IO06, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, + + {PAD_SR_IO07, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, + {PAD_SR_IO07, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1, PINMUX_FOR_MIPI_PAD_IN_2}, + {PAD_SR_IO07, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, + {PAD_SR_IO07, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, + {PAD_SR_IO07, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, + {PAD_SR_IO07, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, + {PAD_SR_IO07, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, + {PAD_SR_IO07, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, + {PAD_SR_IO07, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, + {PAD_SR_IO07, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, + {PAD_SR_IO07, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, + + {PAD_SR_IO08, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, + {PAD_SR_IO08, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT1, PINMUX_FOR_MIPI_PAD_IN_2}, + {PAD_SR_IO08, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, + {PAD_SR_IO08, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, + {PAD_SR_IO08, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, + {PAD_SR_IO08, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, + {PAD_SR_IO08, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, + {PAD_SR_IO08, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, + {PAD_SR_IO08, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, + {PAD_SR_IO08, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, + {PAD_SR_IO08, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, + + {PAD_SR_IO09, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, + {PAD_SR_IO09, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, + {PAD_SR_IO09, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, + {PAD_SR_IO09, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, + {PAD_SR_IO09, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, + {PAD_SR_IO09, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, + {PAD_SR_IO09, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, + {PAD_SR_IO09, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, + {PAD_SR_IO09, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, + {PAD_SR_IO09, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, + + {PAD_SR_IO10, CHIPTOP_BANK, REG_MIPI_PAD_IN, REG_MIPI_PAD_IN_MASK, BIT0, PINMUX_FOR_MIPI_PAD_IN_1}, + {PAD_SR_IO10, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, + {PAD_SR_IO10, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, + {PAD_SR_IO10, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, + {PAD_SR_IO10, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, + {PAD_SR_IO10, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, + {PAD_SR_IO10, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, + {PAD_SR_IO10, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, + + {PAD_SR_IO11, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, + {PAD_SR_IO11, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, + {PAD_SR_IO11, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, + {PAD_SR_IO11, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, + {PAD_SR_IO11, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1|BIT0, PINMUX_FOR_SR_MODE_3}, + {PAD_SR_IO11, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, + {PAD_SR_IO11, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, + + {PAD_SR_IO12, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, + {PAD_SR_IO12, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, + {PAD_SR_IO12, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, + {PAD_SR_IO12, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, + {PAD_SR_IO12, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, + {PAD_SR_IO12, CHIPTOP_BANK, REG_SR_PDN_MODE, REG_SR_PDN_MODE_MASK, BIT9, PINMUX_FOR_SR_PDN_MODE_1}, + {PAD_SR_IO12, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT4, PINMUX_FOR_CCIR_MODE_1}, + {PAD_SR_IO12, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, + + {PAD_SR_IO13, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, + {PAD_SR_IO13, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, + {PAD_SR_IO13, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, + {PAD_SR_IO13, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, + {PAD_SR_IO13, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT2, PINMUX_FOR_SR_MODE_4}, + {PAD_SR_IO13, CHIPTOP_BANK, REG_SR_RST_MODE, REG_SR_RST_MODE_MASK, BIT11, PINMUX_FOR_SR_RST_MODE_1}, + {PAD_SR_IO13, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, + + {PAD_SR_IO14, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, + {PAD_SR_IO14, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, + {PAD_SR_IO14, CHIPTOP_BANK, REG_PWM8_MODE, REG_PWM8_MODE_MASK, BIT11, PINMUX_FOR_PWM8_MODE_4}, + {PAD_SR_IO14, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, + {PAD_SR_IO14, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, + {PAD_SR_IO14, CHIPTOP_BANK, REG_SR_HVSYNC_MODE, REG_SR_HVSYNC_MODE_MASK, BIT6, PINMUX_FOR_SR_HVSYNC_MODE}, + + {PAD_SR_IO15, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, + {PAD_SR_IO15, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, + {PAD_SR_IO15, CHIPTOP_BANK, REG_PWM9_MODE, REG_PWM9_MODE_MASK, BIT14, PINMUX_FOR_PWM9_MODE_4}, + {PAD_SR_IO15, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, + {PAD_SR_IO15, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, + {PAD_SR_IO15, CHIPTOP_BANK, REG_SR_PCK_MODE, REG_SR_PCK_MODE_MASK, BIT8, PINMUX_FOR_SR_PCK_MODE}, + {PAD_SR_IO15, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5, PINMUX_FOR_CCIR_MODE_2}, + {PAD_SR_IO15, CHIPTOP_BANK, REG_CCIR_MODE, REG_CCIR_MODE_MASK, BIT5|BIT4, PINMUX_FOR_CCIR_MODE_3}, + + {PAD_SR_IO16, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, + {PAD_SR_IO16, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, + {PAD_SR_IO16, CHIPTOP_BANK, REG_PWM10_MODE, REG_PWM10_MODE_MASK, BIT2, PINMUX_FOR_PWM10_MODE_4}, + {PAD_SR_IO16, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, + {PAD_SR_IO16, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, + {PAD_SR_IO16, CHIPTOP_BANK, REG_SR_HVSYNC_MODE, REG_SR_HVSYNC_MODE_MASK, BIT6, PINMUX_FOR_SR_HVSYNC_MODE}, + + {PAD_SR_IO17, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, + {PAD_SR_IO17, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, + {PAD_SR_IO17, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT0, PINMUX_FOR_SR_MODE_1}, + {PAD_SR_IO17, CHIPTOP_BANK, REG_SR_MODE, REG_SR_MODE_MASK, BIT1, PINMUX_FOR_SR_MODE_2}, + {PAD_SR_IO17, CHIPTOP_BANK, REG_SR_MCLK_MODE, REG_SR_MCLK_MODE_MASK, BIT7, PINMUX_FOR_SR_MCLK_MODE}, + + {PAD_UART0_RX, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT4, PINMUX_FOR_UART0_MODE_1}, + {PAD_UART0_RX, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9|BIT8, PINMUX_FOR_DMIC_MODE_3}, + + {PAD_UART0_TX, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT4, PINMUX_FOR_UART0_MODE_1}, + {PAD_UART0_TX, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9|BIT8, PINMUX_FOR_DMIC_MODE_3}, + + {PAD_UART1_RX, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT2, PINMUX_FOR_I2C0_MODE_4}, + {PAD_UART1_RX, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT8, PINMUX_FOR_UART1_MODE_1}, + + {PAD_UART1_TX, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT2, PINMUX_FOR_I2C0_MODE_4}, + {PAD_UART1_TX, CHIPTOP_BANK, REG_UART1_MODE, REG_UART1_MODE_MASK, BIT8, PINMUX_FOR_UART1_MODE_1}, + + {PAD_SPI0_CZ, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT1, PINMUX_FOR_EJ_MODE_2}, + {PAD_SPI0_CZ, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, + {PAD_SPI0_CZ, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, + {PAD_SPI0_CZ, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, + {PAD_SPI0_CZ, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, + {PAD_SPI0_CZ, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT0, PINMUX_FOR_SPI0_MODE_1}, + {PAD_SPI0_CZ, CHIPTOP_BANK, REG_PWM4_MODE, REG_PWM4_MODE_MASK, BIT13, PINMUX_FOR_PWM4_MODE_2}, + + {PAD_SPI0_CK, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT1, PINMUX_FOR_EJ_MODE_2}, + {PAD_SPI0_CK, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, + {PAD_SPI0_CK, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, + {PAD_SPI0_CK, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT0, PINMUX_FOR_SPI0_MODE_1}, + {PAD_SPI0_CK, CHIPTOP_BANK, REG_PWM5_MODE, REG_PWM5_MODE_MASK, BIT1, PINMUX_FOR_PWM5_MODE_2}, + + {PAD_SPI0_DI, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT1, PINMUX_FOR_EJ_MODE_2}, + {PAD_SPI0_DI, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, + {PAD_SPI0_DI, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, + {PAD_SPI0_DI, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT0, PINMUX_FOR_SPI0_MODE_1}, + {PAD_SPI0_DI, CHIPTOP_BANK, REG_PWM6_MODE, REG_PWM6_MODE_MASK, BIT4, PINMUX_FOR_PWM6_MODE_2}, + + {PAD_SPI0_DO, CHIPTOP_BANK, REG_EJ_MODE, REG_EJ_MODE_MASK, BIT1, PINMUX_FOR_EJ_MODE_2}, + {PAD_SPI0_DO, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT0, PINMUX_FOR_TEST_IN_MODE_1}, + {PAD_SPI0_DO, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT4, PINMUX_FOR_TEST_OUT_MODE_1}, + {PAD_SPI0_DO, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT0, PINMUX_FOR_SPI0_MODE_1}, + {PAD_SPI0_DO, CHIPTOP_BANK, REG_PWM7_MODE, REG_PWM7_MODE_MASK, BIT7, PINMUX_FOR_PWM7_MODE_2}, + + {PAD_SPI1_CZ, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT4, PINMUX_FOR_SPI1_MODE_1}, + {PAD_SPI1_CZ, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT11|BIT10, PINMUX_FOR_I2S_MODE_3}, + + {PAD_SPI1_CK, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT4, PINMUX_FOR_SPI1_MODE_1}, + {PAD_SPI1_CK, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT11|BIT10, PINMUX_FOR_I2S_MODE_3}, + + {PAD_SPI1_DI, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT4, PINMUX_FOR_SPI1_MODE_1}, + {PAD_SPI1_DI, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT11|BIT10, PINMUX_FOR_I2S_MODE_3}, + + {PAD_SPI1_DO, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT4, PINMUX_FOR_SPI1_MODE_1}, + {PAD_SPI1_DO, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT11|BIT10, PINMUX_FOR_I2S_MODE_3}, + + {PAD_PWM0, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, + {PAD_PWM0, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, + {PAD_PWM0, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, + {PAD_PWM0, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, + {PAD_PWM0, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT1, PINMUX_FOR_I2C0_MODE_2}, + {PAD_PWM0, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT5, PINMUX_FOR_I2C1_MODE_2}, + {PAD_PWM0, CHIPTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT0, PINMUX_FOR_PWM0_MODE_1}, + {PAD_PWM0, CHIPTOP_BANK, REG_PWM9_MODE, REG_PWM9_MODE_MASK, BIT13, PINMUX_FOR_PWM9_MODE_2}, + {PAD_PWM0, CHIPTOP_BANK, REG_SR_PDN_MODE, REG_SR_PDN_MODE_MASK, BIT10, PINMUX_FOR_SR_PDN_MODE_2}, + + {PAD_PWM1, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, + {PAD_PWM1, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, + {PAD_PWM1, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, + {PAD_PWM1, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, + {PAD_PWM1, CHIPTOP_BANK, REG_I2C0_MODE, REG_I2C0_MODE_MASK, BIT1, PINMUX_FOR_I2C0_MODE_2}, + {PAD_PWM1, CHIPTOP_BANK, REG_I2C1_MODE, REG_I2C1_MODE_MASK, BIT5, PINMUX_FOR_I2C1_MODE_2}, + {PAD_PWM1, CHIPTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT3, PINMUX_FOR_PWM1_MODE_1}, + {PAD_PWM1, CHIPTOP_BANK, REG_PWM10_MODE, REG_PWM10_MODE_MASK, BIT1, PINMUX_FOR_PWM10_MODE_2}, + {PAD_PWM1, CHIPTOP_BANK, REG_SR_RST_MODE, REG_SR_RST_MODE_MASK, BIT12, PINMUX_FOR_SR_RST_MODE_2}, + + {PAD_SD_CLK, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, + {PAD_SD_CLK, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, + {PAD_SD_CLK, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, + {PAD_SD_CLK, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, + {PAD_SD_CLK, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT2, PINMUX_FOR_SD_MODE}, + + {PAD_SD_CMD, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, + {PAD_SD_CMD, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, + {PAD_SD_CMD, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, + {PAD_SD_CMD, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, + {PAD_SD_CMD, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT2, PINMUX_FOR_SD_MODE}, + + {PAD_SD_D0, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, + {PAD_SD_D0, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, + {PAD_SD_D0, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_SPI1_MODE_3}, + {PAD_SD_D0, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT2, PINMUX_FOR_SD_MODE}, + + {PAD_SD_D1, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, + {PAD_SD_D1, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, + {PAD_SD_D1, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_SPI1_MODE_3}, + {PAD_SD_D1, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT2, PINMUX_FOR_SD_MODE}, + + {PAD_SD_D2, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, + {PAD_SD_D2, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, + {PAD_SD_D2, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_SPI1_MODE_3}, + {PAD_SD_D2, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT2, PINMUX_FOR_SD_MODE}, + + {PAD_SD_D3, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, + {PAD_SD_D3, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, + {PAD_SD_D3, CHIPTOP_BANK, REG_SPI1_MODE, REG_SPI1_MODE_MASK, BIT5|BIT4, PINMUX_FOR_SPI1_MODE_3}, + {PAD_SD_D3, CHIPTOP_BANK, REG_SD_MODE, REG_SD_MODE_MASK, BIT2, PINMUX_FOR_SD_MODE}, + + {PAD_PM_SD_CDZ, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, + {PAD_PM_SD_CDZ, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, + {PAD_PM_SD_CDZ, PMSLEEP_BANK, REG_PM_SD_CDZ_MODE, REG_PM_SD_CDZ_MODE_MASK, BIT14, PINMUX_FOR_PM_SD_CDZ_MODE}, + + {PAD_PM_IRIN, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, + {PAD_PM_IRIN, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, + {PAD_PM_IRIN, PMSLEEP_BANK, REG_PM_IR_IS_GPIO, REG_PM_IR_IS_GPIO_MASK, 0, PINMUX_FOR_PM_IRIN_MODE}, + + {PAD_PM_GPIO0, PMSLEEP_BANK, REG_PM_PWM0_MODE, REG_PM_PWM0_MODE_MASK, BIT0, PINMUX_FOR_PM_PWM0_MODE_1}, + {PAD_PM_GPIO0, PMSLEEP_BANK, REG_PM_VID_MODE, REG_PM_VID_MODE_MASK, BIT13, PINMUX_FOR_PM_VID_MODE_2}, + {PAD_PM_GPIO0, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, + {PAD_PM_GPIO0, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, + + {PAD_PM_GPIO1, PMSLEEP_BANK, REG_PM_PWM1_MODE, REG_PM_PWM1_MODE_MASK, BIT2, PINMUX_FOR_PM_PWM1_MODE_1}, + {PAD_PM_GPIO1, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, + {PAD_PM_GPIO1, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, + + {PAD_PM_GPIO2, PMSLEEP_BANK, REG_PM_PWM2_MODE, REG_PM_PWM2_MODE_MASK, BIT6, PINMUX_FOR_PM_PWM2_MODE_1}, + + {PAD_PM_GPIO3, PMSLEEP_BANK, REG_PM_PWM3_MODE, REG_PM_PWM3_MODE_MASK, BIT8, PINMUX_FOR_PM_PWM3_MODE_1}, + {PAD_PM_GPIO3, PMSLEEP_BANK, REG_PM_UART1_MODE, REG_PM_UART1_MODE_MASK, BIT8, PINMUX_FOR_PM_UART1_MODE}, + {PAD_PM_GPIO3, PMSLEEP_BANK, REG_PM_VID_MODE, REG_PM_VID_MODE_MASK, BIT13, PINMUX_FOR_PM_VID_MODE_2}, + {PAD_PM_GPIO3, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, + {PAD_PM_GPIO3, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, + + /* + {PAD_PM_GPIO4, PMSLEEP_BANK, REG_PM_UART1_MODE, REG_PM_UART1_MODE_MASK, BIT8, PINMUX_FOR_PM_UART1_MODE}, + {PAD_PM_GPIO4, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, + {PAD_PM_GPIO4, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT7, PINMUX_FOR_TTL_MODE_2}, + */ + + {PAD_PM_GPIO7, PMSLEEP_BANK, REG_PM_PWM3_MODE, REG_PM_PWM3_MODE_MASK, BIT9, PINMUX_FOR_PM_PWM3_MODE_2}, + + {PAD_PM_GPIO9, PMSLEEP_BANK, REG_PM_SPICSZ2_GPIO, REG_PM_SPICSZ2_GPIO_MASK, 0, PINMUX_FOR_PM_SPICSZ2_MODE}, + {PAD_PM_GPIO9, PMSLEEP_BANK, REG_PM_PWM2_MODE, REG_PM_PWM2_MODE_MASK, BIT7, PINMUX_FOR_PM_PWM2_MODE_2}, + {PAD_PM_GPIO9, PMSLEEP_BANK, REG_PM_PWM8_MODE, REG_PM_PWM8_MODE_MASK, BIT2, PINMUX_FOR_PM_PWM8_MODE}, + + {PAD_PM_SPI_CZ, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, + {PAD_PM_SPI_CZ, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, + {PAD_PM_SPI_CZ, PMSLEEP_BANK, REG_PM_SPICSZ1_GPIO, REG_PM_SPICSZ1_GPIO_MASK, 0, PINMUX_FOR_PM_SPICSZ1_MODE}, + + {PAD_PM_SPI_CK, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, + {PAD_PM_SPI_CK, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, + {PAD_PM_SPI_CK, PMSLEEP_BANK, REG_PM_SPI_GPIO, REG_PM_SPI_GPIO_MASK, 0, PINMUX_FOR_PM_SPI_MODE}, + + {PAD_PM_SPI_DI, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, + {PAD_PM_SPI_DI, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, + {PAD_PM_SPI_DI, PMSLEEP_BANK, REG_PM_SPI_GPIO, REG_PM_SPI_GPIO_MASK, 0, PINMUX_FOR_PM_SPI_MODE}, + + {PAD_PM_SPI_DO, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, + {PAD_PM_SPI_DO, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, + {PAD_PM_SPI_DO, PMSLEEP_BANK, REG_PM_SPI_GPIO, REG_PM_SPI_GPIO_MASK, 0, PINMUX_FOR_PM_SPI_MODE}, + + {PAD_PM_SPI_WPZ,CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, + {PAD_PM_SPI_WPZ,CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, + {PAD_PM_SPI_WPZ,PMSLEEP_BANK, REG_PM_SPIWPN_GPIO, REG_PM_SPIWPN_GPIO_MASK, 0, PINMUX_FOR_PM_SPIWPN_MODE}, + + {PAD_PM_SPI_HLD,PMSLEEP_BANK, REG_PM_SPIHOLDN_MODE, REG_PM_SPIHOLDN_MODE_MASK, 0, PINMUX_FOR_PM_SPIHOLDN_MODE}, + + {PAD_PM_LED0, PMSLEEP_BANK, REG_PM_PWM9_MODE, REG_PM_PWM9_MODE_MASK, BIT3, PINMUX_FOR_PM_PWM9_MODE}, + {PAD_PM_LED0, PMSLEEP_BANK, REG_PM_VID_MODE, REG_PM_VID_MODE_MASK, BIT12, PINMUX_FOR_PM_VID_MODE_1}, + {PAD_PM_LED0, PMSLEEP_BANK, REG_PM_VID_MODE, REG_PM_VID_MODE_MASK, BIT13|BIT12, PINMUX_FOR_PM_VID_MODE_3}, + {PAD_PM_LED0, PMSLEEP_BANK, REG_PM_LED_MODE, REG_PM_LED_MODE_MASK, BIT4, PINMUX_FOR_PM_LED_MODE}, + + {PAD_PM_LED1, PMSLEEP_BANK, REG_PM_PWM5_MODE, REG_PM_PWM5_MODE_MASK, BIT1, PINMUX_FOR_PM_PWM5_MODE}, + {PAD_PM_LED1, PMSLEEP_BANK, REG_PM_PWM10_MODE, REG_PM_PWM10_MODE_MASK, BIT4, PINMUX_FOR_PM_PWM10_MODE}, + {PAD_PM_LED1, PMSLEEP_BANK, REG_PM_VID_MODE, REG_PM_VID_MODE_MASK, BIT12, PINMUX_FOR_PM_VID_MODE_1}, + {PAD_PM_LED1, PMSLEEP_BANK, REG_PM_VID_MODE, REG_PM_VID_MODE_MASK, BIT13|BIT12, PINMUX_FOR_PM_VID_MODE_3}, + {PAD_PM_LED1, PMSLEEP_BANK, REG_PM_LED_MODE, REG_PM_LED_MODE_MASK, BIT4, PINMUX_FOR_PM_LED_MODE}, + + /* + {PAD_SAR_GPIO0, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, + {PAD_SAR_GPIO0, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, + + {PAD_ETH_RN, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, + {PAD_ETH_RN, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, + + {PAD_USB_DM, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1, PINMUX_FOR_TEST_IN_MODE_2}, + {PAD_USB_DM, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5, PINMUX_FOR_TEST_OUT_MODE_2}, + */ + + {PAD_SD1_IO0, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, + {PAD_SD1_IO0, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, + {PAD_SD1_IO0, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT2, PINMUX_FOR_SPI0_MODE_4}, + {PAD_SD1_IO0, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2, PINMUX_FOR_FUART_MODE_4}, + {PAD_SD1_IO0, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2|BIT1, PINMUX_FOR_FUART_MODE_6}, + {PAD_SD1_IO0, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE}, + {PAD_SD1_IO0, CHIPTOP_BANK, REG_PWM0_MODE, REG_PWM0_MODE_MASK, BIT2|BIT0, PINMUX_FOR_PWM0_MODE_5}, + {PAD_SD1_IO0, CHIPTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT7|BIT6, PINMUX_FOR_PWM2_MODE_3}, + {PAD_SD1_IO0, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT11, PINMUX_FOR_I2S_MODE_2}, + {PAD_SD1_IO0, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, + + {PAD_SD1_IO1, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, + {PAD_SD1_IO1, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, + {PAD_SD1_IO1, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT2, PINMUX_FOR_SPI0_MODE_4}, + {PAD_SD1_IO1, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2, PINMUX_FOR_FUART_MODE_4}, + {PAD_SD1_IO1, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2|BIT1, PINMUX_FOR_FUART_MODE_6}, + {PAD_SD1_IO1, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE}, + {PAD_SD1_IO1, CHIPTOP_BANK, REG_PWM1_MODE, REG_PWM1_MODE_MASK, BIT5|BIT3, PINMUX_FOR_PWM1_MODE_5}, + {PAD_SD1_IO1, CHIPTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT10|BIT9, PINMUX_FOR_PWM3_MODE_3}, + {PAD_SD1_IO1, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT11, PINMUX_FOR_I2S_MODE_2}, + {PAD_SD1_IO1, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, + + {PAD_SD1_IO2, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, + {PAD_SD1_IO2, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, + {PAD_SD1_IO2, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT2, PINMUX_FOR_SPI0_MODE_4}, + {PAD_SD1_IO2, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2, PINMUX_FOR_FUART_MODE_4}, + {PAD_SD1_IO2, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE}, + {PAD_SD1_IO2, CHIPTOP_BANK, REG_PWM2_MODE, REG_PWM2_MODE_MASK, BIT8|BIT6, PINMUX_FOR_PWM2_MODE_5}, + {PAD_SD1_IO2, CHIPTOP_BANK, REG_PWM4_MODE, REG_PWM4_MODE_MASK, BIT12, PINMUX_FOR_PWM4_MODE_1}, + {PAD_SD1_IO2, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT11, PINMUX_FOR_I2S_MODE_2}, + {PAD_SD1_IO2, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, + + {PAD_SD1_IO3, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, + {PAD_SD1_IO3, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, + {PAD_SD1_IO3, CHIPTOP_BANK, REG_SPI0_MODE, REG_SPI0_MODE_MASK, BIT2, PINMUX_FOR_SPI0_MODE_4}, + {PAD_SD1_IO3, CHIPTOP_BANK, REG_FUART_MODE, REG_FUART_MODE_MASK, BIT2, PINMUX_FOR_FUART_MODE_4}, + {PAD_SD1_IO3, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE}, + {PAD_SD1_IO3, CHIPTOP_BANK, REG_PWM3_MODE, REG_PWM3_MODE_MASK, BIT11|BIT9, PINMUX_FOR_PWM3_MODE_5}, + {PAD_SD1_IO3, CHIPTOP_BANK, REG_PWM5_MODE, REG_PWM5_MODE_MASK, BIT0, PINMUX_FOR_PWM5_MODE_1}, + {PAD_SD1_IO3, CHIPTOP_BANK, REG_I2S_MODE, REG_I2S_MODE_MASK, BIT11, PINMUX_FOR_I2S_MODE_2}, + {PAD_SD1_IO3, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, + + {PAD_SD1_IO4, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, + {PAD_SD1_IO4, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, + {PAD_SD1_IO4, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE}, + {PAD_SD1_IO4, CHIPTOP_BANK, REG_PWM4_MODE, REG_PWM4_MODE_MASK, BIT14, PINMUX_FOR_PWM4_MODE_4}, + {PAD_SD1_IO4, CHIPTOP_BANK, REG_PWM6_MODE, REG_PWM6_MODE_MASK, BIT3, PINMUX_FOR_PWM6_MODE_1}, + {PAD_SD1_IO4, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9, PINMUX_FOR_DMIC_MODE_2}, + {PAD_SD1_IO4, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, + + {PAD_SD1_IO5, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, + {PAD_SD1_IO5, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, + {PAD_SD1_IO5, CHIPTOP_BANK, REG_SDIO_MODE, REG_SDIO_MODE_MASK, BIT8, PINMUX_FOR_SDIO_MODE}, + {PAD_SD1_IO5, CHIPTOP_BANK, REG_PWM5_MODE, REG_PWM5_MODE_MASK, BIT2, PINMUX_FOR_PWM5_MODE_4}, + {PAD_SD1_IO5, CHIPTOP_BANK, REG_PWM7_MODE, REG_PWM7_MODE_MASK, BIT6, PINMUX_FOR_PWM7_MODE_1}, + {PAD_SD1_IO5, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9, PINMUX_FOR_DMIC_MODE_2}, + {PAD_SD1_IO5, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, + + {PAD_SD1_IO6, CHIPTOP_BANK, REG_TEST_IN_MODE, REG_TEST_IN_MODE_MASK, BIT1|BIT0, PINMUX_FOR_TEST_IN_MODE_3}, + {PAD_SD1_IO6, CHIPTOP_BANK, REG_TEST_OUT_MODE, REG_TEST_OUT_MODE_MASK, BIT5|BIT4, PINMUX_FOR_TEST_OUT_MODE_3}, + {PAD_SD1_IO6, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT6, PINMUX_FOR_UART0_MODE_4}, + {PAD_SD1_IO6, CHIPTOP_BANK, REG_PWM6_MODE, REG_PWM6_MODE_MASK, BIT5, PINMUX_FOR_PWM6_MODE_4}, + {PAD_SD1_IO6, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9, PINMUX_FOR_DMIC_MODE_2}, + {PAD_SD1_IO6, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, + + {PAD_SD1_IO7, CHIPTOP_BANK, REG_UART0_MODE, REG_UART0_MODE_MASK, BIT6, PINMUX_FOR_UART0_MODE_4}, + {PAD_SD1_IO7, CHIPTOP_BANK, REG_PWM7_MODE, REG_PWM7_MODE_MASK, BIT8, PINMUX_FOR_PWM7_MODE_4}, + {PAD_SD1_IO7, CHIPTOP_BANK, REG_TTL_MODE, REG_TTL_MODE_MASK, BIT6, PINMUX_FOR_TTL_MODE_1}, + + {PAD_SD1_IO8, CHIPTOP_BANK, REG_PWM8_MODE, REG_PWM8_MODE_MASK, BIT10|BIT9, PINMUX_FOR_PWM8_MODE_3}, + {PAD_SD1_IO8, CHIPTOP_BANK, REG_DMIC_MODE, REG_DMIC_MODE_MASK, BIT9|BIT8, PINMUX_FOR_DMIC_MODE_3}, + +}; + +static const ST_PadModeInfo m_stPadModeInfoTbl[] = +{ + {"GPIO", 0, 0}, + // Non PM + {"EJ_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_EJ_MODE), REG_EJ_MODE_MASK}, + {"EJ_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_EJ_MODE), REG_EJ_MODE_MASK}, + {"ALLPAD_IN", _RIUA_16BIT(CHIPTOP_BANK,REG_ALLPAD_IN), REG_ALLPAD_IN_MASK}, + {"MIPI_PAD_IN_1", _RIUA_16BIT(CHIPTOP_BANK,REG_MIPI_PAD_IN), REG_MIPI_PAD_IN_MASK}, + {"MIPI_PAD_IN_2", _RIUA_16BIT(CHIPTOP_BANK,REG_MIPI_PAD_IN), REG_MIPI_PAD_IN_MASK}, + {"MIPI_PAD_IN_3", _RIUA_16BIT(CHIPTOP_BANK,REG_MIPI_PAD_IN), REG_MIPI_PAD_IN_MASK}, + {"TEST_IN_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_IN_MODE), REG_TEST_IN_MODE_MASK}, + {"TEST_IN_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_IN_MODE), REG_TEST_IN_MODE_MASK}, + {"TEST_IN_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_IN_MODE), REG_TEST_IN_MODE_MASK}, + {"TEST_OUT_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_OUT_MODE), REG_TEST_OUT_MODE_MASK}, + {"TEST_OUT_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_OUT_MODE), REG_TEST_OUT_MODE_MASK}, + {"TEST_OUT_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_TEST_OUT_MODE), REG_TEST_OUT_MODE_MASK}, + {"I2C0_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C0_MODE), REG_I2C0_MODE_MASK}, + {"I2C0_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C0_MODE), REG_I2C0_MODE_MASK}, + {"I2C0_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C0_MODE), REG_I2C0_MODE_MASK}, + {"I2C0_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C0_MODE), REG_I2C0_MODE_MASK}, + {"I2C1_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C1_MODE), REG_I2C1_MODE_MASK}, + {"I2C1_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C1_MODE), REG_I2C1_MODE_MASK}, + {"I2C1_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_I2C1_MODE), REG_I2C1_MODE_MASK}, + {"SPI0_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI0_MODE), REG_SPI0_MODE_MASK}, + {"SPI0_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI0_MODE), REG_SPI0_MODE_MASK}, + {"SPI0_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI0_MODE), REG_SPI0_MODE_MASK}, + {"SPI0_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI0_MODE), REG_SPI0_MODE_MASK}, + {"SPI1_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI1_MODE), REG_SPI1_MODE_MASK}, + {"SPI1_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI1_MODE), REG_SPI1_MODE_MASK}, + {"SPI1_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI1_MODE), REG_SPI1_MODE_MASK}, + {"SPI1_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_SPI1_MODE), REG_SPI1_MODE_MASK}, + {"FUART_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, + {"FUART_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, + {"FUART_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, + {"FUART_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, + {"FUART_MODE_5", _RIUA_16BIT(CHIPTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, + {"FUART_MODE_6", _RIUA_16BIT(CHIPTOP_BANK,REG_FUART_MODE), REG_FUART_MODE_MASK}, + {"UART0_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_UART0_MODE), REG_UART0_MODE_MASK}, + {"UART0_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_UART0_MODE), REG_UART0_MODE_MASK}, + {"UART0_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_UART0_MODE), REG_UART0_MODE_MASK}, + {"UART0_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_UART0_MODE), REG_UART0_MODE_MASK}, + {"UART1_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_UART1_MODE), REG_UART1_MODE_MASK}, + {"UART1_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_UART1_MODE), REG_UART1_MODE_MASK}, + {"UART1_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_UART1_MODE), REG_UART1_MODE_MASK}, + {"UART1_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_UART1_MODE), REG_UART1_MODE_MASK}, + {"SD_MODE", _RIUA_16BIT(CHIPTOP_BANK,REG_SD_MODE), REG_SD_MODE_MASK}, + {"SDIO_MODE", _RIUA_16BIT(CHIPTOP_BANK,REG_SDIO_MODE), REG_SDIO_MODE_MASK}, + {"PWM0_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM0_MODE), REG_PWM0_MODE_MASK}, + {"PWM0_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM0_MODE), REG_PWM0_MODE_MASK}, + {"PWM0_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM0_MODE), REG_PWM0_MODE_MASK}, + {"PWM0_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM0_MODE), REG_PWM0_MODE_MASK}, + {"PWM0_MODE_5", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM0_MODE), REG_PWM0_MODE_MASK}, + {"PWM1_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM1_MODE), REG_PWM1_MODE_MASK}, + {"PWM1_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM1_MODE), REG_PWM1_MODE_MASK}, + {"PWM1_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM1_MODE), REG_PWM1_MODE_MASK}, + {"PWM1_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM1_MODE), REG_PWM1_MODE_MASK}, + {"PWM1_MODE_5", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM1_MODE), REG_PWM1_MODE_MASK}, + {"PWM2_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM2_MODE), REG_PWM2_MODE_MASK}, + {"PWM2_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM2_MODE), REG_PWM2_MODE_MASK}, + {"PWM2_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM2_MODE), REG_PWM2_MODE_MASK}, + {"PWM2_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM2_MODE), REG_PWM2_MODE_MASK}, + {"PWM2_MODE_5", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM2_MODE), REG_PWM2_MODE_MASK}, + {"PWM3_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM3_MODE), REG_PWM3_MODE_MASK}, + {"PWM3_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM3_MODE), REG_PWM3_MODE_MASK}, + {"PWM3_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM3_MODE), REG_PWM3_MODE_MASK}, + {"PWM3_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM3_MODE), REG_PWM3_MODE_MASK}, + {"PWM3_MODE_5", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM3_MODE), REG_PWM3_MODE_MASK}, + {"PWM4_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM4_MODE), REG_PWM4_MODE_MASK}, + {"PWM4_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM4_MODE), REG_PWM4_MODE_MASK}, + {"PWM4_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM4_MODE), REG_PWM4_MODE_MASK}, + {"PWM4_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM4_MODE), REG_PWM4_MODE_MASK}, + {"PWM5_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM5_MODE), REG_PWM5_MODE_MASK}, + {"PWM5_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM5_MODE), REG_PWM5_MODE_MASK}, + {"PWM5_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM5_MODE), REG_PWM5_MODE_MASK}, + {"PWM5_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM5_MODE), REG_PWM5_MODE_MASK}, + {"PWM6_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM6_MODE), REG_PWM6_MODE_MASK}, + {"PWM6_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM6_MODE), REG_PWM6_MODE_MASK}, + {"PWM6_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM6_MODE), REG_PWM6_MODE_MASK}, + {"PWM6_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM6_MODE), REG_PWM6_MODE_MASK}, + {"PWM7_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM7_MODE), REG_PWM7_MODE_MASK}, + {"PWM7_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM7_MODE), REG_PWM7_MODE_MASK}, + {"PWM7_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM7_MODE), REG_PWM7_MODE_MASK}, + {"PWM7_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM7_MODE), REG_PWM7_MODE_MASK}, + {"PWM8_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM8_MODE), REG_PWM8_MODE_MASK}, + {"PWM8_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM8_MODE), REG_PWM8_MODE_MASK}, + {"PWM8_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM8_MODE), REG_PWM8_MODE_MASK}, + {"PWM8_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM8_MODE), REG_PWM8_MODE_MASK}, + {"PWM9_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM9_MODE), REG_PWM9_MODE_MASK}, + {"PWM9_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM9_MODE), REG_PWM9_MODE_MASK}, + {"PWM9_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM9_MODE), REG_PWM9_MODE_MASK}, + {"PWM9_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM9_MODE), REG_PWM9_MODE_MASK}, + {"PWM10_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM10_MODE), REG_PWM10_MODE_MASK}, + {"PWM10_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM10_MODE), REG_PWM10_MODE_MASK}, + {"PWM10_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM10_MODE), REG_PWM10_MODE_MASK}, + {"PWM10_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_PWM10_MODE), REG_PWM10_MODE_MASK}, + {"SR_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_MODE), REG_SR_MODE_MASK}, + {"SR_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_MODE), REG_SR_MODE_MASK}, + {"SR_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_MODE), REG_SR_MODE_MASK}, + {"SR_MODE_4", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_MODE), REG_SR_MODE_MASK}, + {"SR_MCLK_MODE", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_MCLK_MODE), REG_SR_MCLK_MODE_MASK}, + {"SR_PDN_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_PDN_MODE), REG_SR_PDN_MODE_MASK}, + {"SR_PDN_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_PDN_MODE), REG_SR_PDN_MODE_MASK}, + {"SR_RST_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_RST_MODE), REG_SR_RST_MODE_MASK}, + {"SR_RST_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_RST_MODE), REG_SR_RST_MODE_MASK}, + {"SR_HVSYNC_MODE", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_HVSYNC_MODE), REG_SR_HVSYNC_MODE_MASK}, + {"SR_PCK_MODE", _RIUA_16BIT(CHIPTOP_BANK,REG_SR_PCK_MODE), REG_SR_PCK_MODE_MASK}, + {"ETH_MODE", _RIUA_16BIT(CHIPTOP_BANK,REG_ETH_MODE), REG_ETH_MODE_MASK}, + {"I2S_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_I2S_MODE), REG_I2S_MODE_MASK}, + {"I2S_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_I2S_MODE), REG_I2S_MODE_MASK}, + {"I2S_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_I2S_MODE), REG_I2S_MODE_MASK}, + {"DMIC_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_DMIC_MODE), REG_DMIC_MODE_MASK}, + {"DMIC_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_DMIC_MODE), REG_DMIC_MODE_MASK}, + {"DMIC_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_DMIC_MODE), REG_DMIC_MODE_MASK}, + {"TTL_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), REG_TTL_MODE_MASK}, + {"TTL_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), REG_TTL_MODE_MASK}, + {"CCIR_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_CCIR_MODE), REG_CCIR_MODE_MASK}, + {"CCIR_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_CCIR_MODE), REG_CCIR_MODE_MASK}, + {"CCIR_MODE_3", _RIUA_16BIT(CHIPTOP_BANK,REG_CCIR_MODE), REG_CCIR_MODE_MASK}, + // PM Sleep + {"PM_SPI_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPI_GPIO), REG_PM_SPI_GPIO_MASK}, + {"PM_SPIWPN_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPIWPN_GPIO), REG_PM_SPIWPN_GPIO_MASK}, + {"PM_SPIHOLDN_MODE",_RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPIHOLDN_MODE), REG_PM_SPIHOLDN_MODE_MASK}, + {"PM_SPICSZ1_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPICSZ1_GPIO), REG_PM_SPICSZ1_GPIO_MASK}, + {"PM_SPICSZ2_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_SPICSZ2_GPIO), REG_PM_SPICSZ2_GPIO_MASK}, + {"PM_PWM0_MODE_1", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM0_MODE), REG_PM_PWM0_MODE_MASK}, + {"PM_PWM0_MODE_2", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM0_MODE), REG_PM_PWM0_MODE_MASK}, + {"PM_PWM1_MODE_1", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM1_MODE), REG_PM_PWM1_MODE_MASK}, + {"PM_PWM1_MODE_2", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM1_MODE), REG_PM_PWM1_MODE_MASK}, + {"PM_PWM2_MODE_1", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM2_MODE), REG_PM_PWM2_MODE_MASK}, + {"PM_PWM2_MODE_2", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM2_MODE), REG_PM_PWM2_MODE_MASK}, + {"PM_PWM3_MODE_1", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM3_MODE), REG_PM_PWM3_MODE_MASK}, + {"PM_PWM3_MODE_2", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM3_MODE), REG_PM_PWM3_MODE_MASK}, + {"PM_PWM4_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM4_MODE), REG_PM_PWM4_MODE_MASK}, + {"PM_PWM5_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM5_MODE), REG_PM_PWM5_MODE_MASK}, + {"PM_PWM8_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM8_MODE), REG_PM_PWM8_MODE_MASK}, + {"PM_PWM9_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM9_MODE), REG_PM_PWM9_MODE_MASK}, + {"PM_PWM10_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_PWM10_MODE), REG_PM_PWM10_MODE_MASK}, + {"PM_UART1_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_UART1_MODE), REG_PM_UART1_MODE_MASK}, + {"PM_VID_MODE_1", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_VID_MODE), REG_PM_VID_MODE_MASK}, + {"PM_VID_MODE_2", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_VID_MODE), REG_PM_VID_MODE_MASK}, + {"PM_VID_MODE_3", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_VID_MODE), REG_PM_VID_MODE_MASK}, + {"PM_SD_CDZ_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_SD_CDZ_MODE), REG_PM_SD_CDZ_MODE_MASK}, + {"PM_LED_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_LED_MODE), REG_PM_LED_MODE_MASK}, + {"PM_TTL_MODE_1", _RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), REG_TTL_MODE_MASK}, + {"PM_TTL_MODE_2", _RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), REG_TTL_MODE_MASK}, + {"PM_IRIN_MODE", _RIUA_16BIT(PMSLEEP_BANK,REG_PM_IR_IS_GPIO), REG_PM_IR_IS_GPIO_MASK}, + {"PM_SAR_MODE", _RIUA_16BIT(SAR_BANK,0x11), 0x3F}, + {"PM_USB_MODE", _RIUA_16BIT(UTMI0_BANK,REG_UTMI0_GPIO_EN), REG_UTMI0_GPIO_EN_MASK}, +}; + +//============================================================================== +// +// FUNCTIONS +// +//============================================================================== + +//------------------------------------------------------------------------------ +// Function : _HalCheckPin +// Description : +//------------------------------------------------------------------------------ +static S32 _HalCheckPin(U32 padID) +{ + if (GPIO_NR <= padID) { + return FALSE; + } + return TRUE; +} + +static void _HalSARGPIOWriteRegBit(u32 u32RegOffset, bool bEnable, U8 u8BitMsk) +{ + if (bEnable) + _GPIO_R_BYTE(_RIUA_8BIT(SAR_BANK, u32RegOffset)) |= u8BitMsk; + else + _GPIO_R_BYTE(_RIUA_8BIT(SAR_BANK, u32RegOffset)) &= (~u8BitMsk); +} + +static void _HalPadDisablePadMux(U32 u32PadModeID) +{ + if (_GPIO_R_WORD_MASK(m_stPadModeInfoTbl[u32PadModeID].u32ModeRIU, m_stPadModeInfoTbl[u32PadModeID].u32ModeMask)) { + _GPIO_W_WORD_MASK(m_stPadModeInfoTbl[u32PadModeID].u32ModeRIU, 0, m_stPadModeInfoTbl[u32PadModeID].u32ModeMask); + } +} + +static S32 HalPadSetMode_General(U32 u32PadID, U32 u32Mode) +{ + U32 u32RegAddr = 0; + U16 u16RegVal = 0; + U8 u8ModeIsFind = 0; + U16 i = 0; + + for (i = 0; i < sizeof(m_stPadMuxTbl)/sizeof(struct stPadMux); i++) + { + if (u32PadID == m_stPadMuxTbl[i].padID) + { + u32RegAddr = _RIUA_16BIT(m_stPadMuxTbl[i].base, m_stPadMuxTbl[i].offset); + + printk("u32RegAddr %x\n", u32RegAddr); + + if (u32Mode == m_stPadMuxTbl[i].mode) + { + u16RegVal = _GPIO_R_WORD_MASK(u32RegAddr, 0xFFFF); + u16RegVal &= ~(m_stPadMuxTbl[i].mask); + u16RegVal |= m_stPadMuxTbl[i].val; // CHECK Multi-Pad Mode + + _GPIO_W_WORD_MASK(u32RegAddr, u16RegVal, 0xFFFF); + + u8ModeIsFind = 1; +#if (ENABLE_CHECK_ALL_PAD_CONFLICT == 0) + break; +#endif + } + else + { + u16RegVal = _GPIO_R_WORD_MASK(u32RegAddr, m_stPadMuxTbl[i].mask); + + if (u16RegVal == m_stPadMuxTbl[i].val) + { + printk(KERN_INFO"[Padmux]reset PAD%d(reg 0x%x:%x; mask0x%x) t0 %s (org: %s)\n", + u32PadID, + m_stPadMuxTbl[i].base, + m_stPadMuxTbl[i].offset, + m_stPadMuxTbl[i].mask, + m_stPadModeInfoTbl[u32Mode].u8PadName, + m_stPadModeInfoTbl[m_stPadMuxTbl[i].mode].u8PadName); + if (m_stPadMuxTbl[i].val != 0) + { + _GPIO_W_WORD_MASK(u32RegAddr, 0, m_stPadMuxTbl[i].mask); + } + else + { + _GPIO_W_WORD_MASK(u32RegAddr, m_stPadMuxTbl[i].mask, m_stPadMuxTbl[i].mask); + } + } + } + } + } + + return (u8ModeIsFind) ? 0 : -1; +} + +static S32 HalPadSetMode_MISC(U32 u32PadID, U32 u32Mode) +{ + switch(u32PadID) + { + /* PM_GPIO4 */ + case PAD_PM_GPIO4: + if (u32Mode == PINMUX_FOR_GPIO_MODE) + { + _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_GPIO_PM_LOCK), 0xBABE, REG_PM_GPIO_PM_LOCK_MASK); + _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_LINK_WKINT2GPIO4), 0, REG_PM_LINK_WKINT2GPIO4_MASK); + _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_GPIO_PM4_INV), 0, REG_PM_GPIO_PM4_INV_MASK); + _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_UART1_MODE), 0, REG_PM_UART1_MODE_MASK); + _GPIO_W_WORD_MASK(_RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), 0, REG_TTL_MODE_MASK); + } + else if (u32Mode == REG_PM_UART1_MODE) + { + _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_GPIO_PM_LOCK), 0xBABE, REG_PM_GPIO_PM_LOCK_MASK); + _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_LINK_WKINT2GPIO4), 0, REG_PM_LINK_WKINT2GPIO4_MASK); + _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_GPIO_PM4_INV), 0, REG_PM_GPIO_PM4_INV_MASK); + _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_UART1_MODE), 0, REG_PM_UART1_MODE_MASK); + } + else if (u32Mode == PINMUX_FOR_TTL_MODE_1) + { + _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_GPIO_PM_LOCK), 0xBABE, REG_PM_GPIO_PM_LOCK_MASK); + _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_LINK_WKINT2GPIO4), 0, REG_PM_LINK_WKINT2GPIO4_MASK); + _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_GPIO_PM4_INV), 0, REG_PM_GPIO_PM4_INV_MASK); + _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_UART1_MODE), 0, REG_PM_UART1_MODE_MASK); + _GPIO_W_WORD_MASK(_RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), BIT6, REG_TTL_MODE_MASK); + } + else if (u32Mode == PINMUX_FOR_TTL_MODE_2) + { + _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_GPIO_PM_LOCK), 0xBABE, REG_PM_GPIO_PM_LOCK_MASK); + _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_LINK_WKINT2GPIO4), 0, REG_PM_LINK_WKINT2GPIO4_MASK); + _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_GPIO_PM4_INV), 0, REG_PM_GPIO_PM4_INV_MASK); + _GPIO_W_WORD_MASK(_RIUA_16BIT(PMSLEEP_BANK,REG_PM_UART1_MODE), 0, REG_PM_UART1_MODE_MASK); + _GPIO_W_WORD_MASK(_RIUA_16BIT(CHIPTOP_BANK,REG_TTL_MODE), BIT7, REG_TTL_MODE_MASK); + } + else + { + return -1; + } + break; + + /* SAR */ + case PAD_SAR_GPIO0: /* reg_sar_aisel; reg[1422]#5 ~ #0=0b */ + if (u32Mode == PINMUX_FOR_GPIO_MODE) + { + _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); + _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); + _HalSARGPIOWriteRegBit(REG_SAR_AISEL_8BIT, 0, REG_SAR_CH0_AISEL); + } + else if (u32Mode == PINMUX_FOR_SAR_MODE) + { + _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); + _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); + _HalSARGPIOWriteRegBit(REG_SAR_AISEL_8BIT, REG_SAR_CH0_AISEL, REG_SAR_CH0_AISEL); + } + else + { + return -1; + } + break; + case PAD_SAR_GPIO1: + if (u32Mode == PINMUX_FOR_GPIO_MODE) + { + _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); + _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); + _HalSARGPIOWriteRegBit(REG_SAR_AISEL_8BIT, 0, REG_SAR_CH1_AISEL); + } + else if (u32Mode == PINMUX_FOR_SAR_MODE) + { + _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); + _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); + _HalSARGPIOWriteRegBit(REG_SAR_AISEL_8BIT, REG_SAR_CH1_AISEL, REG_SAR_CH1_AISEL); + } + else + { + return -1; + } + break; + case PAD_SAR_GPIO2: + if (u32Mode == PINMUX_FOR_GPIO_MODE) + { + _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); + _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); + _HalSARGPIOWriteRegBit(REG_SAR_AISEL_8BIT, 0, REG_SAR_CH2_AISEL); + } + else if (u32Mode == PINMUX_FOR_SAR_MODE) + { + _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); + _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); + _HalSARGPIOWriteRegBit(REG_SAR_AISEL_8BIT, REG_SAR_CH2_AISEL, REG_SAR_CH2_AISEL); + } + else + { + return -1; + } + break; + case PAD_SAR_GPIO3: + if (u32Mode == PINMUX_FOR_GPIO_MODE) + { + _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); + _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); + _HalSARGPIOWriteRegBit(REG_SAR_AISEL_8BIT, 0, REG_SAR_CH3_AISEL); + } + else if (u32Mode == PINMUX_FOR_SAR_MODE) + { + _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); + _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); + _HalSARGPIOWriteRegBit(REG_SAR_AISEL_8BIT, REG_SAR_CH3_AISEL, REG_SAR_CH3_AISEL); + } + else + { + return -1; + } + break; + + /* lan-top */ + case PAD_ETH_RN: + if (u32Mode == PINMUX_FOR_GPIO_MODE) + { + _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); + _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); + _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), BIT14, BIT14); + _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), BIT0, BIT0); + } + else if (u32Mode == PINMUX_FOR_ETH_MODE) + { + _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); + _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); + _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), 0, BIT14); + _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), 0, BIT0); + } + else + { + return -1; + } + break; + case PAD_ETH_RP: + if (u32Mode == PINMUX_FOR_GPIO_MODE) { + _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); + _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); + _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), BIT14, BIT14); + _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), BIT1, BIT1); + } + else if (u32Mode == PINMUX_FOR_ETH_MODE) + { + _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); + _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); + _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), 0, BIT14); + _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), 0, BIT1); + } + else + { + return -1; + } + break; + case PAD_ETH_TN: + if (u32Mode == PINMUX_FOR_GPIO_MODE) + { + _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); + _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); + _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), BIT15, BIT15); + _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), BIT2, BIT2); + } + else if (u32Mode == PINMUX_FOR_ETH_MODE) + { + _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); + _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); + _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), 0, BIT15); + _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), 0, BIT2); + } + else + { + return -1; + } + break; + case PAD_ETH_TP: + if (u32Mode == PINMUX_FOR_GPIO_MODE) + { + _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); + _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); + _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), BIT15, BIT15); + _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), BIT3, BIT3); + } + else if (u32Mode == PINMUX_FOR_ETH_MODE) + { + _HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE_2); + _HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE_2); + _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY1_BANK,REG_ATOP_RX_INOFF), 0, BIT15); + _GPIO_W_WORD_MASK(_RIUA_16BIT(ALBANY2_BANK,REG_ETH_GPIO_EN), 0, BIT3); + } + else + { + return -1; + } + break; + + /* UTMI */ + case PAD_USB_DM: + case PAD_USB_DP: + if (u32Mode == PINMUX_FOR_GPIO_MODE) + { + //_HalPadDisablePadMux(PINMUX_FOR_TEST_IN_MODE); + //_HalPadDisablePadMux(PINMUX_FOR_TEST_OUT_MODE); + _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_GPIO_EN), REG_UTMI0_GPIO_EN_MASK, REG_UTMI0_GPIO_EN_MASK); + _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_CLK_EXTRA0_EN), REG_UTMI0_CLK_EXTRA0_EN_MASK, REG_UTMI0_CLK_EXTRA0_EN_MASK); + _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_REG_PDN), REG_UTMI0_REG_PDN_MASK, REG_UTMI0_REG_PDN_MASK); + _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_FL_XVR_PDN), REG_UTMI0_FL_XVR_PDN_MASK, REG_UTMI0_FL_XVR_PDN_MASK); + } + else if (u32Mode == PINMUX_FOR_USB_MODE) + { + _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_GPIO_EN), ~REG_UTMI0_GPIO_EN_MASK, REG_UTMI0_GPIO_EN_MASK); + _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_CLK_EXTRA0_EN), ~REG_UTMI0_CLK_EXTRA0_EN_MASK, REG_UTMI0_CLK_EXTRA0_EN_MASK); + _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_REG_PDN), ~REG_UTMI0_REG_PDN_MASK, REG_UTMI0_REG_PDN_MASK); + _GPIO_W_WORD_MASK(_RIUA_16BIT(UTMI0_BANK,REG_UTMI0_FL_XVR_PDN), REG_UTMI0_FL_XVR_PDN_MASK, REG_UTMI0_FL_XVR_PDN_MASK); + } + else + { + return -1; + } + break; + default: + break; + } + + return 0; +} + +//------------------------------------------------------------------------------ +// Function : HalPadSetVal +// Description : +//------------------------------------------------------------------------------ +S32 HalPadSetVal(U32 u32PadID, U32 u32Mode) +{ + if (FALSE == _HalCheckPin(u32PadID)) { + return FALSE; + } + + if (u32PadID == PAD_PM_GPIO4 || + (u32PadID >= PAD_SAR_GPIO0 && u32PadID <= PAD_USB_DP)) + { + return HalPadSetMode_MISC(u32PadID, u32Mode); + } + else + { + return HalPadSetMode_General(u32PadID, u32Mode); + } +} +//------------------------------------------------------------------------------ +// Function : HalPadSet +// Description : +//------------------------------------------------------------------------------ +S32 HalPadSetMode(U32 u32Mode) +{ + U32 u32PadID; + U16 k = 0; + + for (k = 0; k < sizeof(m_stPadMuxTbl)/sizeof(struct stPadMux); k++) + { + if (u32Mode == m_stPadMuxTbl[k].mode) + { + u32PadID = m_stPadMuxTbl[k].padID; + if (HalPadSetMode_General( u32PadID, u32Mode) < 0) + { + return -1; + } + } + } + + return 0; +} diff --git a/general/package/microsnander/Config.in b/general/package/microsnander/Config.in index bef49634..76a1e1c2 100644 --- a/general/package/microsnander/Config.in +++ b/general/package/microsnander/Config.in @@ -1,6 +1,8 @@ config BR2_PACKAGE_MICROSNANDER bool "microsnander" default n + depends on BR2_INSTALL_LIBUSB + select BR2_PACKAGE_LIBUSB help tripped down and modified version of Serial Nor/nAND/Eeprom programmeR diff --git a/general/package/microsnander/microsnander.mk b/general/package/microsnander/microsnander.mk index bf6cac34..137dfc3a 100644 --- a/general/package/microsnander/microsnander.mk +++ b/general/package/microsnander/microsnander.mk @@ -4,7 +4,7 @@ # ################################################################################ -MICROSNANDER_VERSION = df9cc51c27a84c2d7eee8d90b7586a11d97c7ff2 +MICROSNANDER_VERSION = 17ad43fe93126fcff5135c54d7d375f5dd901387 MICROSNANDER_SITE = $(call github,openipc,microsnander,$(MICROSNANDER_VERSION)) MICROSNANDER_LICENSE = MIT MICROSNANDER_LICENSE_FILES = LICENSE @@ -14,7 +14,7 @@ define MICROSNANDER_BUILD_CMDS endef define MICROSNANDER_INSTALL_TARGET_CMDS - $(INSTALL) -m 0755 -D $(@D)/src/snander $(TARGET_DIR)/usr/sbin/microsnander + $(INSTALL) -m 0755 -D $(@D)/src/microsnander $(TARGET_DIR)/usr/sbin/microsnander endef $(eval $(generic-package)) diff --git a/general/package/sigmastar-osdrv-msc313e/files/script/S95sigmastar b/general/package/sigmastar-osdrv-msc313e/files/script/S95sigmastar index 2f98e022..076d7e18 100755 --- a/general/package/sigmastar-osdrv-msc313e/files/script/S95sigmastar +++ b/general/package/sigmastar-osdrv-msc313e/files/script/S95sigmastar @@ -31,7 +31,7 @@ load_majestic() { # The daemon does not create a pidfile, and use "-m" to instruct start-stop-daemon to create one. start() { logger -s -p daemon.info -t sigmastar "Check MAC for Sigmastar devices" - if [ "$(fw_printenv -n ethaddr)" = "D0:22:12:88:88:88" ]; then + if [ "$(fw_printenv -n ethaddr)" = "00:00:23:34:45:66" ]; then logger -s -p daemon.info -t sigmastar "The eth0 interface has a lousy MAC, let's try to change it.." else logger -s -p daemon.info -t sigmastar "The eth0 interface has a correct MAC - $(fw_printenv -n ethaddr)" diff --git a/general/package/sigmastar-osdrv-ssc335/files/script/S95sigmastar b/general/package/sigmastar-osdrv-ssc335/files/script/S95sigmastar index 7408d8c6..35480876 100755 --- a/general/package/sigmastar-osdrv-ssc335/files/script/S95sigmastar +++ b/general/package/sigmastar-osdrv-ssc335/files/script/S95sigmastar @@ -31,7 +31,7 @@ load_majestic() { # The daemon does not create a pidfile, and use "-m" to instruct start-stop-daemon to create one. start() { logger -s -p daemon.info -t sigmastar "Check MAC for Sigmastar devices" - if [ "$(fw_printenv -n ethaddr)" = "D0:22:12:88:88:88" ]; then + if [ "$(fw_printenv -n ethaddr)" = "00:00:23:34:45:66" ]; then logger -s -p daemon.info -t sigmastar "The eth0 interface has a lousy MAC, let's try to change it.." else logger -s -p daemon.info -t sigmastar "The eth0 interface has a correct MAC - $(fw_printenv -n ethaddr)"