diff --git a/general/package/hisilicon-osdrv-hi3516ev200/files/sensor/config/gc4653_i2c_4M.ini b/general/package/hisilicon-osdrv-hi3516ev200/files/sensor/config/gc4653_i2c_4M.ini new file mode 100644 index 00000000..8e92e0d2 --- /dev/null +++ b/general/package/hisilicon-osdrv-hi3516ev200/files/sensor/config/gc4653_i2c_4M.ini @@ -0,0 +1,67 @@ +[sensor] +Sensor_type=stSnsgc4653_2lObj +Mode=WDR_MODE_NONE +DllFile=libsns_gc4653_2l.so + +[mode] +input_mode=INPUT_MODE_MIPI +raw_bitness=10 +clock=27MHz + +[mipi] +lane_id = 0|1|-1|-1|-1|-1|-1|-1| ;lane_id: -1 - disable + +[isp_image] +Isp_FrameRate=25 +Isp_Bayer=BAYER_GRBG + +[vi_dev] +Input_mod=VI_MODE_MIPI +Work_mod = VI_WORK_MODE_1Multiplex +Mask_num = 2 +Mask_0 = 0xFFC00000 +Mask_1 = 0x0 +Scan_mode = VI_SCAN_PROGRESSIVE +Data_seq = VI_DATA_SEQ_YUYV +Vsync =1 ; vertical synchronization signal + ;VI_VSYNC_PULSE, +VsyncNeg=1 ;Polarity of the vertical synchronization signal + ;VI_VSYNC_NEG_HIGH = 0, + ;VI_VSYNC_NEG_LOW /*if VIU_VSYNC_E +Hsync =0 ;Attribute of the horizontal synchronization signal + ;VI_HSYNC_VALID_SINGNAL = 0, + ;VI_HSYNC_PULSE, +HsyncNeg =0 ;Polarity of the horizontal synchronization signal + ;VI_HSYNC_NEG_HIGH = 0, + ;VI_HSYNC_NEG_LOW +VsyncValid =1 ;Attribute of the valid vertical synchronization signal + ;VI_VSYNC_NORM_PULSE = 0, + ;VI_VSYNC_VALID_SINGAL, +VsyncValidNeg =0;Polarity of the valid vertical synchronization signal + ;VI_VSYNC_VALID_NEG_HIGH = 0, + ;VI_VSYNC_VALID_NEG_LOW +Timingblank_HsyncHfb =0 ;Horizontal front blanking width +Timingblank_HsyncAct =2560 ;Horizontal effetive width +Timingblank_HsyncHbb =0 ;Horizontal back blanking width +Timingblank_VsyncVfb =0 ;Vertical front blanking height +Timingblank_VsyncVact =1440 ;Vertical effetive width +Timingblank_VsyncVbb=0 ;Vertical back blanking height +Timingblank_VsyncVbfb =0 ;Even-field vertical front blanking height(interlace, invalid progressive) +Timingblank_VsyncVbact=0 ;Even-field vertical effetive width(interlace, invalid progressive) +Timingblank_VsyncVbbb =0 ;Even-field vertical back blanking height(interlace, invalid progressive) +InputDataType=1 ;VI_DATA_TYPE_YUV = 0,VI_DATA_TYPE_RGB = 1, +DataRev =FALSE ;Data reverse. FALSE = 0; TRUE = 1 +DevRect_w=2560 +DevRect_h=1440 +DevRect_x=0 +DevRect_y=0 + +Combine_mode =0 ;Y/C composite or separation mode + ;VI_COMBINE_COMPOSITE = 0 /*Composite mode */ + ;VI_COMBINE_SEPARATE, /*Separate mode */ +Comp_mode =0 ;Component mode (single-component or dual-component) + ;VI_COMP_MODE_SINGLE = 0, /*single component mode */ + ;VI_COMP_MODE_DOUBLE = 1, /*double component mode */ +Clock_edge =1 ;Clock edge mode (sampling on the rising or falling edge) + ;VI_CLK_EDGE_SINGLE_UP=0, /*rising edge */ + ;VI_CLK_EDGE_SINGLE_DOWN, /*falling edge */ diff --git a/general/package/hisilicon-osdrv-hi3516ev200/files/sensor/config/sc3335_i2c_3M.ini b/general/package/hisilicon-osdrv-hi3516ev200/files/sensor/config/sc3335_i2c_3M.ini new file mode 100644 index 00000000..b12dbe40 --- /dev/null +++ b/general/package/hisilicon-osdrv-hi3516ev200/files/sensor/config/sc3335_i2c_3M.ini @@ -0,0 +1,79 @@ +[sensor] +Sensor_type=stSnsSc3335Obj +Mode=WDR_MODE_NONE +DllFile=libsns_sc3335.so + +[mode] +input_mode=INPUT_MODE_MIPI +raw_bitness=10 + +[mipi] +lane_id = 0|2|-1|-1|-1|-1|-1|-1| ;lane_id: -1 - disable + +[isp_image] +Isp_FrameRate=20 +Isp_Bayer=BAYER_BGGR + +[vi_dev] +Input_mod=VI_MODE_MIPI +Work_mod =0 ;VI_WORK_MODE_1Multiplex = 0 + ;VI_WORK_MODE_2Multiplex, + ;VI_WORK_MODE_4Multiplex +Combine_mode =0 ;Y/C composite or separation mode + ;VI_COMBINE_COMPOSITE = 0 /*Composite mode */ + ;VI_COMBINE_SEPARATE, /*Separate mode */ +Comp_mode =0 ;Component mode (single-component or dual-component) + ;VI_COMP_MODE_SINGLE = 0, /*single component mode */ + ;VI_COMP_MODE_DOUBLE = 1, /*double component mode */ +Clock_edge =1 ;Clock edge mode (sampling on the rising or falling edge) + ;VI_CLK_EDGE_SINGLE_UP=0, /*rising edge */ + ;VI_CLK_EDGE_SINGLE_DOWN, /*falling edge */ +Mask_num =2 ;Component mask +Mask_0 =0xFFF00000 +Mask_1 =0x0 +Scan_mode = 1;VI_SCAN_INTERLACED = 0 + ;VI_SCAN_PROGRESSIVE, +Data_seq =2 ;data sequence (ONLY for YUV format) + ;----2th component U/V sequence in bt1120 + ; VI_INPUT_DATA_VUVU = 0, + ; VI_INPUT_DATA_UVUV, + ;----input sequence for yuv + ; VI_INPUT_DATA_UYVY = 0, + ; VI_INPUT_DATA_VYUY, + ; VI_INPUT_DATA_YUYV, + ; VI_INPUT_DATA_YVYU + +Vsync =1 ; vertical synchronization signal + ;VI_VSYNC_FIELD = 0, + ;VI_VSYNC_PULSE, +VsyncNeg=1 ;Polarity of the vertical synchronization signal + ;VI_VSYNC_NEG_HIGH = 0, + ;VI_VSYNC_NEG_LOW /*if VIU_VSYNC_E +Hsync =0 ;Attribute of the horizontal synchronization signal + ;VI_HSYNC_VALID_SINGNAL = 0, + ;VI_HSYNC_PULSE, +HsyncNeg =0 ;Polarity of the horizontal synchronization signal + ;VI_HSYNC_NEG_HIGH = 0, + ;VI_HSYNC_NEG_LOW +VsyncValid =1 ;Attribute of the valid vertical synchronization signal + ;VI_VSYNC_NORM_PULSE = 0, + ;VI_VSYNC_VALID_SINGAL, +VsyncValidNeg =0;Polarity of the valid vertical synchronization signal + ;VI_VSYNC_VALID_NEG_HIGH = 0, + ;VI_VSYNC_VALID_NEG_LOW +Timingblank_HsyncHfb =0 ;Horizontal front blanking width +Timingblank_HsyncAct =2304 ;Horizontal effetive width +Timingblank_HsyncHbb =0 ;Horizontal back blanking width +Timingblank_VsyncVfb =0 ;Vertical front blanking height +Timingblank_VsyncVact =1296 ;Vertical effetive width +Timingblank_VsyncVbb=0 ;Vertical back blanking height +Timingblank_VsyncVbfb =0 ;Even-field vertical front blanking height(interlace, invalid progressive) +Timingblank_VsyncVbact=0 ;Even-field vertical effetive width(interlace, invalid progressive) +Timingblank_VsyncVbbb =0 ;Even-field vertical back blanking height(interlace, invalid progressive) +InputDataType=1 ;VI_DATA_TYPE_YUV = 0,VI_DATA_TYPE_RGB = 1, +DataRev =FALSE ;Data reverse. FALSE = 0; TRUE = 1 +DevRect_x=200 +DevRect_y=20 +DevRect_w=2304 +DevRect_h=1296 +FullLinesStd=1350 diff --git a/general/package/hisilicon-osdrv-hi3516ev200/files/sensor/libsns_gc4653_2l.so b/general/package/hisilicon-osdrv-hi3516ev200/files/sensor/libsns_gc4653_2l.so new file mode 100644 index 00000000..5fb50b03 Binary files /dev/null and b/general/package/hisilicon-osdrv-hi3516ev200/files/sensor/libsns_gc4653_2l.so differ diff --git a/general/package/hisilicon-osdrv-hi3516ev200/files/sensor/libsns_sc3335.so b/general/package/hisilicon-osdrv-hi3516ev200/files/sensor/libsns_sc3335.so new file mode 100644 index 00000000..17139eb7 Binary files /dev/null and b/general/package/hisilicon-osdrv-hi3516ev200/files/sensor/libsns_sc3335.so differ