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Linux: remove kernel overlay files

pull/853/head
Viktor 2023-06-02 16:51:56 +02:00 committed by viktorxda
parent 7e1518fdc6
commit adcd9904ac
51 changed files with 0 additions and 50643 deletions
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3537
br-ext-chip-allwinner/board/v83x/kernel/overlay/arch/arm/boot/dts/board.dts
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br-ext-chip-anyka/board/ak3918ev300/kernel/overlay/lib/libakaudiofilter_kern.a
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br-ext-chip-anyka/board/ak3918ev300/kernel/overlay/lib/libakecho.a
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br-ext-chip-anyka/board/ak3918ev300/kernel/overlay/lib/libispdrv.a
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br-ext-chip-anyka/board/ak3918ev300/kernel/overlay/lib/libpartition.a
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40
br-ext-chip-fullhan/board/fh8833v100/kernel/overlay/arch/arm/mach-fh/include/mach/board_config.fh8833.appboard
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/*
* board_config.h
*
* Created on: Jan 9, 2017
* Author: duobao
*/
#ifndef BOARD_CONFIG_H_
#define BOARD_CONFIG_H_
/*
* GPIO0 -> IRCUT_ON
* GPIO1 -> IRCUT_OFF
* GPIO2 -> PHY Reset
* GPIO3 -> IR
* GPIO13 -> Sensor Reset
* GPIO14 -> Sensor Power Down
* GPIO55 -> CSN1
*/
#define CONFIG_GPIO_EMACPHY_RESET 2
#define CONFIG_GPIO_EMACPHY_RXDV 41
#define CONFIG_SD_WP_FIXED
#define CONFIG_PINCTRL_SELECT \
"MIPI", "RMII", "UART0", "USB", "DWI2S", \
"I2C0", "SSI0", "SD0_CARD_1BIT", \
"GPIO0", "GPIO1", "GPIO2", "GPIO3", \
"GPIO13", \
\
"GPIO4", "GPIO11", "GPIO5", "GPIO6", "GPIO7", \
"GPIO8", "GPIO9", "GPIO10", "GPIO14", "GPIO19", \
"GPIO20", "GPIO21", "GPIO23", "GPIO28", "GPIO29", \
"GPIO30", "GPIO31", "GPIO32", "GPIO33", "GPIO35", \
"GPIO36", "GPIO37", "GPIO39", "GPIO40", "GPIO44", \
"GPIO45", "GPIO47", "GPIO50", "GPIO51", "GPIO55", \
"GPIO61", \
#endif /* BOARD_CONFIG_H_ */

45
br-ext-chip-fullhan/board/fh8852v100/kernel/overlay/arch/arm/mach-fh/include/mach/board_config.fh8852.appboard
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/*
* board_config.h
*
* Created on: Jan 9, 2017
* Author: duobao
*/
#ifndef BOARD_CONFIG_H_
#define BOARD_CONFIG_H_
/*
* GPIO0 -> IRCUT_ON
* GPIO1 -> IRCUT_OFF
* GPIO2 -> USB_PWREN
* GPIO3 -> SD1_PWREN/WIFI_REG_ON
* GPIO7 -> IR
* GPIO11 -> EMAC PHY Reset
* GPIO12 -> CIS_CLK
* GPIO13 -> CIS_RSTN
* GPIO14 -> CIS_PDN
*/
#define CONFIG_GPIO_EMACPHY_RESET 11
#define CONFIG_GPIO_EMACPHY_RXDV 41
#define CONFIG_GPIO_USB_PWREN 2
#define CONFIG_ISP_CLK_RATE 150000000
#define CONFIG_HEVC_CLK_RATE 200000000
#define CONFIG_PAE_CLK_RATE 240000000
#define FH_BOARD_8852
#define CONFIG_PINCTRL_SELECT \
"I2C0", "MIPI", "RMII", "SD0_NO_WP", "SSI0_4BIT",\
"UART0", "GPIO0", "GPIO1", "GPIO2", "GPIO3", "GPIO7",\
"GPIO11", "GPIO13", "GPIO14",\
\
/* 未引出的pad，默认配置为GPIO */ \
"GPIO4", "GPIO5", "GPIO6", "GPIO8", "GPIO9", "GPIO10",\
"GPIO19", "GPIO20", "GPIO21", "GPIO22", "GPIO23", "GPIO24",\
"GPIO25", "GPIO26", "GPIO27", "GPIO28", "GPIO53",\
"GPIO55"
#endif /* BOARD_CONFIG_H_ */

47
br-ext-chip-fullhan/board/fh8852v100/kernel/overlay/arch/arm/mach-fh/include/mach/board_config.fh8856.appboard
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/*
* board_config.h
*
* Created on: Jan 9, 2017
* Author: duobao
*/
#ifndef BOARD_CONFIG_H_
#define BOARD_CONFIG_H_
/*
* GPIO0 -> IRCUT_ON
* GPIO1 -> IRCUT_OFF
* GPIO2 -> USB_PWREN
* GPIO11 -> EMAC PHY Reset
* GPIO12 -> CIS_CLK
* GPIO13 -> CIS_RSTN
* GPIO14 -> CIS_PDN
* GPIO19 -> SD1_PWREN/WIFI_REG_ON
* GPIO20 -> AK7755 Reset
* GPIO24 -> LED0
* GPIO25 -> LED1
* GPIO26 -> Reset Configs
* GPIO27 -> AK7755 PowerDown
* GPIO28 -> IR
* GPIO53 -> USB_PWREN/SD0_PWREN
* GPIO55 -> SD1 WIFI Interrupt
*/
#define CONFIG_GPIO_EMACPHY_RESET 11
#define CONFIG_GPIO_EMACPHY_RXDV 41
#define CONFIG_GPIO_USB_PWREN 2
#define CONFIG_ISP_CLK_RATE 200000000
#define CONFIG_HEVC_CLK_RATE 300000000
#define CONFIG_PAE_CLK_RATE 400000000
#define FH_BOARD_8856
#define CONFIG_PINCTRL_SELECT \
"I2C0", "I2C1", "MIPI", "RMII", "SD0_NO_WP", \
"SD1_NO_WP", "SSI0_4BIT", "UART0", "GPIO0", "GPIO1", \
"GPIO2", "GPIO3", "GPIO11", "GPIO13", "GPIO14", \
"GPIO19", "GPIO20", "GPIO24", "GPIO25", "GPIO26", \
"GPIO27", "GPIO28", "GPIO53", "GPIO55"
#endif /* BOARD_CONFIG_H_ */

156
br-ext-chip-goke/board/gk7205v200/kernel/overlay/arch/arm/boot/dts/gk7202v300-demb.dts
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/*
* Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
*/
/dts-v1/;
#include "gk7202v300.dtsi"
/ {
model = "Goke GK7202V300 DEMO Board";
compatible = "goke,gk7202v300";
memory {
device_type = "memory";
reg = <0x40000000 0x20000000>;
};
};
&uart0 {
status = "okay";
};
&uart1 {
status = "disabled";
};
&uart2 {
status = "disabled";
};
&i2c_bus0 {
status = "okay";
clock-frequency = <100000>;
};
&i2c_bus1 {
status = "okay";
clock-frequency = <100000>;
};
&i2c_bus2 {
status = "okay";
clock-frequency = <100000>;
};
&spi_bus0{
status = "okay";
num-cs = <1>;
spidev@0 {
compatible = "rohm,dh2228fv";
reg = <0>;
pl022,interface = <0>;
pl022,com-mode = <0>;
spi-max-frequency = <50000000>;
};
};
&spi_bus1{
status = "okay";
num-cs = <2>;
spidev@0 {
compatible = "rohm,dh2228fv";
reg = <0>;
pl022,interface = <0>;
pl022,com-mode = <0>;
spi-max-frequency = <50000000>;
};
spidev@1 {
compatible = "rohm,dh2228fv";
reg = <1>;
pl022,interface = <0>;
pl022,com-mode = <0>;
spi-max-frequency = <50000000>;
};
};
&dual_timer0 {
status = "okay";
};
&mdio0 {
goke,phy-reset-delays-us = <10000 20000 150000>;
phy0: ethernet-phy@1 {
reg = <1>;
};
};
&femac {
mac-address = [00 00 00 00 00 00];
phy-mode = "mii";
phy-handle = <&phy0>;
status = "okay";
};
&sfc {
sfc {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <160000000>;
};
};
&snfc {
nand {
compatible = "jedec,spi-nand";
reg = <0>;
spi-max-frequency = <160000000>;
};
};
&mmc0 {
status = "okay";
};
&mmc1 {
status = "okay";
};
&gpio_chip0 {
status = "okay";
};
&gpio_chip1 {
status = "okay";
};
&gpio_chip2 {
status = "okay";
};
&gpio_chip4 {
status = "okay";
};
&gpio_chip5 {
status = "okay";
};
&gpio_chip6 {
status = "okay";
};
&gpio_chip7 {
status = "okay";
};
&gpio_chip8 {
status = "okay";
};
&usbdrd3_0 {
dwc3@0x100e0000 {
dr_mode = "host";
};
};

626
br-ext-chip-goke/board/gk7205v200/kernel/overlay/arch/arm/boot/dts/gk7202v300.dtsi
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/*
* Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
*/
#include "skeleton.dtsi"
#include <dt-bindings/clock/gk7202v300-clock.h>
/ {
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
i2c0 = &i2c_bus0;
i2c1 = &i2c_bus1;
i2c2 = &i2c_bus2;
spi0 = &spi_bus0;
spi1 = &spi_bus1;
gpio0 = &gpio_chip0;
gpio1 = &gpio_chip1;
gpio2 = &gpio_chip2;
gpio4 = &gpio_chip4;
gpio5 = &gpio_chip5;
gpio6 = &gpio_chip6;
gpio7 = &gpio_chip7;
gpio8 = &gpio_chip8;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "goke,gk7202v300";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
clock-frequency = <GK7202V300_FIXED_1000M>;
reg = <0>;
};
};
pmu {
compatible = "arm,armv7-pmu";
interrupts = <0 58 4>;
};
clock: clock@12010000 {
compatible = "goke,gk7202v300-clock", "syscon";
#address-cells = <1>;
#size-cells = <1>;
#clock-cells = <1>;
#reset-cells = <2>;
reg = <0x12010000 0x1000>;
};
gic: interrupt-controller@10300000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
/* gic dist base, gic cpu base , no virtual support */
reg = <0x10301000 0x1000>, <0x10302000 0x100>;
};
syscounter {
compatible = "arm,armv7-timer";
interrupt-parent = <&gic>;
interrupts = <1 13 0xf08>,
<1 14 0xf08>;
clock-frequency = <50000000>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
clk_3m: clk_3m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <3000000>;
};
clk_apb: clk_apb {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
};
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <0 58 4>;
};
sysctrl: system-controller@12020000 {
compatible = "goke,sysctrl";
reg = <0x12020000 0x1000>;
reboot-offset = <0x4>;
#clock-cells = <1>;
};
iocfg_ctrl: iocfg-controller@100c0000 {
compatible = "syscon";
reg = <0x100C0000 0x10000>;
};
iocfg_ctrl2: iocfg-controller2@112c0000 {
compatible = "syscon";
reg = <0x112C0000 0x10000>;
};
#ifdef CONFIG_EDMAC
edmac: edma-controller@100B0000 {
compatible = "goke,edmac";
reg = <0x100B0000 0x1000>;
interrupts = <0 38 4>;
clocks = <&clock GK7202V300_EDMAC_CLK>, <&clock GK7202V300_EDMAC_AXICLK>;
clock-names = "apb_pclk", "axi_aclk";
clock-cells = <2>;
resets = <&clock 0x194 0>;
reset-names = "dma-reset";
dma-requests = <32>;
dma-channels = <4>;
devid = <0>;
#dma-cells = <2>;
status = "okay";
};
#endif
amba {
#address-cells = <1>;
#size-cells = <1>;
compatible = "arm,amba-bus";
ranges;
dual_timer0: dual_timer@12000000 {
compatible = "arm,sp804", "arm,primecell";
/* timer0 & timer1 */
interrupts = <0 5 4>;
reg = <0x12000000 0x1000>;
clocks = <&clk_3m>, <&clk_3m>, <&clk_apb>;
clock-names = "timer00", "timer01", "apb_pclk";
status = "disabled";
};
dual_timer1: dual_timer@12001000 {
compatible = "arm,sp805", "arm,primecell5";
/* timer2 & timer3 */
interrupts = <0 6 4>;
reg = <0x12001000 0x1000>;
clocks = <&clk_3m>, <&clk_3m>, <&clk_apb>;
clock-names = "timer10", "timer11", "apb_pclk";
status = "okay";
};
uart0: uart@12040000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12040000 0x1000>;
interrupts = <0 7 4>;
clocks = <&clock GK7202V300_UART0_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
uart1: uart@12041000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12041000 0x1000>;
interrupts = <0 8 4>;
clocks = <&clock GK7202V300_UART1_CLK>;
clock-names = "apb_pclk";
#ifdef CONFIG_EDMAC
dmas = <&edmac 19 19>, <&edmac 18 18>;
dma-names = "tx","rx";
#endif
status = "disabled";
};
uart2: uart@12042000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12042000 0x1000>;
interrupts = <0 9 4>;
clocks = <&clock GK7202V300_UART2_CLK>;
clock-names = "apb_pclk";
#ifdef CONFIG_EDMAC
dmas = <&edmac 21 21>, <&edmac 20 20>;
dma-names = "tx","rx";
#endif
status = "disabled";
};
};
i2c_bus0: i2c@12060000 {
compatible = "goke,goke-i2c";
reg = <0x12060000 0x1000>;
clocks = <&clock GK7202V300_I2C0_CLK>;
status = "disabled";
};
i2c_bus1: i2c@12061000 {
compatible = "goke,goke-i2c";
reg = <0x12061000 0x1000>;
clocks = <&clock GK7202V300_I2C1_CLK>;
status = "disabled";
};
i2c_bus2: i2c@12062000 {
compatible = "goke,goke-i2c";
reg = <0x12062000 0x1000>;
clocks = <&clock GK7202V300_I2C2_CLK>;
status = "disabled";
};
spi_bus0: spi@12070000 {
compatible = "arm,pl022", "arm,primecell";
arm,primecell-periphid = <0x00041022>;
reg = <0x12070000 0x1000>;
interrupts = <0 14 4>;
clocks = <&clock GK7202V300_SPI0_CLK>;
clock-names = "apb_pclk";
#address-cells = <1>;
#size-cells = <0>;
#ifdef CONFIG_EDMAC
dmas = <&edmac 27 27>, <&edmac 26 26>;
dma-names = "tx","rx";
#endif
status = "disabled";
};
spi_bus1: spi@12071000 {
compatible = "arm,pl022", "arm,primecell";
arm,primecell-periphid = <0x00041022>;
reg = <0x12071000 0x1000>, <0x12028000 0x4>;
interrupts = <0 15 4>;
clocks = <&clock GK7202V300_SPI1_CLK>;
clock-names = "apb_pclk";
#address-cells = <1>;
#size-cells = <0>;
num-cs = <2>;
spi_cs_sb = <2>;
spi_cs_mask_bit = <0x4>;//0100
#ifdef CONFIG_EDMAC
dmas = <&edmac 29 29>, <&edmac 28 28>;
dma-names = "tx","rx";
#endif
status = "disabled";
};
mdio0: mdio@10041100 {
compatible = "goke,femac-mdio";
reg = <0x10041100 0x10>,<0x12028024 0x4>;
clocks = <&clock GK7202V300_ETH0_CLK>;
clock-names = "mdio";
resets = <&clock 0x16c 3>;
reset-names = "internal-phy";
#address-cells = <1>;
#size-cells = <0>;
};
femac: ethernet@10040000 {
compatible = "goke,femac",
"goke,femac-v2";
reg = <0x10040000 0x1000>,<0x10041300 0x200>;
interrupts = <0 33 4>;
clocks = <&clock GK7202V300_ETH0_CLK>;
resets = <&clock 0x16c 0>;
reset-names = "mac";
};
fmc: flash-memory-controller@10000000 {
compatible = "goke,fmc";
reg = <0x10000000 0x1000>, <0x14000000 0x10000>;
reg-names = "control", "memory";
clocks = <&clock GK7202V300_FMC_CLK>;
max-dma-size = <0x2000>;
#address-cells = <1>;
#size-cells = <0>;
sfc:spi-nor@0 {
compatible = "goke,fmc-spi-nor";
assigned-clocks = <&clock GK7202V300_FMC_CLK>;
assigned-clock-rates = <24000000>;
#address-cells = <1>;
#size-cells = <0>;
};
snfc:spi-nand@0 {
compatible = "goke,fmc-spi-nand";
assigned-clocks = <&clock GK7202V300_FMC_CLK>;
assigned-clock-rates = <24000000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
mmc0: sdhci@0x10010000 {
compatible = "goke,sdhci";
reg = <0x10010000 0x1000>;
interrupts = <0 30 4>;
clocks = <&clock GK7202V300_MMC0_CLK>;
clock-names = "mmc_clk";
resets = <&clock 0x1f4 27>, <&clock 0x1f4 29>;
reset-names = "crg_reset", "dll_reset";
max-frequency = <150000000>;
crg_regmap = <&clock>;
iocfg_regmap = <&iocfg_ctrl>;
bus-width = <4>;
cap-mmc-highspeed;
cap-mmc-hw-reset;
cap-sd-highspeed;
mmc-hs200-1_8v;
full-pwr-cycle;
devid = <0>;
status = "enable";
};
mmc1: sdhci@0x10020000 {
compatible = "goke,sdhci";
reg = <0x10020000 0x1000>;
interrupts = <0 31 4>;
clocks = <&clock GK7202V300_MMC1_CLK>;
clock-names = "mmc_clk";
resets = <&clock 0x22c 27>, <&clock 0x22c 29>;
reset-names = "crg_reset", "dll_reset";
max-frequency = <50000000>;
crg_regmap = <&clock>;
iocfg_regmap = <&iocfg_ctrl2>;
bus-width = <4>;
cap-sd-highspeed;
full-pwr-cycle;
devid = <2>;
status = "enable";
};
usb2_phy0: phy2-0 {
compatible = "goke,usbp2-phy";
reg = <0x100D0000 0x1000>,
<0x12010000 0x1000>,
<0x100c0000 0x1000>;
clocks = <&clock GK7202V300_USB2_PHY_APB_CLK>,
<&clock GK7202V300_USB2_PHY_PLL_CLK>,
<&clock GK7202V300_USB2_PHY_XO_CLK>;
clock-names = "clk_u2phy_apb_ref",
"clk_u2phy_pll_ref",
"clk_u2phy_xo_ref";
resets = <&clock 0x140 0>,
<&clock 0x140 1>;
reset-names = "phy_por_reset",
"phy_tpor_reset";
phy_pll_offset = <0x14>;
phy_pll_mask = <0x03>;
phy_pll_val = <0x00>;
crg_offset = <0x140>;
crg_defal_mask = <0x0c07>;
crg_defal_val = <0x0807>;
vbus_offset = <0x7c>;
vbus_val = <0x0531>;
pwren_offset = <0x80>;
pwren_val = <0x1>;
ana_cfg_0_eye_val = <0x0433cc23>;
ana_cfg_0_offset = <0x00>;
ana_cfg_2_eye_val = <0x00320f0f>;
ana_cfg_2_offset = <0x08>;
ana_cfg_4_eye_val = <0x655>;
ana_cfg_4_offset = <0x10>;
trim_otp_addr = <0x12028004>;
trim_otp_mask = <0x1f>;
trim_otp_bit_offset = <0x00>;
trim_otp_min = <0x09>;
trim_otp_max = <0x1d>;
#phy-cells = <0>;
};
usbdrd3_0: usb3-0{
compatible = "goke,dwusb2";
reg = <0x10030000 0x10000>,
<0x12010000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
crg_offset = <0x140>;
crg_ctrl_def_mask = <0x3308>;
crg_ctrl_def_val = <0x1308>;
clocks = <&clock GK7202V300_USB2_BUS_CLK>,
<&clock GK7202V300_USB2_REF_CLK>,
<&clock GK7202V300_USB2_UTMI_CLK>;
clock-names = "usb2_bus_clk",
"usb2_ref_clk",
"usb2_utmi_clk";
resets = <&clock 0x140 3>;
reset-names = "vcc_reset";
ranges;
dwc3@0x100e0000 {
compatible = "snps,dwc3";
reg = <0x10030000 0x10000>;
interrupts = <0 39 4>;
interrupt-names = "peripheral";
phys = <&usb2_phy0>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
dr_mode = "peripheral";
eps_directions = <0x6a>;
snps,eps_new_init;
eps_map=<0x0 0x1 0x2 0x3 0x4 0x5 0x7>;
snps,usb2-lpm-disable;
};
};
gpio_chip0: gpio_chip@120b0000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b0000 0x1000>;
interrupts = <0 16 4>;
clocks = <&clock GK7202V300_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip1: gpio_chip@120b1000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b1000 0x1000>;
interrupts = <0 17 4>;
clocks = <&clock GK7202V300_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip2: gpio_chip@120b2000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b2000 0x1000>;
interrupts = <0 18 4>;
clocks = <&clock GK7202V300_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip4: gpio_chip@120b4000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b4000 0x1000>;
interrupts = <0 20 4>;
clocks = <&clock GK7202V300_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip5: gpio_chip@120b5000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b5000 0x1000>;
interrupts = <0 21 4>;
clocks = <&clock GK7202V300_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip6: gpio_chip@120b6000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b6000 0x1000>;
interrupts = <0 22 4>;
clocks = <&clock GK7202V300_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip7: gpio_chip@120b7000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b7000 0x1000>;
interrupts = <0 23 4>;
clocks = <&clock GK7202V300_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip8: gpio_chip@120b8000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b8000 0x1000>;
interrupts = <0 24 4>;
clocks = <&clock GK7202V300_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
rtc: rtc@120e0000 {
compatible = "goke,rtc";
reg = <0x120e0000 0x1000>;
interrupts = <0 0 4>;
};
cipher: cipher@0x10050000 {
compatible = "goke,cipher";
reg = <0x10050000 0x10000>;
reg-names = "cipher";
interrupts = <0 34 4>, <0 34 4>;
interrupt-names = "cipher", "hash";
};
adc: adc@120a0000 {
compatible = "goke,lsadc";
reg = <0x120a0000 0x1000>;
interrupts = <0 4 4>;
interrupt-names = "adc";
resets = <&clock 0x1bc 2>;
reset-names = "lsadc-crg";
status = "okay";
};
wdg: wdg@0x12030000 {
compatible = "goke,wdg";
reg = <0x12030000 0x1000>;
reg-names = "wdg";
interrupts = <0 2 4>;
interrupt-names = "wdg";
};
};
media {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
osal: osal {
compatible = "goke,osal";
};
sys: sys@12010000 {
compatible = "goke,sys";
};
mipi: mipi@0x11240000 {
compatible = "goke,mipi";
reg = <0x11240000 0x10000>;
reg-names = "mipi_rx";
interrupts = <0 45 4>;
interrupt-names = "mipi_rx";
};
vi: vi@11000000 {
compatible = "goke,vi";
reg = <0x11000000 0x200000>, <0x11200000 0x40000>;
reg-names = "VI_CAP0", "VI_PROC0";
interrupts = <0 43 4>, <0 44 4>;
interrupt-names = "VI_CAP0", "VI_PROC0";
};
isp: isp@11220000 {
compatible = "goke,isp";
reg = <0x11220000 0x20000>;
reg-names = "ISP";
interrupts = <0 43 4>;
interrupt-names = "ISP";
};
vpss: vpss@11400000 {
compatible = "goke,vpss";
reg = <0x11400000 0x10000>;
reg-names = "vpss0";
interrupts = <0 46 4>;
interrupt-names = "vpss0";
};
vo: vo@11280000 {
compatible = "goke,vo";
reg = <0x11280000 0x40000>;
reg-names = "vo";
interrupts = <0 40 4>;
interrupt-names = "vo";
};
gfbg: gfbg@11280000 {
compatible = "goke,gfbg";
reg = <0x11280000 0x40000>;
reg-names = "gfbg";
interrupts = <0 41 4>;
interrupt-names = "gfbg";
};
vgs: vgs@11300000 {
compatible = "goke,vgs";
reg = <0x11300000 0x10000>;
reg-names = "vgs0";
interrupts = <0 49 4>;
interrupt-names = "vgs0";
};
gzip: gzip@11310000 {
compatible = "goke,gzip";
reg = <0x11310000 0x10000>;
reg-names = "gzip";
interrupts = <0 50 4>;
interrupt-names = "gzip";
};
vedu: vedu@11410000 {
compatible = "goke,vedu";
reg = <0x11410000 0x10000>, <0x11420000 0x10000>;
reg-names = "vedu0", "jpge";
interrupts = <0 47 4>, <0 48 4>;
interrupt-names = "vedu0","jpge";
};
venc: venc {
compatible = "goke,venc";
};
aiao: aiao@100e0000 {
compatible = "goke,aiao";
reg = <0x100e0000 0x10000>,<0x100f0000 0x10000>;
reg-names = "aiao","acodec";
interrupts = <0 42 4>;
interrupt-names = "AIO";
};
ive: ive@11320000 {
compatible = "goke,ive";
reg = <0x11320000 0x10000>;
reg-names = "ive";
interrupts = <0 51 4>;
interrupt-names = "ive";
};
};
};

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br-ext-chip-goke/board/gk7205v200/kernel/overlay/arch/arm/boot/dts/gk7205v200-demb.dts
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@ -1,151 +0,0 @@
/*
* Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
*/
/dts-v1/;
#include "gk7205v200.dtsi"
/ {
model = "Goke GK7205V200 DEMO Board";
compatible = "goke,gk7205v200";
memory {
device_type = "memory";
reg = <0x40000000 0x20000000>;
};
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&i2c_bus0 {
status = "okay";
clock-frequency = <100000>;
};
&i2c_bus1 {
status = "okay";
clock-frequency = <100000>;
};
&i2c_bus2 {
status = "okay";
clock-frequency = <100000>;
};
&spi_bus0{
status = "okay";
num-cs = <1>;
spidev@0 {
compatible = "rohm,dh2228fv";
reg = <0>;
pl022,interface = <0>;
pl022,com-mode = <0>;
spi-max-frequency = <50000000>;
};
};
&spi_bus1{
status = "disabled";
num-cs = <2>;
spidev@0 {
compatible = "rohm,dh2228fv";
reg = <0>;
pl022,interface = <0>;
pl022,com-mode = <0>;
spi-max-frequency = <50000000>;
};
spidev@1 {
compatible = "rohm,dh2228fv";
reg = <1>;
pl022,interface = <0>;
pl022,com-mode = <0>;
spi-max-frequency = <50000000>;
};
};
&dual_timer0 {
status = "okay";
};
&mdio0 {
goke,phy-reset-delays-us = <10000 20000 150000>;
phy0: ethernet-phy@1 {
reg = <1>;
};
};
&femac {
mac-address = [00 00 00 00 00 00];
phy-mode = "mii";
phy-handle = <&phy0>;
status = "okay";
};
&sfc {
sfc {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <160000000>;
};
};
&snfc {
nand {
compatible = "jedec,spi-nand";
reg = <0>;
spi-max-frequency = <160000000>;
};
};
&mmc0 {
status = "okay";
};
&mmc1 {
status = "okay";
};
&gpio_chip0 {
status = "okay";
};
&gpio_chip1 {
status = "okay";
};
&gpio_chip2 {
status = "okay";
};
&gpio_chip4 {
status = "okay";
};
&gpio_chip5 {
status = "okay";
};
&gpio_chip6 {
status = "okay";
};
&gpio_chip7 {
status = "okay";
};
&gpio_chip8 {
status = "okay";
};

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/*
* Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
*/
#include "skeleton.dtsi"
#include <dt-bindings/clock/gk7205v200-clock.h>
/ {
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
i2c0 = &i2c_bus0;
i2c1 = &i2c_bus1;
i2c2 = &i2c_bus2;
spi0 = &spi_bus0;
spi1 = &spi_bus1;
gpio0 = &gpio_chip0;
gpio1 = &gpio_chip1;
gpio2 = &gpio_chip2;
gpio4 = &gpio_chip4;
gpio5 = &gpio_chip5;
gpio6 = &gpio_chip6;
gpio7 = &gpio_chip7;
gpio8 = &gpio_chip8;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "goke,gk7205v200";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
clock-frequency = <GK7205V200_FIXED_1000M>;
reg = <0>;
};
};
pmu {
compatible = "arm,armv7-pmu";
interrupts = <0 58 4>;
};
clock: clock@12010000 {
compatible = "goke,gk7205v200-clock", "syscon";
#address-cells = <1>;
#size-cells = <1>;
#clock-cells = <1>;
#reset-cells = <2>;
reg = <0x12010000 0x1000>;
};
gic: interrupt-controller@10300000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
/* gic dist base, gic cpu base , no virtual support */
reg = <0x10301000 0x1000>, <0x10302000 0x100>;
};
syscounter {
compatible = "arm,armv7-timer";
interrupt-parent = <&gic>;
interrupts = <1 13 0xf08>,
<1 14 0xf08>;
clock-frequency = <50000000>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
clk_3m: clk_3m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <3000000>;
};
clk_apb: clk_apb {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
};
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <0 58 4>;
};
sysctrl: system-controller@12020000 {
compatible = "goke,sysctrl";
reg = <0x12020000 0x1000>;
reboot-offset = <0x4>;
#clock-cells = <1>;
};
iocfg_ctrl: iocfg-controller@100c0000 {
compatible = "syscon";
reg = <0x100C0000 0x10000>;
};
iocfg_ctrl2: iocfg-controller2@112c0000 {
compatible = "syscon";
reg = <0x112C0000 0x10000>;
};
#ifdef CONFIG_EDMAC
edmac: edma-controller@100B0000 {
compatible = "goke,edmac";
reg = <0x100B0000 0x1000>;
interrupts = <0 38 4>;
clocks = <&clock GK7205V200_EDMAC_CLK>, <&clock GK7205V200_EDMAC_AXICLK>;
clock-names = "apb_pclk", "axi_aclk";
clock-cells = <2>;
resets = <&clock 0x194 0>;
reset-names = "dma-reset";
dma-requests = <32>;
dma-channels = <4>;
devid = <0>;
#dma-cells = <2>;
status = "okay";
};
#endif
amba {
#address-cells = <1>;
#size-cells = <1>;
compatible = "arm,amba-bus";
ranges;
dual_timer0: dual_timer@12000000 {
compatible = "arm,sp804", "arm,primecell";
/* timer0 & timer1 */
interrupts = <0 5 4>;
reg = <0x12000000 0x1000>;
clocks = <&clk_3m>, <&clk_3m>, <&clk_apb>;
clock-names = "timer00", "timer01", "apb_pclk";
status = "disabled";
};
dual_timer1: dual_timer@12001000 {
compatible = "arm,sp805", "arm,primecell5";
/* timer2 & timer3 */
interrupts = <0 6 4>;
reg = <0x12001000 0x1000>;
clocks = <&clk_3m>, <&clk_3m>, <&clk_apb>;
clock-names = "timer10", "timer11", "apb_pclk";
status = "okay";
};
uart0: uart@12040000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12040000 0x1000>;
interrupts = <0 7 4>;
clocks = <&clock GK7205V200_UART0_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
uart1: uart@12041000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12041000 0x1000>;
interrupts = <0 8 4>;
clocks = <&clock GK7205V200_UART1_CLK>;
clock-names = "apb_pclk";
#ifdef CONFIG_EDMAC
dmas = <&edmac 19 19>, <&edmac 18 18>;
dma-names = "tx","rx";
#endif
status = "disabled";
};
uart2: uart@12042000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12042000 0x1000>;
interrupts = <0 9 4>;
clocks = <&clock GK7205V200_UART2_CLK>;
clock-names = "apb_pclk";
#ifdef CONFIG_EDMAC
dmas = <&edmac 21 21>, <&edmac 20 20>;
dma-names = "tx","rx";
#endif
status = "disabled";
};
};
i2c_bus0: i2c@12060000 {
compatible = "goke,goke-i2c";
reg = <0x12060000 0x1000>;
clocks = <&clock GK7205V200_I2C0_CLK>;
status = "disabled";
};
i2c_bus1: i2c@12061000 {
compatible = "goke,goke-i2c";
reg = <0x12061000 0x1000>;
clocks = <&clock GK7205V200_I2C1_CLK>;
status = "disabled";
};
i2c_bus2: i2c@12062000 {
compatible = "goke,goke-i2c";
reg = <0x12062000 0x1000>;
clocks = <&clock GK7205V200_I2C2_CLK>;
status = "disabled";
};
spi_bus0: spi@12070000 {
compatible = "arm,pl022", "arm,primecell";
arm,primecell-periphid = <0x00041022>;
reg = <0x12070000 0x1000>;
interrupts = <0 14 4>;
clocks = <&clock GK7205V200_SPI0_CLK>;
clock-names = "apb_pclk";
#address-cells = <1>;
#size-cells = <0>;
#ifdef CONFIG_EDMAC
dmas = <&edmac 27 27>, <&edmac 26 26>;
dma-names = "tx","rx";
#endif
status = "disabled";
};
spi_bus1: spi@12071000 {
compatible = "arm,pl022", "arm,primecell";
arm,primecell-periphid = <0x00041022>;
reg = <0x12071000 0x1000>, <0x12028000 0x4>;
interrupts = <0 15 4>;
clocks = <&clock GK7205V200_SPI1_CLK>;
clock-names = "apb_pclk";
#address-cells = <1>;
#size-cells = <0>;
num-cs = <2>;
spi_cs_sb = <2>;
spi_cs_mask_bit = <0x4>;//0100
#ifdef CONFIG_EDMAC
dmas = <&edmac 29 29>, <&edmac 28 28>;
dma-names = "tx","rx";
#endif
status = "disabled";
};
mdio0: mdio@10041100 {
compatible = "goke,femac-mdio";
reg = <0x10041100 0x10>,<0x12028024 0x4>;
clocks = <&clock GK7205V200_ETH0_CLK>;
clock-names = "mdio";
resets = <&clock 0x16c 3>;
reset-names = "internal-phy";
#address-cells = <1>;
#size-cells = <0>;
};
femac: ethernet@10040000 {
compatible = "goke,femac",
"goke,femac-v2";
reg = <0x10040000 0x1000>,<0x10041300 0x200>;
interrupts = <0 33 4>;
clocks = <&clock GK7205V200_ETH0_CLK>;
resets = <&clock 0x16c 0>;
reset-names = "mac";
};
fmc: flash-memory-controller@10000000 {
compatible = "goke,fmc";
reg = <0x10000000 0x1000>, <0x14000000 0x10000>;
reg-names = "control", "memory";
clocks = <&clock GK7205V200_FMC_CLK>;
max-dma-size = <0x2000>;
#address-cells = <1>;
#size-cells = <0>;
sfc:spi-nor@0 {
compatible = "goke,fmc-spi-nor";
assigned-clocks = <&clock GK7205V200_FMC_CLK>;
assigned-clock-rates = <24000000>;
#address-cells = <1>;
#size-cells = <0>;
};
snfc:spi-nand@0 {
compatible = "goke,fmc-spi-nand";
assigned-clocks = <&clock GK7205V200_FMC_CLK>;
assigned-clock-rates = <24000000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
mmc0: sdhci@0x10010000 {
compatible = "goke,sdhci";
reg = <0x10010000 0x1000>;
interrupts = <0 30 4>;
clocks = <&clock GK7205V200_MMC0_CLK>;
clock-names = "mmc_clk";
resets = <&clock 0x1f4 27>, <&clock 0x1f4 29>;
reset-names = "crg_reset", "dll_reset";
max-frequency = <150000000>;
crg_regmap = <&clock>;
iocfg_regmap = <&iocfg_ctrl>;
bus-width = <4>;
cap-mmc-highspeed;
cap-mmc-hw-reset;
cap-sd-highspeed;
mmc-hs200-1_8v;
full-pwr-cycle;
devid = <0>;
status = "enable";
};
mmc1: sdhci@0x10020000 {
compatible = "goke,sdhci";
reg = <0x10020000 0x1000>;
interrupts = <0 31 4>;
clocks = <&clock GK7205V200_MMC1_CLK>;
clock-names = "mmc_clk";
resets = <&clock 0x22c 27>, <&clock 0x22c 29>;
reset-names = "crg_reset", "dll_reset";
max-frequency = <50000000>;
crg_regmap = <&clock>;
iocfg_regmap = <&iocfg_ctrl2>;
bus-width = <4>;
cap-sd-highspeed;
full-pwr-cycle;
devid = <2>;
status = "enable";
};
usb2_phy0: phy2-0 {
compatible = "goke,usbp2-phy";
reg = <0x100D0000 0x1000>,
<0x12010000 0x1000>,
<0x100c0000 0x1000>;
clocks = <&clock GK7205V200_USB2_PHY_APB_CLK>,
<&clock GK7205V200_USB2_PHY_PLL_CLK>,
<&clock GK7205V200_USB2_PHY_XO_CLK>;
clock-names = "clk_u2phy_apb_ref",
"clk_u2phy_pll_ref",
"clk_u2phy_xo_ref";
resets = <&clock 0x140 0>,
<&clock 0x140 1>;
reset-names = "phy_por_reset",
"phy_tpor_reset";
phy_pll_offset = <0x14>;
phy_pll_mask = <0x03>;
phy_pll_val = <0x00>;
crg_offset = <0x140>;
crg_defal_mask = <0x0c07>;
crg_defal_val = <0x0807>;
vbus_offset = <0x7c>;
vbus_val = <0x0531>;
pwren_offset = <0x80>;
pwren_val = <0x01>;
ana_cfg_0_eye_val = <0x0433cc23>;
ana_cfg_0_offset = <0x00>;
ana_cfg_2_eye_val = <0x00320f0f>;
ana_cfg_2_offset = <0x08>;
ana_cfg_4_eye_val = <0x655>;
ana_cfg_4_offset = <0x10>;
trim_otp_addr = <0x12028004>;
trim_otp_mask = <0x1f>;
trim_otp_bit_offset = <0x00>;
trim_otp_min = <0x09>;
trim_otp_max = <0x1d>;
#phy-cells = <0>;
};
usbdrd3_0: usb3-0{
compatible = "goke,dwusb2";
reg = <0x10030000 0x10000>,
<0x12010000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
crg_offset = <0x140>;
crg_ctrl_def_mask = <0x3308>;
crg_ctrl_def_val = <0x1308>;
clocks = <&clock GK7205V200_USB2_BUS_CLK>,
<&clock GK7205V200_USB2_REF_CLK>,
<&clock GK7205V200_USB2_UTMI_CLK>;
clock-names = "usb2_bus_clk",
"usb2_ref_clk",
"usb2_utmi_clk";
resets = <&clock 0x140 3>;
reset-names = "vcc_reset";
ranges;
dwc3@0x100e0000 {
compatible = "snps,dwc3";
reg = <0x10030000 0x10000>;
interrupts = <0 39 4>;
interrupt-names = "peripheral";
phys = <&usb2_phy0>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
dr_mode = "host";
eps_directions = <0x6a>;
snps,eps_new_init;
eps_map=<0x0 0x1 0x2 0x3 0x4 0x5 0x7>;
snps,usb2-lpm-disable;
};
};
gpio_chip0: gpio_chip@120b0000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b0000 0x1000>;
interrupts = <0 16 4>;
clocks = <&clock GK7205V200_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip1: gpio_chip@120b1000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b1000 0x1000>;
interrupts = <0 17 4>;
clocks = <&clock GK7205V200_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip2: gpio_chip@120b2000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b2000 0x1000>;
interrupts = <0 18 4>;
clocks = <&clock GK7205V200_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip4: gpio_chip@120b4000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b4000 0x1000>;
interrupts = <0 20 4>;
clocks = <&clock GK7205V200_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip5: gpio_chip@120b5000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b5000 0x1000>;
interrupts = <0 21 4>;
clocks = <&clock GK7205V200_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip6: gpio_chip@120b6000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b6000 0x1000>;
interrupts = <0 22 4>;
clocks = <&clock GK7205V200_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip7: gpio_chip@120b7000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b7000 0x1000>;
interrupts = <0 23 4>;
clocks = <&clock GK7205V200_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip8: gpio_chip@120b8000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b8000 0x1000>;
interrupts = <0 24 4>;
clocks = <&clock GK7205V200_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
rtc: rtc@120e0000 {
compatible = "goke,rtc";
reg = <0x120e0000 0x1000>;
interrupts = <0 0 4>;
};
cipher: cipher@0x10050000 {
compatible = "goke,cipher";
reg = <0x10050000 0x10000>;
reg-names = "cipher";
interrupts = <0 34 4>, <0 34 4>;
interrupt-names = "cipher", "hash";
};
adc: adc@120a0000 {
compatible = "goke,lsadc";
reg = <0x120a0000 0x1000>;
interrupts = <0 4 4>;
interrupt-names = "adc";
resets = <&clock 0x1bc 2>;
reset-names = "lsadc-crg";
status = "okay";
};
wdg: wdg@0x12030000 {
compatible = "goke,wdg";
reg = <0x12030000 0x1000>;
reg-names = "wdg";
interrupts = <0 2 4>;
interrupt-names = "wdg";
};
};
media {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
osal: osal {
compatible = "goke,osal";
};
sys: sys@12010000 {
compatible = "goke,sys";
};
mipi: mipi@0x11240000 {
compatible = "goke,mipi";
reg = <0x11240000 0x10000>;
reg-names = "mipi_rx";
interrupts = <0 45 4>;
interrupt-names = "mipi_rx";
};
vi: vi@11000000 {
compatible = "goke,vi";
reg = <0x11000000 0x200000>, <0x11200000 0x40000>;
reg-names = "VI_CAP0", "VI_PROC0";
interrupts = <0 43 4>, <0 44 4>;
interrupt-names = "VI_CAP0", "VI_PROC0";
};
isp: isp@11220000 {
compatible = "goke,isp";
reg = <0x11220000 0x20000>;
reg-names = "ISP";
interrupts = <0 43 4>;
interrupt-names = "ISP";
};
vpss: vpss@11400000 {
compatible = "goke,vpss";
reg = <0x11400000 0x10000>;
reg-names = "vpss0";
interrupts = <0 46 4>;
interrupt-names = "vpss0";
};
vo: vo@11280000 {
compatible = "goke,vo";
reg = <0x11280000 0x40000>;
reg-names = "vo";
interrupts = <0 40 4>;
interrupt-names = "vo";
};
gfbg: gfbg@11280000 {
compatible = "goke,gfbg";
reg = <0x11280000 0x40000>;
reg-names = "gfbg";
interrupts = <0 41 4>;
interrupt-names = "gfbg";
};
vgs: vgs@11300000 {
compatible = "goke,vgs";
reg = <0x11300000 0x10000>;
reg-names = "vgs0";
interrupts = <0 49 4>;
interrupt-names = "vgs0";
};
gzip: gzip@11310000 {
compatible = "goke,gzip";
reg = <0x11310000 0x10000>;
reg-names = "gzip";
interrupts = <0 50 4>;
interrupt-names = "gzip";
};
vedu: vedu@11410000 {
compatible = "goke,vedu";
reg = <0x11410000 0x10000>, <0x11420000 0x10000>;
reg-names = "vedu0", "jpge";
interrupts = <0 47 4>, <0 48 4>;
interrupt-names = "vedu0","jpge";
};
venc: venc {
compatible = "goke,venc";
};
aiao: aiao@100e0000 {
compatible = "goke,aiao";
reg = <0x100e0000 0x10000>,<0x100f0000 0x10000>;
reg-names = "aiao","acodec";
interrupts = <0 42 4>;
interrupt-names = "AIO";
};
ive: ive@11320000 {
compatible = "goke,ive";
reg = <0x11320000 0x10000>;
reg-names = "ive";
interrupts = <0 51 4>;
interrupt-names = "ive";
};
};
};

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br-ext-chip-goke/board/gk7205v200/kernel/overlay/arch/arm/boot/dts/gk7205v300-demb.dts
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@ -1,159 +0,0 @@
/*
* Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
*/
/dts-v1/;
#include "gk7205v300.dtsi"
/ {
model = "Goke GK7205V300 DEMO Board";
compatible = "goke,gk7205v300";
memory {
device_type = "memory";
reg = <0x40000000 0x20000000>;
};
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart2 {
status = "disabled";
};
&i2c_bus0 {
status = "okay";
clock-frequency = <100000>;
};
&i2c_bus1 {
status = "okay";
clock-frequency = <100000>;
};
&i2c_bus2 {
status = "okay";
clock-frequency = <100000>;
};
&spi_bus0{
status = "okay";
num-cs = <1>;
spidev@0 {
compatible = "rohm,dh2228fv";
reg = <0>;
pl022,interface = <0>;
pl022,com-mode = <0>;
spi-max-frequency = <50000000>;
};
};
&spi_bus1{
status = "okay";
num-cs = <2>;
spidev@0 {
compatible = "rohm,dh2228fv";
reg = <0>;
pl022,interface = <0>;
pl022,com-mode = <0>;
spi-max-frequency = <50000000>;
};
spidev@1 {
compatible = "rohm,dh2228fv";
reg = <1>;
pl022,interface = <0>;
pl022,com-mode = <0>;
spi-max-frequency = <50000000>;
};
};
&dual_timer0 {
status = "okay";
};
&mdio0 {
goke,phy-reset-delays-us = <10000 20000 150000>;
phy0: ethernet-phy@1 {
reg = <1>;
};
};
&femac {
mac-address = [00 00 00 00 00 00];
phy-mode = "mii";
phy-handle = <&phy0>;
status = "okay";
};
&sfc {
sfc {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <160000000>;
};
};
&snfc {
nand {
compatible = "jedec,spi-nand";
reg = <0>;
spi-max-frequency = <160000000>;
};
};
&mmc0 {
status = "okay";
};
&mmc1 {
status = "okay";
};
&gpio_chip0 {
status = "okay";
};
&gpio_chip1 {
status = "okay";
};
&gpio_chip2 {
status = "okay";
};
&gpio_chip3 {
status = "okay";
};
&gpio_chip4 {
status = "okay";
};
&gpio_chip5 {
status = "okay";
};
&gpio_chip6 {
status = "okay";
};
&gpio_chip7 {
status = "okay";
};
&gpio_chip8 {
status = "okay";
};
&gpio_chip9 {
status = "okay";
};

645
br-ext-chip-goke/board/gk7205v200/kernel/overlay/arch/arm/boot/dts/gk7205v300.dtsi
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/*
* Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
*/
#include "skeleton.dtsi"
#include <dt-bindings/clock/gk7205v300-clock.h>
/ {
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
i2c0 = &i2c_bus0;
i2c1 = &i2c_bus1;
i2c2 = &i2c_bus2;
spi0 = &spi_bus0;
spi1 = &spi_bus1;
gpio0 = &gpio_chip0;
gpio1 = &gpio_chip1;
gpio2 = &gpio_chip2;
gpio3 = &gpio_chip3;
gpio4 = &gpio_chip4;
gpio5 = &gpio_chip5;
gpio6 = &gpio_chip6;
gpio7 = &gpio_chip7;
gpio8 = &gpio_chip8;
gpio9 = &gpio_chip9;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "goke,gk7205v300";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
clock-frequency = <GK7205V300_FIXED_1000M>;
reg = <0>;
};
};
pmu {
compatible = "arm,armv7-pmu";
interrupts = <0 58 4>;
};
clock: clock@12010000 {
compatible = "goke,gk7205v300-clock", "syscon";
#address-cells = <1>;
#size-cells = <1>;
#clock-cells = <1>;
#reset-cells = <2>;
reg = <0x12010000 0x1000>;
};
gic: interrupt-controller@10300000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
/* gic dist base, gic cpu base , no virtual support */
reg = <0x10301000 0x1000>, <0x10302000 0x100>;
};
syscounter {
compatible = "arm,armv7-timer";
interrupt-parent = <&gic>;
interrupts = <1 13 0xf08>,
<1 14 0xf08>;
clock-frequency = <50000000>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
clk_3m: clk_3m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <3000000>;
};
clk_apb: clk_apb {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
};
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <0 58 4>;
};
sysctrl: system-controller@12020000 {
compatible = "goke,sysctrl";
reg = <0x12020000 0x1000>;
reboot-offset = <0x4>;
#clock-cells = <1>;
};
iocfg_ctrl: iocfg-controller@100c0000 {
compatible = "syscon";
reg = <0x100C0000 0x10000>;
};
#ifdef CONFIG_EDMAC
edmac: edma-controller@100B0000 {
compatible = "goke,edmac";
reg = <0x100B0000 0x1000>;
interrupts = <0 38 4>;
clocks = <&clock GK7205V300_EDMAC_CLK>, <&clock GK7205V300_EDMAC_AXICLK>;
clock-names = "apb_pclk", "axi_aclk";
clock-cells = <2>;
resets = <&clock 0x194 0>;
reset-names = "dma-reset";
dma-requests = <32>;
dma-channels = <4>;
devid = <0>;
#dma-cells = <2>;
status = "okay";
};
#endif
amba {
#address-cells = <1>;
#size-cells = <1>;
compatible = "arm,amba-bus";
ranges;
dual_timer0: dual_timer@12000000 {
compatible = "arm,sp804", "arm,primecell";
/* timer0 & timer1 */
interrupts = <0 5 4>;
reg = <0x12000000 0x1000>;
clocks = <&clk_3m>, <&clk_3m>, <&clk_apb>;
clock-names = "timer00", "timer01", "apb_pclk";
status = "disabled";
};
dual_timer1: dual_timer@12001000 {
compatible = "arm,sp805", "arm,primecell5";
/* timer2 & timer3 */
interrupts = <0 6 4>;
reg = <0x12001000 0x1000>;
clocks = <&clk_3m>, <&clk_3m>, <&clk_apb>;
clock-names = "timer10", "timer11", "apb_pclk";
status = "okay";
};
uart0: uart@12040000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12040000 0x1000>;
interrupts = <0 7 4>;
clocks = <&clock GK7205V300_UART0_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
uart1: uart@12041000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12041000 0x1000>;
interrupts = <0 8 4>;
clocks = <&clock GK7205V300_UART1_CLK>;
clock-names = "apb_pclk";
#ifdef CONFIG_EDMAC
dmas = <&edmac 19 19>, <&edmac 18 18>;
dma-names = "tx","rx";
#endif
status = "disabled";
};
uart2: uart@12042000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12042000 0x1000>;
interrupts = <0 9 4>;
clocks = <&clock GK7205V300_UART2_CLK>;
clock-names = "apb_pclk";
#ifdef CONFIG_EDMAC
dmas = <&edmac 21 21>, <&edmac 20 20>;
dma-names = "tx","rx";
#endif
status = "disabled";
};
};
i2c_bus0: i2c@12060000 {
compatible = "goke,goke-i2c";
reg = <0x12060000 0x1000>;
clocks = <&clock GK7205V300_I2C0_CLK>;
status = "disabled";
};
i2c_bus1: i2c@12061000 {
compatible = "goke,goke-i2c";
reg = <0x12061000 0x1000>;
clocks = <&clock GK7205V300_I2C1_CLK>;
status = "disabled";
};
i2c_bus2: i2c@12062000 {
compatible = "goke,goke-i2c";
reg = <0x12062000 0x1000>;
clocks = <&clock GK7205V300_I2C2_CLK>;
status = "disabled";
};
spi_bus0: spi@12070000 {
compatible = "arm,pl022", "arm,primecell";
arm,primecell-periphid = <0x00041022>;
reg = <0x12070000 0x1000>;
interrupts = <0 14 4>;
clocks = <&clock GK7205V300_SPI0_CLK>;
clock-names = "apb_pclk";
#address-cells = <1>;
#size-cells = <0>;
#ifdef CONFIG_EDMAC
dmas = <&edmac 27 27>, <&edmac 26 26>;
dma-names = "tx","rx";
#endif
status = "disabled";
};
spi_bus1: spi@12071000 {
compatible = "arm,pl022", "arm,primecell";
arm,primecell-periphid = <0x00041022>;
reg = <0x12071000 0x1000>, <0x12028000 0x4>;
interrupts = <0 15 4>;
clocks = <&clock GK7205V300_SPI1_CLK>;
clock-names = "apb_pclk";
#address-cells = <1>;
#size-cells = <0>;
num-cs = <2>;
spi_cs_sb = <2>;
spi_cs_mask_bit = <0x4>;//0100
#ifdef CONFIG_EDMAC
dmas = <&edmac 29 29>, <&edmac 28 28>;
dma-names = "tx","rx";
#endif
status = "disabled";
};
mdio0: mdio@10041100 {
compatible = "goke,femac-mdio";
reg = <0x10041100 0x10>,<0x12028024 0x4>;
clocks = <&clock GK7205V300_ETH0_CLK>;
clock-names = "mdio";
resets = <&clock 0x16c 3>;
reset-names = "internal-phy";
#address-cells = <1>;
#size-cells = <0>;
};
femac: ethernet@10040000 {
compatible = "goke,femac",
"goke,femac-v2";
reg = <0x10040000 0x1000>,<0x10041300 0x200>;
interrupts = <0 33 4>;
clocks = <&clock GK7205V300_ETH0_CLK>;
resets = <&clock 0x16c 0>;
reset-names = "mac";
};
fmc: flash-memory-controller@10000000 {
compatible = "goke,fmc";
reg = <0x10000000 0x1000>, <0x14000000 0x10000>;
reg-names = "control", "memory";
clocks = <&clock GK7205V300_FMC_CLK>;
max-dma-size = <0x2000>;
#address-cells = <1>;
#size-cells = <0>;
sfc:spi-nor@0 {
compatible = "goke,fmc-spi-nor";
assigned-clocks = <&clock GK7205V300_FMC_CLK>;
assigned-clock-rates = <24000000>;
#address-cells = <1>;
#size-cells = <0>;
};
snfc:spi-nand@0 {
compatible = "goke,fmc-spi-nand";
assigned-clocks = <&clock GK7205V300_FMC_CLK>;
assigned-clock-rates = <24000000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
mmc0: sdhci@0x10010000 {
compatible = "goke,sdhci";
reg = <0x10010000 0x1000>;
interrupts = <0 30 4>;
clocks = <&clock GK7205V300_MMC0_CLK>;
clock-names = "mmc_clk";
resets = <&clock 0x1f4 27>, <&clock 0x1f4 29>;
reset-names = "crg_reset", "dll_reset";
max-frequency = <90000000>;
crg_regmap = <&clock>;
iocfg_regmap = <&iocfg_ctrl>;
bus-width = <8>;
cap-mmc-highspeed;
cap-mmc-hw-reset;
cap-sd-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
full-pwr-cycle;
devid = <0>;
status = "enable";
};
mmc1: sdhci@0x10020000 {
compatible = "goke,sdhci";
reg = <0x10020000 0x1000>;
interrupts = <0 31 4>;
clocks = <&clock GK7205V300_MMC1_CLK>;
clock-names = "mmc_clk";
resets = <&clock 0x22c 27>, <&clock 0x22c 29>;
reset-names = "crg_reset", "dll_reset";
max-frequency = <50000000>;
crg_regmap = <&clock>;
iocfg_regmap = <&iocfg_ctrl>;
bus-width = <4>;
cap-sd-highspeed;
full-pwr-cycle;
devid = <2>;
status = "enable";
};
usb2_phy0: phy2-0 {
compatible = "goke,usbp2-phy";
reg = <0x100D0000 0x1000>,
<0x12010000 0x1000>,
<0x100c0000 0x1000>;
clocks = <&clock GK7205V300_USB2_PHY_APB_CLK>,
<&clock GK7205V300_USB2_PHY_PLL_CLK>,
<&clock GK7205V300_USB2_PHY_XO_CLK>;
clock-names = "clk_u2phy_apb_ref",
"clk_u2phy_pll_ref",
"clk_u2phy_xo_ref";
resets = <&clock 0x140 0>,
<&clock 0x140 1>;
reset-names = "phy_por_reset",
"phy_tpor_reset";
phy_pll_offset = <0x14>;
phy_pll_mask = <0x03>;
phy_pll_val = <0x00>;
crg_offset = <0x140>;
crg_defal_mask = <0x0c07>;
crg_defal_val = <0x0807>;
vbus_offset = <0x7c>;
vbus_val = <0x0431>;
pwren_offset = <0x80>;
pwren_val = <0x1>;
ana_cfg_0_eye_val = <0x0433cc23>;
ana_cfg_0_offset = <0x00>;
ana_cfg_2_eye_val = <0x00320f0f>;
ana_cfg_2_offset = <0x08>;
ana_cfg_4_eye_val = <0x655>;
ana_cfg_4_offset = <0x10>;
trim_otp_addr = <0x12028004>;
trim_otp_mask = <0x1f>;
trim_otp_bit_offset = <0x00>;
trim_otp_min = <0x09>;
trim_otp_max = <0x1d>;
#phy-cells = <0>;
};
usbdrd3_0: usb3-0{
compatible = "goke,dwusb2";
reg = <0x10030000 0x10000>,
<0x12010000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
crg_offset = <0x140>;
crg_ctrl_def_mask = <0x3308>;
crg_ctrl_def_val = <0x1308>;
clocks = <&clock GK7205V300_USB2_BUS_CLK>,
<&clock GK7205V300_USB2_REF_CLK>,
<&clock GK7205V300_USB2_UTMI_CLK>;
clock-names = "usb2_bus_clk",
"usb2_ref_clk",
"usb2_utmi_clk";
resets = <&clock 0x140 3>;
reset-names = "vcc_reset";
ranges;
dwc3@0x100e0000 {
compatible = "snps,dwc3";
reg = <0x10030000 0x10000>;
interrupts = <0 39 4>;
interrupt-names = "peripheral";
phys = <&usb2_phy0>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
dr_mode = "host";
eps_directions = <0x6a>;
snps,eps_new_init;
eps_map=<0x0 0x1 0x2 0x3 0x4 0x5 0x7>;
snps,usb2-lpm-disable;
};
};
gpio_chip0: gpio_chip@120b0000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b0000 0x1000>;
interrupts = <0 16 4>;
clocks = <&clock GK7205V300_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip1: gpio_chip@120b1000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b1000 0x1000>;
interrupts = <0 17 4>;
clocks = <&clock GK7205V300_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip2: gpio_chip@120b2000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b2000 0x1000>;
interrupts = <0 18 4>;
clocks = <&clock GK7205V300_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip3: gpio_chip@120b3000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b3000 0x1000>;
interrupts = <0 19 4>;
clocks = <&clock GK7205V300_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip4: gpio_chip@120b4000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b4000 0x1000>;
interrupts = <0 20 4>;
clocks = <&clock GK7205V300_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip5: gpio_chip@120b5000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b5000 0x1000>;
interrupts = <0 21 4>;
clocks = <&clock GK7205V300_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip6: gpio_chip@120b6000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b6000 0x1000>;
interrupts = <0 22 4>;
clocks = <&clock GK7205V300_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip7: gpio_chip@120b7000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b7000 0x1000>;
interrupts = <0 23 4>;
clocks = <&clock GK7205V300_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip8: gpio_chip@120b8000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b8000 0x1000>;
interrupts = <0 24 4>;
clocks = <&clock GK7205V300_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip9: gpio_chip@120b9000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b9000 0x1000>;
interrupts = <0 25 4>;
clocks = <&clock GK7205V300_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
rtc: rtc@120e0000 {
compatible = "goke,rtc";
reg = <0x120e0000 0x1000>;
interrupts = <0 0 4>;
};
cipher: cipher@0x10050000 {
compatible = "goke,cipher";
reg = <0x10050000 0x10000>;
reg-names = "cipher";
interrupts = <0 34 4>, <0 34 4>;
interrupt-names = "cipher", "hash";
};
adc: adc@120a0000 {
compatible = "goke,lsadc";
reg = <0x120a0000 0x1000>;
interrupts = <0 4 4>;
interrupt-names = "adc";
resets = <&clock 0x1bc 2>;
reset-names = "lsadc-crg";
status = "okay";
};
wdg: wdg@0x12030000 {
compatible = "goke,wdg";
reg = <0x12030000 0x1000>;
reg-names = "wdg";
interrupts = <0 2 4>;
interrupt-names = "wdg";
};
};
media {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
osal: osal {
compatible = "goke,osal";
};
sys: sys@12010000 {
compatible = "goke,sys";
};
mipi: mipi@0x11240000 {
compatible = "goke,mipi";
reg = <0x11240000 0x10000>;
reg-names = "mipi_rx";
interrupts = <0 45 4>;
interrupt-names = "mipi_rx";
};
vi: vi@11000000 {
compatible = "goke,vi";
reg = <0x11000000 0x200000>, <0x11200000 0x40000>;
reg-names = "VI_CAP0", "VI_PROC0";
interrupts = <0 43 4>, <0 44 4>;
interrupt-names = "VI_CAP0", "VI_PROC0";
};
isp: isp@11220000 {
compatible = "goke,isp";
reg = <0x11220000 0x20000>;
reg-names = "ISP";
interrupts = <0 43 4>;
interrupt-names = "ISP";
};
vpss: vpss@11400000 {
compatible = "goke,vpss";
reg = <0x11400000 0x10000>;
reg-names = "vpss0";
interrupts = <0 46 4>;
interrupt-names = "vpss0";
};
vo: vo@11280000 {
compatible = "goke,vo";
reg = <0x11280000 0x40000>;
reg-names = "vo";
interrupts = <0 40 4>;
interrupt-names = "vo";
};
gfbg: gfbg@11280000 {
compatible = "goke,gfbg";
reg = <0x11280000 0x40000>;
reg-names = "gfbg";
interrupts = <0 41 4>;
interrupt-names = "gfbg";
};
vgs: vgs@11300000 {
compatible = "goke,vgs";
reg = <0x11300000 0x10000>;
reg-names = "vgs0";
interrupts = <0 49 4>;
interrupt-names = "vgs0";
};
gzip: gzip@11310000 {
compatible = "goke,gzip";
reg = <0x11310000 0x10000>;
reg-names = "gzip";
interrupts = <0 50 4>;
interrupt-names = "gzip";
};
vedu: vedu@11410000 {
compatible = "goke,vedu";
reg = <0x11410000 0x10000>, <0x11420000 0x10000>;
reg-names = "vedu0", "jpge";
interrupts = <0 47 4>, <0 48 4>;
interrupt-names = "vedu0","jpge";
};
venc: venc {
compatible = "goke,venc";
};
aiao: aiao@100e0000 {
compatible = "goke,aiao";
reg = <0x100e0000 0x10000>,<0x100f0000 0x10000>;
reg-names = "aiao","acodec";
interrupts = <0 42 4>;
interrupt-names = "AIO";
};
ive: ive@11320000 {
compatible = "goke,ive";
reg = <0x11320000 0x10000>;
reg-names = "ive";
interrupts = <0 51 4>;
interrupt-names = "ive";
};
};
};

159
br-ext-chip-goke/board/gk7205v200/kernel/overlay/arch/arm/boot/dts/gk7605v100-demb.dts
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@ -1,159 +0,0 @@
/*
* Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
*/
/dts-v1/;
#include "gk7605v100.dtsi"
/ {
model = "Goke GK7605V100 DEMO Board";
compatible = "goke,gk7605v100";
memory {
device_type = "memory";
reg = <0x40000000 0x20000000>;
};
};
&uart0 {
status = "okay";
};
&uart1 {
status = "disabled";
};
&uart2 {
status = "disabled";
};
&i2c_bus0 {
status = "okay";
clock-frequency = <100000>;
};
&i2c_bus1 {
status = "okay";
clock-frequency = <100000>;
};
&i2c_bus2 {
status = "okay";
clock-frequency = <100000>;
};
&spi_bus0{
status = "okay";
num-cs = <1>;
spidev@0 {
compatible = "rohm,dh2228fv";
reg = <0>;
pl022,interface = <0>;
pl022,com-mode = <0>;
spi-max-frequency = <50000000>;
};
};
&spi_bus1{
status = "okay";
num-cs = <2>;
spidev@0 {
compatible = "rohm,dh2228fv";
reg = <0>;
pl022,interface = <0>;
pl022,com-mode = <0>;
spi-max-frequency = <50000000>;
};
spidev@1 {
compatible = "rohm,dh2228fv";
reg = <1>;
pl022,interface = <0>;
pl022,com-mode = <0>;
spi-max-frequency = <50000000>;
};
};
&dual_timer0 {
status = "okay";
};
&mdio0 {
goke,phy-reset-delays-us = <10000 20000 150000>;
phy0: ethernet-phy@1 {
reg = <1>;
};
};
&femac {
mac-address = [00 00 00 00 00 00];
phy-mode = "mii";
phy-handle = <&phy0>;
status = "okay";
};
&sfc {
sfc {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <160000000>;
};
};
&snfc {
nand {
compatible = "jedec,spi-nand";
reg = <0>;
spi-max-frequency = <160000000>;
};
};
&mmc0 {
status = "okay";
};
&mmc1 {
status = "okay";
};
&gpio_chip0 {
status = "okay";
};
&gpio_chip1 {
status = "okay";
};
&gpio_chip2 {
status = "okay";
};
&gpio_chip3 {
status = "okay";
};
&gpio_chip4 {
status = "okay";
};
&gpio_chip5 {
status = "okay";
};
&gpio_chip6 {
status = "okay";
};
&gpio_chip7 {
status = "okay";
};
&gpio_chip8 {
status = "okay";
};
&gpio_chip9 {
status = "okay";
};

645
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@ -1,645 +0,0 @@
/*
* Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
*/
#include "skeleton.dtsi"
#include <dt-bindings/clock/gk7605v100-clock.h>
/ {
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
i2c0 = &i2c_bus0;
i2c1 = &i2c_bus1;
i2c2 = &i2c_bus2;
spi0 = &spi_bus0;
spi1 = &spi_bus1;
gpio0 = &gpio_chip0;
gpio1 = &gpio_chip1;
gpio2 = &gpio_chip2;
gpio3 = &gpio_chip3;
gpio4 = &gpio_chip4;
gpio5 = &gpio_chip5;
gpio6 = &gpio_chip6;
gpio7 = &gpio_chip7;
gpio8 = &gpio_chip8;
gpio9 = &gpio_chip9;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "goke,gk7605v100";
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
clock-frequency = <GK7605V100_FIXED_1000M>;
reg = <0>;
};
};
pmu {
compatible = "arm,armv7-pmu";
interrupts = <0 58 4>;
};
clock: clock@12010000 {
compatible = "goke,gk7605v100-clock", "syscon";
#address-cells = <1>;
#size-cells = <1>;
#clock-cells = <1>;
#reset-cells = <2>;
reg = <0x12010000 0x1000>;
};
gic: interrupt-controller@10300000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
/* gic dist base, gic cpu base , no virtual support */
reg = <0x10301000 0x1000>, <0x10302000 0x100>;
};
syscounter {
compatible = "arm,armv7-timer";
interrupt-parent = <&gic>;
interrupts = <1 13 0xf08>,
<1 14 0xf08>;
clock-frequency = <50000000>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
clk_3m: clk_3m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <3000000>;
};
clk_apb: clk_apb {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
};
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <0 58 4>;
};
sysctrl: system-controller@12020000 {
compatible = "goke,sysctrl";
reg = <0x12020000 0x1000>;
reboot-offset = <0x4>;
#clock-cells = <1>;
};
iocfg_ctrl: iocfg-controller@100c0000 {
compatible = "syscon";
reg = <0x100C0000 0x10000>;
};
#ifdef CONFIG_EDMAC
edmac: edma-controller@100B0000 {
compatible = "goke,edmac";
reg = <0x100B0000 0x1000>;
interrupts = <0 38 4>;
clocks = <&clock GK7605V100_EDMAC_CLK>, <&clock GK7605V100_EDMAC_AXICLK>;
clock-names = "apb_pclk", "axi_aclk";
clock-cells = <2>;
resets = <&clock 0x194 0>;
reset-names = "dma-reset";
dma-requests = <32>;
dma-channels = <4>;
devid = <0>;
#dma-cells = <2>;
status = "okay";
};
#endif
amba {
#address-cells = <1>;
#size-cells = <1>;
compatible = "arm,amba-bus";
ranges;
dual_timer0: dual_timer@12000000 {
compatible = "arm,sp804", "arm,primecell";
/* timer0 & timer1 */
interrupts = <0 5 4>;
reg = <0x12000000 0x1000>;
clocks = <&clk_3m>, <&clk_3m>, <&clk_apb>;
clock-names = "timer00", "timer01", "apb_pclk";
status = "disabled";
};
dual_timer1: dual_timer@12001000 {
compatible = "arm,sp804", "arm,primecell";
/* timer2 & timer3 */
interrupts = <0 6 4>;
reg = <0x12001000 0x1000>;
clocks = <&clk_3m>, <&clk_3m>, <&clk_apb>;
clock-names = "timer10", "timer11", "apb_pclk";
status = "disabled";
};
uart0: uart@12040000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12040000 0x1000>;
interrupts = <0 7 4>;
clocks = <&clock GK7605V100_UART0_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
uart1: uart@12041000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12041000 0x1000>;
interrupts = <0 8 4>;
clocks = <&clock GK7605V100_UART1_CLK>;
clock-names = "apb_pclk";
#ifdef CONFIG_EDMAC
dmas = <&edmac 19 19>, <&edmac 18 18>;
dma-names = "tx","rx";
#endif
status = "disabled";
};
uart2: uart@12042000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12042000 0x1000>;
interrupts = <0 9 4>;
clocks = <&clock GK7605V100_UART2_CLK>;
clock-names = "apb_pclk";
#ifdef CONFIG_EDMAC
dmas = <&edmac 21 21>, <&edmac 20 20>;
dma-names = "tx","rx";
#endif
status = "disabled";
};
};
i2c_bus0: i2c@12060000 {
compatible = "goke,goke-i2c";
reg = <0x12060000 0x1000>;
clocks = <&clock GK7605V100_I2C0_CLK>;
status = "disabled";
};
i2c_bus1: i2c@12061000 {
compatible = "goke,goke-i2c";
reg = <0x12061000 0x1000>;
clocks = <&clock GK7605V100_I2C1_CLK>;
status = "disabled";
};
i2c_bus2: i2c@12062000 {
compatible = "goke,goke-i2c";
reg = <0x12062000 0x1000>;
clocks = <&clock GK7605V100_I2C2_CLK>;
status = "disabled";
};
spi_bus0: spi@12070000 {
compatible = "arm,pl022", "arm,primecell";
arm,primecell-periphid = <0x00041022>;
reg = <0x12070000 0x1000>;
interrupts = <0 14 4>;
clocks = <&clock GK7605V100_SPI0_CLK>;
clock-names = "apb_pclk";
#address-cells = <1>;
#size-cells = <0>;
#ifdef CONFIG_EDMAC
dmas = <&edmac 27 27>, <&edmac 26 26>;
dma-names = "tx","rx";
#endif
status = "disabled";
};
spi_bus1: spi@12071000 {
compatible = "arm,pl022", "arm,primecell";
arm,primecell-periphid = <0x00041022>;
reg = <0x12071000 0x1000>, <0x12028000 0x4>;
interrupts = <0 15 4>;
clocks = <&clock GK7605V100_SPI1_CLK>;
clock-names = "apb_pclk";
#address-cells = <1>;
#size-cells = <0>;
num-cs = <2>;
spi_cs_sb = <2>;
spi_cs_mask_bit = <0x4>;//0100
#ifdef CONFIG_EDMAC
dmas = <&edmac 29 29>, <&edmac 28 28>;
dma-names = "tx","rx";
#endif
status = "disabled";
};
mdio0: mdio@10041100 {
compatible = "goke,femac-mdio";
reg = <0x10041100 0x10>,<0x12028024 0x4>;
clocks = <&clock GK7605V100_ETH0_CLK>;
clock-names = "mdio";
resets = <&clock 0x16c 3>;
reset-names = "internal-phy";
#address-cells = <1>;
#size-cells = <0>;
};
femac: ethernet@10040000 {
compatible = "goke,femac",
"goke,femac-v2";
reg = <0x10040000 0x1000>,<0x10041300 0x200>;
interrupts = <0 33 4>;
clocks = <&clock GK7605V100_ETH0_CLK>;
resets = <&clock 0x16c 0>;
reset-names = "mac";
};
fmc: flash-memory-controller@10000000 {
compatible = "goke,fmc";
reg = <0x10000000 0x1000>, <0x14000000 0x10000>;
reg-names = "control", "memory";
clocks = <&clock GK7605V100_FMC_CLK>;
max-dma-size = <0x2000>;
#address-cells = <1>;
#size-cells = <0>;
sfc:spi-nor@0 {
compatible = "goke,fmc-spi-nor";
assigned-clocks = <&clock GK7605V100_FMC_CLK>;
assigned-clock-rates = <24000000>;
#address-cells = <1>;
#size-cells = <0>;
};
snfc:spi-nand@0 {
compatible = "goke,fmc-spi-nand";
assigned-clocks = <&clock GK7605V100_FMC_CLK>;
assigned-clock-rates = <24000000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
mmc0: sdhci@0x10010000 {
compatible = "goke,sdhci";
reg = <0x10010000 0x1000>;
interrupts = <0 30 4>;
clocks = <&clock GK7605V100_MMC0_CLK>;
clock-names = "mmc_clk";
resets = <&clock 0x1f4 27>, <&clock 0x1f4 29>;
reset-names = "crg_reset", "dll_reset";
max-frequency = <90000000>;
crg_regmap = <&clock>;
iocfg_regmap = <&iocfg_ctrl>;
bus-width = <8>;
cap-mmc-highspeed;
cap-mmc-hw-reset;
cap-sd-highspeed;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
full-pwr-cycle;
devid = <0>;
status = "enable";
};
mmc1: sdhci@0x10020000 {
compatible = "goke,sdhci";
reg = <0x10020000 0x1000>;
interrupts = <0 31 4>;
clocks = <&clock GK7605V100_MMC1_CLK>;
clock-names = "mmc_clk";
resets = <&clock 0x22c 27>, <&clock 0x22c 29>;
reset-names = "crg_reset", "dll_reset";
max-frequency = <50000000>;
crg_regmap = <&clock>;
iocfg_regmap = <&iocfg_ctrl>;
bus-width = <4>;
cap-sd-highspeed;
full-pwr-cycle;
devid = <2>;
status = "enable";
};
usb2_phy0: phy2-0 {
compatible = "goke,usbp2-phy";
reg = <0x100D0000 0x1000>,
<0x12010000 0x1000>,
<0x100c0000 0x1000>;
clocks = <&clock GK7605V100_USB2_PHY_APB_CLK>,
<&clock GK7605V100_USB2_PHY_PLL_CLK>,
<&clock GK7605V100_USB2_PHY_XO_CLK>;
clock-names = "clk_u2phy_apb_ref",
"clk_u2phy_pll_ref",
"clk_u2phy_xo_ref";
resets = <&clock 0x140 0>,
<&clock 0x140 1>;
reset-names = "phy_por_reset",
"phy_tpor_reset";
phy_pll_offset = <0x14>;
phy_pll_mask = <0x03>;
phy_pll_val = <0x00>;
crg_offset = <0x140>;
crg_defal_mask = <0x0c07>;
crg_defal_val = <0x0807>;
vbus_offset = <0x7c>;
vbus_val = <0x0431>;
pwren_offset = <0x80>;
pwren_val = <0x1>;
ana_cfg_0_eye_val = <0x0433cc23>;
ana_cfg_0_offset = <0x00>;
ana_cfg_2_eye_val = <0x00320f0f>;
ana_cfg_2_offset = <0x08>;
ana_cfg_4_eye_val = <0x655>;
ana_cfg_4_offset = <0x10>;
trim_otp_addr = <0x12028004>;
trim_otp_mask = <0x1f>;
trim_otp_bit_offset = <0x00>;
trim_otp_min = <0x09>;
trim_otp_max = <0x1d>;
#phy-cells = <0>;
};
usbdrd3_0: usb3-0{
compatible = "goke,dwusb2";
reg = <0x10030000 0x10000>,
<0x12010000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
crg_offset = <0x140>;
crg_ctrl_def_mask = <0x3308>;
crg_ctrl_def_val = <0x1308>;
clocks = <&clock GK7605V100_USB2_BUS_CLK>,
<&clock GK7605V100_USB2_REF_CLK>,
<&clock GK7605V100_USB2_UTMI_CLK>;
clock-names = "usb2_bus_clk",
"usb2_ref_clk",
"usb2_utmi_clk";
resets = <&clock 0x140 3>;
reset-names = "vcc_reset";
ranges;
dwc3@0x100e0000 {
compatible = "snps,dwc3";
reg = <0x10030000 0x10000>;
interrupts = <0 39 4>;
interrupt-names = "peripheral";
phys = <&usb2_phy0>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
dr_mode = "host";
eps_directions = <0x6a>;
snps,eps_new_init;
eps_map=<0x0 0x1 0x2 0x3 0x4 0x5 0x7>;
snps,usb2-lpm-disable;
};
};
gpio_chip0: gpio_chip@120b0000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b0000 0x1000>;
interrupts = <0 16 4>;
clocks = <&clock GK7605V100_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip1: gpio_chip@120b1000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b1000 0x1000>;
interrupts = <0 17 4>;
clocks = <&clock GK7605V100_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip2: gpio_chip@120b2000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b2000 0x1000>;
interrupts = <0 18 4>;
clocks = <&clock GK7605V100_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip3: gpio_chip@120b3000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b3000 0x1000>;
interrupts = <0 19 4>;
clocks = <&clock GK7605V100_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip4: gpio_chip@120b4000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b4000 0x1000>;
interrupts = <0 20 4>;
clocks = <&clock GK7605V100_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip5: gpio_chip@120b5000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b5000 0x1000>;
interrupts = <0 21 4>;
clocks = <&clock GK7605V100_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip6: gpio_chip@120b6000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b6000 0x1000>;
interrupts = <0 22 4>;
clocks = <&clock GK7605V100_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip7: gpio_chip@120b7000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b7000 0x1000>;
interrupts = <0 23 4>;
clocks = <&clock GK7605V100_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip8: gpio_chip@120b8000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b8000 0x1000>;
interrupts = <0 24 4>;
clocks = <&clock GK7605V100_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
gpio_chip9: gpio_chip@120b9000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x120b9000 0x1000>;
interrupts = <0 25 4>;
clocks = <&clock GK7605V100_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
status = "disabled";
};
rtc: rtc@120e0000 {
compatible = "goke,rtc";
reg = <0x120e0000 0x1000>;
interrupts = <0 0 4>;
};
cipher: cipher@0x10050000 {
compatible = "goke,cipher";
reg = <0x10050000 0x10000>;
reg-names = "cipher";
interrupts = <0 34 4>, <0 34 4>;
interrupt-names = "cipher", "hash";
};
adc: adc@120a0000 {
compatible = "goke,lsadc";
reg = <0x120a0000 0x1000>;
interrupts = <0 4 4>;
interrupt-names = "adc";
resets = <&clock 0x1bc 2>;
reset-names = "lsadc-crg";
status = "okay";
};
wdg: wdg@0x12030000 {
compatible = "goke,wdg";
reg = <0x12030000 0x1000>;
reg-names = "wdg";
interrupts = <0 2 4>;
interrupt-names = "wdg";
};
};
media {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
osal: osal {
compatible = "goke,osal";
};
sys: sys@12010000 {
compatible = "goke,sys";
};
mipi: mipi@0x11240000 {
compatible = "goke,mipi";
reg = <0x11240000 0x10000>;
reg-names = "mipi_rx";
interrupts = <0 45 4>;
interrupt-names = "mipi_rx";
};
vi: vi@11000000 {
compatible = "goke,vi";
reg = <0x11000000 0x200000>, <0x11200000 0x40000>;
reg-names = "VI_CAP0", "VI_PROC0";
interrupts = <0 43 4>, <0 44 4>;
interrupt-names = "VI_CAP0", "VI_PROC0";
};
isp: isp@11220000 {
compatible = "goke,isp";
reg = <0x11220000 0x20000>;
reg-names = "ISP";
interrupts = <0 43 4>;
interrupt-names = "ISP";
};
vpss: vpss@11400000 {
compatible = "goke,vpss";
reg = <0x11400000 0x10000>;
reg-names = "vpss0";
interrupts = <0 46 4>;
interrupt-names = "vpss0";
};
vo: vo@11280000 {
compatible = "goke,vo";
reg = <0x11280000 0x40000>;
reg-names = "vo";
interrupts = <0 40 4>;
interrupt-names = "vo";
};
gfbg: gfbg@11280000 {
compatible = "goke,gfbg";
reg = <0x11280000 0x40000>;
reg-names = "gfbg";
interrupts = <0 41 4>;
interrupt-names = "gfbg";
};
vgs: vgs@11300000 {
compatible = "goke,vgs";
reg = <0x11300000 0x10000>;
reg-names = "vgs0";
interrupts = <0 49 4>;
interrupt-names = "vgs0";
};
gzip: gzip@11310000 {
compatible = "goke,gzip";
reg = <0x11310000 0x10000>;
reg-names = "gzip";
interrupts = <0 50 4>;
interrupt-names = "gzip";
};
vedu: vedu@11410000 {
compatible = "goke,vedu";
reg = <0x11410000 0x10000>, <0x11420000 0x10000>;
reg-names = "vedu0", "jpge";
interrupts = <0 47 4>, <0 48 4>;
interrupt-names = "vedu0","jpge";
};
venc: venc {
compatible = "goke,venc";
};
aiao: aiao@100e0000 {
compatible = "goke,aiao";
reg = <0x100e0000 0x10000>,<0x100f0000 0x10000>;
reg-names = "aiao","acodec";
interrupts = <0 42 4>;
interrupt-names = "AIO";
};
ive: ive@11320000 {
compatible = "goke,ive";
reg = <0x11320000 0x10000>;
reg-names = "ive";
interrupts = <0 51 4>;
interrupt-names = "ive";
};
};
};

2858
br-ext-chip-goke/board/gk7205v200/kernel/overlay/arch/arm/configs/gk7202v300_emmc_defconfig
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238
br-ext-chip-hisilicon/board/hi3516av100/kernel/overlay/arch/arm/boot/dts/hi3516a-demb.dts
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@ -1,238 +0,0 @@
/*
* Copyright (c) 2013-2014 Linaro Ltd.
* Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
/dts-v1/;
#include "hi3516a.dtsi"
/ {
model = "Hisilicon HI3516A DEMO Board";
compatible = "hiSilicon,hi3516a";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0>;
operating-points = <
/* KHz uV */
600000 1100000
732000 1200000
850000 1300000
500000 1060000
400000 1020000
>;
clocks = <&clock HI3516A_A7_MUX>,
<&clock HI3516A_FIXED_400M>,
<&clock HI3516A_FIXED_500M>,
<&clock HI3516A_APLL_CLK>;
clock-names = "a7_mux","400m", "500m","apll";
vcc-supply = <&a7_regulator>;
};
};
avs {
compatible = "hi3516a,avs";
avs-num = <2>;
avs-name-array = "cpu-avs","media-avs";
cpu_avs: cpu_avs{
avs-name = "cpu-avs";
opp-num = <5>;
opp-freq = <600000 732000 850000 500000 400000>;
opp-volt-min = <940000 1000000 1070000 940000 940000>;
opp-hpm = <270 325 365 255 240>;
opp-div = <11 14 16 10 8>;
opp-volt-max = <1310000>;
};
media_avs: media_avs{
avs-name = "media-avs";
opp-num = <5>;
opp-freq = <0 1 2 3 4>;
opp-volt-min = <930000 930000 930000 930000 930000>;
opp-hpm = <245 245 245 260 285>;
opp-div = <3 3 4 5 5>;
opp-volt-max = <1310000>;
};
};
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>;
};
};
&uart0 {
status = "okay";
};
&dual_timer0 {
status = "okay";
};
&hidmac {
status = "okay";
};
&i2c_bus0 {
status = "okay";
};
&i2c_bus1 {
status = "okay";
};
&i2c_bus2 {
status = "okay";
};
&spi_bus0{
status = "okay";
num-cs = <1>;
spidev@0 {
compatible = "rohm,dh2228fv";
reg = <0>;
pl022,interface = <0>;
pl022,com_mode = <0>;
spi-max-frequency = <24000000>;
};
};
&spi_bus1{
status = "okay";
num-cs = <3>;
spidev@0 {
compatible = "rohm,dh2228fv";
reg = <0>;
pl022,interface = <0>;
pl022,com_mode = <0>;
spi-max-frequency = <24000000>;
};
spidev@1 {
compatible = "rohm,dh2228fv";
reg = <1>;
pl022,interface = <0>;
pl022,com_mode = <0>;
spi-max-frequency = <24000000>;
};
spidev@2 {
compatible = "rohm,dh2228fv";
reg = <2>;
pl022,interface = <0>;
pl022,com_mode = <0>;
spi-max-frequency = <24000000>;
};
};
&mdio {
ethphy: ethernet-phy@1 {
reg = <1>; /* Disable to invoke autoprobe */
};
};
&higmac {
phy-handle = <&ethphy>;
phy-mode = "rmii";
};
&mmc0 {
status = "okay";
};
&mmc1 {
status = "okay";
};
&gpio_chip0 {
status = "okay";
};
&gpio_chip1 {
status = "okay";
};
&gpio_chip2 {
status = "okay";
};
&gpio_chip3 {
status = "okay";
};
&gpio_chip4 {
status = "okay";
};
&gpio_chip5 {
status = "okay";
};
&gpio_chip6 {
status = "okay";
};
&gpio_chip7 {
status = "okay";
};
&gpio_chip8 {
status = "okay";
};
&gpio_chip9 {
status = "okay";
};
&gpio_chip10 {
status = "okay";
};
&gpio_chip11 {
status = "okay";
};
&gpio_chip12 {
status = "okay";
};
&gpio_chip13 {
status = "okay";
};
&gpio_chip14 {
status = "okay";
};
&gpio_chip15 {
status = "okay";
};

130
br-ext-chip-hisilicon/board/hi3516cv100/kernel/overlay/arch/arm/lib/memset.S
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@ -1,130 +0,0 @@
/*
* linux/arch/arm/lib/memset.S
*
* Copyright (C) 1995-2000 Russell King
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* ASM optimised string functions
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
.text
.align 5
.word 0
1: subs r2, r2, #4 @ 1 do we have enough
blt 5f @ 1 bytes to align with?
cmp r3, #2 @ 1
strltb r1, [ip], #1 @ 1
strleb r1, [ip], #1 @ 1
strb r1, [ip], #1 @ 1
add r2, r2, r3 @ 1 (r2 = r2 - (4 - r3))
/*
* The pointer is now aligned and the length is adjusted. Try doing the
* memset again.
*/
ENTRY(memset)
/*
* Preserve the contents of r0 for the return value.
*/
mov ip, r0
ands r3, ip, #3 @ 1 unaligned?
bne 1b @ 1
/*
* we know that the pointer in ip is aligned to a word boundary.
*/
orr r1, r1, r1, lsl #8
orr r1, r1, r1, lsl #16
mov r3, r1
cmp r2, #16
blt 4f
#if ! CALGN(1)+0
/*
* We need 2 extra registers for this loop - use r8 and the LR
*/
stmfd sp!, {r8, lr}
mov r8, r1
mov lr, r1
2: subs r2, r2, #64
stmgeia ip!, {r1, r3, r8, lr} @ 64 bytes at a time.
stmgeia ip!, {r1, r3, r8, lr}
stmgeia ip!, {r1, r3, r8, lr}
stmgeia ip!, {r1, r3, r8, lr}
bgt 2b
ldmeqfd sp!, {r8, pc} @ Now <64 bytes to go.
/*
* No need to correct the count; we're only testing bits from now on
*/
tst r2, #32
stmneia ip!, {r1, r3, r8, lr}
stmneia ip!, {r1, r3, r8, lr}
tst r2, #16
stmneia ip!, {r1, r3, r8, lr}
ldmfd sp!, {r8, lr}
#else
/*
* This version aligns the destination pointer in order to write
* whole cache lines at once.
*/
stmfd sp!, {r4-r8, lr}
mov r4, r1
mov r5, r1
mov r6, r1
mov r7, r1
mov r8, r1
mov lr, r1
cmp r2, #96
tstgt ip, #31
ble 3f
and r8, ip, #31
rsb r8, r8, #32
sub r2, r2, r8
movs r8, r8, lsl #(32 - 4)
stmcsia ip!, {r4, r5, r6, r7}
stmmiia ip!, {r4, r5}
tst r8, #(1 << 30)
mov r8, r1
strne r1, [ip], #4
3: subs r2, r2, #64
stmgeia ip!, {r1, r3-r8, lr}
stmgeia ip!, {r1, r3-r8, lr}
bgt 3b
ldmeqfd sp!, {r4-r8, pc}
tst r2, #32
stmneia ip!, {r1, r3-r8, lr}
tst r2, #16
stmneia ip!, {r4-r7}
ldmfd sp!, {r4-r8, lr}
#endif
4: tst r2, #8
stmneia ip!, {r1, r3}
tst r2, #4
strne r1, [ip], #4
/*
* When we get here, we've got less than 4 bytes to zero. We
* may have an unaligned pointer as well.
*/
5: tst r2, #2
strneb r1, [ip], #1
strneb r1, [ip], #1
tst r2, #1
strneb r1, [ip], #1
mov pc, lr
ENDPROC(memset)

379
br-ext-chip-hisilicon/board/hi3516cv100/kernel/overlay/kernel/timeconst.pl
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@ -1,379 +0,0 @@
#!/usr/bin/perl
# -----------------------------------------------------------------------
#
# Copyright 2007-2008 rPath, Inc. - All Rights Reserved
#
# This file is part of the Linux kernel, and is made available under
# the terms of the GNU General Public License version 2 or (at your
# option) any later version; incorporated herein by reference.
#
# -----------------------------------------------------------------------
#
#
# Usage: timeconst.pl HZ > timeconst.h
#
# Precomputed values for systems without Math::BigInt
# Generated by:
# timeconst.pl --can 24 32 48 64 100 122 128 200 250 256 300 512 1000 1024 1200
%canned_values = (
24 => [
'0xa6aaaaab','0x2aaaaaa',26,
125,3,
'0xc49ba5e4','0x1fbe76c8b4',37,
3,125,
'0xa2c2aaab','0xaaaa',16,
125000,3,
'0xc9539b89','0x7fffbce4217d',47,
3,125000,
], 32 => [
'0xfa000000','0x6000000',27,
125,4,
'0x83126e98','0xfdf3b645a',36,
4,125,
'0xf4240000','0x0',17,
31250,1,
'0x8637bd06','0x3fff79c842fa',46,
1,31250,
], 48 => [
'0xa6aaaaab','0x6aaaaaa',27,
125,6,
'0xc49ba5e4','0xfdf3b645a',36,
6,125,
'0xa2c2aaab','0x15555',17,
62500,3,
'0xc9539b89','0x3fffbce4217d',46,
3,62500,
], 64 => [
'0xfa000000','0xe000000',28,
125,8,
'0x83126e98','0x7ef9db22d',35,
8,125,
'0xf4240000','0x0',18,
15625,1,
'0x8637bd06','0x1fff79c842fa',45,
1,15625,
], 100 => [
'0xa0000000','0x0',28,
10,1,
'0xcccccccd','0x733333333',35,
1,10,
'0x9c400000','0x0',18,
10000,1,
'0xd1b71759','0x1fff2e48e8a7',45,
1,10000,
], 122 => [
'0x8325c53f','0xfbcda3a',28,
500,61,
'0xf9db22d1','0x7fbe76c8b',35,
61,500,
'0x8012e2a0','0x3ef36',18,
500000,61,
'0xffda4053','0x1ffffbce4217',45,
61,500000,
], 128 => [
'0xfa000000','0x1e000000',29,
125,16,
'0x83126e98','0x3f7ced916',34,
16,125,
'0xf4240000','0x40000',19,
15625,2,
'0x8637bd06','0xfffbce4217d',44,
2,15625,
], 200 => [
'0xa0000000','0x0',29,
5,1,
'0xcccccccd','0x333333333',34,
1,5,
'0x9c400000','0x0',19,
5000,1,
'0xd1b71759','0xfff2e48e8a7',44,
1,5000,
], 250 => [
'0x80000000','0x0',29,
4,1,
'0x80000000','0x180000000',33,
1,4,
'0xfa000000','0x0',20,
4000,1,
'0x83126e98','0x7ff7ced9168',43,
1,4000,
], 256 => [
'0xfa000000','0x3e000000',30,
125,32,
'0x83126e98','0x1fbe76c8b',33,
32,125,
'0xf4240000','0xc0000',20,
15625,4,
'0x8637bd06','0x7ffde7210be',43,
4,15625,
], 300 => [
'0xd5555556','0x2aaaaaaa',30,
10,3,
'0x9999999a','0x1cccccccc',33,
3,10,
'0xd0555556','0xaaaaa',20,
10000,3,
'0x9d495183','0x7ffcb923a29',43,
3,10000,
], 512 => [
'0xfa000000','0x7e000000',31,
125,64,
'0x83126e98','0xfdf3b645',32,
64,125,
'0xf4240000','0x1c0000',21,
15625,8,
'0x8637bd06','0x3ffef39085f',42,
8,15625,
], 1000 => [
'0x80000000','0x0',31,
1,1,
'0x80000000','0x0',31,
1,1,
'0xfa000000','0x0',22,
1000,1,
'0x83126e98','0x1ff7ced9168',41,
1,1000,
], 1024 => [
'0xfa000000','0xfe000000',32,
125,128,
'0x83126e98','0x7ef9db22',31,
128,125,
'0xf4240000','0x3c0000',22,
15625,16,
'0x8637bd06','0x1fff79c842f',41,
16,15625,
], 1200 => [
'0xd5555556','0xd5555555',32,
5,6,
'0x9999999a','0x66666666',31,
6,5,
'0xd0555556','0x2aaaaa',22,
2500,3,
'0x9d495183','0x1ffcb923a29',41,
3,2500,
]
);
$has_bigint = eval 'use Math::BigInt qw(bgcd); 1;';
sub bint($)
{
my($x) = @_;
return Math::BigInt->new($x);
}
#
# Constants for division by reciprocal multiplication.
# (bits, numerator, denominator)
#
sub fmul($$$)
{
my ($b,$n,$d) = @_;
$n = bint($n);
$d = bint($d);
return scalar (($n << $b)+$d-bint(1))/$d;
}
sub fadj($$$)
{
my($b,$n,$d) = @_;
$n = bint($n);
$d = bint($d);
$d = $d/bgcd($n, $d);
return scalar (($d-bint(1)) << $b)/$d;
}
sub fmuls($$$) {
my($b,$n,$d) = @_;
my($s,$m);
my($thres) = bint(1) << ($b-1);
$n = bint($n);
$d = bint($d);
for ($s = 0; 1; $s++) {
$m = fmul($s,$n,$d);
return $s if ($m >= $thres);
}
return 0;
}
# Generate a hex value if the result fits in 64 bits;
# otherwise skip.
sub bignum_hex($) {
my($x) = @_;
my $s = $x->as_hex();
return (length($s) > 18) ? undef : $s;
}
# Provides mul, adj, and shr factors for a specific
# (bit, time, hz) combination
sub muladj($$$) {
my($b, $t, $hz) = @_;
my $s = fmuls($b, $t, $hz);
my $m = fmul($s, $t, $hz);
my $a = fadj($s, $t, $hz);
return (bignum_hex($m), bignum_hex($a), $s);
}
# Provides numerator, denominator values
sub numden($$) {
my($n, $d) = @_;
my $g = bgcd($n, $d);
return ($n/$g, $d/$g);
}
# All values for a specific (time, hz) combo
sub conversions($$) {
my ($t, $hz) = @_;
my @val = ();
# HZ_TO_xx
push(@val, muladj(32, $t, $hz));
push(@val, numden($t, $hz));
# xx_TO_HZ
push(@val, muladj(32, $hz, $t));
push(@val, numden($hz, $t));
return @val;
}
sub compute_values($) {
my($hz) = @_;
my @val = ();
my $s, $m, $a, $g;
if (!$has_bigint) {
die "$0: HZ == $hz not canned and ".
"Math::BigInt not available\n";
}
# MSEC conversions
push(@val, conversions(1000, $hz));
# USEC conversions
push(@val, conversions(1000000, $hz));
return @val;
}
sub outputval($$)
{
my($name, $val) = @_;
my $csuf;
if (defined($val)) {
if ($name !~ /SHR/) {
$val = "U64_C($val)";
}
printf "#define %-23s %s\n", $name.$csuf, $val.$csuf;
}
}
sub output($@)
{
my($hz, @val) = @_;
my $pfx, $bit, $suf, $s, $m, $a;
print "/* Automatically generated by kernel/timeconst.pl */\n";
print "/* Conversion constants for HZ == $hz */\n";
print "\n";
print "#ifndef KERNEL_TIMECONST_H\n";
print "#define KERNEL_TIMECONST_H\n";
print "\n";
print "#include <linux/param.h>\n";
print "#include <linux/types.h>\n";
print "\n";
print "#if HZ != $hz\n";
print "#error \"kernel/timeconst.h has the wrong HZ value!\"\n";
print "#endif\n";
print "\n";
foreach $pfx ('HZ_TO_MSEC','MSEC_TO_HZ',
'HZ_TO_USEC','USEC_TO_HZ') {
foreach $bit (32) {
foreach $suf ('MUL', 'ADJ', 'SHR') {
outputval("${pfx}_$suf$bit", shift(@val));
}
}
foreach $suf ('NUM', 'DEN') {
outputval("${pfx}_$suf", shift(@val));
}
}
print "\n";
print "#endif /* KERNEL_TIMECONST_H */\n";
}
# Pretty-print Perl values
sub perlvals(@) {
my $v;
my @l = ();
foreach $v (@_) {
if (!defined($v)) {
push(@l, 'undef');
} elsif ($v =~ /^0x/) {
push(@l, "\'".$v."\'");
} else {
push(@l, $v.'');
}
}
return join(',', @l);
}
($hz) = @ARGV;
# Use this to generate the %canned_values structure
if ($hz eq '--can') {
shift(@ARGV);
@hzlist = sort {$a <=> $b} (@ARGV);
print "# Precomputed values for systems without Math::BigInt\n";
print "# Generated by:\n";
print "# timeconst.pl --can ", join(' ', @hzlist), "\n";
print "\%canned_values = (\n";
my $pf = "\t";
foreach $hz (@hzlist) {
my @values = compute_values($hz);
print "$pf$hz => [\n";
while (scalar(@values)) {
my $bit;
foreach $bit (32) {
my $m = shift(@values);
my $a = shift(@values);
my $s = shift(@values);
print "\t\t", perlvals($m,$a,$s), ",\n";
}
my $n = shift(@values);
my $d = shift(@values);
print "\t\t", perlvals($n,$d), ",\n";
}
print "\t]";
$pf = ', ';
}
print "\n);\n";
} else {
$hz += 0; # Force to number
if ($hz < 1) {
die "Usage: $0 HZ\n";
}
@val = @{$canned_values{$hz}};
#if (!defined(@val)) {
if(!@val) {
@val = compute_values($hz);
}
output($hz, @val);
}
exit 0;

576
br-ext-chip-hisilicon/board/hi3516cv200/kernel/overlay/arch/arm/boot/dts/hi3518ev20x.dtsi
View File

@ -1,576 +0,0 @@
/*
* Copyright (c) 2013-2014 Linaro Ltd.
* Copyright (c) 2015-2017 HiSilicon Technologies Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
#include <dt-bindings/clock/hi3518ev20x-clock.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,arm926ej-s";
reg = <0>;
};
};
vic: interrupt-controller@100d0000 {
compatible = "arm,pl190-vic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x100d0000 0x1000>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&vic>;
ranges;
clock: clock@20030000 {
compatible = "hisilicon,hi3518ev20x-clock";
reg = <0x20030000 0x1000>;
#clock-cells = <1>;
#reset-cells = <2>;
};
sysctrl: system-controller@20050000 {
compatible = "hisilicon,hi3518ev20x-sysctrl",
"syscon";
reg = <0x20050000 0x1000>;
#clock-cells = <1>;
};
reboot {
compatible = "syscon-reboot";
regmap = <&sysctrl>;
offset = <0x4>;
mask = <0xdeadbeef>;
};
dual_timer0: dual_timer@20000000 {
compatible = "arm,sp804", "arm,primecell";
/* timer0 & timer1 */
interrupts = <3>;
reg = <0x20000000 0x1000>;
clocks = <&sysctrl HI3518EV20X_TIME0_0_CLK>,
<&sysctrl HI3518EV20X_TIME0_1_CLK>,
<&clock HI3518EV20X_SYSAPB_CLK>;
clock-names = "timer0", "timer1", "apb_pclk";
status = "disabled";
};
dual_timer1: dual_timer@20010000 {
compatible = "arm,sp804", "arm,primecell";
/* timer2 & timer3 */
interrupts = <4>;
reg = <0x20010000 0x1000>;
clocks = <&sysctrl HI3518EV20X_TIME1_2_CLK>,
<&sysctrl HI3518EV20X_TIME1_3_CLK>,
<&clock HI3518EV20X_SYSAPB_CLK>;
clock-names = "timer2", "timer3", "apb_pclk";
status = "disabled";
};
uart0: uart@20080000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x20080000 0x1000>;
interrupts = <5>;
clocks = <&clock HI3518EV20X_UART0_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
uart1: uart@20090000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x20090000 0x1000>;
interrupts = <30>;
clocks = <&clock HI3518EV20X_UART1_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
uart2: uart@200a0000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x200a0000 0x1000>;
interrupts = <25>;
clocks = <&clock HI3518EV20X_UART2_CLK>;
clock-names = "apb_pclk";
status = "disabled";
};
usb_phy: phy {
compatible = "hisilicon,hisi-usb-phy";
reg = <0x20030000 0x10000>, <0x20120000 0x10000>,
<0x20050000 0x10000>;
#phy-cells = <0>;
};
ehci@0x100b0000 {
compatible = "generic-ehci";
reg = <0x100b0000 0x10000>;
interrupts = <15>;
clocks = <&clock HI3518EV20X_USB2_CTRL_UTMI0_REQ>,
<&clock HI3518EV20X_USB2_HRST_REQ>;
clock-names = "usb2_cttl_utmi0_req", "usb2_hrst_req";
};
ohci@0x100a0000 {
compatible = "generic-ohci";
reg = <0x100a0000 0x10000>;
interrupts = <16>;
clocks = <&clock HI3518EV20X_USB2_CTRL_UTMI0_REQ>,
<&clock HI3518EV20X_USB2_HRST_REQ>;
clock-names = "usb2_cttl_utmi0_req", "usb2_hrst_req";
};
hiudc@0x10080000 {
compatible = "hiudc";
reg = <0x10080000 0x10000>;
interrupts = <10>;
clocks = <&clock HI3518EV20X_USB2_HRST_REQ>;
clock-names = "clk";
};
i2c_bus0: i2c@200d0000 {
compatible = "hisilicon,hisi-i2c-hisilicon";
reg = <0x200d0000 0x100>;
interrupts = <20>;
clocks = <&clock HI3518EV20X_SYSAPB_CLK>;
clock-frequency = <100000>;
io-size = <0x1000>;
id = <0>;
status = "disabled";
};
i2c_bus1: i2c@20240000 {
compatible = "hisilicon,hisi-i2c-hisilicon";
reg = <0x20240000 0x100>;
interrupts = <20>;
clocks = <&clock HI3518EV20X_SYSAPB_CLK>;
clock-frequency = <100000>;
io-size = <0x1000>;
id = <1>;
status = "disabled";
};
i2c_bus2: i2c@20250000 {
compatible = "hisilicon,hisi-i2c-hisilicon";
reg = <0x20250000 0x100>;
interrupts = <20>;
clocks = <&clock HI3518EV20X_SYSAPB_CLK>;
clock-frequency = <100000>;
io-size = <0x1000>;
id = <2>;
status = "disabled";
};
spi_bus0: spi@200c0000 {
compatible = "arm,pl022", "arm,primecell";
arm,primecell-periphid = <0x00800022>;
reg = <0x200c0000 0x1000>;
interrupts = <6>;
clocks = <&clock HI3518EV20X_SPI0_CLK>;
clock-names = "apb_pclk";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
spi_bus1: spi@200e0000 {
compatible = "arm,pl022", "arm,primecell";
arm,primecell-periphid = <0x00800022>;
reg = <0x200e0000 0x1000>, <0x20120004 0x4>;
interrupts = <7>;
clocks = <&clock HI3518EV20X_SPI1_CLK>;
clock-names = "apb_pclk";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
hisi,spi_cs_sb = <26>;
hisi,spi_cs_mask_bit = <0x0c000000>;
};
fmc: flash-memory-controller@10010000 {
compatible = "hisilicon,hisi-fmc";
reg = <0x10010000 0x1000>, <0x58000000 0x10000>;
reg-names = "control", "memory";
clocks = <&clock HI3518EV20X_FMC_CLK>;
#address-cells = <1>;
#size-cells = <0>;
hisfc:spi-nor@0 {
compatible = "hisilicon,fmc-spi-nor";
assigned-clocks = <&clock HI3518EV20X_FMC_CLK>;
assigned-clock-rates = <24000000>;
#address-cells = <1>;
#size-cells = <0>;
};
hisnfc:spi-nand@0 {
compatible = "hisilicon,fmc-spi-nand";
assigned-clocks = <&clock HI3518EV20X_FMC_CLK>;
assigned-clock-rates = <24000000>;
#address-cells = <1>;
#size-cells = <0>;
};
};
mdio: mdio@10091100 {
compatible = "hisilicon,hisi-femac-mdio";
reg = <0x10091100 0x10>;
clocks = <&clock HI3518EV20X_ETH_CLK>;
clock-names = "mdio";
assigned-clocks = <&clock HI3518EV20X_ETH_CLK>;
assigned-clock-rates = <54000000>;
resets = <&clock 0xec 3>;
reset-names = "external-phy";
#address-cells = <1>;
#size-cells = <0>;
};
hisi_femac: ethernet@10090000 {
compatible = "hisilicon,hi3518ev20x-femac",
"hisilicon,hisi-femac-v2";
reg = <0x10090000 0x1000>,<0x10091300 0x200>;
interrupts = <12>;
clocks = <&clock HI3518EV20X_ETH_CLK>;
resets = <&clock 0xec 0>;
reset-names = "mac";
};
mmc0_emmc: himciv200.MMC@0x10020000{
compatible = "hisilicon,hi3518ev20x-himci";
reg = <0x10020000 0x1000>;
interrupts = <18>;
clocks = <&clock HI3518EV20X_MMC0_CLK>;
clock-names = "mmc_clk";
max-frequency = <99000000>;
resets = <&clock 0xc4 8>;
reset-names = "mmc_reset";
bus-width = <8>;
cap-mmc-highspeed;
cap-mmc-hw-reset;
mmc-hs200-1_8v;
full-pwr-cycle;
devid = <0>;
status = "disabled";
};
mmc0_sd: himciv200.SD@0x10020000{
compatible = "hisilicon,hi3518ev20x-himci";
reg = <0x10020000 0x1000>;
interrupts = <18>;
clocks = <&clock HI3518EV20X_MMC0_CLK>;
clock-names = "mmc_clk";
max-frequency = <49500000>;
resets = <&clock 0xc4 8>;
reset-names = "mmc_reset";
bus-width = <4>;
cap-sd-highspeed;
devid = <0>;
status = "disabled";
};
mmc1_sd: himciv200.SD@0x10030000{
compatible = "hisilicon,hi3518ev20x-himci";
reg = <0x10030000 0x1000>;
interrupts = <8>;
clocks = <&clock HI3518EV20X_MMC1_CLK>;
clock-names = "mmc_clk";
max-frequency = <49500000>;
resets = <&clock 0xc4 0>;
reset-names = "mmc_reset";
bus-width = <4>;
cap-sd-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
devid = <1>;
status = "disabled";
};
pmux: pinmux@200f0000 {
compatible = "pinctrl-single";
reg = <0x200f0000 0x108>;
#address-cells = <1>;
#size-cells = <1>;
#gpio-range-cells = <3>;
ranges;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <7>;
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 5 0
&range 6 38 0 &range 44 1 2
&range 45 13 0 &range 58 8 1>;
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
};
pconf: pinconf@200f0800 {
compatible = "pinconf-single";
reg = <0x200f0800 0x130>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
pinctrl-single,register-width = <32>;
};
gpio_chip0: gpio_chip@20140000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x20140000 0x10000>;
interrupts = <31>;
clocks = <&clock HI3518EV20X_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
gpio-ranges = <&pmux 0 28 3>, <&pmux 3 12 1>,
<&pmux 4 0 4>;
status = "disabled";
};
gpio_chip1: gpio_chip@20150000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x20150000 0x10000>;
interrupts = <31>;
clocks = <&clock HI3518EV20X_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
gpio-ranges = <&pmux 0 31 8>;
status = "disabled";
};
gpio_chip2: gpio_chip@20160000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x20160000 0x10000>;
interrupts = <31>;
clocks = <&clock HI3518EV20X_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
gpio-ranges = <&pmux 0 4 8>;
status = "disabled";
};
gpio_chip3: gpio_chip@20170000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x20170000 0x10000>;
interrupts = <31>;
clocks = <&clock HI3518EV20X_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
gpio-ranges = <&pmux 0 13 8>;
status = "disabled";
};
gpio_chip4: gpio_chip@20180000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x20180000 0x10000>;
interrupts = <31>;
clocks = <&clock HI3518EV20X_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
gpio-ranges = <&pmux 0 21 7>, <&pmux 7 39 1>;
status = "disabled";
};
gpio_chip5: gpio_chip@20190000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x20190000 0x10000>;
interrupts = <31>;
clocks = <&clock HI3518EV20X_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
gpio-ranges = <&pmux 0 40 8>;
status = "disabled";
};
gpio_chip6: gpio_chip@201a0000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x201a0000 0x10000>;
interrupts = <31>;
clocks = <&clock HI3518EV20X_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
gpio-ranges = <&pmux 0 48 8>;
status = "disabled";
};
gpio_chip7: gpio_chip@201b0000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x201b0000 0x10000>;
interrupts = <31>;
clocks = <&clock HI3518EV20X_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
gpio-ranges = <&pmux 0 56 8>;
status = "disabled";
};
gpio_chip8: gpio_chip@201c0000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x201c0000 0x10000>;
interrupts = <31>;
clocks = <&clock HI3518EV20X_SYSAPB_CLK>;
clock-names = "apb_pclk";
#gpio-cells = <2>;
gpio-ranges = <&pmux 0 64 2>;
status = "disabled";
};
hidmac: hidma-controller@10060000 {
compatible = "hisilicon,hisi-dmac";
reg = <0x10060000 0x1000>;
interrupts = <14>;
clocks = <&clock HI3518EV20X_DMAC_CLK>;
clock-names = "dmac_clk";
resets = <&clock 0xd8 4>;
reset-names = "dma-reset";
#dma-cells = <2>;
status = "disabled";
};
};
media {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&vic>;
ranges;
sys_config {
compatible = "hisilicon,sys_config";
};
sys: sys@20030000 {
compatible = "hisilicon,hi35xx_sys";
reg = <0x20030000 0x10000>, <0x20050000 0x10000>,
<0x20110000 0x10000>, <0x20120000 0x10000>;
reg-names = "crg", "sys", "ddr", "misc";
};
audio: audio@20650000 {
compatible = "hisilicon,hi35xx_aiao";
interrupts = <9>;
reg = <0x20650000 0x10000>;
reg-names = "aiao";
};
ive: ive@206a0000 {
compatible = "hisilicon,hi35xx_ive";
interrupts = <21>;
reg = <0x206a0000 0x10000>;
};
mipi: mipi@20680000 {
compatible = "hisilicon,hi35xx_mipi";
interrupts = <28>;
reg = <0x20680000 0x10000>;
};
isp: isp@20580000 {
compatible = "hisilicon,hi35xx_isp";
interrupts = <22>;
reg = <0x20580000 0x10000>, <0x205a0000 0x20000>;
reg-names = "reg_vicap_base_va", "reg_isp_base_va";
};
viu: viu@20580000 {
compatible = "hisilicon,hi35xx_viu";
interrupts = <22>;
reg = <0x20580000 0x40000>;
};
vou: vou@205c0000 {
compatible = "hisilicon,hi35xx_vou";
interrupts = <23>;
reg = <0x205c0000 0x10000>;
};
vgs: vgs@20630000 {
compatible = "hisilicon,hi35xx_vgs";
interrupts = <29>;
reg = <0x20630000 0x10000>;
};
vpss: vpss@20600000 {
compatible = "hisilicon,hi35xx_vpss";
interrupts = <17>;
reg = <0x20600000 0x10000>;
};
avc: avc@20620000 {
compatible = "hisilicon,hi35xx_avc";
interrupts = <24>;
reg = <0x20620000 0x10000>;
};
jpege: jpege@20660000 {
compatible = "hisilicon,hi35xx_jpege";
interrupts = <26>;
reg = <0x20660000 0x10000>;
};
tde: tde@20610000 {
compatible = "hisilicon,hi35xx_tde";
interrupts = <27>;
reg = <0x20610000 0x10000>;
};
pwm: pwm@20130000 {
compatible = "hisilicon,hi3516cv300-pwm";
reg = <0x20130000 0x10000>;
};
wtdg: wtdg@20040000 {
compatible = "hisilicon,hi_wdg";
reg = <0x20040000 0x10000>;
reg-names = "wtdg";
};
rtc: rtc@20060000 {
compatible = "hisilicon,hi_rtc";
interrupts = <2>, <2>;
interrupt-names = "rtc", "rtc_temp";
reg = <0x20060000 0x10000>;
};
ir: ir@20070000{
compatible = "hisilicon,hi_ir";
interrupts = <19>;
reg = <0x20070000 0x10000>;
};
cipher: cipher@100c0000{
compatible = "hisilicon,hi_cipher";
interrupts = <13>;
reg = <0x100c0000 0x10000>;
};
};
};

65
br-ext-chip-hisilicon/board/hi3516cv300/kernel/overlay/include/linux/compiler-gcc6.h
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@ -1,65 +0,0 @@
#ifndef __LINUX_COMPILER_H
#error "Please don't include <linux/compiler-gcc5.h> directly, include <linux/compiler.h> instead."
#endif
#define __used __attribute__((__used__))
#define __must_check __attribute__((warn_unused_result))
#define __compiler_offsetof(a, b) __builtin_offsetof(a, b)
/* Mark functions as cold. gcc will assume any path leading to a call
to them will be unlikely. This means a lot of manual unlikely()s
are unnecessary now for any paths leading to the usual suspects
like BUG(), printk(), panic() etc. [but let's keep them for now for
older compilers]
Early snapshots of gcc 4.3 don't support this and we can't detect this
in the preprocessor, but we can live with this because they're unreleased.
Maketime probing would be overkill here.
gcc also has a __attribute__((__hot__)) to move hot functions into
a special section, but I don't see any sense in this right now in
the kernel context */
#define __cold __attribute__((__cold__))
#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)
#ifndef __CHECKER__
# define __compiletime_warning(message) __attribute__((warning(message)))
# define __compiletime_error(message) __attribute__((error(message)))
#endif /* __CHECKER__ */
/*
* Mark a position in code as unreachable. This can be used to
* suppress control flow warnings after asm blocks that transfer
* control elsewhere.
*
* Early snapshots of gcc 4.5 don't support this and we can't detect
* this in the preprocessor, but we can live with this because they're
* unreleased. Really, we need to have autoconf for the kernel.
*/
#define unreachable() __builtin_unreachable()
/* Mark a function definition as prohibited from being cloned. */
#define __noclone __attribute__((__noclone__))
/*
* Tell the optimizer that something else uses this function or variable.
*/
#define __visible __attribute__((externally_visible))
/*
* GCC 'asm goto' miscompiles certain code sequences:
*
* http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670
*
* Work it around via a compiler barrier quirk suggested by Jakub Jelinek.
*
* (asm goto is automatically volatile - the naming reflects this.)
*/
#define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0)
#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP
#define __HAVE_BUILTIN_BSWAP32__
#define __HAVE_BUILTIN_BSWAP64__
#define __HAVE_BUILTIN_BSWAP16__
#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */

247
br-ext-chip-hisilicon/board/hi3519v101/kernel/overlay.2/arch/arm/boot/dts/hisi-hi3519v101-demb.dts
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@ -1,247 +0,0 @@
/*
* Copyright (c) 2013-2014 Linaro Ltd.
* Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
/dts-v1/;
#include "hisi-hi3519v101.dtsi"
/ {
model = "Hisilicon HI3519V101 DEMO Board";
compatible = "hisilicon,hi3519v101";
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "hisilicon,hi3519-smp";
cpu@0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
clock-frequency = <HI3519_FIXED_792M>;
reg = <0>;
cci-control-port = <&cci_control0>;
};
/*cpu@100 {
compatible = "arm,cortex-a17";
device_type = "cpu";
clock-frequency = <HI3519_FIXED_1000M>;
reg = <0x100>;
cci-control-port = <&cci_control1>;
};*/
};
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>;
};
};
&uart0 {
status = "okay";
};
&dual_timer0 {
status = "okay";
};
&i2c_bus0 {
status = "okay";
};
&i2c_bus1 {
status = "okay";
};
&i2c_bus2 {
status = "okay";
};
&i2c_bus3 {
status = "okay";
};
&spi_bus0 {
status = "okay";
spidev@0 {
compatible = "rohm,dh2228fv";
reg = <0>;
pl022,interface = <0>;
pl022,com-mode = <0>;
spi-max-frequency = <24750000>;
};
};
&spi_bus1 {
status = "okay";
spidev@0 {
compatible = "rohm,dh2228fv";
reg = <0>;
pl022,interface = <0>;
pl022,com-mode = <0>;
spi-max-frequency = <24750000>;
};
};
&spi_bus2 {
status = "okay";
spidev@0 {
compatible = "rohm,dh2228fv";
reg = <0>;
pl022,interface = <0>;
pl022,com-mode = <0>;
spi-max-frequency = <24750000>;
};
spidev@1 {
compatible = "rohm,dh2228fv";
reg = <1>;
pl022,interface = <0>;
pl022,com-mode = <0>;
spi-max-frequency = <24750000>;
};
};
&spi_bus3 {
status = "okay";
spidev@0 {
compatible = "rohm,dh2228fv";
reg = <0>;
pl022,interface = <0>;
pl022,com-mode = <0>;
spi-max-frequency = <24750000>;
};
};
&hisfc {
hi_sfc {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <160000000>;
m25p,fast-read;
};
};
&hisnfc {
hinand {
compatible = "jedec,spi-nand";
reg = <0>;
spi-max-frequency = <160000000>;
};
};
&hinfc {
hinand {
compatible = "jedec,nand";
reg = <0>;
nand-max-frequency = <200000000>;
};
};
&mmc0 {
status = "okay";
};
&mmc1 {
status = "okay";
};
&mmc2 {
status = "okay";
};
&mdio {
ethphy: ethernet-phy@1 {
reg = <1>;
};
};
&higmac {
phy-handle = <&ethphy>;
phy-mode = "rmii";
};
&gpio_chip0 {
status = "okay";
};
&gpio_chip1 {
status = "okay";
};
&gpio_chip2 {
status = "okay";
};
&gpio_chip3 {
status = "okay";
};
&gpio_chip4 {
status = "okay";
};
&gpio_chip5 {
status = "okay";
};
&gpio_chip6 {
status = "okay";
};
&gpio_chip7 {
status = "okay";
};
&gpio_chip8 {
status = "okay";
};
&gpio_chip9 {
status = "okay";
};
&gpio_chip10 {
status = "okay";
};
&gpio_chip11 {
status = "okay";
};
&gpio_chip12 {
status = "okay";
};
&gpio_chip13 {
status = "okay";
};
&gpio_chip14 {
status = "okay";
};
&gpio_chip16 {
status = "okay";
};

310
br-ext-chip-hisilicon/board/hi3519v101/kernel/overlay.2/arch/arm/boot/dts/hisi-hi3519v101-hmp-demb.dts
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@ -1,310 +0,0 @@
/*
* Copyright (c) 2013-2014 Linaro Ltd.
* Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
/dts-v1/;
#include "hisi-hi3519v101.dtsi"
/ {
model = "Hisilicon HI3519V101 DEMO Board";
compatible = "hisilicon,hi3519v101";
chosen {
bootargs = "console=ttyAMA0,115200 early_printk
root=/dev/mtdblock2 rootfstype=jffs2 mtdparts=hi_sfc:1M(boot),
4M(kernel),11M(rootfs)";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
enable-method = "hisilicon,hi3519-smp";
cpu@0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
clock-frequency = <HI3519_FIXED_792M>;
reg = <0>;
cci-control-port = <&cci_control0>;
};
cpu@100 {
compatible = "arm,cortex-a17";
device_type = "cpu";
reg = <0x100>;
cci-control-port = <&cci_control1>;
operating-points = <
/* KHz uV */
1250000 1060000
1150000 1060000
1000000 1000000
930000 1000000
792000 940000
594000 940000
>;
clocks = <&clock HI3519_A17_MUX>,
<&clock HI3519_FIXED_400M>,
<&clock HI3519_FIXED_500M>,
<&clock HI3519_FIXED_594M>,
<&clock HI3519_FIXED_792M>,
<&clock HI3519_APLL_CLK>;
clock-names = "a17_mux","400m", "500m",
"594m", "792m", "apll";
vcc-supply = <&a17_regulator>;
};
};
avs {
compatible = "hi3519,avs";
avs-num = <2>;
avs-name-array = "cpu-avs","media-avs";
cpu_avs: cpu_avs{
avs-name = "cpu-avs";
opp-num = <6>;
opp-freq = <1250000 1150000 1000000 930000 792000 594000 >;
opp-volt-min = <870000 870000 800000 800000 740000 740000>;
opp-hpm = <310 310 280 280 250 250>;
opp-div = <24 22 19 18 15 11>;
opp-volt-max = <1060000>;
};
media_avs: media_avs{
avs-name = "media-avs";
opp-num = <4>;
opp-prof-num = <2>;
opp-temp-num = <2>;
opp-temp = <50 200>;
opp-freq = <1 2 3 4>;
opp-volt-min = <
/* profile2 profile3*/
770000 770000
770000 770000
>;
opp-hpm = <
/* profile2 profile3*/
210 215
190 215
>;
opp-div = <3 3 3 3>;
opp-volt-max = <
/* profile2 profile3*/
977000 977000
977000 977000
>;
};
};
memory {
device_type = "memory";
reg = <0x80000000 0x40000000>;
};
};
&uart0 {
status = "okay";
};
&dual_timer0 {
status = "okay";
};
&i2c_bus0 {
status = "okay";
};
&i2c_bus1 {
status = "okay";
};
&i2c_bus2 {
status = "okay";
};
&i2c_bus3 {
status = "okay";
};
&spi_bus0 {
status = "okay";
spidev@0 {
compatible = "rohm,dh2228fv";
reg = <0>;
pl022,interface = <0>;
pl022,com-mode = <0>;
spi-max-frequency = <24000000>;
};
};
&spi_bus1 {
status = "okay";
spidev@0 {
compatible = "rohm,dh2228fv";
reg = <0>;
pl022,interface = <0>;
pl022,com-mode = <0>;
spi-max-frequency = <24000000>;
};
spidev@1 {
compatible = "rohm,dh2228fv";
reg = <1>;
pl022,interface = <0>;
pl022,com-mode = <0>;
spi-max-frequency = <24000000>;
};
};
&spi_bus2 {
status = "okay";
spidev@0 {
compatible = "rohm,dh2228fv";
reg = <0>;
pl022,interface = <0>;
pl022,com-mode = <0>;
spi-max-frequency = <24000000>;
};
};
&spi_bus3 {
status = "okay";
spidev@0 {
compatible = "rohm,dh2228fv";
reg = <0>;
pl022,interface = <0>;
pl022,com-mode = <0>;
spi-max-frequency = <24000000>;
};
};
&hisfc {
hi_sfc {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <160000000>;
m25p,fast-read;
};
};
&hisnfc {
hinand {
compatible = "jedec,spi-nand";
reg = <0>;
spi-max-frequency = <160000000>;
};
};
&hinfc {
hinand {
compatible = "jedec,nand";
reg = <0>;
nand-max-frequency = <200000000>;
};
};
&mmc0 {
status = "okay";
};
&mmc1 {
status = "okay";
};
&mmc2 {
status = "okay";
};
&mdio {
ethphy: ethernet-phy@1 {
reg = <1>;
};
};
&higmac {
compatible = "hisilicon,higmac-v3", "hisilicon,higmac";
phy-handle = <&ethphy>;
phy-mode = "rmii";
};
&gpio_chip0 {
status = "okay";
};
&gpio_chip1 {
status = "okay";
};
&gpio_chip2 {
status = "okay";
};
&gpio_chip3 {
status = "okay";
};
&gpio_chip4 {
status = "okay";
};
&gpio_chip5 {
status = "okay";
};
&gpio_chip6 {
status = "okay";
};
&gpio_chip7 {
status = "okay";
};
&gpio_chip8 {
status = "okay";
};
&gpio_chip9 {
status = "okay";
};
&gpio_chip10 {
status = "okay";
};
&gpio_chip11 {
status = "okay";
};
&gpio_chip12 {
status = "okay";
};
&gpio_chip13 {
status = "okay";
};
&gpio_chip14 {
status = "okay";
};
&gpio_chip16 {
status = "okay";
};

207
br-ext-chip-hisilicon/board/hi3519v101/kernel/overlay/arch/arm/mach-hisi/pmc_hi3516av200.c
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@ -1,207 +0,0 @@
/*
* power mangager control for hisilicon hi3516av200 soc
*
* Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
* Authors: zengtao@hisilicon.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
#include <linux/io.h>
#include <linux/linkage.h>
#include <linux/bug.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/resource.h>
#include <mach/platform.h>
#include <linux/delay.h>
#define PERI_PMC77 (0x134)
#define PERI_PMC79 (0x13c)
#define PERI_PMC85 (0x154)
static void __iomem *pmc_base;
static u32 __attribute__((used)) pmc_phys_addr;
#define PMC_ADDRESS(reg) (pmc_base + reg)
/* set bitfield of reg from start bit to end - 1 bit */
static void reg_bit_set(u32 reg, u32 start, u32 end, u32 val)
{
u32 regval, mask;
regval = readl((void __iomem *)PMC_ADDRESS(reg));
mask = ((0xffffffff << (32 - start)) >> (32 - start))
| ((0xffffffff >> end) << end);
regval &= mask;
regval |= (val << start);
writel(regval, (void __iomem *)PMC_ADDRESS(reg));
}
/* get bitfield of reg from start bit to end - 1 bit */
static u32 reg_bit_get(u32 reg, u32 start, u32 end)
{
u32 regval;
regval = readl((void __iomem *)PMC_ADDRESS(reg));
regval = (regval << (32 - end)) >> (32 - end);
regval = regval >> start;
return regval;
}
void hi_pmc_power_up_done(void)
{
writel(0, (void __iomem *)PMC_ADDRESS(PERI_PMC85));
writel(1, (void __iomem *)PMC_ADDRESS(PERI_PMC85));
}
/* before power down set ac inactive */
void hi_pmc_set_ac_inactive(void)
{
reg_bit_set(PERI_PMC79, 8, 9, 1);
}
/* after powerup clear ac inactive */
void hi_pmc_clear_ac_inactive(void)
{
reg_bit_set(PERI_PMC79, 8, 9, 0);
}
EXPORT_SYMBOL(hi_pmc_clear_ac_inactive);
/* call from assable context */
asmlinkage void __naked hi_pmc_clear_a17_ac(void)
{
asm volatile("\n"
"adr r2, 1f\n"
"ldmia r2, {r1, r3}\n"
"sub r0, r2, r1\n"
"ldr r2, [r0, r3]\n"
"ldr r0, ="__stringify(PERI_PMC79)"\n"
"add r0, r0, r2\n"
"ldr r1, [r0]\n"
"bic r1, #0x100\n"
"str r1, [r0]\n"
"mov r0, #0\n"
"bx lr\n"
".align 2\n"
"1: .word .\n"
" .word pmc_phys_addr\n"
);
unreachable();
}
static void hi_pmc_config(void)
{
/* enable pmc timeout */
reg_bit_set(PERI_PMC77, 12, 13, 1);
/* enable pmc auto mode */
reg_bit_set(PERI_PMC79, 0, 2, 0);
/* enable irq triger source power on */
reg_bit_set(PERI_PMC79, 7, 8, 1);
}
/* cpu hotplug powerup */
void hi_pmc_power_up(void)
{
u32 power_state;
hi_pmc_config();
/* make sure it powerup state when power up */
power_state = reg_bit_get(PERI_PMC79, 12, 16);
BUG_ON(power_state != 0);
/* disable interrupt wakeup */
reg_bit_set(PERI_PMC79, 5, 6, 0);
/* power on */
reg_bit_set(PERI_PMC79, 3, 4, 0);
reg_bit_set(PERI_PMC79, 3, 4, 1);
}
/* cpu hotplug powerdown */
void hi_pmc_power_down(void)
{
u32 power_state;
power_state = reg_bit_get(PERI_PMC79, 12, 16);
BUG_ON(power_state != 6);
/* disable interrupt wakeup */
reg_bit_set(PERI_PMC79, 5, 6, 0);
/* power off */
reg_bit_set(PERI_PMC79, 4, 5, 0);
reg_bit_set(PERI_PMC79, 4, 5, 1);
}
/* cpuidle powerdown */
void hi_pmc_automode_power_down(void)
{
u32 power_state;
power_state = reg_bit_get(PERI_PMC79, 12, 16);
BUG_ON(power_state != 6);
/* enable interrupt wakeup */
reg_bit_set(PERI_PMC79, 5, 6, 1);
/* power off */
reg_bit_set(PERI_PMC79, 4, 5, 0);
reg_bit_set(PERI_PMC79, 4, 5, 1);
}
EXPORT_SYMBOL(hi_pmc_automode_power_down);
/* enable timeout */
static int hi_pmc_init(void)
{
struct device_node *np;
struct resource res;
int ret = -ENODEV;
np = of_find_compatible_node(NULL, NULL, "hisilicon,pmc");
if (!np)
goto err;
pmc_base = of_iomap(np, 0);
if (!pmc_base) {
pr_err("failed to map pmc base\n");
ret = -ENOMEM;
goto err;
}
ret = of_address_to_resource(np, 0, &res);
if (ret) {
pr_err("failed to get pmc base phys\n");
ret = -ENOMEM;
goto err;
}
pmc_phys_addr = res.start;
err:
return ret;
}
early_initcall(hi_pmc_init);

207
br-ext-chip-hisilicon/board/hi3519v101/kernel/overlay/arch/arm/mach-hisi/pmc_hi3519v101.c
View File

@ -1,207 +0,0 @@
/*
* power mangager control for hisilicon hi3519 soc
*
* Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
* Authors: zengtao@hisilicon.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
#include <linux/io.h>
#include <linux/linkage.h>
#include <linux/bug.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/resource.h>
#include <mach/platform.h>
#include <linux/delay.h>
#define PERI_PMC77 (0x134)
#define PERI_PMC79 (0x13c)
#define PERI_PMC85 (0x154)
static void __iomem *pmc_base;
static u32 __attribute__((used)) pmc_phys_addr;
#define PMC_ADDRESS(reg) (pmc_base + reg)
/* set bitfield of reg from start bit to end - 1 bit */
static void reg_bit_set(u32 reg, u32 start, u32 end, u32 val)
{
u32 regval, mask;
regval = readl((void __iomem *)PMC_ADDRESS(reg));
mask = ((0xffffffff << (32 - start)) >> (32 - start))
| ((0xffffffff >> end) << end);
regval &= mask;
regval |= (val << start);
writel(regval, (void __iomem *)PMC_ADDRESS(reg));
}
/* get bitfield of reg from start bit to end - 1 bit */
static u32 reg_bit_get(u32 reg, u32 start, u32 end)
{
u32 regval;
regval = readl((void __iomem *)PMC_ADDRESS(reg));
regval = (regval << (32 - end)) >> (32 - end);
regval = regval >> start;
return regval;
}
void hi_pmc_power_up_done(void)
{
writel(0, (void __iomem *)PMC_ADDRESS(PERI_PMC85));
writel(1, (void __iomem *)PMC_ADDRESS(PERI_PMC85));
}
/* before power down set ac inactive */
void hi_pmc_set_ac_inactive(void)
{
reg_bit_set(PERI_PMC79, 8, 9, 1);
}
/* after powerup clear ac inactive */
void hi_pmc_clear_ac_inactive(void)
{
reg_bit_set(PERI_PMC79, 8, 9, 0);
}
EXPORT_SYMBOL(hi_pmc_clear_ac_inactive);
/* call from assable context */
asmlinkage void __naked hi_pmc_clear_a17_ac(void)
{
asm volatile("\n"
"adr r2, 1f\n"
"ldmia r2, {r1, r3}\n"
"sub r0, r2, r1\n"
"ldr r2, [r0, r3]\n"
"ldr r0, ="__stringify(PERI_PMC79)"\n"
"add r0, r0, r2\n"
"ldr r1, [r0]\n"
"bic r1, #0x100\n"
"str r1, [r0]\n"
"mov r0, #0\n"
"bx lr\n"
".align 2\n"
"1: .word .\n"
" .word pmc_phys_addr\n"
);
unreachable();
}
static void hi_pmc_config(void)
{
/* enable pmc timeout */
reg_bit_set(PERI_PMC77, 12, 13, 1);
/* enable pmc auto mode */
reg_bit_set(PERI_PMC79, 0, 2, 0);
/* enable irq triger source power on */
reg_bit_set(PERI_PMC79, 7, 8, 1);
}
/* cpu hotplug powerup */
void hi_pmc_power_up(void)
{
u32 power_state;
hi_pmc_config();
/* make sure it powerup state when power up */
power_state = reg_bit_get(PERI_PMC79, 12, 16);
BUG_ON(power_state != 0);
/* disable interrupt wakeup */
reg_bit_set(PERI_PMC79, 5, 6, 0);
/* power on */
reg_bit_set(PERI_PMC79, 3, 4, 0);
reg_bit_set(PERI_PMC79, 3, 4, 1);
}
/* cpu hotplug powerdown */
void hi_pmc_power_down(void)
{
u32 power_state;
power_state = reg_bit_get(PERI_PMC79, 12, 16);
BUG_ON(power_state != 6);
/* disable interrupt wakeup */
reg_bit_set(PERI_PMC79, 5, 6, 0);
/* power off */
reg_bit_set(PERI_PMC79, 4, 5, 0);
reg_bit_set(PERI_PMC79, 4, 5, 1);
}
/* cpuidle powerdown */
void hi_pmc_automode_power_down(void)
{
u32 power_state;
power_state = reg_bit_get(PERI_PMC79, 12, 16);
BUG_ON(power_state != 6);
/* enable interrupt wakeup */
reg_bit_set(PERI_PMC79, 5, 6, 1);
/* power off */
reg_bit_set(PERI_PMC79, 4, 5, 0);
reg_bit_set(PERI_PMC79, 4, 5, 1);
}
EXPORT_SYMBOL(hi_pmc_automode_power_down);
/* enable timeout */
static int hi_pmc_init(void)
{
struct device_node *np;
struct resource res;
int ret = -ENODEV;
np = of_find_compatible_node(NULL, NULL, "hisilicon,pmc");
if (!np)
goto err;
pmc_base = of_iomap(np, 0);
if (!pmc_base) {
pr_err("failed to map pmc base\n");
ret = -ENOMEM;
goto err;
}
ret = of_address_to_resource(np, 0, &res);
if (ret) {
pr_err("failed to get pmc base phys\n");
ret = -ENOMEM;
goto err;
}
pmc_phys_addr = res.start;
err:
return ret;
}
early_initcall(hi_pmc_init);

65
br-ext-chip-hisilicon/board/hi3519v101/kernel/overlay/include/linux/compiler-gcc6.h
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@ -1,65 +0,0 @@
#ifndef __LINUX_COMPILER_H
#error "Please don't include <linux/compiler-gcc5.h> directly, include <linux/compiler.h> instead."
#endif
#define __used __attribute__((__used__))
#define __must_check __attribute__((warn_unused_result))
#define __compiler_offsetof(a, b) __builtin_offsetof(a, b)
/* Mark functions as cold. gcc will assume any path leading to a call
to them will be unlikely. This means a lot of manual unlikely()s
are unnecessary now for any paths leading to the usual suspects
like BUG(), printk(), panic() etc. [but let's keep them for now for
older compilers]
Early snapshots of gcc 4.3 don't support this and we can't detect this
in the preprocessor, but we can live with this because they're unreleased.
Maketime probing would be overkill here.
gcc also has a __attribute__((__hot__)) to move hot functions into
a special section, but I don't see any sense in this right now in
the kernel context */
#define __cold __attribute__((__cold__))
#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)
#ifndef __CHECKER__
# define __compiletime_warning(message) __attribute__((warning(message)))
# define __compiletime_error(message) __attribute__((error(message)))
#endif /* __CHECKER__ */
/*
* Mark a position in code as unreachable. This can be used to
* suppress control flow warnings after asm blocks that transfer
* control elsewhere.
*
* Early snapshots of gcc 4.5 don't support this and we can't detect
* this in the preprocessor, but we can live with this because they're
* unreleased. Really, we need to have autoconf for the kernel.
*/
#define unreachable() __builtin_unreachable()
/* Mark a function definition as prohibited from being cloned. */
#define __noclone __attribute__((__noclone__))
/*
* Tell the optimizer that something else uses this function or variable.
*/
#define __visible __attribute__((externally_visible))
/*
* GCC 'asm goto' miscompiles certain code sequences:
*
* http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670
*
* Work it around via a compiler barrier quirk suggested by Jakub Jelinek.
*
* (asm goto is automatically volatile - the naming reflects this.)
*/
#define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0)
#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP
#define __HAVE_BUILTIN_BSWAP32__
#define __HAVE_BUILTIN_BSWAP64__
#define __HAVE_BUILTIN_BSWAP16__
#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */

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br-ext-chip-rockchip/board/rv11xx/kernel/overlay/arch/arm/boot/dts/rv1109-38x38-v10-spi-nand-imx307.dts
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br-ext-chip-sigmastar/board/infinity3/kernel/overlay/arch/arm/boot/dts/infinity3-QFN64M-openipc.dts
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/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Matthias Brugger <matthias.bgg@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "infinity3.dtsi"
/ {
model = "INFINITY3 MSC000A-S03A-64M";
compatible = "mstar,infinity3";
chosen {
bootargs = "console=ttyS0,115200 panic=20 root=/dev/mtdblock3 rootfstype=squashfs init=/init";
linux,initrd-start = <0x20FE0000>;
linux,initrd-end = <0x21000000>;
};
memory {
reg = <0x20000000 0x04000000>;
};
/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/*
miu_bist_mem: miu_bist_mem@23F00000 {
reg = <0x23F00000 0x00100000>;
no-map ;
status = "okay";
};
*/
cma0 {
compatible = "shared-dma-pool";
reusable;
size = <0x01a00000>;
linux,cma-default;
};
};
soc {
isp: isp {
//clk-pad = <PAD_SPI0_CK>; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads
isp-flag = <0x0>; //Disable DNR and ROT
isp-res = <0x1>; //max image size 2M
};
Mstar-ehci-1 {
power-enable-pad = <PAD_SPI0_CK>;
};
vip: vip {
CMDQ-mode = <0>;
};
cpufreq {
compatible = "mstar,infinity-cpufreq";
vid1-gpio = <PAD_SAR_GPIO3>;
};
};
};

2125
br-ext-chip-sigmastar/board/infinity6b0/kernel/overlay/arch/arm/boot/dts/infinity6b0-ssc009a-s01a-qfn88-tiandy.dts
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1359
br-ext-chip-sigmastar/board/infinity6b0/kernel/overlay/drivers/sstar/gpio/infinity6b0/mhal_pinmux.c
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2973
br-ext-chip-xiongmai/board/xm530/kernel/overlay/kernel/printk.c
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