From 9cb072ca215d8e5d5e7028f595595998f1df8c8e Mon Sep 17 00:00:00 2001 From: Dmitry Ermakov Date: Tue, 15 Mar 2022 11:33:38 +0300 Subject: [PATCH] Add IMX327 config for Hi3519v101 --- .../files/script/load_hisilicon | 46 +++++++- .../files/sensor/config/imx327_i2c_1080p.ini | 106 ++++++++++++++++++ .../files/sensor/config/imx327_spi_1080p.ini | 106 ++++++++++++++++++ 3 files changed, 253 insertions(+), 5 deletions(-) create mode 100644 general/package/hisilicon-osdrv-hi3519v101/files/sensor/config/imx327_i2c_1080p.ini create mode 100644 general/package/hisilicon-osdrv-hi3519v101/files/sensor/config/imx327_spi_1080p.ini diff --git a/general/package/hisilicon-osdrv-hi3519v101/files/script/load_hisilicon b/general/package/hisilicon-osdrv-hi3519v101/files/script/load_hisilicon index f976f66c..ae5550d7 100755 --- a/general/package/hisilicon-osdrv-hi3519v101/files/script/load_hisilicon +++ b/general/package/hisilicon-osdrv-hi3519v101/files/script/load_hisilicon @@ -161,7 +161,32 @@ sysconfig() { devmem 0x12040984 32 0x120 #I2C3_SDA devmem 0x1204096C 32 0x120 #I2C3_SCL } + spi0_4wire_pin_mux() + { + #pinmux + devmem 0x1204018c 32 0x1 #SPI0_SCLK + devmem 0x12040190 32 0x1 #SPI0_SD0 + devmem 0x12040194 32 0x1 #SPI0_SDI + devmem 0x12040198 32 0x1 #SPI0_CSN + + #drive capability... + devmem 0x12040998 32 0x150 #SPI0_SCLK + devmem 0x1204099c 32 0x160 #SPI0_SD0 + devmem 0x120409a0 32 0x160 #SPI0_SDI + devmem 0x120409a4 32 0x160 #SPI0_CSN + } + spi0_3wire_pin_mux() + { + #pinmux + devmem 0x1204018c 32 0x3 #SPI0_3WIRE_CLK + devmem 0x12040190 32 0x3 #SPI0_3WIRE_DATA + devmem 0x12040198 32 0x3 #SPI0_3WIRE_CSN + #drive capability... + devmem 0x12040998 32 0x150 #SPI0_3WIRE_CLK + devmem 0x1204099c 32 0x160 #SPI0_3WIRE_DATA + devmem 0x120409a4 32 0x160 #SPI0_3WIRE_CSN + } #spi1 -> vi spi1_pin_mux() { #pinmux @@ -400,7 +425,7 @@ insert_sns() { devmem 0x12010054 32 0x0004041 devmem 0x12010040 32 0x11 # sensor0 clk_en, 72MHz spi0_4wire_pin_mux - insmod extdrv/hi_ssp_sony.ko + insmod hi_ssp_sony.ko ;; imx265) tmp=0x18 @@ -410,7 +435,7 @@ insert_sns() { devmem 0x12010054 32 0x0004041 devmem 0x12010040 32 0x18 # sensor0 clk_en, 37.125MHz spi0_4wire_pin_mux - insmod extdrv/hi_ssp_sony.ko + insmod hi_ssp_sony.ko ;; imx377) tmp=0x14 @@ -429,7 +454,7 @@ insert_sns() { devmem 0x12010054 32 0x0004041 devmem 0x12010040 32 0x11 # sensor0 clk_en, 72MHz spi0_4wire_pin_mux - insmod extdrv/hi_ssp_sony.ko + insmod hi_ssp_sony.ko ;; imx290) tmp=0x18 @@ -440,6 +465,17 @@ insert_sns() { devmem 0x12010040 32 0x18 # sensor0 clk_en, 37.125MHz i2c0_pin_mux ;; + imx327_spi) + tmp=0x18 + # SDK config: IVE:396M, GDC:475M, VGS:500M, VEDU:600M, VPSS:300M + #imx290:viu0:340M,isp0:214M, viu1:340M,isp1:214M + devmem 0x1201004c 32 0x00094c24 + devmem 0x12010054 32 0x0004 + # devmem 0x12010040 32 0x11 # sensor0 clk_en, 72MHz + devmem 0x12010040 32 0x18 # sensor0 clk_en, 37.125MHz + spi0_4wire_pin_mux + insmod hi_ssp_sony.ko + ;; imx327) tmp=0x18 # SDK config: IVE:396M, GDC:475M, VGS:500M, VEDU:600M, VPSS:300M @@ -466,7 +502,7 @@ insert_sns() { devmem 0x12010054 32 0x0004041 devmem 0x12010040 32 0x12 # sensor0 clk_en, 54MHz spi0_3wire_pin_mux - insmod extdrv/hi_ssp_3wire.ko + insmod hi_ssp_3wire.ko ;; imx385_lvds) tmp=0x18 @@ -508,7 +544,7 @@ insert_sns() { devmem 0x12010040 32 0x18 # sensor0 clk_en, 37.125MHz i2c0_pin_mux #spi0_4wire_pin_mux; - #insmod extdrv/hi_ssp_sony.ko; + #insmod hi_ssp_sony.ko; ;; os08a | os08a10) tmp=0x14 diff --git a/general/package/hisilicon-osdrv-hi3519v101/files/sensor/config/imx327_i2c_1080p.ini b/general/package/hisilicon-osdrv-hi3519v101/files/sensor/config/imx327_i2c_1080p.ini new file mode 100644 index 00000000..ff848785 --- /dev/null +++ b/general/package/hisilicon-osdrv-hi3519v101/files/sensor/config/imx327_i2c_1080p.ini @@ -0,0 +1,106 @@ +[sensor] +Sensor_type=stSnsObj +Mode=WDR_MODE_NONE +DllFile=libsns_imx327.so + +[mode] +input_mode=INPUT_MODE_MIPI +dev_attr=0 + +[mipi] +data_type=RAW_DATA_10BIT +lane_id = 0|1|2|3|-1|-1|-1|-1| ;lane_id: -1 - disable + +[isp_image] +Isp_x =0 +Isp_y =0 +Isp_W =1920 +Isp_H =1080 +Isp_FrameRate=25 +Isp_Bayer=BAYER_RGGB + +[vi_dev] +Input_mod=VI_MODE_MIPI +Work_mod =0 ;VI_WORK_MODE_1Multiplex = 0 + ;VI_WORK_MODE_2Multiplex, + ;VI_WORK_MODE_4Multiplex +Combine_mode =0 ;Y/C composite or separation mode + ;VI_COMBINE_COMPOSITE = 0 /*Composite mode */ + ;VI_COMBINE_SEPARATE, /*Separate mode */ +Comp_mode =0 ;Component mode (single-component or dual-component) + ;VI_COMP_MODE_SINGLE = 0, /*single component mode */ + ;VI_COMP_MODE_DOUBLE = 1, /*double component mode */ +Clock_edge =1 ;Clock edge mode (sampling on the rising or falling edge) + ;VI_CLK_EDGE_SINGLE_UP=0, /*rising edge */ + ;VI_CLK_EDGE_SINGLE_DOWN, /*falling edge */ +Mask_num =2 ;Component mask +Mask_0 =0xFFF00000 +Mask_1 =0x0 +Scan_mode = 1;VI_SCAN_INTERLACED = 0 + ;VI_SCAN_PROGRESSIVE, +Data_seq =2 ;data sequence (ONLY for YUV format) + ;----2th component U/V sequence in bt1120 + ; VI_INPUT_DATA_VUVU = 0, + ; VI_INPUT_DATA_UVUV, + ;----input sequence for yuv + ; VI_INPUT_DATA_UYVY = 0, + ; VI_INPUT_DATA_VYUY, + ; VI_INPUT_DATA_YUYV, + ; VI_INPUT_DATA_YVYU + +Vsync =1 ; vertical synchronization signal + ;VI_VSYNC_FIELD = 0, + ;VI_VSYNC_PULSE, +VsyncNeg=1 ;Polarity of the vertical synchronization signal + ;VI_VSYNC_NEG_HIGH = 0, + ;VI_VSYNC_NEG_LOW /*if VIU_VSYNC_E +Hsync =0 ;Attribute of the horizontal synchronization signal + ;VI_HSYNC_VALID_SINGNAL = 0, + ;VI_HSYNC_PULSE, +HsyncNeg =0 ;Polarity of the horizontal synchronization signal + ;VI_HSYNC_NEG_HIGH = 0, + ;VI_HSYNC_NEG_LOW +VsyncValid =1 ;Attribute of the valid vertical synchronization signal + ;VI_VSYNC_NORM_PULSE = 0, + ;VI_VSYNC_VALID_SINGAL, +VsyncValidNeg =0;Polarity of the valid vertical synchronization signal + ;VI_VSYNC_VALID_NEG_HIGH = 0, + ;VI_VSYNC_VALID_NEG_LOW +Timingblank_HsyncHfb =0 ;Horizontal front blanking width +Timingblank_HsyncAct =1920 ;Horizontal effetive width +Timingblank_HsyncHbb =0 ;Horizontal back blanking width +Timingblank_VsyncVfb =0 ;Vertical front blanking height +Timingblank_VsyncVact =1080 ;Vertical effetive width +Timingblank_VsyncVbb=0 ;Vertical back blanking height +Timingblank_VsyncVbfb =0 ;Even-field vertical front blanking height(interlace, invalid progressive) +Timingblank_VsyncVbact=0 ;Even-field vertical effetive width(interlace, invalid progressive) +Timingblank_VsyncVbbb =0 ;Even-field vertical back blanking height(interlace, invalid progressive) +FixCode=0 +FieldPolar=0 +DataPath=1 +InputDataType=1 ;VI_DATA_TYPE_YUV = 0,VI_DATA_TYPE_RGB = 1, +DataRev =FALSE ;Data reverse. FALSE = 0; TRUE = 1 +DevRect_x=4 +DevRect_y=4 +DevRect_w=1920 +DevRect_h=1080 + +[vi_chn] +CapRect_X =0 +CapRect_Y =0 +CapRect_Width=1920 +CapRect_Height=1080 +DestSize_Width=1920 +DestSize_Height=1080 +CapSel =2 ;Frame/field select. ONLY used in interlaced mode + ;VI_CAPSEL_TOP = 0, /* top field */ + ;VI_CAPSEL_BOTTOM, /* bottom field */ + ;VI_CAPSEL_BOTH, /* top and bottom field */ + +PixFormat =23;PIXEL_FORMAT_YUV_SEMIPLANAR_422 = 22 + ;PIXEL_FORMAT_YUV_SEMIPLANAR_420 = 23 ...etc +CompressMode =0 ;COMPRESS_MODE_NONE = 0 + ;COMPRESS_MODE_SEG =1 ...etc + +SrcFrameRate=-1 ;Source frame rate. -1: not controll +FrameRate =-1 ;Target frame rate. -1: not controll diff --git a/general/package/hisilicon-osdrv-hi3519v101/files/sensor/config/imx327_spi_1080p.ini b/general/package/hisilicon-osdrv-hi3519v101/files/sensor/config/imx327_spi_1080p.ini new file mode 100644 index 00000000..e72adb1f --- /dev/null +++ b/general/package/hisilicon-osdrv-hi3519v101/files/sensor/config/imx327_spi_1080p.ini @@ -0,0 +1,106 @@ +[sensor] +Sensor_type=stSnsObj +Mode=WDR_MODE_NONE +DllFile=libsns_imx327_spi.so + +[mode] +input_mode=INPUT_MODE_MIPI +dev_attr=0 + +[mipi] +data_type=RAW_DATA_10BIT +lane_id = 0|1|2|3|-1|-1|-1|-1| ;lane_id: -1 - disable + +[isp_image] +Isp_x =0 +Isp_y =0 +Isp_W =1920 +Isp_H =1080 +Isp_FrameRate=25 +Isp_Bayer=BAYER_RGGB + +[vi_dev] +Input_mod=VI_MODE_MIPI +Work_mod =0 ;VI_WORK_MODE_1Multiplex = 0 + ;VI_WORK_MODE_2Multiplex, + ;VI_WORK_MODE_4Multiplex +Combine_mode =0 ;Y/C composite or separation mode + ;VI_COMBINE_COMPOSITE = 0 /*Composite mode */ + ;VI_COMBINE_SEPARATE, /*Separate mode */ +Comp_mode =0 ;Component mode (single-component or dual-component) + ;VI_COMP_MODE_SINGLE = 0, /*single component mode */ + ;VI_COMP_MODE_DOUBLE = 1, /*double component mode */ +Clock_edge =1 ;Clock edge mode (sampling on the rising or falling edge) + ;VI_CLK_EDGE_SINGLE_UP=0, /*rising edge */ + ;VI_CLK_EDGE_SINGLE_DOWN, /*falling edge */ +Mask_num =2 ;Component mask +Mask_0 =0xFFF00000 +Mask_1 =0x0 +Scan_mode = 1;VI_SCAN_INTERLACED = 0 + ;VI_SCAN_PROGRESSIVE, +Data_seq =2 ;data sequence (ONLY for YUV format) + ;----2th component U/V sequence in bt1120 + ; VI_INPUT_DATA_VUVU = 0, + ; VI_INPUT_DATA_UVUV, + ;----input sequence for yuv + ; VI_INPUT_DATA_UYVY = 0, + ; VI_INPUT_DATA_VYUY, + ; VI_INPUT_DATA_YUYV, + ; VI_INPUT_DATA_YVYU + +Vsync =1 ; vertical synchronization signal + ;VI_VSYNC_FIELD = 0, + ;VI_VSYNC_PULSE, +VsyncNeg=1 ;Polarity of the vertical synchronization signal + ;VI_VSYNC_NEG_HIGH = 0, + ;VI_VSYNC_NEG_LOW /*if VIU_VSYNC_E +Hsync =0 ;Attribute of the horizontal synchronization signal + ;VI_HSYNC_VALID_SINGNAL = 0, + ;VI_HSYNC_PULSE, +HsyncNeg =0 ;Polarity of the horizontal synchronization signal + ;VI_HSYNC_NEG_HIGH = 0, + ;VI_HSYNC_NEG_LOW +VsyncValid =1 ;Attribute of the valid vertical synchronization signal + ;VI_VSYNC_NORM_PULSE = 0, + ;VI_VSYNC_VALID_SINGAL, +VsyncValidNeg =0;Polarity of the valid vertical synchronization signal + ;VI_VSYNC_VALID_NEG_HIGH = 0, + ;VI_VSYNC_VALID_NEG_LOW +Timingblank_HsyncHfb =0 ;Horizontal front blanking width +Timingblank_HsyncAct =1920 ;Horizontal effetive width +Timingblank_HsyncHbb =0 ;Horizontal back blanking width +Timingblank_VsyncVfb =0 ;Vertical front blanking height +Timingblank_VsyncVact =1080 ;Vertical effetive width +Timingblank_VsyncVbb=0 ;Vertical back blanking height +Timingblank_VsyncVbfb =0 ;Even-field vertical front blanking height(interlace, invalid progressive) +Timingblank_VsyncVbact=0 ;Even-field vertical effetive width(interlace, invalid progressive) +Timingblank_VsyncVbbb =0 ;Even-field vertical back blanking height(interlace, invalid progressive) +FixCode=0 +FieldPolar=0 +DataPath=1 +InputDataType=1 ;VI_DATA_TYPE_YUV = 0,VI_DATA_TYPE_RGB = 1, +DataRev =FALSE ;Data reverse. FALSE = 0; TRUE = 1 +DevRect_x=4 +DevRect_y=4 +DevRect_w=1920 +DevRect_h=1080 + +[vi_chn] +CapRect_X =0 +CapRect_Y =0 +CapRect_Width=1920 +CapRect_Height=1080 +DestSize_Width=1920 +DestSize_Height=1080 +CapSel =2 ;Frame/field select. ONLY used in interlaced mode + ;VI_CAPSEL_TOP = 0, /* top field */ + ;VI_CAPSEL_BOTTOM, /* bottom field */ + ;VI_CAPSEL_BOTH, /* top and bottom field */ + +PixFormat =23;PIXEL_FORMAT_YUV_SEMIPLANAR_422 = 22 + ;PIXEL_FORMAT_YUV_SEMIPLANAR_420 = 23 ...etc +CompressMode =0 ;COMPRESS_MODE_NONE = 0 + ;COMPRESS_MODE_SEG =1 ...etc + +SrcFrameRate=-1 ;Source frame rate. -1: not controll +FrameRate =-1 ;Target frame rate. -1: not controll