From 988ebe7585ced18ee01c57b113490d38571bc43c Mon Sep 17 00:00:00 2001 From: Dmitry Ermakov Date: Fri, 24 Jun 2022 23:39:33 +0300 Subject: [PATCH] [RV11xx] Fix kernel configs, add DTS for longse RV1109+IMX307 board --- .../dts/rv1109-38x38-v10-spi-nand-imx307.dts | 3759 +++++++++++++++++ .../board/rv11xx/kernel/rv1126.generic.config | 40 +- .../unknown_unknown_rv1109_openipc_defconfig | 3 +- .../unknown_unknown_rv1126_openipc_defconfig | 3 +- 4 files changed, 3783 insertions(+), 22 deletions(-) create mode 100644 br-ext-chip-rockchip/board/rv11xx/kernel/overlay/arch/arm/boot/dts/rv1109-38x38-v10-spi-nand-imx307.dts diff --git a/br-ext-chip-rockchip/board/rv11xx/kernel/overlay/arch/arm/boot/dts/rv1109-38x38-v10-spi-nand-imx307.dts b/br-ext-chip-rockchip/board/rv11xx/kernel/overlay/arch/arm/boot/dts/rv1109-38x38-v10-spi-nand-imx307.dts new file mode 100644 index 00000000..fd76e989 --- /dev/null +++ b/br-ext-chip-rockchip/board/rv11xx/kernel/overlay/arch/arm/boot/dts/rv1109-38x38-v10-spi-nand-imx307.dts @@ -0,0 +1,3759 @@ +//Longse RV1109+IMX307 + +/dts-v1/; +/ { + #address-cells = <0x00000001>; + #size-cells = <0x00000001>; + compatible = "rockchip,rv1109-38x38-v10-spi-nand-imx307", "rockchip,rv1109"; + interrupt-parent = <0x00000001>; + model = "Rockchip RV1109 38x38 V10 SPI NAND IMX307 DDR3 Board"; + ddr_timing { + compatible = "rockchip,ddr-timing"; + ddr2_speed_bin = <0x00000000>; + ddr3_speed_bin = <0x00000015>; + ddr4_speed_bin = <0x0000000c>; + pd_idle = <0x0000000d>; + sr_idle = <0x0000005d>; + sr_mc_gate_idle = <0x00000000>; + srpd_lite_idle = <0x00000000>; + standby_idle = <0x00000000>; + auto_pd_dis_freq = <0x0000042a>; + auto_sr_dis_freq = <0x00000320>; + ddr2_dll_dis_freq = <0x0000012c>; + ddr3_dll_dis_freq = <0x0000012c>; + ddr4_dll_dis_freq = <0x00000271>; + phy_dll_dis_freq = <0x00000190>; + ddr2_odt_dis_freq = <0x00000064>; + phy_ddr2_odt_dis_freq = <0x00000064>; + ddr2_drv = <0x00000002>; + ddr2_odt = <0x00000040>; + phy_ddr2_ca_drv = <0x00000015>; + phy_ddr2_ck_drv = <0x00000013>; + phy_ddr2_dq_drv = <0x00000015>; + phy_ddr2_odt = <0x00000002>; + ddr3_odt_dis_freq = <0x0000014d>; + phy_ddr3_odt_dis_freq = <0x0000014d>; + ddr3_drv = <0x00000002>; + ddr3_odt = <0x00000040>; + phy_ddr3_ca_drv = <0x00000013>; + phy_ddr3_ck_drv = <0x00000014>; + phy_ddr3_dq_drv = <0x00000017>; + phy_ddr3_odt = <0x00000004>; + phy_lpddr2_odt_dis_freq = <0x0000014d>; + lpddr2_drv = <0x00000002>; + phy_lpddr2_ca_drv = <0x00000016>; + phy_lpddr2_ck_drv = <0x00000014>; + phy_lpddr2_dq_drv = <0x00000016>; + phy_lpddr2_odt = <0x00000000>; + lpddr3_odt_dis_freq = <0x0000014d>; + phy_lpddr3_odt_dis_freq = <0x0000014d>; + lpddr3_drv = <0x00000001>; + lpddr3_odt = <0x00000002>; + phy_lpddr3_ca_drv = <0x00000015>; + phy_lpddr3_ck_drv = <0x00000016>; + phy_lpddr3_dq_drv = <0x00000019>; + phy_lpddr3_odt = <0x00000004>; + lpddr4_odt_dis_freq = <0x0000014d>; + phy_lpddr4_odt_dis_freq = <0x0000014d>; + lpddr4_drv = <0x00000030>; + lpddr4_dq_odt = <0x00000001>; + lpddr4_ca_odt = <0x00000000>; + phy_lpddr4_ca_drv = <0x00000013>; + phy_lpddr4_ck_cs_drv = <0x00000015>; + phy_lpddr4_dq_drv = <0x00000015>; + phy_lpddr4_odt = <0x00000012>; + ddr4_odt_dis_freq = <0x00000271>; + phy_ddr4_odt_dis_freq = <0x00000271>; + ddr4_drv = <0x00000000>; + ddr4_odt = <0x00000200>; + phy_ddr4_ca_drv = <0x00000013>; + phy_ddr4_ck_drv = <0x00000015>; + phy_ddr4_dq_drv = <0x00000015>; + phy_ddr4_odt = <0x00000004>; + a0_a3_a3_cke1-a_de-skew = <0x00000007>; + a1_ba1_null_cke0-b_de-skew = <0x00000007>; + a2_a9_a9_a4-a_de-skew = <0x00000007>; + a3_a15_null_a5-b_de-skew = <0x00000007>; + a4_a6_a6_ck-a_de-skew = <0x00000007>; + a5_a12_null_odt0-b_de-skew = <0x00000007>; + a6_ba2_null_a0-a_de-skew = <0x00000007>; + a7_a4_a4_odt0-a_de-skew = <0x00000007>; + a8_a1_a1_cke0-a_de-skew = <0x00000007>; + a9_a5_a5_a5-a_de-skew = <0x00000007>; + a10_a8_a8_clkb-a_de-skew = <0x00000007>; + a11_a7_a7_ca2-a_de-skew = <0x00000007>; + a12_rasn_null_ca1-a_de-skew = <0x00000007>; + a13_a13_null_ca3-a_de-skew = <0x00000007>; + a14_a14_null_csb1-b_de-skew = <0x00000007>; + a15_a10_null_ca0-b_de-skew = <0x00000007>; + a16_a11_null_csb0-b_de-skew = <0x00000007>; + a17_null_null_null_de-skew = <0x00000007>; + ba0_csb1_csb1_csb0-a_de-skew = <0x00000007>; + ba1_wen_null_cke1-b_de-skew = <0x00000007>; + bg0_odt1_odt1_csb1-a_de-skew = <0x00000007>; + bg1_a2_a2_odt1-a_de-skew = <0x00000007>; + cke0_casb_null_ca1-b_de-skew = <0x00000007>; + ck_ck_ck_ck-b_de-skew = <0x00000007>; + ckb_ckb_ckb_ckb-b_de-skew = <0x00000007>; + csb0_odt0_odt0_ca2-b_de-skew = <0x00000007>; + odt0_csb0_csb0_ca4-b_de-skew = <0x00000007>; + resetn_resetn_null-resetn_de-skew = <0x00000007>; + actn_cke_cke_ca3-b_de-skew = <0x00000007>; + cke1_null_null_null_de-skew = <0x00000007>; + csb1_ba0_null_null_de-skew = <0x00000007>; + odt1_a0_a0_odt1-b_de-skew = <0x00000007>; + cs0_dm0_rx_de-skew = <0x00000007>; + cs0_dq0_rx_de-skew = <0x00000007>; + cs0_dq1_rx_de-skew = <0x00000007>; + cs0_dq2_rx_de-skew = <0x00000007>; + cs0_dq3_rx_de-skew = <0x00000007>; + cs0_dq4_rx_de-skew = <0x00000007>; + cs0_dq5_rx_de-skew = <0x00000007>; + cs0_dq6_rx_de-skew = <0x00000007>; + cs0_dq7_rx_de-skew = <0x00000007>; + cs0_dqs0p_rx_de-skew = <0x0000000e>; + cs0_dqs0n_rx_de-skew = <0x0000000e>; + cs0_dm1_rx_de-skew = <0x00000007>; + cs0_dq8_rx_de-skew = <0x00000007>; + cs0_dq9_rx_de-skew = <0x00000007>; + cs0_dq10_rx_de-skew = <0x00000007>; + cs0_dq11_rx_de-skew = <0x00000007>; + cs0_dq12_rx_de-skew = <0x00000007>; + cs0_dq13_rx_de-skew = <0x00000007>; + cs0_dq14_rx_de-skew = <0x00000007>; + cs0_dq15_rx_de-skew = <0x00000007>; + cs0_dqs1p_rx_de-skew = <0x0000000e>; + cs0_dqs1n_rx_de-skew = <0x0000000e>; + cs0_dm0_tx_de-skew = <0x00000007>; + cs0_dq0_tx_de-skew = <0x00000007>; + cs0_dq1_tx_de-skew = <0x00000007>; + cs0_dq2_tx_de-skew = <0x00000007>; + cs0_dq3_tx_de-skew = <0x00000007>; + cs0_dq4_tx_de-skew = <0x00000007>; + cs0_dq5_tx_de-skew = <0x00000007>; + cs0_dq6_tx_de-skew = <0x00000007>; + cs0_dq7_tx_de-skew = <0x00000007>; + cs0_dqs0p_tx_de-skew = <0x00000007>; + cs0_dqs0n_tx_de-skew = <0x00000007>; + cs0_dm1_tx_de-skew = <0x00000007>; + cs0_dq8_tx_de-skew = <0x00000007>; + cs0_dq9_tx_de-skew = <0x00000007>; + cs0_dq10_tx_de-skew = <0x00000007>; + cs0_dq11_tx_de-skew = <0x00000007>; + cs0_dq12_tx_de-skew = <0x00000007>; + cs0_dq13_tx_de-skew = <0x00000007>; + cs0_dq14_tx_de-skew = <0x00000007>; + cs0_dq15_tx_de-skew = <0x00000007>; + cs0_dqs1p_tx_de-skew = <0x00000007>; + cs0_dqs1n_tx_de-skew = <0x00000007>; + cs0_dm2_rx_de-skew = <0x00000007>; + cs0_dq16_rx_de-skew = <0x00000007>; + cs0_dq17_rx_de-skew = <0x00000007>; + cs0_dq18_rx_de-skew = <0x00000007>; + cs0_dq19_rx_de-skew = <0x00000007>; + cs0_dq20_rx_de-skew = <0x00000007>; + cs0_dq21_rx_de-skew = <0x00000007>; + cs0_dq22_rx_de-skew = <0x00000007>; + cs0_dq23_rx_de-skew = <0x00000007>; + cs0_dqs2p_rx_de-skew = <0x0000000e>; + cs0_dqs2n_rx_de-skew = <0x0000000e>; + cs0_dm3_rx_de-skew = <0x00000007>; + cs0_dq24_rx_de-skew = <0x00000007>; + cs0_dq25_rx_de-skew = <0x00000007>; + cs0_dq26_rx_de-skew = <0x00000007>; + cs0_dq27_rx_de-skew = <0x00000007>; + cs0_dq28_rx_de-skew = <0x00000007>; + cs0_dq29_rx_de-skew = <0x00000007>; + cs0_dq30_rx_de-skew = <0x00000007>; + cs0_dq31_rx_de-skew = <0x00000007>; + cs0_dqs3p_rx_de-skew = <0x0000000e>; + cs0_dqs3n_rx_de-skew = <0x0000000e>; + cs0_dm2_tx_de-skew = <0x00000007>; + cs0_dq16_tx_de-skew = <0x00000007>; + cs0_dq17_tx_de-skew = <0x00000007>; + cs0_dq18_tx_de-skew = <0x00000007>; + cs0_dq19_tx_de-skew = <0x00000007>; + cs0_dq20_tx_de-skew = <0x00000007>; + cs0_dq21_tx_de-skew = <0x00000007>; + cs0_dq22_tx_de-skew = <0x00000007>; + cs0_dq23_tx_de-skew = <0x00000007>; + cs0_dqs2p_tx_de-skew = <0x00000007>; + cs0_dqs2n_tx_de-skew = <0x00000007>; + cs0_dm3_tx_de-skew = <0x00000007>; + cs0_dq24_tx_de-skew = <0x00000007>; + cs0_dq25_tx_de-skew = <0x00000007>; + cs0_dq26_tx_de-skew = <0x00000007>; + cs0_dq27_tx_de-skew = <0x00000007>; + cs0_dq28_tx_de-skew = <0x00000007>; + cs0_dq29_tx_de-skew = <0x00000007>; + cs0_dq30_tx_de-skew = <0x00000007>; + cs0_dq31_tx_de-skew = <0x00000007>; + cs0_dqs3p_tx_de-skew = <0x00000007>; + cs0_dqs3n_tx_de-skew = <0x00000007>; + cs1_dm0_rx_de-skew = <0x00000007>; + cs1_dq0_rx_de-skew = <0x00000007>; + cs1_dq1_rx_de-skew = <0x00000007>; + cs1_dq2_rx_de-skew = <0x00000007>; + cs1_dq3_rx_de-skew = <0x00000007>; + cs1_dq4_rx_de-skew = <0x00000007>; + cs1_dq5_rx_de-skew = <0x00000007>; + cs1_dq6_rx_de-skew = <0x00000007>; + cs1_dq7_rx_de-skew = <0x00000007>; + cs1_dqs0p_rx_de-skew = <0x0000000e>; + cs1_dqs0n_rx_de-skew = <0x0000000e>; + cs1_dm1_rx_de-skew = <0x00000007>; + cs1_dq8_rx_de-skew = <0x00000007>; + cs1_dq9_rx_de-skew = <0x00000007>; + cs1_dq10_rx_de-skew = <0x00000007>; + cs1_dq11_rx_de-skew = <0x00000007>; + cs1_dq12_rx_de-skew = <0x00000007>; + cs1_dq13_rx_de-skew = <0x00000007>; + cs1_dq14_rx_de-skew = <0x00000007>; + cs1_dq15_rx_de-skew = <0x00000007>; + cs1_dqs1p_rx_de-skew = <0x0000000e>; + cs1_dqs1n_rx_de-skew = <0x0000000e>; + cs1_dm0_tx_de-skew = <0x00000007>; + cs1_dq0_tx_de-skew = <0x00000007>; + cs1_dq1_tx_de-skew = <0x00000007>; + cs1_dq2_tx_de-skew = <0x00000007>; + cs1_dq3_tx_de-skew = <0x00000007>; + cs1_dq4_tx_de-skew = <0x00000007>; + cs1_dq5_tx_de-skew = <0x00000007>; + cs1_dq6_tx_de-skew = <0x00000007>; + cs1_dq7_tx_de-skew = <0x00000007>; + cs1_dqs0p_tx_de-skew = <0x00000007>; + cs1_dqs0n_tx_de-skew = <0x00000007>; + cs1_dm1_tx_de-skew = <0x00000007>; + cs1_dq8_tx_de-skew = <0x00000007>; + cs1_dq9_tx_de-skew = <0x00000007>; + cs1_dq10_tx_de-skew = <0x00000007>; + cs1_dq11_tx_de-skew = <0x00000007>; + cs1_dq12_tx_de-skew = <0x00000007>; + cs1_dq13_tx_de-skew = <0x00000007>; + cs1_dq14_tx_de-skew = <0x00000007>; + cs1_dq15_tx_de-skew = <0x00000007>; + cs1_dqs1p_tx_de-skew = <0x00000007>; + cs1_dqs1n_tx_de-skew = <0x00000007>; + cs1_dm2_rx_de-skew = <0x00000007>; + cs1_dq16_rx_de-skew = <0x00000007>; + cs1_dq17_rx_de-skew = <0x00000007>; + cs1_dq18_rx_de-skew = <0x00000007>; + cs1_dq19_rx_de-skew = <0x00000007>; + cs1_dq20_rx_de-skew = <0x00000007>; + cs1_dq21_rx_de-skew = <0x00000007>; + cs1_dq22_rx_de-skew = <0x00000007>; + cs1_dq23_rx_de-skew = <0x00000007>; + cs1_dqs2p_rx_de-skew = <0x0000000e>; + cs1_dqs2n_rx_de-skew = <0x0000000e>; + cs1_dm3_rx_de-skew = <0x00000007>; + cs1_dq24_rx_de-skew = <0x00000007>; + cs1_dq25_rx_de-skew = <0x00000007>; + cs1_dq26_rx_de-skew = <0x00000007>; + cs1_dq27_rx_de-skew = <0x00000007>; + cs1_dq28_rx_de-skew = <0x00000007>; + cs1_dq29_rx_de-skew = <0x00000007>; + cs1_dq30_rx_de-skew = <0x00000007>; + cs1_dq31_rx_de-skew = <0x00000007>; + cs1_dqs3p_rx_de-skew = <0x0000000e>; + cs1_dqs3n_rx_de-skew = <0x0000000e>; + cs1_dm2_tx_de-skew = <0x00000007>; + cs1_dq16_tx_de-skew = <0x00000007>; + cs1_dq17_tx_de-skew = <0x00000007>; + cs1_dq18_tx_de-skew = <0x00000007>; + cs1_dq19_tx_de-skew = <0x00000007>; + cs1_dq20_tx_de-skew = <0x00000007>; + cs1_dq21_tx_de-skew = <0x00000007>; + cs1_dq22_tx_de-skew = <0x00000007>; + cs1_dq23_tx_de-skew = <0x00000007>; + cs1_dqs2p_tx_de-skew = <0x00000007>; + cs1_dqs2n_tx_de-skew = <0x00000007>; + cs1_dm3_tx_de-skew = <0x00000007>; + cs1_dq24_tx_de-skew = <0x00000007>; + cs1_dq25_tx_de-skew = <0x00000007>; + cs1_dq26_tx_de-skew = <0x00000007>; + cs1_dq27_tx_de-skew = <0x00000007>; + cs1_dq28_tx_de-skew = <0x00000007>; + cs1_dq29_tx_de-skew = <0x00000007>; + cs1_dq30_tx_de-skew = <0x00000007>; + cs1_dq31_tx_de-skew = <0x00000007>; + cs1_dqs3p_tx_de-skew = <0x00000007>; + cs1_dqs3n_tx_de-skew = <0x00000007>; + phandle = <0x0000009a>; + }; + aliases { + i2c0 = "/i2c@ff3f0000"; + i2c1 = "/i2c@ff510000"; + i2c2 = "/i2c@ff400000"; + i2c3 = "/i2c@ff520000"; + i2c4 = "/i2c@ff530000"; + i2c5 = "/i2c@ff540000"; + mmc0 = "/dwmmc@ffc50000"; + mmc1 = "/dwmmc@ffc70000"; + mmc2 = "/dwmmc@ffc60000"; + serial0 = "/serial@ff560000"; + serial1 = "/serial@ff410000"; + serial2 = "/serial@ff570000"; + serial3 = "/serial@ff580000"; + serial4 = "/serial@ff590000"; + serial5 = "/serial@ff5a0000"; + spi0 = "/spi@ff450000"; + spi1 = "/spi@ff5b0000"; + dphy0 = "/csi-dphy@ff4b0000"; + dphy1 = "/csi-dphy@ff4b8000"; + }; + cpus { + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x00000f00>; + enable-method = "psci"; + clocks = <0x00000002 0x00000005>; + operating-points-v2 = <0x00000003>; + dynamic-power-coefficient = <0x0000003c>; + #cooling-cells = <0x00000002>; + cpu-idle-states = <0x00000004>; + cpu-supply = <0x00000005>; + phandle = <0x0000000a>; + }; + cpu@f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x00000f01>; + enable-method = "psci"; + clocks = <0x00000002 0x00000005>; + operating-points-v2 = <0x00000003>; + dynamic-power-coefficient = <0x0000003c>; + cpu-idle-states = <0x00000004>; + phandle = <0x0000000b>; + }; + cpu@f02 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x00000f02>; + enable-method = "psci"; + clocks = <0x00000002 0x00000005>; + operating-points-v2 = <0x00000003>; + dynamic-power-coefficient = <0x0000003c>; + cpu-idle-states = <0x00000004>; + phandle = <0x0000000c>; + }; + cpu@f03 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x00000f03>; + enable-method = "psci"; + clocks = <0x00000002 0x00000005>; + operating-points-v2 = <0x00000003>; + dynamic-power-coefficient = <0x0000003c>; + cpu-idle-states = <0x00000004>; + phandle = <0x0000000d>; + }; + idle-states { + entry-method = "psci"; + cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x00010000>; + entry-latency-us = <0x00000078>; + exit-latency-us = <0x000000fa>; + min-residency-us = <0x00000384>; + phandle = <0x00000004>; + }; + }; + }; + cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + nvmem-cells = <0x00000006 0x00000007>; + nvmem-cell-names = "leakage", "performance"; + rockchip,reboot-freq = <0x000c7380>; + rockchip,temp-freq-table = <0x000186a0 0x0013c680>; + clocks = <0x00000002 0x00000001>; + rockchip,bin-scaling-sel = <0x00000000 0x00000005 0x00000001 0x00000009>; + rockchip,bin-voltage-sel = <0x00000001 0x00000000>; + rockchip,pvtm-voltage-sel = <0x00000000 0x00018894 0x00000001 0x00018895 0x00019834 0x00000002 0x00019835 0x0001abbc 0x00000003 0x0001abbd 0x000f423f 0x00000004>; + rockchip,pvtm-freq = <0x000639c0>; + rockchip,pvtm-volt = <0x000c3500>; + rockchip,pvtm-ch = <0x00000000 0x00000000>; + rockchip,pvtm-sample-time = <0x000003e8>; + rockchip,pvtm-number = <0x0000000a>; + rockchip,pvtm-error = <0x000003e8>; + rockchip,pvtm-ref-temp = <0x00000025>; + rockchip,pvtm-temp-prop = <0xffffffd8 0x0000000d>; + rockchip,pvtm-thermal-zone = "cpu-thermal"; + phandle = <0x00000003>; + opp-408000000 { + opp-hz = <0x00000000 0x18519600>; + opp-microvolt = <0x000b1008 0x000b1008 0x000f4240>; + opp-microvolt-L0 = <0x000b1008 0x000b1008 0x000f4240>; + clock-latency-ns = <0x00009c40>; + }; + opp-600000000 { + opp-hz = <0x00000000 0x23c34600>; + opp-microvolt = <0x000b1008 0x000b1008 0x000f4240>; + opp-microvolt-L0 = <0x000b1008 0x000b1008 0x000f4240>; + clock-latency-ns = <0x00009c40>; + }; + opp-816000000 { + opp-hz = <0x00000000 0x30a32c00>; + opp-microvolt = <0x000b1008 0x000b1008 0x000f4240>; + opp-microvolt-L0 = <0x000b71b0 0x000b71b0 0x000f4240>; + clock-latency-ns = <0x00009c40>; + opp-suspend; + }; + opp-1008000000 { + opp-hz = <0x00000000 0x3c14dc00>; + opp-microvolt = <0x000bd358 0x000bd358 0x000f4240>; + opp-microvolt-L0 = <0x000c3500 0x000c3500 0x000f4240>; + opp-microvolt-L1 = <0x000bd358 0x000bd358 0x000f4240>; + opp-microvolt-L2 = <0x000bd358 0x000bd358 0x000f4240>; + opp-microvolt-L3 = <0x000b71b0 0x000b71b0 0x000f4240>; + opp-microvolt-L4 = <0x000b1008 0x000b1008 0x000f4240>; + clock-latency-ns = <0x00009c40>; + }; + opp-1200000000 { + opp-hz = <0x00000000 0x47868c00>; + opp-microvolt = <0x000cf850 0x000cf850 0x000f4240>; + opp-microvolt-L0 = <0x000d59f8 0x000d59f8 0x000f4240>; + opp-microvolt-L1 = <0x000cf850 0x000cf850 0x000f4240>; + opp-microvolt-L2 = <0x000cf850 0x000cf850 0x000f4240>; + opp-microvolt-L3 = <0x000c96a8 0x000c96a8 0x000f4240>; + opp-microvolt-L4 = <0x000c3500 0x000c3500 0x000f4240>; + clock-latency-ns = <0x00009c40>; + }; + opp-1296000000 { + opp-hz = <0x00000000 0x4d3f6400>; + opp-microvolt = <0x000d59f8 0x000d59f8 0x000f4240>; + opp-microvolt-L0 = <0x000e1d48 0x000e1d48 0x000f4240>; + opp-microvolt-L1 = <0x000d59f8 0x000d59f8 0x000f4240>; + opp-microvolt-L2 = <0x000d59f8 0x000d59f8 0x000f4240>; + opp-microvolt-L3 = <0x000cf850 0x000cf850 0x000f4240>; + opp-microvolt-L4 = <0x000c96a8 0x000c96a8 0x000f4240>; + clock-latency-ns = <0x00009c40>; + }; + opp-1416000000 { + opp-hz = <0x00000000 0x54667200>; + opp-microvolt = <0x000e1d48 0x000e1d48 0x000f4240>; + opp-microvolt-L0 = <0x000ee098 0x000ee098 0x000f4240>; + opp-microvolt-L1 = <0x000e1d48 0x000e1d48 0x000f4240>; + opp-microvolt-L2 = <0x000e1d48 0x000e1d48 0x000f4240>; + opp-microvolt-L3 = <0x000dbba0 0x000dbba0 0x000f4240>; + opp-microvolt-L4 = <0x000d59f8 0x000d59f8 0x000f4240>; + clock-latency-ns = <0x00009c40>; + }; + opp-1512000000 { + opp-hz = <0x00000000 0x5a1f4a00>; + opp-microvolt = <0x000ee098 0x000ee098 0x000f4240>; + opp-microvolt-L1 = <0x000ee098 0x000ee098 0x000f4240>; + opp-microvolt-L2 = <0x000e7ef0 0x000e7ef0 0x000f4240>; + opp-microvolt-L3 = <0x000e1d48 0x000e1d48 0x000f4240>; + opp-microvolt-L4 = <0x000dbba0 0x000dbba0 0x000f4240>; + clock-latency-ns = <0x00009c40>; + }; + }; + cpuinfo { + compatible = "rockchip,cpuinfo"; + nvmem-cells = <0x00000008 0x00000009>; + nvmem-cell-names = "id", "cpu-code"; + }; + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <0x00000000 0x0000007b 0x00000004 0x00000000 0x0000007c 0x00000004 0x00000000 0x0000007d 0x00000004 0x00000000 0x0000007e 0x00000004>; + interrupt-affinity = <0x0000000a 0x0000000b 0x0000000c 0x0000000d>; + }; + bus-soc { + compatible = "rockchip,rv1126-bus"; + rockchip,busfreq-policy = "smc"; + phandle = <0x000000de>; + soc-bus0 { + bus-id = <0x00000000>; + cfg-val = <0x00300020>; + enable-msk = <0x00007144>; + status = "okay"; + }; + soc-bus1 { + bus-id = <0x00000001>; + cfg-val = <0x00300020>; + enable-msk = <0x000070ff>; + status = "disabled"; + }; + soc-bus2 { + bus-id = <0x00000002>; + cfg-val = <0x00300020>; + enable-msk = <0x000070ff>; + status = "disabled"; + }; + soc-bus3 { + bus-id = <0x00000003>; + cfg-val = <0x00300020>; + enable-msk = <0x000070ff>; + status = "disabled"; + }; + soc-bus4 { + bus-id = <0x00000004>; + cfg-val = <0x00300020>; + enable-msk = <0x00007011>; + status = "disabled"; + }; + soc-bus5 { + bus-id = <0x00000005>; + cfg-val = <0x00300020>; + enable-msk = <0x00007011>; + status = "disabled"; + }; + soc-bus6 { + bus-id = <0x00000006>; + cfg-val = <0x00300020>; + enable-msk = <0x00007011>; + status = "disabled"; + }; + soc-bus7 { + bus-id = <0x00000007>; + cfg-val = <0x00300020>; + enable-msk = <0x00000000>; + status = "disabled"; + }; + soc-bus8 { + bus-id = <0x00000008>; + cfg-val = <0x00300020>; + enable-msk = <0x00000000>; + status = "disabled"; + }; + soc-bus9 { + bus-id = <0x00000009>; + cfg-val = <0x00300020>; + enable-msk = <0x00000000>; + status = "disabled"; + }; + soc-bus10 { + bus-id = <0x0000000a>; + cfg-val = <0x00300020>; + enable-msk = <0x00000000>; + status = "disabled"; + }; + soc-bus11 { + bus-id = <0x0000000b>; + cfg-val = <0x00300020>; + enable-msk = <0x00007000>; + status = "disabled"; + }; + }; + display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <0x0000000e>; + status = "okay"; + logo-memory-region = <0x0000000f>; + phandle = <0x000000df>; + route { + route-dsi { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x00000010>; + phandle = <0x000000e0>; + }; + route-rgb { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <0x00000011>; + phandle = <0x000000e1>; + }; + }; + }; + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0x00000002>; + rockchip,wake-irq = <0x00000000>; + rockchip,irq-mode-enable = <0x00000000>; + rockchip,baudrate = <0x0016e360>; + interrupts = <0x00000000 0x0000007f 0x00000004>; + status = "okay"; + phandle = <0x000000e2>; + }; + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + status = "disabled"; + phandle = <0x000000e3>; + }; + }; + mpp-srv { + compatible = "rockchip,mpp-service"; + rockchip,taskqueue-count = <0x00000004>; + rockchip,resetgroup-count = <0x00000004>; + status = "okay"; + phandle = <0x0000009e>; + }; + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + reserved-memory { + #address-cells = <0x00000001>; + #size-cells = <0x00000001>; + ranges; + linux,cma { + compatible = "shared-dma-pool"; + inactive; + reusable; + size = <0x00800000>; + linux,cma-default; + }; + drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x00000000 0x00000000>; + phandle = <0x0000000f>; + }; + isp { + compatible = "shared-dma-pool"; + inactive; + reusable; + size = <0x02800000>; + phandle = <0x00000013>; + }; + ramoops@8000000 { + compatible = "ramoops"; + reg = <0x08000000 0x00100000>; + record-size = <0x00020000>; + console-size = <0x00040000>; + ftrace-size = <0x00000000>; + pmsg-size = <0x00040000>; + status = "okay"; + phandle = <0x000000e4>; + }; + }; + rkcif_dvp { + compatible = "rockchip,rkcif-dvp"; + rockchip,hw = <0x00000012>; + memory-region = <0x00000013>; + status = "disabled"; + phandle = <0x00000014>; + }; + rkcif_dvp_sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x00000014>; + status = "disabled"; + phandle = <0x000000e5>; + }; + rkcif_lite_mipi_lvds { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <0x00000015>; + iommus = <0x00000016>; + status = "disabled"; + phandle = <0x00000017>; + }; + rkcif_lite_sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x00000017>; + status = "disabled"; + phandle = <0x000000e6>; + }; + rkcif_mipi_lvds { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <0x00000012>; + memory-region = <0x00000013>; + status = "okay"; + phandle = <0x00000019>; + port { + endpoint { + remote-endpoint = <0x00000018>; + data-lanes = <0x00000004>; + bus-type = <0x00000003>; + phandle = <0x00000052>; + }; + }; + }; + rkcif_mipi_lvds_sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <0x00000019>; + status = "okay"; + phandle = <0x000000e7>; + port { + endpoint { + remote-endpoint = <0x0000001a>; + data-lanes = <0x00000001 0x00000002 0x00000003 0x00000004>; + phandle = <0x000000a4>; + }; + }; + }; + rockchip-suspend { + compatible = "rockchip,pm-rv1126"; + status = "okay"; + rockchip,sleep-debug-en = <0x00000001>; + rockchip,sleep-mode-config = <0x00000602>; + rockchip,wakeup-config = <0x00000010>; + phandle = <0x000000e8>; + }; + rockchip-system-monitor { + compatible = "rockchip,system-monitor"; + phandle = <0x000000e9>; + }; + thermal-zones { + phandle = <0x000000ea>; + cpu-thermal { + polling-delay-passive = <0x00000014>; + polling-delay = <0x000003e8>; + sustainable-power = <0x0000036b>; + k_pu = <0x0000004b>; + k_po = <0x000000af>; + k_i = <0x00000000>; + thermal-sensors = <0x0000001b 0x00000000>; + phandle = <0x000000eb>; + trips { + trip-point-0 { + temperature = <0x00014c08>; + hysteresis = <0x000007d0>; + type = "passive"; + phandle = <0x000000ec>; + }; + trip-point-1 { + temperature = <0x00017318>; + hysteresis = <0x000007d0>; + type = "passive"; + phandle = <0x0000001c>; + }; + soc-crit { + temperature = <0x0001e848>; + hysteresis = <0x000007d0>; + type = "critical"; + phandle = <0x000000ed>; + }; + }; + cooling-maps { + map0 { + trip = <0x0000001c>; + cooling-device = <0x0000000a 0xffffffff 0xffffffff>; + contribution = <0x00000400>; + }; + map1 { + trip = <0x0000001c>; + cooling-device = <0x0000001d 0xffffffff 0xffffffff>; + contribution = <0x00000400>; + }; + map2 { + trip = <0x0000001c>; + cooling-device = <0x0000001e 0xffffffff 0xffffffff>; + contribution = <0x00000424>; + }; + }; + }; + npu-thermal { + polling-delay-passive = <0x00000014>; + polling-delay = <0x000003e8>; + sustainable-power = <0x000003d1>; + thermal-sensors = <0x0000001f 0x00000000>; + phandle = <0x000000ee>; + }; + }; + timer { + compatible = "arm,armv7-timer"; + interrupts = <0x00000001 0x0000000d 0x00000f04 0x00000001 0x0000000e 0x00000f04 0x00000001 0x0000000b 0x00000f04 0x00000001 0x0000000a 0x00000f04>; + clock-frequency = <0x016e3600>; + }; + oscillator { + compatible = "fixed-clock"; + clock-frequency = <0x016e3600>; + clock-output-names = "xin24m"; + #clock-cells = <0x00000000>; + phandle = <0x000000ef>; + }; + dummy_cpll { + compatible = "fixed-clock"; + clock-frequency = <0x00000000>; + clock-output-names = "dummy_cpll"; + #clock-cells = <0x00000000>; + phandle = <0x000000f0>; + }; + external-gmac-clockm0 { + compatible = "fixed-clock"; + clock-frequency = <0x07735940>; + clock-output-names = "clk_gmac_rgmii_clkin_m0"; + #clock-cells = <0x00000000>; + phandle = <0x000000f1>; + }; + external-gmac-clockm1 { + compatible = "fixed-clock"; + clock-frequency = <0x07735940>; + clock-output-names = "clk_gmac_rgmii_clkin_m1"; + #clock-cells = <0x00000000>; + phandle = <0x000000f2>; + }; + syscon@fe000000 { + compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd"; + reg = <0xfe000000 0x00020000>; + phandle = <0x00000050>; + rgb { + compatible = "rockchip,rv1126-rgb"; + status = "disabled"; + phandle = <0x000000f3>; + ports { + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + port@0 { + reg = <0x00000000>; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + endpoint@0 { + reg = <0x00000000>; + remote-endpoint = <0x00000011>; + phandle = <0x0000009c>; + }; + }; + }; + }; + }; + syscon@fe020000 { + compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd"; + reg = <0xfe020000 0x00001000>; + phandle = <0x0000003a>; + io-domains { + compatible = "rockchip,rv1126-pmu-io-voltage-domain"; + status = "okay"; + pmuio0-supply = <0x00000020>; + pmuio1-supply = <0x00000020>; + vccio2-supply = <0x00000020>; + vccio3-supply = <0x00000020>; + vccio4-supply = <0x00000021>; + vccio5-supply = <0x00000020>; + vccio6-supply = <0x00000020>; + vccio7-supply = <0x00000020>; + phandle = <0x000000f4>; + }; + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x00000200>; + mode-bootloader = <0x5242c301>; + mode-charge = <0x5242c30b>; + mode-fastboot = <0x5242c309>; + mode-loader = <0x5242c301>; + mode-normal = <0x5242c300>; + mode-recovery = <0x5242c303>; + mode-ums = <0x5242c30c>; + mode-panic = <0x5242c307>; + mode-watchdog = <0x5242c308>; + }; + }; + qos@fe810000 { + compatible = "syscon"; + reg = <0xfe810000 0x00000020>; + phandle = <0x00000036>; + }; + qos@fe810080 { + compatible = "syscon"; + reg = <0xfe810080 0x00000020>; + phandle = <0x00000037>; + }; + qos@fe850000 { + compatible = "syscon"; + reg = <0xfe850000 0x00000020>; + phandle = <0x00000022>; + }; + qos@fe860000 { + compatible = "syscon"; + reg = <0xfe860000 0x00000020>; + phandle = <0x00000032>; + }; + qos@fe860080 { + compatible = "syscon"; + reg = <0xfe860080 0x00000020>; + phandle = <0x00000033>; + }; + qos@fe860200 { + compatible = "syscon"; + reg = <0xfe860200 0x00000020>; + phandle = <0x00000034>; + }; + qos@fe86c000 { + compatible = "syscon"; + reg = <0xfe86c000 0x00000020>; + phandle = <0x00000035>; + }; + qos@fe870000 { + compatible = "syscon"; + reg = <0xfe870000 0x00000020>; + phandle = <0x00000023>; + }; + qos@fe870080 { + compatible = "syscon"; + reg = <0xfe870080 0x00000020>; + phandle = <0x00000024>; + }; + qos@fe870100 { + compatible = "syscon"; + reg = <0xfe870100 0x00000020>; + phandle = <0x00000025>; + }; + qos@fe880000 { + compatible = "syscon"; + reg = <0xfe880000 0x00000020>; + phandle = <0x0000002e>; + }; + qos@fe880080 { + compatible = "syscon"; + reg = <0xfe880080 0x00000020>; + phandle = <0x0000002f>; + }; + qos@fe890000 { + compatible = "syscon"; + reg = <0xfe890000 0x00000020>; + phandle = <0x00000027>; + }; + qos@fe890080 { + compatible = "syscon"; + reg = <0xfe890080 0x00000020>; + phandle = <0x00000028>; + }; + qos@fe890100 { + compatible = "syscon"; + reg = <0xfe890100 0x00000020>; + phandle = <0x00000029>; + }; + qos@fe8a0000 { + compatible = "syscon"; + reg = <0xfe8a0000 0x00000020>; + phandle = <0x0000002d>; + }; + qos@fe8a0080 { + compatible = "syscon"; + reg = <0xfe8a0080 0x00000020>; + phandle = <0x0000002a>; + }; + qos@fe8a0100 { + compatible = "syscon"; + reg = <0xfe8a0100 0x00000020>; + phandle = <0x0000002b>; + }; + qos@fe8a0180 { + compatible = "syscon"; + reg = <0xfe8a0180 0x00000020>; + phandle = <0x0000002c>; + }; + qos@fe8b0000 { + compatible = "syscon"; + reg = <0xfe8b0000 0x00000020>; + phandle = <0x00000030>; + }; + qos@fe8c0000 { + compatible = "syscon"; + reg = <0xfe8c0000 0x00000020>; + phandle = <0x00000031>; + }; + qos@fe8d0000 { + compatible = "syscon"; + reg = <0xfe8d0000 0x00000020>; + phandle = <0x00000026>; + }; + interrupt-controller@feff0000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <0x00000003>; + #address-cells = <0x00000000>; + reg = <0xfeff1000 0x00001000 0xfeff2000 0x00002000 0xfeff4000 0x00002000 0xfeff6000 0x00002000>; + interrupts = <0x00000001 0x00000009 0x00000f04>; + phandle = <0x00000001>; + }; + arm-debug@ff010000 { + compatible = "rockchip,debug"; + reg = <0xff010000 0x00001000 0xff012000 0x00001000 0xff014000 0x00001000 0xff016000 0x00001000>; + }; + pvtm@ff040000 { + compatible = "rockchip,rv1126-cpu-pvtm"; + reg = <0xff040000 0x00000100>; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pvtm@0 { + reg = <0x00000000>; + clocks = <0x00000002 0x00000008 0x00000002 0x000000f5>; + clock-names = "clk", "pclk"; + resets = <0x00000002 0x000000ec 0x00000002 0x000000eb>; + reset-names = "rst", "rst-p"; + }; + }; + power-management@ff3e0000 { + compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd"; + reg = <0xff3e0000 0x00001000>; + phandle = <0x000000f5>; + power-controller { + compatible = "rockchip,rv1126-power-controller"; + #power-domain-cells = <0x00000001>; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + status = "okay"; + phandle = <0x00000054>; + pd_npu@7 { + reg = <0x00000007>; + clocks = <0x00000002 0x000000c3 0x00000002 0x000000f0 0x00000002 0x00000119 0x00000002 0x00000090>; + pm_qos = <0x00000022>; + }; + pd_vepu@8 { + reg = <0x00000008>; + clocks = <0x00000002 0x000000a8 0x00000002 0x000000d3 0x00000002 0x00000056>; + pm_qos = <0x00000023 0x00000024 0x00000025>; + }; + pd_crypto@13 { + reg = <0x0000000d>; + clocks = <0x00000002 0x000000a6 0x00000002 0x000000cb 0x00000002 0x00000038 0x00000002 0x00000039>; + pm_qos = <0x00000026>; + }; + pd_vi@9 { + reg = <0x00000009>; + clocks = <0x00000002 0x000000b4 0x00000002 0x000000dd 0x00000002 0x0000005f 0x00000002 0x000000b5 0x00000002 0x000000de 0x00000002 0x0000009b 0x00000002 0x00000063 0x00000002 0x00000067 0x00000002 0x00000114 0x00000002 0x000000b6 0x00000002 0x000000df 0x00000002 0x0000009c>; + pm_qos = <0x00000027 0x00000028 0x00000029>; + }; + pd_vo@10 { + reg = <0x0000000a>; + clocks = <0x00000002 0x000000ae 0x00000002 0x000000d9 0x00000002 0x0000005a 0x00000002 0x000000af 0x00000002 0x000000da 0x00000002 0x0000009a 0x00000002 0x00000112 0x00000002 0x000000b0 0x00000002 0x000000db 0x00000002 0x0000005b>; + pm_qos = <0x0000002a 0x0000002b 0x0000002c 0x0000002d>; + }; + pd_ispp@11 { + reg = <0x0000000b>; + clocks = <0x00000002 0x000000ba 0x00000002 0x000000e1 0x00000002 0x0000006b>; + pm_qos = <0x0000002e 0x0000002f>; + }; + pd_vdpu@12 { + reg = <0x0000000c>; + clocks = <0x00000002 0x000000ab 0x00000002 0x000000d6 0x00000002 0x00000057 0x00000002 0x00000058 0x00000002 0x00000059 0x00000002 0x000000ac 0x00000002 0x000000d7>; + pm_qos = <0x00000030 0x00000031>; + }; + pd_nvm@15 { + reg = <0x0000000f>; + clocks = <0x00000002 0x000000e8 0x00000002 0x00000072 0x00000002 0x000000e9 0x00000002 0x00000075 0x00000002 0x000000ea 0x00000002 0x000000eb 0x00000002 0x00000076>; + pm_qos = <0x00000032 0x00000033 0x00000034>; + }; + pd_sdio@16 { + reg = <0x00000010>; + clocks = <0x00000002 0x000000e6 0x00000002 0x0000006f>; + pm_qos = <0x00000035>; + }; + pd_usb@17 { + reg = <0x00000011>; + clocks = <0x00000002 0x000000ed 0x00000002 0x000000ee 0x00000002 0x00000077 0x00000002 0x000000bd 0x00000002 0x00000078>; + pm_qos = <0x00000036 0x00000037>; + }; + }; + }; + i2c@ff3f0000 { + compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; + reg = <0xff3f0000 0x00001000>; + interrupts = <0x00000000 0x00000004 0x00000004>; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + clocks = <0x00000038 0x0000000c 0x00000038 0x00000021>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <0x00000039>; + status = "okay"; + phandle = <0x000000f6>; + pcf8563@51 { + compatible = "pcf8563"; + reg = <0x00000051>; + #clock-cells = <0x00000000>; + clock-frequency = <0x00008000>; + clock-output-names = "xin32k"; + phandle = <0x000000f7>; + }; + }; + i2c@ff400000 { + compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; + reg = <0xff400000 0x00001000>; + interrupts = <0x00000000 0x00000006 0x00000004>; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + rockchip,grf = <0x0000003a>; + clocks = <0x00000038 0x0000000d 0x00000038 0x00000022>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <0x0000003b>; + status = "disabled"; + phandle = <0x000000f8>; + }; + amba { + compatible = "simple-bus"; + #address-cells = <0x00000001>; + #size-cells = <0x00000001>; + ranges; + dma-controller@ff4e0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xff4e0000 0x00004000>; + interrupts = <0x00000000 0x00000001 0x00000004 0x00000000 0x00000002 0x00000004>; + #dma-cells = <0x00000001>; + clocks = <0x00000002 0x000000a1>; + clock-names = "apb_pclk"; + arm,pl330-periph-burst; + phandle = <0x0000003c>; + }; + }; + serial@ff410000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff410000 0x00000100>; + interrupts = <0x00000000 0x0000000d 0x00000004>; + reg-shift = <0x00000002>; + reg-io-width = <0x00000004>; + dmas = <0x0000003c 0x00000007 0x0000003c 0x00000006>; + clock-frequency = <0x016e3600>; + clocks = <0x00000038 0x0000000b 0x00000038 0x00000020>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <0x0000003d 0x0000003e 0x0000003f>; + status = "disabled"; + phandle = <0x000000f9>; + }; + pwm@ff430000 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff430000 0x00000010>; + #pwm-cells = <0x00000003>; + pinctrl-names = "active"; + pinctrl-0 = <0x00000040>; + clocks = <0x00000038 0x0000000f 0x00000038 0x00000023>; + clock-names = "pwm", "pclk"; + status = "okay"; + phandle = <0x000000d7>; + }; + pwm@ff430010 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff430010 0x00000010>; + #pwm-cells = <0x00000003>; + pinctrl-names = "active"; + pinctrl-0 = <0x00000041>; + clocks = <0x00000038 0x0000000f 0x00000038 0x00000023>; + clock-names = "pwm", "pclk"; + status = "okay"; + phandle = <0x000000d8>; + }; + pwm@ff430020 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff430020 0x00000010>; + #pwm-cells = <0x00000003>; + pinctrl-names = "active"; + pinctrl-0 = <0x00000042>; + clocks = <0x00000038 0x0000000f 0x00000038 0x00000023>; + clock-names = "pwm", "pclk"; + status = "disabled"; + phandle = <0x000000fa>; + }; + pwm@ff430030 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff430030 0x00000010>; + #pwm-cells = <0x00000003>; + pinctrl-names = "active"; + pinctrl-0 = <0x00000043>; + clocks = <0x00000038 0x0000000f 0x00000038 0x00000023>; + clock-names = "pwm", "pclk"; + status = "okay"; + phandle = <0x000000da>; + }; + pwm@ff440000 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff440000 0x00000010>; + #pwm-cells = <0x00000003>; + pinctrl-names = "active"; + pinctrl-0 = <0x00000044>; + clocks = <0x00000038 0x00000011 0x00000038 0x00000024>; + clock-names = "pwm", "pclk"; + status = "disabled"; + phandle = <0x000000fb>; + }; + pwm@ff440010 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff440010 0x00000010>; + #pwm-cells = <0x00000003>; + pinctrl-names = "active"; + pinctrl-0 = <0x00000045>; + clocks = <0x00000038 0x00000011 0x00000038 0x00000024>; + clock-names = "pwm", "pclk"; + status = "disabled"; + phandle = <0x000000fc>; + }; + pwm@ff440020 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff440020 0x00000010>; + #pwm-cells = <0x00000003>; + pinctrl-names = "active"; + pinctrl-0 = <0x00000046>; + clocks = <0x00000038 0x00000011 0x00000038 0x00000024>; + clock-names = "pwm", "pclk"; + status = "okay"; + phandle = <0x000000dd>; + }; + pwm@ff440030 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff440030 0x00000010>; + #pwm-cells = <0x00000003>; + pinctrl-names = "active"; + pinctrl-0 = <0x00000047>; + clocks = <0x00000038 0x00000011 0x00000038 0x00000024>; + clock-names = "pwm", "pclk"; + status = "disabled"; + phandle = <0x000000fd>; + }; + spi@ff450000 { + compatible = "rockchip,rv1126-spi", "rockchip,rk3066-spi"; + reg = <0xff450000 0x00001000>; + interrupts = <0x00000000 0x0000000a 0x00000004>; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + clocks = <0x00000038 0x00000012 0x00000038 0x00000025>; + clock-names = "spiclk", "apb_pclk"; + dmas = <0x0000003c 0x00000001 0x0000003c 0x00000000>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "high_speed"; + pinctrl-0 = <0x00000048 0x00000049 0x0000004a 0x0000004b 0x0000004c>; + pinctrl-1 = <0x0000004d 0x00000049 0x0000004a 0x0000004e 0x0000004f>; + status = "disabled"; + phandle = <0x000000fe>; + }; + pvtm@ff470000 { + compatible = "rockchip,rv1126-pmu-pvtm"; + reg = <0xff470000 0x00000100>; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pvtm@2 { + reg = <0x00000002>; + clocks = <0x00000038 0x00000014 0x00000038 0x0000002c>; + clock-names = "clk", "pclk"; + resets = <0x00000038 0x00000018 0x00000038 0x00000019>; + reset-names = "rst", "rst-p"; + }; + }; + clock-controller@ff480000 { + compatible = "rockchip,rv1126-pmucru"; + reg = <0xff480000 0x00001000>; + rockchip,pmugrf = <0x0000003a>; + #clock-cells = <0x00000001>; + #reset-cells = <0x00000001>; + phandle = <0x00000038>; + }; + clock-controller@ff490000 { + compatible = "rockchip,rv1126-cru"; + reg = <0xff490000 0x00001000>; + rockchip,grf = <0x00000050>; + #clock-cells = <0x00000001>; + #reset-cells = <0x00000001>; + assigned-clocks = <0x00000038 0x00000003 0x00000038 0x00000001 0x00000038 0x0000001e 0x00000002 0x00000003 0x00000002 0x00000004 0x00000002 0x00000005 0x00000002 0x000000a0 0x00000002 0x000000ec 0x00000002 0x000000f6 0x00000002 0x000000bb 0x00000002 0x000000e2 0x00000002 0x000000cc 0x00000002 0x000000c8>; + assigned-clock-rates = <0x00008000 0x46cf7100 0x05f5e100 0x1dcd6500 0x53724e00 0x23c34600 0x1dcd6500 0x0bebc200 0x05f5e100 0x11e1a300 0x0bebc200 0x08f0d180 0x0bebc200>; + assigned-clock-parents = <0x00000038 0x00000002>; + phandle = <0x00000002>; + }; + csi-dphy@ff4b0000 { + compatible = "rockchip,rv1126-csi-dphy"; + reg = <0xff4b0000 0x00008000>; + clocks = <0x00000002 0x00000122>; + clock-names = "pclk"; + rockchip,grf = <0x00000050>; + status = "okay"; + phandle = <0x000000ff>; + ports { + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + port@0 { + reg = <0x00000000>; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + endpoint@1 { + reg = <0x00000001>; + remote-endpoint = <0x00000051>; + data-lanes = <0x00000004>; + bus-type = <0x00000003>; + phandle = <0x0000005c>; + }; + }; + port@1 { + reg = <0x00000001>; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + endpoint@0 { + reg = <0x00000000>; + remote-endpoint = <0x00000052>; + data-lanes = <0x00000004>; + bus-type = <0x00000003>; + phandle = <0x00000018>; + }; + }; + }; + }; + csi-dphy@ff4b8000 { + compatible = "rockchip,rv1126-csi-dphy"; + reg = <0xff4b8000 0x00008000>; + clocks = <0x00000002 0x00000123>; + clock-names = "pclk"; + rockchip,grf = <0x00000050>; + status = "disabled"; + phandle = <0x00000100>; + }; + usb2-phy@ff4c0000 { + compatible = "rockchip,rv1126-usb2phy"; + reg = <0xff4c0000 0x00008000>; + rockchip,grf = <0x00000050>; + clocks = <0x00000038 0x00000017 0x00000002 0x00000125>; + clock-names = "phyclk", "pclk"; + resets = <0x00000002 0x000000b8 0x00000002 0x000000b6>; + reset-names = "u2phy", "u2phy-apb"; + #clock-cells = <0x00000000>; + status = "okay"; + phandle = <0x000000c6>; + otg-port { + #phy-cells = <0x00000000>; + interrupts = <0x00000000 0x00000073 0x00000004 0x00000000 0x00000074 0x00000004 0x00000000 0x00000075 0x00000004 0x00000000 0x00000078 0x00000004>; + interrupt-names = "otg-bvalid", "otg-id", "linestate", "disconnect"; + status = "okay"; + phandle = <0x000000c5>; + }; + }; + usb2-phy@ff4c8000 { + compatible = "rockchip,rv1126-usb2phy"; + reg = <0xff4c8000 0x00008000>; + rockchip,grf = <0x00000050>; + clocks = <0x00000038 0x00000018 0x00000002 0x00000124>; + clock-names = "phyclk", "pclk"; + assigned-clocks = <0x00000002 0x00000006>; + assigned-clock-parents = <0x00000053>; + resets = <0x00000002 0x000000b9 0x00000002 0x000000b7>; + reset-names = "u2phy", "u2phy-apb"; + #clock-cells = <0x00000000>; + clock-output-names = "usb480m_phy"; + status = "okay"; + phandle = <0x00000053>; + host-port { + #phy-cells = <0x00000000>; + interrupts = <0x00000000 0x00000076 0x00000004 0x00000000 0x00000077 0x00000004>; + interrupt-names = "linestate", "disconnect"; + status = "okay"; + phandle = <0x000000c7>; + }; + }; + mipi-dphy@ff4d0000 { + compatible = "rockchip,rv1126-mipi-dphy", "rockchip,rk1808-mipi-dphy"; + reg = <0xff4d0000 0x00000500>; + assigned-clocks = <0x00000038 0x0000001a>; + assigned-clock-rates = <0x016e3600>; + clocks = <0x00000038 0x0000001a 0x00000002 0x00000121>; + clock-names = "ref", "pclk"; + clock-output-names = "mipi_dphy_pll"; + #clock-cells = <0x00000000>; + resets = <0x00000002 0x000000e6>; + reset-names = "apb"; + #phy-cells = <0x00000000>; + rockchip,grf = <0x00000050>; + status = "disabled"; + phandle = <0x000000a0>; + }; + rng@ff500000 { + compatible = "rockchip,cryptov2-rng"; + reg = <0xff500000 0x00004000>; + clocks = <0x00000002 0x00000038 0x00000002 0x00000039 0x00000002 0x000000a6 0x00000002 0x000000cb>; + clock-names = "clk_crypto", "clk_crypto_apk", "aclk_crypto", "hclk_crypto"; + assigned-clocks = <0x00000002 0x00000038 0x00000002 0x00000039 0x00000002 0x000000a6 0x00000002 0x000000cb>; + assigned-clock-rates = <0x08f0d180 0x08f0d180 0x0bebc200 0x05f5e100>; + power-domains = <0x00000054 0x0000000d>; + resets = <0x00000002 0x0000005c>; + reset-names = "reset"; + status = "okay"; + phandle = <0x00000101>; + }; + crypto@ff500000 { + compatible = "rockchip,rv1126-crypto"; + reg = <0xff500000 0x00004000>; + interrupts = <0x00000000 0x00000003 0x00000004>; + clocks = <0x00000002 0x00000038 0x00000002 0x00000039 0x00000002 0x000000a6 0x00000002 0x000000cb>; + clock-names = "aclk", "hclk", "sclk", "apb_pclk"; + power-domains = <0x00000054 0x0000000d>; + resets = <0x00000002 0x0000005c>; + reset-names = "crypto-rst"; + status = "disabled"; + phandle = <0x00000102>; + }; + i2c@ff510000 { + compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; + reg = <0xff510000 0x00001000>; + interrupts = <0x00000000 0x00000005 0x00000004>; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + clocks = <0x00000002 0x00000021 0x00000002 0x000000ff>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <0x00000055>; + status = "okay"; + clock-frequency = <0x00061a80>; + phandle = <0x00000103>; + imx307@1a { + compatible = "sony,imx307"; + reg = <0x0000001a>; + clocks = <0x00000002 0x00000067>; + clock-names = "xvclk"; + power-domains = <0x00000054 0x00000009>; + pinctrl-names = "rockchip,camera_default"; + pinctrl-0 = <0x00000056>; + avdd-supply = <0x00000020>; + dovdd-supply = <0x00000021>; + dvdd-supply = <0x00000057>; + reset-gpios = <0x00000058 0x0000001d 0x00000000>; + rockchip,camera-module-index = <0x00000001>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "MTV4-IR-E-P"; + rockchip,camera-module-lens-name = "40IRC-4MP-F16"; + ir-cut = <0x00000059>; + flash-leds = <0x0000005a>; + lens-focus = <0x0000005b>; + phandle = <0x00000104>; + port { + endpoint { + remote-endpoint = <0x0000005c>; + data-lanes = <0x00000004>; + bus-type = <0x00000003>; + phandle = <0x00000051>; + }; + }; + }; + }; + i2c@ff520000 { + compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; + reg = <0xff520000 0x00001000>; + interrupts = <0x00000000 0x00000007 0x00000004>; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + clocks = <0x00000002 0x00000022 0x00000002 0x00000100>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <0x0000005d>; + status = "disabled"; + phandle = <0x00000105>; + }; + i2c@ff530000 { + compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; + reg = <0xff530000 0x00001000>; + interrupts = <0x00000000 0x00000008 0x00000004>; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + clocks = <0x00000002 0x00000023 0x00000002 0x00000101>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <0x0000005e>; + status = "okay"; + clock-frequency = <0x00061a80>; + phandle = <0x00000106>; + es8311@18 { + compatible = "everest,es8311"; + reg = <0x00000018>; + clocks = <0x00000002 0x00000042>; + clock-names = "mclk"; + adc-volume = <0x000000bf>; + dac-volume = <0x000000bf>; + aec-mode = "dac left, adc right"; + pinctrl-names = "default"; + pinctrl-0 = <0x0000005f 0x00000060>; + assigned-clocks = <0x00000002 0x00000042>; + assigned-clock-parents = <0x00000002 0x0000003d>; + spk-ctl-gpios = <0x00000061 0x00000005 0x00000000>; + #sound-dai-cells = <0x00000000>; + phandle = <0x000000dc>; + }; + }; + i2c@ff540000 { + compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; + reg = <0xff540000 0x00001000>; + interrupts = <0x00000000 0x00000009 0x00000004>; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + clocks = <0x00000002 0x00000024 0x00000002 0x00000102>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <0x00000062>; + status = "disabled"; + phandle = <0x00000107>; + }; + pwm@ff550000 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff550000 0x00000010>; + #pwm-cells = <0x00000003>; + pinctrl-names = "active"; + pinctrl-0 = <0x00000063>; + clocks = <0x00000002 0x00000027 0x00000002 0x00000105>; + clock-names = "pwm", "pclk"; + status = "disabled"; + phandle = <0x00000108>; + }; + pwm@ff550010 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff550010 0x00000010>; + #pwm-cells = <0x00000003>; + pinctrl-names = "active"; + pinctrl-0 = <0x00000064>; + clocks = <0x00000002 0x00000027 0x00000002 0x00000105>; + clock-names = "pwm", "pclk"; + status = "disabled"; + phandle = <0x00000109>; + }; + pwm@ff550020 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff550020 0x00000010>; + #pwm-cells = <0x00000003>; + pinctrl-names = "active"; + pinctrl-0 = <0x00000065>; + clocks = <0x00000002 0x00000027 0x00000002 0x00000105>; + clock-names = "pwm", "pclk"; + status = "disabled"; + phandle = <0x0000010a>; + }; + pwm@ff550030 { + compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; + reg = <0xff550030 0x00000010>; + #pwm-cells = <0x00000003>; + pinctrl-names = "active"; + pinctrl-0 = <0x00000066>; + clocks = <0x00000002 0x00000027 0x00000002 0x00000105>; + clock-names = "pwm", "pclk"; + status = "disabled"; + phandle = <0x0000010b>; + }; + serial@ff560000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff560000 0x00000100>; + interrupts = <0x00000000 0x0000000c 0x00000004>; + reg-shift = <0x00000002>; + reg-io-width = <0x00000004>; + dmas = <0x0000003c 0x00000005 0x0000003c 0x00000004>; + clock-frequency = <0x016e3600>; + clocks = <0x00000002 0x00000010 0x00000002 0x000000fa>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <0x00000067 0x00000068 0x00000069>; + status = "disabled"; + phandle = <0x0000010c>; + }; + serial@ff570000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff570000 0x00000100>; + interrupts = <0x00000000 0x0000000e 0x00000004>; + reg-shift = <0x00000002>; + reg-io-width = <0x00000004>; + dmas = <0x0000003c 0x00000009 0x0000003c 0x00000008>; + clock-frequency = <0x016e3600>; + clocks = <0x00000002 0x00000014 0x00000002 0x000000fb>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <0x0000006a>; + status = "disabled"; + phandle = <0x0000010d>; + }; + serial@ff580000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff580000 0x00000100>; + interrupts = <0x00000000 0x0000000f 0x00000004>; + reg-shift = <0x00000002>; + reg-io-width = <0x00000004>; + dmas = <0x0000003c 0x0000000b 0x0000003c 0x0000000a>; + clock-frequency = <0x016e3600>; + clocks = <0x00000002 0x00000018 0x00000002 0x000000fc>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <0x0000006b 0x0000006c 0x0000006d>; + status = "okay"; + wakeup-source; + phandle = <0x0000010e>; + }; + serial@ff590000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff590000 0x00000100>; + interrupts = <0x00000000 0x00000010 0x00000004>; + reg-shift = <0x00000002>; + reg-io-width = <0x00000004>; + dmas = <0x0000003c 0x0000000d 0x0000003c 0x0000000c>; + clock-frequency = <0x016e3600>; + clocks = <0x00000002 0x0000001c 0x00000002 0x000000fd>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <0x0000006e 0x0000006f 0x00000070>; + status = "disabled"; + phandle = <0x0000010f>; + }; + serial@ff5a0000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff5a0000 0x00000100>; + interrupts = <0x00000000 0x00000011 0x00000004>; + reg-shift = <0x00000002>; + reg-io-width = <0x00000004>; + dmas = <0x0000003c 0x0000000f 0x0000003c 0x0000000e>; + clock-frequency = <0x016e3600>; + clocks = <0x00000002 0x00000020 0x00000002 0x000000fe>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <0x00000071 0x00000072 0x00000073>; + status = "disabled"; + phandle = <0x00000110>; + }; + spi@ff5b0000 { + compatible = "rockchip,rv1126-spi", "rockchip,rk3066-spi"; + reg = <0xff5b0000 0x00001000>; + interrupts = <0x00000000 0x0000000b 0x00000004>; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + clocks = <0x00000002 0x00000025 0x00000002 0x00000103>; + clock-names = "spiclk", "apb_pclk"; + dmas = <0x0000003c 0x00000003 0x0000003c 0x00000002>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "high_speed"; + pinctrl-0 = <0x00000074 0x00000075 0x00000076 0x00000077 0x00000078>; + pinctrl-1 = <0x00000079 0x00000075 0x00000076 0x0000007a 0x0000007b>; + status = "disabled"; + phandle = <0x00000111>; + }; + otp@ff5c0000 { + compatible = "rockchip,rv1126-otp"; + reg = <0xff5c0000 0x00001000>; + #address-cells = <0x00000001>; + #size-cells = <0x00000001>; + clocks = <0x00000002 0x00000094 0x00000002 0x00000126>; + clock-names = "otp", "apb_pclk"; + status = "okay"; + phandle = <0x00000112>; + cpu-code@2 { + reg = <0x00000002 0x00000002>; + phandle = <0x00000009>; + }; + id@7 { + reg = <0x00000007 0x00000010>; + phandle = <0x00000008>; + }; + cpu-leakage@17 { + reg = <0x00000017 0x00000001>; + phandle = <0x00000006>; + }; + logic-leakage@18 { + reg = <0x00000018 0x00000001>; + phandle = <0x00000113>; + }; + npu-leakage@19 { + reg = <0x00000019 0x00000001>; + phandle = <0x000000c3>; + }; + venc-leakage@1a { + reg = <0x0000001a 0x00000001>; + phandle = <0x000000b1>; + }; + cpu-performance@1e { + reg = <0x0000001e 0x00000001>; + bits = <0x00000004 0x00000003>; + phandle = <0x00000007>; + }; + npu-performance@1f { + reg = <0x0000001f 0x00000001>; + bits = <0x00000000 0x00000002>; + phandle = <0x000000c4>; + }; + venc-performance@1f { + reg = <0x0000001f 0x00000001>; + bits = <0x00000002 0x00000002>; + phandle = <0x000000b2>; + }; + cpu-tsadc-trim-l@23 { + reg = <0x00000023 0x00000001>; + phandle = <0x0000007c>; + }; + cpu-tsadc-trim-h@24 { + reg = <0x00000024 0x00000001>; + bits = <0x00000000 0x00000004>; + phandle = <0x0000007d>; + }; + npu-tsadc-trim-l@25 { + reg = <0x00000025 0x00000001>; + phandle = <0x00000081>; + }; + npu-tsadc-trim-h@26 { + reg = <0x00000026 0x00000001>; + bits = <0x00000000 0x00000004>; + phandle = <0x00000082>; + }; + tsadc-trim-base@27 { + reg = <0x00000027 0x00000001>; + phandle = <0x0000007e>; + }; + }; + saradc@ff5e0000 { + compatible = "rockchip,rk3399-saradc"; + reg = <0xff5e0000 0x00000100>; + interrupts = <0x00000000 0x00000028 0x00000004>; + #io-channel-cells = <0x00000001>; + clocks = <0x00000002 0x0000002c 0x00000002 0x0000010a>; + clock-names = "saradc", "apb_pclk"; + resets = <0x00000002 0x0000003b>; + reset-names = "saradc-apb"; + status = "okay"; + vref-supply = <0x00000021>; + phandle = <0x000000d9>; + }; + tsadc@ff5f0000 { + compatible = "rockchip,rv1126-tsadc"; + reg = <0xff5f0000 0x00000100>; + rockchip,grf = <0x00000050>; + interrupts = <0x00000000 0x00000027 0x00000004>; + assigned-clocks = <0x00000002 0x00000036>; + assigned-clock-rates = <0x003d0900>; + clocks = <0x00000002 0x00000036 0x00000002 0x0000010f 0x00000002 0x00000037>; + clock-names = "tsadc", "apb_pclk", "phy_clk"; + resets = <0x00000002 0x000000e8 0x00000002 0x000000e9 0x00000002 0x000000ea>; + reset-names = "tsadc-apb", "tsadc", "tsadc-phy"; + rockchip,hw-tshut-temp = <0x0001d4c0>; + #thermal-sensor-cells = <0x00000001>; + nvmem-cells = <0x0000007c 0x0000007d 0x0000007e>; + nvmem-cell-names = "trim_l", "trim_h", "trim_base"; + rockchip,hw-tshut-mode = <0x00000000>; + rockchip,hw-tshut-polarity = <0x00000000>; + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <0x0000007f>; + pinctrl-1 = <0x00000080>; + status = "okay"; + phandle = <0x0000001b>; + }; + tsadc@ff5f8000 { + compatible = "rockchip,rv1126-tsadc"; + reg = <0xff5f8000 0x00000100>; + rockchip,grf = <0x00000050>; + interrupts = <0x00000000 0x00000071 0x00000004>; + assigned-clocks = <0x00000002 0x00000034>; + assigned-clock-rates = <0x003d0900>; + clocks = <0x00000002 0x00000034 0x00000002 0x0000010e 0x00000002 0x00000035>; + clock-names = "tsadc", "apb_pclk", "phy_clk"; + resets = <0x00000002 0x000000d8 0x00000002 0x000000d9 0x00000002 0x000000da>; + reset-names = "tsadc-apb", "tsadc", "tsadc-phy"; + rockchip,hw-tshut-temp = <0x0001d4c0>; + #thermal-sensor-cells = <0x00000001>; + nvmem-cells = <0x00000081 0x00000082 0x0000007e>; + nvmem-cell-names = "trim_l", "trim_h", "trim_base"; + rockchip,hw-tshut-mode = <0x00000000>; + rockchip,hw-tshut-polarity = <0x00000000>; + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <0x0000007f>; + pinctrl-1 = <0x00000080>; + status = "okay"; + phandle = <0x0000001f>; + }; + dcf@ff600000 { + compatible = "syscon"; + reg = <0xff600000 0x00001000>; + status = "disabled"; + phandle = <0x00000097>; + }; + can@ff610000 { + compatible = "rockchip,can-1.0"; + reg = <0xff610000 0x00000100>; + interrupts = <0x00000000 0x00000064 0x00000004>; + assigned-clocks = <0x00000002 0x00000033>; + assigned-clock-rates = <0x0bebc200>; + clocks = <0x00000002 0x00000033 0x00000002 0x0000010d>; + clock-names = "baudclk", "apb_pclk"; + resets = <0x00000002 0x00000051 0x00000002 0x00000050>; + reset-names = "can", "can-apb"; + status = "disabled"; + phandle = <0x00000114>; + }; + rktimer@ff660000 { + compatible = "rockchip,rk3288-timer"; + reg = <0xff660000 0x00000020>; + interrupts = <0x00000000 0x00000018 0x00000004>; + clocks = <0x00000002 0x0000010b 0x00000002 0x0000002d>; + clock-names = "pclk", "timer"; + phandle = <0x00000115>; + }; + watchdog@ff680000 { + compatible = "rockchip,rv1126-wdt", "snps,dw-wdt"; + reg = <0xff680000 0x00000100>; + clocks = <0x00000002 0x000000f8>; + interrupts = <0x00000000 0x00000020 0x00000004>; + status = "okay"; + phandle = <0x00000116>; + }; + mailbox@ff6a0000 { + compatible = "rockchip,rv1126-mailbox", "rockchip,rk3368-mailbox"; + reg = <0xff6a0000 0x00001000>; + interrupts = <0x00000000 0x0000006f 0x00000004>; + clocks = <0x00000002 0x000000f9>; + clock-names = "pclk_mailbox"; + #mbox-cells = <0x00000001>; + status = "disabled"; + phandle = <0x00000117>; + }; + decompress@ff6c0000 { + compatible = "rockchip,hw-decompress"; + reg = <0xff6c0000 0x00001000>; + interrupts = <0x00000000 0x00000051 0x00000004>; + clocks = <0x00000002 0x000000a4 0x00000002 0x00000096 0x00000002 0x0000010c>; + clock-names = "aclk", "dclk", "pclk"; + resets = <0x00000002 0x00000057>; + reset-names = "dresetn"; + status = "disabled"; + phandle = <0x00000118>; + }; + i2s@ff800000 { + compatible = "rockchip,rv1126-i2s-tdm"; + reg = <0xff800000 0x00001000>; + interrupts = <0x00000000 0x0000002e 0x00000004>; + clocks = <0x00000002 0x0000003d 0x00000002 0x00000041 0x00000002 0x000000cd>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <0x0000003c 0x00000014 0x0000003c 0x00000013>; + dma-names = "tx", "rx"; + resets = <0x00000002 0x00000063 0x00000002 0x00000064>; + reset-names = "tx-m", "rx-m"; + rockchip,cru = <0x00000002>; + rockchip,grf = <0x00000050>; + pinctrl-names = "default"; + pinctrl-0 = <0x00000083 0x00000084 0x00000085 0x00000086>; + status = "okay"; + rockchip,clk-trcm = <0x00000001>; + #sound-dai-cells = <0x00000000>; + phandle = <0x000000db>; + }; + i2s@ff810000 { + compatible = "rockchip,rv1126-i2s", "rockchip,rk3066-i2s"; + reg = <0xff810000 0x00001000>; + interrupts = <0x00000000 0x0000002f 0x00000004>; + clocks = <0x00000002 0x00000047 0x00000002 0x000000ce>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <0x0000003c 0x00000016 0x0000003c 0x00000015>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <0x00000087 0x00000088 0x00000089 0x0000008a>; + status = "disabled"; + phandle = <0x00000119>; + }; + i2s@ff820000 { + compatible = "rockchip,rv1126-i2s", "rockchip,rk3066-i2s"; + reg = <0xff820000 0x00001000>; + interrupts = <0x00000000 0x00000030 0x00000004>; + clocks = <0x00000002 0x0000004c 0x00000002 0x000000cf>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <0x0000003c 0x00000018 0x0000003c 0x00000017>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <0x0000008b 0x0000008c 0x0000008d 0x0000008e>; + status = "disabled"; + phandle = <0x0000011a>; + }; + pdm@ff830000 { + compatible = "rockchip,rv1126-pdm", "rockchip,pdm"; + reg = <0xff830000 0x00001000>; + clocks = <0x00000002 0x0000004e 0x00000002 0x000000d0>; + clock-names = "pdm_clk", "pdm_hclk"; + dmas = <0x0000003c 0x00000019>; + dma-names = "rx"; + pinctrl-names = "default"; + pinctrl-0 = <0x0000008f 0x00000090 0x00000091 0x00000092 0x00000093 0x00000094>; + status = "disabled"; + phandle = <0x0000011b>; + }; + audpwm@ff840000 { + compatible = "rockchip,rv1126-audio-pwm", "rockchip,audio-pwm-v1"; + reg = <0xff840000 0x00001000>; + clocks = <0x00000002 0x00000052 0x00000002 0x000000d1>; + clock-names = "clk", "hclk"; + dmas = <0x0000003c 0x0000001a>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <0x00000095>; + rockchip,sample-width-bits = <0x0000000b>; + rockchip,interpolat-points = <0x00000001>; + status = "disabled"; + phandle = <0x0000011c>; + }; + codec-digital@ff850000 { + compatible = "rockchip,rv1126-codec-digital", "rockchip,codec-digital-v1"; + reg = <0xff850000 0x00001000>; + clocks = <0x00000002 0x00000053 0x00000002 0x00000054 0x00000002 0x00000110>; + clock-names = "adc", "dac", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <0x00000096>; + resets = <0x00000002 0x0000006e>; + reset-names = "reset"; + rockchip,grf = <0x00000050>; + status = "disabled"; + phandle = <0x0000011d>; + }; + dfi@ff9c0000 { + reg = <0xff9c0000 0x00000400>; + compatible = "rockchip,rv1126-dfi"; + rockchip,pmugrf = <0x0000003a>; + status = "disabled"; + phandle = <0x00000098>; + }; + dmc { + compatible = "rockchip,rv1126-dmc"; + dcf = <0x00000097>; + interrupts = <0x00000000 0x00000000 0x00000004>; + interrupt-names = "complete"; + devfreq-events = <0x00000098>; + clocks = <0x00000002 0x00000093>; + clock-names = "dmc_clk"; + operating-points-v2 = <0x00000099>; + ddr_timing = <0x0000009a>; + upthreshold = <0x00000028>; + downdifferential = <0x00000014>; + system-status-freq = <0x00000001 0x000e1960 0x00000008 0x00050140 0x00000002 0x00050140 0x00000020 0x000e1960 0x00001000 0x000e1960 0x00004000 0x000e1960 0x00002000 0x000e1960>; + auto-min-freq = <0x00050140>; + auto-freq-en = <0x00000001>; + #cooling-cells = <0x00000002>; + status = "disabled"; + phandle = <0x0000011e>; + }; + dmc-opp-table { + compatible = "operating-points-v2"; + phandle = <0x00000099>; + opp-328000000 { + opp-hz = <0x00000000 0x138ce200>; + opp-microvolt = <0x000c3500>; + }; + opp-528000000 { + opp-hz = <0x00000000 0x1f78a400>; + opp-microvolt = <0x000c3500>; + }; + opp-784000000 { + opp-hz = <0x00000000 0x2ebae400>; + opp-microvolt = <0x000c3500>; + }; + opp-924000000 { + opp-hz = <0x00000000 0x37131f00>; + opp-microvolt = <0x000c3500>; + }; + opp-1056000000 { + opp-hz = <0x00000000 0x3ef14800>; + opp-microvolt = <0x000c3500>; + status = "disabled"; + }; + }; + dmcdbg { + compatible = "rockchip,rv1126-dmcdbg"; + status = "disabled"; + phandle = <0x0000011f>; + }; + rkcif@ffae0000 { + compatible = "rockchip,rv1126-cif"; + reg = <0xffae0000 0x00008000>; + reg-names = "cif_regs"; + interrupts = <0x00000000 0x0000003a 0x00000004>; + interrupt-names = "cif-intr"; + clocks = <0x00000002 0x000000b5 0x00000002 0x000000de 0x00000002 0x0000009b>; + clock-names = "aclk_cif", "hclk_cif", "dclk_cif"; + resets = <0x00000002 0x00000094 0x00000002 0x00000095 0x00000002 0x00000096 0x00000002 0x00000097 0x00000002 0x00000098 0x00000002 0x00000099>; + reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_d", "rst_cif_p", "rst_cif_i", "rst_cif_rx_p"; + assigned-clocks = <0x00000002 0x0000009b>; + assigned-clock-rates = <0x11e1a300>; + power-domains = <0x00000054 0x00000009>; + rockchip,grf = <0x00000050>; + memory-region = <0x00000013>; + status = "okay"; + phandle = <0x00000012>; + }; + iommu@ffae0800 { + compatible = "rockchip,iommu"; + reg = <0xffae0800 0x00000100>; + interrupts = <0x00000000 0x0000003a 0x00000004>; + interrupt-names = "cif_mmu"; + clocks = <0x00000002 0x000000b5 0x00000002 0x000000de>; + clock-names = "aclk", "iface"; + power-domains = <0x00000054 0x00000009>; + #iommu-cells = <0x00000000>; + status = "disabled"; + phandle = <0x00000120>; + }; + rkcif_lite@ffae8000 { + compatible = "rockchip,rv1126-cif-lite"; + reg = <0xffae8000 0x00008000>; + reg-names = "cif_regs"; + interrupts = <0x00000000 0x00000035 0x00000004>; + interrupt-names = "cif-lite-intr"; + clocks = <0x00000002 0x000000b6 0x00000002 0x000000df 0x00000002 0x0000009c>; + clock-names = "aclk_cif_lite", "hclk_cif_lite", "dclk_cif_lite"; + resets = <0x00000002 0x000000dc 0x00000002 0x000000dd 0x00000002 0x000000de 0x00000002 0x000000df>; + reset-names = "rst_cif_lite_a", "rst_cif_lite_h", "rst_cif_lite_d", "rst_cif_lite_rx_p"; + assigned-clocks = <0x00000002 0x0000009c>; + assigned-clock-rates = <0x11e1a300>; + power-domains = <0x00000054 0x00000009>; + iommus = <0x00000016>; + status = "disabled"; + phandle = <0x00000015>; + }; + iommu@ffae8800 { + compatible = "rockchip,iommu"; + reg = <0xffae8800 0x00000100>; + interrupts = <0x00000000 0x00000035 0x00000004>; + interrupt-names = "cif_lite_mmu"; + clocks = <0x00000002 0x000000b6 0x00000002 0x000000df>; + clock-names = "aclk", "iface"; + power-domains = <0x00000054 0x00000009>; + #iommu-cells = <0x00000000>; + status = "disabled"; + phandle = <0x00000016>; + }; + rk_rga@ffaf0000 { + compatible = "rockchip,rga2"; + reg = <0xffaf0000 0x00001000>; + interrupts = <0x00000000 0x0000003e 0x00000004>; + clocks = <0x00000002 0x000000ae 0x00000002 0x000000d9 0x00000002 0x0000005a>; + clock-names = "aclk_rga", "hclk_rga", "clk_rga"; + power-domains = <0x00000054 0x0000000a>; + status = "okay"; + phandle = <0x00000121>; + }; + vop@ffb00000 { + compatible = "rockchip,rv1126-vop"; + reg = <0xffb00000 0x00000200 0xffb00a00 0x00000400>; + reg-names = "regs", "gamma_lut"; + rockchip,grf = <0x00000050>; + interrupts = <0x00000000 0x0000003b 0x00000004>; + clocks = <0x00000002 0x000000af 0x00000002 0x0000009a 0x00000002 0x000000da>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + iommus = <0x0000009b>; + power-domains = <0x00000054 0x0000000a>; + status = "okay"; + phandle = <0x00000122>; + port { + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + phandle = <0x0000000e>; + endpoint@0 { + reg = <0x00000000>; + remote-endpoint = <0x0000009c>; + phandle = <0x00000011>; + }; + endpoint@1 { + reg = <0x00000001>; + remote-endpoint = <0x0000009d>; + phandle = <0x00000010>; + }; + }; + }; + iommu@ffb00f00 { + compatible = "rockchip,iommu"; + reg = <0xffb00f00 0x00000100>; + interrupts = <0x00000000 0x0000003b 0x00000004>; + interrupt-names = "vop_mmu"; + clocks = <0x00000002 0x000000af 0x00000002 0x000000da>; + clock-names = "aclk", "iface"; + #iommu-cells = <0x00000000>; + rockchip,disable-device-link-resume; + power-domains = <0x00000054 0x0000000a>; + status = "disabled"; + phandle = <0x0000009b>; + }; + mipi-csi2@ffb10000 { + compatible = "rockchip,rv1126-mipi-csi2"; + reg = <0xffb10000 0x00010000>; + reg-names = "csihost_regs"; + interrupts = <0x00000000 0x00000038 0x00000004 0x00000000 0x00000039 0x00000004>; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <0x00000002 0x00000114 0x00000002 0x0000009f>; + clock-names = "pclk_csi2host", "srst_csihost_p"; + power-domains = <0x00000054 0x00000009>; + status = "disabled"; + phandle = <0x00000123>; + ports { + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + port@0 { + reg = <0x00000000>; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + endpoint@1 { + reg = <0x00000001>; + remote-endpoint = <0x00000018>; + data-lanes = <0x00000001 0x00000002 0x00000003 0x00000004>; + phandle = <0x00000124>; + }; + }; + port@1 { + reg = <0x00000001>; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + endpoint@0 { + reg = <0x00000000>; + remote-endpoint = <0x00000052>; + data-lanes = <0x00000001 0x00000002 0x00000003 0x00000004>; + phandle = <0x00000125>; + }; + }; + }; + }; + iep@ffb20000 { + compatible = "rockchip,rv1126-iep", "rockchip,iep-v2"; + reg = <0xffb20000 0x00000500>; + interrupts = <0x00000000 0x00000072 0x00000004>; + clocks = <0x00000002 0x000000b0 0x00000002 0x000000db 0x00000002 0x0000005b>; + clock-names = "aclk", "hclk", "sclk"; + resets = <0x00000002 0x0000008b 0x00000002 0x0000008c 0x00000002 0x0000008d>; + reset-names = "rst_a", "rst_h", "rst_s"; + power-domains = <0x00000054 0x0000000a>; + rockchip,srv = <0x0000009e>; + rockchip,taskqueue-node = <0x00000003>; + rockchip,resetgroup-node = <0x00000003>; + iommus = <0x0000009f>; + status = "disabled"; + phandle = <0x00000126>; + }; + iommu@ffb20800 { + compatible = "rockchip,iommu"; + reg = <0xffb20800 0x00000100>; + interrupts = <0x00000000 0x00000072 0x00000004>; + interrupt-names = "iep_mmu"; + clocks = <0x00000002 0x000000b0 0x00000002 0x000000db>; + clock-names = "aclk", "iface"; + #iommu-cells = <0x00000000>; + power-domains = <0x00000054 0x0000000a>; + status = "disabled"; + phandle = <0x0000009f>; + }; + dsi@ffb30000 { + compatible = "rockchip,rv1126-mipi-dsi"; + reg = <0xffb30000 0x00000500>; + interrupts = <0x00000000 0x0000003d 0x00000004>; + clocks = <0x00000002 0x00000112 0x000000a0>; + clock-names = "pclk", "hs_clk"; + resets = <0x00000002 0x0000008a>; + reset-names = "apb"; + phys = <0x000000a0>; + phy-names = "mipi_dphy"; + rockchip,grf = <0x00000050>; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + power-domains = <0x00000054 0x0000000a>; + status = "disabled"; + phandle = <0x00000127>; + ports { + port { + endpoint { + remote-endpoint = <0x00000010>; + phandle = <0x0000009d>; + }; + }; + }; + }; + rkisp@ffb50000 { + compatible = "rockchip,rv1126-rkisp"; + reg = <0xffb50000 0x00010000>; + interrupts = <0x00000000 0x00000034 0x00000004 0x00000000 0x00000036 0x00000004 0x00000000 0x00000037 0x00000004>; + interrupt-names = "isp_irq", "mi_irq", "mipi_irq"; + clocks = <0x00000002 0x000000b4 0x00000002 0x000000dd 0x00000002 0x0000005f>; + clock-names = "aclk_isp", "hclk_isp", "clk_isp"; + assigned-clocks = <0x00000002 0x000000b4 0x00000002 0x000000dd>; + assigned-clock-rates = <0x1dcd6500 0x0ee6b280>; + resets = <0x00000002 0x00000093 0x00000002 0x0000008e>; + reset-names = "isp", "isp-rx-p"; + power-domains = <0x00000054 0x00000009>; + iommus = <0x000000a1>; + memory-region = <0x00000013>; + status = "okay"; + phandle = <0x000000a2>; + }; + iommu@ffb51a00 { + compatible = "rockchip,iommu"; + reg = <0xffb51a00 0x00000100>; + interrupts = <0x00000000 0x00000033 0x00000004>; + interrupt-names = "isp_mmu"; + clocks = <0x00000002 0x000000b4 0x00000002 0x000000dd>; + clock-names = "aclk", "iface"; + power-domains = <0x00000054 0x00000009>; + #iommu-cells = <0x00000000>; + rockchip,disable-mmu-reset; + status = "okay"; + phandle = <0x000000a1>; + }; + rkisp-vir0 { + compatible = "rockchip,rv1126-rkisp-vir"; + rockchip,hw = <0x000000a2>; + status = "okay"; + phandle = <0x00000128>; + ports { + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + port@1 { + reg = <0x00000001>; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + endpoint@1 { + reg = <0x00000001>; + remote-endpoint = <0x000000a3>; + phandle = <0x000000a9>; + }; + }; + port@0 { + reg = <0x00000000>; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + endpoint@0 { + reg = <0x00000000>; + remote-endpoint = <0x000000a4>; + phandle = <0x0000001a>; + }; + }; + }; + }; + rkisp-vir1 { + compatible = "rockchip,rv1126-rkisp-vir"; + rockchip,hw = <0x000000a2>; + status = "disabled"; + phandle = <0x00000129>; + ports { + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + port@1 { + reg = <0x00000001>; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + endpoint@1 { + reg = <0x00000001>; + remote-endpoint = <0x000000a5>; + phandle = <0x000000aa>; + }; + }; + }; + }; + rkisp-vir2 { + compatible = "rockchip,rv1126-rkisp-vir"; + rockchip,hw = <0x000000a2>; + status = "disabled"; + phandle = <0x0000012a>; + ports { + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + port@1 { + reg = <0x00000001>; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + endpoint@1 { + reg = <0x00000001>; + remote-endpoint = <0x000000a6>; + phandle = <0x000000ab>; + }; + }; + }; + }; + rkispp@ffb60000 { + compatible = "rockchip,rv1126-rkispp"; + reg = <0xffb60000 0x00020000>; + interrupts = <0x00000000 0x0000003f 0x00000004 0x00000000 0x00000040 0x00000004>; + interrupt-names = "ispp_irq", "fec_irq"; + clocks = <0x00000002 0x000000ba 0x00000002 0x000000e1 0x00000002 0x0000006b>; + clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp"; + assigned-clocks = <0x00000002 0x000000ba 0x00000002 0x000000e1 0x00000002 0x0000006b>; + assigned-clock-rates = <0x1dcd6500 0x0ee6b280 0x17d78400>; + power-domains = <0x00000054 0x0000000b>; + iommus = <0x000000a7>; + rockchip,restart-monitor-en; + status = "okay"; + phandle = <0x000000a8>; + }; + iommu@ffb60e00 { + compatible = "rockchip,iommu"; + reg = <0xffb60e00 0x00000040 0xffb60e40 0x00000040 0xffb60f00 0x00000040>; + interrupts = <0x00000000 0x00000041 0x00000004 0x00000000 0x00000042 0x00000004 0x00000000 0x00000043 0x00000004>; + interrupt-names = "ispp_mmu0_r", "ispp_mmu0_w", "ispp_mmu1"; + clocks = <0x00000002 0x000000ba 0x00000002 0x000000e1>; + clock-names = "aclk", "iface"; + power-domains = <0x00000054 0x0000000b>; + #iommu-cells = <0x00000000>; + rockchip,disable-mmu-reset; + status = "okay"; + phandle = <0x000000a7>; + }; + rkispp-vir0 { + compatible = "rockchip,rv1126-rkispp-vir"; + rockchip,hw = <0x000000a8>; + status = "okay"; + phandle = <0x0000012b>; + port { + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + endpoint@0 { + reg = <0x00000000>; + remote-endpoint = <0x000000a9>; + phandle = <0x000000a3>; + }; + }; + }; + rkispp-vir1 { + compatible = "rockchip,rv1126-rkispp-vir"; + rockchip,hw = <0x000000a8>; + status = "disabled"; + phandle = <0x0000012c>; + port { + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + endpoint@0 { + reg = <0x00000000>; + remote-endpoint = <0x000000aa>; + phandle = <0x000000a5>; + }; + }; + }; + rkispp-vir2 { + compatible = "rockchip,rv1126-rkispp-vir"; + rockchip,hw = <0x000000a8>; + status = "disabled"; + phandle = <0x0000012d>; + port { + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + endpoint@0 { + reg = <0x00000000>; + remote-endpoint = <0x000000ab>; + phandle = <0x000000a6>; + }; + }; + }; + rkvdec@ffb80000 { + compatible = "rockchip,rkv-decoder-v1"; + reg = <0xffb80000 0x00000400>; + interrupts = <0x00000000 0x00000047 0x00000004>; + interrupt-names = "irq_dec"; + clocks = <0x00000002 0x000000ab 0x00000002 0x000000d6 0x00000002 0x00000058 0x00000002 0x00000057 0x00000002 0x00000059>; + clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core", "clk_hevc_cabac"; + resets = <0x00000002 0x00000077 0x00000002 0x00000078 0x00000002 0x0000007a 0x00000002 0x00000079 0x00000002 0x0000007b>; + reset-names = "video_a", "video_h", "video_cabac", "video_core", "video_hevc_cabac"; + power-domains = <0x00000054 0x0000000c>; + iommus = <0x000000ac>; + rockchip,srv = <0x0000009e>; + rockchip,taskqueue-node = <0x00000000>; + rockchip,resetgroup-node = <0x00000000>; + status = "okay"; + phandle = <0x0000012e>; + }; + iommu@ffb80480 { + compatible = "rockchip,iommu"; + reg = <0xffb80480 0x00000040 0xffb804c0 0x00000040>; + interrupts = <0x00000000 0x00000048 0x00000004>; + interrupt-names = "rkvdec_mmu"; + clocks = <0x00000002 0x000000ab 0x00000002 0x000000d6>; + clock-names = "aclk", "iface"; + power-domains = <0x00000054 0x0000000c>; + #iommu-cells = <0x00000000>; + status = "okay"; + phandle = <0x000000ac>; + }; + vepu@ffb90000 { + compatible = "rockchip,vpu-encoder-v2"; + reg = <0xffb90000 0x00000400>; + interrupts = <0x00000000 0x0000004a 0x00000004>; + clocks = <0x00000002 0x000000ac 0x00000002 0x000000d7>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,normal-rates = <0x17d78400 0x00000000>; + rockchip,advanced-rates = <0x1dcd6500 0x00000000>; + rockchip,default-max-load = <0x001fe000>; + resets = <0x00000002 0x0000007e 0x00000002 0x0000007f>; + reset-names = "shared_video_a", "shared_video_h"; + iommus = <0x000000ad>; + rockchip,srv = <0x0000009e>; + rockchip,taskqueue-node = <0x00000001>; + rockchip,resetgroup-node = <0x00000001>; + power-domains = <0x00000054 0x0000000c>; + status = "okay"; + phandle = <0x0000012f>; + }; + vdpu@ffb90400 { + compatible = "rockchip,vpu-decoder-v2"; + reg = <0xffb90400 0x00000400>; + interrupts = <0x00000000 0x00000049 0x00000004>; + interrupt-names = "irq_dec"; + clocks = <0x00000002 0x000000ac 0x00000002 0x000000d7>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + resets = <0x00000002 0x0000007e 0x00000002 0x0000007f>; + reset-names = "shared_video_a", "shared_video_h"; + iommus = <0x000000ad>; + power-domains = <0x00000054 0x0000000c>; + rockchip,srv = <0x0000009e>; + rockchip,taskqueue-node = <0x00000001>; + rockchip,resetgroup-node = <0x00000001>; + status = "okay"; + phandle = <0x00000130>; + }; + iommu@ffb90800 { + compatible = "rockchip,iommu"; + reg = <0xffb90800 0x00000040>; + interrupts = <0x00000000 0x0000004b 0x00000004>; + interrupt-names = "vpu_mmu"; + clock-names = "aclk", "iface"; + clocks = <0x00000002 0x000000ac 0x00000002 0x000000d7>; + power-domains = <0x00000054 0x0000000c>; + #iommu-cells = <0x00000000>; + status = "okay"; + phandle = <0x000000ad>; + }; + rkvenc@ffbb0000 { + compatible = "rockchip,rkv-encoder-v1"; + reg = <0xffbb0000 0x00000400>; + interrupts = <0x00000000 0x00000044 0x00000004>; + interrupt-names = "irq_enc"; + clocks = <0x00000002 0x000000a8 0x00000002 0x000000d3 0x00000002 0x00000056>; + clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; + rockchip,normal-rates = <0x11e1a300 0x00000000 0x2367b880>; + rockchip,advanced-rates = <0x11e1a300 0x00000000 0x2367b880>; + rockchip,default-max-load = <0x000e1000>; + resets = <0x00000002 0x00000072 0x00000002 0x00000073 0x00000002 0x00000074>; + reset-names = "video_a", "video_h", "video_core"; + assigned-clocks = <0x00000002 0x000000a8 0x00000002 0x00000056>; + assigned-clock-rates = <0x11b3dc40 0x2367b880>; + operating-points-v2 = <0x000000ae>; + dynamic-power-coefficient = <0x0000058a>; + #cooling-cells = <0x00000002>; + iommus = <0x000000af>; + node-name = "rkvenc"; + rockchip,srv = <0x0000009e>; + rockchip,taskqueue-node = <0x00000002>; + rockchip,resetgroup-node = <0x00000002>; + power-domains = <0x00000054 0x00000008>; + status = "okay"; + venc-supply = <0x000000b0>; + phandle = <0x0000001e>; + }; + rkvenc-opp-table { + compatible = "operating-points-v2"; + nvmem-cells = <0x000000b1 0x000000b2>; + nvmem-cell-names = "leakage", "performance"; + rockchip,temp-freq-table = <0x00017318 0x0007a120 0x000186a0 0x00060ae0>; + clocks = <0x00000038 0x00000001>; + rockchip,bin-scaling-sel = <0x00000000 0x00000025 0x00000001 0x00000028>; + rockchip,bin-voltage-sel = <0x00000001 0x00000000>; + rockchip,evb-irdrop = <0x000061a8>; + phandle = <0x000000ae>; + opp-297000000 { + opp-hz = <0x00000000 0x11b3dc40>; + opp-microvolt = <0x000b1008 0x000b1008 0x000f4240>; + opp-microvolt-L0 = <0x000b71b0 0x000b71b0 0x000f4240>; + }; + opp-396000000 { + opp-hz = <0x00000000 0x179a7b00>; + opp-microvolt = <0x000b1008 0x000b1008 0x000f4240>; + opp-microvolt-L0 = <0x000bd358 0x000bd358 0x000f4240>; + }; + opp-500000000 { + opp-hz = <0x00000000 0x1dcd6500>; + opp-microvolt = <0x000b71b0 0x000b71b0 0x000f4240>; + opp-microvolt-L0 = <0x000c3500 0x000c3500 0x000f4240>; + }; + opp-594000000 { + opp-hz = <0x00000000 0x2367b880>; + opp-microvolt = <0x000c96a8 0x000c96a8 0x000f4240>; + }; + }; + iommu@ffbb0f00 { + compatible = "rockchip,iommu"; + reg = <0xffbb0f00 0x00000040 0xffbb0f40 0x00000040>; + interrupts = <0x00000000 0x00000045 0x00000004 0x00000000 0x00000046 0x00000004>; + interrupt-names = "rkvenc_mmu0", "rkvenc_mmu1"; + clocks = <0x00000002 0x000000a8 0x00000002 0x000000d3>; + clock-names = "aclk", "iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + #iommu-cells = <0x00000000>; + power-domains = <0x00000054 0x00000008>; + status = "okay"; + phandle = <0x000000af>; + }; + pvtm@ffc00000 { + compatible = "rockchip,rv1126-npu-pvtm"; + reg = <0xffc00000 0x00000100>; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + pvtm@1 { + reg = <0x00000001>; + clocks = <0x00000002 0x00000092 0x00000002 0x0000011a>; + clock-names = "clk", "pclk"; + resets = <0x00000002 0x000000d7 0x00000002 0x000000d6>; + reset-names = "rts", "rst-p"; + }; + }; + ethernet@ffc40000 { + compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a"; + reg = <0xffc40000 0x0000ffff>; + interrupts = <0x00000000 0x0000005f 0x00000004 0x00000000 0x00000060 0x00000004>; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <0x00000050>; + clocks = <0x00000002 0x0000007e 0x00000002 0x00000088 0x00000002 0x00000088 0x00000002 0x0000007f 0x00000002 0x000000bf 0x00000002 0x00000116 0x00000002 0x00000088 0x00000002 0x00000089>; + clock-names = "stmmaceth", "mac_clk_rx", "mac_clk_tx", "clk_mac_ref", "aclk_mac", "pclk_mac", "clk_mac_speed", "ptp_ref"; + resets = <0x00000002 0x000000be>; + reset-names = "stmmaceth"; + snps,mixed-burst; + snps,tso; + snps,axi-config = <0x000000b3>; + snps,mtl-rx-config = <0x000000b4>; + snps,mtl-tx-config = <0x000000b5>; + status = "okay"; + phy-mode = "rmii"; + clock_in_out = "output"; + snps,reset-gpio = <0x000000b6 0x00000015 0x00000001>; + snps,reset-active-low; + snps,reset-delays-us = <0x00000000 0x0000c350 0x00002710>; + assigned-clocks = <0x00000002 0x0000007b 0x00000002 0x0000007e 0x00000002 0x00000088>; + assigned-clock-rates = <0x00000000 0x02faf080>; + assigned-clock-parents = <0x00000002 0x0000007a 0x00000002 0x0000007b 0x00000002 0x00000087>; + pinctrl-names = "default"; + pinctrl-0 = <0x000000b7 0x000000b8>; + phy-handle = <0x000000b9>; + phandle = <0x00000131>; + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + phandle = <0x00000132>; + phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x00000001>; + phandle = <0x000000b9>; + }; + }; + stmmac-axi-config { + snps,wr_osr_lmt = <0x00000004>; + snps,rd_osr_lmt = <0x00000008>; + snps,blen = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000010 0x00000008 0x00000004>; + phandle = <0x000000b3>; + }; + rx-queues-config { + snps,rx-queues-to-use = <0x00000001>; + phandle = <0x000000b4>; + queue0 { + }; + }; + tx-queues-config { + snps,tx-queues-to-use = <0x00000001>; + phandle = <0x000000b5>; + queue0 { + }; + }; + }; + dwmmc@ffc50000 { + compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0xffc50000 0x00004000>; + interrupts = <0x00000000 0x0000004e 0x00000004>; + clocks = <0x00000002 0x000000e8 0x00000002 0x00000072 0x00000002 0x00000073 0x00000002 0x00000074>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x00000100>; + max-frequency = <0x0bebc200>; + power-domains = <0x00000054 0x0000000f>; + rockchip,use-v2-tuning; + status = "okay"; + bus-width = <0x00000008>; + cap-mmc-highspeed; + non-removable; + mmc-hs200-1_8v; + rockchip,default-sample-phase = <0x0000005a>; + supports-emmc; + phandle = <0x00000133>; + }; + dwmmc@ffc60000 { + compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0xffc60000 0x00004000>; + interrupts = <0x00000000 0x0000004c 0x00000004>; + clocks = <0x00000002 0x000000e4 0x00000002 0x0000006c 0x00000002 0x0000006d 0x00000002 0x0000006e>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x00000100>; + max-frequency = <0x0bebc200>; + pinctrl-names = "default"; + pinctrl-0 = <0x000000ba 0x000000bb 0x000000bc 0x000000bd>; + status = "okay"; + bus-width = <0x00000004>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <0x000000c8>; + rockchip,default-sample-phase = <0x0000005a>; + supports-sd; + vmmc-supply = <0x000000be>; + phandle = <0x00000134>; + }; + dwmmc@ffc70000 { + compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0xffc70000 0x00004000>; + interrupts = <0x00000000 0x0000004d 0x00000004>; + clocks = <0x00000002 0x000000e6 0x00000002 0x0000006f 0x00000002 0x00000070 0x00000002 0x00000071>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x00000100>; + max-frequency = <0x0bebc200>; + pinctrl-names = "default"; + pinctrl-0 = <0x000000bf 0x000000c0 0x000000c1>; + power-domains = <0x00000054 0x00000010>; + status = "disabled"; + phandle = <0x00000135>; + }; + nandc@ffc80000 { + compatible = "rockchip,rk-nandc"; + reg = <0xffc80000 0x00004000>; + interrupts = <0x00000000 0x0000004f 0x00000004>; + nandc_id = <0x00000000>; + clocks = <0x00000002 0x00000075 0x00000002 0x000000e9>; + clock-names = "clk_nandc", "hclk_nandc"; + power-domains = <0x00000054 0x0000000f>; + status = "disabled"; + #address-cells = <0x00000001>; + #size-cells = <0x00000000>; + phandle = <0x00000136>; + nand@0 { + reg = <0x00000000>; + nand-bus-width = <0x00000008>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <0x00000010>; + nand-ecc-step-size = <0x00000400>; + }; + }; + sfc@ffc90000 { + compatible = "rockchip,sfc"; + reg = <0xffc90000 0x00004000>; + interrupts = <0x00000000 0x00000050 0x00000004>; + clocks = <0x00000002 0x00000076 0x00000002 0x000000ea>; + clock-names = "clk_sfc", "hclk_sfc"; + assigned-clocks = <0x00000002 0x00000076>; + assigned-clock-rates = <0x04c4b400>; + power-domains = <0x00000054 0x0000000f>; + status = "okay"; + phandle = <0x00000137>; + }; + npu@ffbc0000 { + compatible = "rockchip,npu"; + reg = <0xffbc0000 0x00004000>; + clocks = <0x00000002 0x000000c3 0x00000002 0x000000f0 0x00000002 0x00000119 0x00000002 0x00000090>; + clock-names = "aclk_npu", "hclk_npu", "pclk_pdnpu", "sclk_npu"; + assigned-clocks = <0x00000002 0x00000090 0x00000002 0x000000c3>; + assigned-clock-rates = <0x179a7b00 0x23c34600>; + operating-points-v2 = <0x000000c2>; + dynamic-power-coefficient = <0x0000053f>; + #cooling-cells = <0x00000002>; + interrupts = <0x00000000 0x0000006b 0x00000004>; + power-domains = <0x00000054 0x00000007>; + status = "okay"; + npu-supply = <0x000000b0>; + phandle = <0x0000001d>; + }; + npu-opp-table { + compatible = "operating-points-v2"; + nvmem-cells = <0x000000c3 0x000000c4>; + nvmem-cell-names = "leakage", "performance"; + rockchip,temp-freq-table = <0x00013880 0x000927c0 0x00015f90 0x00060ae0 0x000186a0 0x000493e0>; + clocks = <0x00000038 0x00000001>; + rockchip,bin-scaling-sel = <0x00000000 0x00000017 0x00000001 0x00000025 0x00000002 0x00000025>; + rockchip,bin-voltage-sel = <0x00000002 0x00000000>; + rockchip,pvtm-voltage-sel = <0x00000000 0x0001a7d4 0x00000001 0x0001a7d5 0x0001bb5c 0x00000002 0x0001bb5d 0x000f423f 0x00000003>; + rockchip,pvtm-freq = <0x00060ae0>; + rockchip,pvtm-volt = <0x000c3500>; + rockchip,pvtm-ch = <0x00000001 0x00000000>; + rockchip,pvtm-sample-time = <0x000003e8>; + rockchip,pvtm-number = <0x0000000a>; + rockchip,pvtm-error = <0x000003e8>; + rockchip,pvtm-ref-temp = <0x00000025>; + rockchip,pvtm-temp-prop = <0xffffffe3 0x00000000>; + rockchip,pvtm-thermal-zone = "npu-thermal"; + phandle = <0x000000c2>; + opp-200000000 { + opp-hz = <0x00000000 0x0bebc200>; + opp-microvolt = <0x000b1008 0x000b1008 0x000f4240>; + opp-microvolt-L0 = <0x000b1008 0x000b1008 0x000f4240>; + }; + opp-300000000 { + opp-hz = <0x00000000 0x11e1a300>; + opp-microvolt = <0x000b1008 0x000b1008 0x000f4240>; + opp-microvolt-L0 = <0x000b1008 0x000b1008 0x000f4240>; + }; + opp-396000000 { + opp-hz = <0x00000000 0x179a7b00>; + opp-microvolt = <0x000b1008 0x000b1008 0x000f4240>; + opp-microvolt-L0 = <0x000b71b0 0x000b71b0 0x000f4240>; + }; + opp-500000000 { + opp-hz = <0x00000000 0x1dcd6500>; + opp-microvolt = <0x000b1008 0x000b1008 0x000f4240>; + opp-microvolt-L0 = <0x000b71b0 0x000b71b0 0x000f4240>; + }; + opp-600000000 { + opp-hz = <0x00000000 0x23c34600>; + opp-microvolt = <0x000b71b0 0x000b71b0 0x000f4240>; + opp-microvolt-L0 = <0x000bd358 0x000bd358 0x000f4240>; + }; + opp-700000000 { + opp-hz = <0x00000000 0x29b92700>; + opp-microvolt = <0x000c3500 0x000c3500 0x000f4240>; + opp-microvolt-L1 = <0x000c3500 0x000c3500 0x000f4240>; + opp-microvolt-L2 = <0x000bd358 0x000bd358 0x000f4240>; + opp-microvolt-L3 = <0x000b71b0 0x000b71b0 0x000f4240>; + }; + }; + usb0 { + compatible = "rockchip,rv1126-dwc3", "rockchip,rk3399-dwc3"; + #address-cells = <0x00000001>; + #size-cells = <0x00000001>; + ranges; + clocks = <0x00000002 0x00000078 0x00000002 0x000000bd 0x00000002 0x000000c9>; + clock-names = "ref_clk", "bus_clk", "hclk"; + status = "okay"; + phandle = <0x00000138>; + dwc3@ffd00000 { + compatible = "snps,dwc3"; + reg = <0xffd00000 0x00100000>; + interrupts = <0x00000000 0x00000055 0x00000004>; + dr_mode = "otg"; + maximum-speed = "high-speed"; + phys = <0x000000c5>; + phy-names = "usb2-phy"; + phy_type = "utmi_wide"; + power-domains = <0x00000054 0x00000011>; + resets = <0x00000002 0x000000b5>; + reset-names = "usb3-otg"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,tx-ipgap-linecheck-dis-quirk; + snps,tx-fifo-resize; + snps,xhci-trb-ent-quirk; + status = "okay"; + extcon = <0x000000c6>; + phandle = <0x00000139>; + }; + }; + usb@ffe00000 { + compatible = "generic-ehci"; + reg = <0xffe00000 0x00010000>; + interrupts = <0x00000000 0x00000052 0x00000004>; + clocks = <0x00000002 0x000000ed 0x00000002 0x000000ee 0x00000053>; + clock-names = "usbhost", "arbiter", "utmi"; + phys = <0x000000c7>; + phy-names = "usb"; + power-domains = <0x00000054 0x00000011>; + status = "okay"; + phandle = <0x0000013a>; + }; + usb@ffe10000 { + compatible = "generic-ohci"; + reg = <0xffe10000 0x00010000>; + interrupts = <0x00000000 0x00000053 0x00000004>; + clocks = <0x00000002 0x000000ed 0x00000002 0x000000ee 0x00000053>; + clock-names = "usbhost", "arbiter", "utmi"; + phys = <0x000000c7>; + phy-names = "usb"; + power-domains = <0x00000054 0x00000011>; + status = "okay"; + phandle = <0x0000013b>; + }; + pinctrl { + compatible = "rockchip,rv1126-pinctrl"; + rockchip,grf = <0x00000050>; + rockchip,pmu = <0x0000003a>; + #address-cells = <0x00000001>; + #size-cells = <0x00000001>; + ranges; + phandle = <0x0000013c>; + gpio0@ff460000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff460000 0x00000100>; + interrupts = <0x00000000 0x00000022 0x00000004>; + clocks = <0x00000038 0x00000026 0x00000038 0x00000013>; + gpio-controller; + #gpio-cells = <0x00000002>; + interrupt-controller; + #interrupt-cells = <0x00000002>; + phandle = <0x000000d5>; + }; + gpio1@ff620000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff620000 0x00000100>; + interrupts = <0x00000000 0x00000023 0x00000004>; + clocks = <0x00000002 0x00000106 0x00000002 0x00000028>; + gpio-controller; + #gpio-cells = <0x00000002>; + interrupt-controller; + #interrupt-cells = <0x00000002>; + phandle = <0x00000058>; + }; + gpio2@ff630000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff630000 0x00000100>; + interrupts = <0x00000000 0x00000024 0x00000004>; + clocks = <0x00000002 0x00000107 0x00000002 0x00000029>; + gpio-controller; + #gpio-cells = <0x00000002>; + interrupt-controller; + #interrupt-cells = <0x00000002>; + phandle = <0x00000061>; + }; + gpio3@ff640000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff640000 0x00000100>; + interrupts = <0x00000000 0x00000025 0x00000004>; + clocks = <0x00000002 0x00000108 0x00000002 0x0000002a>; + gpio-controller; + #gpio-cells = <0x00000002>; + interrupt-controller; + #interrupt-cells = <0x00000002>; + phandle = <0x000000b6>; + }; + gpio4@ff650000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff650000 0x00000100>; + interrupts = <0x00000000 0x00000026 0x00000004>; + clocks = <0x00000002 0x00000109 0x00000002 0x0000002b>; + gpio-controller; + #gpio-cells = <0x00000002>; + interrupt-controller; + #interrupt-cells = <0x00000002>; + phandle = <0x0000013d>; + }; + pcfg-pull-up { + bias-pull-up; + phandle = <0x000000cb>; + }; + pcfg-pull-down { + bias-pull-down; + phandle = <0x000000ca>; + }; + pcfg-pull-none { + bias-disable; + phandle = <0x000000c8>; + }; + pcfg-pull-none-drv-level-0 { + bias-disable; + drive-strength = <0x00000000>; + phandle = <0x000000cd>; + }; + pcfg-pull-none-drv-level-2 { + bias-disable; + drive-strength = <0x00000002>; + phandle = <0x000000cf>; + }; + pcfg-pull-none-drv-level-3 { + bias-disable; + drive-strength = <0x00000003>; + phandle = <0x000000d1>; + }; + pcfg-pull-none-drv-level-8 { + bias-disable; + drive-strength = <0x00000008>; + phandle = <0x000000ce>; + }; + pcfg-pull-up-drv-level-0 { + bias-pull-up; + drive-strength = <0x00000000>; + phandle = <0x000000d2>; + }; + pcfg-pull-up-drv-level-1 { + bias-pull-up; + drive-strength = <0x00000001>; + phandle = <0x000000d4>; + }; + pcfg-pull-up-drv-level-2 { + bias-pull-up; + drive-strength = <0x00000002>; + phandle = <0x000000c9>; + }; + pcfg-pull-up-drv-level-3 { + bias-pull-up; + drive-strength = <0x00000003>; + phandle = <0x000000d3>; + }; + pcfg-pull-none-drv-level-0-smt { + bias-disable; + drive-strength = <0x00000000>; + input-schmitt-enable; + phandle = <0x000000cc>; + }; + pcfg-output-low { + output-low; + phandle = <0x000000d0>; + }; + acodec { + acodec-pins { + rockchip,pins = <0x00000003 0x00000019 0x00000003 0x000000c8 0x00000003 0x0000001f 0x00000003 0x000000c8 0x00000003 0x0000001c 0x00000003 0x000000c8 0x00000003 0x00000018 0x00000003 0x000000c8 0x00000003 0x0000001e 0x00000003 0x000000c8 0x00000003 0x0000001d 0x00000003 0x000000c8 0x00000003 0x0000001b 0x00000003 0x000000c8>; + phandle = <0x00000096>; + }; + }; + audpwm { + audpwmm0-pins { + rockchip,pins = <0x00000004 0x00000000 0x00000003 0x000000c8 0x00000004 0x00000001 0x00000003 0x000000c8>; + phandle = <0x00000095>; + }; + }; + i2c0 { + i2c0-xfer { + rockchip,pins = <0x00000000 0x0000000c 0x00000001 0x000000cc 0x00000000 0x0000000d 0x00000001 0x000000cc>; + phandle = <0x00000039>; + }; + }; + i2c1 { + i2c1-xfer { + rockchip,pins = <0x00000001 0x0000001b 0x00000001 0x000000cc 0x00000001 0x0000001a 0x00000001 0x000000cc>; + phandle = <0x00000055>; + }; + }; + i2c2 { + i2c2-xfer { + rockchip,pins = <0x00000000 0x00000012 0x00000001 0x000000cc 0x00000000 0x00000013 0x00000001 0x000000cc>; + phandle = <0x0000003b>; + }; + }; + i2c3 { + i2c3m0-xfer { + rockchip,pins = <0x00000003 0x00000004 0x00000005 0x000000cc 0x00000003 0x00000005 0x00000005 0x000000cc>; + phandle = <0x0000005d>; + }; + }; + i2c4 { + i2c4m1-xfer { + rockchip,pins = <0x00000004 0x00000000 0x00000004 0x000000cc 0x00000004 0x00000001 0x00000004 0x000000cc>; + phandle = <0x0000005e>; + }; + }; + i2c5 { + i2c5m0-xfer { + rockchip,pins = <0x00000002 0x00000005 0x00000007 0x000000cc 0x00000002 0x0000000b 0x00000007 0x000000cc>; + phandle = <0x00000062>; + }; + }; + i2s0 { + i2s0m0-lrck-tx { + rockchip,pins = <0x00000003 0x0000001b 0x00000001 0x000000cd>; + phandle = <0x00000084>; + }; + i2s0m0-mclk { + rockchip,pins = <0x00000003 0x0000001a 0x00000001 0x000000cd>; + phandle = <0x0000005f>; + }; + i2s0m0-sclk-tx { + rockchip,pins = <0x00000003 0x00000018 0x00000001 0x000000cd>; + phandle = <0x00000083>; + }; + i2s0m0-sdi0 { + rockchip,pins = <0x00000003 0x0000001e 0x00000001 0x000000cd>; + phandle = <0x00000085>; + }; + i2s0m0-sdo0 { + rockchip,pins = <0x00000003 0x0000001d 0x00000001 0x000000cd>; + phandle = <0x00000086>; + }; + }; + i2s1 { + i2s1m0-lrck { + rockchip,pins = <0x00000001 0x00000000 0x00000004 0x000000c8>; + phandle = <0x00000088>; + }; + i2s1m0-sclk { + rockchip,pins = <0x00000001 0x00000001 0x00000004 0x000000c8>; + phandle = <0x00000087>; + }; + i2s1m0-sdi { + rockchip,pins = <0x00000001 0x00000002 0x00000004 0x000000c8>; + phandle = <0x00000089>; + }; + i2s1m0-sdo { + rockchip,pins = <0x00000000 0x0000001e 0x00000004 0x000000c8>; + phandle = <0x0000008a>; + }; + }; + i2s2 { + i2s2m0-lrck { + rockchip,pins = <0x00000001 0x00000017 0x00000001 0x000000c8>; + phandle = <0x0000008c>; + }; + i2s2m0-sclk { + rockchip,pins = <0x00000001 0x00000016 0x00000001 0x000000c8>; + phandle = <0x0000008b>; + }; + i2s2m0-sdi { + rockchip,pins = <0x00000001 0x00000015 0x00000001 0x000000c8>; + phandle = <0x0000008d>; + }; + i2s2m0-sdo { + rockchip,pins = <0x00000001 0x00000014 0x00000001 0x000000c8>; + phandle = <0x0000008e>; + }; + }; + mipicsi { + mipi-csi-clk0 { + rockchip,pins = <0x00000002 0x00000003 0x00000001 0x000000c8>; + phandle = <0x00000056>; + }; + }; + pdm { + pdmm0-clk { + rockchip,pins = <0x00000003 0x0000001c 0x00000002 0x000000c8>; + phandle = <0x0000008f>; + }; + pdmm0-clk1 { + rockchip,pins = <0x00000003 0x00000019 0x00000002 0x000000c8>; + phandle = <0x00000090>; + }; + pdmm0-sdi0 { + rockchip,pins = <0x00000003 0x0000001e 0x00000002 0x000000c8>; + phandle = <0x00000091>; + }; + pdmm0-sdi1 { + rockchip,pins = <0x00000004 0x00000001 0x00000002 0x000000c8>; + phandle = <0x00000092>; + }; + pdmm0-sdi2 { + rockchip,pins = <0x00000004 0x00000000 0x00000002 0x000000c8>; + phandle = <0x00000093>; + }; + pdmm0-sdi3 { + rockchip,pins = <0x00000003 0x0000001f 0x00000002 0x000000c8>; + phandle = <0x00000094>; + }; + }; + pwm0 { + pwm0m0-pins-pull-down { + rockchip,pins = <0x00000000 0x0000000e 0x00000003 0x000000ca>; + phandle = <0x00000040>; + }; + }; + pwm1 { + pwm1m0-pins-pull-down { + rockchip,pins = <0x00000000 0x0000000f 0x00000003 0x000000ca>; + phandle = <0x00000041>; + }; + }; + pwm10 { + pwm10m0-pins { + rockchip,pins = <0x00000003 0x00000006 0x00000006 0x000000c8>; + phandle = <0x00000065>; + }; + }; + pwm11 { + pwm11m0-pins { + rockchip,pins = <0x00000003 0x00000007 0x00000006 0x000000c8>; + phandle = <0x00000066>; + }; + }; + pwm2 { + pwm2m0-pins { + rockchip,pins = <0x00000000 0x00000010 0x00000003 0x000000c8>; + phandle = <0x00000042>; + }; + }; + pwm3 { + pwm3m0-pins-pull-down { + rockchip,pins = <0x00000000 0x00000011 0x00000003 0x000000ca>; + phandle = <0x00000043>; + }; + }; + pwm4 { + pwm4m0-pins { + rockchip,pins = <0x00000000 0x00000012 0x00000003 0x000000c8>; + phandle = <0x00000044>; + }; + }; + pwm5 { + pwm5m0-pins { + rockchip,pins = <0x00000000 0x00000013 0x00000003 0x000000c8>; + phandle = <0x00000045>; + }; + }; + pwm6 { + pwm6m0-pins-pull-down { + rockchip,pins = <0x00000000 0x0000000a 0x00000003 0x000000ca>; + phandle = <0x00000046>; + }; + }; + pwm7 { + pwm7m0-pins { + rockchip,pins = <0x00000000 0x00000009 0x00000003 0x000000c8>; + phandle = <0x00000047>; + }; + }; + pwm8 { + pwm8m0-pins { + rockchip,pins = <0x00000003 0x00000004 0x00000006 0x000000c8>; + phandle = <0x00000063>; + }; + }; + pwm9 { + pwm9m0-pins { + rockchip,pins = <0x00000003 0x00000005 0x00000006 0x000000c8>; + phandle = <0x00000064>; + }; + }; + rmii { + rmiim0-pins { + rockchip,pins = <0x00000003 0x00000014 0x00000002 0x000000cd 0x00000003 0x00000013 0x00000002 0x000000c8 0x00000003 0x0000000e 0x00000002 0x000000c8 0x00000003 0x0000000f 0x00000002 0x000000c8 0x00000003 0x00000011 0x00000002 0x000000c8 0x00000003 0x00000012 0x00000002 0x000000c8 0x00000003 0x0000000b 0x00000002 0x000000cd 0x00000003 0x0000000c 0x00000002 0x000000cd 0x00000003 0x0000000d 0x00000002 0x000000cd>; + phandle = <0x000000b7>; + }; + }; + gmac_clk { + gmac-clk-m0-pins { + rockchip,pins = <0x00000003 0x00000010 0x00000002 0x000000c8>; + phandle = <0x000000b8>; + }; + }; + sdmmc0 { + sdmmc0-bus4 { + rockchip,pins = <0x00000001 0x00000004 0x00000001 0x000000d2 0x00000001 0x00000005 0x00000001 0x000000d2 0x00000001 0x00000006 0x00000001 0x000000d2 0x00000001 0x00000007 0x00000001 0x000000d2>; + phandle = <0x000000bd>; + }; + sdmmc0-clk { + rockchip,pins = <0x00000001 0x00000008 0x00000001 0x000000d3>; + phandle = <0x000000ba>; + }; + sdmmc0-cmd { + rockchip,pins = <0x00000001 0x00000009 0x00000001 0x000000d2>; + phandle = <0x000000bb>; + }; + sdmmc0-det { + rockchip,pins = <0x00000000 0x00000003 0x00000001 0x000000c8>; + phandle = <0x000000bc>; + }; + }; + sdmmc1 { + sdmmc1-bus4 { + rockchip,pins = <0x00000001 0x0000000c 0x00000001 0x000000c9 0x00000001 0x0000000d 0x00000001 0x000000c9 0x00000001 0x0000000e 0x00000001 0x000000c9 0x00000001 0x0000000f 0x00000001 0x000000c9>; + phandle = <0x000000c1>; + }; + sdmmc1-clk { + rockchip,pins = <0x00000001 0x0000000a 0x00000001 0x000000c9>; + phandle = <0x000000bf>; + }; + sdmmc1-cmd { + rockchip,pins = <0x00000001 0x0000000b 0x00000001 0x000000c9>; + phandle = <0x000000c0>; + }; + }; + spi0 { + spi0m0-clk { + rockchip,pins = <0x00000000 0x00000008 0x00000001 0x000000d2>; + phandle = <0x00000048>; + }; + spi0m0-cs0n { + rockchip,pins = <0x00000000 0x00000005 0x00000001 0x000000d2>; + phandle = <0x00000049>; + }; + spi0m0-cs1n { + rockchip,pins = <0x00000000 0x00000004 0x00000001 0x000000d2>; + phandle = <0x0000004a>; + }; + spi0m0-miso { + rockchip,pins = <0x00000000 0x00000007 0x00000001 0x000000d2>; + phandle = <0x0000004b>; + }; + spi0m0-mosi { + rockchip,pins = <0x00000000 0x00000006 0x00000001 0x000000d2>; + phandle = <0x0000004c>; + }; + spi0m0-clk_hs { + rockchip,pins = <0x00000000 0x00000008 0x00000001 0x000000d4>; + phandle = <0x0000004d>; + }; + spi0m0-miso_hs { + rockchip,pins = <0x00000000 0x00000007 0x00000001 0x000000d4>; + phandle = <0x0000004e>; + }; + spi0m0-mosi_hs { + rockchip,pins = <0x00000000 0x00000006 0x00000001 0x000000d4>; + phandle = <0x0000004f>; + }; + }; + spi1 { + spi1m0-clk { + rockchip,pins = <0x00000003 0x00000010 0x00000005 0x000000d2>; + phandle = <0x00000074>; + }; + spi1m0-cs0n { + rockchip,pins = <0x00000003 0x0000000d 0x00000005 0x000000d2>; + phandle = <0x00000075>; + }; + spi1m0-cs1n { + rockchip,pins = <0x00000003 0x0000000c 0x00000005 0x000000d2>; + phandle = <0x00000076>; + }; + spi1m0-miso { + rockchip,pins = <0x00000003 0x0000000f 0x00000005 0x000000d2>; + phandle = <0x00000077>; + }; + spi1m0-mosi { + rockchip,pins = <0x00000003 0x0000000e 0x00000005 0x000000d2>; + phandle = <0x00000078>; + }; + spi1m0-clk_hs { + rockchip,pins = <0x00000003 0x00000010 0x00000005 0x000000d4>; + phandle = <0x00000079>; + }; + spi1m0-miso_hs { + rockchip,pins = <0x00000003 0x0000000f 0x00000005 0x000000d4>; + phandle = <0x0000007a>; + }; + spi1m0-mosi_hs { + rockchip,pins = <0x00000003 0x0000000e 0x00000005 0x000000d4>; + phandle = <0x0000007b>; + }; + }; + tsadc { + tsadcm0-pins { + rockchip,pins = <0x00000000 0x00000001 0x00000001 0x000000c8>; + phandle = <0x0000007f>; + }; + tsadc-shutorg { + rockchip,pins = <0x00000000 0x00000001 0x00000002 0x000000c8>; + phandle = <0x00000080>; + }; + }; + uart0 { + uart0-xfer { + rockchip,pins = <0x00000001 0x00000012 0x00000001 0x000000cb 0x00000001 0x00000013 0x00000001 0x000000cb>; + phandle = <0x00000067>; + }; + uart0-ctsn { + rockchip,pins = <0x00000001 0x00000011 0x00000001 0x000000c8>; + phandle = <0x00000068>; + }; + uart0-rtsn { + rockchip,pins = <0x00000001 0x00000010 0x00000001 0x000000c8>; + phandle = <0x00000069>; + }; + }; + uart1 { + uart1m0-xfer { + rockchip,pins = <0x00000000 0x0000000f 0x00000002 0x000000cb 0x00000000 0x0000000e 0x00000002 0x000000cb>; + phandle = <0x0000003d>; + }; + uart1m0-ctsn { + rockchip,pins = <0x00000000 0x00000011 0x00000002 0x000000c8>; + phandle = <0x0000003e>; + }; + uart1m0-rtsn { + rockchip,pins = <0x00000000 0x00000010 0x00000002 0x000000c8>; + phandle = <0x0000003f>; + }; + }; + uart2 { + uart2m1-xfer { + rockchip,pins = <0x00000003 0x00000003 0x00000001 0x000000cb 0x00000003 0x00000002 0x00000001 0x000000cb>; + phandle = <0x0000006a>; + }; + }; + uart3 { + uart3m2-xfer { + rockchip,pins = <0x00000003 0x00000001 0x00000004 0x000000cb 0x00000003 0x00000000 0x00000004 0x000000cb>; + phandle = <0x0000006b>; + }; + uart3m2-ctsn { + rockchip,pins = <0x00000002 0x0000001f 0x00000004 0x000000c8>; + phandle = <0x0000006c>; + }; + uart3m2-rtsn { + rockchip,pins = <0x00000002 0x0000001e 0x00000004 0x000000c8>; + phandle = <0x0000006d>; + }; + }; + uart4 { + uart4m0-xfer { + rockchip,pins = <0x00000003 0x00000005 0x00000004 0x000000cb 0x00000003 0x00000004 0x00000004 0x000000cb>; + phandle = <0x0000006e>; + }; + uart4m0-ctsn { + rockchip,pins = <0x00000003 0x0000000b 0x00000004 0x000000c8>; + phandle = <0x0000006f>; + }; + uart4m0-rtsn { + rockchip,pins = <0x00000003 0x0000000a 0x00000004 0x000000c8>; + phandle = <0x00000070>; + }; + }; + uart5 { + uart5m0-xfer { + rockchip,pins = <0x00000003 0x00000007 0x00000004 0x000000cb 0x00000003 0x00000006 0x00000004 0x000000cb>; + phandle = <0x00000071>; + }; + uart5m0-ctsn { + rockchip,pins = <0x00000003 0x00000009 0x00000004 0x000000c8>; + phandle = <0x00000072>; + }; + uart5m0-rtsn { + rockchip,pins = <0x00000003 0x00000008 0x00000004 0x000000c8>; + phandle = <0x00000073>; + }; + }; + es8311 { + spk-ctl { + rockchip,pins = <0x00000002 0x00000005 0x00000000 0x000000c8>; + phandle = <0x00000060>; + }; + }; + sdmmc-pwr { + sdmmc-pwr { + rockchip,pins = <0x00000000 0x00000004 0x00000000 0x000000c8>; + phandle = <0x000000d6>; + }; + }; + }; + chosen { + bootargs = "earlycon=uart8250,mmio32,0xff570000 console=ttyFIQ0 ubi.mtd=7 root=ubi0:rootfs rootfstype=ubifs rootnowait snd_aloop.index=7"; + }; + vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x004c4b40>; + regulator-max-microvolt = <0x004c4b40>; + phandle = <0x0000013e>; + }; + vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x001b7740>; + regulator-max-microvolt = <0x001b7740>; + phandle = <0x00000021>; + }; + vcc-dvdd { + compatible = "regulator-fixed"; + regulator-name = "vcc_dvdd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x00124f80>; + regulator-max-microvolt = <0x00124f80>; + phandle = <0x00000057>; + }; + vcc33sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x00325aa0>; + regulator-max-microvolt = <0x00325aa0>; + phandle = <0x00000020>; + }; + vcc-sd { + compatible = "regulator-fixed"; + gpio = <0x000000d5 0x00000004 0x00000000>; + pinctrl-0 = <0x000000d6>; + pinctrl-names = "default"; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <0x00325aa0>; + regulator-max-microvolt = <0x00325aa0>; + startup-delay-us = <0x000186a0>; + vin-supply = <0x00000020>; + enable-active-high; + phandle = <0x000000be>; + }; + vdd-arm { + compatible = "pwm-regulator"; + pwms = <0x000000d7 0x00000000 0x00001388 0x00000001>; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <0x000afc80>; + regulator-max-microvolt = <0x000f4240>; + regulator-init-microvolt = <0x000c96a8>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <0x000000fa>; + pwm-supply = <0x00000020>; + status = "okay"; + phandle = <0x00000005>; + }; + vdd-logic-npu-vepu { + compatible = "pwm-regulator"; + pwms = <0x000000d8 0x00000000 0x00001388 0x00000001>; + regulator-name = "vdd_logic_npu_vepu"; + regulator-min-microvolt = <0x000afc80>; + regulator-max-microvolt = <0x000d6d80>; + regulator-init-microvolt = <0x000c96a8>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <0x000000fa>; + pwm-supply = <0x00000020>; + status = "okay"; + phandle = <0x0000013f>; + }; + vdd-logic-npu-vepu-fixed { + compatible = "regulator-fixed"; + regulator-name = "vdd_logic_npu_vepu-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <0x000c96a8>; + regulator-max-microvolt = <0x000c96a8>; + phandle = <0x000000b0>; + }; + adc-keys { + compatible = "adc-keys"; + io-channels = <0x000000d9 0x00000000>; + io-channel-names = "buttons"; + poll-interval = <0x00000064>; + keyup-threshold-microvolt = <0x001b7740>; + esc-key { + label = "esc"; + linux,code = <0x00000001>; + press-threshold-microvolt = <0x00000000>; + }; + }; + cam_ircut { + status = "okay"; + compatible = "rockchip,ircut"; + ircut-open-gpios = <0x000000b6 0x00000009 0x00000000>; + ircut-close-gpios = <0x000000b6 0x00000008 0x00000000>; + rockchip,camera-module-index = <0x00000001>; + rockchip,camera-module-facing = "front"; + phandle = <0x00000059>; + }; + flash-ir { + status = "okay"; + compatible = "led,rgb13h"; + label = "pwm-flash-ir"; + led-max-microamp = <0x00004e20>; + flash-max-microamp = <0x00004e20>; + flash-max-timeout-us = <0x000f4240>; + pwms = <0x000000da 0x00000000 0x000061a8 0x00000000>; + rockchip,camera-module-index = <0x00000001>; + rockchip,camera-module-facing = "front"; + phandle = <0x0000005a>; + }; + i2s0-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <0x00000100>; + simple-audio-card,name = "rockchip,i2s0-sound"; + phandle = <0x00000140>; + simple-audio-card,cpu { + sound-dai = <0x000000db>; + }; + simple-audio-card,codec { + sound-dai = <0x000000dc>; + }; + }; + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <0x00000050>; + wifi_chip_type = "USB-WiFi"; + WIFI,poweren_gpio = <0x000000d5 0x00000010 0x00000000>; + status = "okay"; + phandle = <0x00000141>; + }; + hal_dc_motor { + status = "okay"; + compatible = "rockchip,hall-dc"; + pwms = <0x000000dd 0x00000000 0x0000d903 0x00000001>; + rockchip,camera-module-index = <0x00000001>; + rockchip,camera-module-facing = "front"; + phandle = <0x0000005b>; + }; + __symbols__ { + ddr_timing = "/ddr_timing"; + cpu0 = "/cpus/cpu@f00"; + cpu1 = "/cpus/cpu@f01"; + cpu2 = "/cpus/cpu@f02"; + cpu3 = "/cpus/cpu@f03"; + CPU_SLEEP = "/cpus/idle-states/cpu-sleep"; + cpu0_opp_table = "/cpu0-opp-table"; + bus_soc = "/bus-soc"; + display_subsystem = "/display-subsystem"; + route_dsi = "/display-subsystem/route/route-dsi"; + route_rgb = "/display-subsystem/route/route-rgb"; + fiq_debugger = "/fiq-debugger"; + optee = "/firmware/optee"; + mpp_srv = "/mpp-srv"; + drm_logo = "/reserved-memory/drm-logo@00000000"; + isp_reserved = "/reserved-memory/isp"; + ramoops = "/reserved-memory/ramoops@8000000"; + rkcif_dvp = "/rkcif_dvp"; + rkcif_dvp_sditf = "/rkcif_dvp_sditf"; + rkcif_lite_mipi_lvds = "/rkcif_lite_mipi_lvds"; + rkcif_lite_sditf = "/rkcif_lite_sditf"; + rkcif_mipi_lvds = "/rkcif_mipi_lvds"; + cif_mipi_in = "/rkcif_mipi_lvds/port/endpoint"; + rkcif_mipi_lvds_sditf = "/rkcif_mipi_lvds_sditf"; + mipi_lvds_sditf = "/rkcif_mipi_lvds_sditf/port/endpoint"; + rockchip_suspend = "/rockchip-suspend"; + rockchip_system_monitor = "/rockchip-system-monitor"; + thermal_zones = "/thermal-zones"; + cpu_thermal = "/thermal-zones/cpu-thermal"; + threshold = "/thermal-zones/cpu-thermal/trips/trip-point-0"; + target = "/thermal-zones/cpu-thermal/trips/trip-point-1"; + soc_crit = "/thermal-zones/cpu-thermal/trips/soc-crit"; + npu_thermal = "/thermal-zones/npu-thermal"; + xin24m = "/oscillator"; + dummy_cpll = "/dummy_cpll"; + gmac_clkin_m0 = "/external-gmac-clockm0"; + gmac_clkini_m1 = "/external-gmac-clockm1"; + grf = "/syscon@fe000000"; + rgb = "/syscon@fe000000/rgb"; + rgb_in_vop = "/syscon@fe000000/rgb/ports/port@0/endpoint@0"; + pmugrf = "/syscon@fe020000"; + pmu_io_domains = "/syscon@fe020000/io-domains"; + qos_usb_host = "/qos@fe810000"; + qos_usb_otg = "/qos@fe810080"; + qos_npu = "/qos@fe850000"; + qos_emmc = "/qos@fe860000"; + qos_nandc = "/qos@fe860080"; + qos_sfc = "/qos@fe860200"; + qos_sdio = "/qos@fe86c000"; + qos_vepu_rd0 = "/qos@fe870000"; + qos_vepu_rd1 = "/qos@fe870080"; + qos_vepu_wr = "/qos@fe870100"; + qos_ispp_m0 = "/qos@fe880000"; + qos_ispp_m1 = "/qos@fe880080"; + qos_isp = "/qos@fe890000"; + qos_cif_lite = "/qos@fe890080"; + qos_cif = "/qos@fe890100"; + qos_iep = "/qos@fe8a0000"; + qos_rga_rd = "/qos@fe8a0080"; + qos_rga_wr = "/qos@fe8a0100"; + qos_vop = "/qos@fe8a0180"; + qos_vdpu = "/qos@fe8b0000"; + qos_jpeg = "/qos@fe8c0000"; + qos_crypto = "/qos@fe8d0000"; + gic = "/interrupt-controller@feff0000"; + pmu = "/power-management@ff3e0000"; + power = "/power-management@ff3e0000/power-controller"; + i2c0 = "/i2c@ff3f0000"; + pcf8563 = "/i2c@ff3f0000/pcf8563@51"; + i2c2 = "/i2c@ff400000"; + dmac = "/amba/dma-controller@ff4e0000"; + uart1 = "/serial@ff410000"; + pwm0 = "/pwm@ff430000"; + pwm1 = "/pwm@ff430010"; + pwm2 = "/pwm@ff430020"; + pwm3 = "/pwm@ff430030"; + pwm4 = "/pwm@ff440000"; + pwm5 = "/pwm@ff440010"; + pwm6 = "/pwm@ff440020"; + pwm7 = "/pwm@ff440030"; + spi0 = "/spi@ff450000"; + pmucru = "/clock-controller@ff480000"; + cru = "/clock-controller@ff490000"; + csi_dphy0 = "/csi-dphy@ff4b0000"; + mipi_in_ucam2 = "/csi-dphy@ff4b0000/ports/port@0/endpoint@1"; + mipi_in_ucam0 = "/csi-dphy@ff4b0000/ports/port@0/endpoint@1"; + csidphy0_out = "/csi-dphy@ff4b0000/ports/port@1/endpoint@0"; + csi_dphy1 = "/csi-dphy@ff4b8000"; + u2phy0 = "/usb2-phy@ff4c0000"; + u2phy_otg = "/usb2-phy@ff4c0000/otg-port"; + u2phy1 = "/usb2-phy@ff4c8000"; + u2phy_host = "/usb2-phy@ff4c8000/host-port"; + mipi_dphy = "/mipi-dphy@ff4d0000"; + rng = "/rng@ff500000"; + crypto = "/crypto@ff500000"; + i2c1 = "/i2c@ff510000"; + imx307 = "/i2c@ff510000/imx307@1a"; + ucam_out2 = "/i2c@ff510000/imx307@1a/port/endpoint"; + i2c3 = "/i2c@ff520000"; + i2c4 = "/i2c@ff530000"; + es8311 = "/i2c@ff530000/es8311@18"; + i2c5 = "/i2c@ff540000"; + pwm8 = "/pwm@ff550000"; + pwm9 = "/pwm@ff550010"; + pwm10 = "/pwm@ff550020"; + pwm11 = "/pwm@ff550030"; + uart0 = "/serial@ff560000"; + uart2 = "/serial@ff570000"; + uart3 = "/serial@ff580000"; + uart4 = "/serial@ff590000"; + uart5 = "/serial@ff5a0000"; + spi1 = "/spi@ff5b0000"; + otp = "/otp@ff5c0000"; + otp_cpu_code = "/otp@ff5c0000/cpu-code@2"; + otp_id = "/otp@ff5c0000/id@7"; + cpu_leakage = "/otp@ff5c0000/cpu-leakage@17"; + logic_leakage = "/otp@ff5c0000/logic-leakage@18"; + npu_leakage = "/otp@ff5c0000/npu-leakage@19"; + venc_leakage = "/otp@ff5c0000/venc-leakage@1a"; + cpu_performance = "/otp@ff5c0000/cpu-performance@1e"; + npu_performance = "/otp@ff5c0000/npu-performance@1f"; + venc_performance = "/otp@ff5c0000/venc-performance@1f"; + cpu_tsadc_trim_l = "/otp@ff5c0000/cpu-tsadc-trim-l@23"; + cpu_tsadc_trim_h = "/otp@ff5c0000/cpu-tsadc-trim-h@24"; + npu_tsadc_trim_l = "/otp@ff5c0000/npu-tsadc-trim-l@25"; + npu_tsadc_trim_h = "/otp@ff5c0000/npu-tsadc-trim-h@26"; + tsadc_trim_base = "/otp@ff5c0000/tsadc-trim-base@27"; + saradc = "/saradc@ff5e0000"; + cpu_tsadc = "/tsadc@ff5f0000"; + npu_tsadc = "/tsadc@ff5f8000"; + dcf = "/dcf@ff600000"; + can = "/can@ff610000"; + rktimer = "/rktimer@ff660000"; + wdt = "/watchdog@ff680000"; + mailbox = "/mailbox@ff6a0000"; + hw_decompress = "/decompress@ff6c0000"; + i2s0_8ch = "/i2s@ff800000"; + i2s1_2ch = "/i2s@ff810000"; + i2s2_2ch = "/i2s@ff820000"; + pdm = "/pdm@ff830000"; + audpwm = "/audpwm@ff840000"; + rkacdc_dig = "/codec-digital@ff850000"; + dfi = "/dfi@ff9c0000"; + dmc = "/dmc"; + dmc_opp_table = "/dmc-opp-table"; + dmcdbg = "/dmcdbg"; + rkcif = "/rkcif@ffae0000"; + rkcif_mmu = "/iommu@ffae0800"; + rkcif_lite = "/rkcif_lite@ffae8000"; + rkcif_lite_mmu = "/iommu@ffae8800"; + rk_rga = "/rk_rga@ffaf0000"; + vop = "/vop@ffb00000"; + vop_out = "/vop@ffb00000/port"; + vop_out_rgb = "/vop@ffb00000/port/endpoint@0"; + vop_out_dsi = "/vop@ffb00000/port/endpoint@1"; + vop_mmu = "/iommu@ffb00f00"; + mipi_csi2 = "/mipi-csi2@ffb10000"; + mipi_csi2_input = "/mipi-csi2@ffb10000/ports/port@0/endpoint@1"; + mipi_csi2_output = "/mipi-csi2@ffb10000/ports/port@1/endpoint@0"; + iep = "/iep@ffb20000"; + iep_mmu = "/iommu@ffb20800"; + dsi = "/dsi@ffb30000"; + dsi_in_vop = "/dsi@ffb30000/ports/port/endpoint"; + rkisp = "/rkisp@ffb50000"; + rkisp_mmu = "/iommu@ffb51a00"; + rkisp_vir0 = "/rkisp-vir0"; + isp0_out = "/rkisp-vir0/ports/port@1/endpoint@1"; + isp_in = "/rkisp-vir0/ports/port@0/endpoint@0"; + rkisp_vir1 = "/rkisp-vir1"; + isp1_out = "/rkisp-vir1/ports/port@1/endpoint@1"; + rkisp_vir2 = "/rkisp-vir2"; + isp2_out = "/rkisp-vir2/ports/port@1/endpoint@1"; + rkispp = "/rkispp@ffb60000"; + rkispp_mmu = "/iommu@ffb60e00"; + rkispp_vir0 = "/rkispp-vir0"; + ispp0_in = "/rkispp-vir0/port/endpoint@0"; + rkispp_vir1 = "/rkispp-vir1"; + ispp1_in = "/rkispp-vir1/port/endpoint@0"; + rkispp_vir2 = "/rkispp-vir2"; + ispp2_in = "/rkispp-vir2/port/endpoint@0"; + rkvdec = "/rkvdec@ffb80000"; + rkvdec_mmu = "/iommu@ffb80480"; + vepu = "/vepu@ffb90000"; + vdpu = "/vdpu@ffb90400"; + vpu_mmu = "/iommu@ffb90800"; + rkvenc = "/rkvenc@ffbb0000"; + rkvenc_opp_table = "/rkvenc-opp-table"; + rkvenc_mmu = "/iommu@ffbb0f00"; + gmac = "/ethernet@ffc40000"; + mdio = "/ethernet@ffc40000/mdio"; + phy = "/ethernet@ffc40000/mdio/phy@1"; + stmmac_axi_setup = "/ethernet@ffc40000/stmmac-axi-config"; + mtl_rx_setup = "/ethernet@ffc40000/rx-queues-config"; + mtl_tx_setup = "/ethernet@ffc40000/tx-queues-config"; + emmc = "/dwmmc@ffc50000"; + sdmmc = "/dwmmc@ffc60000"; + sdio = "/dwmmc@ffc70000"; + nandc = "/nandc@ffc80000"; + sfc = "/sfc@ffc90000"; + npu = "/npu@ffbc0000"; + npu_opp_table = "/npu-opp-table"; + usbdrd = "/usb0"; + usbdrd_dwc3 = "/usb0/dwc3@ffd00000"; + usb_host0_ehci = "/usb@ffe00000"; + usb_host0_ohci = "/usb@ffe10000"; + pinctrl = "/pinctrl"; + gpio0 = "/pinctrl/gpio0@ff460000"; + gpio1 = "/pinctrl/gpio1@ff620000"; + gpio2 = "/pinctrl/gpio2@ff630000"; + gpio3 = "/pinctrl/gpio3@ff640000"; + gpio4 = "/pinctrl/gpio4@ff650000"; + pcfg_pull_up = "/pinctrl/pcfg-pull-up"; + pcfg_pull_down = "/pinctrl/pcfg-pull-down"; + pcfg_pull_none = "/pinctrl/pcfg-pull-none"; + pcfg_pull_none_drv_level_0 = "/pinctrl/pcfg-pull-none-drv-level-0"; + pcfg_pull_none_drv_level_2 = "/pinctrl/pcfg-pull-none-drv-level-2"; + pcfg_pull_none_drv_level_3 = "/pinctrl/pcfg-pull-none-drv-level-3"; + pcfg_pull_none_drv_level_8 = "/pinctrl/pcfg-pull-none-drv-level-8"; + pcfg_pull_up_drv_level_0 = "/pinctrl/pcfg-pull-up-drv-level-0"; + pcfg_pull_up_drv_level_1 = "/pinctrl/pcfg-pull-up-drv-level-1"; + pcfg_pull_up_drv_level_2 = "/pinctrl/pcfg-pull-up-drv-level-2"; + pcfg_pull_up_drv_level_3 = "/pinctrl/pcfg-pull-up-drv-level-3"; + pcfg_pull_none_drv_level_0_smt = "/pinctrl/pcfg-pull-none-drv-level-0-smt"; + pcfg_output_low = "/pinctrl/pcfg-output-low"; + acodec_pins = "/pinctrl/acodec/acodec-pins"; + audpwmm0_pins = "/pinctrl/audpwm/audpwmm0-pins"; + i2c0_xfer = "/pinctrl/i2c0/i2c0-xfer"; + i2c1_xfer = "/pinctrl/i2c1/i2c1-xfer"; + i2c2_xfer = "/pinctrl/i2c2/i2c2-xfer"; + i2c3m0_xfer = "/pinctrl/i2c3/i2c3m0-xfer"; + i2c4m1_xfer = "/pinctrl/i2c4/i2c4m1-xfer"; + i2c5m0_xfer = "/pinctrl/i2c5/i2c5m0-xfer"; + i2s0m0_lrck_tx = "/pinctrl/i2s0/i2s0m0-lrck-tx"; + i2s0m0_mclk = "/pinctrl/i2s0/i2s0m0-mclk"; + i2s0m0_sclk_tx = "/pinctrl/i2s0/i2s0m0-sclk-tx"; + i2s0m0_sdi0 = "/pinctrl/i2s0/i2s0m0-sdi0"; + i2s0m0_sdo0 = "/pinctrl/i2s0/i2s0m0-sdo0"; + i2s1m0_lrck = "/pinctrl/i2s1/i2s1m0-lrck"; + i2s1m0_sclk = "/pinctrl/i2s1/i2s1m0-sclk"; + i2s1m0_sdi = "/pinctrl/i2s1/i2s1m0-sdi"; + i2s1m0_sdo = "/pinctrl/i2s1/i2s1m0-sdo"; + i2s2m0_lrck = "/pinctrl/i2s2/i2s2m0-lrck"; + i2s2m0_sclk = "/pinctrl/i2s2/i2s2m0-sclk"; + i2s2m0_sdi = "/pinctrl/i2s2/i2s2m0-sdi"; + i2s2m0_sdo = "/pinctrl/i2s2/i2s2m0-sdo"; + mipicsi_clk0 = "/pinctrl/mipicsi/mipi-csi-clk0"; + pdmm0_clk = "/pinctrl/pdm/pdmm0-clk"; + pdmm0_clk1 = "/pinctrl/pdm/pdmm0-clk1"; + pdmm0_sdi0 = "/pinctrl/pdm/pdmm0-sdi0"; + pdmm0_sdi1 = "/pinctrl/pdm/pdmm0-sdi1"; + pdmm0_sdi2 = "/pinctrl/pdm/pdmm0-sdi2"; + pdmm0_sdi3 = "/pinctrl/pdm/pdmm0-sdi3"; + pwm0m0_pins_pull_down = "/pinctrl/pwm0/pwm0m0-pins-pull-down"; + pwm1m0_pins_pull_down = "/pinctrl/pwm1/pwm1m0-pins-pull-down"; + pwm10m0_pins = "/pinctrl/pwm10/pwm10m0-pins"; + pwm11m0_pins = "/pinctrl/pwm11/pwm11m0-pins"; + pwm2m0_pins = "/pinctrl/pwm2/pwm2m0-pins"; + pwm3m0_pins_pull_down = "/pinctrl/pwm3/pwm3m0-pins-pull-down"; + pwm4m0_pins = "/pinctrl/pwm4/pwm4m0-pins"; + pwm5m0_pins = "/pinctrl/pwm5/pwm5m0-pins"; + pwm6m0_pins_pull_down = "/pinctrl/pwm6/pwm6m0-pins-pull-down"; + pwm7m0_pins = "/pinctrl/pwm7/pwm7m0-pins"; + pwm8m0_pins = "/pinctrl/pwm8/pwm8m0-pins"; + pwm9m0_pins = "/pinctrl/pwm9/pwm9m0-pins"; + rmiim0_pins = "/pinctrl/rmii/rmiim0-pins"; + gmac_clk_m0_pins = "/pinctrl/gmac_clk/gmac-clk-m0-pins"; + sdmmc0_bus4 = "/pinctrl/sdmmc0/sdmmc0-bus4"; + sdmmc0_clk = "/pinctrl/sdmmc0/sdmmc0-clk"; + sdmmc0_cmd = "/pinctrl/sdmmc0/sdmmc0-cmd"; + sdmmc0_det = "/pinctrl/sdmmc0/sdmmc0-det"; + sdmmc1_bus4 = "/pinctrl/sdmmc1/sdmmc1-bus4"; + sdmmc1_clk = "/pinctrl/sdmmc1/sdmmc1-clk"; + sdmmc1_cmd = "/pinctrl/sdmmc1/sdmmc1-cmd"; + spi0m0_clk = "/pinctrl/spi0/spi0m0-clk"; + spi0m0_cs0n = "/pinctrl/spi0/spi0m0-cs0n"; + spi0m0_cs1n = "/pinctrl/spi0/spi0m0-cs1n"; + spi0m0_miso = "/pinctrl/spi0/spi0m0-miso"; + spi0m0_mosi = "/pinctrl/spi0/spi0m0-mosi"; + spi0m0_clk_hs = "/pinctrl/spi0/spi0m0-clk_hs"; + spi0m0_miso_hs = "/pinctrl/spi0/spi0m0-miso_hs"; + spi0m0_mosi_hs = "/pinctrl/spi0/spi0m0-mosi_hs"; + spi1m0_clk = "/pinctrl/spi1/spi1m0-clk"; + spi1m0_cs0n = "/pinctrl/spi1/spi1m0-cs0n"; + spi1m0_cs1n = "/pinctrl/spi1/spi1m0-cs1n"; + spi1m0_miso = "/pinctrl/spi1/spi1m0-miso"; + spi1m0_mosi = "/pinctrl/spi1/spi1m0-mosi"; + spi1m0_clk_hs = "/pinctrl/spi1/spi1m0-clk_hs"; + spi1m0_miso_hs = "/pinctrl/spi1/spi1m0-miso_hs"; + spi1m0_mosi_hs = "/pinctrl/spi1/spi1m0-mosi_hs"; + tsadcm0_pins = "/pinctrl/tsadc/tsadcm0-pins"; + tsadc_shutorg = "/pinctrl/tsadc/tsadc-shutorg"; + uart0_xfer = "/pinctrl/uart0/uart0-xfer"; + uart0_ctsn = "/pinctrl/uart0/uart0-ctsn"; + uart0_rtsn = "/pinctrl/uart0/uart0-rtsn"; + uart1m0_xfer = "/pinctrl/uart1/uart1m0-xfer"; + uart1m0_ctsn = "/pinctrl/uart1/uart1m0-ctsn"; + uart1m0_rtsn = "/pinctrl/uart1/uart1m0-rtsn"; + uart2m1_xfer = "/pinctrl/uart2/uart2m1-xfer"; + uart3m2_xfer = "/pinctrl/uart3/uart3m2-xfer"; + uart3m2_ctsn = "/pinctrl/uart3/uart3m2-ctsn"; + uart3m2_rtsn = "/pinctrl/uart3/uart3m2-rtsn"; + uart4m0_xfer = "/pinctrl/uart4/uart4m0-xfer"; + uart4m0_ctsn = "/pinctrl/uart4/uart4m0-ctsn"; + uart4m0_rtsn = "/pinctrl/uart4/uart4m0-rtsn"; + uart5m0_xfer = "/pinctrl/uart5/uart5m0-xfer"; + uart5m0_ctsn = "/pinctrl/uart5/uart5m0-ctsn"; + uart5m0_rtsn = "/pinctrl/uart5/uart5m0-rtsn"; + spk_ctl = "/pinctrl/es8311/spk-ctl"; + sdmmc_pwr = "/pinctrl/sdmmc-pwr/sdmmc-pwr"; + vcc5v0_sys = "/vccsys"; + vcc_1v8 = "/vcc-1v8"; + vcc_dvdd = "/vcc-dvdd"; + vcc3v3_sys = "/vcc33sys"; + vcc_sd = "/vcc-sd"; + vdd_arm = "/vdd-arm"; + vdd_logic_npu_vepu = "/vdd-logic-npu-vepu"; + vdd_logic_npu_vepu_fixed = "/vdd-logic-npu-vepu-fixed"; + cam_ircut0 = "/cam_ircut"; + flash_ir = "/flash-ir"; + i2s0_sound = "/i2s0-sound"; + wireless_wlan = "/wireless-wlan"; + hal_dc_motor = "/hal_dc_motor"; + }; +}; diff --git a/br-ext-chip-rockchip/board/rv11xx/kernel/rv1126.generic.config b/br-ext-chip-rockchip/board/rv11xx/kernel/rv1126.generic.config index c720b21a..8fdb8282 100644 --- a/br-ext-chip-rockchip/board/rv11xx/kernel/rv1126.generic.config +++ b/br-ext-chip-rockchip/board/rv11xx/kernel/rv1126.generic.config @@ -1561,6 +1561,7 @@ CONFIG_I2C_MUX=y # CONFIG_I2C_DEMUX_PINCTRL is not set # CONFIG_I2C_MUX_MLXCPLD is not set CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=y # # I2C Hardware Bus support @@ -1995,7 +1996,7 @@ CONFIG_VIDEO_V4L2_SUBDEV_API=y CONFIG_VIDEO_V4L2=y # CONFIG_VIDEO_ADV_DEBUG is not set # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -CONFIG_V4L2_FWNODE=m +CONFIG_V4L2_FWNODE=y # # Media drivers @@ -2006,12 +2007,12 @@ CONFIG_V4L_PLATFORM_DRIVERS=y # CONFIG_VIDEO_MUX is not set # CONFIG_SOC_CAMERA is not set # CONFIG_VIDEO_XILINX is not set -CONFIG_VIDEO_ROCKCHIP_CIF=m +CONFIG_VIDEO_ROCKCHIP_CIF=y CONFIG_ROCKCHIP_CIF_WORKMODE_PINGPONG=y # CONFIG_ROCKCHIP_CIF_WORKMODE_ONEFRAME is not set # CONFIG_VIDEO_ROCKCHIP_ISP1 is not set -CONFIG_VIDEO_ROCKCHIP_ISP=m -CONFIG_VIDEO_ROCKCHIP_ISPP=m +CONFIG_VIDEO_ROCKCHIP_ISP=y +CONFIG_VIDEO_ROCKCHIP_ISPP=y # CONFIG_VIDEO_ROCKCHIP_ISPP_FEC is not set # CONFIG_V4L_MEM2MEM_DRIVERS is not set # CONFIG_V4L_TEST_DRIVERS is not set @@ -2020,12 +2021,12 @@ CONFIG_VIDEO_ROCKCHIP_ISPP=m # Supported MMC/SDIO adapters # # CONFIG_CYPRESS_FIRMWARE is not set -CONFIG_VIDEOBUF2_CORE=m -CONFIG_VIDEOBUF2_V4L2=m -CONFIG_VIDEOBUF2_MEMOPS=m -CONFIG_VIDEOBUF2_DMA_CONTIG=m -CONFIG_VIDEOBUF2_VMALLOC=m -CONFIG_VIDEOBUF2_DMA_SG=m +CONFIG_VIDEOBUF2_CORE=y +CONFIG_VIDEOBUF2_V4L2=y +CONFIG_VIDEOBUF2_MEMOPS=y +CONFIG_VIDEOBUF2_DMA_CONTIG=y +CONFIG_VIDEOBUF2_VMALLOC=y +CONFIG_VIDEOBUF2_DMA_SG=y # # Media ancillary drivers (tuners, sensors, i2c, spi, frontends) @@ -2754,7 +2755,9 @@ CONFIG_USB_STORAGE=y # CONFIG_USBIP_CORE is not set # CONFIG_USB_MUSB_HDRC is not set CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_HOST=y +# CONFIG_USB_DWC3_HOST is not set +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_DWC3_DUAL_ROLE=y # # Platform Glue Driver Support @@ -3832,7 +3835,8 @@ CONFIG_ARM_PMU=y # # Android # -# CONFIG_ANDROID is not set +CONFIG_ANDROID=y +# CONFIG_ANDROID_BINDER_IPC is not set # CONFIG_DAX is not set CONFIG_NVMEM=y # CONFIG_ROCKCHIP_EFUSE is not set @@ -3845,12 +3849,12 @@ CONFIG_ROCKCHIP_OTP=y # CONFIG_INTEL_TH is not set # CONFIG_FPGA is not set # CONFIG_FSI is not set -CONFIG_TEE=m +CONFIG_TEE=y # # TEE drivers # -CONFIG_OPTEE=m +CONFIG_OPTEE=y CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1 CONFIG_PM_OPP=y # CONFIG_SIOX is not set @@ -4008,7 +4012,7 @@ CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y # CONFIG_NFS_V4 is not set # CONFIG_NFS_SWAP is not set -# CONFIG_ROOT_NFS is not set +CONFIG_ROOT_NFS=y CONFIG_NFSD=y # CONFIG_NFSD_V3 is not set # CONFIG_NFSD_V4 is not set @@ -4080,11 +4084,7 @@ CONFIG_NLS_UTF8=y # # Security options # -CONFIG_KEYS=y -# CONFIG_PERSISTENT_KEYRINGS is not set -# CONFIG_BIG_KEYS is not set -# CONFIG_ENCRYPTED_KEYS is not set -# CONFIG_KEY_DH_OPERATIONS is not set +# CONFIG_KEYS is not set # CONFIG_SECURITY_DMESG_RESTRICT is not set # CONFIG_SECURITY_PERF_EVENTS_RESTRICT is not set # CONFIG_SECURITY is not set diff --git a/br-ext-chip-rockchip/configs/unknown_unknown_rv1109_openipc_defconfig b/br-ext-chip-rockchip/configs/unknown_unknown_rv1109_openipc_defconfig index 36b6142e..c373347e 100644 --- a/br-ext-chip-rockchip/configs/unknown_unknown_rv1109_openipc_defconfig +++ b/br-ext-chip-rockchip/configs/unknown_unknown_rv1109_openipc_defconfig @@ -1,6 +1,7 @@ # Architecture BR2_arm=y BR2_cortex_a7=y +BR2_ARM_EABIHF=y BR2_ARM_FPU_NEON_VFPV4=y # BR2_ARM_INSTRUCTIONS_THUMB2=y BR2_KERNEL_HEADERS_VERSION=y @@ -33,7 +34,7 @@ BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.19.111" BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_ROCKCHIP_PATH)/board/rv11xx/kernel/rv1126.generic.config" BR2_LINUX_KERNEL_IMAGE_TARGET_CUSTOM=y -BR2_LINUX_KERNEL_IMAGE_TARGET_NAME="rv1126-evb-ddr3-v13.img" +BR2_LINUX_KERNEL_IMAGE_TARGET_NAME="rv1109-38x38-v11-spi-nand-imx307.img" BR2_LINUX_KERNEL_IMAGE_NAME="zboot.img" BR2_LINUX_KERNEL_XZ=y BR2_LINUX_KERNEL_EXT_ROCKCHIP_PATCHER=y diff --git a/br-ext-chip-rockchip/configs/unknown_unknown_rv1126_openipc_defconfig b/br-ext-chip-rockchip/configs/unknown_unknown_rv1126_openipc_defconfig index ba6a8193..336fe4f4 100644 --- a/br-ext-chip-rockchip/configs/unknown_unknown_rv1126_openipc_defconfig +++ b/br-ext-chip-rockchip/configs/unknown_unknown_rv1126_openipc_defconfig @@ -1,6 +1,7 @@ # Architecture BR2_arm=y BR2_cortex_a7=y +BR2_ARM_EABIHF=y BR2_ARM_FPU_NEON_VFPV4=y # BR2_ARM_INSTRUCTIONS_THUMB2=y BR2_KERNEL_HEADERS_VERSION=y @@ -33,7 +34,7 @@ BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.19.111" BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_ROCKCHIP_PATH)/board/rv11xx/kernel/rv1126.generic.config" BR2_LINUX_KERNEL_IMAGE_TARGET_CUSTOM=y -BR2_LINUX_KERNEL_IMAGE_TARGET_NAME="rv1126-evb-ddr3-v13.img" +BR2_LINUX_KERNEL_IMAGE_TARGET_NAME="rv1126-ai-cam-ddr3-v1.img" BR2_LINUX_KERNEL_IMAGE_NAME="zboot.img" BR2_LINUX_KERNEL_XZ=y BR2_LINUX_KERNEL_EXT_ROCKCHIP_PATCHER=y