From 82f5b15772ecc48b813f7704bf6d2e836e97e63e Mon Sep 17 00:00:00 2001
From: "Igor Zalatov (from Citadel PC)" <flyrouter@gmail.com>
Date: Tue, 28 Jun 2022 19:41:53 +0300
Subject: [PATCH] [MSC313E] Add infinity3-QFN64M-openipc.dts

---
 .../arm/boot/dts/infinity3-QFN64M-openipc.dts | 64 +++++++++++++++++++
 1 file changed, 64 insertions(+)
 create mode 100644 br-ext-chip-sigmastar/board/infinity3/kernel/overlay/arch/arm/boot/dts/infinity3-QFN64M-openipc.dts

diff --git a/br-ext-chip-sigmastar/board/infinity3/kernel/overlay/arch/arm/boot/dts/infinity3-QFN64M-openipc.dts b/br-ext-chip-sigmastar/board/infinity3/kernel/overlay/arch/arm/boot/dts/infinity3-QFN64M-openipc.dts
new file mode 100644
index 00000000..c4b51a4d
--- /dev/null
+++ b/br-ext-chip-sigmastar/board/infinity3/kernel/overlay/arch/arm/boot/dts/infinity3-QFN64M-openipc.dts
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2014 MundoReader S.L.
+ * Author: Matthias Brugger <matthias.bgg@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "infinity3.dtsi"
+
+/ {
+    model = "INFINITY3 MSC000A-S03A-64M";
+    compatible = "mstar,infinity3";
+
+
+    chosen {
+        bootargs = "console=ttyS0,115200 panic=20 root=/dev/mtdblock3 rootfstype=squashfs init=/init";
+        linux,initrd-start = <0x20FE0000>;
+        linux,initrd-end =   <0x21000000>;
+    };
+
+    memory {
+        reg = <0x20000000 0x04000000>;
+    };
+
+/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/
+    reserved-memory {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+
+/*
+        miu_bist_mem: miu_bist_mem@23F00000 {
+            reg = <0x23F00000 0x00100000>;
+            no-map ;
+            status = "okay";
+        };
+*/
+
+        cma0 {
+            compatible = "shared-dma-pool";
+            reusable;
+            size = <0x05000000>;
+            alignment = <0x1000>;
+            linux,cma-default;
+        };
+    };
+
+    soc {
+        isp: isp {
+            //clk-pad = <PAD_SPI0_CK>; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads
+            isp-flag = <0x3>; //enable DNR and ROT
+            isp-res = <0x5>; //max image size 5M
+        };
+    };
+};